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From 5340673ba16e3c8c9c1406d5ab84aca82e83e2ce Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 23 May 2013 18:46:25 +0200
Subject: [PATCH 10/33] MIPS: ralink: add spi clock definition to mt7620a
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/mt7620.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 62356a0..96422e5 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -183,6 +183,7 @@ void __init ralink_clk_init(void)
ralink_clk_add("cpu", cpu_rate);
ralink_clk_add("10000100.timer", 40000000);
ralink_clk_add("10000500.uart", 40000000);
+ ralink_clk_add("10000b00.spi", 40000000);
ralink_clk_add("10000c00.uartlite", 40000000);
}
--
1.7.10.4
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