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-rw-r--r--target/linux/ixp4xx/config-2.6.304
-rw-r--r--target/linux/ixp4xx/patches-2.6.30/050-disable_dmabounce.patch164
-rw-r--r--target/linux/ixp4xx/patches-2.6.30/400-dmabounce.patch27
3 files changed, 167 insertions, 28 deletions
diff --git a/target/linux/ixp4xx/config-2.6.30 b/target/linux/ixp4xx/config-2.6.30
index 3a2747853e..f5f7a895a4 100644
--- a/target/linux/ixp4xx/config-2.6.30
+++ b/target/linux/ixp4xx/config-2.6.30
@@ -9,6 +9,7 @@ CONFIG_ALIGNMENT_TRAP=y
# CONFIG_ARCH_EP93XX is not set
CONFIG_ARCH_FLATMEM_HAS_HOLES=y
# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -84,7 +85,6 @@ CONFIG_DEVPORT=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_DM9000 is not set
CONFIG_DMABOUNCE=y
-CONFIG_DMABOUNCE_DEBUG=y
CONFIG_DNOTIFY=y
CONFIG_EEPROM_AT24=y
# CONFIG_EEPROM_LEGACY is not set
@@ -137,9 +137,11 @@ CONFIG_IP_PIMSM_V2=y
# CONFIG_IWMMXT is not set
CONFIG_IXP4XX_ETH=y
# CONFIG_IXP4XX_INDIRECT_PCI is not set
+CONFIG_IXP4XX_LEGACY_DMABOUNCE=y
CONFIG_IXP4XX_NPE=y
CONFIG_IXP4XX_QMGR=y
CONFIG_IXP4XX_WATCHDOG=y
+# CONFIG_IXP4XX_ZONE_DMA is not set
CONFIG_LEDS_FSG=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LATCH=y
diff --git a/target/linux/ixp4xx/patches-2.6.30/050-disable_dmabounce.patch b/target/linux/ixp4xx/patches-2.6.30/050-disable_dmabounce.patch
new file mode 100644
index 0000000000..a4b1e816d4
--- /dev/null
+++ b/target/linux/ixp4xx/patches-2.6.30/050-disable_dmabounce.patch
@@ -0,0 +1,164 @@
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -374,7 +374,6 @@ config ARCH_IXP4XX
+ select GENERIC_GPIO
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+- select DMABOUNCE if PCI
+ help
+ Support for Intel's IXP4XX (XScale) family of processors.
+
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -193,6 +193,45 @@ config IXP4XX_INDIRECT_PCI
+ need to use the indirect method instead. If you don't know
+ what you need, leave this option unselected.
+
++config IXP4XX_LEGACY_DMABOUNCE
++ bool "legacy PCI DMA bounce support"
++ depends on PCI
++ default n
++ select DMABOUNCE
++ help
++ The IXP4xx is limited to a 64MB window for PCI DMA, which
++ requires that PCI accesses above 64MB are bounced via buffers
++ below 64MB. Furthermore the IXP4xx has an erratum where PCI
++ read prefetches just below the 64MB limit can trigger lockups.
++
++ The kernel has traditionally handled these two issue by using
++ ARM specific DMA bounce support code for all accesses >= 64MB.
++ That code causes problems of its own, so it is desirable to
++ disable it. As the kernel now has a workaround for the PCI read
++ prefetch erratum, it no longer requires the ARM bounce code.
++
++ Enabling this option makes IXP4xx continue to use the problematic
++ ARM DMA bounce code. Disabling this option makes IXP4xx use the
++ kernel's generic bounce code.
++
++ Say 'N'.
++
++config IXP4XX_ZONE_DMA
++ bool "Support > 64MB RAM"
++ depends on !IXP4XX_LEGACY_DMABOUNCE
++ default y
++ select ZONE_DMA
++ help
++ The IXP4xx is limited to a 64MB window for PCI DMA, which
++ requires that PCI accesses above 64MB are bounced via buffers
++ below 64MB.
++
++ Disabling this option allows you to omit the support code for
++ DMA-able memory allocations and DMA bouncing, but the kernel
++ will then not work properly if more than 64MB of RAM is present.
++
++ Say 'Y' unless your platform is limited to <= 64MB of RAM.
++
+ config IXP4XX_QMGR
+ tristate "IXP4xx Queue Manager support"
+ help
+--- a/arch/arm/mach-ixp4xx/common-pci.c
++++ b/arch/arm/mach-ixp4xx/common-pci.c
+@@ -321,27 +321,38 @@ static int abort_handler(unsigned long a
+ */
+ static int ixp4xx_pci_platform_notify(struct device *dev)
+ {
+- if(dev->bus == &pci_bus_type) {
+- *dev->dma_mask = SZ_64M - 1;
++ if (dev->bus == &pci_bus_type) {
++ *dev->dma_mask = SZ_64M - 1;
+ dev->coherent_dma_mask = SZ_64M - 1;
++#ifdef CONFIG_DMABOUNCE
+ dmabounce_register_dev(dev, 2048, 4096);
++#endif
+ }
+ return 0;
+ }
+
+ static int ixp4xx_pci_platform_notify_remove(struct device *dev)
+ {
+- if(dev->bus == &pci_bus_type) {
++#ifdef CONFIG_DMABOUNCE
++ if (dev->bus == &pci_bus_type)
+ dmabounce_unregister_dev(dev);
+- }
++#endif
+ return 0;
+ }
+
++#ifdef CONFIG_DMABOUNCE
+ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
+ {
++ /* Note that this returns true for the last page below 64M due to
++ * IXP4xx erratum 15 (SCR 1289), which states that PCI prefetches
++ * can cross the boundary between valid memory and a reserved region
++ * causing AHB bus errors and a lock-up.
++ */
+ return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
+ }
++#endif
+
++#ifdef CONFIG_ZONE_DMA
+ /*
+ * Only first 64MB of memory can be accessed via PCI.
+ * We use GFP_DMA to allocate safe buffers to do map/unmap.
+@@ -364,6 +375,7 @@ void __init ixp4xx_adjust_zones(int node
+ zhole_size[1] = zhole_size[0];
+ zhole_size[0] = 0;
+ }
++#endif
+
+ void __init ixp4xx_pci_preinit(void)
+ {
+@@ -517,19 +529,35 @@ struct pci_bus * __devinit ixp4xx_scan_b
+ int
+ pci_set_dma_mask(struct pci_dev *dev, u64 mask)
+ {
+- if (mask >= SZ_64M - 1 )
++#ifdef CONFIG_DMABOUNCE
++ if (mask >= SZ_64M - 1)
+ return 0;
+
+ return -EIO;
++#else
++ /* Only honour masks < SZ_64M. Silently ignore masks >= SZ_64M
++ as generic drivers do not know about IXP4xx PCI DMA quirks. */
++ if (mask < SZ_64M)
++ dev->dma_mask = mask;
++ return 0;
++#endif
+ }
+
+ int
+ pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
+ {
+- if (mask >= SZ_64M - 1 )
++#ifdef CONFIG_DMABOUNCE
++ if (mask >= SZ_64M - 1)
+ return 0;
+
+ return -EIO;
++#else
++ /* Only honour masks < SZ_64M. Silently ignore masks >= SZ_64M
++ as generic drivers do not know about IXP4xx PCI DMA quirks. */
++ if (mask < SZ_64M)
++ dev->dev.coherent_dma_mask = mask;
++ return 0;
++#endif
+ }
+
+ EXPORT_SYMBOL(ixp4xx_pci_read);
+--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
++++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
+@@ -16,10 +16,12 @@
+
+ #if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
+
++#ifdef CONFIG_ZONE_DMA
+ void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
+
+ #define arch_adjust_zones(node, size, holes) \
+ ixp4xx_adjust_zones(node, size, holes)
++#endif
+
+ #define ISA_DMA_THRESHOLD (SZ_64M - 1)
+ #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
diff --git a/target/linux/ixp4xx/patches-2.6.30/400-dmabounce.patch b/target/linux/ixp4xx/patches-2.6.30/400-dmabounce.patch
deleted file mode 100644
index af68a55b12..0000000000
--- a/target/linux/ixp4xx/patches-2.6.30/400-dmabounce.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/arch/arm/common/dmabounce.c
-+++ b/arch/arm/common/dmabounce.c
-@@ -117,6 +117,10 @@ alloc_safe_buffer(struct dmabounce_devic
- } else if (size <= device_info->large.size) {
- pool = &device_info->large;
- } else {
-+#ifdef CONFIG_DMABOUNCE_DEBUG
-+ printk(KERN_INFO "A dma bounce buffer outside the pool size was requested. Requested size was 0x%08X\nThe calling code was :\n", size);
-+ dump_stack();
-+#endif
- pool = NULL;
- }
-
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -246,6 +246,11 @@ config MACH_MI424WR
-
- comment "IXP4xx Options"
-
-+config DMABOUNCE_DEBUG
-+ bool "Enable DMABounce debuging"
-+ default n
-+ depends on DMABOUNCE
-+
- config IXP4XX_INDIRECT_PCI
- bool "Use indirect PCI memory access"
- depends on PCI
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 04:48:18 +0000