diff options
Diffstat (limited to 'target/linux/brcm63xx/files-2.6.30/include/asm-mips')
24 files changed, 0 insertions, 2206 deletions
diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_board.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_board.h deleted file mode 100644 index fa3e7e617b..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_board.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef BCM63XX_BOARD_H_ -#define BCM63XX_BOARD_H_ - -const char *board_get_name(void); - -void board_prom_init(void); - -void board_setup(void); - -int board_register_devices(void); - -#endif /* ! BCM63XX_BOARD_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h deleted file mode 100644 index 8fcf8df441..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef BCM63XX_CLK_H_ -#define BCM63XX_CLK_H_ - -struct clk { - void (*set)(struct clk *, int); - unsigned int rate; - unsigned int usage; - int id; -}; - -#endif /* ! BCM63XX_CLK_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h deleted file mode 100644 index e27bd5b3d0..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h +++ /dev/null @@ -1,673 +0,0 @@ -#ifndef BCM63XX_CPU_H_ -#define BCM63XX_CPU_H_ - -#include <linux/types.h> -#include <linux/init.h> - -#include <bcm63xx_regs.h> - -/* - * Macro to fetch bcm63xx cpu id and revision, should be optimized at - * compile time if only one CPU support is enabled (idea stolen from - * arm mach-types) - */ -#define BCM6338_CPU_ID 0x6338 -#define BCM6345_CPU_ID 0x6345 -#define BCM6348_CPU_ID 0x6348 -#define BCM6358_CPU_ID 0x6358 - -void __init bcm63xx_cpu_init(void); -u16 __bcm63xx_get_cpu_id(void); -u16 bcm63xx_get_cpu_rev(void); -unsigned int bcm63xx_get_cpu_freq(void); - -#ifdef CONFIG_BCM63XX_CPU_6338 -# ifdef bcm63xx_get_cpu_id -# undef bcm63xx_get_cpu_id -# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() -# define BCMCPU_RUNTIME_DETECT -# else -# define bcm63xx_get_cpu_id() BCM6338_CPU_ID -# endif -# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) -#else -# define BCMCPU_IS_6338() (0) -#endif - -#ifdef CONFIG_BCM63XX_CPU_6345 -# ifdef bcm63xx_get_cpu_id -# undef bcm63xx_get_cpu_id -# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() -# define BCMCPU_RUNTIME_DETECT -# else -# define bcm63xx_get_cpu_id() BCM6345_CPU_ID -# endif -# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) -#else -# define BCMCPU_IS_6345() (0) -#endif - -#ifdef CONFIG_BCM63XX_CPU_6348 -# ifdef bcm63xx_get_cpu_id -# undef bcm63xx_get_cpu_id -# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() -# define BCMCPU_RUNTIME_DETECT -# else -# define bcm63xx_get_cpu_id() BCM6348_CPU_ID -# endif -# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) -#else -# define BCMCPU_IS_6348() (0) -#endif - -#ifdef CONFIG_BCM63XX_CPU_6358 -# ifdef bcm63xx_get_cpu_id -# undef bcm63xx_get_cpu_id -# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() -# define BCMCPU_RUNTIME_DETECT -# else -# define bcm63xx_get_cpu_id() BCM6358_CPU_ID -# endif -# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) -#else -# define BCMCPU_IS_6358() (0) -#endif - -#ifndef bcm63xx_get_cpu_id -#error "No CPU support configured" -#endif - -/* - * While registers sets are (mostly) the same across 63xx CPU, base - * address of these sets do change. - */ -enum bcm63xx_regs_set { - RSET_DSL_LMEM = 0, - RSET_PERF, - RSET_TIMER, - RSET_WDT, - RSET_UART0, - RSET_GPIO, - RSET_SPI, - RSET_UDC0, - RSET_OHCI0, - RSET_OHCI_PRIV, - RSET_USBH_PRIV, - RSET_MPI, - RSET_PCMCIA, - RSET_DSL, - RSET_ENET0, - RSET_ENET1, - RSET_ENETDMA, - RSET_EHCI0, - RSET_SDRAM, - RSET_MEMC, - RSET_DDR, -}; - -#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) -#define RSET_DSL_SIZE 4096 -#define RSET_WDT_SIZE 12 -#define RSET_ENET_SIZE 2048 -#define RSET_ENETDMA_SIZE 2048 -#define RSET_UART_SIZE 24 -#define RSET_SPI_SIZE 256 -#define RSET_UDC_SIZE 256 -#define RSET_OHCI_SIZE 256 -#define RSET_EHCI_SIZE 256 -#define RSET_PCMCIA_SIZE 12 - -/* - * 6338 register sets base address - */ - -#define BCM_6338_DSL_LMEM_BASE (0xfff00000) -#define BCM_6338_PERF_BASE (0xfffe0000) -#define BCM_6338_BB_BASE (0xfffe0100) -#define BCM_6338_TIMER_BASE (0xfffe0200) -#define BCM_6338_WDT_BASE (0xfffe021c) -#define BCM_6338_UART0_BASE (0xfffe0300) -#define BCM_6338_GPIO_BASE (0xfffe0400) -#define BCM_6338_SPI_BASE (0xfffe0c00) -#define BCM_6338_UDC0_BASE (0xfffe3000) -#define BCM_6338_USBDMA_BASE (0xfffe2400) -#define BCM_6338_OHCI0_BASE (0xdeadbeef) -#define BCM_6338_OHCI_PRIV_BASE (0xdeadbeef) -#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) -#define BCM_6338_MPI_BASE (0xfffe3160) -#define BCM_6338_PCMCIA_BASE (0xdeadbeef) -#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) -#define BCM_6338_DSL_BASE (0xfffe1000) -#define BCM_6338_SAR_BASE (0xfffe2000) -#define BCM_6338_UBUS_BASE (0xdeadbeef) -#define BCM_6338_ENET0_BASE (0xfffe2800) -#define BCM_6338_ENET1_BASE (0xdeadbeef) -#define BCM_6338_ENETDMA_BASE (0xfffe2400) -#define BCM_6338_EHCI0_BASE (0xdeadbeef) -#define BCM_6338_SDRAM_BASE (0xfffe3100) -#define BCM_6338_MEMC_BASE (0xdeadbeef) -#define BCM_6338_DDR_BASE (0xdeadbeef) - -/* - * 6345 register sets base address - */ -#define BCM_6345_DSL_LMEM_BASE (0xfff00000) -#define BCM_6345_PERF_BASE (0xfffe0000) -#define BCM_6345_BB_BASE (0xfffe0100) -#define BCM_6345_TIMER_BASE (0xfffe0200) -#define BCM_6345_WDT_BASE (0xfffe021c) -#define BCM_6345_UART0_BASE (0xfffe0300) -#define BCM_6345_GPIO_BASE (0xfffe0400) -#define BCM_6345_SPI_BASE (0xdeadbeef) -#define BCM_6345_UDC0_BASE (0xfffe2100) -#define BCM_6345_USBDMA_BASE (0xfffe2b00) -#define BCM_6345_ENET0_BASE (0xfffe1800) -#define BCM_6345_ENETDMA_BASE (0xfffe2800) -#define BCM_6345_PCMCIA_BASE (0xfffe2028) -#define BCM_6345_MPI_BASE (0xdeadbeef) -#define BCM_6345_OHCI0_BASE (0xdeadbeef) -#define BCM_6345_OHCI_PRIV_BASE (0xdeadbeef) -#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) -#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) -#define BCM_6345_DSL_BASE (0xdeadbeef) -#define BCM_6345_SAR_BASE (0xdeadbeef) -#define BCM_6345_UBUS_BASE (0xdeadbeef) -#define BCM_6345_ENET1_BASE (0xdeadbeef) -#define BCM_6345_EHCI0_BASE (0xdeadbeef) -#define BCM_6345_SDRAM_BASE (0xfffe2300) -#define BCM_6345_MEMC_BASE (0xdeadbeef) -#define BCM_6345_DDR_BASE (0xdeadbeef) - -/* - * 6348 register sets base address - */ -#define BCM_6348_DSL_LMEM_BASE (0xfff00000) -#define BCM_6348_PERF_BASE (0xfffe0000) -#define BCM_6348_BB_BASE (0xfffe0100) -#define BCM_6348_TIMER_BASE (0xfffe0200) -#define BCM_6348_WDT_BASE (0xfffe021c) -#define BCM_6348_UART0_BASE (0xfffe0300) -#define BCM_6348_GPIO_BASE (0xfffe0400) -#define BCM_6348_SPI_BASE (0xfffe0c00) -#define BCM_6348_UDC0_BASE (0xfffe1000) -#define BCM_6348_USBDMA_BASE (0xfffe1400) -#define BCM_6348_OHCI0_BASE (0xfffe1b00) -#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) -#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) -#define BCM_6348_MPI_BASE (0xfffe2000) -#define BCM_6348_PCMCIA_BASE (0xfffe2054) -#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) -#define BCM_6348_DSL_BASE (0xfffe3000) -#define BCM_6348_SAR_BASE (0xfffe4000) -#define BCM_6348_UBUS_BASE (0xfffe5000) -#define BCM_6348_ENET0_BASE (0xfffe6000) -#define BCM_6348_ENET1_BASE (0xfffe6800) -#define BCM_6348_ENETDMA_BASE (0xfffe7000) -#define BCM_6348_EHCI0_BASE (0xdeadbeef) -#define BCM_6348_SDRAM_BASE (0xfffe2300) -#define BCM_6348_MEMC_BASE (0xdeadbeef) -#define BCM_6348_DDR_BASE (0xdeadbeef) - -/* - * 6358 register sets base address - */ -#define BCM_6358_DSL_LMEM_BASE (0xfff00000) -#define BCM_6358_PERF_BASE (0xfffe0000) -#define BCM_6358_TIMER_BASE (0xfffe0040) -#define BCM_6358_WDT_BASE (0xfffe005c) -#define BCM_6358_GPIO_BASE (0xfffe0080) -#define BCM_6358_UART0_BASE (0xfffe0100) -#define BCM_6358_UDC0_BASE (0xfffe0400) -#define BCM_6358_SPI_BASE (0xfffe0800) -#define BCM_6358_MPI_BASE (0xfffe1000) -#define BCM_6358_PCMCIA_BASE (0xfffe1054) -#define BCM_6358_OHCI0_BASE (0xfffe1400) -#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) -#define BCM_6358_USBH_PRIV_BASE (0xfffe1500) -#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) -#define BCM_6358_DSL_BASE (0xfffe3000) -#define BCM_6358_ENET0_BASE (0xfffe4000) -#define BCM_6358_ENET1_BASE (0xfffe4800) -#define BCM_6358_ENETDMA_BASE (0xfffe5000) -#define BCM_6358_EHCI0_BASE (0xfffe1300) -#define BCM_6358_SDRAM_BASE (0xdeadbeef) -#define BCM_6358_MEMC_BASE (0xfffe1200) -#define BCM_6358_DDR_BASE (0xfffe12a0) - - -extern const unsigned long *bcm63xx_regs_base; - -static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) -{ -#ifdef BCMCPU_RUNTIME_DETECT - return bcm63xx_regs_base[set]; -#else -#ifdef CONFIG_BCM63XX_CPU_6338 - switch (set) { - case RSET_DSL_LMEM: - return BCM_6338_DSL_LMEM_BASE; - case RSET_PERF: - return BCM_6338_PERF_BASE; - case RSET_TIMER: - return BCM_6338_TIMER_BASE; - case RSET_WDT: - return BCM_6338_WDT_BASE; - case RSET_UART0: - return BCM_6338_UART0_BASE; - case RSET_GPIO: - return BCM_6338_GPIO_BASE; - case RSET_SPI: - return BCM_6338_SPI_BASE; - case RSET_UDC0: - return BCM_6338_UDC0_BASE; - case RSET_OHCI0: - return BCM_6338_OHCI0_BASE; - case RSET_OHCI_PRIV: - return BCM_6338_OHCI_PRIV_BASE; - case RSET_USBH_PRIV: - return BCM_6338_USBH_PRIV_BASE; - case RSET_MPI: - return BCM_6338_MPI_BASE; - case RSET_PCMCIA: - return BCM_6338_PCMCIA_BASE; - case RSET_DSL: - return BCM_6338_DSL_BASE; - case RSET_ENET0: - return BCM_6338_ENET0_BASE; - case RSET_ENET1: - return BCM_6338_ENET1_BASE; - case RSET_ENETDMA: - return BCM_6338_ENETDMA_BASE; - case RSET_EHCI0: - return BCM_6338_EHCI0_BASE; - case RSET_SDRAM: - return BCM_6338_SDRAM_BASE; - case RSET_MEMC: - return BCM_6338_MEMC_BASE; - case RSET_DDR: - return BCM_6338_DDR_BASE; - } -#endif -#ifdef CONFIG_BCM63XX_CPU_6345 - switch (set) { - case RSET_DSL_LMEM: - return BCM_6345_DSL_LMEM_BASE; - case RSET_PERF: - return BCM_6345_PERF_BASE; - case RSET_TIMER: - return BCM_6345_TIMER_BASE; - case RSET_WDT: - return BCM_6345_WDT_BASE; - case RSET_UART0: - return BCM_6345_UART0_BASE; - case RSET_GPIO: - return BCM_6345_GPIO_BASE; - case RSET_SPI: - return BCM_6345_SPI_BASE; - case RSET_UDC0: - return BCM_6345_UDC0_BASE; - case RSET_OHCI0: - return BCM_6345_OHCI0_BASE; - case RSET_OHCI_PRIV: - return BCM_6345_OHCI_PRIV_BASE; - case RSET_USBH_PRIV: - return BCM_6345_USBH_PRIV_BASE; - case RSET_MPI: - return BCM_6345_MPI_BASE; - case RSET_PCMCIA: - return BCM_6345_PCMCIA_BASE; - case RSET_DSL: - return BCM_6345_DSL_BASE; - case RSET_ENET0: - return BCM_6345_ENET0_BASE; - case RSET_ENET1: - return BCM_6345_ENET1_BASE; - case RSET_ENETDMA: - return BCM_6345_ENETDMA_BASE; - case RSET_EHCI0: - return BCM_6345_EHCI0_BASE; - case RSET_SDRAM: - return BCM_6345_SDRAM_BASE; - case RSET_MEMC: - return BCM_6345_MEMC_BASE; - case RSET_DDR: - return BCM_6345_DDR_BASE; - } -#endif -#ifdef CONFIG_BCM63XX_CPU_6348 - switch (set) { - case RSET_DSL_LMEM: - return BCM_6348_DSL_LMEM_BASE; - case RSET_PERF: - return BCM_6348_PERF_BASE; - case RSET_TIMER: - return BCM_6348_TIMER_BASE; - case RSET_WDT: - return BCM_6348_WDT_BASE; - case RSET_UART0: - return BCM_6348_UART0_BASE; - case RSET_GPIO: - return BCM_6348_GPIO_BASE; - case RSET_SPI: - return BCM_6348_SPI_BASE; - case RSET_UDC0: - return BCM_6348_UDC0_BASE; - case RSET_OHCI0: - return BCM_6348_OHCI0_BASE; - case RSET_OHCI_PRIV: - return BCM_6348_OHCI_PRIV_BASE; - case RSET_USBH_PRIV: - return BCM_6348_USBH_PRIV_BASE; - case RSET_MPI: - return BCM_6348_MPI_BASE; - case RSET_PCMCIA: - return BCM_6348_PCMCIA_BASE; - case RSET_DSL: - return BCM_6348_DSL_BASE; - case RSET_ENET0: - return BCM_6348_ENET0_BASE; - case RSET_ENET1: - return BCM_6348_ENET1_BASE; - case RSET_ENETDMA: - return BCM_6348_ENETDMA_BASE; - case RSET_EHCI0: - return BCM_6348_EHCI0_BASE; - case RSET_SDRAM: - return BCM_6348_SDRAM_BASE; - case RSET_MEMC: - return BCM_6348_MEMC_BASE; - case RSET_DDR: - return BCM_6348_DDR_BASE; - } -#endif -#ifdef CONFIG_BCM63XX_CPU_6358 - switch (set) { - case RSET_DSL_LMEM: - return BCM_6358_DSL_LMEM_BASE; - case RSET_PERF: - return BCM_6358_PERF_BASE; - case RSET_TIMER: - return BCM_6358_TIMER_BASE; - case RSET_WDT: - return BCM_6358_WDT_BASE; - case RSET_UART0: - return BCM_6358_UART0_BASE; - case RSET_GPIO: - return BCM_6358_GPIO_BASE; - case RSET_SPI: - return BCM_6358_SPI_BASE; - case RSET_UDC0: - return BCM_6358_UDC0_BASE; - case RSET_OHCI0: - return BCM_6358_OHCI0_BASE; - case RSET_OHCI_PRIV: - return BCM_6358_OHCI_PRIV_BASE; - case RSET_USBH_PRIV: - return BCM_6358_USBH_PRIV_BASE; - case RSET_MPI: - return BCM_6358_MPI_BASE; - case RSET_PCMCIA: - return BCM_6358_PCMCIA_BASE; - case RSET_ENET0: - return BCM_6358_ENET0_BASE; - case RSET_ENET1: - return BCM_6358_ENET1_BASE; - case RSET_ENETDMA: - return BCM_6358_ENETDMA_BASE; - case RSET_DSL: - return BCM_6358_DSL_BASE; - case RSET_EHCI0: - return BCM_6358_EHCI0_BASE; - case RSET_SDRAM: - return BCM_6358_SDRAM_BASE; - case RSET_MEMC: - return BCM_6358_MEMC_BASE; - case RSET_DDR: - return BCM_6358_DDR_BASE; - } -#endif -#endif - /* unreached */ - return 0; -} - -/* - * SPI register layout is not compatible - * accross CPU versions but it is software - * compatible - */ - -enum bcm63xx_regs_spi { - SPI_CMD, - SPI_INT_STATUS, - SPI_INT_MASK_ST, - SPI_INT_MASK, - SPI_ST, - SPI_CLK_CFG, - SPI_FILL_BYTE, - SPI_MSG_TAIL, - SPI_RX_TAIL, - SPI_MSG_CTL, - SPI_MSG_DATA, - SPI_RX_DATA, -}; - -extern const unsigned long *bcm63xx_regs_spi; - -static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) -{ -#ifdef BCMCPU_RUNTIME_DETECT - return bcm63xx_regs_spi[reg]; -#else -#ifdef CONFIG_BCM63XX_CPU_6338 -switch (reg) { - case SPI_CMD: - return SPI_BCM_6338_SPI_CMD; - case SPI_INT_STATUS: - return SPI_BCM_6338_SPI_INT_STATUS; - case SPI_INT_MASK_ST: - return SPI_BCM_6338_SPI_MASK_INT_ST; - case SPI_INT_MASK: - return SPI_BCM_6338_SPI_INT_MASK; - case SPI_ST: - return SPI_BCM_6338_SPI_ST; - case SPI_CLK_CFG: - return SPI_BCM_6338_SPI_CLK_CFG; - case SPI_FILL_BYTE: - return SPI_BCM_6338_SPI_FILL_BYTE; - case SPI_MSG_TAIL: - return SPI_BCM_6338_SPI_MSG_TAIL; - case SPI_RX_TAIL: - return SPI_BCM_6338_SPI_RX_TAIL; - case SPI_MSG_CTL: - return SPI_BCM_6338_SPI_MSG_CTL; - case SPI_MSG_DATA: - return SPI_BCM_6338_SPI_MSG_DATA; - case SPI_RX_DATA: - return SPI_BCM_6338_SPI_RX_DATA; -} -#endif -#ifdef CONFIG_BCM63XX_CPU_6348 -switch (reg) { - case SPI_CMD: - return SPI_BCM_6348_SPI_CMD; - case SPI_INT_MASK_ST: - return SPI_BCM_6348_SPI_MASK_INT_ST; - case SPI_INT_MASK: - return SPI_BCM_6348_SPI_INT_MASK; - case SPI_INT_STATUS: - return SPI_BCM_6348_SPI_INT_STATUS; - case SPI_ST: - return SPI_BCM_6348_SPI_ST; - case SPI_CLK_CFG: - return SPI_BCM_6348_SPI_CLK_CFG; - case SPI_FILL_BYTE: - return SPI_BCM_6348_SPI_FILL_BYTE; - case SPI_MSG_TAIL: - return SPI_BCM_6348_SPI_MSG_TAIL; - case SPI_RX_TAIL: - return SPI_BCM_6348_SPI_RX_TAIL; - case SPI_MSG_CTL: - return SPI_BCM_6348_SPI_MSG_CTL; - case SPI_MSG_DATA: - return SPI_BCM_6348_SPI_MSG_DATA; - case SPI_RX_DATA: - return SPI_BCM_6348_SPI_RX_DATA; -} -#endif -#ifdef CONFIG_BCM63XX_CPU_6358 -switch (reg) { - case SPI_CMD: - return SPI_BCM_6358_SPI_CMD; - case SPI_INT_STATUS: - return SPI_BCM_6358_SPI_INT_STATUS; - case SPI_INT_MASK_ST: - return SPI_BCM_6358_SPI_MASK_INT_ST; - case SPI_INT_MASK: - return SPI_BCM_6358_SPI_INT_MASK; - case SPI_ST: - return SPI_BCM_6358_SPI_STATUS; - case SPI_CLK_CFG: - return SPI_BCM_6358_SPI_CLK_CFG; - case SPI_FILL_BYTE: - return SPI_BCM_6358_SPI_FILL_BYTE; - case SPI_MSG_TAIL: - return SPI_BCM_6358_SPI_MSG_TAIL; - case SPI_RX_TAIL: - return SPI_BCM_6358_SPI_RX_TAIL; - case SPI_MSG_CTL: - return SPI_BCM_6358_MSG_CTL; - case SPI_MSG_DATA: - return SPI_BCM_6358_SPI_MSG_DATA; - case SPI_RX_DATA: - return SPI_BCM_6358_SPI_RX_DATA; -} -#endif -#endif - return 0; -} - -/* - * IRQ number changes across CPU too - */ -enum bcm63xx_irq { - IRQ_TIMER = 0, - IRQ_UART0, - IRQ_SPI, - IRQ_DSL, - IRQ_UDC0, - IRQ_ENET0, - IRQ_ENET1, - IRQ_ENET_PHY, - IRQ_OHCI0, - IRQ_EHCI0, - IRQ_PCMCIA0, - IRQ_ENET0_RXDMA, - IRQ_ENET0_TXDMA, - IRQ_ENET1_RXDMA, - IRQ_ENET1_TXDMA, - IRQ_PCI, - IRQ_PCMCIA, -}; - -/* - * 6338 irqs - */ -#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) -#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) -#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) -#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) -#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6) -#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7) -#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) -#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) -#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) -#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) -#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12) -#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13) -#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14) -#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) -#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) -#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) - -/* - * 6345 irqs - */ -#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) -#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) -#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4) -#define BCM_6345_UDC0_IRQ (IRQ_INTERNAL_BASE + 5) -#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) -#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) -#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) -#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) -#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) -#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) -#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) -#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) -#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) -#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) -#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) -#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) -#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) -#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) - -/* - * 6348 irqs - */ -#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) -#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) -#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) -#define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6) -#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) -#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) -#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) -#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) -#define BCM_6348_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 14) -#define BCM_6348_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 15) -#define BCM_6348_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 16) -#define BCM_6348_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 17) -#define BCM_6348_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 18) -#define BCM_6348_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 19) -#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) -#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) -#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) -#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) -#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) -#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) - -/* - * 6358 irqs - */ -#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) -#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) -#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) -#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) -#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) -#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) -#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) -#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) -#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) -#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) -#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) -#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) -#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) -#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) - -extern const int *bcm63xx_irqs; - -static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) -{ - return bcm63xx_irqs[irq]; -} - -/* - * return installed memory size - */ -unsigned int bcm63xx_get_memory_size(void); - -#endif /* !BCM63XX_CPU_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h deleted file mode 100644 index b1821c866e..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef BCM63XX_CS_H -#define BCM63XX_CS_H - -int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size); -int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait, - unsigned int setup, unsigned int hold); -int bcm63xx_set_cs_param(unsigned int cs, u32 flags); -int bcm63xx_set_cs_status(unsigned int cs, int enable); - -#endif /* !BCM63XX_CS_H */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_dsp.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_dsp.h deleted file mode 100644 index b587d45c30..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_dsp.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __BCM63XX_DSP_H -#define __BCM63XX_DSP_H - -struct bcm63xx_dsp_platform_data { - unsigned gpio_rst; - unsigned gpio_int; - unsigned cs; - unsigned ext_irq; -}; - -int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd); - -#endif /* __BCM63XX_DSP_H */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_enet.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_enet.h deleted file mode 100644 index d53f611184..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_enet.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef BCM63XX_DEV_ENET_H_ -#define BCM63XX_DEV_ENET_H_ - -#include <linux/if_ether.h> -#include <linux/init.h> - -/* - * on board ethernet platform data - */ -struct bcm63xx_enet_platform_data { - char mac_addr[ETH_ALEN]; - - int has_phy; - - /* if has_phy, then set use_internal_phy */ - int use_internal_phy; - - /* or fill phy info to use an external one */ - int phy_id; - int has_phy_interrupt; - int phy_interrupt; - - /* if has_phy, use autonegociated pause parameters or force - * them */ - int pause_auto; - int pause_rx; - int pause_tx; - - /* if !has_phy, set desired forced speed/duplex */ - int force_speed_100; - int force_duplex_full; - - /* if !has_phy, set callback to perform mii device - * init/remove */ - int (*mii_config)(struct net_device *dev, int probe, - int (*mii_read)(struct net_device *dev, - int phy_id, int reg), - void (*mii_write)(struct net_device *dev, - int phy_id, int reg, int val)); -}; - -int __init bcm63xx_enet_register(int unit, - const struct bcm63xx_enet_platform_data *pd); - -#endif /* ! BCM63XX_DEV_ENET_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h deleted file mode 100644 index c549344b70..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef BCM63XX_DEV_PCI_H_ -#define BCM63XX_DEV_PCI_H_ - -extern int bcm63xx_pci_enabled; - -#endif /* BCM63XX_DEV_PCI_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pcmcia.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pcmcia.h deleted file mode 100644 index 2beb3969ce..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pcmcia.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef BCM63XX_DEV_PCMCIA_H_ -#define BCM63XX_DEV_PCMCIA_H_ - -/* - * PCMCIA driver platform data - */ -struct bcm63xx_pcmcia_platform_data { - unsigned int ready_gpio; -}; - -int bcm63xx_pcmcia_register(void); - -#endif /* BCM63XX_DEV_PCMCIA_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_spi.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_spi.h deleted file mode 100644 index cfa79bf94b..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_spi.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef BCM63XX_DEV_SPI_H -#define BCM63XX_DEV_SPI_H - -#include <linux/types.h> - -int __init bcm63xx_spi_register(void); - -struct bcm63xx_spi_pdata { - unsigned int fifo_size; - int bus_num; - int num_chipselect; - u32 speed_hz; -}; - -#endif /* BCM63XX_DEV_SPI_H */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_uart.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_uart.h deleted file mode 100644 index bf348f573b..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_uart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef BCM63XX_DEV_UART_H_ -#define BCM63XX_DEV_UART_H_ - -int bcm63xx_uart_register(void); - -#endif /* BCM63XX_DEV_UART_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ehci.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ehci.h deleted file mode 100644 index 17fb519dde..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ehci.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef BCM63XX_DEV_USB_EHCI_H_ -#define BCM63XX_DEV_USB_EHCI_H_ - -int bcm63xx_ehci_register(void); - -#endif /* BCM63XX_DEV_USB_EHCI_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ohci.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ohci.h deleted file mode 100644 index 518a04d03f..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ohci.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef BCM63XX_DEV_USB_OHCI_H_ -#define BCM63XX_DEV_USB_OHCI_H_ - -int bcm63xx_ohci_register(void); - -#endif /* BCM63XX_DEV_USB_OHCI_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_udc.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_udc.h deleted file mode 100644 index 54d37f0bc7..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_udc.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef BCM63XX_DEV_USB_UDC_H_ -#define BCM63XX_DEV_USB_UDC_H_ - -int bcm63xx_udc_register(void); - -#endif /* BCM63XX_DEV_USB_UDC_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_wdt.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_wdt.h deleted file mode 100644 index 4aae2c7966..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_dev_wdt.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef BCM63XX_DEV_WDT_H_ -#define BCM63XX_DEV_WDT_H_ - -int bcm63xx_wdt_register(void); - -#endif /* BCM63XX_DEV_WDT_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h deleted file mode 100644 index 43d4da0b1e..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef BCM63XX_GPIO_H -#define BCM63XX_GPIO_H - -#include <linux/init.h> - -int __init bcm63xx_gpio_init(void); - -static inline unsigned long bcm63xx_gpio_count(void) -{ - switch (bcm63xx_get_cpu_id()) { - case BCM6358_CPU_ID: - return 40; - case BCM6338_CPU_ID: - return 8; - case BCM6345_CPU_ID: - return 16; - case BCM6348_CPU_ID: - default: - return 37; - } -} - -#define GPIO_DIR_OUT 0x0 -#define GPIO_DIR_IN 0x1 - -#endif /* !BCM63XX_GPIO_H */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_io.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_io.h deleted file mode 100644 index 31e950e117..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_io.h +++ /dev/null @@ -1,107 +0,0 @@ -#ifndef BCM63XX_IO_H_ -#define BCM63XX_IO_H_ - -#include "bcm63xx_cpu.h" - -/* - * Physical memory map, RAM is mapped at 0x0. - * - * Note that size MUST be a power of two. - */ -#define BCM_PCMCIA_COMMON_BASE_PA (0x20000000) -#define BCM_PCMCIA_COMMON_SIZE (16 * 1024 * 1024) -#define BCM_PCMCIA_COMMON_END_PA (BCM_PCMCIA_COMMON_BASE_PA + \ - BCM_PCMCIA_COMMON_SIZE - 1) - -#define BCM_PCMCIA_ATTR_BASE_PA (0x21000000) -#define BCM_PCMCIA_ATTR_SIZE (16 * 1024 * 1024) -#define BCM_PCMCIA_ATTR_END_PA (BCM_PCMCIA_ATTR_BASE_PA + \ - BCM_PCMCIA_ATTR_SIZE - 1) - -#define BCM_PCMCIA_IO_BASE_PA (0x22000000) -#define BCM_PCMCIA_IO_SIZE (64 * 1024) -#define BCM_PCMCIA_IO_END_PA (BCM_PCMCIA_IO_BASE_PA + \ - BCM_PCMCIA_IO_SIZE - 1) - -#define BCM_PCI_MEM_BASE_PA (0x30000000) -#define BCM_PCI_MEM_SIZE (128 * 1024 * 1024) -#define BCM_PCI_MEM_END_PA (BCM_PCI_MEM_BASE_PA + \ - BCM_PCI_MEM_SIZE - 1) - -#define BCM_PCI_IO_BASE_PA (0x08000000) -#define BCM_PCI_IO_SIZE (64 * 1024) -#define BCM_PCI_IO_END_PA (BCM_PCI_IO_BASE_PA + \ - BCM_PCI_IO_SIZE - 1) -#define BCM_PCI_IO_HALF_PA (BCM_PCI_IO_BASE_PA + \ - (BCM_PCI_IO_SIZE / 2) - 1) - -#define BCM_CB_MEM_BASE_PA (0x38000000) -#define BCM_CB_MEM_SIZE (128 * 1024 * 1024) -#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ - BCM_CB_MEM_SIZE - 1) - - -/* - * Internal registers are accessed through KSEG3 - */ -#define BCM_REGS_VA(x) ((void __iomem *)(x)) - -#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a)) -#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a)) -#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a)) -#define bcm_writeb(v,a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v)) -#define bcm_writew(v,a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v)) -#define bcm_writel(v,a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v)) - -/* - * IO helpers to access register set for current CPU - */ -#define bcm_rset_readb(s,o) bcm_readb(bcm63xx_regset_address(s) + (o)) -#define bcm_rset_readw(s,o) bcm_readw(bcm63xx_regset_address(s) + (o)) -#define bcm_rset_readl(s,o) bcm_readl(bcm63xx_regset_address(s) + (o)) -#define bcm_rset_writeb(s,v,o) bcm_writeb((v), \ - bcm63xx_regset_address(s) + (o)) -#define bcm_rset_writew(s,v,o) bcm_writew((v), \ - bcm63xx_regset_address(s) + (o)) -#define bcm_rset_writel(s,v,o) bcm_writel((v), \ - bcm63xx_regset_address(s) + (o)) - -/* - * helpers for frequently used register sets - */ -#define bcm_perf_readl(o) bcm_rset_readl(RSET_PERF, (o)) -#define bcm_perf_writel(v,o) bcm_rset_writel(RSET_PERF, (v), (o)) -#define bcm_timer_readl(o) bcm_rset_readl(RSET_TIMER, (o)) -#define bcm_timer_writel(v,o) bcm_rset_writel(RSET_TIMER, (v), (o)) -#define bcm_wdt_readl(o) bcm_rset_readl(RSET_WDT, (o)) -#define bcm_wdt_writel(v,o) bcm_rset_writel(RSET_WDT, (v), (o)) -#define bcm_gpio_readl(o) bcm_rset_readl(RSET_GPIO, (o)) -#define bcm_gpio_writel(v,o) bcm_rset_writel(RSET_GPIO, (v), (o)) -#define bcm_uart0_readl(o) bcm_rset_readl(RSET_UART0, (o)) -#define bcm_uart0_writel(v,o) bcm_rset_writel(RSET_UART0, (v), (o)) -#define bcm_mpi_readl(o) bcm_rset_readl(RSET_MPI, (o)) -#define bcm_mpi_writel(v,o) bcm_rset_writel(RSET_MPI, (v), (o)) -#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o)) -#define bcm_pcmcia_writel(v,o) bcm_rset_writel(RSET_PCMCIA, (v), (o)) -#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o)) -#define bcm_sdram_writel(v,o) bcm_rset_writel(RSET_SDRAM, (v), (o)) -#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o)) -#define bcm_memc_writel(v,o) bcm_rset_writel(RSET_MEMC, (v), (o)) -#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o)) -#define bcm_ddr_writel(v,o) bcm_rset_writel(RSET_DDR, (v), (o)) - -/* - * helpers for the SPI register sets - */ -#define bcm_spi_readb(b,o) bcm_readb((b) + \ - bcm63xx_spireg(o)) -#define bcm_spi_readw(b,o) bcm_readw((b) + \ - bcm63xx_spireg(o)) -#define bcm_spi_writeb(v,b,o) bcm_writeb((v), \ - (b) + \ - bcm63xx_spireg(o)) -#define bcm_spi_writew(v,b,o) bcm_writew((v), \ - (b) + \ - bcm63xx_spireg(o)) - -#endif /* ! BCM63XX_IO_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h deleted file mode 100644 index 5f95577c82..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef BCM63XX_IRQ_H_ -#define BCM63XX_IRQ_H_ - -#include <bcm63xx_cpu.h> - -#define IRQ_MIPS_BASE 0 -#define IRQ_INTERNAL_BASE 8 - -#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3) -#define IRQ_EXT_0 (IRQ_EXT_BASE + 0) -#define IRQ_EXT_1 (IRQ_EXT_BASE + 1) -#define IRQ_EXT_2 (IRQ_EXT_BASE + 2) -#define IRQ_EXT_3 (IRQ_EXT_BASE + 3) - -#endif /* ! BCM63XX_IRQ_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h deleted file mode 100644 index e2cc60758e..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h +++ /dev/null @@ -1,886 +0,0 @@ -#ifndef BCM63XX_REGS_H_ -#define BCM63XX_REGS_H_ - -/************************************************************************* - * _REG relative to RSET_PERF - *************************************************************************/ - -/* Chip Identifier / Revision register */ -#define PERF_REV_REG 0x0 -#define REV_CHIPID_SHIFT 16 -#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) -#define REV_REVID_SHIFT 0 -#define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) - -/* Clock Control register */ -#define PERF_CKCTL_REG 0x4 - -#define CKCTL_6338_ADSLPHY_EN (1 << 0) -#define CKCTL_6338_MPI_EN (1 << 1) -#define CKCTL_6338_DRAM_EN (1 << 2) -#define CKCTL_6338_ENET_EN (1 << 4) -#define CKCTL_6338_USBS_EN (1 << 4) -#define CKCTL_6338_SAR_EN (1 << 5) -#define CKCTL_6338_SPI_EN (1 << 9) - -#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \ - CKCTL_6338_MPI_EN | \ - CKCTL_6338_ENET_EN | \ - CKCTL_6338_SAR_EN | \ - CKCTL_6338_SPI_EN) - -#define CKCTL_6345_CPU_EN (1 << 0) -#define CKCTL_6345_BUS_EN (1 << 1) -#define CKCTL_6345_EBI_EN (1 << 2) -#define CKCTL_6345_UART_EN (1 << 3) -#define CKCTL_6345_ADSLPHY_EN (1 << 4) -#define CKCTL_6345_ENET_EN (1 << 7) -#define CKCTL_6345_USBS_EN (1 << 8) - -#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ - CKCTL_6345_USBS_EN | \ - CKCTL_6345_ADSLPHY_EN) - -#define CKCTL_6348_ADSLPHY_EN (1 << 0) -#define CKCTL_6348_MPI_EN (1 << 1) -#define CKCTL_6348_SDRAM_EN (1 << 2) -#define CKCTL_6348_M2M_EN (1 << 3) -#define CKCTL_6348_ENET_EN (1 << 4) -#define CKCTL_6348_SAR_EN (1 << 5) -#define CKCTL_6348_USBS_EN (1 << 6) -#define CKCTL_6348_USBH_EN (1 << 8) -#define CKCTL_6348_SPI_EN (1 << 9) - -#define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \ - CKCTL_6348_M2M_EN | \ - CKCTL_6348_ENET_EN | \ - CKCTL_6348_SAR_EN | \ - CKCTL_6348_USBS_EN | \ - CKCTL_6348_USBH_EN | \ - CKCTL_6348_SPI_EN) - -#define CKCTL_6358_ENET_EN (1 << 4) -#define CKCTL_6358_ADSLPHY_EN (1 << 5) -#define CKCTL_6358_PCM_EN (1 << 8) -#define CKCTL_6358_SPI_EN (1 << 9) -#define CKCTL_6358_USBS_EN (1 << 10) -#define CKCTL_6358_SAR_EN (1 << 11) -#define CKCTL_6358_EMUSB_EN (1 << 17) -#define CKCTL_6358_ENET0_EN (1 << 18) -#define CKCTL_6358_ENET1_EN (1 << 19) -#define CKCTL_6358_USBSU_EN (1 << 20) -#define CKCTL_6358_EPHY_EN (1 << 21) - -#define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \ - CKCTL_6358_ADSLPHY_EN | \ - CKCTL_6358_PCM_EN | \ - CKCTL_6358_SPI_EN | \ - CKCTL_6358_USBS_EN | \ - CKCTL_6358_SAR_EN | \ - CKCTL_6358_EMUSB_EN | \ - CKCTL_6358_ENET0_EN | \ - CKCTL_6358_ENET1_EN | \ - CKCTL_6358_USBSU_EN | \ - CKCTL_6358_EPHY_EN) - -/* System PLL Control register */ -#define PERF_SYS_PLL_CTL_REG 0x8 -#define SYS_PLL_SOFT_RESET 0x1 - -/* Interrupt Mask register */ -#define PERF_IRQMASK_REG 0xc - -/* Interrupt Status register */ -#define PERF_IRQSTAT_REG 0x10 - -/* External Interrupt Configuration register */ -#define PERF_EXTIRQ_CFG_REG 0x14 -#define EXTIRQ_CFG_SENSE(x) (1 << (x)) -#define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) -#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) -#define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) -#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) -#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) - -#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) -#define EXTIRQ_CFG_MASK_ALL (0xf << 15) - -/* Soft Reset register */ -#define PERF_SOFTRESET_REG 0x28 - -#define SOFTRESET_6338_SPI_MASK (1 << 0) -#define SOFTRESET_6338_ENET_MASK (1 << 2) -#define SOFTRESET_6338_USBH_MASK (1 << 3) -#define SOFTRESET_6338_USBS_MASK (1 << 4) -#define SOFTRESET_6338_ADSL_MASK (1 << 5) -#define SOFTRESET_6338_DMAMEM_MASK (1 << 6) -#define SOFTRESET_6338_SAR_MASK (1 << 7) -#define SOFTRESET_6338_ACLC_MASK (1 << 8) -#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) -#define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \ - SOFTRESET_6338_ENET_MASK | \ - SOFTRESET_6338_USBH_MASK | \ - SOFTRESET_6338_USBS_MASK | \ - SOFTRESET_6338_ADSL_MASK | \ - SOFTRESET_6338_DMAMEM_MASK | \ - SOFTRESET_6338_SAR_MASK | \ - SOFTRESET_6338_ACLC_MASK | \ - SOFTRESET_6338_ADSLMIPSPLL_MASK) - -#define SOFTRESET_6348_SPI_MASK (1 << 0) -#define SOFTRESET_6348_ENET_MASK (1 << 2) -#define SOFTRESET_6348_USBH_MASK (1 << 3) -#define SOFTRESET_6348_USBS_MASK (1 << 4) -#define SOFTRESET_6348_ADSL_MASK (1 << 5) -#define SOFTRESET_6348_DMAMEM_MASK (1 << 6) -#define SOFTRESET_6348_SAR_MASK (1 << 7) -#define SOFTRESET_6348_ACLC_MASK (1 << 8) -#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) - -#define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \ - SOFTRESET_6348_ENET_MASK | \ - SOFTRESET_6348_USBH_MASK | \ - SOFTRESET_6348_USBS_MASK | \ - SOFTRESET_6348_ADSL_MASK | \ - SOFTRESET_6348_DMAMEM_MASK | \ - SOFTRESET_6348_SAR_MASK | \ - SOFTRESET_6348_ACLC_MASK | \ - SOFTRESET_6348_ADSLMIPSPLL_MASK) - -/* MIPS PLL control register */ -#define PERF_MIPSPLLCTL_REG 0x34 -#define MIPSPLLCTL_N1_SHIFT 20 -#define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT) -#define MIPSPLLCTL_N2_SHIFT 15 -#define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT) -#define MIPSPLLCTL_M1REF_SHIFT 12 -#define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT) -#define MIPSPLLCTL_M2REF_SHIFT 9 -#define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT) -#define MIPSPLLCTL_M1CPU_SHIFT 6 -#define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT) -#define MIPSPLLCTL_M1BUS_SHIFT 3 -#define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT) -#define MIPSPLLCTL_M2BUS_SHIFT 0 -#define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT) - -/* ADSL PHY PLL Control register */ -#define PERF_ADSLPLLCTL_REG 0x38 -#define ADSLPLLCTL_N1_SHIFT 20 -#define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT) -#define ADSLPLLCTL_N2_SHIFT 15 -#define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT) -#define ADSLPLLCTL_M1REF_SHIFT 12 -#define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT) -#define ADSLPLLCTL_M2REF_SHIFT 9 -#define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT) -#define ADSLPLLCTL_M1CPU_SHIFT 6 -#define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT) -#define ADSLPLLCTL_M1BUS_SHIFT 3 -#define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT) -#define ADSLPLLCTL_M2BUS_SHIFT 0 -#define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT) - -#define ADSLPLLCTL_VAL(n1,n2,m1ref,m2ref,m1cpu,m1bus,m2bus) \ - (((n1) << ADSLPLLCTL_N1_SHIFT) | \ - ((n2) << ADSLPLLCTL_N2_SHIFT) | \ - ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \ - ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \ - ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \ - ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \ - ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT)) - - -/************************************************************************* - * _REG relative to RSET_TIMER - *************************************************************************/ - -#define BCM63XX_TIMER_COUNT 4 -#define TIMER_T0_ID 0 -#define TIMER_T1_ID 1 -#define TIMER_T2_ID 2 -#define TIMER_WDT_ID 3 - -/* Timer irqstat register */ -#define TIMER_IRQSTAT_REG 0 -#define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x)) -#define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0) -#define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1) -#define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2) -#define TIMER_IRQSTAT_WDT_CAUSE (1 << 3) -#define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8)) -#define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8) -#define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) -#define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) - -/* Timer control register */ -#define TIMER_CTLx_REG(x) (0x4 + (x * 4)) -#define TIMER_CTL0_REG 0x4 -#define TIMER_CTL1_REG 0x8 -#define TIMER_CTL2_REG 0xC -#define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff) -#define TIMER_CTL_MONOTONIC_MASK (1 << 30) -#define TIMER_CTL_ENABLE_MASK (1 << 31) - - -/************************************************************************* - * _REG relative to RSET_WDT - *************************************************************************/ - -/* Watchdog default count register */ -#define WDT_DEFVAL_REG 0x0 - -/* Watchdog control register */ -#define WDT_CTL_REG 0x4 - -/* Watchdog control register constants */ -#define WDT_START_1 (0xff00) -#define WDT_START_2 (0x00ff) -#define WDT_STOP_1 (0xee00) -#define WDT_STOP_2 (0x00ee) - -/* Watchdog reset length register */ -#define WDT_RSTLEN_REG 0x8 - - -/************************************************************************* - * _REG relative to RSET_UARTx - *************************************************************************/ - -/* UART Control Register */ -#define UART_CTL_REG 0x0 -#define UART_CTL_RXTMOUTCNT_SHIFT 0 -#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) -#define UART_CTL_RSTTXDN_SHIFT 5 -#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) -#define UART_CTL_RSTRXFIFO_SHIFT 6 -#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) -#define UART_CTL_RSTTXFIFO_SHIFT 7 -#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) -#define UART_CTL_STOPBITS_SHIFT 8 -#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) -#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) -#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) -#define UART_CTL_BITSPERSYM_SHIFT 12 -#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) -#define UART_CTL_XMITBRK_SHIFT 14 -#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) -#define UART_CTL_RSVD_SHIFT 15 -#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) -#define UART_CTL_RXPAREVEN_SHIFT 16 -#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) -#define UART_CTL_RXPAREN_SHIFT 17 -#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) -#define UART_CTL_TXPAREVEN_SHIFT 18 -#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) -#define UART_CTL_TXPAREN_SHIFT 18 -#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) -#define UART_CTL_LOOPBACK_SHIFT 20 -#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) -#define UART_CTL_RXEN_SHIFT 21 -#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) -#define UART_CTL_TXEN_SHIFT 22 -#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) -#define UART_CTL_BRGEN_SHIFT 23 -#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) - -/* UART Baudword register */ -#define UART_BAUD_REG 0x4 - -/* UART Misc Control register */ -#define UART_MCTL_REG 0x8 -#define UART_MCTL_DTR_SHIFT 0 -#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) -#define UART_MCTL_RTS_SHIFT 1 -#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) -#define UART_MCTL_RXFIFOTHRESH_SHIFT 8 -#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) -#define UART_MCTL_TXFIFOTHRESH_SHIFT 12 -#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) -#define UART_MCTL_RXFIFOFILL_SHIFT 16 -#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) -#define UART_MCTL_TXFIFOFILL_SHIFT 24 -#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) - -/* UART External Input Configuration register */ -#define UART_EXTINP_REG 0xc -#define UART_EXTINP_RI_SHIFT 0 -#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) -#define UART_EXTINP_CTS_SHIFT 1 -#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) -#define UART_EXTINP_DCD_SHIFT 2 -#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) -#define UART_EXTINP_DSR_SHIFT 3 -#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) -#define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) -#define UART_EXTINP_IRMASK(x) (1 << (x + 8)) -#define UART_EXTINP_IR_RI 0 -#define UART_EXTINP_IR_CTS 1 -#define UART_EXTINP_IR_DCD 2 -#define UART_EXTINP_IR_DSR 3 -#define UART_EXTINP_RI_NOSENSE_SHIFT 16 -#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) -#define UART_EXTINP_CTS_NOSENSE_SHIFT 17 -#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) -#define UART_EXTINP_DCD_NOSENSE_SHIFT 18 -#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) -#define UART_EXTINP_DSR_NOSENSE_SHIFT 19 -#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) - -/* UART Interrupt register */ -#define UART_IR_REG 0x10 -#define UART_IR_MASK(x) (1 << (x + 16)) -#define UART_IR_STAT(x) (1 << (x)) -#define UART_IR_EXTIP 0 -#define UART_IR_TXUNDER 1 -#define UART_IR_TXOVER 2 -#define UART_IR_TXTRESH 3 -#define UART_IR_TXRDLATCH 4 -#define UART_IR_TXEMPTY 5 -#define UART_IR_RXUNDER 6 -#define UART_IR_RXOVER 7 -#define UART_IR_RXTIMEOUT 8 -#define UART_IR_RXFULL 9 -#define UART_IR_RXTHRESH 10 -#define UART_IR_RXNOTEMPTY 11 -#define UART_IR_RXFRAMEERR 12 -#define UART_IR_RXPARERR 13 -#define UART_IR_RXBRK 14 -#define UART_IR_TXDONE 15 - -/* UART Fifo register */ -#define UART_FIFO_REG 0x14 -#define UART_FIFO_VALID_SHIFT 0 -#define UART_FIFO_VALID_MASK 0xff -#define UART_FIFO_FRAMEERR_SHIFT 8 -#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) -#define UART_FIFO_PARERR_SHIFT 9 -#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) -#define UART_FIFO_BRKDET_SHIFT 10 -#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) -#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ - UART_FIFO_PARERR_MASK | \ - UART_FIFO_BRKDET_MASK) - - -/************************************************************************* - * _REG relative to RSET_GPIO - *************************************************************************/ - -/* GPIO registers */ -#define GPIO_CTL_HI_REG 0x0 -#define GPIO_CTL_LO_REG 0x4 -#define GPIO_DATA_HI_REG 0x8 -#define GPIO_DATA_LO_REG 0xC - -/* GPIO mux registers and constants */ -#define GPIO_MODE_REG 0x18 - -#define GPIO_MODE_6348_G4_DIAG 0x00090000 -#define GPIO_MODE_6348_G4_UTOPIA 0x00080000 -#define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000 -#define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000 -#define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000 -#define GPIO_MODE_6348_G3_DIAG 0x00009000 -#define GPIO_MODE_6348_G3_UTOPIA 0x00008000 -#define GPIO_MODE_6348_G3_EXT_MII 0x00007000 -#define GPIO_MODE_6348_G2_DIAG 0x00000900 -#define GPIO_MODE_6348_G2_PCI 0x00000500 -#define GPIO_MODE_6348_G1_DIAG 0x00000090 -#define GPIO_MODE_6348_G1_UTOPIA 0x00000080 -#define GPIO_MODE_6348_G1_SPI_UART 0x00000060 -#define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060 -#define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040 -#define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020 -#define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010 -#define GPIO_MODE_6348_G0_DIAG 0x00000009 -#define GPIO_MODE_6348_G0_EXT_MII 0x00000007 - -#define GPIO_MODE_6358_EXTRACS (1 << 5) -#define GPIO_MODE_6358_UART1 (1 << 6) -#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) -#define GPIO_MODE_6358_SERIAL_LED (1 << 10) -#define GPIO_MODE_6358_UTOPIA (1 << 12) - - -/************************************************************************* - * _REG relative to RSET_ENET - *************************************************************************/ - -/* Receiver Configuration register */ -#define ENET_RXCFG_REG 0x0 -#define ENET_RXCFG_ALLMCAST_SHIFT 1 -#define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT) -#define ENET_RXCFG_PROMISC_SHIFT 3 -#define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT) -#define ENET_RXCFG_LOOPBACK_SHIFT 4 -#define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT) -#define ENET_RXCFG_ENFLOW_SHIFT 5 -#define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT) - -/* Receive Maximum Length register */ -#define ENET_RXMAXLEN_REG 0x4 -#define ENET_RXMAXLEN_SHIFT 0 -#define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT) - -/* Transmit Maximum Length register */ -#define ENET_TXMAXLEN_REG 0x8 -#define ENET_TXMAXLEN_SHIFT 0 -#define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT) - -/* MII Status/Control register */ -#define ENET_MIISC_REG 0x10 -#define ENET_MIISC_MDCFREQDIV_SHIFT 0 -#define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT) -#define ENET_MIISC_PREAMBLEEN_SHIFT 7 -#define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT) - -/* MII Data register */ -#define ENET_MIIDATA_REG 0x14 -#define ENET_MIIDATA_DATA_SHIFT 0 -#define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT) -#define ENET_MIIDATA_TA_SHIFT 16 -#define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT) -#define ENET_MIIDATA_REG_SHIFT 18 -#define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT) -#define ENET_MIIDATA_PHYID_SHIFT 23 -#define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT) -#define ENET_MIIDATA_OP_READ_MASK (0x6 << 28) -#define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28) - -/* Ethernet Interrupt Mask register */ -#define ENET_IRMASK_REG 0x18 - -/* Ethernet Interrupt register */ -#define ENET_IR_REG 0x1c -#define ENET_IR_MII (1 << 0) -#define ENET_IR_MIB (1 << 1) -#define ENET_IR_FLOWC (1 << 2) - -/* Ethernet Control register */ -#define ENET_CTL_REG 0x2c -#define ENET_CTL_ENABLE_SHIFT 0 -#define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT) -#define ENET_CTL_DISABLE_SHIFT 1 -#define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT) -#define ENET_CTL_SRESET_SHIFT 2 -#define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT) -#define ENET_CTL_EPHYSEL_SHIFT 3 -#define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT) - -/* Transmit Control register */ -#define ENET_TXCTL_REG 0x30 -#define ENET_TXCTL_FD_SHIFT 0 -#define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT) - -/* Transmit Watermask register */ -#define ENET_TXWMARK_REG 0x34 -#define ENET_TXWMARK_WM_SHIFT 0 -#define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT) - -/* MIB Control register */ -#define ENET_MIBCTL_REG 0x38 -#define ENET_MIBCTL_RDCLEAR_SHIFT 0 -#define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT) - -/* Perfect Match Data Low register */ -#define ENET_PML_REG(x) (0x58 + (x) * 8) -#define ENET_PMH_REG(x) (0x5c + (x) * 8) -#define ENET_PMH_DATAVALID_SHIFT 16 -#define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT) - -/* MIB register */ -#define ENET_MIB_REG(x) (0x200 + (x) * 4) -#define ENET_MIB_REG_COUNT 55 - - -/************************************************************************* - * _REG relative to RSET_ENETDMA - *************************************************************************/ - -/* Controller Configuration Register */ -#define ENETDMA_CFG_REG (0x0) -#define ENETDMA_CFG_EN_SHIFT 0 -#define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT) -#define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1)) - -/* Flow Control Descriptor Low Threshold register */ -#define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6) - -/* Flow Control Descriptor High Threshold register */ -#define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6) - -/* Flow Control Descriptor Buffer Alloca Threshold register */ -#define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6) -#define ENETDMA_BUFALLOC_FORCE_SHIFT 31 -#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) - -/* Channel Configuration register */ -#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) -#define ENETDMA_CHANCFG_EN_SHIFT 0 -#define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) -#define ENETDMA_CHANCFG_PKTHALT_SHIFT 1 -#define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) - -/* Interrupt Control/Status register */ -#define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10) -#define ENETDMA_IR_BUFDONE_MASK (1 << 0) -#define ENETDMA_IR_PKTDONE_MASK (1 << 1) -#define ENETDMA_IR_NOTOWNER_MASK (1 << 2) - -/* Interrupt Mask register */ -#define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10) - -/* Maximum Burst Length */ -#define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10) - -/* Ring Start Address register */ -#define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10) - -/* State Ram Word 2 */ -#define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10) - -/* State Ram Word 3 */ -#define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10) - -/* State Ram Word 4 */ -#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) - - -/************************************************************************* - * _REG relative to RSET_OHCI_PRIV - *************************************************************************/ - -#define OHCI_PRIV_REG 0x0 -#define OHCI_PRIV_PORT1_HOST_SHIFT 0 -#define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT) -#define OHCI_PRIV_REG_SWAP_SHIFT 3 -#define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT) - - -/************************************************************************* - * _REG relative to RSET_USBH_PRIV - *************************************************************************/ - -#define USBH_PRIV_SWAP_REG 0x0 -#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 -#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) -#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 -#define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT) -#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1 -#define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT) -#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 -#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) - -#define USBH_PRIV_TEST_REG 0x24 - - -/************************************************************************* - * _REG relative to RSET_MPI - *************************************************************************/ - -/* well known (hard wired) chip select */ -#define MPI_CS_PCMCIA_COMMON 4 -#define MPI_CS_PCMCIA_ATTR 5 -#define MPI_CS_PCMCIA_IO 6 - -/* Chip select base register */ -#define MPI_CSBASE_REG(x) (0x0 + (x) * 8) -#define MPI_CSBASE_BASE_SHIFT 13 -#define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT) -#define MPI_CSBASE_SIZE_SHIFT 0 -#define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT) - -#define MPI_CSBASE_SIZE_8K 0 -#define MPI_CSBASE_SIZE_16K 1 -#define MPI_CSBASE_SIZE_32K 2 -#define MPI_CSBASE_SIZE_64K 3 -#define MPI_CSBASE_SIZE_128K 4 -#define MPI_CSBASE_SIZE_256K 5 -#define MPI_CSBASE_SIZE_512K 6 -#define MPI_CSBASE_SIZE_1M 7 -#define MPI_CSBASE_SIZE_2M 8 -#define MPI_CSBASE_SIZE_4M 9 -#define MPI_CSBASE_SIZE_8M 10 -#define MPI_CSBASE_SIZE_16M 11 -#define MPI_CSBASE_SIZE_32M 12 -#define MPI_CSBASE_SIZE_64M 13 -#define MPI_CSBASE_SIZE_128M 14 -#define MPI_CSBASE_SIZE_256M 15 - -/* Chip select control register */ -#define MPI_CSCTL_REG(x) (0x4 + (x) * 8) -#define MPI_CSCTL_ENABLE_MASK (1 << 0) -#define MPI_CSCTL_WAIT_SHIFT 1 -#define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT) -#define MPI_CSCTL_DATA16_MASK (1 << 4) -#define MPI_CSCTL_SYNCMODE_MASK (1 << 7) -#define MPI_CSCTL_TSIZE_MASK (1 << 8) -#define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10) -#define MPI_CSCTL_SETUP_SHIFT 16 -#define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT) -#define MPI_CSCTL_HOLD_SHIFT 20 -#define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT) - -/* PCI registers */ -#define MPI_SP0_RANGE_REG 0x100 -#define MPI_SP0_REMAP_REG 0x104 -#define MPI_SP0_REMAP_ENABLE_MASK (1 << 0) -#define MPI_SP1_RANGE_REG 0x10C -#define MPI_SP1_REMAP_REG 0x110 -#define MPI_SP1_REMAP_ENABLE_MASK (1 << 0) - -#define MPI_L2PCFG_REG 0x11C -#define MPI_L2PCFG_CFG_TYPE_SHIFT 0 -#define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT) -#define MPI_L2PCFG_REG_SHIFT 2 -#define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT) -#define MPI_L2PCFG_FUNC_SHIFT 8 -#define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT) -#define MPI_L2PCFG_DEVNUM_SHIFT 11 -#define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT) -#define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30) -#define MPI_L2PCFG_CFG_SEL_MASK (1 << 31) - -#define MPI_L2PMEMRANGE1_REG 0x120 -#define MPI_L2PMEMBASE1_REG 0x124 -#define MPI_L2PMEMREMAP1_REG 0x128 -#define MPI_L2PMEMRANGE2_REG 0x12C -#define MPI_L2PMEMBASE2_REG 0x130 -#define MPI_L2PMEMREMAP2_REG 0x134 -#define MPI_L2PIORANGE_REG 0x138 -#define MPI_L2PIOBASE_REG 0x13C -#define MPI_L2PIOREMAP_REG 0x140 -#define MPI_L2P_BASE_MASK (0xffff8000) -#define MPI_L2PREMAP_ENABLED_MASK (1 << 0) -#define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2) - -#define MPI_PCIMODESEL_REG 0x144 -#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) -#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) -#define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2) -#define MPI_PCIMODESEL_PREFETCH_SHIFT 4 -#define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT) - -#define MPI_LOCBUSCTL_REG 0x14C -#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0) -#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1) - -#define MPI_LOCINT_REG 0x150 -#define MPI_LOCINT_MASK(x) (1 << (x + 16)) -#define MPI_LOCINT_STAT(x) (1 << (x)) -#define MPI_LOCINT_DIR_FAILED 6 -#define MPI_LOCINT_EXT_PCI_INT 7 -#define MPI_LOCINT_SERR 8 -#define MPI_LOCINT_CSERR 9 - -#define MPI_PCICFGCTL_REG 0x178 -#define MPI_PCICFGCTL_CFGADDR_SHIFT 2 -#define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT) -#define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7) - -#define MPI_PCICFGDATA_REG 0x17C - -/* PCI host bridge custom register */ -#define BCMPCI_REG_TIMERS 0x40 -#define REG_TIMER_TRDY_SHIFT 0 -#define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT) -#define REG_TIMER_RETRY_SHIFT 8 -#define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT) - - -/************************************************************************* - * _REG relative to RSET_PCMCIA - *************************************************************************/ - -#define PCMCIA_C1_REG 0x0 -#define PCMCIA_C1_CD1_MASK (1 << 0) -#define PCMCIA_C1_CD2_MASK (1 << 1) -#define PCMCIA_C1_VS1_MASK (1 << 2) -#define PCMCIA_C1_VS2_MASK (1 << 3) -#define PCMCIA_C1_VS1OE_MASK (1 << 6) -#define PCMCIA_C1_VS2OE_MASK (1 << 7) -#define PCMCIA_C1_CBIDSEL_SHIFT (8) -#define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT) -#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13) -#define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14) -#define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15) -#define PCMCIA_C1_RESET_MASK (1 << 18) - -#define PCMCIA_C2_REG 0x8 -#define PCMCIA_C2_DATA16_MASK (1 << 0) -#define PCMCIA_C2_BYTESWAP_MASK (1 << 1) -#define PCMCIA_C2_RWCOUNT_SHIFT 2 -#define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT) -#define PCMCIA_C2_INACTIVE_SHIFT 8 -#define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT) -#define PCMCIA_C2_SETUP_SHIFT 16 -#define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT) -#define PCMCIA_C2_HOLD_SHIFT 24 -#define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT) - - -/************************************************************************* - * _REG relative to RSET_SDRAM - *************************************************************************/ - -#define SDRAM_CFG_REG 0x0 -#define SDRAM_CFG_ROW_SHIFT 4 -#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT) -#define SDRAM_CFG_COL_SHIFT 6 -#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT) -#define SDRAM_CFG_32B_SHIFT 10 -#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) -#define SDRAM_CFG_BANK_SHIFT 13 -#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) - -#define SDRAM_MEM_REG 0xc - -#define SDRAM_PRIO_REG 0x2C -#define SDRAM_PRIO_MIPS_SHIFT 29 -#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) -#define SDRAM_PRIO_ADSL_SHIFT 30 -#define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT) -#define SDRAM_PRIO_EN_SHIFT 31 -#define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT) - - -/************************************************************************* - * _REG relative to RSET_MEMC - *************************************************************************/ - -#define MEMC_CFG_REG 0x4 -#define MEMC_CFG_32B_SHIFT 1 -#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) -#define MEMC_CFG_COL_SHIFT 3 -#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) -#define MEMC_CFG_ROW_SHIFT 6 -#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) - - -/************************************************************************* - * _REG relative to RSET_DDR - *************************************************************************/ - -#define DDR_DMIPSPLLCFG_REG 0x18 -#define DMIPSPLLCFG_M1_SHIFT 0 -#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) -#define DMIPSPLLCFG_N1_SHIFT 23 -#define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT) -#define DMIPSPLLCFG_N2_SHIFT 29 -#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) - -/************************************************************************* - * _REG relative to RSET_SPI - *************************************************************************/ - -/* BCM 6338 SPI core */ -#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */ -#define SPI_BCM_6338_SPI_INT_STATUS 0x02 -#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03 -#define SPI_BCM_6338_SPI_INT_MASK 0x04 -#define SPI_BCM_6338_SPI_ST 0x05 -#define SPI_BCM_6338_SPI_CLK_CFG 0x06 -#define SPI_BCM_6338_SPI_FILL_BYTE 0x07 -#define SPI_BCM_6338_SPI_MSG_TAIL 0x09 -#define SPI_BCM_6338_SPI_RX_TAIL 0x0b -#define SPI_BCM_6338_SPI_MSG_CTL 0x40 -#define SPI_BCM_6338_SPI_MSG_DATA 0x41 -#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f -#define SPI_BCM_6338_SPI_RX_DATA 0x80 -#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f - -/* BCM 6348 SPI core */ -#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00 -#define SPI_BCM_6348_SPI_INT_STATUS 0x01 -#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */ -#define SPI_BCM_6348_SPI_FILL_BYTE 0x04 -#define SPI_BCM_6348_SPI_CLK_CFG 0x05 -#define SPI_BCM_6348_SPI_ST 0x06 -#define SPI_BCM_6348_SPI_INT_MASK 0x07 -#define SPI_BCM_6348_SPI_RX_TAIL 0x08 -#define SPI_BCM_6348_SPI_MSG_TAIL 0x10 -#define SPI_BCM_6348_SPI_MSG_DATA 0x40 -#define SPI_BCM_6348_SPI_MSG_CTL 0x42 -#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f -#define SPI_BCM_6348_SPI_RX_DATA 0x80 -#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f - -/* BCM 6358 SPI core */ -#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */ - -#define SPI_BCM_6358_SPI_MSG_DATA 0x02 -#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e - -#define SPI_BCM_6358_SPI_RX_DATA 0x400 -#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220 - -#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */ - -#define SPI_BCM_6358_SPI_INT_STATUS 0x702 -#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703 - -#define SPI_BCM_6358_SPI_INT_MASK 0x704 - -#define SPI_BCM_6358_SPI_STATUS 0x705 - -#define SPI_BCM_6358_SPI_CLK_CFG 0x706 - -#define SPI_BCM_6358_SPI_FILL_BYTE 0x707 -#define SPI_BCM_6358_SPI_MSG_TAIL 0x709 -#define SPI_BCM_6358_SPI_RX_TAIL 0x70B - -/* Shared SPI definitions */ - -/* Message configuration */ -#define SPI_FD_RW 0x00 -#define SPI_HD_W 0x01 -#define SPI_HD_R 0x02 -#define SPI_BYTE_CNT_SHIFT 0 -#define SPI_MSG_TYPE_SHIFT 14 - -/* Command */ -#define SPI_CMD_NOOP 0x01 -#define SPI_CMD_SOFT_RESET 0x02 -#define SPI_CMD_HARD_RESET 0x04 -#define SPI_CMD_START_IMMEDIATE 0x08 -#define SPI_CMD_COMMAND_SHIFT 0 -#define SPI_CMD_COMMAND_MASK 0x000f -#define SPI_CMD_DEVICE_ID_SHIFT 4 -#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 -#define SPI_CMD_ONE_BYTE_SHIFT 11 -#define SPI_CMD_ONE_WIRE_SHIFT 12 -#define SPI_DEV_ID_0 0 -#define SPI_DEV_ID_1 1 -#define SPI_DEV_ID_2 2 -#define SPI_DEV_ID_3 3 - -/* Interrupt mask */ -#define SPI_INTR_CMD_DONE 0x01 -#define SPI_INTR_RX_OVERFLOW 0x02 -#define SPI_INTR_TX_UNDERFLOW 0x04 -#define SPI_INTR_TX_OVERFLOW 0x08 -#define SPI_INTR_RX_UNDERFLOW 0x10 -#define SPI_INTR_CLEAR_ALL 0x1f - -/* Status */ -#define SPI_RX_EMPTY 0x02 -#define SPI_CMD_BUSY 0x04 -#define SPI_SERIAL_BUSY 0x08 - -/* Clock configuration */ -#define SPI_CLK_20MHZ 0x00 -#define SPI_CLK_0_391MHZ 0x01 -#define SPI_CLK_0_781MHZ 0x02 /* default */ -#define SPI_CLK_1_563MHZ 0x03 -#define SPI_CLK_3_125MHZ 0x04 -#define SPI_CLK_6_250MHZ 0x05 -#define SPI_CLK_12_50MHZ 0x06 -#define SPI_CLK_25MHZ 0x07 -#define SPI_CLK_MASK 0x07 -#define SPI_SSOFFTIME_MASK 0x38 -#define SPI_SSOFFTIME_SHIFT 3 -#define SPI_BYTE_SWAP 0x80 - - -#endif /* BCM63XX_REGS_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h deleted file mode 100644 index c0fce833c9..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef BCM63XX_TIMER_H_ -#define BCM63XX_TIMER_H_ - -int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data); -void bcm63xx_timer_unregister(int id); -int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us); -int bcm63xx_timer_enable(int id); -int bcm63xx_timer_disable(int id); -unsigned int bcm63xx_timer_countdown(unsigned int countdown_us); - -#endif /* !BCM63XX_TIMER_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm_tag.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm_tag.h deleted file mode 100644 index c06f668942..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/bcm_tag.h +++ /dev/null @@ -1,178 +0,0 @@ -#ifndef __BCM63XX_TAG_H -#define __BCM63XX_TAG_H - -#define IMAGE_LEN 10 /* Length of Length Field */ -#define ADDRESS_LEN 12 /* Length of Address field */ -#define TAGID_LEN 6 /* Length of tag ID */ -#define TAGINFO_LEN 20 /* Length of vendor information field in tag */ -#define TAGVER_LEN 4 /* Length of Tag Version */ -#define TAGLAYOUT_LEN 4 /* Length of FlashLayoutVer */ - -#define NUM_TAGID 5 -#define IMAGETAG_CRC_START 0xFFFFFFFF - -struct tagiddesc_t { - char tagid[TAGID_LEN + 1]; - char tagiddesc[80]; -}; - - // bc221 is used by BT Voyager and should be right - // bc310 should be right, and may apply to 3.08 code as well -#define TAGID_DEFINITIONS { \ - { "bccfe", "Broadcom CFE flash image" }, \ - { "bc300", "Broadcom code version 3.00-3.06 and all ftp/tftp flash" }, \ - { "ag306", "Alice Gate (Pirelli, based on Broadcom 3.06)" }, \ - { "bc221", "Broadcom code version 2.21" }, \ - { "bc310", "Broadcom code version 3.10-3.12" }, \ -} - -struct bcm_tag_bccfe { - unsigned char tagVersion[TAGVER_LEN]; // 0-3: Version of the image tag - unsigned char sig_1[20]; // 4-23: Company Line 1 - unsigned char sig_2[14]; // 24-37: Company Line 2 - unsigned char chipid[6]; // 38-43: Chip this image is for - unsigned char boardid[16]; // 44-59: Board name - unsigned char big_endian[2]; // 60-61: Map endianness -- 1 BE 0 LE - unsigned char totalLength[IMAGE_LEN]; // 62-71: Total length of image - unsigned char cfeAddress[ADDRESS_LEN]; // 72-83: Address in memory of CFE - unsigned char cfeLength[IMAGE_LEN]; // 84-93: Size of CFE - unsigned char rootAddress[ADDRESS_LEN]; // 94-105: Address in memory of rootfs - unsigned char rootLength[IMAGE_LEN]; // 106-115: Size of rootfs - unsigned char kernelAddress[ADDRESS_LEN]; // 116-127: Address in memory of kernel - unsigned char kernelLength[IMAGE_LEN]; // 128-137: Size of kernel - unsigned char dualImage[2]; // 138-139: Unused at present - unsigned char inactiveFlag[2]; // 140-141: Unused at present - unsigned char information1[TAGINFO_LEN]; // 142-161: Unused at present - unsigned char tagId[TAGID_LEN]; // 162-167: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced - unsigned char tagIdCRC[4]; // 168-171: CRC32 of tagId - unsigned char reserved1[44]; // 172-215: Reserved area not in use - unsigned char imageCRC[4]; // 216-219: CRC32 of images - unsigned char reserved2[16]; // 220-235: Unused at present - unsigned char headerCRC[4]; // 236-239: CRC32 of header excluding tagVersion - unsigned char reserved3[16]; // 240-255: Unused at present -}; - -struct bcm_tag_bc300 { - unsigned char tagVersion[TAGVER_LEN]; // 0-3: Version of the image tag - unsigned char sig_1[20]; // 4-23: Company Line 1 - unsigned char sig_2[14]; // 24-37: Company Line 2 - unsigned char chipid[6]; // 38-43: Chip this image is for - unsigned char boardid[16]; // 44-59: Board name - unsigned char big_endian[2]; // 60-61: Map endianness -- 1 BE 0 LE - unsigned char totalLength[IMAGE_LEN]; // 62-71: Total length of image - unsigned char cfeAddress[ADDRESS_LEN]; // 72-83: Address in memory of CFE - unsigned char cfeLength[IMAGE_LEN]; // 84-93: Size of CFE - unsigned char flashImageStart[ADDRESS_LEN]; // 94-105: Address in memory of kernel (start of image) - unsigned char flashRootLength[IMAGE_LEN]; // 106-115: Size of rootfs + deadcode (web flash uses this + kernelLength to determine the size of the kernel+rootfs flash image) - unsigned char kernelAddress[ADDRESS_LEN]; // 116-127: Address in memory of kernel - unsigned char kernelLength[IMAGE_LEN]; // 128-137: Size of kernel - unsigned char dualImage[2]; // 138-139: Unused at present - unsigned char inactiveFlag[2]; // 140-141: Unused at present - unsigned char information1[TAGINFO_LEN]; // 142-161: Unused at present - unsigned char tagId[TAGID_LEN]; // 162-167: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced - unsigned char tagIdCRC[4]; // 168-173: CRC32 to ensure validity of tagId - unsigned char rootAddress[ADDRESS_LEN]; // 174-183: Address in memory of rootfs partition - unsigned char rootLength[IMAGE_LEN]; // 184-193: Size of rootfs partition - unsigned char reserved1[22]; // 194-215: Reserved area not in use - unsigned char imageCRC[4]; // 216-219: CRC32 of images - unsigned char reserved2[16]; // 220-235: Unused at present - unsigned char headerCRC[4]; // 236-239: CRC32 of header excluding tagVersion - unsigned char reserved3[16]; // 240-255: Unused at present -}; - -struct bcm_tag_ag306 { - unsigned char tagVersion[TAGVER_LEN]; // 0-3: Version of the image tag - unsigned char sig_1[20]; // 4-23: Company Line 1 - unsigned char sig_2[14]; // 24-37: Company Line 2 - unsigned char chipid[6]; // 38-43: Chip this image is for - unsigned char boardid[16]; // 44-59: Board name - unsigned char big_endian[2]; // 60-61: Map endianness -- 1 BE 0 LE - unsigned char totalLength[IMAGE_LEN]; // 62-71: Total length of image - unsigned char cfeAddress[ADDRESS_LEN]; // 72-83: Address in memory of CFE - unsigned char cfeLength[IMAGE_LEN]; // 84-93: Size of CFE - unsigned char flashImageStart[ADDRESS_LEN]; // 94-105: Address in memory of kernel (start of image) - unsigned char flashRootLength[IMAGE_LEN]; // 106-115: Size of rootfs + deadcode (web flash uses this + kernelLength to determine the size of the kernel+rootfs flash image) - unsigned char kernelAddress[ADDRESS_LEN]; // 116-127: Address in memory of kernel - unsigned char kernelLength[IMAGE_LEN]; // 128-137: Size of kernel - unsigned char dualImage[2]; // 138-139: Unused at present - unsigned char inactiveFlag[2]; // 140-141: Unused at present - unsigned char information1[TAGINFO_LEN]; // 142-161: Unused at present - unsigned char information2[54]; // 162-215: Compilation and related information (not generated/used by OpenWRT) - unsigned char kernelCRC[4] ; // 216-219: CRC32 of images - unsigned char rootAddress[ADDRESS_LEN]; // 220-231: Address in memory of rootfs partition - unsigned char tagIdCRC[4]; // 232-235: Checksum to ensure validity of tagId - unsigned char headerCRC[4]; // 236-239: CRC32 of header excluding tagVersion - unsigned char rootLength[IMAGE_LEN]; // 240-249: Size of rootfs - unsigned char tagId[TAGID_LEN]; // 250-255: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced -}; - -struct bcm_tag_bc221 { - unsigned char tagVersion[TAGVER_LEN]; // 0-3: Version of the image tag - unsigned char sig_1[20]; // 4-23: Company Line 1 - unsigned char sig_2[14]; // 24-37: Company Line 2 - unsigned char chipid[6]; // 38-43: Chip this image is for - unsigned char boardid[16]; // 44-59: Board name - unsigned char big_endian[2]; // 60-61: Map endianness -- 1 BE 0 LE - unsigned char totalLength[IMAGE_LEN]; // 62-71: Total length of image - unsigned char cfeAddress[ADDRESS_LEN]; // 72-83: Address in memory of CFE - unsigned char cfeLength[IMAGE_LEN]; // 84-93: Size of CFE - unsigned char flashImageStart[ADDRESS_LEN]; // 94-105: Address in memory of kernel (start of image) - unsigned char flashRootLength[IMAGE_LEN]; // 106-115: Size of rootfs + deadcode (web flash uses this + kernelLength to determine the size of the kernel+rootfs flash image) - unsigned char kernelAddress[ADDRESS_LEN]; // 116-127: Address in memory of kernel - unsigned char kernelLength[IMAGE_LEN]; // 128-137: Size of kernel - unsigned char dualImage[2]; // 138-139: Unused at present - unsigned char inactiveFlag[2]; // 140-141: Unused at present - unsigned char rsa_signature[TAGINFO_LEN]; // 142-161: RSA Signature (unused at present; some vendors may use this) - unsigned char reserved5[2]; // 162-163: Unused at present - unsigned char tagId[TAGID_LEN]; // 164-169: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced - unsigned char rootAddress[ADDRESS_LEN]; // 170-181: Address in memory of rootfs partition - unsigned char rootLength[IMAGE_LEN]; // 182-191: Size of rootfs partition - unsigned char flashLayoutVer[4]; // 192-195: Version flash layout - unsigned char fskernelCRC[4]; // 196-199: Guessed to be kernel CRC - unsigned char reserved4[16]; // 200-215: Reserved area; unused at present - unsigned char imageCRC[4]; // 216-219: CRC32 of images - unsigned char reserved2[12]; // 220-231: Unused at present - unsigned char tagIdCRC[4]; // 232-235: CRC32 to ensure validity of tagId - unsigned char headerCRC[4]; // 236-239: CRC32 of header excluding tagVersion - unsigned char reserved3[16]; // 240-255: Unused at present -}; - -struct bcm_tag_bc310 { - unsigned char tagVersion[4]; // 0-3: Version of the image tag - unsigned char sig_1[20]; // 4-23: Company Line 1 - unsigned char sig_2[14]; // 24-37: Company Line 2 - unsigned char chipid[6]; // 38-43: Chip this image is for - unsigned char boardid[16]; // 44-59: Board name - unsigned char big_endian[2]; // 60-61: Map endianness -- 1 BE 0 LE - unsigned char totalLength[IMAGE_LEN]; // 62-71: Total length of image - unsigned char cfeAddress[ADDRESS_LEN]; // 72-83: Address in memory of CFE - unsigned char cfeLength[IMAGE_LEN]; // 84-93: Size of CFE - unsigned char flashImageStart[ADDRESS_LEN]; // 94-105: Address in memory of kernel (start of image) - unsigned char flashRootLength[IMAGE_LEN]; // 106-115: Size of rootfs + deadcode (web flash uses this + kernelLength to determine the size of the kernel+rootfs flash image) - unsigned char kernelAddress[ADDRESS_LEN]; // 116-127: Address in memory of kernel - unsigned char kernelLength[IMAGE_LEN]; // 128-137: Size of kernel - unsigned char dualImage[2]; // 138-139: Unused at present - unsigned char inactiveFlag[2]; // 140-141: Unused at present - unsigned char information1[TAGINFO_LEN]; // 142-161: Unused at present; Some vendors use this for optional information - unsigned char tagId[6]; // 162-167: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced - unsigned char tagIdCRC[4]; // 168-171: CRC32 to ensure validity of tagId - unsigned char rootAddress[ADDRESS_LEN]; // 172-183: Address in memory of rootfs partition - unsigned char rootLength[IMAGE_LEN]; // 184-193: Size of rootfs partition - unsigned char reserved1[22]; // 193-215: Reserved area not in use - unsigned char imageCRC[4]; // 216-219: CRC32 of images - unsigned char rootfsCRC[4]; // 220-227: CRC32 of rootfs partition - unsigned char kernelCRC[4]; // 224-227: CRC32 of kernel partition - unsigned char reserved2[8]; // 228-235: Unused at present - unsigned char headerCRC[4]; // 235-239: CRC32 of header excluding tagVersion - unsigned char reserved3[16]; // 240-255: Unused at present -}; - -union bcm_tag { - struct bcm_tag_bccfe bccfe; - struct bcm_tag_bc300 bc300; - struct bcm_tag_ag306 ag306; - struct bcm_tag_bc221 bc221; - struct bcm_tag_bc310 bc310; -}; - -#endif /* __BCM63XX_TAG_H */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/board_bcm963xx.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/board_bcm963xx.h deleted file mode 100644 index e5b916036f..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/board_bcm963xx.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef BOARD_BCM963XX_H_ -#define BOARD_BCM963XX_H_ - -#include <linux/types.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <bcm63xx_dev_enet.h> -#include <bcm63xx_dev_dsp.h> - -/* - * flash mapping - */ -#define BCM963XX_CFE_VERSION_OFFSET 0x570 -#define BCM963XX_NVRAM_OFFSET 0x580 - -/* - * nvram structure - */ -struct bcm963xx_nvram { - u32 version; - u8 reserved1[256]; - u8 name[16]; - u32 main_tp_number; - u32 psi_size; - u32 mac_addr_count; - u8 mac_addr_base[6]; - u8 reserved2[2]; - u32 checksum_old; - u8 reserved3[720]; - u32 checksum_high; -}; - -/* - * board definition - */ -struct board_info { - u8 name[16]; - unsigned int expected_cpu_id; - - /* enabled feature/device */ - unsigned int has_enet0:1; - unsigned int has_enet1:1; - unsigned int has_pci:1; - unsigned int has_pccard:1; - unsigned int has_ohci0:1; - unsigned int has_ehci0:1; - unsigned int has_udc0:1; - unsigned int has_dsp:1; - - /* ethernet config */ - struct bcm63xx_enet_platform_data enet0; - struct bcm63xx_enet_platform_data enet1; - - /* DSP config */ - struct bcm63xx_dsp_platform_data dsp; - - /* GPIO LEDs */ - struct gpio_led leds[8]; - - /* Reset button */ - struct gpio_button reset_buttons[1]; -}; - -#endif /* ! BOARD_BCM963XX_H_ */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h deleted file mode 100644 index 71742bac94..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H - -#include <bcm63xx_cpu.h> - -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -#define cpu_has_fpu 0 -#define cpu_has_32fpr 0 -#define cpu_has_counter 1 -#define cpu_has_watch 0 -#define cpu_has_divec 1 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 1 -#define cpu_has_ejtag 1 -#define cpu_has_llsc 1 -#define cpu_has_mips16 0 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 -#define cpu_has_vtag_icache 0 - -#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338) || defined(CONFIG_CPU_IS_BCM6345)) -#define cpu_has_dc_aliases 0 -#endif - -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_pindexed_dcache 0 - -#define cpu_has_mips32r1 1 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 0 -#define cpu_has_64bit_zero_reg 0 - -#define cpu_dcache_line_size() 16 -#define cpu_icache_line_size() 16 -#define cpu_scache_line_size() 0 - -#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/gpio.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/gpio.h deleted file mode 100644 index 7cda8c0a39..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/gpio.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H -#define __ASM_MIPS_MACH_BCM63XX_GPIO_H - -#include <bcm63xx_gpio.h> - -#define gpio_to_irq(gpio) NULL - -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value - -#define gpio_cansleep __gpio_cansleep - -#include <asm-generic/gpio.h> - -#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */ diff --git a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/war.h b/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/war.h deleted file mode 100644 index 8e3f3fdf32..0000000000 --- a/target/linux/brcm63xx/files-2.6.30/include/asm-mips/mach-bcm63xx/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H -#define __ASM_MIPS_MACH_BCM63XX_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */ |