bcm4710: port a missing part of the cache fixes to linux 2.6

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@5163 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 51 insertions, 33 deletions

diff --git a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
index 966382ad4f..d0487fb926 100644
--- a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
+++ b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
@@ -1,6 +1,6 @@
-diff -Nur linux-2.6.17/arch/mips/kernel/genex.S linux-2.6.17-owrt/arch/mips/kernel/genex.S
---- linux-2.6.17/arch/mips/kernel/genex.S	2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/arch/mips/kernel/genex.S	2006-06-18 15:36:58.000000000 +0200
+diff -ur linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
+--- linux.old/arch/mips/kernel/genex.S	2006-10-16 19:09:36.000000000 +0200
++++ linux.dev/arch/mips/kernel/genex.S	2006-10-16 19:06:50.000000000 +0200
 @@ -73,6 +73,10 @@
  	.set	push
  	.set	mips3
@@ -12,10 +12,10 @@ diff -Nur linux-2.6.17/arch/mips/kernel/genex.S linux-2.6.17-owrt/arch/mips/kern
  	mfc0	k1, CP0_CAUSE
  	li	k0, 31<<2
  	andi	k1, k1, 0x7c
-diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k.c
---- linux-2.6.17/arch/mips/mm/c-r4k.c	2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/arch/mips/mm/c-r4k.c	2006-06-18 15:36:58.000000000 +0200
-@@ -14,6 +14,12 @@
+diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
+--- linux.old/arch/mips/mm/c-r4k.c	2006-10-16 19:09:36.000000000 +0200
++++ linux.dev/arch/mips/mm/c-r4k.c	2006-10-16 19:08:46.000000000 +0200
+@@ -14,6 +14,15 @@
  #include <linux/mm.h>
  #include <linux/bitops.h>
  
@@ -23,12 +23,15 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
 +#include "../bcm947xx/include/typedefs.h"
 +#include "../bcm947xx/include/sbconfig.h"
 +#include "../bcm947xx/include/mipsinc.h"
++#undef MTC0
++#undef MFC0
++#undef cache_op
 +#include <asm/paccess.h>
 +#endif
  #include <asm/bcache.h>
  #include <asm/bootinfo.h>
  #include <asm/cache.h>
-@@ -30,6 +36,9 @@
+@@ -30,6 +39,9 @@
  #include <asm/cacheflush.h> /* for run_uncached() */
  
  
@@ -38,7 +41,7 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  /*
   * Special Variant of smp_call_function for use by cache functions:
   *
-@@ -94,7 +103,9 @@
+@@ -94,7 +106,9 @@
  {
  	unsigned long  dc_lsize = cpu_dcache_line_size();
  
@@ -49,7 +52,7 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  		r4k_blast_dcache_page = blast_dcache16_page;
  	else if (dc_lsize == 32)
  		r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
-@@ -106,7 +117,9 @@
+@@ -106,7 +120,9 @@
  {
  	unsigned long dc_lsize = cpu_dcache_line_size();
  
@@ -60,7 +63,7 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  		r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  	else if (dc_lsize == 32)
  		r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
-@@ -118,7 +131,9 @@
+@@ -118,7 +134,9 @@
  {
  	unsigned long dc_lsize = cpu_dcache_line_size();
  
@@ -71,7 +74,17 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  		r4k_blast_dcache = blast_dcache16;
  	else if (dc_lsize == 32)
  		r4k_blast_dcache = blast_dcache32;
-@@ -683,6 +698,8 @@
+@@ -527,6 +545,9 @@
+ 		r4k_blast_icache();
+ 	else
+ 		protected_blast_icache_range(start, end);
++
++	if (bcm4710)
++		r4k_flush_cache_all();
+ }
+ 
+ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
+@@ -683,6 +704,8 @@
  	unsigned long addr = (unsigned long) arg;
  
  	R4600_HIT_CACHEOP_WAR_IMPL;
@@ -80,7 +93,7 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
  	if (!cpu_icache_snoops_remote_store && scache_size)
  		protected_writeback_scache_line(addr & ~(sc_lsize - 1));
-@@ -1189,6 +1206,16 @@
+@@ -1189,6 +1212,16 @@
  static inline void coherency_setup(void)
  {
  	change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
@@ -97,7 +110,7 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  
  	/*
  	 * c0_status.cu=0 specifies that updates by the sc instruction use
-@@ -1227,6 +1254,15 @@
+@@ -1227,6 +1260,15 @@
  
  	/* Default cache error handler for R4000 and R5000 family */
  	set_uncached_handler (0x100, &except_vec2_generic, 0x80);
@@ -113,9 +126,9 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  
  	probe_pcache();
  	setup_scache();
-diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
---- linux-2.6.17/arch/mips/mm/tlbex.c	2006-06-18 15:34:19.000000000 +0200
-+++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c	2006-06-18 15:36:58.000000000 +0200
+diff -ur linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
+--- linux.old/arch/mips/mm/tlbex.c	2006-10-16 19:09:36.000000000 +0200
++++ linux.dev/arch/mips/mm/tlbex.c	2006-10-16 19:06:50.000000000 +0200
 @@ -38,6 +38,10 @@
  
  /* #define DEBUG_TLB */
@@ -140,9 +153,9 @@ diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex
  	/*
  	 * create the plain linear handler
  	 */
-diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm-mips/r4kcache.h
---- linux-2.6.17/include/asm-mips/r4kcache.h	2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/include/asm-mips/r4kcache.h	2006-06-18 15:56:57.000000000 +0200
+diff -ur linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
+--- linux.old/include/asm-mips/r4kcache.h	2006-10-16 19:09:36.000000000 +0200
++++ linux.dev/include/asm-mips/r4kcache.h	2006-10-16 19:09:11.000000000 +0200
 @@ -17,6 +17,18 @@
  #include <asm/cpu-features.h>
  #include <asm/mipsmtregs.h>
@@ -281,7 +294,7 @@ diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm
  	__##pfx##flush_prologue						\
  									\
  	for (ws = 0; ws < ws_end; ws += ws_inc)				\
-@@ -393,24 +458,25 @@
+@@ -393,28 +458,30 @@
  	__##pfx##flush_epilogue						\
  }
  
@@ -306,7 +319,7 @@ diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm
  
  /* build blast_xxx_range, protected_blast_xxx_range */
 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war) \
++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
  static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
  						    unsigned long end)	\
  {									\
@@ -317,7 +330,12 @@ diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm
  									\
  	__##pfx##flush_prologue						\
  									\
-@@ -424,13 +490,13 @@
+ 	while (1) {							\
++		war2						\
+ 		prot##cache_op(hitop, addr);				\
+ 		if (addr == aend)					\
+ 			break;						\
+@@ -424,13 +491,13 @@
  	__##pfx##flush_epilogue						\
  }
  
@@ -326,21 +344,21 @@ diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm
 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
  /* blast_inv_dcache_range */
 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
  
  #endif /* _ASM_R4KCACHE_H */
-diff -Nur linux-2.6.17/include/asm-mips/stackframe.h linux-2.6.17-owrt/include/asm-mips/stackframe.h
---- linux-2.6.17/include/asm-mips/stackframe.h	2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/include/asm-mips/stackframe.h	2006-06-18 15:36:58.000000000 +0200
+diff -ur linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
+--- linux.old/include/asm-mips/stackframe.h	2006-10-16 19:09:36.000000000 +0200
++++ linux.dev/include/asm-mips/stackframe.h	2006-10-16 19:06:50.000000000 +0200
 @@ -361,6 +361,10 @@
  		.macro	RESTORE_SP_AND_RET
  		LONG_L	sp, PT_R29(sp)