[lantiq]

* backport 2.6.8 patches to .39 / .32.33
* remove lqtapi
* bump tapi/dsl to .39
* migrate to new ltq_ style api
* add amazon_se support

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27026 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 0 insertions, 33 deletions

diff --git a/target/linux/lantiq/patches/010-mips_clocksource_init_war.patch b/target/linux/lantiq/patches/010-mips_clocksource_init_war.patch
deleted file mode 100644
index 1670ccb8d8..0000000000
--- a/target/linux/lantiq/patches/010-mips_clocksource_init_war.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -23,6 +23,22 @@
- 
- #ifndef CONFIG_MIPS_MT_SMTC
- 
-+/*
-+ * Compare interrupt can be routed and latched outside the core,
-+ * so a single execution hazard barrier may not be enough to give
-+ * it time to clear as seen in the Cause register.  4 time the
-+ * pipeline depth seems reasonably conservative, and empirically
-+ * works better in configurations with high CPU/bus clock ratios.
-+ */
-+
-+#define compare_change_hazard() \
-+	do { \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+	} while (0)
-+
- static int mips_next_event(unsigned long delta,
-                            struct clock_event_device *evt)
- {
-@@ -32,6 +48,7 @@
- 	cnt = read_c0_count();
- 	cnt += delta;
- 	write_c0_compare(cnt);
-+	compare_change_hazard();
- 	res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
- 	return res;
- }