initial merge of danube, pci is still broken and the new dma code still needs to be tested, before the merge

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9704 3c298f89-4303-0410-b956-a3cf2f4a3e73

3 files changed, 1235 insertions, 0 deletions

diff --git a/target/linux/danube/files/drivers/mtd/maps/danube.c b/target/linux/danube/files/drivers/mtd/maps/danube.c
new file mode 100644
index 0000000000..25e9df3de8
--- /dev/null
+++ b/target/linux/danube/files/drivers/mtd/maps/danube.c
@@ -0,0 +1,194 @@
+/*
+ *  Driver for DANUBE flashmap 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <asm/io.h>
+
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/cfi.h>
+#include <asm/danube/danube.h>
+#include <linux/magic.h>
+
+static struct map_info
+danube_map = {
+	.name = "DANUBE_FLASH",
+	.bankwidth = 2,
+	.size = 0x400000,
+};
+
+static map_word
+danube_read16 (struct map_info * map, unsigned long adr)
+{
+	map_word temp;
+
+	adr ^= 2;
+	temp.x[0] = *((__u16 *) (map->virt + adr));
+
+	return temp;
+}
+
+static void
+danube_write16 (struct map_info *map, map_word d, unsigned long adr)
+{
+	adr ^= 2;
+	*((__u16 *) (map->virt + adr)) = d.x[0];
+}
+
+void
+danube_copy_from (struct map_info *map, void *to, unsigned long from, ssize_t len)
+{
+	u8 *p;
+	u8 *to_8;
+
+	from = (unsigned long) (from + map->virt);
+	p = (u8 *) from;
+	to_8 = (u8 *) to;
+	while(len--){
+		*to_8++ = *p++;
+	}
+}
+
+void
+danube_copy_to (struct map_info *map, unsigned long to, const void *from, ssize_t len)
+{
+	u8 *p =  (u8*) from;
+	u8 *to_8;
+
+	to += (unsigned long) map->virt;
+	to_8 = (u8*)to;
+	while(len--){
+		*p++ = *to_8++;
+	}
+}
+
+static struct mtd_partition
+danube_partitions[4] = {
+	{
+		name:"U-Boot",
+		offset:0x00000000,
+		size:0x00020000,
+	},
+	{
+		name:"U-Boot-Env",
+		offset:0x00020000,
+		size:0x00010000,
+	},
+	{
+		name:"kernel",
+		offset:0x00030000,
+		size:0x0,
+	},
+	{
+		name:"rootfs",
+		offset:0x0,
+		size:0x0,
+	},
+};
+
+#define DANUBE_FLASH_START		0x10000000
+#define DANUBE_FLASH_MAX		0x2000000
+
+int
+find_uImage_size (unsigned long start_offset){
+	unsigned long temp;
+
+	danube_copy_from(&danube_map, &temp, start_offset + 12, 4);
+	printk("kernel size is %ld \n", temp + 0x40);
+	return temp + 0x40;
+}
+
+int
+detect_squashfs_partition (unsigned long start_offset){
+	unsigned long temp;
+
+	danube_copy_from(&danube_map, &temp, start_offset, 4);
+
+	return (temp == SQUASHFS_MAGIC);
+}
+
+int __init
+init_danube_mtd (void)
+{
+	struct mtd_info *danube_mtd = NULL;
+	struct mtd_partition *parts = NULL;
+	unsigned long uimage_size;
+
+	writel(0x1d7ff, DANUBE_EBU_BUSCON0);
+
+	danube_map.read = danube_read16;
+	danube_map.write = danube_write16;
+	danube_map.copy_from = danube_copy_from;
+	danube_map.copy_to = danube_copy_to;
+
+	danube_map.phys = DANUBE_FLASH_START;
+	danube_map.virt = ioremap_nocache(DANUBE_FLASH_START, DANUBE_FLASH_MAX);
+	danube_map.size = DANUBE_FLASH_MAX;
+	if (!danube_map.virt) {
+		printk(KERN_WARNING "Failed to ioremap!\n");
+		return -EIO;
+	}
+
+	danube_mtd = (struct mtd_info *) do_map_probe("cfi_probe", &danube_map);
+	if (!danube_mtd) {
+		iounmap(danube_map.virt);
+		printk("probing failed\n");
+		return -ENXIO;
+	}
+
+	danube_mtd->owner = THIS_MODULE;
+
+	uimage_size = find_uImage_size(danube_partitions[2].offset);
+
+	if(detect_squashfs_partition(danube_partitions[2].offset + uimage_size)){
+		printk("Found a squashfs following the uImage\n");
+	} else {
+		uimage_size &= ~0xffff;
+		uimage_size += 0x10000;
+	}
+
+	danube_partitions[2].size = uimage_size;
+	danube_partitions[3].offset = danube_partitions[2].offset + danube_partitions[2].size;
+	danube_partitions[3].size = ((danube_mtd->size >> 20) * 1024 * 1024) - danube_partitions[3].offset;
+
+	parts = &danube_partitions[0];
+	add_mtd_partitions(danube_mtd, parts, 4);
+
+	printk("Added danube flash with %dMB\n", danube_mtd->size >> 20);
+	return 0;
+}
+
+static void
+__exit
+cleanup_danube_mtd (void)
+{
+}
+
+module_init (init_danube_mtd);
+module_exit (cleanup_danube_mtd);
+
+MODULE_LICENSE ("GPL");
+MODULE_AUTHOR ("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION ("MTD map driver for DANUBE boards");
diff --git a/target/linux/danube/files/drivers/net/danube_mii0.c b/target/linux/danube/files/drivers/net/danube_mii0.c
new file mode 100644
index 0000000000..63a7febbf6
--- /dev/null
+++ b/target/linux/danube/files/drivers/net/danube_mii0.c
@@ -0,0 +1,433 @@
+/*
+ *   drivers/net/danube_mii0.c
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 Infineon
+ *
+ *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   software and hardware
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <asm/uaccess.h>
+#include <linux/in.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/skbuff.h>
+#include <linux/mm.h>
+#include <linux/ethtool.h>
+#include <asm/checksum.h>
+#include <linux/init.h>
+#include <asm/delay.h>
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_mii0.h>
+#include <asm/danube/danube_dma.h>
+
+static struct net_device danube_mii0_dev;
+static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
+
+void
+danube_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
+{
+	u32 val = MDIO_ACC_REQUEST |
+		((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
+		((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
+		phy_data;
+
+	while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
+	writel(val, DANUBE_PPE32_MDIO_ACC);
+}
+
+unsigned short
+danube_read_mdio (u32 phy_addr, u32 phy_reg)
+{
+	u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
+		((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
+		((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
+
+	writel(val, DANUBE_PPE32_MDIO_ACC);
+	while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
+	val = readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
+
+	return val;
+}
+
+int
+danube_switch_open (struct net_device *dev)
+{
+	struct switch_priv* priv = (struct switch_priv*)dev->priv;
+	struct dma_device_info* dma_dev = priv->dma_device;
+	int i;
+
+	for (i = 0; i < dma_dev->max_rx_chan_num; i++)
+	{
+		if ((dma_dev->rx_chan[i])->control == DANUBE_DMA_CH_ON)
+			(dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
+	}
+
+	netif_start_queue(dev);
+
+	return 0;
+}
+
+int
+switch_release (struct net_device *dev){
+	struct switch_priv* priv = (struct switch_priv*)dev->priv;
+	struct dma_device_info* dma_dev = priv->dma_device;
+	int i;
+
+	for (i = 0; i < dma_dev->max_rx_chan_num; i++)
+		dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
+
+	netif_stop_queue(dev);
+
+	return 0;
+}
+
+int
+switch_hw_receive (struct net_device* dev,struct dma_device_info* dma_dev)
+{
+	struct switch_priv *priv = (struct switch_priv*)dev->priv;
+	unsigned char* buf = NULL;
+	struct sk_buff *skb = NULL;
+	int len = 0;
+
+	len = dma_device_read(dma_dev, &buf, (void**)&skb);
+
+	if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
+	{
+		printk("packet too large %d\n",len);
+		goto switch_hw_receive_err_exit;
+	}
+
+	/* remove CRC */
+	len -= 4;
+	if (skb == NULL )
+	{
+		printk("cannot restore pointer\n");
+		goto switch_hw_receive_err_exit;
+	}
+
+	if (len > (skb->end - skb->tail))
+	{
+		printk("BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail);
+		goto switch_hw_receive_err_exit;
+	}
+
+	skb_put(skb, len);
+	skb->dev = dev;
+	skb->protocol = eth_type_trans(skb, dev);
+	netif_rx(skb);
+
+	priv->stats.rx_packets++;
+	priv->stats.rx_bytes += len;
+
+	return 0;
+
+switch_hw_receive_err_exit:
+	if (len == 0)
+	{
+		if(skb)
+			dev_kfree_skb_any(skb);
+		priv->stats.rx_errors++;
+		priv->stats.rx_dropped++;
+
+		return -EIO;
+	} else {
+		return len;
+	}
+}
+
+int
+switch_hw_tx (char *buf, int len, struct net_device *dev)
+{
+	int ret = 0;
+	struct switch_priv *priv = dev->priv;
+	struct dma_device_info* dma_dev = priv->dma_device;
+
+	ret = dma_device_write(dma_dev, buf, len, priv->skb);
+
+	return ret;
+}
+
+int
+switch_tx (struct sk_buff *skb, struct net_device *dev)
+{
+	int len;
+	char *data;
+	struct switch_priv *priv = dev->priv;
+	struct dma_device_info* dma_dev = priv->dma_device;
+
+	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+	data = skb->data;
+	priv->skb = skb;
+	dev->trans_start = jiffies;
+	// TODO we got more than 1 dma channel, so we should do something intelligent
+	// here to select one
+	dma_dev->current_tx_chan = 0;
+
+	wmb();
+
+	if (switch_hw_tx(data, len, dev) != len)
+	{
+		dev_kfree_skb_any(skb);
+		priv->stats.tx_errors++;
+		priv->stats.tx_dropped++;
+	} else {
+		priv->stats.tx_packets++;
+		priv->stats.tx_bytes+=len;
+	}
+
+	return 0;
+}
+
+void
+switch_tx_timeout (struct net_device *dev)
+{
+	int i;
+	struct switch_priv* priv = (struct switch_priv*)dev->priv;
+
+	priv->stats.tx_errors++;
+
+	for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
+	{
+		priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
+	}
+
+	netif_wake_queue(dev);
+
+	return;
+}
+
+int
+dma_intr_handler (struct dma_device_info* dma_dev, int status)
+{
+	int i;
+
+	switch (status)
+	{
+	case RCV_INT:
+		switch_hw_receive(&danube_mii0_dev, dma_dev);
+		break;
+
+	case TX_BUF_FULL_INT:
+		printk("tx buffer full\n");
+		netif_stop_queue(&danube_mii0_dev);
+		for (i = 0; i < dma_dev->max_tx_chan_num; i++)
+		{
+			if ((dma_dev->tx_chan[i])->control==DANUBE_DMA_CH_ON)
+				dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
+		}
+		break;
+
+	case TRANSMIT_CPT_INT:
+		for (i = 0; i < dma_dev->max_tx_chan_num; i++)
+			dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
+
+		netif_wake_queue(&danube_mii0_dev);
+		break;
+	}
+
+	return 0;
+}
+
+unsigned char*
+danube_etop_dma_buffer_alloc (int len, int *byte_offset, void **opt)
+{
+	unsigned char *buffer = NULL;
+	struct sk_buff *skb = NULL;
+
+	skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
+	if (skb == NULL)
+		return NULL;
+
+	buffer = (unsigned char*)(skb->data);
+	skb_reserve(skb, 2);
+	*(int*)opt = (int)skb;
+	*byte_offset = 2;
+
+	return buffer;
+}
+
+void
+danube_etop_dma_buffer_free (unsigned char *dataptr, void *opt)
+{
+	struct sk_buff *skb = NULL;
+
+	if(opt == NULL)
+	{
+		kfree(dataptr);
+	} else {
+		skb = (struct sk_buff*)opt;
+		dev_kfree_skb_any(skb);
+	}
+}
+
+static struct net_device_stats*
+danube_get_stats (struct net_device *dev)
+{
+	return (struct net_device_stats *)dev->priv;
+}
+
+static int
+switch_init (struct net_device *dev)
+{
+	u64 retval = 0;
+	int i;
+	struct switch_priv *priv;
+
+	ether_setup(dev);
+
+	printk("%s up\n", dev->name);
+
+	dev->open = danube_switch_open;
+	dev->stop = switch_release;
+	dev->hard_start_xmit = switch_tx;
+	dev->get_stats = danube_get_stats;
+	dev->tx_timeout = switch_tx_timeout;
+	dev->watchdog_timeo = 10 * HZ;
+	dev->priv = kmalloc(sizeof(struct switch_priv), GFP_KERNEL);
+
+	if (dev->priv == NULL)
+		return -ENOMEM;
+
+	memset(dev->priv, 0, sizeof(struct switch_priv));
+	priv = dev->priv;
+
+	priv->dma_device = dma_device_reserve("PPE");
+
+	if (!priv->dma_device){
+		BUG();
+		return -ENODEV;
+	}
+
+	priv->dma_device->buffer_alloc = &danube_etop_dma_buffer_alloc;
+	priv->dma_device->buffer_free = &danube_etop_dma_buffer_free;
+	priv->dma_device->intr_handler = &dma_intr_handler;
+	priv->dma_device->max_rx_chan_num = 4;
+
+	for (i = 0; i < priv->dma_device->max_rx_chan_num; i++)
+	{
+		priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
+		priv->dma_device->rx_chan[i]->control = DANUBE_DMA_CH_ON;
+	}
+
+	for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
+	{
+		if(i == 0)
+			priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_ON;
+		else
+			priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_OFF;
+	}
+
+	dma_device_register(priv->dma_device);
+
+	/*read the mac address from the mac table and put them into the mac table.*/
+	for (i = 0; i < 6; i++)
+	{
+		retval += u_boot_ethaddr[i];
+	}
+
+	//TODO
+	/* ethaddr not set in u-boot ? */
+	if (retval == 0)
+	{
+		printk("use default MAC address\n");
+		dev->dev_addr[0] = 0x00;
+		dev->dev_addr[1] = 0x11;
+		dev->dev_addr[2] = 0x22;
+		dev->dev_addr[3] = 0x33;
+		dev->dev_addr[4] = 0x44;
+		dev->dev_addr[5] = 0x55;
+	} else {
+		for (i = 0; i < 6; i++)
+			dev->dev_addr[i] = u_boot_ethaddr[i];
+	}
+
+	return 0;
+}
+
+static void
+danube_sw_chip_init (int mode)
+{
+	writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_DMA, DANUBE_PMU_PWDCR);
+	writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_PPE, DANUBE_PMU_PWDCR);
+	wmb();
+
+	if(mode == REV_MII_MODE)
+		writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, DANUBE_PPE32_CFG);
+	else if(mode == MII_MODE)
+		writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, DANUBE_PPE32_CFG);
+
+	writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, DANUBE_PPE32_IG_PLEN_CTRL);
+
+	writel(PPE32_CGEN, DANUBE_PPE32_ENET_MAC_CFG);
+
+	wmb();
+}
+
+int __init
+switch_init_module(void)
+{
+	int result = 0;
+
+	danube_mii0_dev.init = switch_init;
+
+	strcpy(danube_mii0_dev.name, "eth%d");
+	SET_MODULE_OWNER(dev);
+
+	result = register_netdev(&danube_mii0_dev);
+	if (result)
+	{
+		printk("error %i registering device \"%s\"\n", result, danube_mii0_dev.name);
+		goto out;
+	}
+
+	/* danube eval kit connects the phy/switch in REV mode */
+	danube_sw_chip_init(REV_MII_MODE);
+	printk("danube MAC driver loaded!\n");
+
+out:
+	return result;
+}
+
+static void __exit
+switch_cleanup(void)
+{
+	struct switch_priv *priv = (struct switch_priv*)danube_mii0_dev.priv;
+
+	printk("danube_mii0 cleanup\n");
+
+	dma_device_unregister(priv->dma_device);
+	dma_device_release(priv->dma_device);
+	kfree(priv->dma_device);
+	kfree(danube_mii0_dev.priv);
+	unregister_netdev(&danube_mii0_dev);
+
+	return;
+}
+
+module_init(switch_init_module);
+module_exit(switch_cleanup);
diff --git a/target/linux/danube/files/drivers/serial/danube_asc.c b/target/linux/danube/files/drivers/serial/danube_asc.c
new file mode 100644
index 0000000000..b50b1e7bee
--- /dev/null
+++ b/target/linux/danube/files/drivers/serial/danube_asc.c
@@ -0,0 +1,608 @@
+/*
+ *  Driver for DANUBEASC serial ports
+ *
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Copyright (C) 2004 Infineon IFAP DC COM CPE
+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/major.h>
+#include <linux/string.h>
+#include <linux/fcntl.h>
+#include <linux/ptrace.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/circ_buf.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/irq.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/bitops.h>
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_irq.h>
+#include <asm/danube/danube_serial.h>
+
+#define PORT_DANUBEASC  111
+
+#include <linux/serial_core.h>
+
+#define UART_DUMMY_UER_RX 1
+
+static void danubeasc_tx_chars(struct uart_port *port);
+extern void prom_printf(const char * fmt, ...);
+static struct uart_port danubeasc_port;
+static struct uart_driver danubeasc_reg;
+static unsigned int uartclk = 0;
+extern unsigned int danube_get_fpi_hz(void);
+
+static void
+danubeasc_stop_tx (struct uart_port *port)
+{
+	/* fifo underrun shuts up after firing once */
+	return;
+}
+
+static void
+danubeasc_start_tx (struct uart_port *port)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	danubeasc_tx_chars(port);
+	local_irq_restore(flags);
+
+	return;
+}
+
+static void
+danubeasc_stop_rx (struct uart_port *port)
+{
+	/* clear the RX enable bit */
+	writel(ASCWHBSTATE_CLRREN, DANUBE_ASC1_WHBSTATE);
+}
+
+static void
+danubeasc_enable_ms (struct uart_port *port)
+{
+	/* no modem signals */
+	return;
+}
+
+static void
+danubeasc_rx_chars (struct uart_port *port)
+{
+	struct tty_struct *tty = port->info->tty;
+	unsigned int ch = 0, rsr = 0, fifocnt;
+
+	fifocnt = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
+	while (fifocnt--)
+	{
+		u8 flag = TTY_NORMAL;
+		ch = readl(DANUBE_ASC1_RBUF);
+		rsr = (readl(DANUBE_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
+		tty_flip_buffer_push(tty);
+		port->icount.rx++;
+
+		/*
+		 * Note that the error handling code is
+		 * out of the main execution path
+		 */
+		if (rsr & ASCSTATE_ANY) {
+			if (rsr & ASCSTATE_PE) {
+				port->icount.parity++;
+				writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, DANUBE_ASC1_WHBSTATE);
+			} else if (rsr & ASCSTATE_FE) {
+				port->icount.frame++;
+				writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, DANUBE_ASC1_WHBSTATE);
+			}
+			if (rsr & ASCSTATE_ROE) {
+				port->icount.overrun++;
+				writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
+			}
+
+			rsr &= port->read_status_mask;
+
+			if (rsr & ASCSTATE_PE)
+				flag = TTY_PARITY;
+			else if (rsr & ASCSTATE_FE)
+				flag = TTY_FRAME;
+		}
+
+		if ((rsr & port->ignore_status_mask) == 0)
+			tty_insert_flip_char(tty, ch, flag);
+
+		if (rsr & ASCSTATE_ROE)
+			/*
+			 * Overrun is special, since it's reported
+			 * immediately, and doesn't affect the current
+			 * character
+			 */
+			tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+	}
+	if (ch != 0)
+		tty_flip_buffer_push(tty);
+
+	return;
+}
+
+
+static void
+danubeasc_tx_chars (struct uart_port *port)
+{
+	struct circ_buf *xmit = &port->info->xmit;
+
+	if (uart_tx_stopped(port)) {
+		danubeasc_stop_tx(port);
+		return;
+	}
+
+	while(((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+			        >> ASCFSTAT_TXFFLOFF) != DANUBEASC_TXFIFO_FULL)
+	{
+		if (port->x_char) {
+			writel(port->x_char, DANUBE_ASC1_TBUF);
+			port->icount.tx++;
+			port->x_char = 0;
+			continue;
+		}
+
+		if (uart_circ_empty(xmit))
+			break;
+
+		writel(port->info->xmit.buf[port->info->xmit.tail], DANUBE_ASC1_TBUF);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		port->icount.tx++;
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+}
+
+static irqreturn_t
+danubeasc_tx_int (int irq, void *port)
+{
+	writel(ASC_IRNCR_TIR, DANUBE_ASC1_IRNCR);
+	danubeasc_start_tx(port);
+	mask_and_ack_danube_irq(irq);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t
+danubeasc_er_int (int irq, void *port)
+{
+	/* clear any pending interrupts */
+	writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
+			ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t
+danubeasc_rx_int (int irq, void *port)
+{
+	writel(ASC_IRNCR_RIR, DANUBE_ASC1_IRNCR);
+	danubeasc_rx_chars((struct uart_port *) port);
+	mask_and_ack_danube_irq(irq);
+
+	return IRQ_HANDLED;
+}
+
+static unsigned int
+danubeasc_tx_empty (struct uart_port *port)
+{
+	int status;
+
+	status = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
+
+	return status ? 0 : TIOCSER_TEMT;
+}
+
+static unsigned int
+danubeasc_get_mctrl (struct uart_port *port)
+{
+	return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
+}
+
+static void
+danubeasc_set_mctrl (struct uart_port *port, u_int mctrl)
+{
+	return;
+}
+
+static void
+danubeasc_break_ctl (struct uart_port *port, int break_state)
+{
+	return;
+}
+
+static void
+danubeasc1_hw_init (void)
+{
+	/* this setup was probably already done in ROM/u-boot  but we do it again*/
+	/* TODO: GPIO pins are multifunction */
+	writel(readl(DANUBE_ASC1_CLC) & ~DANUBE_ASC1_CLC_DISS, DANUBE_ASC1_CLC);
+	writel((readl(DANUBE_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), DANUBE_ASC1_CLC);
+	writel(0, DANUBE_ASC1_PISEL);
+	writel(((DANUBEASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
+		ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
+	writel(((DANUBEASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
+		ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
+	wmb ();
+
+	/*framing, overrun, enable */
+	writel(readl(DANUBE_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
+		DANUBE_ASC1_CON);
+}
+
+static int
+danubeasc_startup (struct uart_port *port)
+{
+	unsigned long flags;
+	int retval;
+
+	/* this assumes: CON.BRS = CON.FDE = 0 */
+	if (uartclk == 0)
+		uartclk = danube_get_fpi_hz();
+
+	danubeasc_port.uartclk = uartclk;
+
+	danubeasc1_hw_init();
+
+	local_irq_save(flags);
+
+	retval = request_irq(DANUBEASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
+	if (retval){
+		printk("failed to request danubeasc_rx_int\n");
+		return retval;
+	}
+
+	retval = request_irq(DANUBEASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
+	if (retval){
+		printk("failed to request danubeasc_tx_int\n");
+		goto err1;
+	}
+
+	retval = request_irq(DANUBEASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
+	if (retval){
+		printk("failed to request danubeasc_er_int\n");
+		goto err2;
+	}
+
+	writel(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
+		DANUBE_ASC1_IRNREN);
+
+	local_irq_restore(flags);
+
+	return 0;
+
+err2:
+	free_irq(DANUBEASC1_TIR, port);
+
+err1:
+	free_irq(DANUBEASC1_RIR, port);
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static void
+danubeasc_shutdown (struct uart_port *port)
+{
+	free_irq(DANUBEASC1_RIR, port);
+	free_irq(DANUBEASC1_TIR, port);
+	free_irq(DANUBEASC1_EIR, port);
+	/*
+	 * disable the baudrate generator to disable the ASC
+	 */
+	writel(0, DANUBE_ASC1_CON);
+
+	/* flush and then disable the fifos */
+	writel(readl(DANUBE_ASC1_RXFCON) | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
+	writel(readl(DANUBE_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, DANUBE_ASC1_RXFCON);
+	writel(readl(DANUBE_ASC1_TXFCON) | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
+	writel(readl(DANUBE_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, DANUBE_ASC1_TXFCON);
+}
+
+static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
+{
+	unsigned int cflag;
+	unsigned int iflag;
+	unsigned int quot;
+	unsigned int baud;
+	unsigned int con = 0;
+	unsigned long flags;
+
+	cflag = new->c_cflag;
+	iflag = new->c_iflag;
+
+	/* byte size and parity */
+	switch (cflag & CSIZE) {
+	case CS7:
+		con = ASCCON_M_7ASYNC;
+		break;
+
+	case CS5:
+	case CS6:
+	default:
+		con = ASCCON_M_8ASYNC;
+		break;
+	}
+
+	if (cflag & CSTOPB)
+		con |= ASCCON_STP;
+
+	if (cflag & PARENB) {
+		if (!(cflag & PARODD))
+			con &= ~ASCCON_ODD;
+		else
+			con |= ASCCON_ODD;
+	}
+
+	port->read_status_mask = ASCSTATE_ROE;
+	if (iflag & INPCK)
+		port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
+
+	port->ignore_status_mask = 0;
+	if (iflag & IGNPAR)
+		port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
+
+	if (iflag & IGNBRK) {
+		/*
+		 * If we're ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support).
+		 */
+		if (iflag & IGNPAR)
+			port->ignore_status_mask |= ASCSTATE_ROE;
+	}
+
+	if ((cflag & CREAD) == 0)
+		port->ignore_status_mask |= UART_DUMMY_UER_RX;
+
+	/* set error signals  - framing, parity  and overrun, enable receiver */
+	con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
+
+	local_irq_save(flags);
+
+	/* set up CON */
+	writel(readl(DANUBE_ASC1_CON) | con, DANUBE_ASC1_CON);
+
+	/* Set baud rate - take a divider of 2 into account */
+    baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
+	quot = uart_get_divisor(port, baud);
+	quot = quot / 2 - 1;
+
+	/* disable the baudrate generator */
+	writel(readl(DANUBE_ASC1_CON) & ~ASCCON_R, DANUBE_ASC1_CON);
+
+	/* make sure the fractional divider is off */
+	writel(readl(DANUBE_ASC1_CON) & ~ASCCON_FDE, DANUBE_ASC1_CON);
+
+	/* set up to use divisor of 2 */
+	writel(readl(DANUBE_ASC1_CON) & ~ASCCON_BRS, DANUBE_ASC1_CON);
+
+	/* now we can write the new baudrate into the register */
+	writel(quot, DANUBE_ASC1_BG);
+
+	/* turn the baudrate generator back on */
+	writel(readl(DANUBE_ASC1_CON) | ASCCON_R, DANUBE_ASC1_CON);
+
+	/* enable rx */
+	writel(ASCWHBSTATE_SETREN, DANUBE_ASC1_WHBSTATE);
+
+	local_irq_restore(flags);
+}
+
+static const char*
+danubeasc_type (struct uart_port *port)
+{
+	return port->type == PORT_DANUBEASC ? "DANUBEASC" : NULL;
+}
+
+static void
+danubeasc_release_port (struct uart_port *port)
+{
+	return;
+}
+
+static int
+danubeasc_request_port (struct uart_port *port)
+{
+	return 0;
+}
+
+static void
+danubeasc_config_port (struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE) {
+		port->type = PORT_DANUBEASC;
+		danubeasc_request_port(port);
+	}
+}
+
+static int
+danubeasc_verify_port (struct uart_port *port, struct serial_struct *ser)
+{
+	int ret = 0;
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_DANUBEASC)
+		ret = -EINVAL;
+	if (ser->irq < 0 || ser->irq >= NR_IRQS)
+		ret = -EINVAL;
+	if (ser->baud_base < 9600)
+		ret = -EINVAL;
+	return ret;
+}
+
+static struct uart_ops danubeasc_pops = {
+	.tx_empty =		danubeasc_tx_empty,
+	.set_mctrl =	danubeasc_set_mctrl,
+	.get_mctrl =	danubeasc_get_mctrl,
+	.stop_tx =		danubeasc_stop_tx,
+	.start_tx =		danubeasc_start_tx,
+	.stop_rx =		danubeasc_stop_rx,
+	.enable_ms =	danubeasc_enable_ms,
+	.break_ctl =	danubeasc_break_ctl,
+	.startup =		danubeasc_startup,
+	.shutdown =		danubeasc_shutdown,
+	.set_termios =	danubeasc_set_termios,
+	.type =			danubeasc_type,
+	.release_port =	danubeasc_release_port,
+	.request_port =	danubeasc_request_port,
+	.config_port =	danubeasc_config_port,
+	.verify_port =	danubeasc_verify_port,
+};
+
+static struct uart_port danubeasc_port = {
+		membase:	(void *)DANUBE_ASC1_BASE_ADDR,
+		mapbase:	DANUBE_ASC1_BASE_ADDR,
+		iotype:		SERIAL_IO_MEM,
+		irq:		DANUBEASC1_RIR,
+		uartclk:	0,
+		fifosize:	16,
+		unused:		{DANUBEASC1_TIR, DANUBEASC1_EIR},
+		type:		PORT_DANUBEASC,
+		ops:		&danubeasc_pops,
+		flags:		ASYNC_BOOT_AUTOCONF,
+};
+
+static void
+danubeasc_console_write (struct console *co, const char *s, u_int count)
+{
+	int i, fifocnt;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	for (i = 0; i < count; i++)
+	{
+		/* wait until the FIFO is not full */
+		do
+		{
+			fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+			                >> ASCFSTAT_TXFFLOFF;
+		} while (fifocnt == DANUBEASC_TXFIFO_FULL);
+
+		if (s[i] == '\0')
+		{
+			break;
+		}
+
+		if (s[i] == '\n')
+		{
+			writel('\r', DANUBE_ASC1_TBUF);
+			do
+			{
+				fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+					>> ASCFSTAT_TXFFLOFF;
+			} while (fifocnt == DANUBEASC_TXFIFO_FULL);
+		}
+		writel(s[i], DANUBE_ASC1_TBUF);
+	}
+
+	local_irq_restore(flags);
+}
+
+static int __init
+danubeasc_console_setup (struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	if (uartclk == 0)
+		uartclk = danube_get_fpi_hz();
+	co->index = 0;
+	port = &danubeasc_port;
+	danubeasc_port.uartclk = uartclk;
+	danubeasc_port.type = PORT_DANUBEASC;
+
+	if (options){
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	}
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver danubeasc_reg;
+static struct console danubeasc_console = {
+	name:		"ttyS",
+	write:		danubeasc_console_write,
+	device:		uart_console_device,
+	setup:		danubeasc_console_setup,
+	flags:		CON_PRINTBUFFER,
+	index:		-1,
+	data:		&danubeasc_reg,
+};
+
+static int __init
+danubeasc_console_init (void)
+{
+	register_console(&danubeasc_console);
+	return 0;
+}
+console_initcall(danubeasc_console_init);
+
+static struct uart_driver danubeasc_reg = {
+	.owner =			THIS_MODULE,
+	.driver_name =		"serial",
+	.dev_name =			"ttyS",
+	.major =			TTY_MAJOR,
+	.minor =			64,
+	.nr =				1,
+	.cons =				&danubeasc_console,
+};
+
+static int __init
+danubeasc_init (void)
+{
+	unsigned char res;
+
+	uart_register_driver(&danubeasc_reg);
+	res = uart_add_one_port(&danubeasc_reg, &danubeasc_port);
+
+	return res;
+}
+
+static void __exit
+danubeasc_exit (void)
+{
+	uart_unregister_driver(&danubeasc_reg);
+}
+
+module_init(danubeasc_init);
+module_exit(danubeasc_exit);
+
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("MIPS Danube serial port driver");
+MODULE_LICENSE("GPL");