diff options
author | jogo <jogo@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2014-04-04 10:17:08 +0000 |
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committer | jogo <jogo@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2014-04-04 10:17:08 +0000 |
commit | 8ef323302f93b40854fa628da94cc6c699732702 (patch) | |
tree | 6c76bb06b74246f20373557028e20adcc258a443 /target/linux/brcm63xx/patches-3.13/003-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch | |
parent | 89191cd685dd4452eddc8f308e33061bc623b149 (diff) |
brcm63xx: update development kernel to linux 3.14
Now that 3.13 will be EOL soon, switch to 3.14.
Known issues:
* 74x164 is not available because upstream dropped non-DT support
* jffs2 breaks with SMP
Unknown issues:
* probably plenty
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@40380 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/patches-3.13/003-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch')
-rw-r--r-- | target/linux/brcm63xx/patches-3.13/003-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch | 36 |
1 files changed, 0 insertions, 36 deletions
diff --git a/target/linux/brcm63xx/patches-3.13/003-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch b/target/linux/brcm63xx/patches-3.13/003-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch deleted file mode 100644 index c08bf00741..0000000000 --- a/target/linux/brcm63xx/patches-3.13/003-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch +++ /dev/null @@ -1,36 +0,0 @@ -From c8b7d2630d907025ce30989bddd01f4f0f13c103 Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Wed, 20 Nov 2013 17:22:40 +0100 -Subject: [PATCH 2/5] MIPS: BCM63XX: setup the HSSPI clock rate - -Properly set up the HSSPI clock rate depending on the SoC's PLL rate. - -Signed-off-by: Jonas Gorski <jogo@openwrt.org> ---- - arch/mips/bcm63xx/clk.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/mips/bcm63xx/clk.c -+++ b/arch/mips/bcm63xx/clk.c -@@ -390,3 +390,21 @@ void clk_put(struct clk *clk) - } - - EXPORT_SYMBOL(clk_put); -+ -+#define HSSPI_PLL_HZ_6328 133333333 -+#define HSSPI_PLL_HZ_6362 400000000 -+ -+static int __init bcm63xx_clk_init(void) -+{ -+ switch (bcm63xx_get_cpu_id()) { -+ case BCM6328_CPU_ID: -+ clk_hsspi.rate = HSSPI_PLL_HZ_6328; -+ break; -+ case BCM6362_CPU_ID: -+ clk_hsspi.rate = HSSPI_PLL_HZ_6362; -+ break; -+ } -+ -+ return 0; -+} -+arch_initcall(bcm63xx_clk_init); |