diff options
author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-11-06 07:38:18 +0000 |
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committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-11-06 07:38:18 +0000 |
commit | 3db29425052b10709666caa788e9ad4d9ca918d8 (patch) | |
tree | 2592ef6395fa3c87500bae19403d96795219ad9e /package/system/ltq-dsl/src | |
parent | 019f1724300c5cde061e68bc8998ac8833e9f458 (diff) |
[lantiq] prepare dsl driver for 3.6 and split fw into a seperate package
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34096 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/system/ltq-dsl/src')
-rw-r--r-- | package/system/ltq-dsl/src/Makefile | 2 | ||||
-rw-r--r-- | package/system/ltq-dsl/src/ifxmips_atm_ppe_danube.h | 1 | ||||
-rw-r--r-- | package/system/ltq-dsl/src/lantiq_mei.c | 8 |
3 files changed, 11 insertions, 0 deletions
diff --git a/package/system/ltq-dsl/src/Makefile b/package/system/ltq-dsl/src/Makefile index 44d2efbc05..691518a74e 100644 --- a/package/system/ltq-dsl/src/Makefile +++ b/package/system/ltq-dsl/src/Makefile @@ -1,6 +1,8 @@ obj-m = lantiq_mei.o lantiq_atm.o lantiq_atm-objs := ifxmips_atm_core.o +CFLAGS_MODULE+=-DSOC_TYPE_XWAY +EXTRA_CFLAGS+=-DSOC_TYPE_XWAY ifeq ($(BUILD_VARIANT),danube) CFLAGS_MODULE+=-DCONFIG_DANUBE EXTRA_CFLAGS+=-DCONFIG_DANUBE diff --git a/package/system/ltq-dsl/src/ifxmips_atm_ppe_danube.h b/package/system/ltq-dsl/src/ifxmips_atm_ppe_danube.h index 7e46cc1838..58db3a7460 100644 --- a/package/system/ltq-dsl/src/ifxmips_atm_ppe_danube.h +++ b/package/system/ltq-dsl/src/ifxmips_atm_ppe_danube.h @@ -122,6 +122,7 @@ /* * Mailbox IGU1 Interrupt */ +#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24) #define PPE_MAILBOX_IGU1_INT LTQ_PPE_MBOX_INT diff --git a/package/system/ltq-dsl/src/lantiq_mei.c b/package/system/ltq-dsl/src/lantiq_mei.c index aadb098c6d..00ac90289b 100644 --- a/package/system/ltq-dsl/src/lantiq_mei.c +++ b/package/system/ltq-dsl/src/lantiq_mei.c @@ -81,6 +81,14 @@ #define ltq_w32_mask(clear, set, reg) ltq_w32((ltq_r32(reg) & ~clear) | set, reg) */ +#define LTQ_RCU_BASE_ADDR 0x1F203000 +#define LTQ_ICU_BASE_ADDR 0x1F880200 +#define LTQ_MEI_BASE_ADDR 0x1E116000 +#define LTQ_PMU_BASE_ADDR 0x1F102000 +#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) +#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) +#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23) + #define LTQ_RCU_RST_REQ_DFE (1 << 7) #define LTQ_RCU_RST_REQ_AFE (1 << 11) |