diff options
| author | jogo <jogo@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2014-02-24 15:54:12 +0000 |
|---|---|---|
| committer | jogo <jogo@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2014-02-24 15:54:12 +0000 |
| commit | ee7f93855f48630d93d1282f85fecee1dbe6597a (patch) | |
| tree | 4b55700cffab2b78e023eaa583de8dc96326893c | |
| parent | f6e55885768e39c94cc2d7bbbcdc7db4497b0c38 (diff) | |
brcm63xx: add preliminary support for 3.13
Add support for 3.13 as a development kernel. Mostly untested, only net
booted. If flashed may brick your router or kill your cat.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39746 3c298f89-4303-0410-b956-a3cf2f4a3e73
155 files changed, 16434 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/config-3.13 b/target/linux/brcm63xx/config-3.13 new file mode 100644 index 0000000000..9cf4d6011d --- /dev/null +++ b/target/linux/brcm63xx/config-3.13 @@ -0,0 +1,195 @@ +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_AUDIT=y +CONFIG_AUDIT_GENERIC=y +CONFIG_B53=y +CONFIG_B53_MMAP_DRIVER=y +CONFIG_B53_PHY_DRIVER=y +CONFIG_B53_PHY_FIXUP=y +CONFIG_B53_SPI_DRIVER=y +# CONFIG_B53_SRAB_DRIVER is not set +CONFIG_BCM63XX=y +CONFIG_BCM63XX_CPU_3368=y +CONFIG_BCM63XX_CPU_6318=y +CONFIG_BCM63XX_CPU_63268=y +CONFIG_BCM63XX_CPU_6328=y +CONFIG_BCM63XX_CPU_6338=y +CONFIG_BCM63XX_CPU_6345=y +CONFIG_BCM63XX_CPU_6348=y +CONFIG_BCM63XX_CPU_6358=y +CONFIG_BCM63XX_CPU_6362=y +CONFIG_BCM63XX_CPU_6368=y +CONFIG_BCM63XX_EHCI=y +CONFIG_BCM63XX_ENET=y +CONFIG_BCM63XX_OHCI=y +CONFIG_BCM63XX_PHY=y +CONFIG_BCM63XX_WDT=y +CONFIG_BOARD_BCM963XX=y +# CONFIG_BOARD_LIVEBOX is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_BMIPS=y +CONFIG_CPU_BMIPS32_3300=y +CONFIG_CPU_BMIPS4350=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK_8250 is not set +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_74X164=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HAMRADIO is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_BCM63XX=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_HZ_PERIODIC=y +CONFIG_IMAGE_CMDLINE_HACK=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_KEXEC=y +CONFIG_LEDS_GPIO=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_MT_DISABLED=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_BCM63XX_PARTS=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_BE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +# CONFIG_MTD_CFI_NOSWAP is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RELAY=y +CONFIG_RTL8366_SMI=y +CONFIG_RTL8367_PHY=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_BCM63XX=y +CONFIG_SERIAL_BCM63XX_CONSOLE=y +CONFIG_SPI=y +CONFIG_SPI_BCM63XX=y +CONFIG_SPI_BCM63XX_HSSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_SSB=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_BLOCKIO=y +# CONFIG_SSB_DRIVER_MIPS is not set +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_SPROM=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWCONFIG=y +CONFIG_SYS_HAS_CPU_BMIPS=y +CONFIG_SYS_HAS_CPU_BMIPS32_3300=y +CONFIG_SYS_HAS_CPU_BMIPS4350=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_USB_SUPPORT=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_WEAK_ORDERING=y +# CONFIG_ZBUD is not set +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/brcm63xx/patches-3.13/001-spi-add-bcm63xx-HSSPI-driver.patch b/target/linux/brcm63xx/patches-3.13/001-spi-add-bcm63xx-HSSPI-driver.patch new file mode 100644 index 0000000000..0cd7982c39 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/001-spi-add-bcm63xx-HSSPI-driver.patch @@ -0,0 +1,531 @@ +From 8e051b79ae3f66dbad96312fe2976401c28d2148 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 12 Nov 2011 12:19:55 +0100 +Subject: [PATCH 5/5] spi: add bcm63xx HSSPI driver + +Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs. + +It does feature some new modes like 3-wire or dual spi, but neither of it +is currently implemented. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + drivers/spi/Kconfig | 7 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-bcm63xx-hsspi.c | 484 ++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 492 insertions(+) + create mode 100644 drivers/spi/spi-bcm63xx-hsspi.c + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -118,6 +118,13 @@ config SPI_BCM63XX + help + Enable support for the SPI controller on the Broadcom BCM63xx SoCs. + ++config SPI_BCM63XX_HSSPI ++ tristate "Broadcom BCM63XX HS SPI controller driver" ++ depends on BCM63XX || COMPILE_TEST ++ help ++ This enables support for the High Speed SPI controller present on ++ newer Broadcom BCM63XX SoCs. ++ + config SPI_BITBANG + tristate "Utilities for Bitbanging SPI masters" + help +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_SPI_ATH79) += spi-ath79.o + obj-$(CONFIG_SPI_AU1550) += spi-au1550.o + obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o + obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o ++obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o + obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o + obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o + obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o +--- /dev/null ++++ b/drivers/spi/spi-bcm63xx-hsspi.c +@@ -0,0 +1,484 @@ ++/* ++ * Broadcom BCM63XX High Speed SPI Controller driver ++ * ++ * Copyright 2000-2010 Broadcom Corporation ++ * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/io.h> ++#include <linux/clk.h> ++#include <linux/module.h> ++#include <linux/platform_device.h> ++#include <linux/delay.h> ++#include <linux/dma-mapping.h> ++#include <linux/err.h> ++#include <linux/interrupt.h> ++#include <linux/spi/spi.h> ++#include <linux/workqueue.h> ++#include <linux/mutex.h> ++ ++#define HSSPI_GLOBAL_CTRL_REG 0x0 ++#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 ++#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff ++#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8 ++#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00 ++#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16) ++#define GLOBAL_CTRL_CLK_POLARITY BIT(17) ++#define GLOBAL_CTRL_MOSI_IDLE BIT(18) ++ ++#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4 ++ ++#define HSSPI_INT_STATUS_REG 0x8 ++#define HSSPI_INT_STATUS_MASKED_REG 0xc ++#define HSSPI_INT_MASK_REG 0x10 ++ ++#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0) ++#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1) ++#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2) ++#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3) ++#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4) ++ ++#define HSSPI_INT_CLEAR_ALL 0xff001f1f ++ ++#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40) ++#define PINGPONG_CMD_COMMAND_MASK 0xf ++#define PINGPONG_COMMAND_NOOP 0 ++#define PINGPONG_COMMAND_START_NOW 1 ++#define PINGPONG_COMMAND_START_TRIGGER 2 ++#define PINGPONG_COMMAND_HALT 3 ++#define PINGPONG_COMMAND_FLUSH 4 ++#define PINGPONG_CMD_PROFILE_SHIFT 8 ++#define PINGPONG_CMD_SS_SHIFT 12 ++ ++#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40) ++ ++#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20) ++#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff ++#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14) ++#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15) ++ ++#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20) ++#define SIGNAL_CTRL_LATCH_RISING BIT(12) ++#define SIGNAL_CTRL_LAUNCH_RISING BIT(13) ++#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16) ++ ++#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20) ++#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8 ++#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12 ++#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16 ++#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18 ++#define MODE_CTRL_MODE_3WIRE BIT(20) ++#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24 ++ ++#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200) ++ ++ ++#define HSSPI_OP_CODE_SHIFT 13 ++#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT) ++#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT) ++#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT) ++#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT) ++#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT) ++ ++#define HSSPI_BUFFER_LEN 512 ++#define HSSPI_OPCODE_LEN 2 ++ ++#define HSSPI_MAX_PREPEND_LEN 15 ++ ++#define HSSPI_MAX_SYNC_CLOCK 30000000 ++ ++#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */ ++ ++struct bcm63xx_hsspi { ++ struct completion done; ++ struct mutex bus_mutex; ++ ++ struct platform_device *pdev; ++ struct clk *clk; ++ void __iomem *regs; ++ u8 __iomem *fifo; ++ ++ u32 speed_hz; ++ u8 cs_polarity; ++}; ++ ++static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs, ++ bool active) ++{ ++ u32 reg; ++ ++ mutex_lock(&bs->bus_mutex); ++ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ ++ reg &= ~BIT(cs); ++ if (active == !(bs->cs_polarity & BIT(cs))) ++ reg |= BIT(cs); ++ ++ __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ mutex_unlock(&bs->bus_mutex); ++} ++ ++static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, ++ struct spi_device *spi, int hz) ++{ ++ unsigned profile = spi->chip_select; ++ u32 reg; ++ ++ reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); ++ __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg, ++ bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile)); ++ ++ reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); ++ if (hz > HSSPI_MAX_SYNC_CLOCK) ++ reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH; ++ else ++ reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH; ++ __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); ++ ++ mutex_lock(&bs->bus_mutex); ++ /* setup clock polarity */ ++ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ reg &= ~GLOBAL_CTRL_CLK_POLARITY; ++ if (spi->mode & SPI_CPOL) ++ reg |= GLOBAL_CTRL_CLK_POLARITY; ++ __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ mutex_unlock(&bs->bus_mutex); ++} ++ ++static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) ++{ ++ struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); ++ unsigned chip_select = spi->chip_select; ++ u16 opcode = 0; ++ int pending = t->len; ++ int step_size = HSSPI_BUFFER_LEN; ++ const u8 *tx = t->tx_buf; ++ u8 *rx = t->rx_buf; ++ ++ bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); ++ bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); ++ ++ if (tx && rx) ++ opcode = HSSPI_OP_READ_WRITE; ++ else if (tx) ++ opcode = HSSPI_OP_WRITE; ++ else if (rx) ++ opcode = HSSPI_OP_READ; ++ ++ if (opcode != HSSPI_OP_READ) ++ step_size -= HSSPI_OPCODE_LEN; ++ ++ __raw_writel(0 << MODE_CTRL_PREPENDBYTE_CNT_SHIFT | ++ 2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT | ++ 2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff, ++ bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); ++ ++ while (pending > 0) { ++ int curr_step = min_t(int, step_size, pending); ++ ++ init_completion(&bs->done); ++ if (tx) { ++ memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step); ++ tx += curr_step; ++ } ++ ++ __raw_writew(opcode | curr_step, bs->fifo); ++ ++ /* enable interrupt */ ++ __raw_writel(HSSPI_PINGx_CMD_DONE(0), ++ bs->regs + HSSPI_INT_MASK_REG); ++ ++ /* start the transfer */ ++ __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT | ++ chip_select << PINGPONG_CMD_PROFILE_SHIFT | ++ PINGPONG_COMMAND_START_NOW, ++ bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); ++ ++ if (wait_for_completion_timeout(&bs->done, HZ) == 0) { ++ dev_err(&bs->pdev->dev, "transfer timed out!\n"); ++ return -ETIMEDOUT; ++ } ++ ++ if (rx) { ++ memcpy_fromio(rx, bs->fifo, curr_step); ++ rx += curr_step; ++ } ++ ++ pending -= curr_step; ++ } ++ ++ return 0; ++} ++ ++static int bcm63xx_hsspi_setup(struct spi_device *spi) ++{ ++ struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); ++ u32 reg; ++ ++ reg = __raw_readl(bs->regs + ++ HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); ++ reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING); ++ if (spi->mode & SPI_CPHA) ++ reg |= SIGNAL_CTRL_LAUNCH_RISING; ++ else ++ reg |= SIGNAL_CTRL_LATCH_RISING; ++ __raw_writel(reg, bs->regs + ++ HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); ++ ++ mutex_lock(&bs->bus_mutex); ++ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ ++ /* only change actual polarities if there is no transfer */ ++ if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) { ++ if (spi->mode & SPI_CS_HIGH) ++ reg |= BIT(spi->chip_select); ++ else ++ reg &= ~BIT(spi->chip_select); ++ __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ } ++ ++ if (spi->mode & SPI_CS_HIGH) ++ bs->cs_polarity |= BIT(spi->chip_select); ++ else ++ bs->cs_polarity &= ~BIT(spi->chip_select); ++ ++ mutex_unlock(&bs->bus_mutex); ++ ++ return 0; ++} ++ ++static int bcm63xx_hsspi_transfer_one(struct spi_master *master, ++ struct spi_message *msg) ++{ ++ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); ++ struct spi_transfer *t; ++ struct spi_device *spi = msg->spi; ++ int status = -EINVAL; ++ int dummy_cs; ++ u32 reg; ++ ++ /* This controller does not support keeping CS active during idle. ++ * To work around this, we use the following ugly hack: ++ * ++ * a. Invert the target chip select's polarity so it will be active. ++ * b. Select a "dummy" chip select to use as the hardware target. ++ * c. Invert the dummy chip select's polarity so it will be inactive ++ * during the actual transfers. ++ * d. Tell the hardware to send to the dummy chip select. Thanks to ++ * the multiplexed nature of SPI the actual target will receive ++ * the transfer and we see its response. ++ * ++ * e. At the end restore the polarities again to their default values. ++ */ ++ ++ dummy_cs = !spi->chip_select; ++ bcm63xx_hsspi_set_cs(bs, dummy_cs, true); ++ ++ list_for_each_entry(t, &msg->transfers, transfer_list) { ++ status = bcm63xx_hsspi_do_txrx(spi, t); ++ if (status) ++ break; ++ ++ msg->actual_length += t->len; ++ ++ if (t->delay_usecs) ++ udelay(t->delay_usecs); ++ ++ if (t->cs_change) ++ bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); ++ } ++ ++ mutex_lock(&bs->bus_mutex); ++ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK; ++ reg |= bs->cs_polarity; ++ __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ mutex_unlock(&bs->bus_mutex); ++ ++ msg->status = status; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++ ++static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id) ++{ ++ struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id; ++ ++ if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0) ++ return IRQ_NONE; ++ ++ __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); ++ __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); ++ ++ complete(&bs->done); ++ ++ return IRQ_HANDLED; ++} ++ ++static int bcm63xx_hsspi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct bcm63xx_hsspi *bs; ++ struct resource *res_mem; ++ void __iomem *regs; ++ struct device *dev = &pdev->dev; ++ struct clk *clk; ++ int irq, ret; ++ u32 reg, rate; ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(dev, "no irq\n"); ++ return -ENXIO; ++ } ++ ++ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ regs = devm_request_and_ioremap(dev, res_mem); ++ if (IS_ERR(regs)) ++ return PTR_ERR(regs); ++ ++ clk = clk_get(dev, "hsspi"); ++ ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ rate = clk_get_rate(clk); ++ if (!rate) { ++ ret = -EINVAL; ++ goto out_put_clk; ++ } ++ ++ clk_prepare_enable(clk); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master) { ++ ret = -ENOMEM; ++ goto out_disable_clk; ++ } ++ ++ bs = spi_master_get_devdata(master); ++ bs->pdev = pdev; ++ bs->clk = clk; ++ bs->regs = regs; ++ bs->speed_hz = rate; ++ bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0)); ++ ++ mutex_init(&bs->bus_mutex); ++ ++ master->bus_num = HSSPI_BUS_NUM; ++ master->num_chipselect = 8; ++ master->setup = bcm63xx_hsspi_setup; ++ master->transfer_one_message = bcm63xx_hsspi_transfer_one; ++ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; ++ master->bits_per_word_mask = SPI_BPW_MASK(8); ++ master->auto_runtime_pm = true; ++ ++ platform_set_drvdata(pdev, master); ++ ++ /* Initialize the hardware */ ++ __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); ++ ++ /* clean up any pending interrupts */ ++ __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); ++ ++ /* read out default CS polarities */ ++ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK; ++ __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF, ++ bs->regs + HSSPI_GLOBAL_CTRL_REG); ++ ++ ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED, ++ pdev->name, bs); ++ ++ if (ret) ++ goto out_put_master; ++ ++ /* register and we are done */ ++ ret = spi_register_master(master); ++ if (ret) ++ goto out_put_master; ++ ++ return 0; ++ ++out_put_master: ++ spi_master_put(master); ++out_disable_clk: ++ clk_disable_unprepare(clk); ++out_put_clk: ++ clk_put(clk); ++ ++ return ret; ++} ++ ++ ++static int bcm63xx_hsspi_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); ++ ++ spi_unregister_master(master); ++ ++ /* reset the hardware and block queue progress */ ++ __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); ++ clk_disable_unprepare(bs->clk); ++ clk_put(bs->clk); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int bcm63xx_hsspi_suspend(struct device *dev) ++{ ++ struct spi_master *master = dev_get_drvdata(dev); ++ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); ++ ++ spi_master_suspend(master); ++ clk_disable(bs->clk); ++ ++ return 0; ++} ++ ++static int bcm63xx_hsspi_resume(struct device *dev) ++{ ++ struct spi_master *master = dev_get_drvdata(dev); ++ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); ++ ++ clk_enable(bs->clk); ++ spi_master_resume(master); ++ ++ return 0; ++} ++ ++static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = { ++ .suspend = bcm63xx_hsspi_suspend, ++ .resume = bcm63xx_hsspi_resume, ++}; ++ ++#define BCM63XX_HSSPI_PM_OPS (&bcm63xx_hsspi_pm_ops) ++#else ++#define BCM63XX_HSSPI_PM_OPS NULL ++#endif ++ ++ ++ ++static struct platform_driver bcm63xx_hsspi_driver = { ++ .driver = { ++ .name = "bcm63xx-hsspi", ++ .owner = THIS_MODULE, ++ .pm = BCM63XX_HSSPI_PM_OPS, ++ }, ++ .probe = bcm63xx_hsspi_probe, ++ .remove = bcm63xx_hsspi_remove, ++}; ++ ++module_platform_driver(bcm63xx_hsspi_driver); ++ ++MODULE_ALIAS("platform:bcm63xx_hsspi"); ++MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver"); ++MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm63xx/patches-3.13/002-MIPS-BCM63XX-expose-the-HSSPI-clock.patch b/target/linux/brcm63xx/patches-3.13/002-MIPS-BCM63XX-expose-the-HSSPI-clock.patch new file mode 100644 index 0000000000..38aa69a73c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/002-MIPS-BCM63XX-expose-the-HSSPI-clock.patch @@ -0,0 +1,50 @@ +From f0df10fb498c21bbb201bc81dd209ea646b5a311 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 12 Nov 2011 12:19:09 +0100 +Subject: [PATCH 1/5] MIPS: BCM63XX: expose the HSSPI clock + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/clk.c | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -226,6 +226,28 @@ static struct clk clk_spi = { + }; + + /* ++ * HSSPI clock ++ */ ++static void hsspi_set(struct clk *clk, int enable) ++{ ++ u32 mask; ++ ++ if (BCMCPU_IS_6328()) ++ mask = CKCTL_6328_HSSPI_EN; ++ else if (BCMCPU_IS_6362()) ++ mask = CKCTL_6362_HSSPI_EN; ++ else ++ return; ++ ++ bcm_hwclock_set(mask, enable); ++} ++ ++static struct clk clk_hsspi = { ++ .set = hsspi_set, ++}; ++ ++ ++/* + * XTM clock + */ + static void xtm_set(struct clk *clk, int enable) +@@ -346,6 +368,8 @@ struct clk *clk_get(struct device *dev, + return &clk_usbd; + if (!strcmp(id, "spi")) + return &clk_spi; ++ if (!strcmp(id, "hsspi")) ++ return &clk_hsspi; + if (!strcmp(id, "xtm")) + return &clk_xtm; + if (!strcmp(id, "periph")) diff --git a/target/linux/brcm63xx/patches-3.13/003-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch b/target/linux/brcm63xx/patches-3.13/003-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch new file mode 100644 index 0000000000..c08bf00741 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/003-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch @@ -0,0 +1,36 @@ +From c8b7d2630d907025ce30989bddd01f4f0f13c103 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Wed, 20 Nov 2013 17:22:40 +0100 +Subject: [PATCH 2/5] MIPS: BCM63XX: setup the HSSPI clock rate + +Properly set up the HSSPI clock rate depending on the SoC's PLL rate. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/clk.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -390,3 +390,21 @@ void clk_put(struct clk *clk) + } + + EXPORT_SYMBOL(clk_put); ++ ++#define HSSPI_PLL_HZ_6328 133333333 ++#define HSSPI_PLL_HZ_6362 400000000 ++ ++static int __init bcm63xx_clk_init(void) ++{ ++ switch (bcm63xx_get_cpu_id()) { ++ case BCM6328_CPU_ID: ++ clk_hsspi.rate = HSSPI_PLL_HZ_6328; ++ break; ++ case BCM6362_CPU_ID: ++ clk_hsspi.rate = HSSPI_PLL_HZ_6362; ++ break; ++ } ++ ++ return 0; ++} ++arch_initcall(bcm63xx_clk_init); diff --git a/target/linux/brcm63xx/patches-3.13/004-MIPS-BCM63XX-add-HSSPI-IRQ-and-register-offsets.patch b/target/linux/brcm63xx/patches-3.13/004-MIPS-BCM63XX-add-HSSPI-IRQ-and-register-offsets.patch new file mode 100644 index 0000000000..7bd98c158b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/004-MIPS-BCM63XX-add-HSSPI-IRQ-and-register-offsets.patch @@ -0,0 +1,156 @@ +From 33a6acbe47636adcd9062a0e0af7985c0df9faa5 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 12 Nov 2011 12:19:55 +0100 +Subject: [PATCH 3/5] MIPS: BCM63XX: add HSSPI IRQ and register offsets + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -145,6 +145,7 @@ enum bcm63xx_regs_set { + RSET_UART1, + RSET_GPIO, + RSET_SPI, ++ RSET_HSSPI, + RSET_UDC0, + RSET_OHCI0, + RSET_OHCI_PRIV, +@@ -193,6 +194,7 @@ enum bcm63xx_regs_set { + #define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) + #define RSET_ENETSW_SIZE 65536 + #define RSET_UART_SIZE 24 ++#define RSET_HSSPI_SIZE 1536 + #define RSET_UDC_SIZE 256 + #define RSET_OHCI_SIZE 256 + #define RSET_EHCI_SIZE 256 +@@ -265,6 +267,7 @@ enum bcm63xx_regs_set { + #define BCM_6328_UART1_BASE (0xb0000120) + #define BCM_6328_GPIO_BASE (0xb0000080) + #define BCM_6328_SPI_BASE (0xdeadbeef) ++#define BCM_6328_HSSPI_BASE (0xb0001000) + #define BCM_6328_UDC0_BASE (0xdeadbeef) + #define BCM_6328_USBDMA_BASE (0xb000c000) + #define BCM_6328_OHCI0_BASE (0xb0002600) +@@ -313,6 +316,7 @@ enum bcm63xx_regs_set { + #define BCM_6338_UART1_BASE (0xdeadbeef) + #define BCM_6338_GPIO_BASE (0xfffe0400) + #define BCM_6338_SPI_BASE (0xfffe0c00) ++#define BCM_6338_HSSPI_BASE (0xdeadbeef) + #define BCM_6338_UDC0_BASE (0xdeadbeef) + #define BCM_6338_USBDMA_BASE (0xfffe2400) + #define BCM_6338_OHCI0_BASE (0xdeadbeef) +@@ -360,6 +364,7 @@ enum bcm63xx_regs_set { + #define BCM_6345_UART1_BASE (0xdeadbeef) + #define BCM_6345_GPIO_BASE (0xfffe0400) + #define BCM_6345_SPI_BASE (0xdeadbeef) ++#define BCM_6345_HSSPI_BASE (0xdeadbeef) + #define BCM_6345_UDC0_BASE (0xdeadbeef) + #define BCM_6345_USBDMA_BASE (0xfffe2800) + #define BCM_6345_ENET0_BASE (0xfffe1800) +@@ -406,6 +411,7 @@ enum bcm63xx_regs_set { + #define BCM_6348_UART1_BASE (0xdeadbeef) + #define BCM_6348_GPIO_BASE (0xfffe0400) + #define BCM_6348_SPI_BASE (0xfffe0c00) ++#define BCM_6348_HSSPI_BASE (0xdeadbeef) + #define BCM_6348_UDC0_BASE (0xfffe1000) + #define BCM_6348_USBDMA_BASE (0xdeadbeef) + #define BCM_6348_OHCI0_BASE (0xfffe1b00) +@@ -451,6 +457,7 @@ enum bcm63xx_regs_set { + #define BCM_6358_UART1_BASE (0xfffe0120) + #define BCM_6358_GPIO_BASE (0xfffe0080) + #define BCM_6358_SPI_BASE (0xfffe0800) ++#define BCM_6358_HSSPI_BASE (0xdeadbeef) + #define BCM_6358_UDC0_BASE (0xfffe0800) + #define BCM_6358_USBDMA_BASE (0xdeadbeef) + #define BCM_6358_OHCI0_BASE (0xfffe1400) +@@ -553,6 +560,7 @@ enum bcm63xx_regs_set { + #define BCM_6368_UART1_BASE (0xb0000120) + #define BCM_6368_GPIO_BASE (0xb0000080) + #define BCM_6368_SPI_BASE (0xb0000800) ++#define BCM_6368_HSSPI_BASE (0xdeadbeef) + #define BCM_6368_UDC0_BASE (0xdeadbeef) + #define BCM_6368_USBDMA_BASE (0xb0004800) + #define BCM_6368_OHCI0_BASE (0xb0001600) +@@ -604,6 +612,7 @@ extern const unsigned long *bcm63xx_regs + __GEN_RSET_BASE(__cpu, UART1) \ + __GEN_RSET_BASE(__cpu, GPIO) \ + __GEN_RSET_BASE(__cpu, SPI) \ ++ __GEN_RSET_BASE(__cpu, HSSPI) \ + __GEN_RSET_BASE(__cpu, UDC0) \ + __GEN_RSET_BASE(__cpu, OHCI0) \ + __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ +@@ -647,6 +656,7 @@ extern const unsigned long *bcm63xx_regs + [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ + [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ + [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ ++ [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \ + [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ + [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ + [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ +@@ -727,6 +737,7 @@ enum bcm63xx_irq { + IRQ_ENET0, + IRQ_ENET1, + IRQ_ENET_PHY, ++ IRQ_HSSPI, + IRQ_OHCI0, + IRQ_EHCI0, + IRQ_USBD, +@@ -815,6 +826,7 @@ enum bcm63xx_irq { + #define BCM_6328_ENET0_IRQ 0 + #define BCM_6328_ENET1_IRQ 0 + #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) ++#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) + #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) + #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) + #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) +@@ -860,6 +872,7 @@ enum bcm63xx_irq { + #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) + #define BCM_6338_ENET1_IRQ 0 + #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_6338_HSSPI_IRQ 0 + #define BCM_6338_OHCI0_IRQ 0 + #define BCM_6338_EHCI0_IRQ 0 + #define BCM_6338_USBD_IRQ 0 +@@ -898,6 +911,7 @@ enum bcm63xx_irq { + #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) + #define BCM_6345_ENET1_IRQ 0 + #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) ++#define BCM_6345_HSSPI_IRQ 0 + #define BCM_6345_OHCI0_IRQ 0 + #define BCM_6345_EHCI0_IRQ 0 + #define BCM_6345_USBD_IRQ 0 +@@ -936,6 +950,7 @@ enum bcm63xx_irq { + #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) + #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) + #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_6348_HSSPI_IRQ 0 + #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) + #define BCM_6348_EHCI0_IRQ 0 + #define BCM_6348_USBD_IRQ 0 +@@ -974,6 +989,7 @@ enum bcm63xx_irq { + #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) + #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) + #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_6358_HSSPI_IRQ 0 + #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) + #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) + #define BCM_6358_USBD_IRQ 0 +@@ -1086,6 +1102,7 @@ enum bcm63xx_irq { + #define BCM_6368_ENET0_IRQ 0 + #define BCM_6368_ENET1_IRQ 0 + #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) ++#define BCM_6368_HSSPI_IRQ 0 + #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) + #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) + #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) +@@ -1133,6 +1150,7 @@ extern const int *bcm63xx_irqs; + [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ + [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ + [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ ++ [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \ + [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ + [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ + [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ diff --git a/target/linux/brcm63xx/patches-3.13/005-MIPS-BCM63XX-add-HSSPI-platform-device-and-register-.patch b/target/linux/brcm63xx/patches-3.13/005-MIPS-BCM63XX-add-HSSPI-platform-device-and-register-.patch new file mode 100644 index 0000000000..b20cf2c867 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/005-MIPS-BCM63XX-add-HSSPI-platform-device-and-register-.patch @@ -0,0 +1,107 @@ +From ad04c99347cf9e583457f7258e97f0be22fad2ec Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 12 Nov 2011 12:18:26 +0100 +Subject: [PATCH 4/5] MIPS: BCM63XX: add HSSPI platform device and register it + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/Makefile | 4 +- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 3 ++ + arch/mips/bcm63xx/dev-hsspi.c | 47 ++++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h | 8 ++++ + 4 files changed, 60 insertions(+), 2 deletions(-) + create mode 100644 arch/mips/bcm63xx/dev-hsspi.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,7 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ +- dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-wdt.o \ +- dev-usb-usbd.o ++ dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ ++ dev-wdt.o dev-usb-usbd.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -23,6 +23,7 @@ + #include <bcm63xx_dev_enet.h> + #include <bcm63xx_dev_dsp.h> + #include <bcm63xx_dev_flash.h> ++#include <bcm63xx_dev_hsspi.h> + #include <bcm63xx_dev_pcmcia.h> + #include <bcm63xx_dev_spi.h> + #include <bcm63xx_dev_usb_usbd.h> +@@ -915,6 +916,8 @@ int __init board_register_devices(void) + + bcm63xx_spi_register(); + ++ bcm63xx_hsspi_register(); ++ + bcm63xx_flash_register(); + + bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); +--- /dev/null ++++ b/arch/mips/bcm63xx/dev-hsspi.c +@@ -0,0 +1,47 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com> ++ */ ++ ++#include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/platform_device.h> ++ ++#include <bcm63xx_cpu.h> ++#include <bcm63xx_dev_hsspi.h> ++#include <bcm63xx_regs.h> ++ ++static struct resource spi_resources[] = { ++ { ++ .start = -1, /* filled at runtime */ ++ .end = -1, /* filled at runtime */ ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = -1, /* filled at runtime */ ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device bcm63xx_hsspi_device = { ++ .name = "bcm63xx-hsspi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(spi_resources), ++ .resource = spi_resources, ++}; ++ ++int __init bcm63xx_hsspi_register(void) ++{ ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362()) ++ return -ENODEV; ++ ++ spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); ++ spi_resources[0].end = spi_resources[0].start; ++ spi_resources[0].end += RSET_HSSPI_SIZE - 1; ++ spi_resources[1].start = bcm63xx_get_irq_number(IRQ_HSSPI); ++ ++ return platform_device_register(&bcm63xx_hsspi_device); ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h +@@ -0,0 +1,8 @@ ++#ifndef BCM63XX_DEV_HSSPI_H ++#define BCM63XX_DEV_HSSPI_H ++ ++#include <linux/types.h> ++ ++int bcm63xx_hsspi_register(void); ++ ++#endif /* BCM63XX_DEV_HSSPI_H */ diff --git a/target/linux/brcm63xx/patches-3.13/006-spi-bcm63xx-don-t-reject-reads-256-bytes.patch b/target/linux/brcm63xx/patches-3.13/006-spi-bcm63xx-don-t-reject-reads-256-bytes.patch new file mode 100644 index 0000000000..60abbda044 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/006-spi-bcm63xx-don-t-reject-reads-256-bytes.patch @@ -0,0 +1,31 @@ +From 4d8fa9d3d1fe1d70fe7d59537acf49797f6010a1 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 1 Dec 2013 16:19:46 +0100 +Subject: [PATCH 2/2] spi/bcm63xx: don't reject reads >= 256 bytes + +The rx_tail register is only 8 bit wide, so it will wrap around +after 256 read bytes. This makes it rather meaningless, so drop any +usage of it to not treat reads over 256 as failed. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + drivers/spi/spi-bcm63xx.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +--- a/drivers/spi/spi-bcm63xx.c ++++ b/drivers/spi/spi-bcm63xx.c +@@ -205,13 +205,7 @@ static int bcm63xx_txrx_bufs(struct spi_ + if (!timeout) + return -ETIMEDOUT; + +- /* read out all data */ +- rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); +- +- if (do_rx && rx_tail != len) +- return -EIO; +- +- if (!rx_tail) ++ if (!do_rx) + return 0; + + len = 0; diff --git a/target/linux/brcm63xx/patches-3.13/007-MIPS-BCM63XX-disable-SMP-also-on-BCM3368.patch b/target/linux/brcm63xx/patches-3.13/007-MIPS-BCM63XX-disable-SMP-also-on-BCM3368.patch new file mode 100644 index 0000000000..b50f0b8e65 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/007-MIPS-BCM63XX-disable-SMP-also-on-BCM3368.patch @@ -0,0 +1,36 @@ +From 8bd8f46cbc709974b26396aa440133db4484015e Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Fri, 28 Jun 2013 00:25:13 +0200 +Subject: [PATCH V2 01/13] MIPS: BCM63XX: disable SMP also on BCM3368 + +BCM3368 has the same shared TLB as BCM6358. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/prom.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -64,9 +64,9 @@ void __init prom_init(void) + register_smp_ops(&bmips_smp_ops); + + /* +- * BCM6328 might not have its second CPU enabled, while BCM6358 +- * needs special handling for its shared TLB, so disable SMP +- * for now. ++ * BCM6328 might not have its second CPU enabled, while BCM3368 ++ * and BCM6358 need special handling for their shared TLB, so ++ * disable SMP for now. + */ + if (BCMCPU_IS_6328()) { + reg = bcm_readl(BCM_6328_OTP_BASE + +@@ -74,7 +74,7 @@ void __init prom_init(void) + + if (reg & OTP_6328_REG3_TP1_DISABLED) + bmips_smp_enabled = 0; +- } else if (BCMCPU_IS_6358()) { ++ } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { + bmips_smp_enabled = 0; + } + diff --git a/target/linux/brcm63xx/patches-3.13/008-MIPS-allow-asm-cpu.h-to-be-included-from-assembly.patch b/target/linux/brcm63xx/patches-3.13/008-MIPS-allow-asm-cpu.h-to-be-included-from-assembly.patch new file mode 100644 index 0000000000..92b7f98229 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/008-MIPS-allow-asm-cpu.h-to-be-included-from-assembly.patch @@ -0,0 +1,31 @@ +From 72a1c3ad0392d7b42bf50e6ecade63a775166c73 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 27 Jun 2013 21:32:41 +0200 +Subject: [PATCH V2 02/13] MIPS: allow asm/cpu.h to be included from assembly + +Add guards around the enum to allow including cpu.h from assembly. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/include/asm/cpu.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/mips/include/asm/cpu.h ++++ b/arch/mips/include/asm/cpu.h +@@ -249,6 +249,8 @@ + + #define FPIR_IMP_NONE 0x0000 + ++#if !defined(__ASSEMBLY__) ++ + enum cpu_type_enum { + CPU_UNKNOWN, + +@@ -301,6 +303,7 @@ enum cpu_type_enum { + CPU_LAST + }; + ++#endif /* !__ASSEMBLY */ + + /* + * ISA Level encodings diff --git a/target/linux/brcm63xx/patches-3.13/009-MIPS-BMIPS-change-compile-time-checks-to-runtime-che.patch b/target/linux/brcm63xx/patches-3.13/009-MIPS-BMIPS-change-compile-time-checks-to-runtime-che.patch new file mode 100644 index 0000000000..2f56f15e76 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/009-MIPS-BMIPS-change-compile-time-checks-to-runtime-che.patch @@ -0,0 +1,602 @@ +From 7d790bd6cab314462a29ba194e243b8b1d529524 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 27 Jun 2013 21:33:56 +0200 +Subject: [PATCH V2 03/13] MIPS: BMIPS: change compile time checks to runtime + checks + +Allow building for all bmips cpus at the same time by changing ifdefs +to checks for the cpu type, or adding appropriate checks to the +assembly. + +Since BMIPS43XX and BMIPS5000 require different IPI implementations, +split the SMP ops into one for each, so the runtime overhead is only +at registration time for them. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- +V1 -> V2: + * use switch (cpu_type()) instead of if () else if () ... + * split the smp ops into bmips43xx and bmips5000 + + arch/mips/bcm63xx/prom.c | 2 +- + arch/mips/include/asm/bmips.h | 3 +- + arch/mips/kernel/bmips_vec.S | 55 ++++++-- + arch/mips/kernel/smp-bmips.c | 312 +++++++++++++++++++++++++----------------- + 4 files changed, 235 insertions(+), 137 deletions(-) + +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -61,7 +61,7 @@ void __init prom_init(void) + + if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) { + /* set up SMP */ +- register_smp_ops(&bmips_smp_ops); ++ register_smp_ops(&bmips43xx_smp_ops); + + /* + * BCM6328 might not have its second CPU enabled, while BCM3368 +--- a/arch/mips/include/asm/bmips.h ++++ b/arch/mips/include/asm/bmips.h +@@ -47,7 +47,8 @@ + #include <linux/cpumask.h> + #include <asm/r4kcache.h> + +-extern struct plat_smp_ops bmips_smp_ops; ++extern struct plat_smp_ops bmips43xx_smp_ops; ++extern struct plat_smp_ops bmips5000_smp_ops; + extern char bmips_reset_nmi_vec; + extern char bmips_reset_nmi_vec_end; + extern char bmips_smp_movevec; +--- a/arch/mips/kernel/bmips_vec.S ++++ b/arch/mips/kernel/bmips_vec.S +@@ -13,6 +13,7 @@ + #include <asm/asm.h> + #include <asm/asmmacro.h> + #include <asm/cacheops.h> ++#include <asm/cpu.h> + #include <asm/regdef.h> + #include <asm/mipsregs.h> + #include <asm/stackframe.h> +@@ -91,12 +92,18 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) + beqz k0, bmips_smp_entry + + #if defined(CONFIG_CPU_BMIPS5000) ++ mfc0 k0, CP0_PRID ++ li k1, PRID_IMP_BMIPS5000 ++ andi k0, 0xff00 ++ bne k0, k1, 1f ++ + /* if we're not on core 0, this must be the SMP boot signal */ + li k1, (3 << 25) + mfc0 k0, $22 + and k0, k1 + bnez k0, bmips_smp_entry +-#endif ++1: ++#endif /* CONFIG_CPU_BMIPS5000 */ + #endif /* CONFIG_SMP */ + + /* nope, it's just a regular NMI */ +@@ -139,7 +146,12 @@ bmips_smp_entry: + xori k0, 0x04 + mtc0 k0, CP0_CONFIG + ++ mfc0 k0, CP0_PRID ++ andi k0, 0xff00 + #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) ++ li k1, PRID_IMP_BMIPS43XX ++ bne k0, k1, 2f ++ + /* initialize CPU1's local I-cache */ + li k0, 0x80000000 + li k1, 0x80010000 +@@ -150,14 +162,21 @@ bmips_smp_entry: + 1: cache Index_Store_Tag_I, 0(k0) + addiu k0, 16 + bne k0, k1, 1b +-#elif defined(CONFIG_CPU_BMIPS5000) ++ ++ b 3f ++2: ++#endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */ ++#if defined(CONFIG_CPU_BMIPS5000) + /* set exception vector base */ ++ li k1, PRID_IMP_BMIPS5000 ++ bne k0, k1, 3f ++ + la k0, ebase + lw k0, 0(k0) + mtc0 k0, $15, 1 + BARRIER +-#endif +- ++#endif /* CONFIG_CPU_BMIPS5000 */ ++3: + /* jump back to kseg0 in case we need to remap the kseg1 area */ + la k0, 1f + jr k0 +@@ -221,8 +240,18 @@ END(bmips_smp_int_vec) + LEAF(bmips_enable_xks01) + + #if defined(CONFIG_XKS01) +- ++ mfc0 t0, CP0_PRID ++ andi t2, t0, 0xff00 + #if defined(CONFIG_CPU_BMIPS4380) ++ li t1, PRID_IMP_BMIPS43XX ++ bne t2, t1, 1f ++ ++ andi t0, 0xff ++ addiu t1, t0, -PRID_REV_BMIPS4380_HI ++ bgtz t1, 2f ++ addiu t0, -PRID_REV_BMIPS4380_LO ++ bltz t0, 2f ++ + mfc0 t0, $22, 3 + li t1, 0x1ff0 + li t2, (1 << 12) | (1 << 9) +@@ -231,7 +260,13 @@ LEAF(bmips_enable_xks01) + or t0, t2 + mtc0 t0, $22, 3 + BARRIER +-#elif defined(CONFIG_CPU_BMIPS5000) ++ b 2f ++1: ++#endif /* CONFIG_CPU_BMIPS4380 */ ++#if defined(CONFIG_CPU_BMIPS5000) ++ li t1, PRID_IMP_BMIPS5000 ++ bne t2, t1, 2f ++ + mfc0 t0, $22, 5 + li t1, 0x01ff + li t2, (1 << 8) | (1 << 5) +@@ -240,12 +275,8 @@ LEAF(bmips_enable_xks01) + or t0, t2 + mtc0 t0, $22, 5 + BARRIER +-#else +- +-#error Missing XKS01 setup +- +-#endif +- ++#endif /* CONFIG_CPU_BMIPS5000 */ ++2: + #endif /* defined(CONFIG_XKS01) */ + + jr ra +--- a/arch/mips/kernel/smp-bmips.c ++++ b/arch/mips/kernel/smp-bmips.c +@@ -49,8 +49,10 @@ cpumask_t bmips_booted_mask; + unsigned long bmips_smp_boot_sp; + unsigned long bmips_smp_boot_gp; + +-static void bmips_send_ipi_single(int cpu, unsigned int action); +-static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id); ++static void bmips43xx_send_ipi_single(int cpu, unsigned int action); ++static void bmips5000_send_ipi_single(int cpu, unsigned int action); ++static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); ++static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); + + /* SW interrupts 0,1 are used for interprocessor signaling */ + #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) +@@ -64,49 +66,58 @@ static irqreturn_t bmips_ipi_interrupt(i + static void __init bmips_smp_setup(void) + { + int i, cpu = 1, boot_cpu = 0; +- +-#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) + int cpu_hw_intr; + +- /* arbitration priority */ +- clear_c0_brcm_cmt_ctrl(0x30); +- +- /* NBK and weak order flags */ +- set_c0_brcm_config_0(0x30000); +- +- /* Find out if we are running on TP0 or TP1 */ +- boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); +- +- /* +- * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread +- * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output +- * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output +- */ +- if (boot_cpu == 0) +- cpu_hw_intr = 0x02; +- else +- cpu_hw_intr = 0x1d; +- +- change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15)); +- +- /* single core, 2 threads (2 pipelines) */ +- max_cpus = 2; +-#elif defined(CONFIG_CPU_BMIPS5000) +- /* enable raceless SW interrupts */ +- set_c0_brcm_config(0x03 << 22); +- +- /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ +- change_c0_brcm_mode(0x1f << 27, 0x02 << 27); +- +- /* N cores, 2 threads per core */ +- max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; ++ switch (current_cpu_type()) { ++ case CPU_BMIPS4350: ++ case CPU_BMIPS4380: ++ /* arbitration priority */ ++ clear_c0_brcm_cmt_ctrl(0x30); ++ ++ /* NBK and weak order flags */ ++ set_c0_brcm_config_0(0x30000); ++ ++ /* Find out if we are running on TP0 or TP1 */ ++ boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); ++ ++ /* ++ * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other ++ * thread ++ * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output ++ * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output ++ */ ++ if (boot_cpu == 0) ++ cpu_hw_intr = 0x02; ++ else ++ cpu_hw_intr = 0x1d; ++ ++ change_c0_brcm_cmt_intr(0xf8018000, ++ (cpu_hw_intr << 27) | (0x03 << 15)); ++ ++ /* single core, 2 threads (2 pipelines) */ ++ max_cpus = 2; ++ ++ break; ++ case CPU_BMIPS5000: ++ /* enable raceless SW interrupts */ ++ set_c0_brcm_config(0x03 << 22); ++ ++ /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ ++ change_c0_brcm_mode(0x1f << 27, 0x02 << 27); ++ ++ /* N cores, 2 threads per core */ ++ max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; ++ ++ /* clear any pending SW interrupts */ ++ for (i = 0; i < max_cpus; i++) { ++ write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); ++ write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); ++ } + +- /* clear any pending SW interrupts */ +- for (i = 0; i < max_cpus; i++) { +- write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); +- write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); ++ break; ++ default: ++ max_cpus = 1; + } +-#endif + + if (!bmips_smp_enabled) + max_cpus = 1; +@@ -134,6 +145,20 @@ static void __init bmips_smp_setup(void) + */ + static void bmips_prepare_cpus(unsigned int max_cpus) + { ++ irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); ++ ++ switch (current_cpu_type()) { ++ case CPU_BMIPS4350: ++ case CPU_BMIPS4380: ++ bmips_ipi_interrupt = bmips43xx_ipi_interrupt; ++ break; ++ case CPU_BMIPS5000: ++ bmips_ipi_interrupt = bmips5000_ipi_interrupt; ++ break; ++ default: ++ return; ++ } ++ + if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, + "smp_ipi0", NULL)) + panic("Can't request IPI0 interrupt"); +@@ -168,26 +193,39 @@ static void bmips_boot_secondary(int cpu + + pr_info("SMP: Booting CPU%d...\n", cpu); + +- if (cpumask_test_cpu(cpu, &bmips_booted_mask)) +- bmips_send_ipi_single(cpu, 0); ++ if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { ++ switch (current_cpu_type()) { ++ case CPU_BMIPS4350: ++ case CPU_BMIPS4380: ++ bmips43xx_send_ipi_single(cpu, 0); ++ break; ++ case CPU_BMIPS5000: ++ bmips5000_send_ipi_single(cpu, 0); ++ break; ++ } ++ } + else { +-#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) +- /* Reset slave TP1 if booting from TP0 */ +- if (cpu_logical_map(cpu) == 1) +- set_c0_brcm_cmt_ctrl(0x01); +-#elif defined(CONFIG_CPU_BMIPS5000) +- if (cpu & 0x01) +- write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); +- else { +- /* +- * core N thread 0 was already booted; just +- * pulse the NMI line +- */ +- bmips_write_zscm_reg(0x210, 0xc0000000); +- udelay(10); +- bmips_write_zscm_reg(0x210, 0x00); ++ switch (current_cpu_type()) { ++ case CPU_BMIPS4350: ++ case CPU_BMIPS4380: ++ /* Reset slave TP1 if booting from TP0 */ ++ if (cpu_logical_map(cpu) == 1) ++ set_c0_brcm_cmt_ctrl(0x01); ++ break; ++ case CPU_BMIPS5000: ++ if (cpu & 0x01) ++ write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); ++ else { ++ /* ++ * core N thread 0 was already booted; just ++ * pulse the NMI line ++ */ ++ bmips_write_zscm_reg(0x210, 0xc0000000); ++ udelay(10); ++ bmips_write_zscm_reg(0x210, 0x00); ++ } ++ break; + } +-#endif + cpumask_set_cpu(cpu, &bmips_booted_mask); + } + } +@@ -199,26 +237,32 @@ static void bmips_init_secondary(void) + { + /* move NMI vector to kseg0, in case XKS01 is enabled */ + +-#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) +- void __iomem *cbr = BMIPS_GET_CBR(); ++ void __iomem *cbr; + unsigned long old_vec; + unsigned long relo_vector; + int boot_cpu; + +- boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); +- relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 : +- BMIPS_RELO_VECTOR_CONTROL_1; +- +- old_vec = __raw_readl(cbr + relo_vector); +- __raw_writel(old_vec & ~0x20000000, cbr + relo_vector); +- +- clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); +-#elif defined(CONFIG_CPU_BMIPS5000) +- write_c0_brcm_bootvec(read_c0_brcm_bootvec() & +- (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000)); ++ switch (current_cpu_type()) { ++ case CPU_BMIPS4350: ++ case CPU_BMIPS4380: ++ cbr = BMIPS_GET_CBR(); ++ ++ boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); ++ relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 : ++ BMIPS_RELO_VECTOR_CONTROL_1; ++ ++ old_vec = __raw_readl(cbr + relo_vector); ++ __raw_writel(old_vec & ~0x20000000, cbr + relo_vector); ++ ++ clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); ++ break; ++ case CPU_BMIPS5000: ++ write_c0_brcm_bootvec(read_c0_brcm_bootvec() & ++ (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000)); + +- write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); +-#endif ++ write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); ++ break; ++ } + } + + /* +@@ -243,8 +287,6 @@ static void bmips_cpus_done(void) + { + } + +-#if defined(CONFIG_CPU_BMIPS5000) +- + /* + * BMIPS5000 raceless IPIs + * +@@ -253,12 +295,12 @@ static void bmips_cpus_done(void) + * IPI1 is used for SMP_CALL_FUNCTION + */ + +-static void bmips_send_ipi_single(int cpu, unsigned int action) ++static void bmips5000_send_ipi_single(int cpu, unsigned int action) + { + write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); + } + +-static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id) ++static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) + { + int action = irq - IPI0_IRQ; + +@@ -272,7 +314,14 @@ static irqreturn_t bmips_ipi_interrupt(i + return IRQ_HANDLED; + } + +-#else ++static void bmips5000_send_ipi_mask(const struct cpumask *mask, ++ unsigned int action) ++{ ++ unsigned int i; ++ ++ for_each_cpu(i, mask) ++ bmips5000_send_ipi_single(i, action); ++} + + /* + * BMIPS43xx racey IPIs +@@ -287,7 +336,7 @@ static irqreturn_t bmips_ipi_interrupt(i + static DEFINE_SPINLOCK(ipi_lock); + static DEFINE_PER_CPU(int, ipi_action_mask); + +-static void bmips_send_ipi_single(int cpu, unsigned int action) ++static void bmips43xx_send_ipi_single(int cpu, unsigned int action) + { + unsigned long flags; + +@@ -298,7 +347,7 @@ static void bmips_send_ipi_single(int cp + spin_unlock_irqrestore(&ipi_lock, flags); + } + +-static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id) ++static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) + { + unsigned long flags; + int action, cpu = irq - IPI0_IRQ; +@@ -317,15 +366,13 @@ static irqreturn_t bmips_ipi_interrupt(i + return IRQ_HANDLED; + } + +-#endif /* BMIPS type */ +- +-static void bmips_send_ipi_mask(const struct cpumask *mask, ++static void bmips43xx_send_ipi_mask(const struct cpumask *mask, + unsigned int action) + { + unsigned int i; + + for_each_cpu(i, mask) +- bmips_send_ipi_single(i, action); ++ bmips43xx_send_ipi_single(i, action); + } + + #ifdef CONFIG_HOTPLUG_CPU +@@ -381,15 +428,30 @@ void __ref play_dead(void) + + #endif /* CONFIG_HOTPLUG_CPU */ + +-struct plat_smp_ops bmips_smp_ops = { ++struct plat_smp_ops bmips43xx_smp_ops = { ++ .smp_setup = bmips_smp_setup, ++ .prepare_cpus = bmips_prepare_cpus, ++ .boot_secondary = bmips_boot_secondary, ++ .smp_finish = bmips_smp_finish, ++ .init_secondary = bmips_init_secondary, ++ .cpus_done = bmips_cpus_done, ++ .send_ipi_single = bmips43xx_send_ipi_single, ++ .send_ipi_mask = bmips43xx_send_ipi_mask, ++#ifdef CONFIG_HOTPLUG_CPU ++ .cpu_disable = bmips_cpu_disable, ++ .cpu_die = bmips_cpu_die, ++#endif ++}; ++ ++struct plat_smp_ops bmips5000_smp_ops = { + .smp_setup = bmips_smp_setup, + .prepare_cpus = bmips_prepare_cpus, + .boot_secondary = bmips_boot_secondary, + .smp_finish = bmips_smp_finish, + .init_secondary = bmips_init_secondary, + .cpus_done = bmips_cpus_done, +- .send_ipi_single = bmips_send_ipi_single, +- .send_ipi_mask = bmips_send_ipi_mask, ++ .send_ipi_single = bmips5000_send_ipi_single, ++ .send_ipi_mask = bmips5000_send_ipi_mask, + #ifdef CONFIG_HOTPLUG_CPU + .cpu_disable = bmips_cpu_disable, + .cpu_die = bmips_cpu_die, +@@ -427,43 +489,47 @@ void bmips_ebase_setup(void) + + BUG_ON(ebase != CKSEG0); + +-#if defined(CONFIG_CPU_BMIPS4350) +- /* +- * BMIPS4350 cannot relocate the normal vectors, but it +- * can relocate the BEV=1 vectors. So CPU1 starts up at +- * the relocated BEV=1, IV=0 general exception vector @ +- * 0xa000_0380. +- * +- * set_uncached_handler() is used here because: +- * - CPU1 will run this from uncached space +- * - None of the cacheflush functions are set up yet +- */ +- set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, +- &bmips_smp_int_vec, 0x80); +- __sync(); +- return; +-#elif defined(CONFIG_CPU_BMIPS4380) +- /* +- * 0x8000_0000: reset/NMI (initially in kseg1) +- * 0x8000_0400: normal vectors +- */ +- new_ebase = 0x80000400; +- cbr = BMIPS_GET_CBR(); +- __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0); +- __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1); +-#elif defined(CONFIG_CPU_BMIPS5000) +- /* +- * 0x8000_0000: reset/NMI (initially in kseg1) +- * 0x8000_1000: normal vectors +- */ +- new_ebase = 0x80001000; +- write_c0_brcm_bootvec(0xa0088008); +- write_c0_ebase(new_ebase); +- if (max_cpus > 2) +- bmips_write_zscm_reg(0xa0, 0xa008a008); +-#else +- return; +-#endif ++ switch (current_cpu_type()) { ++ case CPU_BMIPS4350: ++ /* ++ * BMIPS4350 cannot relocate the normal vectors, but it ++ * can relocate the BEV=1 vectors. So CPU1 starts up at ++ * the relocated BEV=1, IV=0 general exception vector @ ++ * 0xa000_0380. ++ * ++ * set_uncached_handler() is used here because: ++ * - CPU1 will run this from uncached space ++ * - None of the cacheflush functions are set up yet ++ */ ++ set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, ++ &bmips_smp_int_vec, 0x80); ++ __sync(); ++ return; ++ case CPU_BMIPS4380: ++ /* ++ * 0x8000_0000: reset/NMI (initially in kseg1) ++ * 0x8000_0400: normal vectors ++ */ ++ new_ebase = 0x80000400; ++ cbr = BMIPS_GET_CBR(); ++ __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0); ++ __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1); ++ break; ++ case CPU_BMIPS5000: ++ /* ++ * 0x8000_0000: reset/NMI (initially in kseg1) ++ * 0x8000_1000: normal vectors ++ */ ++ new_ebase = 0x80001000; ++ write_c0_brcm_bootvec(0xa0088008); ++ write_c0_ebase(new_ebase); ++ if (max_cpus > 2) ++ bmips_write_zscm_reg(0xa0, 0xa008a008); ++ break; ++ default: ++ return; ++ } ++ + board_nmi_handler_setup = &bmips_nmi_handler_setup; + ebase = new_ebase; + } diff --git a/target/linux/brcm63xx/patches-3.13/010-MIPS-BMIPS-merge-CPU-options-into-one-option.patch b/target/linux/brcm63xx/patches-3.13/010-MIPS-BMIPS-merge-CPU-options-into-one-option.patch new file mode 100644 index 0000000000..0bf6db8f40 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/010-MIPS-BMIPS-merge-CPU-options-into-one-option.patch @@ -0,0 +1,137 @@ +From 81d6f5e024884ce904b7bd36fec60291d751df48 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 27 Jun 2013 23:57:20 +0200 +Subject: [PATCH V2 04/13] MIPS: BMIPS: merge CPU options into one option + +Instead of treating each flavour as an exclusive CPU to select, make +BMIPS the only option and let SYS_HAS_CPU_BMIPS* decide for which +flavours to include support. + +Run tested on BMIPS3300 and BMIPS4350, only build tested for BMIPS4380 +and BMIPS5000. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- +V1 -> V2: + * Let the SYS_HAS_CPU_BMIPS* symbols select SYS_HAS_CPU_BMIPS instead of + requiring users to select it + + arch/mips/Kconfig | 80 +++++++++++++++++++++++++++---------------------------- + 1 file changed, 39 insertions(+), 41 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1396,41 +1396,21 @@ config CPU_CAVIUM_OCTEON + can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets. + Full details can be found at http://www.caviumnetworks.com. + +-config CPU_BMIPS3300 +- bool "BMIPS3300" +- depends on SYS_HAS_CPU_BMIPS3300 +- select CPU_BMIPS +- help +- Broadcom BMIPS3300 processors. +- +-config CPU_BMIPS4350 +- bool "BMIPS4350" +- depends on SYS_HAS_CPU_BMIPS4350 +- select CPU_BMIPS +- select SYS_SUPPORTS_SMP +- select SYS_SUPPORTS_HOTPLUG_CPU +- help +- Broadcom BMIPS4350 ("VIPER") processors. +- +-config CPU_BMIPS4380 +- bool "BMIPS4380" +- depends on SYS_HAS_CPU_BMIPS4380 +- select CPU_BMIPS +- select SYS_SUPPORTS_SMP +- select SYS_SUPPORTS_HOTPLUG_CPU +- help +- Broadcom BMIPS4380 processors. +- +-config CPU_BMIPS5000 +- bool "BMIPS5000" +- depends on SYS_HAS_CPU_BMIPS5000 +- select CPU_BMIPS +- select CPU_SUPPORTS_HIGHMEM +- select MIPS_CPU_SCACHE +- select SYS_SUPPORTS_SMP +- select SYS_SUPPORTS_HOTPLUG_CPU ++config CPU_BMIPS ++ bool "Broadcom BMIPS" ++ depends on SYS_HAS_CPU_BMIPS ++ select CPU_MIPS32 ++ select CPU_BMIPS3300 if SYS_HAS_CPU_BMIPS3300 ++ select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350 ++ select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380 ++ select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000 ++ select CPU_SUPPORTS_32BIT_KERNEL ++ select DMA_NONCOHERENT ++ select IRQ_CPU ++ select SWAP_IO_SPACE ++ select WEAK_ORDERING + help +- Broadcom BMIPS5000 processors. ++ Support for BMIPS3300/4350/4380 and BMIPS5000 processors. + + config CPU_XLR + bool "Netlogic XLR SoC" +@@ -1513,14 +1493,25 @@ config CPU_LOONGSON1 + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + +-config CPU_BMIPS ++config CPU_BMIPS3300 + bool +- select CPU_MIPS32 +- select CPU_SUPPORTS_32BIT_KERNEL +- select DMA_NONCOHERENT +- select IRQ_CPU +- select SWAP_IO_SPACE +- select WEAK_ORDERING ++ ++config CPU_BMIPS4350 ++ bool ++ select SYS_SUPPORTS_SMP ++ select SYS_SUPPORTS_HOTPLUG_CPU ++ ++config CPU_BMIPS4380 ++ bool ++ select SYS_SUPPORTS_SMP ++ select SYS_SUPPORTS_HOTPLUG_CPU ++ ++config CPU_BMIPS5000 ++ bool ++ select CPU_SUPPORTS_HIGHMEM ++ select MIPS_CPU_SCACHE ++ select SYS_SUPPORTS_SMP ++ select SYS_SUPPORTS_HOTPLUG_CPU + + config SYS_HAS_CPU_LOONGSON2E + bool +@@ -1594,17 +1585,24 @@ config SYS_HAS_CPU_SB1 + config SYS_HAS_CPU_CAVIUM_OCTEON + bool + ++config SYS_HAS_CPU_BMIPS ++ bool ++ + config SYS_HAS_CPU_BMIPS3300 + bool ++ select SYS_HAS_CPU_BMIPS + + config SYS_HAS_CPU_BMIPS4350 + bool ++ select SYS_HAS_CPU_BMIPS + + config SYS_HAS_CPU_BMIPS4380 + bool ++ select SYS_HAS_CPU_BMIPS + + config SYS_HAS_CPU_BMIPS5000 + bool ++ select SYS_HAS_CPU_BMIPS + + config SYS_HAS_CPU_XLR + bool diff --git a/target/linux/brcm63xx/patches-3.13/011-MIPS-BMIPS-select-CPU_SUPPORTS_HIGHMEM.patch b/target/linux/brcm63xx/patches-3.13/011-MIPS-BMIPS-select-CPU_SUPPORTS_HIGHMEM.patch new file mode 100644 index 0000000000..2c66d566e0 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/011-MIPS-BMIPS-select-CPU_SUPPORTS_HIGHMEM.patch @@ -0,0 +1,30 @@ +From 89d4a38dde99a6b141e90860fca594a9ac66336b Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Tue, 16 Jul 2013 14:02:57 +0200 +Subject: [PATCH V2 05/13] MIPS: BMIPS: select CPU_SUPPORTS_HIGHMEM + +All BMIPS CPUs support HIGHMEM, so it should be selected by CPU_BMIPS. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1409,6 +1409,7 @@ config CPU_BMIPS + select IRQ_CPU + select SWAP_IO_SPACE + select WEAK_ORDERING ++ select CPU_SUPPORTS_HIGHMEM + help + Support for BMIPS3300/4350/4380 and BMIPS5000 processors. + +@@ -1508,7 +1509,6 @@ config CPU_BMIPS4380 + + config CPU_BMIPS5000 + bool +- select CPU_SUPPORTS_HIGHMEM + select MIPS_CPU_SCACHE + select SYS_SUPPORTS_SMP + select SYS_SUPPORTS_HOTPLUG_CPU diff --git a/target/linux/brcm63xx/patches-3.13/012-MIPS-BMIPS-select-CPU_HAS_PREFETCH.patch b/target/linux/brcm63xx/patches-3.13/012-MIPS-BMIPS-select-CPU_HAS_PREFETCH.patch new file mode 100644 index 0000000000..733dc04efd --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/012-MIPS-BMIPS-select-CPU_HAS_PREFETCH.patch @@ -0,0 +1,22 @@ +From 58827e709eb7a2e0899260893a5c9c58eb0c5db1 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Tue, 16 Jul 2013 14:04:40 +0200 +Subject: [PATCH V2 06/13] MIPS: BMIPS: select CPU_HAS_PREFETCH + +As they are MIPS32 CPUs they do support the prefetch opcode. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1410,6 +1410,7 @@ config CPU_BMIPS + select SWAP_IO_SPACE + select WEAK_ORDERING + select CPU_SUPPORTS_HIGHMEM ++ select CPU_HAS_PREFETCH + help + Support for BMIPS3300/4350/4380 and BMIPS5000 processors. + diff --git a/target/linux/brcm63xx/patches-3.13/013-MIPS-BMIPS-extend-BMIPS3300-to-include-BMIPS32.patch b/target/linux/brcm63xx/patches-3.13/013-MIPS-BMIPS-extend-BMIPS3300-to-include-BMIPS32.patch new file mode 100644 index 0000000000..a5667ad202 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/013-MIPS-BMIPS-extend-BMIPS3300-to-include-BMIPS32.patch @@ -0,0 +1,52 @@ +From e742d5b77ec18926293ec5d101470522f67ee159 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 15 Aug 2013 12:10:11 +0200 +Subject: [PATCH V2 07/13] MIPS: BMIPS: extend BMIPS3300 to include BMIPS32 + +Codewise there is no difference between these two, so it does not make +sense to treat them differently. Also chip families having one of these +tend to have the other. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/Kconfig | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1400,7 +1400,7 @@ config CPU_BMIPS + bool "Broadcom BMIPS" + depends on SYS_HAS_CPU_BMIPS + select CPU_MIPS32 +- select CPU_BMIPS3300 if SYS_HAS_CPU_BMIPS3300 ++ select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300 + select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350 + select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380 + select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000 +@@ -1412,7 +1412,7 @@ config CPU_BMIPS + select CPU_SUPPORTS_HIGHMEM + select CPU_HAS_PREFETCH + help +- Support for BMIPS3300/4350/4380 and BMIPS5000 processors. ++ Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors. + + config CPU_XLR + bool "Netlogic XLR SoC" +@@ -1495,7 +1495,7 @@ config CPU_LOONGSON1 + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + +-config CPU_BMIPS3300 ++config CPU_BMIPS32_3300 + bool + + config CPU_BMIPS4350 +@@ -1589,7 +1589,7 @@ config SYS_HAS_CPU_CAVIUM_OCTEON + config SYS_HAS_CPU_BMIPS + bool + +-config SYS_HAS_CPU_BMIPS3300 ++config SYS_HAS_CPU_BMIPS32_3300 + bool + select SYS_HAS_CPU_BMIPS + diff --git a/target/linux/brcm63xx/patches-3.13/014-MIPS-BMIPS-add-a-smp-ops-registration-helper.patch b/target/linux/brcm63xx/patches-3.13/014-MIPS-BMIPS-add-a-smp-ops-registration-helper.patch new file mode 100644 index 0000000000..c236075275 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/014-MIPS-BMIPS-add-a-smp-ops-registration-helper.patch @@ -0,0 +1,77 @@ +From 0b135a3e8f344061ed0aa66e2514627dd7aa946f Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 23 Jun 2013 14:04:51 +0200 +Subject: [PATCH V2 08/13] MIPS: BMIPS: add a smp ops registration helper + +Add a helper similar to the generic register_XXX_smp_ops() for bmips. +Register SMP UP ops in case of BMIPS32/3300. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- +V1 -> V2: + * use SMP_UP (ops) in case of BMIPS32_3300 + + arch/mips/Kconfig | 1 + + arch/mips/bcm63xx/prom.c | 2 +- + arch/mips/include/asm/bmips.h | 26 ++++++++++++++++++++++++++ + 3 files changed, 28 insertions(+), 1 deletion(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1496,6 +1496,7 @@ config CPU_LOONGSON1 + select CPU_SUPPORTS_HIGHMEM + + config CPU_BMIPS32_3300 ++ select SMP_UP if SMP + bool + + config CPU_BMIPS4350 +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -61,7 +61,7 @@ void __init prom_init(void) + + if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) { + /* set up SMP */ +- register_smp_ops(&bmips43xx_smp_ops); ++ register_bmips_smp_ops(); + + /* + * BCM6328 might not have its second CPU enabled, while BCM3368 +--- a/arch/mips/include/asm/bmips.h ++++ b/arch/mips/include/asm/bmips.h +@@ -46,9 +46,35 @@ + + #include <linux/cpumask.h> + #include <asm/r4kcache.h> ++#include <asm/smp-ops.h> + + extern struct plat_smp_ops bmips43xx_smp_ops; + extern struct plat_smp_ops bmips5000_smp_ops; ++ ++static inline int register_bmips_smp_ops(void) ++{ ++#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP) ++ switch (current_cpu_type()) { ++ case CPU_BMIPS32: ++ case CPU_BMIPS3300: ++ return register_up_smp_ops(); ++ case CPU_BMIPS4350: ++ case CPU_BMIPS4380: ++ register_smp_ops(&bmips43xx_smp_ops); ++ break; ++ case CPU_BMIPS5000: ++ register_smp_ops(&bmips5000_smp_ops); ++ break; ++ default: ++ return -ENODEV; ++ } ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} ++ + extern char bmips_reset_nmi_vec; + extern char bmips_reset_nmi_vec_end; + extern char bmips_smp_movevec; diff --git a/target/linux/brcm63xx/patches-3.13/015-MIPS-BCM63XX-always-register-bmips-smp-ops.patch b/target/linux/brcm63xx/patches-3.13/015-MIPS-BCM63XX-always-register-bmips-smp-ops.patch new file mode 100644 index 0000000000..659018505e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/015-MIPS-BCM63XX-always-register-bmips-smp-ops.patch @@ -0,0 +1,27 @@ +From 08181bee8ee375225129d086656c567022becf41 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Fri, 28 Jun 2013 00:08:16 +0200 +Subject: [PATCH V2 09/13] MIPS: BCM63XX: always register bmips smp ops + +Use the return value for guarding further SMP setup. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/prom.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -59,10 +59,8 @@ void __init prom_init(void) + /* do low level board init */ + board_prom_init(); + +- if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) { +- /* set up SMP */ +- register_bmips_smp_ops(); +- ++ /* set up SMP */ ++ if (!register_bmips_smp_ops()) { + /* + * BCM6328 might not have its second CPU enabled, while BCM3368 + * and BCM6358 need special handling for their shared TLB, so diff --git a/target/linux/brcm63xx/patches-3.13/016-MIPS-BCM63XX-let-the-individual-SoCs-select-the-appr.patch b/target/linux/brcm63xx/patches-3.13/016-MIPS-BCM63XX-let-the-individual-SoCs-select-the-appr.patch new file mode 100644 index 0000000000..9c17a7bf35 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/016-MIPS-BCM63XX-let-the-individual-SoCs-select-the-appr.patch @@ -0,0 +1,70 @@ +From 949b88531a779af4f6456ff43d3de2d4f74e44ee Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 23 Jun 2013 12:25:49 +0200 +Subject: [PATCH V2 10/13] MIPS: BCM63XX: let the individual SoCs select the + appropriate CPUs + +Let each supported chip select the appropirate SYS_HAS_CPU_BMIPS* +option for its embedded processor, so support will be conditionally +included. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/Kconfig | 1 - + arch/mips/bcm63xx/Kconfig | 8 ++++++++ + 2 files changed, 8 insertions(+), 1 deletion(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -133,7 +133,6 @@ config BCM63XX + select DMA_NONCOHERENT + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 +- select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_HAS_EARLY_PRINTK +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -3,33 +3,41 @@ menu "CPU support" + + config BCM63XX_CPU_3368 + bool "support 3368 CPU" ++ select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + + config BCM63XX_CPU_6328 + bool "support 6328 CPU" ++ select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + + config BCM63XX_CPU_6338 + bool "support 6338 CPU" ++ select SYS_HAS_CPU_BMIPS32_3300 + select HW_HAS_PCI + + config BCM63XX_CPU_6345 + bool "support 6345 CPU" ++ select SYS_HAS_CPU_BMIPS32_3300 + + config BCM63XX_CPU_6348 + bool "support 6348 CPU" ++ select SYS_HAS_CPU_BMIPS32_3300 + select HW_HAS_PCI + + config BCM63XX_CPU_6358 + bool "support 6358 CPU" ++ select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + + config BCM63XX_CPU_6362 + bool "support 6362 CPU" ++ select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + + config BCM63XX_CPU_6368 + bool "support 6368 CPU" ++ select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + endmenu + diff --git a/target/linux/brcm63xx/patches-3.13/017-MIPS-cpu-type-guard-BMIPS-variants-with-SYS_HAS_CPU_.patch b/target/linux/brcm63xx/patches-3.13/017-MIPS-cpu-type-guard-BMIPS-variants-with-SYS_HAS_CPU_.patch new file mode 100644 index 0000000000..96e6dfbc69 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/017-MIPS-cpu-type-guard-BMIPS-variants-with-SYS_HAS_CPU_.patch @@ -0,0 +1,44 @@ +From c515f21d7680015bc94e0c081b73aba5a3d74680 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 17 Oct 2013 13:14:48 +0200 +Subject: [PATCH V2 12/13] MIPS: cpu-type: guard BMIPS variants with + SYS_HAS_CPU_BMIPS* + +BMIPS32 and BMIPS3300 also need to be available for MIPS32R1, as +bcm47xx might not select BMIPS. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/include/asm/cpu-type.h | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +--- a/arch/mips/include/asm/cpu-type.h ++++ b/arch/mips/include/asm/cpu-type.h +@@ -27,10 +27,7 @@ static inline int __pure __get_cpu_type( + #ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1 + case CPU_4KC: + case CPU_ALCHEMY: +- case CPU_BMIPS3300: +- case CPU_BMIPS4350: + case CPU_PR4450: +- case CPU_BMIPS32: + case CPU_JZRISC: + #endif + +@@ -163,6 +160,16 @@ static inline int __pure __get_cpu_type( + case CPU_CAVIUM_OCTEON2: + #endif + ++#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \ ++ defined (CONFIG_SYS_HAS_CPU_MIPS32_R1) ++ case CPU_BMIPS32: ++ case CPU_BMIPS3300: ++#endif ++ ++#ifdef CONFIG_SYS_HAS_CPU_BMIPS4350 ++ case CPU_BMIPS4350: ++#endif ++ + #ifdef CONFIG_SYS_HAS_CPU_BMIPS4380 + case CPU_BMIPS4380: + #endif diff --git a/target/linux/brcm63xx/patches-3.13/018-MIPS-BCM63XX-drop-SYS_HAS_CPU_MIPS32R1.patch b/target/linux/brcm63xx/patches-3.13/018-MIPS-BCM63XX-drop-SYS_HAS_CPU_MIPS32R1.patch new file mode 100644 index 0000000000..0337697d23 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/018-MIPS-BCM63XX-drop-SYS_HAS_CPU_MIPS32R1.patch @@ -0,0 +1,24 @@ +From c6c4897703d825c9efea6d9a708aaa080c8c3177 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 17 Oct 2013 13:16:08 +0200 +Subject: [PATCH V2 13/13] MIPS: BCM63XX: drop SYS_HAS_CPU_MIPS32R1 + +All MIPS cores on BCM63XX identify as Broadcom, not MIPS, so no need +to support non-broadcom MIPS CPUs. This also ensures that CPU_BMIPS +is always selected. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -132,7 +132,6 @@ config BCM63XX + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU +- select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_HAS_EARLY_PRINTK diff --git a/target/linux/brcm63xx/patches-3.13/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch b/target/linux/brcm63xx/patches-3.13/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch new file mode 100644 index 0000000000..63d385be4e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch @@ -0,0 +1,28 @@ +From 80a2f983e9f44dbc3e01ae31c62d877846a7f791 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:19 +0100 +Subject: [PATCH 01/11] MIPS: BCM63XX: add USB host clock enable delay + +Knowledge of the clock setup delay should remain at the clock level (so +it can be clock specific and CPU specific). Add the 100 milliseconds +required clock delay for the USB host clock when it gets enabled. + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/clk.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -177,6 +177,11 @@ static void usbh_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); ++ else ++ return; ++ ++ if (enable) ++ msleep(100); + } + + static struct clk clk_usbh = { diff --git a/target/linux/brcm63xx/patches-3.13/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch b/target/linux/brcm63xx/patches-3.13/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch new file mode 100644 index 0000000000..eaf75030f0 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch @@ -0,0 +1,41 @@ +From 8e9bf528a122741f0171b89c297b63041116d704 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:20 +0100 +Subject: [PATCH 02/11] MIPS: BCM63XX: add USB device clock enable delay to + clock code + +This patch adds the required 10 micro seconds delay to the USB device +clock enable operation. Put this where the correct clock knowledege is, +which is in the clock code, and remove this delay from the bcm63xx_udc +gadget driver where it was before. + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/clk.c | 5 +++++ + drivers/usb/gadget/bcm63xx_udc.c | 1 - + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -199,6 +199,11 @@ static void usbd_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBD_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); ++ else ++ return; ++ ++ if (enable) ++ udelay(10); + } + + static struct clk clk_usbd = { +--- a/drivers/usb/gadget/bcm63xx_udc.c ++++ b/drivers/usb/gadget/bcm63xx_udc.c +@@ -386,7 +386,6 @@ static inline void set_clocks(struct bcm + if (is_enabled) { + clk_enable(udc->usbh_clk); + clk_enable(udc->usbd_clk); +- udelay(10); + } else { + clk_disable(udc->usbd_clk); + clk_disable(udc->usbh_clk); diff --git a/target/linux/brcm63xx/patches-3.13/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch b/target/linux/brcm63xx/patches-3.13/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch new file mode 100644 index 0000000000..88217bd656 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch @@ -0,0 +1,151 @@ +From ac9b0b574d54be28b300bf99ffe092a2c589484f Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:21 +0100 +Subject: [PATCH 03/11] MIPS: BCM63XX: move code touching the USB private + register + +This patch moves the code touching the USB private register in the +bcm63xx USB gadget driver to arch/mips/bcm63xx/usb-common.c in +preparation for adding support for OHCI and EHCI host controllers which +will also touch the USB private register. + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/usb-common.c | 53 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h | 9 ++++ + drivers/usb/gadget/bcm63xx_udc.c | 27 ++-------- + 4 files changed, 67 insertions(+), 24 deletions(-) + create mode 100644 arch/mips/bcm63xx/usb-common.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,7 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ +- dev-wdt.o dev-usb-usbd.o ++ dev-wdt.o dev-usb-usbd.o usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -0,0 +1,53 @@ ++/* ++ * Broadcom BCM63xx common USB device configuration code ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com> ++ * Copyright (C) 2012 Broadcom Corporation ++ * ++ */ ++#include <linux/export.h> ++ ++#include <bcm63xx_cpu.h> ++#include <bcm63xx_regs.h> ++#include <bcm63xx_io.h> ++#include <bcm63xx_usb_priv.h> ++ ++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device) ++{ ++ u32 val; ++ ++ val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); ++ if (is_device) { ++ val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); ++ val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ } else { ++ val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); ++ val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ } ++ bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++ ++ val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ if (is_device) ++ val |= USBH_PRIV_SWAP_USBD_MASK; ++ else ++ val &= ~USBH_PRIV_SWAP_USBD_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); ++} ++EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode); ++ ++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on) ++{ ++ u32 val; ++ ++ val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); ++ if (is_on) ++ val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ else ++ val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++} ++EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup); +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h +@@ -0,0 +1,9 @@ ++#ifndef BCM63XX_USB_PRIV_H_ ++#define BCM63XX_USB_PRIV_H_ ++ ++#include <linux/types.h> ++ ++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device); ++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on); ++ ++#endif /* BCM63XX_USB_PRIV_H_ */ +--- a/drivers/usb/gadget/bcm63xx_udc.c ++++ b/drivers/usb/gadget/bcm63xx_udc.c +@@ -41,6 +41,7 @@ + #include <bcm63xx_dev_usb_usbd.h> + #include <bcm63xx_io.h> + #include <bcm63xx_regs.h> ++#include <bcm63xx_usb_priv.h> + + #define DRV_MODULE_NAME "bcm63xx_udc" + +@@ -863,22 +864,7 @@ static void bcm63xx_select_phy_mode(stru + bcm_gpio_writel(val, GPIO_PINMUX_OTHR_REG); + } + +- val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); +- if (is_device) { +- val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); +- val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- } else { +- val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); +- val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- } +- bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); +- +- val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); +- if (is_device) +- val |= USBH_PRIV_SWAP_USBD_MASK; +- else +- val &= ~USBH_PRIV_SWAP_USBD_MASK; +- bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); ++ bcm63xx_usb_priv_select_phy_mode(portmask, is_device); + } + + /** +@@ -892,14 +878,9 @@ static void bcm63xx_select_phy_mode(stru + */ + static void bcm63xx_select_pullup(struct bcm63xx_udc *udc, bool is_on) + { +- u32 val, portmask = BIT(udc->pd->port_no); ++ u32 portmask = BIT(udc->pd->port_no); + +- val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); +- if (is_on) +- val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- else +- val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++ bcm63xx_usb_priv_select_pullup(portmask, is_on); + } + + /** diff --git a/target/linux/brcm63xx/patches-3.13/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch b/target/linux/brcm63xx/patches-3.13/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch new file mode 100644 index 0000000000..40bbe083a7 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch @@ -0,0 +1,169 @@ +From 28758a9da77954ed323f86123ef448c6a563c037 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:22 +0100 +Subject: [PATCH 04/11] MIPS: BCM63XX: add OHCI/EHCI configuration bits to + common USB code + +This patch updates the common USB code touching the USB private +registers with the specific bits to properly enable OHCI and EHCI +controllers on BCM63xx SoCs. As a result we now need to protect access +to Read Modify Write sequences using a spinlock because we cannot +guarantee that any of the exposed helper will not be called +concurrently. + +Signed-off-by: Maxime Bizon <mbizon@freebox.fr> +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/usb-common.c | 97 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h | 2 + + 2 files changed, 99 insertions(+) + +--- a/arch/mips/bcm63xx/usb-common.c ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -5,10 +5,12 @@ + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * ++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> + * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com> + * Copyright (C) 2012 Broadcom Corporation + * + */ ++#include <linux/spinlock.h> + #include <linux/export.h> + + #include <bcm63xx_cpu.h> +@@ -16,9 +18,14 @@ + #include <bcm63xx_io.h> + #include <bcm63xx_usb_priv.h> + ++static DEFINE_SPINLOCK(usb_priv_reg_lock); ++ + void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device) + { + u32 val; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); + + val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); + if (is_device) { +@@ -36,12 +43,17 @@ void bcm63xx_usb_priv_select_phy_mode(u3 + else + val &= ~USBH_PRIV_SWAP_USBD_MASK; + bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); + } + EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode); + + void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on) + { + u32 val; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); + + val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); + if (is_on) +@@ -49,5 +61,90 @@ void bcm63xx_usb_priv_select_pullup(u32 + else + val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); + bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); + } + EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup); ++ ++/* The following array represents the meaning of the DESC/DATA ++ * endian swapping with respect to the CPU configured endianness ++ * ++ * DATA ENDN mmio descriptor ++ * 0 0 BE invalid ++ * 0 1 BE LE ++ * 1 0 BE BE ++ * 1 1 BE invalid ++ * ++ * Since BCM63XX SoCs are configured to be in big-endian mode ++ * we want configuration at line 3. ++ */ ++void bcm63xx_usb_priv_ohci_cfg_set(void) ++{ ++ u32 reg; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); ++ ++ if (BCMCPU_IS_6348()) ++ bcm_rset_writel(RSET_OHCI_PRIV, 0, OHCI_PRIV_REG); ++ else if (BCMCPU_IS_6358()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG); ++ /* ++ * The magic value comes for the original vendor BSP ++ * and is needed for USB to work. Datasheet does not ++ * help, so the magic value is used as-is. ++ */ ++ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, ++ USBH_PRIV_TEST_6358_REG); ++ ++ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); ++} ++ ++void bcm63xx_usb_priv_ehci_cfg_set(void) ++{ ++ u32 reg; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); ++ ++ if (BCMCPU_IS_6358()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG); ++ ++ /* ++ * The magic value comes for the original vendor BSP ++ * and is needed for USB to work. Datasheet does not ++ * help, so the magic value is used as-is. ++ */ ++ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, ++ USBH_PRIV_TEST_6358_REG); ++ ++ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); ++} +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h +@@ -5,5 +5,7 @@ + + void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device); + void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on); ++void bcm63xx_usb_priv_ohci_cfg_set(void); ++void bcm63xx_usb_priv_ehci_cfg_set(void); + + #endif /* BCM63XX_USB_PRIV_H_ */ diff --git a/target/linux/brcm63xx/patches-3.13/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch b/target/linux/brcm63xx/patches-3.13/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch new file mode 100644 index 0000000000..768dccac5e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch @@ -0,0 +1,62 @@ +From 94ec618bd1a6b07fafbbfc9bcc54e7f9360ff9a0 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:23 +0100 +Subject: [PATCH 05/11] MIPS: BCM63XX: introduce BCM63XX_OHCI configuration + symbol + +This configuration symbol can be used by CPUs supporting the on-chip +OHCI controller, and ensures that all relevant OHCI-related +configuration options are correctly selected. So far, OHCI support is +available for the 6328, 6348, 6358 and 6358 SoCs. + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/Kconfig | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -6,10 +6,17 @@ config BCM63XX_CPU_3368 + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + ++config BCM63XX_OHCI ++ bool ++ select USB_ARCH_HAS_OHCI ++ select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD ++ select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD ++ + config BCM63XX_CPU_6328 + bool "support 6328 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6338 + bool "support 6338 CPU" +@@ -24,21 +31,25 @@ config BCM63XX_CPU_6348 + bool "support 6348 CPU" + select SYS_HAS_CPU_BMIPS32_3300 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6358 + bool "support 6358 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6362 + bool "support 6362 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6368 + bool "support 6368 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" diff --git a/target/linux/brcm63xx/patches-3.13/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch b/target/linux/brcm63xx/patches-3.13/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch new file mode 100644 index 0000000000..111d481e54 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch @@ -0,0 +1,138 @@ +From 30d22baef255c99a12c4858ce4ab0d45f0d8c9ae Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:24 +0100 +Subject: [PATCH 06/11] MIPS: BCM63XX: add support for the on-chip OHCI + controller + +Broadcom BCM63XX SoCs include an on-chip OHCI controller which can be +driven by the ohci-platform generic driver by using specific power +on/off/suspend callback to manage clocks and hardware specific +configuration. + +Signed-off-by: Maxime Bizon <mbizon@freebox.fr> +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/dev-usb-ohci.c | 94 ++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h | 6 ++ + 3 files changed, 101 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/dev-usb-ohci.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,7 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ +- dev-wdt.o dev-usb-usbd.o usb-common.o ++ dev-wdt.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/dev-usb-ohci.c +@@ -0,0 +1,94 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> ++ * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org> ++ */ ++ ++#include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/platform_device.h> ++#include <linux/usb/ohci_pdriver.h> ++#include <linux/dma-mapping.h> ++#include <linux/clk.h> ++#include <linux/delay.h> ++ ++#include <bcm63xx_cpu.h> ++#include <bcm63xx_regs.h> ++#include <bcm63xx_io.h> ++#include <bcm63xx_usb_priv.h> ++#include <bcm63xx_dev_usb_ohci.h> ++ ++static struct resource ohci_resources[] = { ++ { ++ .start = -1, /* filled at runtime */ ++ .end = -1, /* filled at runtime */ ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = -1, /* filled at runtime */ ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ohci_dmamask = DMA_BIT_MASK(32); ++ ++static struct clk *usb_host_clock; ++ ++static int bcm63xx_ohci_power_on(struct platform_device *pdev) ++{ ++ usb_host_clock = clk_get(&pdev->dev, "usbh"); ++ if (IS_ERR_OR_NULL(usb_host_clock)) ++ return -ENODEV; ++ ++ clk_prepare_enable(usb_host_clock); ++ ++ bcm63xx_usb_priv_ohci_cfg_set(); ++ ++ return 0; ++} ++ ++static void bcm63xx_ohci_power_off(struct platform_device *pdev) ++{ ++ if (!IS_ERR_OR_NULL(usb_host_clock)) { ++ clk_disable_unprepare(usb_host_clock); ++ clk_put(usb_host_clock); ++ } ++} ++ ++static struct usb_ohci_pdata bcm63xx_ohci_pdata = { ++ .big_endian_desc = 1, ++ .big_endian_mmio = 1, ++ .no_big_frame_no = 1, ++ .num_ports = 1, ++ .power_on = bcm63xx_ohci_power_on, ++ .power_off = bcm63xx_ohci_power_off, ++ .power_suspend = bcm63xx_ohci_power_off, ++}; ++ ++static struct platform_device bcm63xx_ohci_device = { ++ .name = "ohci-platform", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(ohci_resources), ++ .resource = ohci_resources, ++ .dev = { ++ .platform_data = &bcm63xx_ohci_pdata, ++ .dma_mask = &ohci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++int __init bcm63xx_ohci_register(void) ++{ ++ if (BCMCPU_IS_6345() || BCMCPU_IS_6338()) ++ return -ENODEV; ++ ++ ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0); ++ ohci_resources[0].end = ohci_resources[0].start; ++ ohci_resources[0].end += RSET_OHCI_SIZE - 1; ++ ohci_resources[1].start = bcm63xx_get_irq_number(IRQ_OHCI0); ++ ++ return platform_device_register(&bcm63xx_ohci_device); ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h +@@ -0,0 +1,6 @@ ++#ifndef BCM63XX_DEV_USB_OHCI_H_ ++#define BCM63XX_DEV_USB_OHCI_H_ ++ ++int bcm63xx_ohci_register(void); ++ ++#endif /* BCM63XX_DEV_USB_OHCI_H_ */ diff --git a/target/linux/brcm63xx/patches-3.13/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch b/target/linux/brcm63xx/patches-3.13/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch new file mode 100644 index 0000000000..2c264829fb --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch @@ -0,0 +1,36 @@ +From 33ef960aed15f9a98a2c51d8d794cd72418e0be4 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:25 +0100 +Subject: [PATCH 07/11] MIPS: BCM63XX: register OHCI controller if board + enables it + +BCM63XX-based boards can control the registration of the OHCI controller +by setting their has_ohci0 flag to 1. Handle this in the generic +code dealing with board registration and call the actual helper to +register the OHCI controller. + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -26,6 +26,7 @@ + #include <bcm63xx_dev_hsspi.h> + #include <bcm63xx_dev_pcmcia.h> + #include <bcm63xx_dev_spi.h> ++#include <bcm63xx_dev_usb_ohci.h> + #include <bcm63xx_dev_usb_usbd.h> + #include <board_bcm963xx.h> + +@@ -898,6 +899,9 @@ int __init board_register_devices(void) + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + ++ if (board.has_ohci0) ++ bcm63xx_ohci_register(); ++ + if (board.has_dsp) + bcm63xx_dsp_register(&board.dsp); + diff --git a/target/linux/brcm63xx/patches-3.13/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch b/target/linux/brcm63xx/patches-3.13/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch new file mode 100644 index 0000000000..bce91e3736 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch @@ -0,0 +1,62 @@ +From 00da1683364e58c6430a4577123d01037f8faddc Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:26 +0100 +Subject: [PATCH 08/11] MIPS: BCM63XX: introduce BCM63XX_EHCI configuration + symbol + +This configuration symbol can be used by CPUs supporting the on-chip +EHCI controller, and ensures that all relevant EHCI-related +configuration options are selected. So far BCM6328, BCM6358 and BCM6368 +have an EHCI controller and do select this symbol. Update +drivers/usb/host/Kconfig with BCM63XX to update direct unmet +dependencies. + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/Kconfig | 9 +++++++++ + drivers/usb/host/Kconfig | 5 +++-- + 2 files changed, 12 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -12,11 +12,18 @@ config BCM63XX_OHCI + select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD + select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD + ++config BCM63XX_EHCI ++ bool ++ select USB_ARCH_HAS_EHCI ++ select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD ++ select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD ++ + config BCM63XX_CPU_6328 + bool "support 6328 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6338 + bool "support 6338 CPU" +@@ -38,18 +45,21 @@ config BCM63XX_CPU_6358 + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6362 + bool "support 6362 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6368 + bool "support 6368 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" diff --git a/target/linux/brcm63xx/patches-3.13/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch b/target/linux/brcm63xx/patches-3.13/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch new file mode 100644 index 0000000000..8b1f8d22b8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch @@ -0,0 +1,137 @@ +From e38f13bd6408769c0b565bb1079024f496eee121 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:27 +0100 +Subject: [PATCH 09/11] MIPS: BCM63XX: add support for the on-chip EHCI + controller + +Broadcom BCM63XX SoCs include an on-chip EHCI controller which can be +driven by the generic ehci-platform driver by using specific power +on/off/suspend callbacks to manage clocks and hardware specific +configuration. + +Signed-off-by: Maxime Bizon <mbizon@freebox.fr> +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/dev-usb-ehci.c | 92 ++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h | 6 ++ + 3 files changed, 99 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/dev-usb-ehci.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,8 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ +- dev-wdt.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o ++ dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ ++ usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -0,0 +1,92 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> ++ * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org> ++ */ ++ ++#include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/platform_device.h> ++#include <linux/clk.h> ++#include <linux/delay.h> ++#include <linux/usb/ehci_pdriver.h> ++#include <linux/dma-mapping.h> ++ ++#include <bcm63xx_cpu.h> ++#include <bcm63xx_regs.h> ++#include <bcm63xx_io.h> ++#include <bcm63xx_usb_priv.h> ++#include <bcm63xx_dev_usb_ehci.h> ++ ++static struct resource ehci_resources[] = { ++ { ++ .start = -1, /* filled at runtime */ ++ .end = -1, /* filled at runtime */ ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = -1, /* filled at runtime */ ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ehci_dmamask = DMA_BIT_MASK(32); ++ ++static struct clk *usb_host_clock; ++ ++static int bcm63xx_ehci_power_on(struct platform_device *pdev) ++{ ++ usb_host_clock = clk_get(&pdev->dev, "usbh"); ++ if (IS_ERR_OR_NULL(usb_host_clock)) ++ return -ENODEV; ++ ++ clk_prepare_enable(usb_host_clock); ++ ++ bcm63xx_usb_priv_ehci_cfg_set(); ++ ++ return 0; ++} ++ ++static void bcm63xx_ehci_power_off(struct platform_device *pdev) ++{ ++ if (!IS_ERR_OR_NULL(usb_host_clock)) { ++ clk_disable_unprepare(usb_host_clock); ++ clk_put(usb_host_clock); ++ } ++} ++ ++static struct usb_ehci_pdata bcm63xx_ehci_pdata = { ++ .big_endian_desc = 1, ++ .big_endian_mmio = 1, ++ .power_on = bcm63xx_ehci_power_on, ++ .power_off = bcm63xx_ehci_power_off, ++ .power_suspend = bcm63xx_ehci_power_off, ++}; ++ ++static struct platform_device bcm63xx_ehci_device = { ++ .name = "ehci-platform", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(ehci_resources), ++ .resource = ehci_resources, ++ .dev = { ++ .platform_data = &bcm63xx_ehci_pdata, ++ .dma_mask = &ehci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++int __init bcm63xx_ehci_register(void) ++{ ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ return 0; ++ ++ ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); ++ ehci_resources[0].end = ehci_resources[0].start; ++ ehci_resources[0].end += RSET_EHCI_SIZE - 1; ++ ehci_resources[1].start = bcm63xx_get_irq_number(IRQ_EHCI0); ++ ++ return platform_device_register(&bcm63xx_ehci_device); ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h +@@ -0,0 +1,6 @@ ++#ifndef BCM63XX_DEV_USB_EHCI_H_ ++#define BCM63XX_DEV_USB_EHCI_H_ ++ ++int bcm63xx_ehci_register(void); ++ ++#endif /* BCM63XX_DEV_USB_EHCI_H_ */ diff --git a/target/linux/brcm63xx/patches-3.13/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch b/target/linux/brcm63xx/patches-3.13/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch new file mode 100644 index 0000000000..641a57c4c0 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch @@ -0,0 +1,36 @@ +From 709ef2034f5ba06da35f89856ad7baf2b7a41287 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:28 +0100 +Subject: [PATCH 10/11] MIPS: BCM63XX: register EHCI controller if board + enables it + +BCM63XX-based board can control the registration of the EHCI controller +by setting their has_ehci0 flag to 1. Handle this in the generic +code dealing with board registration and call the actual helper to register +the EHCI controller. + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -26,6 +26,7 @@ + #include <bcm63xx_dev_hsspi.h> + #include <bcm63xx_dev_pcmcia.h> + #include <bcm63xx_dev_spi.h> ++#include <bcm63xx_dev_usb_ehci.h> + #include <bcm63xx_dev_usb_ohci.h> + #include <bcm63xx_dev_usb_usbd.h> + #include <board_bcm963xx.h> +@@ -899,6 +900,9 @@ int __init board_register_devices(void) + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + ++ if (board.has_ehci0) ++ bcm63xx_ehci_register(); ++ + if (board.has_ohci0) + bcm63xx_ohci_register(); + diff --git a/target/linux/brcm63xx/patches-3.13/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch b/target/linux/brcm63xx/patches-3.13/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch new file mode 100644 index 0000000000..6d91129932 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch @@ -0,0 +1,24 @@ +From 111bbd770441ab34f9da5bb1d85767a9b75227b4 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Mon, 28 Jan 2013 20:06:30 +0100 +Subject: [PATCH 12/12] MIPS: BCM63XX: EHCI controller does not support + overcurrent + +This patch sets the ignore_oc flag for the BCM63XX EHCI controller as it +does not support proper overcurrent reporting. + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/bcm63xx/dev-usb-ehci.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -61,6 +61,7 @@ static void bcm63xx_ehci_power_off(struc + static struct usb_ehci_pdata bcm63xx_ehci_pdata = { + .big_endian_desc = 1, + .big_endian_mmio = 1, ++ .ignore_oc = 1, + .power_on = bcm63xx_ehci_power_on, + .power_off = bcm63xx_ehci_power_off, + .power_suspend = bcm63xx_ehci_power_off, diff --git a/target/linux/brcm63xx/patches-3.13/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch b/target/linux/brcm63xx/patches-3.13/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch new file mode 100644 index 0000000000..00dc9c90ee --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch @@ -0,0 +1,38 @@ +From 3f650fc30aa0badf9d02842ce396cea3eef2eeaa Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Fri, 1 Jul 2011 23:16:47 +0200 +Subject: [PATCH 49/79] SPI: Allow specifying the parsers for SPI flash + +Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> +--- + include/linux/spi/flash.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -2,7 +2,7 @@ + #define LINUX_SPI_FLASH_H + + struct mtd_partition; +- ++struct mtd_part_parser_data; + /** + * struct flash_platform_data: board-specific flash data + * @name: optional flash device name (eg, as used with mtdparts=) +@@ -10,6 +10,8 @@ struct mtd_partition; + * @nr_parts: number of mtd_partitions for static partitoning + * @type: optional flash device type (e.g. m25p80 vs m25p64), for use + * with chips that can't be queried for JEDEC or other IDs ++ * @part_probe_types: optional list of MTD parser names to use for ++ * partitioning + * + * Board init code (in arch/.../mach-xxx/board-yyy.c files) can + * provide information about SPI flash parts (such as DataFlash) to +@@ -25,6 +27,7 @@ struct flash_platform_data { + + char *type; + ++ const char **part_probe_types; + /* we'll likely add more ... use JEDEC IDs, etc */ + }; + diff --git a/target/linux/brcm63xx/patches-3.13/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch b/target/linux/brcm63xx/patches-3.13/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch new file mode 100644 index 0000000000..2396aeb75b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch @@ -0,0 +1,23 @@ +From c7c3c338cb25d7f55ddb3f6bfbf3572758ca3896 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Thu, 10 Nov 2011 16:53:08 +0100 +Subject: [PATCH 50/79] MTD: DEVICES: m25p80: use parsers if provided in flash + platform data + +Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> +--- + drivers/mtd/devices/m25p80.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -1124,7 +1124,8 @@ static int m25p_probe(struct spi_device + /* partitions should match sector boundaries; and it may be good to + * use readonly partitions for writeprotected sectors (BP2..BP0). + */ +- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, ++ return mtd_device_parse_register(&flash->mtd, ++ data ? data->part_probe_types : NULL, &ppdata, + data ? data->parts : NULL, + data ? data->nr_parts : 0); + } diff --git a/target/linux/brcm63xx/patches-3.13/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch b/target/linux/brcm63xx/patches-3.13/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch new file mode 100644 index 0000000000..c2842c163b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch @@ -0,0 +1,92 @@ +From 5fb4e8d7287ac8fcb33aae8b1e9e22c5a3c392bd Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Thu, 10 Nov 2011 17:33:40 +0100 +Subject: [PATCH 51/79] MTD: DEVICES: m25p80: add support for limiting reads + +Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> +--- + drivers/mtd/devices/m25p80.c | 29 +++++++++++++++++++++++++++-- + include/linux/spi/flash.h | 4 ++++ + 2 files changed, 31 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -101,6 +101,7 @@ struct m25p { + u8 program_opcode; + u8 *command; + bool fast_read; ++ int max_transfer_len; + }; + + static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) +@@ -359,10 +360,9 @@ static int m25p80_erase(struct mtd_info + * Read an address range from the flash chip. The address range + * may be any size provided it is within the physical boundaries. + */ +-static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, ++static int __m25p80_read(struct m25p *flash, loff_t from, size_t len, + size_t *retlen, u_char *buf) + { +- struct m25p *flash = mtd_to_m25p(mtd); + struct spi_transfer t[2]; + struct spi_message m; + uint8_t opcode; +@@ -405,6 +405,28 @@ static int m25p80_read(struct mtd_info * + return 0; + } + ++static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct m25p *flash = mtd_to_m25p(mtd); ++ size_t off; ++ size_t read_len = flash->max_transfer_len; ++ size_t part_len; ++ int ret = 0; ++ ++ if (!read_len) ++ return __m25p80_read(flash, from, len, retlen, buf); ++ ++ *retlen = 0; ++ ++ for (off = 0; off < len && !ret; off += read_len) { ++ ret = __m25p80_read(flash, from + off, min(len - off, read_len), ++ &part_len, buf + off); ++ *retlen += part_len; ++ } ++ ++ return ret; ++} + /* + * Write an address range to the flash chip. Data must be written in + * FLASH_PAGESIZE chunks. The address range may be any size provided +@@ -1001,6 +1023,9 @@ static int m25p_probe(struct spi_device + if (!flash->command) + return -ENOMEM; + ++ if (data) ++ flash->max_transfer_len = data->max_transfer_len; ++ + flash->spi = spi; + mutex_init(&flash->lock); + spi_set_drvdata(spi, flash); +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -13,6 +13,8 @@ struct mtd_part_parser_data; + * @part_probe_types: optional list of MTD parser names to use for + * partitioning + * ++ * @max_transfer_len: option maximum read/write length limitation for ++ * SPI controllers not able to transfer any length commands. + * Board init code (in arch/.../mach-xxx/board-yyy.c files) can + * provide information about SPI flash parts (such as DataFlash) to + * help set up the device and its appropriate default partitioning. +@@ -28,6 +30,8 @@ struct flash_platform_data { + char *type; + + const char **part_probe_types; ++ ++ unsigned int max_transfer_len; + /* we'll likely add more ... use JEDEC IDs, etc */ + }; + diff --git a/target/linux/brcm63xx/patches-3.13/204-USB-OHCI-allow-other-arches-to-use-the-BE-frame-numb.patch b/target/linux/brcm63xx/patches-3.13/204-USB-OHCI-allow-other-arches-to-use-the-BE-frame-numb.patch new file mode 100644 index 0000000000..1f175f4797 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/204-USB-OHCI-allow-other-arches-to-use-the-BE-frame-numb.patch @@ -0,0 +1,31 @@ +From b2f399dcd674a692a64bb3b300b77b78ae57b530 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 12 Jan 2014 16:47:35 +0100 +Subject: [PATCH] USB: OHCI: allow other arches to use the BE frame number + quirk + +Intead of guarding it with a certain PPC SoC and expanding the list +for each SoC requiring it, just guard it with USB_OHCI_BIG_ENDIAN_DESC. + +This makes it less suprising that passing no_big_frame_no = 1 for the +platform data does not do what expected (or + +Checking it for all big endian descriptor setups should not impact +performance much as USB1.1 is rather slow anyway. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + drivers/usb/host/ohci.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/usb/host/ohci.h ++++ b/drivers/usb/host/ohci.h +@@ -650,7 +650,7 @@ static inline u32 hc32_to_cpup (const st + * some big-endian SOC implementations. Same thing happens with PSW access. + */ + +-#ifdef CONFIG_PPC_MPC52xx ++#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC + #define big_endian_frame_no_quirk(ohci) (ohci->flags & OHCI_QUIRK_FRAME_NO) + #else + #define big_endian_frame_no_quirk(ohci) 0 diff --git a/target/linux/brcm63xx/patches-3.13/205-USB-fix-bcm63xx_udc.patch b/target/linux/brcm63xx/patches-3.13/205-USB-fix-bcm63xx_udc.patch new file mode 100644 index 0000000000..f13a13dc26 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/205-USB-fix-bcm63xx_udc.patch @@ -0,0 +1,168 @@ +From a864a5b3efe9dce1647172d105559a1b850cf4c9 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Tue, 14 Jan 2014 15:29:25 -0800 +Subject: [PATCH] usb: gadget: bcm63xx_udc: fix build failure on DMA channel + code + +Commit 3dc6475 ("bcm63xx_enet: add support Broadcom BCM6345 Ethernet") +changed the ENETDMA[CS] macros such that they are no longer macros, but +actual register offset definitions. The bcm63xx_udc driver was not +updated, and as a result, causes the following build error to pop up: + + CC drivers/usb/gadget/u_ether.o +drivers/usb/gadget/bcm63xx_udc.c: In function 'iudma_write': +drivers/usb/gadget/bcm63xx_udc.c:642:24: error: called object '0' is not +a function +drivers/usb/gadget/bcm63xx_udc.c: In function 'iudma_reset_channel': +drivers/usb/gadget/bcm63xx_udc.c:698:46: error: called object '0' is not +a function +drivers/usb/gadget/bcm63xx_udc.c:700:49: error: called object '0' is not +a function + +Fix this by updating usb_dmac_{read,write}l and usb_dmas_{read,write}l to +take an extra channel argument, and use the channel width +(ENETDMA_CHAN_WIDTH) to offset the register we want to access, hence +doing again what the macro implicitely did for us. + +CC: Kevin Cernekee <cernekee@gmail.com> +CC: Jonas Gorski <jogo@openwrt.org> +CC: stable@vger.kernel.org +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- +Felipe, + +This is against your branch as balbi/usb.git, and this fix should be applied to +stable 3.11 onwards. + +Thanks! + + drivers/usb/gadget/bcm63xx_udc.c | 58 ++++++++++++++++++++++------------------ + 1 file changed, 32 insertions(+), 26 deletions(-) + +--- a/drivers/usb/gadget/bcm63xx_udc.c ++++ b/drivers/usb/gadget/bcm63xx_udc.c +@@ -362,24 +362,30 @@ static inline void usb_dma_writel(struct + bcm_writel(val, udc->iudma_regs + off); + } + +-static inline u32 usb_dmac_readl(struct bcm63xx_udc *udc, u32 off) ++static inline u32 usb_dmac_readl(struct bcm63xx_udc *udc, u32 off, int chan) + { +- return bcm_readl(udc->iudma_regs + IUDMA_DMAC_OFFSET + off); ++ return bcm_readl(udc->iudma_regs + IUDMA_DMAC_OFFSET + off + ++ (ENETDMA_CHAN_WIDTH * chan)); + } + +-static inline void usb_dmac_writel(struct bcm63xx_udc *udc, u32 val, u32 off) ++static inline void usb_dmac_writel(struct bcm63xx_udc *udc, u32 val, u32 off, ++ int chan) + { +- bcm_writel(val, udc->iudma_regs + IUDMA_DMAC_OFFSET + off); ++ bcm_writel(val, udc->iudma_regs + IUDMA_DMAC_OFFSET + off + ++ (ENETDMA_CHAN_WIDTH * chan)); + } + +-static inline u32 usb_dmas_readl(struct bcm63xx_udc *udc, u32 off) ++static inline u32 usb_dmas_readl(struct bcm63xx_udc *udc, u32 off, int chan) + { +- return bcm_readl(udc->iudma_regs + IUDMA_DMAS_OFFSET + off); ++ return bcm_readl(udc->iudma_regs + IUDMA_DMAS_OFFSET + off + ++ (ENETDMA_CHAN_WIDTH * chan)); + } + +-static inline void usb_dmas_writel(struct bcm63xx_udc *udc, u32 val, u32 off) ++static inline void usb_dmas_writel(struct bcm63xx_udc *udc, u32 val, u32 off, ++ int chan) + { +- bcm_writel(val, udc->iudma_regs + IUDMA_DMAS_OFFSET + off); ++ bcm_writel(val, udc->iudma_regs + IUDMA_DMAS_OFFSET + off + ++ (ENETDMA_CHAN_WIDTH * chan)); + } + + static inline void set_clocks(struct bcm63xx_udc *udc, bool is_enabled) +@@ -639,7 +645,7 @@ static void iudma_write(struct bcm63xx_u + } while (!last_bd); + + usb_dmac_writel(udc, ENETDMAC_CHANCFG_EN_MASK, +- ENETDMAC_CHANCFG_REG(iudma->ch_idx)); ++ ENETDMAC_CHANCFG_REG, iudma->ch_idx); + } + + /** +@@ -695,9 +701,9 @@ static void iudma_reset_channel(struct b + bcm63xx_fifo_reset_ep(udc, max(0, iudma->ep_num)); + + /* stop DMA, then wait for the hardware to wrap up */ +- usb_dmac_writel(udc, 0, ENETDMAC_CHANCFG_REG(ch_idx)); ++ usb_dmac_writel(udc, 0, ENETDMAC_CHANCFG_REG, ch_idx); + +- while (usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG(ch_idx)) & ++ while (usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG, ch_idx) & + ENETDMAC_CHANCFG_EN_MASK) { + udelay(1); + +@@ -714,10 +720,10 @@ static void iudma_reset_channel(struct b + dev_warn(udc->dev, "forcibly halting IUDMA channel %d\n", + ch_idx); + usb_dmac_writel(udc, ENETDMAC_CHANCFG_BUFHALT_MASK, +- ENETDMAC_CHANCFG_REG(ch_idx)); ++ ENETDMAC_CHANCFG_REG, ch_idx); + } + } +- usb_dmac_writel(udc, ~0, ENETDMAC_IR_REG(ch_idx)); ++ usb_dmac_writel(udc, ~0, ENETDMAC_IR_REG, ch_idx); + + /* don't leave "live" HW-owned entries for the next guy to step on */ + for (d = iudma->bd_ring; d <= iudma->end_bd; d++) +@@ -729,11 +735,11 @@ static void iudma_reset_channel(struct b + + /* set up IRQs, UBUS burst size, and BD base for this channel */ + usb_dmac_writel(udc, ENETDMAC_IR_BUFDONE_MASK, +- ENETDMAC_IRMASK_REG(ch_idx)); +- usb_dmac_writel(udc, 8, ENETDMAC_MAXBURST_REG(ch_idx)); ++ ENETDMAC_IRMASK_REG, ch_idx); ++ usb_dmac_writel(udc, 8, ENETDMAC_MAXBURST_REG, ch_idx); + +- usb_dmas_writel(udc, iudma->bd_ring_dma, ENETDMAS_RSTART_REG(ch_idx)); +- usb_dmas_writel(udc, 0, ENETDMAS_SRAM2_REG(ch_idx)); ++ usb_dmas_writel(udc, iudma->bd_ring_dma, ENETDMAS_RSTART_REG, ch_idx); ++ usb_dmas_writel(udc, 0, ENETDMAS_SRAM2_REG, ch_idx); + } + + /** +@@ -2016,7 +2022,7 @@ static irqreturn_t bcm63xx_udc_data_isr( + spin_lock(&udc->lock); + + usb_dmac_writel(udc, ENETDMAC_IR_BUFDONE_MASK, +- ENETDMAC_IR_REG(iudma->ch_idx)); ++ ENETDMAC_IR_REG, iudma->ch_idx); + bep = iudma->bep; + rc = iudma_read(udc, iudma); + +@@ -2156,18 +2162,18 @@ static int bcm63xx_iudma_dbg_show(struct + seq_printf(s, " [ep%d]:\n", + max_t(int, iudma_defaults[ch_idx].ep_num, 0)); + seq_printf(s, " cfg: %08x; irqstat: %08x; irqmask: %08x; maxburst: %08x\n", +- usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG(ch_idx)), +- usb_dmac_readl(udc, ENETDMAC_IR_REG(ch_idx)), +- usb_dmac_readl(udc, ENETDMAC_IRMASK_REG(ch_idx)), +- usb_dmac_readl(udc, ENETDMAC_MAXBURST_REG(ch_idx))); ++ usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG, ch_idx), ++ usb_dmac_readl(udc, ENETDMAC_IR_REG, ch_idx), ++ usb_dmac_readl(udc, ENETDMAC_IRMASK_REG, ch_idx), ++ usb_dmac_readl(udc, ENETDMAC_MAXBURST_REG, ch_idx)); + +- sram2 = usb_dmas_readl(udc, ENETDMAS_SRAM2_REG(ch_idx)); +- sram3 = usb_dmas_readl(udc, ENETDMAS_SRAM3_REG(ch_idx)); ++ sram2 = usb_dmas_readl(udc, ENETDMAS_SRAM2_REG, ch_idx); ++ sram3 = usb_dmas_readl(udc, ENETDMAS_SRAM3_REG, ch_idx); + seq_printf(s, " base: %08x; index: %04x_%04x; desc: %04x_%04x %08x\n", +- usb_dmas_readl(udc, ENETDMAS_RSTART_REG(ch_idx)), ++ usb_dmas_readl(udc, ENETDMAS_RSTART_REG, ch_idx), + sram2 >> 16, sram2 & 0xffff, + sram3 >> 16, sram3 & 0xffff, +- usb_dmas_readl(udc, ENETDMAS_SRAM4_REG(ch_idx))); ++ usb_dmas_readl(udc, ENETDMAS_SRAM4_REG, ch_idx)); + seq_printf(s, " desc: %d/%d used", iudma->n_bds_used, + iudma->n_bds); + diff --git a/target/linux/brcm63xx/patches-3.13/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch b/target/linux/brcm63xx/patches-3.13/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch new file mode 100644 index 0000000000..7375acb57b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch @@ -0,0 +1,65 @@ +From 6ac09efa8f0e189ffe7dd7b0889289de56ee44cc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 19 Jan 2014 12:18:03 +0100 +Subject: [PATCH] USB: EHCI: allow limiting ports for ehci-platform + +In the same way as the ohci platform driver allows limiting ports, +enable the same for ehci. This prevents a mismatch in the available +ports between ehci/ohci on USB 2.0 controllers. + +This is needed if the USB host controller always reports the maximum +number of ports regardless of the number of available ports (because +one might be set to be usb device). + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + drivers/usb/host/ehci-hcd.c | 4 ++++ + drivers/usb/host/ehci-platform.c | 2 ++ + drivers/usb/host/ehci.h | 1 + + include/linux/usb/ehci_pdriver.h | 1 + + 4 files changed, 8 insertions(+) + +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -661,6 +661,10 @@ int ehci_setup(struct usb_hcd *hcd) + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ++ if (ehci->num_ports) { ++ ehci->hcs_params &= ~0xf; /* bits 3:0, ports on HC */ ++ ehci->hcs_params |= ehci->num_ports; ++ } + + ehci->sbrn = HCD_USB2; + +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -48,6 +48,8 @@ static int ehci_platform_reset(struct us + ehci->big_endian_desc = pdata->big_endian_desc; + ehci->big_endian_mmio = pdata->big_endian_mmio; + ehci->ignore_oc = pdata->ignore_oc; ++ if (pdata->num_ports && pdata->num_ports <= 15) ++ ehci->num_ports = pdata->num_ports; + + if (pdata->pre_setup) { + retval = pdata->pre_setup(hcd); +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -213,6 +213,7 @@ struct ehci_hcd { /* one per controlle + u32 command; + + /* SILICON QUIRKS */ ++ unsigned int num_ports; + unsigned no_selective_suspend:1; + unsigned has_fsl_port_bug:1; /* FreeScale */ + unsigned big_endian_mmio:1; +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -40,6 +40,7 @@ struct usb_hcd; + */ + struct usb_ehci_pdata { + int caps_offset; ++ unsigned int num_ports; + unsigned has_tt:1; + unsigned has_synopsys_hc_bug:1; + unsigned big_endian_desc:1; diff --git a/target/linux/brcm63xx/patches-3.13/300-reset_buttons.patch b/target/linux/brcm63xx/patches-3.13/300-reset_buttons.patch new file mode 100644 index 0000000000..0886f6c5fc --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/300-reset_buttons.patch @@ -0,0 +1,116 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -12,6 +12,8 @@ + #include <linux/string.h> + #include <linux/platform_device.h> + #include <linux/ssb/ssb.h> ++#include <linux/gpio_keys.h> ++#include <linux/input.h> + #include <asm/addrspace.h> + #include <bcm63xx_board.h> + #include <bcm63xx_cpu.h> +@@ -37,6 +39,9 @@ + + #define HCS_OFFSET_128K 0x20000 + ++#define BCM963XX_KEYS_POLL_INTERVAL 20 ++#define BCM963XX_KEYS_DEBOUNCE_INTERVAL (BCM963XX_KEYS_POLL_INTERVAL * 3) ++ + static struct board_info board; + + /* +@@ -380,6 +385,16 @@ static struct board_info __initdata boar + .active_low = 1, + }, + }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 33, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, + }; + + static struct board_info __initdata board_96348gw = { +@@ -438,6 +453,16 @@ static struct board_info __initdata boar + .active_low = 1, + }, + }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 36, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, + }; + + static struct board_info __initdata board_FAST2404 = { +@@ -871,11 +896,23 @@ static struct platform_device bcm63xx_gp + .dev.platform_data = &bcm63xx_led_data, + }; + ++static struct gpio_keys_platform_data bcm63xx_gpio_keys_data = { ++ .poll_interval = BCM963XX_KEYS_POLL_INTERVAL, ++}; ++ ++static struct platform_device bcm63xx_gpio_keys_device = { ++ .name = "gpio-keys-polled", ++ .id = 0, ++ .dev.platform_data = &bcm63xx_gpio_keys_data, ++}; ++ + /* + * third stage init callback, register all board devices. + */ + int __init board_register_devices(void) + { ++ int button_count = 0; ++ + if (board.has_uart0) + bcm63xx_uart_register(0); + +@@ -937,5 +974,16 @@ int __init board_register_devices(void) + gpio_request_one(board.ephy_reset_gpio, + board.ephy_reset_gpio_flags, "ephy-reset"); + ++ /* count number of BUTTONs defined by this device */ ++ while (button_count < ARRAY_SIZE(board.buttons) && board.buttons[button_count].desc) ++ button_count++; ++ ++ if (button_count) { ++ bcm63xx_gpio_keys_data.nbuttons = button_count; ++ bcm63xx_gpio_keys_data.buttons = board.buttons; ++ ++ platform_device_register(&bcm63xx_gpio_keys_device); ++ } ++ + return 0; + } +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -3,6 +3,7 @@ + + #include <linux/types.h> + #include <linux/gpio.h> ++#include <linux/gpio_keys.h> + #include <linux/leds.h> + #include <bcm63xx_dev_enet.h> + #include <bcm63xx_dev_usb_usbd.h> +@@ -48,6 +49,9 @@ struct board_info { + /* GPIO LEDs */ + struct gpio_led leds[5]; + ++ /* Buttons */ ++ struct gpio_keys_button buttons[4]; ++ + /* External PHY reset GPIO */ + unsigned int ephy_reset_gpio; + diff --git a/target/linux/brcm63xx/patches-3.13/301-led_count.patch b/target/linux/brcm63xx/patches-3.13/301-led_count.patch new file mode 100644 index 0000000000..5b9a12e96e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/301-led_count.patch @@ -0,0 +1,41 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -912,6 +912,7 @@ static struct platform_device bcm63xx_gp + int __init board_register_devices(void) + { + int button_count = 0; ++ int led_count = 0; + + if (board.has_uart0) + bcm63xx_uart_register(0); +@@ -965,10 +966,16 @@ int __init board_register_devices(void) + + bcm63xx_flash_register(); + +- bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); +- bcm63xx_led_data.leds = board.leds; ++ /* count number of LEDs defined by this device */ ++ while (led_count < ARRAY_SIZE(board.leds) && board.leds[led_count].name) ++ led_count++; ++ ++ if (led_count) { ++ bcm63xx_led_data.num_leds = led_count; ++ bcm63xx_led_data.leds = board.leds; + +- platform_device_register(&bcm63xx_gpio_leds); ++ platform_device_register(&bcm63xx_gpio_leds); ++ } + + if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) + gpio_request_one(board.ephy_reset_gpio, +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -47,7 +47,7 @@ struct board_info { + struct bcm63xx_dsp_platform_data dsp; + + /* GPIO LEDs */ +- struct gpio_led leds[5]; ++ struct gpio_led leds[14]; + + /* Buttons */ + struct gpio_keys_button buttons[4]; diff --git a/target/linux/brcm63xx/patches-3.13/302-extended-platform-devices.patch b/target/linux/brcm63xx/patches-3.13/302-extended-platform-devices.patch new file mode 100644 index 0000000000..2810b6f629 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/302-extended-platform-devices.patch @@ -0,0 +1,25 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -964,6 +964,9 @@ int __init board_register_devices(void) + + bcm63xx_hsspi_register(); + ++ if (board.num_devs) ++ platform_add_devices(board.devs, board.num_devs); ++ + bcm63xx_flash_register(); + + /* count number of LEDs defined by this device */ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -57,6 +57,10 @@ struct board_info { + + /* External PHY reset GPIO flags from gpio.h */ + unsigned long ephy_reset_gpio_flags; ++ ++ /* Additional platform devices */ ++ struct platform_device **devs; ++ unsigned int num_devs; + }; + + #endif /* ! BOARD_BCM963XX_H_ */ diff --git a/target/linux/brcm63xx/patches-3.13/303-spi-board-info.patch b/target/linux/brcm63xx/patches-3.13/303-spi-board-info.patch new file mode 100644 index 0000000000..0258710f0b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/303-spi-board-info.patch @@ -0,0 +1,33 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -14,6 +14,7 @@ + #include <linux/ssb/ssb.h> + #include <linux/gpio_keys.h> + #include <linux/input.h> ++#include <linux/spi/spi.h> + #include <asm/addrspace.h> + #include <bcm63xx_board.h> + #include <bcm63xx_cpu.h> +@@ -967,6 +968,9 @@ int __init board_register_devices(void) + if (board.num_devs) + platform_add_devices(board.devs, board.num_devs); + ++ if (board.num_spis) ++ spi_register_board_info(board.spis, board.num_spis); ++ + bcm63xx_flash_register(); + + /* count number of LEDs defined by this device */ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -61,6 +61,10 @@ struct board_info { + /* Additional platform devices */ + struct platform_device **devs; + unsigned int num_devs; ++ ++ /* Additional platform devices */ ++ struct spi_board_info *spis; ++ unsigned int num_spis; + }; + + #endif /* ! BOARD_BCM963XX_H_ */ diff --git a/target/linux/brcm63xx/patches-3.13/304-boardid_fixup.patch b/target/linux/brcm63xx/patches-3.13/304-boardid_fixup.patch new file mode 100644 index 0000000000..937b9d64f3 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/304-boardid_fixup.patch @@ -0,0 +1,62 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -35,6 +35,7 @@ + #include <board_bcm963xx.h> + + #include <uapi/linux/bcm933xx_hcs.h> ++#include <uapi/linux/bcm963xx_tag.h> + + #define PFX "board_bcm963xx: " + +@@ -43,6 +44,9 @@ + #define BCM963XX_KEYS_POLL_INTERVAL 20 + #define BCM963XX_KEYS_DEBOUNCE_INTERVAL (BCM963XX_KEYS_POLL_INTERVAL * 3) + ++#define CFE_OFFSET_64K 0x10000 ++#define CFE_OFFSET_128K 0x20000 ++ + static struct board_info board; + + /* +@@ -782,6 +786,30 @@ const char *board_get_name(void) + return board.name; + } + ++static void __init boardid_fixup(u8 *boot_addr) ++{ ++ struct bcm_tag *tag = (struct bcm_tag *)(boot_addr + CFE_OFFSET_64K); ++ char *board_name = (char *)bcm63xx_nvram_get_name(); ++ ++ /* check if bcm_tag is at 64k offset */ ++ if (strncmp(board_name, tag->board_id, BOARDID_LEN) != 0) { ++ /* else try 128k */ ++ tag = (struct bcm_tag *)(boot_addr + CFE_OFFSET_128K); ++ if (strncmp(board_name, tag->board_id, BOARDID_LEN) != 0) { ++ /* No tag found */ ++ printk(KERN_DEBUG "No bcm_tag found!\n"); ++ return; ++ } ++ } ++ /* check if we should override the boardid */ ++ if (tag->information1[0] != '+') ++ return; ++ ++ strncpy(board_name, &tag->information1[1], BOARDID_LEN); ++ ++ printk(KERN_INFO "Overriding boardid with '%s'\n", board_name); ++} ++ + /* + * early init callback, read nvram data from flash and checksum it + */ +@@ -820,6 +848,10 @@ void __init board_prom_init(void) + hcs = (struct bcm_hcs *)boot_addr; + board_name = hcs->filename; + } else { ++ if (strcmp(cfe_version, "unknown") != 0) { ++ /* cfe present */ ++ boardid_fixup(boot_addr); ++ } + board_name = bcm63xx_nvram_get_name(); + } + /* find board by name */ diff --git a/target/linux/brcm63xx/patches-3.13/308-board_leds_naming.patch b/target/linux/brcm63xx/patches-3.13/308-board_leds_naming.patch new file mode 100644 index 0000000000..0064066803 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/308-board_leds_naming.patch @@ -0,0 +1,267 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -148,28 +148,28 @@ static struct board_info __initdata boar + + .leds = { + { +- .name = "adsl", ++ .name = "96338GW:green:adsl", + .gpio = 3, + .active_low = 1, + }, + { +- .name = "ses", ++ .name = "96338GW:green:ses", + .gpio = 5, + .active_low = 1, + }, + { +- .name = "ppp-fail", ++ .name = "96338GW:green:ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { +- .name = "power", ++ .name = "96338GW:green:power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { +- .name = "stop", ++ .name = "96338GW:green:stop", + .gpio = 1, + .active_low = 1, + } +@@ -189,28 +189,28 @@ static struct board_info __initdata boar + + .leds = { + { +- .name = "adsl", ++ .name = "96338W:green:adsl", + .gpio = 3, + .active_low = 1, + }, + { +- .name = "ses", ++ .name = "96338W:green:ses", + .gpio = 5, + .active_low = 1, + }, + { +- .name = "ppp-fail", ++ .name = "96338W:green:ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { +- .name = "power", ++ .name = "96338W:green:power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { +- .name = "stop", ++ .name = "96338W:green:stop", + .gpio = 1, + .active_low = 1, + }, +@@ -249,29 +249,29 @@ static struct board_info __initdata boar + + .leds = { + { +- .name = "adsl-fail", ++ .name = "96348R:green:adsl-fail", + .gpio = 2, + .active_low = 1, + }, + { +- .name = "ppp", ++ .name = "96348R:green:ppp", + .gpio = 3, + .active_low = 1, + }, + { +- .name = "ppp-fail", ++ .name = "96348R:green:ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { +- .name = "power", ++ .name = "96348R:green:power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + + }, + { +- .name = "stop", ++ .name = "96348R:green:stop", + .gpio = 1, + .active_low = 1, + }, +@@ -310,28 +310,28 @@ static struct board_info __initdata boar + + .leds = { + { +- .name = "adsl-fail", ++ .name = "96348GW-10:green:adsl-fail", + .gpio = 2, + .active_low = 1, + }, + { +- .name = "ppp", ++ .name = "96348GW-10:green:ppp", + .gpio = 3, + .active_low = 1, + }, + { +- .name = "ppp-fail", ++ .name = "96348GW-10:green:ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { +- .name = "power", ++ .name = "96348GW-10:green:power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { +- .name = "stop", ++ .name = "96348GW-10:green:stop", + .gpio = 1, + .active_low = 1, + }, +@@ -364,28 +364,28 @@ static struct board_info __initdata boar + + .leds = { + { +- .name = "adsl-fail", ++ .name = "96348GW-11:green:adsl-fail", + .gpio = 2, + .active_low = 1, + }, + { +- .name = "ppp", ++ .name = "96348GW-11:green:ppp", + .gpio = 3, + .active_low = 1, + }, + { +- .name = "ppp-fail", ++ .name = "96348GW-11:green:ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { +- .name = "power", ++ .name = "96348GW-11:green:power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { +- .name = "stop", ++ .name = "96348GW-11:green:stop", + .gpio = 1, + .active_low = 1, + }, +@@ -432,28 +432,28 @@ static struct board_info __initdata boar + + .leds = { + { +- .name = "adsl-fail", ++ .name = "96348GW:green:adsl-fail", + .gpio = 2, + .active_low = 1, + }, + { +- .name = "ppp", ++ .name = "96348GW:green:ppp", + .gpio = 3, + .active_low = 1, + }, + { +- .name = "ppp-fail", ++ .name = "96348GW:green:ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { +- .name = "power", ++ .name = "96348GW:green:power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { +- .name = "stop", ++ .name = "96348GW:green:stop", + .gpio = 1, + .active_low = 1, + }, +@@ -585,27 +585,27 @@ static struct board_info __initdata boar + + .leds = { + { +- .name = "adsl-fail", ++ .name = "96358VW:green:adsl-fail", + .gpio = 15, + .active_low = 1, + }, + { +- .name = "ppp", ++ .name = "96358VW:green:ppp", + .gpio = 22, + .active_low = 1, + }, + { +- .name = "ppp-fail", ++ .name = "96358VW:green:ppp-fail", + .gpio = 23, + .active_low = 1, + }, + { +- .name = "power", ++ .name = "96358VW:green:power", + .gpio = 4, + .default_trigger = "default-on", + }, + { +- .name = "stop", ++ .name = "96358VW:green:stop", + .gpio = 5, + }, + }, +@@ -637,22 +637,22 @@ static struct board_info __initdata boar + + .leds = { + { +- .name = "adsl", ++ .name = "96358VW2:green:adsl", + .gpio = 22, + .active_low = 1, + }, + { +- .name = "ppp-fail", ++ .name = "96358VW2:green:ppp-fail", + .gpio = 23, + }, + { +- .name = "power", ++ .name = "96358VW2:green:power", + .gpio = 5, + .active_low = 1, + .default_trigger = "default-on", + }, + { +- .name = "stop", ++ .name = "96358VW2:green:stop", + .gpio = 4, + .active_low = 1, + }, diff --git a/target/linux/brcm63xx/patches-3.13/309-cfe_version_mod.patch b/target/linux/brcm63xx/patches-3.13/309-cfe_version_mod.patch new file mode 100644 index 0000000000..dfc33841ea --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/309-cfe_version_mod.patch @@ -0,0 +1,27 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -835,10 +835,20 @@ void __init board_prom_init(void) + + /* dump cfe version */ + cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET; +- if (!memcmp(cfe, "cfe-v", 5)) +- snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u", +- cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]); +- else ++ if (strstarts(cfe, "cfe-")) { ++ if(cfe[4] == 'v') { ++ if(cfe[5] == 'd') ++ snprintf(cfe_version, 11, "%s", (char *) &cfe[5]); ++ else if (cfe[10] > 0) ++ snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u-%u", ++ cfe[5], cfe[6], cfe[7], cfe[8], cfe[9], cfe[10]); ++ else ++ snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u", ++ cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]); ++ } else { ++ snprintf(cfe_version, 12, "%s", (char *) &cfe[4]); ++ } ++ } else + strcpy(cfe_version, "unknown"); + printk(KERN_INFO PFX "CFE version: %s\n", cfe_version); + diff --git a/target/linux/brcm63xx/patches-3.13/310-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-from-registe.patch b/target/linux/brcm63xx/patches-3.13/310-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-from-registe.patch new file mode 100644 index 0000000000..04b34266b1 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/310-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-from-registe.patch @@ -0,0 +1,61 @@ +From 082a49f0490008b999db80e3ccf1521c7dd21cec Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Mon, 2 Dec 2013 12:32:44 +0100 +Subject: [PATCH 1/8] MIPS: BCM63XX: remove !RUNTIME_DETECT code from register + sets + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 33 ------------------------ + 1 file changed, 33 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -598,10 +598,6 @@ enum bcm63xx_regs_set { + + extern const unsigned long *bcm63xx_regs_base; + +-#define __GEN_RSET_BASE(__cpu, __rset) \ +- case RSET_## __rset : \ +- return BCM_## __cpu ##_## __rset ##_BASE; +- + #define __GEN_RSET(__cpu) \ + switch (set) { \ + __GEN_RSET_BASE(__cpu, DSL_LMEM) \ +@@ -693,36 +689,7 @@ extern const unsigned long *bcm63xx_regs + + static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) + { +-#ifdef BCMCPU_RUNTIME_DETECT + return bcm63xx_regs_base[set]; +-#else +-#ifdef CONFIG_BCM63XX_CPU_3368 +- __GEN_RSET(3368) +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6328 +- __GEN_RSET(6328) +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6338 +- __GEN_RSET(6338) +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6345 +- __GEN_RSET(6345) +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6348 +- __GEN_RSET(6348) +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6358 +- __GEN_RSET(6358) +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6362 +- __GEN_RSET(6362) +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6368 +- __GEN_RSET(6368) +-#endif +-#endif +- /* unreached */ +- return 0; + } + + /* diff --git a/target/linux/brcm63xx/patches-3.13/311-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-irq-setup-co.patch b/target/linux/brcm63xx/patches-3.13/311-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-irq-setup-co.patch new file mode 100644 index 0000000000..92265302fc --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/311-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-irq-setup-co.patch @@ -0,0 +1,135 @@ +From 07d0224576cbb2e6ac680b4ade4bba7a49bd0a07 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Mon, 2 Dec 2013 12:34:11 +0100 +Subject: [PATCH 2/8] MIPS: BCM63XX: remove !RUNTIME_DETECT from irq setup code + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 109 ------------------------------------------------ + 1 file changed, 109 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -26,114 +26,6 @@ static void __internal_irq_mask_64(unsig + static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; + static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; + +-#ifndef BCMCPU_RUNTIME_DETECT +-#ifdef CONFIG_BCM63XX_CPU_3368 +-#define irq_stat_reg PERF_IRQSTAT_3368_REG +-#define irq_mask_reg PERF_IRQMASK_3368_REG +-#define irq_bits 32 +-#define is_ext_irq_cascaded 0 +-#define ext_irq_start 0 +-#define ext_irq_end 0 +-#define ext_irq_count 4 +-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368 +-#define ext_irq_cfg_reg2 0 +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6328 +-#define irq_stat_reg PERF_IRQSTAT_6328_REG +-#define irq_mask_reg PERF_IRQMASK_6328_REG +-#define irq_bits 64 +-#define is_ext_irq_cascaded 1 +-#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE) +-#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE) +-#define ext_irq_count 4 +-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328 +-#define ext_irq_cfg_reg2 0 +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6338 +-#define irq_stat_reg PERF_IRQSTAT_6338_REG +-#define irq_mask_reg PERF_IRQMASK_6338_REG +-#define irq_bits 32 +-#define is_ext_irq_cascaded 0 +-#define ext_irq_start 0 +-#define ext_irq_end 0 +-#define ext_irq_count 4 +-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338 +-#define ext_irq_cfg_reg2 0 +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6345 +-#define irq_stat_reg PERF_IRQSTAT_6345_REG +-#define irq_mask_reg PERF_IRQMASK_6345_REG +-#define irq_bits 32 +-#define is_ext_irq_cascaded 0 +-#define ext_irq_start 0 +-#define ext_irq_end 0 +-#define ext_irq_count 4 +-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345 +-#define ext_irq_cfg_reg2 0 +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6348 +-#define irq_stat_reg PERF_IRQSTAT_6348_REG +-#define irq_mask_reg PERF_IRQMASK_6348_REG +-#define irq_bits 32 +-#define is_ext_irq_cascaded 0 +-#define ext_irq_start 0 +-#define ext_irq_end 0 +-#define ext_irq_count 4 +-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348 +-#define ext_irq_cfg_reg2 0 +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6358 +-#define irq_stat_reg PERF_IRQSTAT_6358_REG +-#define irq_mask_reg PERF_IRQMASK_6358_REG +-#define irq_bits 32 +-#define is_ext_irq_cascaded 1 +-#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE) +-#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE) +-#define ext_irq_count 4 +-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358 +-#define ext_irq_cfg_reg2 0 +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6362 +-#define irq_stat_reg PERF_IRQSTAT_6362_REG +-#define irq_mask_reg PERF_IRQMASK_6362_REG +-#define irq_bits 64 +-#define is_ext_irq_cascaded 1 +-#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE) +-#define ext_irq_end (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE) +-#define ext_irq_count 4 +-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6362 +-#define ext_irq_cfg_reg2 0 +-#endif +-#ifdef CONFIG_BCM63XX_CPU_6368 +-#define irq_stat_reg PERF_IRQSTAT_6368_REG +-#define irq_mask_reg PERF_IRQMASK_6368_REG +-#define irq_bits 64 +-#define is_ext_irq_cascaded 1 +-#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE) +-#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE) +-#define ext_irq_count 6 +-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368 +-#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368 +-#endif +- +-#if irq_bits == 32 +-#define dispatch_internal __dispatch_internal +-#define internal_irq_mask __internal_irq_mask_32 +-#define internal_irq_unmask __internal_irq_unmask_32 +-#else +-#define dispatch_internal __dispatch_internal_64 +-#define internal_irq_mask __internal_irq_mask_64 +-#define internal_irq_unmask __internal_irq_unmask_64 +-#endif +- +-#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg) +-#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg) +- +-static inline void bcm63xx_init_irq(void) +-{ +-} +-#else /* ! BCMCPU_RUNTIME_DETECT */ +- + static u32 irq_stat_addr, irq_mask_addr; + static void (*dispatch_internal)(void); + static int is_ext_irq_cascaded; +@@ -234,7 +126,6 @@ static void bcm63xx_init_irq(void) + internal_irq_unmask = __internal_irq_unmask_64; + } + } +-#endif /* ! BCMCPU_RUNTIME_DETECT */ + + static inline u32 get_ext_irq_perf_reg(int irq) + { diff --git a/target/linux/brcm63xx/patches-3.13/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch b/target/linux/brcm63xx/patches-3.13/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch new file mode 100644 index 0000000000..f26624eb4f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch @@ -0,0 +1,85 @@ +From 72578a46543821c5b9544842e45fcbed0c1b7eb8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Tue, 3 Dec 2013 13:35:12 +0100 +Subject: [PATCH 3/8] MIPS: BCM63XX: remove !RUNTIME_DETECT from reset code + +--- + arch/mips/bcm63xx/reset.c | 60 ----------------------------------------------- + 1 file changed, 60 deletions(-) + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -125,8 +125,6 @@ + #define BCM6368_RESET_PCIE 0 + #define BCM6368_RESET_PCIE_EXT 0 + +-#ifdef BCMCPU_RUNTIME_DETECT +- + /* + * core reset bits + */ +@@ -188,64 +186,6 @@ static int __init bcm63xx_reset_bits_ini + + return 0; + } +-#else +- +-#ifdef CONFIG_BCM63XX_CPU_3368 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(3368) +-}; +-#define reset_reg PERF_SOFTRESET_6358_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6328 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6328) +-}; +-#define reset_reg PERF_SOFTRESET_6328_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6338 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6338) +-}; +-#define reset_reg PERF_SOFTRESET_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6345 +-static const u32 bcm63xx_reset_bits[] = { }; +-#define reset_reg 0 +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6348 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6348) +-}; +-#define reset_reg PERF_SOFTRESET_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6358 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6358) +-}; +-#define reset_reg PERF_SOFTRESET_6358_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6362 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6362) +-}; +-#define reset_reg PERF_SOFTRESET_6362_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6368 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6368) +-}; +-#define reset_reg PERF_SOFTRESET_6368_REG +-#endif +- +-static int __init bcm63xx_reset_bits_init(void) { return 0; } +-#endif + + static DEFINE_SPINLOCK(reset_mutex); + diff --git a/target/linux/brcm63xx/patches-3.13/313-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-from-gpio.patch b/target/linux/brcm63xx/patches-3.13/313-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-from-gpio.patch new file mode 100644 index 0000000000..49a3475e84 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/313-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-from-gpio.patch @@ -0,0 +1,39 @@ +From 1aab93c5c97c55fef130726a6f58c9a1fd5b6240 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Tue, 3 Dec 2013 13:36:45 +0100 +Subject: [PATCH 4/8] MIPS: BCM63XX: remove !RUNTIME_DETECT code from gpio + +--- + arch/mips/bcm63xx/gpio.c | 14 -------------- + 1 file changed, 14 deletions(-) + +--- a/arch/mips/bcm63xx/gpio.c ++++ b/arch/mips/bcm63xx/gpio.c +@@ -18,19 +18,6 @@ + #include <bcm63xx_io.h> + #include <bcm63xx_regs.h> + +-#ifndef BCMCPU_RUNTIME_DETECT +-#define gpio_out_low_reg GPIO_DATA_LO_REG +-#ifdef CONFIG_BCM63XX_CPU_6345 +-#ifdef gpio_out_low_reg +-#undef gpio_out_low_reg +-#define gpio_out_low_reg GPIO_DATA_LO_REG_6345 +-#endif /* gpio_out_low_reg */ +-#endif /* CONFIG_BCM63XX_CPU_6345 */ +- +-static inline void bcm63xx_gpio_out_low_reg_init(void) +-{ +-} +-#else /* ! BCMCPU_RUNTIME_DETECT */ + static u32 gpio_out_low_reg; + + static void bcm63xx_gpio_out_low_reg_init(void) +@@ -44,7 +31,6 @@ static void bcm63xx_gpio_out_low_reg_ini + break; + } + } +-#endif /* ! BCMCPU_RUNTIME_DETECT */ + + static DEFINE_SPINLOCK(bcm63xx_gpio_lock); + static u32 gpio_out_low, gpio_out_high; diff --git a/target/linux/brcm63xx/patches-3.13/314-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-spi-code.patch b/target/linux/brcm63xx/patches-3.13/314-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-spi-code.patch new file mode 100644 index 0000000000..afde39bbaa --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/314-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-spi-code.patch @@ -0,0 +1,80 @@ +From 94f819bc230bb61a9ff21da6c860a40ca68c2805 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Tue, 3 Dec 2013 13:43:35 +0100 +Subject: [PATCH 5/8] MIPS: BCM63XX: remove !RUNTIME_DETECT from spi code + +--- + arch/mips/bcm63xx/dev-spi.c | 4 --- + .../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 31 ---------------------- + 2 files changed, 35 deletions(-) + +--- a/arch/mips/bcm63xx/dev-spi.c ++++ b/arch/mips/bcm63xx/dev-spi.c +@@ -18,7 +18,6 @@ + #include <bcm63xx_dev_spi.h> + #include <bcm63xx_regs.h> + +-#ifdef BCMCPU_RUNTIME_DETECT + /* + * register offsets + */ +@@ -41,9 +40,6 @@ static __init void bcm63xx_spi_regs_init + BCMCPU_IS_6362() || BCMCPU_IS_6368()) + bcm63xx_regs_spi = bcm6358_regs_spi; + } +-#else +-static __init void bcm63xx_spi_regs_init(void) { } +-#endif + + static struct resource spi_resources[] = { + { +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h +@@ -30,26 +30,6 @@ enum bcm63xx_regs_spi { + SPI_RX_DATA, + }; + +-#define __GEN_SPI_RSET_BASE(__cpu, __rset) \ +- case SPI_## __rset: \ +- return SPI_## __cpu ##_## __rset; +- +-#define __GEN_SPI_RSET(__cpu) \ +- switch (reg) { \ +- __GEN_SPI_RSET_BASE(__cpu, CMD) \ +- __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \ +- __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \ +- __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \ +- __GEN_SPI_RSET_BASE(__cpu, ST) \ +- __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \ +- __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \ +- __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \ +- __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \ +- __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \ +- __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \ +- __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \ +- } +- + #define __GEN_SPI_REGS_TABLE(__cpu) \ + [SPI_CMD] = SPI_## __cpu ##_CMD, \ + [SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \ +@@ -66,20 +46,9 @@ enum bcm63xx_regs_spi { + + static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) + { +-#ifdef BCMCPU_RUNTIME_DETECT + extern const unsigned long *bcm63xx_regs_spi; + + return bcm63xx_regs_spi[reg]; +-#else +-#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348) +- __GEN_SPI_RSET(6348) +-#endif +-#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) || \ +- defined(CONFIG_BCM63XX_CPU_6368) +- __GEN_SPI_RSET(6358) +-#endif +-#endif +- return 0; + } + + #endif /* BCM63XX_DEV_SPI_H */ diff --git a/target/linux/brcm63xx/patches-3.13/315-MIPS-BCM63XX-remove-RUNTIME_DETECT-usage-from-enet-c.patch b/target/linux/brcm63xx/patches-3.13/315-MIPS-BCM63XX-remove-RUNTIME_DETECT-usage-from-enet-c.patch new file mode 100644 index 0000000000..0dba2e2f1e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/315-MIPS-BCM63XX-remove-RUNTIME_DETECT-usage-from-enet-c.patch @@ -0,0 +1,89 @@ +From ed6c71de07ad042691ec02e9eb97375ddc91ed01 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Tue, 3 Dec 2013 13:45:22 +0100 +Subject: [PATCH 6/8] MIPS: BCM63XX: remove !RUNTIME_DETECT usage from enet + code + +--- + arch/mips/bcm63xx/dev-enet.c | 4 -- + .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 46 ---------------------- + 2 files changed, 50 deletions(-) + +--- a/arch/mips/bcm63xx/dev-enet.c ++++ b/arch/mips/bcm63xx/dev-enet.c +@@ -14,7 +14,6 @@ + #include <bcm63xx_io.h> + #include <bcm63xx_regs.h> + +-#ifdef BCMCPU_RUNTIME_DETECT + static const unsigned long bcm6348_regs_enetdmac[] = { + [ENETDMAC_CHANCFG] = ENETDMAC_CHANCFG_REG, + [ENETDMAC_IR] = ENETDMAC_IR_REG, +@@ -43,9 +42,6 @@ static __init void bcm63xx_enetdmac_regs + else + bcm63xx_regs_enetdmac = bcm6348_regs_enetdmac; + } +-#else +-static __init void bcm63xx_enetdmac_regs_init(void) { } +-#endif + + static struct resource shared_res[] = { + { +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h +@@ -112,55 +112,9 @@ enum bcm63xx_regs_enetdmac { + + static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg) + { +-#ifdef BCMCPU_RUNTIME_DETECT + extern const unsigned long *bcm63xx_regs_enetdmac; + + return bcm63xx_regs_enetdmac[reg]; +-#else +-#ifdef CONFIG_BCM63XX_CPU_6345 +- switch (reg) { +- case ENETDMAC_CHANCFG: +- return ENETDMA_6345_CHANCFG_REG; +- case ENETDMAC_IR: +- return ENETDMA_6345_IR_REG; +- case ENETDMAC_IRMASK: +- return ENETDMA_6345_IRMASK_REG; +- case ENETDMAC_MAXBURST: +- return ENETDMA_6345_MAXBURST_REG; +- case ENETDMAC_BUFALLOC: +- return ENETDMA_6345_BUFALLOC_REG; +- case ENETDMAC_RSTART: +- return ENETDMA_6345_RSTART_REG; +- case ENETDMAC_FC: +- return ENETDMA_6345_FC_REG; +- case ENETDMAC_LEN: +- return ENETDMA_6345_LEN_REG; +- } +-#endif +-#if defined(CONFIG_BCM63XX_CPU_6328) || \ +- defined(CONFIG_BCM63XX_CPU_6338) || \ +- defined(CONFIG_BCM63XX_CPU_6348) || \ +- defined(CONFIG_BCM63XX_CPU_6358) || \ +- defined(CONFIG_BCM63XX_CPU_6362) || \ +- defined(CONFIG_BCM63XX_CPU_6368) +- switch (reg) { +- case ENETDMAC_CHANCFG: +- return ENETDMAC_CHANCFG_REG; +- case ENETDMAC_IR: +- return ENETDMAC_IR_REG; +- case ENETDMAC_IRMASK: +- return ENETDMAC_IRMASK_REG; +- case ENETDMAC_MAXBURST: +- return ENETDMAC_MAXBURST_REG; +- case ENETDMAC_BUFALLOC: +- case ENETDMAC_RSTART: +- case ENETDMAC_FC: +- case ENETDMAC_LEN: +- return 0; +- } +-#endif +-#endif +- return 0; + } + + diff --git a/target/linux/brcm63xx/patches-3.13/316-MIPS-BCM63XX-remove-RUNTIME_DETECT-in-cpu-feature-ov.patch b/target/linux/brcm63xx/patches-3.13/316-MIPS-BCM63XX-remove-RUNTIME_DETECT-in-cpu-feature-ov.patch new file mode 100644 index 0000000000..6316b8dee5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/316-MIPS-BCM63XX-remove-RUNTIME_DETECT-in-cpu-feature-ov.patch @@ -0,0 +1,23 @@ +From 12c6957004d6770f4b34d59d8a3cafd5d8bfce15 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Tue, 3 Dec 2013 14:06:12 +0100 +Subject: [PATCH 7/8] MIPS: BCM63XX: remove !RUNTIME_DETECT in + cpu-feature-overrides + +All three SoCs have in common they have a BMIPS32/BMIPS3300 CPU, so +we can replace this as no SoC with BMIPS4350 support enabled. +--- + arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h ++++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h +@@ -24,7 +24,7 @@ + #define cpu_has_smartmips 0 + #define cpu_has_vtag_icache 0 + +-#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCM63XX_CPU_6348) || defined(CONFIG_BCM63XX_CPU_6345) || defined(CONFIG_BCM63XX_CPU_6338)) ++#if !defined(CONFIG_SYS_HAS_CPU_BMIPS4350) + #define cpu_has_dc_aliases 0 + #endif + diff --git a/target/linux/brcm63xx/patches-3.13/317-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-for-bcmcpu_g.patch b/target/linux/brcm63xx/patches-3.13/317-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-for-bcmcpu_g.patch new file mode 100644 index 0000000000..e40cfa02b7 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/317-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-for-bcmcpu_g.patch @@ -0,0 +1,199 @@ +From 78c3d2e796a28ad55f6c2310a11ab22e91bb52fc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Mon, 2 Dec 2013 12:30:44 +0100 +Subject: [PATCH 8/8] MIPS: BCM63XX: remove !RUNTIME_DETECT code for + bcmcpu_get_id + +Use the same pattern as with get_*_cpu_type() to allow the compiler +to remove code for non enabled devices. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/cpu.c | 11 +-- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 120 +++++++---------------- + 2 files changed, 38 insertions(+), 93 deletions(-) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -24,7 +24,9 @@ EXPORT_SYMBOL(bcm63xx_regs_base); + const int *bcm63xx_irqs; + EXPORT_SYMBOL(bcm63xx_irqs); + +-static u16 bcm63xx_cpu_id; ++u16 bcm63xx_cpu_id __read_mostly; ++EXPORT_SYMBOL(bcm63xx_cpu_id); ++ + static u8 bcm63xx_cpu_rev; + static unsigned int bcm63xx_cpu_freq; + static unsigned int bcm63xx_memory_size; +@@ -97,13 +99,6 @@ static const int bcm6368_irqs[] = { + + }; + +-u16 __bcm63xx_get_cpu_id(void) +-{ +- return bcm63xx_cpu_id; +-} +- +-EXPORT_SYMBOL(__bcm63xx_get_cpu_id); +- + u8 bcm63xx_get_cpu_rev(void) + { + return bcm63xx_cpu_rev; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -19,118 +19,68 @@ + #define BCM6368_CPU_ID 0x6368 + + void __init bcm63xx_cpu_init(void); +-u16 __bcm63xx_get_cpu_id(void); + u8 bcm63xx_get_cpu_rev(void); + unsigned int bcm63xx_get_cpu_freq(void); + ++static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id) ++{ ++ switch (cpu_id) { + #ifdef CONFIG_BCM63XX_CPU_3368 +-# ifdef bcm63xx_get_cpu_id +-# undef bcm63xx_get_cpu_id +-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +-# define BCMCPU_RUNTIME_DETECT +-# else +-# define bcm63xx_get_cpu_id() BCM3368_CPU_ID +-# endif +-# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) +-#else +-# define BCMCPU_IS_3368() (0) ++ case BCM3368_CPU_ID: + #endif + + #ifdef CONFIG_BCM63XX_CPU_6328 +-# ifdef bcm63xx_get_cpu_id +-# undef bcm63xx_get_cpu_id +-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +-# define BCMCPU_RUNTIME_DETECT +-# else +-# define bcm63xx_get_cpu_id() BCM6328_CPU_ID +-# endif +-# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) +-#else +-# define BCMCPU_IS_6328() (0) ++ case BCM6328_CPU_ID: + #endif + + #ifdef CONFIG_BCM63XX_CPU_6338 +-# ifdef bcm63xx_get_cpu_id +-# undef bcm63xx_get_cpu_id +-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +-# define BCMCPU_RUNTIME_DETECT +-# else +-# define bcm63xx_get_cpu_id() BCM6338_CPU_ID +-# endif +-# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) +-#else +-# define BCMCPU_IS_6338() (0) ++ case BCM6338_CPU_ID: + #endif + + #ifdef CONFIG_BCM63XX_CPU_6345 +-# ifdef bcm63xx_get_cpu_id +-# undef bcm63xx_get_cpu_id +-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +-# define BCMCPU_RUNTIME_DETECT +-# else +-# define bcm63xx_get_cpu_id() BCM6345_CPU_ID +-# endif +-# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) +-#else +-# define BCMCPU_IS_6345() (0) ++ case BCM6345_CPU_ID: + #endif + + #ifdef CONFIG_BCM63XX_CPU_6348 +-# ifdef bcm63xx_get_cpu_id +-# undef bcm63xx_get_cpu_id +-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +-# define BCMCPU_RUNTIME_DETECT +-# else +-# define bcm63xx_get_cpu_id() BCM6348_CPU_ID +-# endif +-# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) +-#else +-# define BCMCPU_IS_6348() (0) ++ case BCM6348_CPU_ID: + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +-# ifdef bcm63xx_get_cpu_id +-# undef bcm63xx_get_cpu_id +-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +-# define BCMCPU_RUNTIME_DETECT +-# else +-# define bcm63xx_get_cpu_id() BCM6358_CPU_ID +-# endif +-# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) +-#else +-# define BCMCPU_IS_6358() (0) ++ case BCM6358_CPU_ID: + #endif + + #ifdef CONFIG_BCM63XX_CPU_6362 +-# ifdef bcm63xx_get_cpu_id +-# undef bcm63xx_get_cpu_id +-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +-# define BCMCPU_RUNTIME_DETECT +-# else +-# define bcm63xx_get_cpu_id() BCM6362_CPU_ID +-# endif +-# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) +-#else +-# define BCMCPU_IS_6362() (0) ++ case BCM6362_CPU_ID: + #endif + +- + #ifdef CONFIG_BCM63XX_CPU_6368 +-# ifdef bcm63xx_get_cpu_id +-# undef bcm63xx_get_cpu_id +-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +-# define BCMCPU_RUNTIME_DETECT +-# else +-# define bcm63xx_get_cpu_id() BCM6368_CPU_ID +-# endif +-# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) +-#else +-# define BCMCPU_IS_6368() (0) +-#endif +- +-#ifndef bcm63xx_get_cpu_id +-#error "No CPU support configured" ++ case BCM6368_CPU_ID: + #endif ++ break; ++ default: ++ unreachable(); ++ } ++ ++ return cpu_id; ++} ++ ++extern u16 bcm63xx_cpu_id; ++ ++static inline u16 __pure bcm63xx_get_cpu_id(void) ++{ ++ const u16 cpu_id = bcm63xx_cpu_id; ++ ++ return __bcm63xx_get_cpu_id(cpu_id); ++} ++ ++#define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) ++#define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) ++#define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) ++#define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) ++#define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) ++#define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) ++#define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) ++#define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) + + /* + * While registers sets are (mostly) the same across 63xx CPU, base diff --git a/target/linux/brcm63xx/patches-3.13/318-MIPS-BCM63XX-rename-__dispatch_internal-to-__dispatc.patch b/target/linux/brcm63xx/patches-3.13/318-MIPS-BCM63XX-rename-__dispatch_internal-to-__dispatc.patch new file mode 100644 index 0000000000..f4d98c3454 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/318-MIPS-BCM63XX-rename-__dispatch_internal-to-__dispatc.patch @@ -0,0 +1,42 @@ +From 653dcc09407a695efb203337c6f72515d4c4ee43 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 21 Mar 2013 17:05:15 +0100 +Subject: [PATCH 29/53] MIPS: BCM63XX: rename __dispatch_internal to + __dispatch_internal_32 + +Make it follow the same naming convention as the other functions. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -19,7 +19,7 @@ + #include <bcm63xx_io.h> + #include <bcm63xx_irq.h> + +-static void __dispatch_internal(void) __maybe_unused; ++static void __dispatch_internal_32(void) __maybe_unused; + static void __dispatch_internal_64(void) __maybe_unused; + static void __internal_irq_mask_32(unsigned int irq) __maybe_unused; + static void __internal_irq_mask_64(unsigned int irq) __maybe_unused; +@@ -117,7 +117,7 @@ static void bcm63xx_init_irq(void) + } + + if (irq_bits == 32) { +- dispatch_internal = __dispatch_internal; ++ dispatch_internal = __dispatch_internal_32; + internal_irq_mask = __internal_irq_mask_32; + internal_irq_unmask = __internal_irq_unmask_32; + } else { +@@ -149,7 +149,7 @@ static inline void handle_internal(int i + * will resume the loop where it ended the last time we left this + * function. + */ +-static void __dispatch_internal(void) ++static void __dispatch_internal_32(void) + { + u32 pending; + static int i; diff --git a/target/linux/brcm63xx/patches-3.13/319-MIPS-BCM63XX-move-bcm63xx_init_irq-down.patch b/target/linux/brcm63xx/patches-3.13/319-MIPS-BCM63XX-move-bcm63xx_init_irq-down.patch new file mode 100644 index 0000000000..fb579396b2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/319-MIPS-BCM63XX-move-bcm63xx_init_irq-down.patch @@ -0,0 +1,223 @@ +From c28c639b031385ecf965eecf3bfb532e88044c89 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 15 Dec 2013 20:52:53 +0100 +Subject: [PATCH 30/53] MIPS: BCM63XX: move bcm63xx_init_irq down + +Allows up to drop the prototypes from the top. +--- + arch/mips/bcm63xx/irq.c | 190 +++++++++++++++++++++++------------------------- + 1 file changed, 92 insertions(+), 98 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -19,13 +19,6 @@ + #include <bcm63xx_io.h> + #include <bcm63xx_irq.h> + +-static void __dispatch_internal_32(void) __maybe_unused; +-static void __dispatch_internal_64(void) __maybe_unused; +-static void __internal_irq_mask_32(unsigned int irq) __maybe_unused; +-static void __internal_irq_mask_64(unsigned int irq) __maybe_unused; +-static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; +-static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; +- + static u32 irq_stat_addr, irq_mask_addr; + static void (*dispatch_internal)(void); + static int is_ext_irq_cascaded; +@@ -35,97 +28,6 @@ static unsigned int ext_irq_cfg_reg1, ex + static void (*internal_irq_mask)(unsigned int irq); + static void (*internal_irq_unmask)(unsigned int irq); + +-static void bcm63xx_init_irq(void) +-{ +- int irq_bits; +- +- irq_stat_addr = bcm63xx_regset_address(RSET_PERF); +- irq_mask_addr = bcm63xx_regset_address(RSET_PERF); +- +- switch (bcm63xx_get_cpu_id()) { +- case BCM3368_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_3368_REG; +- irq_mask_addr += PERF_IRQMASK_3368_REG; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; +- break; +- case BCM6328_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6328_REG; +- irq_mask_addr += PERF_IRQMASK_6328_REG; +- irq_bits = 64; +- ext_irq_count = 4; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; +- break; +- case BCM6338_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6338_REG; +- irq_mask_addr += PERF_IRQMASK_6338_REG; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; +- break; +- case BCM6345_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6345_REG; +- irq_mask_addr += PERF_IRQMASK_6345_REG; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; +- break; +- case BCM6348_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6348_REG; +- irq_mask_addr += PERF_IRQMASK_6348_REG; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; +- break; +- case BCM6358_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6358_REG; +- irq_mask_addr += PERF_IRQMASK_6358_REG; +- irq_bits = 32; +- ext_irq_count = 4; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; +- break; +- case BCM6362_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6362_REG; +- irq_mask_addr += PERF_IRQMASK_6362_REG; +- irq_bits = 64; +- ext_irq_count = 4; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; +- break; +- case BCM6368_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6368_REG; +- irq_mask_addr += PERF_IRQMASK_6368_REG; +- irq_bits = 64; +- ext_irq_count = 6; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; +- ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; +- break; +- default: +- BUG(); +- } +- +- if (irq_bits == 32) { +- dispatch_internal = __dispatch_internal_32; +- internal_irq_mask = __internal_irq_mask_32; +- internal_irq_unmask = __internal_irq_unmask_32; +- } else { +- dispatch_internal = __dispatch_internal_64; +- internal_irq_mask = __internal_irq_mask_64; +- internal_irq_unmask = __internal_irq_unmask_64; +- } +-} + + static inline u32 get_ext_irq_perf_reg(int irq) + { +@@ -451,6 +353,98 @@ static struct irqaction cpu_ext_cascade_ + .flags = IRQF_NO_THREAD, + }; + ++static void bcm63xx_init_irq(void) ++{ ++ int irq_bits; ++ ++ irq_stat_addr = bcm63xx_regset_address(RSET_PERF); ++ irq_mask_addr = bcm63xx_regset_address(RSET_PERF); ++ ++ switch (bcm63xx_get_cpu_id()) { ++ case BCM3368_CPU_ID: ++ irq_stat_addr += PERF_IRQSTAT_3368_REG; ++ irq_mask_addr += PERF_IRQMASK_3368_REG; ++ irq_bits = 32; ++ ext_irq_count = 4; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; ++ break; ++ case BCM6328_CPU_ID: ++ irq_stat_addr += PERF_IRQSTAT_6328_REG; ++ irq_mask_addr += PERF_IRQMASK_6328_REG; ++ irq_bits = 64; ++ ext_irq_count = 4; ++ is_ext_irq_cascaded = 1; ++ ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; ++ ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; ++ break; ++ case BCM6338_CPU_ID: ++ irq_stat_addr += PERF_IRQSTAT_6338_REG; ++ irq_mask_addr += PERF_IRQMASK_6338_REG; ++ irq_bits = 32; ++ ext_irq_count = 4; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; ++ break; ++ case BCM6345_CPU_ID: ++ irq_stat_addr += PERF_IRQSTAT_6345_REG; ++ irq_mask_addr += PERF_IRQMASK_6345_REG; ++ irq_bits = 32; ++ ext_irq_count = 4; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; ++ break; ++ case BCM6348_CPU_ID: ++ irq_stat_addr += PERF_IRQSTAT_6348_REG; ++ irq_mask_addr += PERF_IRQMASK_6348_REG; ++ irq_bits = 32; ++ ext_irq_count = 4; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; ++ break; ++ case BCM6358_CPU_ID: ++ irq_stat_addr += PERF_IRQSTAT_6358_REG; ++ irq_mask_addr += PERF_IRQMASK_6358_REG; ++ irq_bits = 32; ++ ext_irq_count = 4; ++ is_ext_irq_cascaded = 1; ++ ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; ++ ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; ++ break; ++ case BCM6362_CPU_ID: ++ irq_stat_addr += PERF_IRQSTAT_6362_REG; ++ irq_mask_addr += PERF_IRQMASK_6362_REG; ++ irq_bits = 64; ++ ext_irq_count = 4; ++ is_ext_irq_cascaded = 1; ++ ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; ++ ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; ++ break; ++ case BCM6368_CPU_ID: ++ irq_stat_addr += PERF_IRQSTAT_6368_REG; ++ irq_mask_addr += PERF_IRQMASK_6368_REG; ++ irq_bits = 64; ++ ext_irq_count = 6; ++ is_ext_irq_cascaded = 1; ++ ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; ++ ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; ++ ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; ++ break; ++ default: ++ BUG(); ++ } ++ ++ if (irq_bits == 32) { ++ dispatch_internal = __dispatch_internal_32; ++ internal_irq_mask = __internal_irq_mask_32; ++ internal_irq_unmask = __internal_irq_unmask_32; ++ } else { ++ dispatch_internal = __dispatch_internal_64; ++ internal_irq_mask = __internal_irq_mask_64; ++ internal_irq_unmask = __internal_irq_unmask_64; ++ } ++} ++ + void __init arch_init_irq(void) + { + int i; diff --git a/target/linux/brcm63xx/patches-3.13/320-MIPS-BCM63XX-replace-irq-dispatch-code-with-a-generi.patch b/target/linux/brcm63xx/patches-3.13/320-MIPS-BCM63XX-replace-irq-dispatch-code-with-a-generi.patch new file mode 100644 index 0000000000..f0311ce90c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/320-MIPS-BCM63XX-replace-irq-dispatch-code-with-a-generi.patch @@ -0,0 +1,167 @@ +From 01bf26c51b427e24ac69f604d33f7d9360a9e470 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 18 Apr 2013 21:14:49 +0200 +Subject: [PATCH 31/53] MIPS: BCM63XX: replace irq dispatch code with a generic + version + +The generic version uses a variable length of u32 registers of u32/u64. +This allows easier support for longer registers without having to rewrite +verything. + +This "generic" version is not slower than the old version in the best case +(= i == next set bit), and twice as fast in the worst case in 64 bits. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 130 +++++++++++++++++++++--------------------------- + 1 file changed, 56 insertions(+), 74 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -51,47 +51,65 @@ static inline void handle_internal(int i + * will resume the loop where it ended the last time we left this + * function. + */ +-static void __dispatch_internal_32(void) +-{ +- u32 pending; +- static int i; +- +- pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr); +- +- if (!pending) +- return ; +- +- while (1) { +- int to_call = i; + +- i = (i + 1) & 0x1f; +- if (pending & (1 << to_call)) { +- handle_internal(to_call); +- break; +- } +- } ++#define BUILD_IPIC_INTERNAL(width) \ ++void __dispatch_internal_##width(void) \ ++{ \ ++ u32 pending[width / 32]; \ ++ unsigned int src, tgt; \ ++ bool irqs_pending = false; \ ++ static int i; \ ++ \ ++ /* read registers in reverse order */ \ ++ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ ++ u32 val; \ ++ \ ++ val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \ ++ val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \ ++ pending[--tgt] = val; \ ++ \ ++ if (val) \ ++ irqs_pending = true; \ ++ } \ ++ \ ++ if (!irqs_pending) \ ++ return; \ ++ \ ++ while (1) { \ ++ int to_call = i; \ ++ \ ++ i = (i + 1) & (width - 1); \ ++ if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ ++ handle_internal(to_call); \ ++ break; \ ++ } \ ++ } \ ++} \ ++ \ ++static void __internal_irq_mask_##width(unsigned int irq) \ ++{ \ ++ u32 val; \ ++ unsigned reg = (irq / 32) ^ (width/32 - 1); \ ++ unsigned bit = irq & 0x1f; \ ++ \ ++ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ ++ val &= ~(1 << bit); \ ++ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ ++} \ ++ \ ++static void __internal_irq_unmask_##width(unsigned int irq) \ ++{ \ ++ u32 val; \ ++ unsigned reg = (irq / 32) ^ (width/32 - 1); \ ++ unsigned bit = irq & 0x1f; \ ++ \ ++ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ ++ val |= (1 << bit); \ ++ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ + } + +-static void __dispatch_internal_64(void) +-{ +- u64 pending; +- static int i; +- +- pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr); +- +- if (!pending) +- return ; +- +- while (1) { +- int to_call = i; +- +- i = (i + 1) & 0x3f; +- if (pending & (1ull << to_call)) { +- handle_internal(to_call); +- break; +- } +- } +-} ++BUILD_IPIC_INTERNAL(32); ++BUILD_IPIC_INTERNAL(64); + + asmlinkage void plat_irq_dispatch(void) + { +@@ -128,42 +146,6 @@ asmlinkage void plat_irq_dispatch(void) + * internal IRQs operations: only mask/unmask on PERF irq mask + * register. + */ +-static void __internal_irq_mask_32(unsigned int irq) +-{ +- u32 mask; +- +- mask = bcm_readl(irq_mask_addr); +- mask &= ~(1 << irq); +- bcm_writel(mask, irq_mask_addr); +-} +- +-static void __internal_irq_mask_64(unsigned int irq) +-{ +- u64 mask; +- +- mask = bcm_readq(irq_mask_addr); +- mask &= ~(1ull << irq); +- bcm_writeq(mask, irq_mask_addr); +-} +- +-static void __internal_irq_unmask_32(unsigned int irq) +-{ +- u32 mask; +- +- mask = bcm_readl(irq_mask_addr); +- mask |= (1 << irq); +- bcm_writel(mask, irq_mask_addr); +-} +- +-static void __internal_irq_unmask_64(unsigned int irq) +-{ +- u64 mask; +- +- mask = bcm_readq(irq_mask_addr); +- mask |= (1ull << irq); +- bcm_writeq(mask, irq_mask_addr); +-} +- + static void bcm63xx_internal_irq_mask(struct irq_data *d) + { + internal_irq_mask(d->irq - IRQ_INTERNAL_BASE); diff --git a/target/linux/brcm63xx/patches-3.13/321-MIPS-BCM63XX-append-irq-line-number-to-irq_-stat-mas.patch b/target/linux/brcm63xx/patches-3.13/321-MIPS-BCM63XX-append-irq-line-number-to-irq_-stat-mas.patch new file mode 100644 index 0000000000..e53f230df8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/321-MIPS-BCM63XX-append-irq-line-number-to-irq_-stat-mas.patch @@ -0,0 +1,183 @@ +From 1003fb4a5ee9fcff518f20eefdee1a9bf500af7e Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 25 Apr 2013 00:24:06 +0200 +Subject: [PATCH 32/53] MIPS: BCM63XX: append irq line number to + irq_{stat,mask}* + +The SMP capable irq controllers have two interupt output pins which are +controlled through separate registers, so make the variables arrays. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 51 ++++++++++++----------- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 +++---- + 2 files changed, 34 insertions(+), 33 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -19,7 +19,8 @@ + #include <bcm63xx_io.h> + #include <bcm63xx_irq.h> + +-static u32 irq_stat_addr, irq_mask_addr; ++static u32 irq_stat_addr[2]; ++static u32 irq_mask_addr[2]; + static void (*dispatch_internal)(void); + static int is_ext_irq_cascaded; + static unsigned int ext_irq_count; +@@ -64,8 +65,8 @@ void __dispatch_internal_##width(void) + for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ + u32 val; \ + \ +- val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \ +- val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \ ++ val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \ ++ val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \ + pending[--tgt] = val; \ + \ + if (val) \ +@@ -92,9 +93,9 @@ static void __internal_irq_mask_##width( + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ + \ +- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ ++ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ + val &= ~(1 << bit); \ +- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ ++ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ + } \ + \ + static void __internal_irq_unmask_##width(unsigned int irq) \ +@@ -103,9 +104,9 @@ static void __internal_irq_unmask_##widt + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ + \ +- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ ++ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ + val |= (1 << bit); \ +- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ ++ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ + } + + BUILD_IPIC_INTERNAL(32); +@@ -339,20 +340,20 @@ static void bcm63xx_init_irq(void) + { + int irq_bits; + +- irq_stat_addr = bcm63xx_regset_address(RSET_PERF); +- irq_mask_addr = bcm63xx_regset_address(RSET_PERF); ++ irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); ++ irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); + + switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_3368_REG; +- irq_mask_addr += PERF_IRQMASK_3368_REG; ++ irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; ++ irq_mask_addr[0] += PERF_IRQMASK_3368_REG; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; + break; + case BCM6328_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6328_REG; +- irq_mask_addr += PERF_IRQMASK_6328_REG; ++ irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); ++ irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); + irq_bits = 64; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; +@@ -361,29 +362,29 @@ static void bcm63xx_init_irq(void) + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; + break; + case BCM6338_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6338_REG; +- irq_mask_addr += PERF_IRQMASK_6338_REG; ++ irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; ++ irq_mask_addr[0] += PERF_IRQMASK_6338_REG; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; + break; + case BCM6345_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6345_REG; +- irq_mask_addr += PERF_IRQMASK_6345_REG; ++ irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; ++ irq_mask_addr[0] += PERF_IRQMASK_6345_REG; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; + break; + case BCM6348_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6348_REG; +- irq_mask_addr += PERF_IRQMASK_6348_REG; ++ irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; ++ irq_mask_addr[0] += PERF_IRQMASK_6348_REG; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; + break; + case BCM6358_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6358_REG; +- irq_mask_addr += PERF_IRQMASK_6358_REG; ++ irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); ++ irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); + irq_bits = 32; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; +@@ -392,8 +393,8 @@ static void bcm63xx_init_irq(void) + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; + break; + case BCM6362_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6362_REG; +- irq_mask_addr += PERF_IRQMASK_6362_REG; ++ irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); ++ irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); + irq_bits = 64; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; +@@ -402,8 +403,8 @@ static void bcm63xx_init_irq(void) + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; + break; + case BCM6368_CPU_ID: +- irq_stat_addr += PERF_IRQSTAT_6368_REG; +- irq_mask_addr += PERF_IRQMASK_6368_REG; ++ irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); ++ irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); + irq_bits = 64; + ext_irq_count = 6; + is_ext_irq_cascaded = 1; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -215,23 +215,23 @@ + + /* Interrupt Mask register */ + #define PERF_IRQMASK_3368_REG 0xc +-#define PERF_IRQMASK_6328_REG 0x20 ++#define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10) + #define PERF_IRQMASK_6338_REG 0xc + #define PERF_IRQMASK_6345_REG 0xc + #define PERF_IRQMASK_6348_REG 0xc +-#define PERF_IRQMASK_6358_REG 0xc +-#define PERF_IRQMASK_6362_REG 0x20 +-#define PERF_IRQMASK_6368_REG 0x20 ++#define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c) ++#define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10) ++#define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10) + + /* Interrupt Status register */ + #define PERF_IRQSTAT_3368_REG 0x10 +-#define PERF_IRQSTAT_6328_REG 0x28 ++#define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10) + #define PERF_IRQSTAT_6338_REG 0x10 + #define PERF_IRQSTAT_6345_REG 0x10 + #define PERF_IRQSTAT_6348_REG 0x10 +-#define PERF_IRQSTAT_6358_REG 0x10 +-#define PERF_IRQSTAT_6362_REG 0x28 +-#define PERF_IRQSTAT_6368_REG 0x28 ++#define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c) ++#define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10) ++#define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10) + + /* External Interrupt Configuration register */ + #define PERF_EXTIRQ_CFG_REG_3368 0x14 diff --git a/target/linux/brcm63xx/patches-3.13/322-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch b/target/linux/brcm63xx/patches-3.13/322-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch new file mode 100644 index 0000000000..a21137fe50 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/322-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch @@ -0,0 +1,92 @@ +From 842f213228e6fc9fd6cca01ab5128623112aa7a9 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 25 Apr 2013 00:31:29 +0200 +Subject: [PATCH 33/53] MIPS: BCM63XX: populate irq_{stat,mask}_addr for second + pin + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -342,11 +342,15 @@ static void bcm63xx_init_irq(void) + + irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); + irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); ++ irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF); ++ irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF); + + switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: + irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; + irq_mask_addr[0] += PERF_IRQMASK_3368_REG; ++ irq_stat_addr[1] = 0; ++ irq_stat_addr[1] = 0; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; +@@ -354,6 +358,8 @@ static void bcm63xx_init_irq(void) + case BCM6328_CPU_ID: + irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); + irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); ++ irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1); ++ irq_stat_addr[1] += PERF_IRQMASK_6328_REG(1); + irq_bits = 64; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; +@@ -364,6 +370,8 @@ static void bcm63xx_init_irq(void) + case BCM6338_CPU_ID: + irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; + irq_mask_addr[0] += PERF_IRQMASK_6338_REG; ++ irq_stat_addr[1] = 0; ++ irq_mask_addr[1] = 0; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; +@@ -371,6 +379,8 @@ static void bcm63xx_init_irq(void) + case BCM6345_CPU_ID: + irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; + irq_mask_addr[0] += PERF_IRQMASK_6345_REG; ++ irq_stat_addr[1] = 0; ++ irq_mask_addr[1] = 0; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; +@@ -378,6 +388,8 @@ static void bcm63xx_init_irq(void) + case BCM6348_CPU_ID: + irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; + irq_mask_addr[0] += PERF_IRQMASK_6348_REG; ++ irq_stat_addr[1] = 0; ++ irq_mask_addr[1] = 0; + irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; +@@ -385,6 +397,8 @@ static void bcm63xx_init_irq(void) + case BCM6358_CPU_ID: + irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); + irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); ++ irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1); ++ irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1); + irq_bits = 32; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; +@@ -395,6 +409,8 @@ static void bcm63xx_init_irq(void) + case BCM6362_CPU_ID: + irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); + irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); ++ irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1); ++ irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1); + irq_bits = 64; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; +@@ -405,6 +421,8 @@ static void bcm63xx_init_irq(void) + case BCM6368_CPU_ID: + irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); + irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); ++ irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1); ++ irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1); + irq_bits = 64; + ext_irq_count = 6; + is_ext_irq_cascaded = 1; diff --git a/target/linux/brcm63xx/patches-3.13/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch b/target/linux/brcm63xx/patches-3.13/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch new file mode 100644 index 0000000000..1b8921cbf2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch @@ -0,0 +1,70 @@ +From a33bb660c712447ba8b561109cda6734954a6efa Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Fri, 26 Apr 2013 11:21:16 +0200 +Subject: [PATCH 34/53] MIPS: BCM63XX: add pin argument to dispatch internal + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 18 ++++++++++-------- + 1 file changed, 10 insertions(+), 8 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -19,9 +19,10 @@ + #include <bcm63xx_io.h> + #include <bcm63xx_irq.h> + ++ + static u32 irq_stat_addr[2]; + static u32 irq_mask_addr[2]; +-static void (*dispatch_internal)(void); ++static void (*dispatch_internal)(int pin); + static int is_ext_irq_cascaded; + static unsigned int ext_irq_count; + static unsigned int ext_irq_start, ext_irq_end; +@@ -54,19 +55,20 @@ static inline void handle_internal(int i + */ + + #define BUILD_IPIC_INTERNAL(width) \ +-void __dispatch_internal_##width(void) \ ++void __dispatch_internal_##width(int pin) \ + { \ + u32 pending[width / 32]; \ + unsigned int src, tgt; \ + bool irqs_pending = false; \ +- static int i; \ ++ static int i[2]; \ ++ int *next = &i[pin]; \ + \ + /* read registers in reverse order */ \ + for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ + u32 val; \ + \ +- val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \ +- val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \ ++ val = bcm_readl(irq_stat_addr[pin] + src * sizeof(u32)); \ ++ val &= bcm_readl(irq_mask_addr[pin] + src * sizeof(u32)); \ + pending[--tgt] = val; \ + \ + if (val) \ +@@ -77,9 +79,9 @@ void __dispatch_internal_##width(void) + return; \ + \ + while (1) { \ +- int to_call = i; \ ++ int to_call = *next; \ + \ +- i = (i + 1) & (width - 1); \ ++ *next = (*next + 1) & (width - 1); \ + if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ + handle_internal(to_call); \ + break; \ +@@ -129,7 +131,7 @@ asmlinkage void plat_irq_dispatch(void) + if (cause & CAUSEF_IP1) + do_IRQ(1); + if (cause & CAUSEF_IP2) +- dispatch_internal(); ++ dispatch_internal(0); + if (!is_ext_irq_cascaded) { + if (cause & CAUSEF_IP3) + do_IRQ(IRQ_EXT_0); diff --git a/target/linux/brcm63xx/patches-3.13/324-MIPS-BCM63XX-protect-irq-register-accesses.patch b/target/linux/brcm63xx/patches-3.13/324-MIPS-BCM63XX-protect-irq-register-accesses.patch new file mode 100644 index 0000000000..c38137dc81 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/324-MIPS-BCM63XX-protect-irq-register-accesses.patch @@ -0,0 +1,158 @@ +From 85257b702e1d4c6dcc839c737833c42ca53bae93 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 21 Apr 2013 15:38:56 +0200 +Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses + +--- + arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -12,6 +12,7 @@ + #include <linux/interrupt.h> + #include <linux/module.h> + #include <linux/irq.h> ++#include <linux/spinlock.h> + #include <asm/irq_cpu.h> + #include <asm/mipsregs.h> + #include <bcm63xx_cpu.h> +@@ -20,6 +21,9 @@ + #include <bcm63xx_irq.h> + + ++static DEFINE_SPINLOCK(ipic_lock); ++static DEFINE_SPINLOCK(epic_lock); ++ + static u32 irq_stat_addr[2]; + static u32 irq_mask_addr[2]; + static void (*dispatch_internal)(int pin); +@@ -62,8 +66,10 @@ void __dispatch_internal_##width(int pin + bool irqs_pending = false; \ + static int i[2]; \ + int *next = &i[pin]; \ ++ unsigned long flags; \ + \ + /* read registers in reverse order */ \ ++ spin_lock_irqsave(&ipic_lock, flags); \ + for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ + u32 val; \ + \ +@@ -74,6 +80,7 @@ void __dispatch_internal_##width(int pin + if (val) \ + irqs_pending = true; \ + } \ ++ spin_unlock_irqrestore(&ipic_lock, flags); \ + \ + if (!irqs_pending) \ + return; \ +@@ -94,10 +101,13 @@ static void __internal_irq_mask_##width( + u32 val; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ ++ unsigned long flags; \ + \ ++ spin_lock_irqsave(&ipic_lock, flags); \ + val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ + val &= ~(1 << bit); \ + bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ ++ spin_unlock_irqrestore(&ipic_lock, flags); \ + } \ + \ + static void __internal_irq_unmask_##width(unsigned int irq) \ +@@ -105,10 +115,13 @@ static void __internal_irq_unmask_##widt + u32 val; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ ++ unsigned long flags; \ + \ ++ spin_lock_irqsave(&ipic_lock, flags); \ + val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ + val |= (1 << bit); \ + bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ ++ spin_unlock_irqrestore(&ipic_lock, flags); \ + } + + BUILD_IPIC_INTERNAL(32); +@@ -167,8 +180,10 @@ static void bcm63xx_external_irq_mask(st + { + unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; + u32 reg, regaddr; ++ unsigned long flags; + + regaddr = get_ext_irq_perf_reg(irq); ++ spin_lock_irqsave(&epic_lock, flags); + reg = bcm_perf_readl(regaddr); + + if (BCMCPU_IS_6348()) +@@ -177,6 +192,8 @@ static void bcm63xx_external_irq_mask(st + reg &= ~EXTIRQ_CFG_MASK(irq % 4); + + bcm_perf_writel(reg, regaddr); ++ spin_unlock_irqrestore(&epic_lock, flags); ++ + if (is_ext_irq_cascaded) + internal_irq_mask(irq + ext_irq_start); + } +@@ -185,8 +202,10 @@ static void bcm63xx_external_irq_unmask( + { + unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; + u32 reg, regaddr; ++ unsigned long flags; + + regaddr = get_ext_irq_perf_reg(irq); ++ spin_lock_irqsave(&epic_lock, flags); + reg = bcm_perf_readl(regaddr); + + if (BCMCPU_IS_6348()) +@@ -195,6 +214,7 @@ static void bcm63xx_external_irq_unmask( + reg |= EXTIRQ_CFG_MASK(irq % 4); + + bcm_perf_writel(reg, regaddr); ++ spin_unlock_irqrestore(&epic_lock, flags); + + if (is_ext_irq_cascaded) + internal_irq_unmask(irq + ext_irq_start); +@@ -204,8 +224,10 @@ static void bcm63xx_external_irq_clear(s + { + unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; + u32 reg, regaddr; ++ unsigned long flags; + + regaddr = get_ext_irq_perf_reg(irq); ++ spin_lock_irqsave(&epic_lock, flags); + reg = bcm_perf_readl(regaddr); + + if (BCMCPU_IS_6348()) +@@ -214,6 +236,7 @@ static void bcm63xx_external_irq_clear(s + reg |= EXTIRQ_CFG_CLEAR(irq % 4); + + bcm_perf_writel(reg, regaddr); ++ spin_unlock_irqrestore(&epic_lock, flags); + } + + static int bcm63xx_external_irq_set_type(struct irq_data *d, +@@ -222,6 +245,7 @@ static int bcm63xx_external_irq_set_type + unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; + u32 reg, regaddr; + int levelsense, sense, bothedge; ++ unsigned long flags; + + flow_type &= IRQ_TYPE_SENSE_MASK; + +@@ -256,6 +280,7 @@ static int bcm63xx_external_irq_set_type + } + + regaddr = get_ext_irq_perf_reg(irq); ++ spin_lock_irqsave(&epic_lock, flags); + reg = bcm_perf_readl(regaddr); + irq %= 4; + +@@ -300,6 +325,7 @@ static int bcm63xx_external_irq_set_type + } + + bcm_perf_writel(reg, regaddr); ++ spin_unlock_irqrestore(&epic_lock, flags); + + irqd_set_trigger_type(d, flow_type); + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) diff --git a/target/linux/brcm63xx/patches-3.13/325-MIPS-BCM63XX-wire-up-the-second-cpu-s-irq-line.patch b/target/linux/brcm63xx/patches-3.13/325-MIPS-BCM63XX-wire-up-the-second-cpu-s-irq-line.patch new file mode 100644 index 0000000000..189965a971 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/325-MIPS-BCM63XX-wire-up-the-second-cpu-s-irq-line.patch @@ -0,0 +1,92 @@ +From df6661d1b5c001eb91ce07f364fd5b6468fd6f99 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Fri, 26 Apr 2013 12:03:15 +0200 +Subject: [PATCH 36/53] MIPS: BCM63XX: wire up the second cpu's irq line + +--- + arch/mips/bcm63xx/irq.c | 44 +++++++++++++++++++++++++++++++++++++------- + 1 file changed, 37 insertions(+), 7 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -102,11 +102,17 @@ static void __internal_irq_mask_##width( + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ + unsigned long flags; \ ++ int cpu; \ + \ + spin_lock_irqsave(&ipic_lock, flags); \ +- val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ +- val &= ~(1 << bit); \ +- bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ ++ for_each_present_cpu(cpu) { \ ++ if (!irq_mask_addr[cpu]) \ ++ break; \ ++ \ ++ val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ ++ val &= ~(1 << bit); \ ++ bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ ++ } \ + spin_unlock_irqrestore(&ipic_lock, flags); \ + } \ + \ +@@ -116,11 +122,20 @@ static void __internal_irq_unmask_##widt + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ + unsigned long flags; \ ++ int cpu; \ + \ + spin_lock_irqsave(&ipic_lock, flags); \ +- val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \ +- val |= (1 << bit); \ +- bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \ ++ for_each_present_cpu(cpu) { \ ++ if (!irq_mask_addr[cpu]) \ ++ break; \ ++ \ ++ val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ ++ if (cpu_online(cpu)) \ ++ val |= (1 << bit); \ ++ else \ ++ val &= ~(1 << bit); \ ++ bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ ++ } \ + spin_unlock_irqrestore(&ipic_lock, flags); \ + } + +@@ -145,7 +160,10 @@ asmlinkage void plat_irq_dispatch(void) + do_IRQ(1); + if (cause & CAUSEF_IP2) + dispatch_internal(0); +- if (!is_ext_irq_cascaded) { ++ if (is_ext_irq_cascaded) { ++ if (cause & CAUSEF_IP3) ++ dispatch_internal(1); ++ } else { + if (cause & CAUSEF_IP3) + do_IRQ(IRQ_EXT_0); + if (cause & CAUSEF_IP4) +@@ -358,6 +376,14 @@ static struct irqaction cpu_ip2_cascade_ + .flags = IRQF_NO_THREAD, + }; + ++#ifdef CONFIG_SMP ++static struct irqaction cpu_ip3_cascade_action = { ++ .handler = no_action, ++ .name = "cascade_ip3", ++ .flags = IRQF_NO_THREAD, ++}; ++#endif ++ + static struct irqaction cpu_ext_cascade_action = { + .handler = no_action, + .name = "cascade_extirq", +@@ -494,4 +520,8 @@ void __init arch_init_irq(void) + } + + setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); ++#ifdef CONFIG_SMP ++ if (is_ext_irq_cascaded) ++ setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); ++#endif + } diff --git a/target/linux/brcm63xx/patches-3.13/326-MIPS-BCM63XX-use-irq_desc-as-argument-for-un-mask.patch b/target/linux/brcm63xx/patches-3.13/326-MIPS-BCM63XX-use-irq_desc-as-argument-for-un-mask.patch new file mode 100644 index 0000000000..468cbc34a6 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/326-MIPS-BCM63XX-use-irq_desc-as-argument-for-un-mask.patch @@ -0,0 +1,83 @@ +From b665117faa0dfde70689502fc420d72bbf8e6bd4 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Tue, 30 Apr 2013 11:26:53 +0200 +Subject: [PATCH 37/53] MIPS: BCM63XX: use irq_desc as argument for (un)mask + +In preparation for applying affinity, use the irq descriptor as the +argument for (un)mask. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 18 ++++++++++-------- + 1 file changed, 10 insertions(+), 8 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -31,8 +31,8 @@ static int is_ext_irq_cascaded; + static unsigned int ext_irq_count; + static unsigned int ext_irq_start, ext_irq_end; + static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; +-static void (*internal_irq_mask)(unsigned int irq); +-static void (*internal_irq_unmask)(unsigned int irq); ++static void (*internal_irq_mask)(struct irq_data *d); ++static void (*internal_irq_unmask)(struct irq_data *d); + + + static inline u32 get_ext_irq_perf_reg(int irq) +@@ -96,9 +96,10 @@ void __dispatch_internal_##width(int pin + } \ + } \ + \ +-static void __internal_irq_mask_##width(unsigned int irq) \ ++static void __internal_irq_mask_##width(struct irq_data *d) \ + { \ + u32 val; \ ++ unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ + unsigned long flags; \ +@@ -116,9 +117,10 @@ static void __internal_irq_mask_##width( + spin_unlock_irqrestore(&ipic_lock, flags); \ + } \ + \ +-static void __internal_irq_unmask_##width(unsigned int irq) \ ++static void __internal_irq_unmask_##width(struct irq_data *d) \ + { \ + u32 val; \ ++ unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ + unsigned long flags; \ +@@ -182,12 +184,12 @@ asmlinkage void plat_irq_dispatch(void) + */ + static void bcm63xx_internal_irq_mask(struct irq_data *d) + { +- internal_irq_mask(d->irq - IRQ_INTERNAL_BASE); ++ internal_irq_mask(d); + } + + static void bcm63xx_internal_irq_unmask(struct irq_data *d) + { +- internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE); ++ internal_irq_unmask(d); + } + + /* +@@ -213,7 +215,7 @@ static void bcm63xx_external_irq_mask(st + spin_unlock_irqrestore(&epic_lock, flags); + + if (is_ext_irq_cascaded) +- internal_irq_mask(irq + ext_irq_start); ++ internal_irq_mask(irq_get_irq_data(irq + ext_irq_start)); + } + + static void bcm63xx_external_irq_unmask(struct irq_data *d) +@@ -235,7 +237,7 @@ static void bcm63xx_external_irq_unmask( + spin_unlock_irqrestore(&epic_lock, flags); + + if (is_ext_irq_cascaded) +- internal_irq_unmask(irq + ext_irq_start); ++ internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start)); + } + + static void bcm63xx_external_irq_clear(struct irq_data *d) diff --git a/target/linux/brcm63xx/patches-3.13/327-MIPS-BCM63XX-allow-setting-affinity-for-IPIC.patch b/target/linux/brcm63xx/patches-3.13/327-MIPS-BCM63XX-allow-setting-affinity-for-IPIC.patch new file mode 100644 index 0000000000..9394e230ef --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/327-MIPS-BCM63XX-allow-setting-affinity-for-IPIC.patch @@ -0,0 +1,111 @@ +From 9249f2f6a309e3f45c35d16decdcc5b2cadcadb8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Fri, 26 Apr 2013 12:06:03 +0200 +Subject: [PATCH 38/53] MIPS: BCM63XX: allow setting affinity for IPIC + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 43 +++++++++++++++++++++++++++++++++++++------ + 1 file changed, 37 insertions(+), 6 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -32,7 +32,7 @@ static unsigned int ext_irq_count; + static unsigned int ext_irq_start, ext_irq_end; + static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; + static void (*internal_irq_mask)(struct irq_data *d); +-static void (*internal_irq_unmask)(struct irq_data *d); ++static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m); + + + static inline u32 get_ext_irq_perf_reg(int irq) +@@ -51,6 +51,20 @@ static inline void handle_internal(int i + do_IRQ(intbit + IRQ_INTERNAL_BASE); + } + ++static inline int enable_irq_for_cpu(int cpu, struct irq_data *d, ++ const struct cpumask *m) ++{ ++ bool enable = cpu_online(cpu); ++#ifdef CONFIG_SMP ++ ++ if (m) ++ enable &= cpu_isset(cpu, *m); ++ else if (irqd_affinity_was_set(d)) ++ enable &= cpu_isset(cpu, *d->affinity); ++#endif ++ return enable; ++} ++ + /* + * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not + * prioritize any interrupt relatively to another. the static counter +@@ -117,7 +131,8 @@ static void __internal_irq_mask_##width( + spin_unlock_irqrestore(&ipic_lock, flags); \ + } \ + \ +-static void __internal_irq_unmask_##width(struct irq_data *d) \ ++static void __internal_irq_unmask_##width(struct irq_data *d, \ ++ const struct cpumask *m) \ + { \ + u32 val; \ + unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ +@@ -132,7 +147,7 @@ static void __internal_irq_unmask_##widt + break; \ + \ + val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ +- if (cpu_online(cpu)) \ ++ if (enable_irq_for_cpu(cpu, d, m)) \ + val |= (1 << bit); \ + else \ + val &= ~(1 << bit); \ +@@ -189,7 +204,7 @@ static void bcm63xx_internal_irq_mask(st + + static void bcm63xx_internal_irq_unmask(struct irq_data *d) + { +- internal_irq_unmask(d); ++ internal_irq_unmask(d, NULL); + } + + /* +@@ -237,7 +252,8 @@ static void bcm63xx_external_irq_unmask( + spin_unlock_irqrestore(&epic_lock, flags); + + if (is_ext_irq_cascaded) +- internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start)); ++ internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start), ++ NULL); + } + + static void bcm63xx_external_irq_clear(struct irq_data *d) +@@ -356,6 +372,18 @@ static int bcm63xx_external_irq_set_type + return IRQ_SET_MASK_OK_NOCOPY; + } + ++#ifdef CONFIG_SMP ++static int bcm63xx_internal_set_affinity(struct irq_data *data, ++ const struct cpumask *dest, ++ bool force) ++{ ++ if (!irqd_irq_disabled(data)) ++ internal_irq_unmask(data, dest); ++ ++ return 0; ++} ++#endif ++ + static struct irq_chip bcm63xx_internal_irq_chip = { + .name = "bcm63xx_ipic", + .irq_mask = bcm63xx_internal_irq_mask, +@@ -523,7 +551,10 @@ void __init arch_init_irq(void) + + setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); + #ifdef CONFIG_SMP +- if (is_ext_irq_cascaded) ++ if (is_ext_irq_cascaded) { + setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); ++ bcm63xx_internal_irq_chip.irq_set_affinity = ++ bcm63xx_internal_set_affinity; ++ } + #endif + } diff --git a/target/linux/brcm63xx/patches-3.13/328-cfe_simplify_detection.patch b/target/linux/brcm63xx/patches-3.13/328-cfe_simplify_detection.patch new file mode 100644 index 0000000000..e05c91d931 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/328-cfe_simplify_detection.patch @@ -0,0 +1,20 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h +@@ -1,6 +1,8 @@ + #ifndef BCM63XX_BOARD_H_ + #define BCM63XX_BOARD_H_ + ++#include <asm/bootinfo.h> ++ + const char *board_get_name(void); + + void board_prom_init(void); +@@ -9,4 +11,8 @@ void board_setup(void); + + int board_register_devices(void); + ++static inline bool bcm63xx_is_cfe_present(void) { ++ return fw_arg3 == 0x43464531; ++} ++ + #endif /* ! BCM63XX_BOARD_H_ */ diff --git a/target/linux/brcm63xx/patches-3.13/329-bcm63xxpart_use_cfedetection.patch b/target/linux/brcm63xx/patches-3.13/329-bcm63xxpart_use_cfedetection.patch new file mode 100644 index 0000000000..dedd728ce9 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/329-bcm63xxpart_use_cfedetection.patch @@ -0,0 +1,51 @@ +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -35,7 +35,7 @@ + + #include <asm/mach-bcm63xx/bcm63xx_nvram.h> + #include <linux/bcm963xx_tag.h> +-#include <asm/mach-bcm63xx/board_bcm963xx.h> ++#include <asm/mach-bcm63xx/bcm63xx_board.h> + + #define BCM63XX_EXTENDED_SIZE 0xBFC00000 /* Extended flash address */ + +@@ -43,30 +43,6 @@ + + #define BCM63XX_CFE_MAGIC_OFFSET 0x4e0 + +-static int bcm63xx_detect_cfe(struct mtd_info *master) +-{ +- char buf[9]; +- int ret; +- size_t retlen; +- +- ret = mtd_read(master, BCM963XX_CFE_VERSION_OFFSET, 5, &retlen, +- (void *)buf); +- buf[retlen] = 0; +- +- if (ret) +- return ret; +- +- if (strncmp("cfe-v", buf, 5) == 0) +- return 0; +- +- /* very old CFE's do not have the cfe-v string, so check for magic */ +- ret = mtd_read(master, BCM63XX_CFE_MAGIC_OFFSET, 8, &retlen, +- (void *)buf); +- buf[retlen] = 0; +- +- return strncmp("CFE1CFE1", buf, 8); +-} +- + static int bcm63xx_parse_cfe_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -85,7 +61,7 @@ static int bcm63xx_parse_cfe_partitions( + u32 computed_crc; + bool rootfs_first = false; + +- if (bcm63xx_detect_cfe(master)) ++ if (!bcm63xx_is_cfe_present()) + return -EINVAL; + + cfe_erasesize = max_t(uint32_t, master->erasesize, diff --git a/target/linux/brcm63xx/patches-3.13/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch b/target/linux/brcm63xx/patches-3.13/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch new file mode 100644 index 0000000000..2cf02f6c5b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch @@ -0,0 +1,77 @@ +From c50acd37b425a8a907a6f7f93aa2e658256e79ce Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:08:36 +0100 +Subject: [PATCH 40/53] MIPS: BCM63XX: add a new cpu variant helper + +--- + arch/mips/bcm63xx/cpu.c | 10 ++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++ + 2 files changed, 28 insertions(+) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -27,6 +27,8 @@ EXPORT_SYMBOL(bcm63xx_irqs); + u16 bcm63xx_cpu_id __read_mostly; + EXPORT_SYMBOL(bcm63xx_cpu_id); + ++static u32 bcm63xx_cpu_variant __read_mostly; ++ + static u8 bcm63xx_cpu_rev; + static unsigned int bcm63xx_cpu_freq; + static unsigned int bcm63xx_memory_size; +@@ -99,6 +101,13 @@ static const int bcm6368_irqs[] = { + + }; + ++u32 bcm63xx_get_cpu_variant(void) ++{ ++ return bcm63xx_cpu_variant; ++} ++ ++EXPORT_SYMBOL(bcm63xx_get_cpu_variant); ++ + u8 bcm63xx_get_cpu_rev(void) + { + return bcm63xx_cpu_rev; +@@ -332,6 +341,7 @@ void __init bcm63xx_cpu_init(void) + /* read out CPU type */ + tmp = bcm_readl(chipid_reg); + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; ++ bcm63xx_cpu_variant = bcm63xx_cpu_id; + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; + + switch (bcm63xx_cpu_id) { +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -19,6 +19,7 @@ + #define BCM6368_CPU_ID 0x6368 + + void __init bcm63xx_cpu_init(void); ++u32 bcm63xx_get_cpu_variant(void); + u8 bcm63xx_get_cpu_rev(void); + unsigned int bcm63xx_get_cpu_freq(void); + +@@ -82,6 +83,23 @@ static inline u16 __pure bcm63xx_get_cpu + #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) + #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) + ++#define BCMCPU_VARIANT_IS_3368() \ ++ (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) ++#define BCMCPU_VARIANT_IS_6328() \ ++ (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID) ++#define BCMCPU_VARIANT_IS_6338() \ ++ (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID) ++#define BCMCPU_VARIANT_IS_6345() \ ++ (bcm63xx_get_cpu_variant() == BCM6345_CPU_ID) ++#define BCMCPU_VARIANT_IS_6348() \ ++ (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID) ++#define BCMCPU_VARIANT_IS_6358() \ ++ (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID) ++#define BCMCPU_VARIANT_IS_6362() \ ++ (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) ++#define BCMCPU_VARIANT_IS_6368() \ ++ (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) ++ + /* + * While registers sets are (mostly) the same across 63xx CPU, base + * address of these sets do change. diff --git a/target/linux/brcm63xx/patches-3.13/331-MIPS-BCM63XX-define-variant-id-field.patch b/target/linux/brcm63xx/patches-3.13/331-MIPS-BCM63XX-define-variant-id-field.patch new file mode 100644 index 0000000000..0ffc5bd0f5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/331-MIPS-BCM63XX-define-variant-id-field.patch @@ -0,0 +1,20 @@ +From 9cd8b4a2ee9d0e6a5b91845bdd6f4b7e114fc8c4 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:22:41 +0100 +Subject: [PATCH 41/53] MIPS: BCM63XX: define variant id field + +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -9,6 +9,8 @@ + #define PERF_REV_REG 0x0 + #define REV_CHIPID_SHIFT 16 + #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) ++#define REV_VARID_SHIFT 8 ++#define REV_VARID_MASK (0xf << REV_VARID_SHIFT) + #define REV_REVID_SHIFT 0 + #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) + diff --git a/target/linux/brcm63xx/patches-3.13/332-MIPS-BCM63XX-detect-bcm6328-variants.patch b/target/linux/brcm63xx/patches-3.13/332-MIPS-BCM63XX-detect-bcm6328-variants.patch new file mode 100644 index 0000000000..4eb5234a0d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/332-MIPS-BCM63XX-detect-bcm6328-variants.patch @@ -0,0 +1,67 @@ +From 6c8d94aaf5e2f0a3327e4f69ccd980bd5617f925 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:30:59 +0100 +Subject: [PATCH 42/53] MIPS: BCM63XX: detect bcm6328 variants + +--- + arch/mips/bcm63xx/cpu.c | 10 ++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++++-- + 2 files changed, 16 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -304,6 +304,7 @@ void __init bcm63xx_cpu_init(void) + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int cpu = smp_processor_id(); + u32 chipid_reg; ++ u8 __maybe_unused varid = 0; + + /* soc registers location depends on cpu type */ + chipid_reg = 0; +@@ -343,6 +344,7 @@ void __init bcm63xx_cpu_init(void) + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; + bcm63xx_cpu_variant = bcm63xx_cpu_id; + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; ++ varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; + + switch (bcm63xx_cpu_id) { + case BCM3368_CPU_ID: +@@ -352,6 +354,14 @@ void __init bcm63xx_cpu_init(void) + case BCM6328_CPU_ID: + bcm63xx_regs_base = bcm6328_regs_base; + bcm63xx_irqs = bcm6328_irqs; ++ ++ if (varid == 1) ++ bcm63xx_cpu_variant = BCM63281_CPU_ID; ++ else if (varid == 3) ++ bcm63xx_cpu_variant = BCM63283_CPU_ID; ++ else ++ pr_warn("unknown BCM6328 variant: %x\n", varid); ++ + break; + case BCM6338_CPU_ID: + bcm63xx_regs_base = bcm6338_regs_base; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -11,6 +11,8 @@ + */ + #define BCM3368_CPU_ID 0x3368 + #define BCM6328_CPU_ID 0x6328 ++#define BCM63281_CPU_ID 0x63281 ++#define BCM63283_CPU_ID 0x63283 + #define BCM6338_CPU_ID 0x6338 + #define BCM6345_CPU_ID 0x6345 + #define BCM6348_CPU_ID 0x6348 +@@ -85,8 +87,10 @@ static inline u16 __pure bcm63xx_get_cpu + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) +-#define BCMCPU_VARIANT_IS_6328() \ +- (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID) ++#define BCMCPU_VARIANT_IS_63281() \ ++ (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID) ++#define BCMCPU_VARIANT_IS_63283() \ ++ (bcm63xx_get_cpu_variant() == BCM63283_CPU_ID) + #define BCMCPU_VARIANT_IS_6338() \ + (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID) + #define BCMCPU_VARIANT_IS_6345() \ diff --git a/target/linux/brcm63xx/patches-3.13/333-MIPS-BCM63XX-detect-BCM6362-variants.patch b/target/linux/brcm63xx/patches-3.13/333-MIPS-BCM63XX-detect-BCM6362-variants.patch new file mode 100644 index 0000000000..145d18f98c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/333-MIPS-BCM63XX-detect-BCM6362-variants.patch @@ -0,0 +1,46 @@ +From dc48adb13a99086d1f484d3379a918626c5b1658 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:33:28 +0100 +Subject: [PATCH 43/53] MIPS: BCM63XX: detect BCM6362 variants + +--- + arch/mips/bcm63xx/cpu.c | 8 ++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++ + 2 files changed, 11 insertions(+) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -382,6 +382,14 @@ void __init bcm63xx_cpu_init(void) + case BCM6362_CPU_ID: + bcm63xx_regs_base = bcm6362_regs_base; + bcm63xx_irqs = bcm6362_irqs; ++ ++ if (varid == 1) ++ bcm63xx_cpu_variant = BCM6362_CPU_ID; ++ else if (varid == 2) ++ bcm63xx_cpu_variant = BCM6361_CPU_ID; ++ else ++ pr_warn("unknown BCM6362 variant: %x\n", varid); ++ + break; + case BCM6368_CPU_ID: + bcm63xx_regs_base = bcm6368_regs_base; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -17,6 +17,7 @@ + #define BCM6345_CPU_ID 0x6345 + #define BCM6348_CPU_ID 0x6348 + #define BCM6358_CPU_ID 0x6358 ++#define BCM6361_CPU_ID 0x6361 + #define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 + +@@ -99,6 +100,8 @@ static inline u16 __pure bcm63xx_get_cpu + (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID) + #define BCMCPU_VARIANT_IS_6358() \ + (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID) ++#define BCMCPU_VARIANT_IS_6361() \ ++ (bcm63xx_get_cpu_variant() == BCM6361_CPU_ID) + #define BCMCPU_VARIANT_IS_6362() \ + (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) + #define BCMCPU_VARIANT_IS_6368() \ diff --git a/target/linux/brcm63xx/patches-3.13/334-MIPS-BCM63XX-add-support-for-BCM6368-variants.patch b/target/linux/brcm63xx/patches-3.13/334-MIPS-BCM63XX-add-support-for-BCM6368-variants.patch new file mode 100644 index 0000000000..19539cf31e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/334-MIPS-BCM63XX-add-support-for-BCM6368-variants.patch @@ -0,0 +1,44 @@ +From 311b0246d51e09d13464e76abb0e231c855dd333 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:36:56 +0100 +Subject: [PATCH 44/53] MIPS: BCM63XX: add support for BCM6368 variants + +--- + arch/mips/bcm63xx/cpu.c | 4 ++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++ + 2 files changed, 7 insertions(+) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -392,8 +392,12 @@ void __init bcm63xx_cpu_init(void) + + break; + case BCM6368_CPU_ID: ++ case BCM6369_CPU_ID: + bcm63xx_regs_base = bcm6368_regs_base; + bcm63xx_irqs = bcm6368_irqs; ++ ++ /* BCM6369 is a BCM6368 without xDSL, so treat it the same */ ++ bcm63xx_cpu_id = BCM6368_CPU_ID; + break; + default: + panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -20,6 +20,7 @@ + #define BCM6361_CPU_ID 0x6361 + #define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 ++#define BCM6369_CPU_ID 0x6369 + + void __init bcm63xx_cpu_init(void); + u32 bcm63xx_get_cpu_variant(void); +@@ -106,6 +107,8 @@ static inline u16 __pure bcm63xx_get_cpu + (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) + #define BCMCPU_VARIANT_IS_6368() \ + (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) ++#define BCMCPU_VARIANT_IS_6369() \ ++ (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID) + + /* + * While registers sets are (mostly) the same across 63xx CPU, base diff --git a/target/linux/brcm63xx/patches-3.13/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch b/target/linux/brcm63xx/patches-3.13/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch new file mode 100644 index 0000000000..3230add278 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch @@ -0,0 +1,20 @@ +From f67f8134b4537c8bbafe7e1975edfe808b813997 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 8 Dec 2013 03:05:54 +0100 +Subject: [PATCH 45/53] MIPS: BCM63XX: fix PCIe memory window size + +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -41,7 +41,7 @@ + BCM_CB_MEM_SIZE - 1) + + #define BCM_PCIE_MEM_BASE_PA 0x10f00000 +-#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define BCM_PCIE_MEM_SIZE (1 * 1024 * 1024) + #define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \ + BCM_PCIE_MEM_SIZE - 1) + diff --git a/target/linux/brcm63xx/patches-3.13/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch b/target/linux/brcm63xx/patches-3.13/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch new file mode 100644 index 0000000000..d6eb54d2e8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch @@ -0,0 +1,70 @@ +From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 8 Dec 2013 03:13:06 +0100 +Subject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows + +Different SoCs use different memory windows (and sizes), so don't +hardcode it. +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 8 ++++---- + arch/mips/pci/pci-bcm63xx.c | 15 ++++++++++----- + 2 files changed, 14 insertions(+), 9 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -40,10 +40,10 @@ + #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ + BCM_CB_MEM_SIZE - 1) + +-#define BCM_PCIE_MEM_BASE_PA 0x10f00000 +-#define BCM_PCIE_MEM_SIZE (1 * 1024 * 1024) +-#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \ +- BCM_PCIE_MEM_SIZE - 1) ++#define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000 ++#define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024) ++#define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ ++ BCM_PCIE_MEM_SIZE_6328 - 1) + + /* + * Internal registers are accessed through KSEG3 +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control + + static struct resource bcm_pcie_mem_resource = { + .name = "bcm63xx PCIe memory space", +- .start = BCM_PCIE_MEM_BASE_PA, +- .end = BCM_PCIE_MEM_END_PA, ++ .start = 0, ++ .end = 0, + .flags = IORESOURCE_MEM, + }; + +@@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie( + bcm_pcie_writel(val, PCIE_CONFIG2_REG); + + /* set bar0 to little endian */ +- val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; +- val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; ++ val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; ++ val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; + val |= BASEMASK_REMAP_EN; + bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); + +- val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; ++ val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; + bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); + + register_pci_controller(&bcm63xx_pcie_controller); +@@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void) + if (!bcm63xx_pci_enabled) + return -ENODEV; + ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { ++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; ++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; ++ } ++ + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: diff --git a/target/linux/brcm63xx/patches-3.13/337-MIPS-BCM63XX-widen-cpuid-field.patch b/target/linux/brcm63xx/patches-3.13/337-MIPS-BCM63XX-widen-cpuid-field.patch new file mode 100644 index 0000000000..5b641a0026 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/337-MIPS-BCM63XX-widen-cpuid-field.patch @@ -0,0 +1,47 @@ +From f1477f6e3551fd6beecfee5368fed1325dcd421f Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:54:51 +0100 +Subject: [PATCH 47/53] MIPS: BCM63XX: widen cpuid field + +--- + arch/mips/bcm63xx/cpu.c | 2 +- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -24,7 +24,7 @@ EXPORT_SYMBOL(bcm63xx_regs_base); + const int *bcm63xx_irqs; + EXPORT_SYMBOL(bcm63xx_irqs); + +-u16 bcm63xx_cpu_id __read_mostly; ++u32 bcm63xx_cpu_id __read_mostly; + EXPORT_SYMBOL(bcm63xx_cpu_id); + + static u32 bcm63xx_cpu_variant __read_mostly; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -27,7 +27,7 @@ u32 bcm63xx_get_cpu_variant(void); + u8 bcm63xx_get_cpu_rev(void); + unsigned int bcm63xx_get_cpu_freq(void); + +-static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id) ++static inline u32 __pure __bcm63xx_get_cpu_id(const u32 cpu_id) + { + switch (cpu_id) { + #ifdef CONFIG_BCM63XX_CPU_3368 +@@ -69,11 +69,11 @@ static inline u16 __pure __bcm63xx_get_c + return cpu_id; + } + +-extern u16 bcm63xx_cpu_id; ++extern u32 bcm63xx_cpu_id; + +-static inline u16 __pure bcm63xx_get_cpu_id(void) ++static inline u32 __pure bcm63xx_get_cpu_id(void) + { +- const u16 cpu_id = bcm63xx_cpu_id; ++ const u32 cpu_id = bcm63xx_cpu_id; + + return __bcm63xx_get_cpu_id(cpu_id); + } diff --git a/target/linux/brcm63xx/patches-3.13/338-MIPS-BCM63XX-increase-number-of-IRQs.patch b/target/linux/brcm63xx/patches-3.13/338-MIPS-BCM63XX-increase-number-of-IRQs.patch new file mode 100644 index 0000000000..9132e42312 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/338-MIPS-BCM63XX-increase-number-of-IRQs.patch @@ -0,0 +1,39 @@ +From 6f5658c845cf1f79213b1d20423a04967259fdaa Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 15 Dec 2013 20:46:26 +0100 +Subject: [PATCH 48/53] MIPS: BCM63XX: increase number of IRQs + +Newer SoCs have 128 bit wide irq registers, thus 128 available internal +interupts. +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h | 4 +++- + arch/mips/include/asm/mach-bcm63xx/irq.h | 2 +- + 2 files changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h +@@ -1,10 +1,12 @@ + #ifndef BCM63XX_IRQ_H_ + #define BCM63XX_IRQ_H_ + ++#include <irq.h> + #include <bcm63xx_cpu.h> + + #define IRQ_INTERNAL_BASE 8 +-#define IRQ_EXTERNAL_BASE 100 ++#define NR_INTERNAL_IRQS 128 ++#define IRQ_EXTERNAL_BASE (IRQ_INTERNAL_BASE + NR_INTERNAL_IRQS) + #define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0) + #define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1) + #define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2) +--- a/arch/mips/include/asm/mach-bcm63xx/irq.h ++++ b/arch/mips/include/asm/mach-bcm63xx/irq.h +@@ -1,7 +1,7 @@ + #ifndef __ASM_MACH_BCM63XX_IRQ_H + #define __ASM_MACH_BCM63XX_IRQ_H + +-#define NR_IRQS 128 ++#define NR_IRQS 256 + #define MIPS_CPU_IRQ_BASE 0 + + #endif diff --git a/target/linux/brcm63xx/patches-3.13/339-MIPS-BCM63XX-add-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.13/339-MIPS-BCM63XX-add-support-for-BCM63268.patch new file mode 100644 index 0000000000..9c5967f3a3 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/339-MIPS-BCM63XX-add-support-for-BCM63268.patch @@ -0,0 +1,769 @@ +From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 17:14:17 +0100 +Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268 + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/Kconfig | 5 + + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/clk.c | 25 ++++- + arch/mips/bcm63xx/cpu.c | 59 +++++++++- + arch/mips/bcm63xx/dev-flash.c | 6 + + arch/mips/bcm63xx/dev-spi.c | 4 +- + arch/mips/bcm63xx/irq.c | 20 +++- + arch/mips/bcm63xx/reset.c | 21 ++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 130 ++++++++++++++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 + + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 79 +++++++++++++ + arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + + 12 files changed, 342 insertions(+), 12 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -60,6 +60,11 @@ config BCM63XX_CPU_6368 + select HW_HAS_PCI + select BCM63XX_OHCI + select BCM63XX_EHCI ++ ++config BCM63XX_CPU_63268 ++ bool "support 63268 CPU" ++ select SYS_HAS_CPU_BMIPS4350 ++ select HW_HAS_PCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -825,7 +825,7 @@ void __init board_prom_init(void) + /* read base address of boot chip select (0) + * 6328/6362 do not have MPI but boot from a fixed address + */ +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { + val = 0x18000000; + } else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -133,6 +133,8 @@ static void enetsw_set(struct clk *clk, + CKCTL_6368_SWPKT_USB_EN | + CKCTL_6368_SWPKT_SAR_EN, + enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable); + else + return; + +@@ -177,6 +179,8 @@ static void usbh_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); + else + return; + +@@ -199,6 +203,8 @@ static void usbd_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBD_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_USBD_EN, enable); + else + return; + +@@ -225,9 +231,13 @@ static void spi_set(struct clk *clk, int + mask = CKCTL_6358_SPI_EN; + else if (BCMCPU_IS_6362()) + mask = CKCTL_6362_SPI_EN; +- else +- /* BCMCPU_IS_6368 */ ++ else if (BCMCPU_IS_6368()) + mask = CKCTL_6368_SPI_EN; ++ else if (BCMCPU_IS_63268()) ++ mask = CKCTL_63268_SPI_EN; ++ else ++ return; ++ + bcm_hwclock_set(mask, enable); + } + +@@ -246,6 +256,8 @@ static void hsspi_set(struct clk *clk, i + mask = CKCTL_6328_HSSPI_EN; + else if (BCMCPU_IS_6362()) + mask = CKCTL_6362_HSSPI_EN; ++ else if (BCMCPU_IS_63268()) ++ mask = CKCTL_63268_HSSPI_EN; + else + return; + +@@ -307,6 +319,8 @@ static void pcie_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable); + else if (BCMCPU_IS_6362()) + bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable); + } + + static struct clk clk_pcie = { +@@ -386,9 +400,11 @@ struct clk *clk_get(struct device *dev, + return &clk_periph; + if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm")) + return &clk_pcm; +- if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec")) ++ if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) && ++ !strcmp(id, "ipsec")) + return &clk_ipsec; +- if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie")) ++ if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) && ++ !strcmp(id, "pcie")) + return &clk_pcie; + return ERR_PTR(-ENOENT); + } +@@ -411,6 +427,7 @@ static int __init bcm63xx_clk_init(void) + clk_hsspi.rate = HSSPI_PLL_HZ_6328; + break; + case BCM6362_CPU_ID: ++ case BCM63268_CPU_ID: + clk_hsspi.rate = HSSPI_PLL_HZ_6362; + break; + } +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = { + + }; + ++static const unsigned long bcm63268_regs_base[] = { ++ __GEN_CPU_REGS_TABLE(63268) ++}; ++ ++static const int bcm63268_irqs[] = { ++ __GEN_CPU_IRQ_TABLE(63268) ++ ++}; ++ + u32 bcm63xx_get_cpu_variant(void) + { + return bcm63xx_cpu_variant; +@@ -251,6 +260,27 @@ static unsigned int detect_cpu_clock(voi + + return (((64 * 1000000) / p1) * p2 * ndiv) / m1; + } ++ case BCM63268_CPU_ID: ++ { ++ unsigned int tmp, mips_pll_fcvo; ++ ++ tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG); ++ mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >> ++ STRAPBUS_63268_FCVO_SHIFT; ++ switch (mips_pll_fcvo) { ++ case 0x3: ++ case 0xe: ++ return 320000000; ++ case 0xa: ++ return 333000000; ++ case 0x2: ++ case 0xb: ++ case 0xf: ++ return 400000000; ++ default: ++ return 0; ++ } ++ } + + default: + BUG(); +@@ -265,7 +295,7 @@ static unsigned int detect_memory_size(v + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; + u32 val; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) + return bcm_ddr_readl(DDR_CSEND_REG) << 24; + + if (BCMCPU_IS_6345()) { +@@ -304,6 +334,7 @@ void __init bcm63xx_cpu_init(void) + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int cpu = smp_processor_id(); + u32 chipid_reg; ++ bool long_chipid = false; + u8 __maybe_unused varid = 0; + + /* soc registers location depends on cpu type */ +@@ -325,6 +356,9 @@ void __init bcm63xx_cpu_init(void) + case 0x10: + chipid_reg = BCM_6345_PERF_BASE; + break; ++ case 0x80: ++ long_chipid = true; ++ /* fall-through */ + default: + chipid_reg = BCM_6368_PERF_BASE; + break; +@@ -332,6 +366,7 @@ void __init bcm63xx_cpu_init(void) + break; + } + ++ + /* + * really early to panic, but delaying panic would not help since we + * will never get any working console +@@ -341,10 +376,17 @@ void __init bcm63xx_cpu_init(void) + + /* read out CPU type */ + tmp = bcm_readl(chipid_reg); +- bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; +- bcm63xx_cpu_variant = bcm63xx_cpu_id; ++ ++ if (long_chipid) { ++ bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK; ++ bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT; ++ } else { ++ bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; ++ varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; ++ } ++ + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; +- varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; ++ bcm63xx_cpu_variant = bcm63xx_cpu_id; + + switch (bcm63xx_cpu_id) { + case BCM3368_CPU_ID: +@@ -399,6 +441,15 @@ void __init bcm63xx_cpu_init(void) + /* BCM6369 is a BCM6368 without xDSL, so treat it the same */ + bcm63xx_cpu_id = BCM6368_CPU_ID; + break; ++ case BCM63168_CPU_ID: ++ case BCM63169_CPU_ID: ++ case BCM63268_CPU_ID: ++ case BCM63269_CPU_ID: ++ bcm63xx_regs_base = bcm63268_regs_base; ++ bcm63xx_irqs = bcm63268_irqs; ++ ++ bcm63xx_cpu_id = BCM63268_CPU_ID; ++ break; + default: + panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); + break; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -94,6 +94,12 @@ static int __init bcm63xx_detect_flash_t + case STRAPBUS_6368_BOOT_SEL_PARALLEL: + return BCM63XX_FLASH_TYPE_PARALLEL; + } ++ case BCM63268_CPU_ID: ++ val = bcm_misc_readl(MISC_STRAPBUS_63268_REG); ++ if (val & STRAPBUS_63268_BOOT_SEL_SERIAL) ++ return BCM63XX_FLASH_TYPE_SERIAL; ++ else ++ return BCM63XX_FLASH_TYPE_NAND; + default: + return -EINVAL; + } +--- a/arch/mips/bcm63xx/dev-spi.c ++++ b/arch/mips/bcm63xx/dev-spi.c +@@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init + if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) + bcm63xx_regs_spi = bcm6348_regs_spi; + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || +- BCMCPU_IS_6362() || BCMCPU_IS_6368()) ++ BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) + bcm63xx_regs_spi = bcm6358_regs_spi; + } + +@@ -85,7 +85,7 @@ int __init bcm63xx_spi_register(void) + } + + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || +- BCMCPU_IS_6368()) { ++ BCMCPU_IS_6368() || BCMCPU_IS_63268()) { + spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; + spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; + spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT; +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -158,6 +158,7 @@ static void __internal_irq_unmask_##widt + + BUILD_IPIC_INTERNAL(32); + BUILD_IPIC_INTERNAL(64); ++BUILD_IPIC_INTERNAL(128); + + asmlinkage void plat_irq_dispatch(void) + { +@@ -343,6 +344,7 @@ static int bcm63xx_external_irq_set_type + case BCM6358_CPU_ID: + case BCM6362_CPU_ID: + case BCM6368_CPU_ID: ++ case BCM63268_CPU_ID: + if (levelsense) + reg |= EXTIRQ_CFG_LEVELSENSE(irq); + else +@@ -515,6 +517,18 @@ static void bcm63xx_init_irq(void) + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; + ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; + break; ++ case BCM63268_CPU_ID: ++ irq_stat_addr[0] += PERF_IRQSTAT_63268_REG(0); ++ irq_mask_addr[0] += PERF_IRQMASK_63268_REG(0); ++ irq_stat_addr[1] += PERF_IRQSTAT_63268_REG(1); ++ irq_mask_addr[1] += PERF_IRQMASK_63268_REG(1); ++ irq_bits = 128; ++ ext_irq_count = 4; ++ is_ext_irq_cascaded = 1; ++ ext_irq_start = BCM_63268_EXT_IRQ0 - IRQ_INTERNAL_BASE; ++ ext_irq_end = BCM_63268_EXT_IRQ3 - IRQ_INTERNAL_BASE; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_63268; ++ break; + default: + BUG(); + } +@@ -523,10 +537,14 @@ static void bcm63xx_init_irq(void) + dispatch_internal = __dispatch_internal_32; + internal_irq_mask = __internal_irq_mask_32; + internal_irq_unmask = __internal_irq_unmask_32; +- } else { ++ } else if (irq_bits == 64) { + dispatch_internal = __dispatch_internal_64; + internal_irq_mask = __internal_irq_mask_64; + internal_irq_unmask = __internal_irq_unmask_64; ++ } else { ++ dispatch_internal = __dispatch_internal_128; ++ internal_irq_mask = __internal_irq_mask_128; ++ internal_irq_unmask = __internal_irq_unmask_128; + } + } + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -125,6 +125,20 @@ + #define BCM6368_RESET_PCIE 0 + #define BCM6368_RESET_PCIE_EXT 0 + ++#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK ++#define BCM63268_RESET_ENET 0 ++#define BCM63268_RESET_USBH SOFTRESET_63268_USBH_MASK ++#define BCM63268_RESET_USBD SOFTRESET_63268_USBS_MASK ++#define BCM63268_RESET_DSL 0 ++#define BCM63268_RESET_SAR SOFTRESET_63268_SAR_MASK ++#define BCM63268_RESET_EPHY 0 ++#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK ++#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK ++#define BCM63268_RESET_MPI 0 ++#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ ++ SOFTRESET_63268_PCIE_CORE_MASK) ++#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK ++ + /* + * core reset bits + */ +@@ -156,6 +170,10 @@ static const u32 bcm6368_reset_bits[] = + __GEN_RESET_BITS_TABLE(6368) + }; + ++static const u32 bcm63268_reset_bits[] = { ++ __GEN_RESET_BITS_TABLE(63268) ++}; ++ + const u32 *bcm63xx_reset_bits; + static int reset_reg; + +@@ -182,6 +200,9 @@ static int __init bcm63xx_reset_bits_ini + } else if (BCMCPU_IS_6368()) { + reset_reg = PERF_SOFTRESET_6368_REG; + bcm63xx_reset_bits = bcm6368_reset_bits; ++ } else if (BCMCPU_IS_63268()) { ++ reset_reg = PERF_SOFTRESET_63268_REG; ++ bcm63xx_reset_bits = bcm63268_reset_bits; + } + + return 0; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -21,6 +21,10 @@ + #define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 + #define BCM6369_CPU_ID 0x6369 ++#define BCM63168_CPU_ID 0x63168 ++#define BCM63169_CPU_ID 0x63169 ++#define BCM63268_CPU_ID 0x63268 ++#define BCM63269_CPU_ID 0x63269 + + void __init bcm63xx_cpu_init(void); + u32 bcm63xx_get_cpu_variant(void); +@@ -61,6 +65,10 @@ static inline u32 __pure __bcm63xx_get_c + #ifdef CONFIG_BCM63XX_CPU_6368 + case BCM6368_CPU_ID: + #endif ++ ++#ifdef CONFIG_BCM63XX_CPU_63268 ++ case BCM63268_CPU_ID: ++#endif + break; + default: + unreachable(); +@@ -86,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu + #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) + #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) + #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) ++#define BCMCPU_IS_63268() (bcm63xx_get_cpu_id() == BCM63268_CPU_ID) + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) +@@ -109,6 +118,14 @@ static inline u32 __pure bcm63xx_get_cpu + (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) + #define BCMCPU_VARIANT_IS_6369() \ + (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID) ++#define BCMCPU_VARIANT_IS_63168() \ ++ (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID) ++#define BCMCPU_VARIANT_IS_63169() \ ++ (bcm63xx_get_cpu_variant() == BCM63169_CPU_ID) ++#define BCMCPU_VARIANT_IS_63268() \ ++ (bcm63xx_get_cpu_variant() == BCM63268_CPU_ID) ++#define BCMCPU_VARIANT_IS_63269() \ ++ (bcm63xx_get_cpu_variant() == BCM63269_CPU_ID) + + /* + * While registers sets are (mostly) the same across 63xx CPU, base +@@ -573,6 +590,52 @@ enum bcm63xx_regs_set { + #define BCM_6368_RNG_BASE (0xb0004180) + #define BCM_6368_MISC_BASE (0xdeadbeef) + ++/* ++ * 63268 register sets base address ++ */ ++#define BCM_63268_DSL_LMEM_BASE (0xdeadbeef) ++#define BCM_63268_PERF_BASE (0xb0000000) ++#define BCM_63268_TIMER_BASE (0xb0000080) ++#define BCM_63268_WDT_BASE (0xb000009c) ++#define BCM_63268_UART0_BASE (0xb0000180) ++#define BCM_63268_UART1_BASE (0xb00001a0) ++#define BCM_63268_GPIO_BASE (0xb00000c0) ++#define BCM_63268_SPI_BASE (0xb0000800) ++#define BCM_63268_HSSPI_BASE (0xb0001000) ++#define BCM_63268_UDC0_BASE (0xdeadbeef) ++#define BCM_63268_USBDMA_BASE (0xb000c800) ++#define BCM_63268_OHCI0_BASE (0xb0002600) ++#define BCM_63268_OHCI_PRIV_BASE (0xdeadbeef) ++#define BCM_63268_USBH_PRIV_BASE (0xb0002700) ++#define BCM_63268_USBD_BASE (0xb0002400) ++#define BCM_63268_MPI_BASE (0xdeadbeef) ++#define BCM_63268_PCMCIA_BASE (0xdeadbeef) ++#define BCM_63268_PCIE_BASE (0xb06e0000) ++#define BCM_63268_SDRAM_REGS_BASE (0xdeadbeef) ++#define BCM_63268_DSL_BASE (0xdeadbeef) ++#define BCM_63268_UBUS_BASE (0xdeadbeef) ++#define BCM_63268_ENET0_BASE (0xdeadbeef) ++#define BCM_63268_ENET1_BASE (0xdeadbeef) ++#define BCM_63268_ENETDMA_BASE (0xb000d800) ++#define BCM_63268_ENETDMAC_BASE (0xb000da00) ++#define BCM_63268_ENETDMAS_BASE (0xb000dc00) ++#define BCM_63268_ENETSW_BASE (0xb0700000) ++#define BCM_63268_EHCI0_BASE (0xb0002500) ++#define BCM_63268_SDRAM_BASE (0xdeadbeef) ++#define BCM_63268_MEMC_BASE (0xdeadbeef) ++#define BCM_63268_DDR_BASE (0xb0003000) ++#define BCM_63268_M2M_BASE (0xdeadbeef) ++#define BCM_63268_ATM_BASE (0xdeadbeef) ++#define BCM_63268_XTM_BASE (0xb0007000) ++#define BCM_63268_XTMDMA_BASE (0xb000b800) ++#define BCM_63268_XTMDMAC_BASE (0xdeadbeef) ++#define BCM_63268_XTMDMAS_BASE (0xdeadbeef) ++#define BCM_63268_PCM_BASE (0xb000b000) ++#define BCM_63268_PCMDMA_BASE (0xb000b800) ++#define BCM_63268_PCMDMAC_BASE (0xdeadbeef) ++#define BCM_63268_PCMDMAS_BASE (0xdeadbeef) ++#define BCM_63268_RNG_BASE (0xdeadbeef) ++#define BCM_63268_MISC_BASE (0xb0001800) + + extern const unsigned long *bcm63xx_regs_base; + +@@ -1084,6 +1147,73 @@ enum bcm63xx_irq { + #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) + #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) + ++/* ++ * 63268 irqs ++ */ ++#define BCM_63268_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) ++#define BCM_63268_VERY_HIGH_IRQ_BASE (BCM_63268_HIGH_IRQ_BASE + 32) ++ ++#define BCM_63268_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) ++#define BCM_63268_SPI_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 16) ++#define BCM_63268_UART0_IRQ (IRQ_INTERNAL_BASE + 5) ++#define BCM_63268_UART1_IRQ (BCM_63268_HIGH_IRQ_BASE + 2) ++#define BCM_63268_DSL_IRQ (IRQ_INTERNAL_BASE + 23) ++#define BCM_63268_UDC0_IRQ 0 ++#define BCM_63268_ENET0_IRQ 0 ++#define BCM_63268_ENET1_IRQ 0 ++#define BCM_63268_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 13) ++#define BCM_63268_HSSPI_IRQ (IRQ_INTERNAL_BASE + 6) ++#define BCM_63268_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_63268_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) ++#define BCM_63268_USBD_IRQ (IRQ_INTERNAL_BASE + 11) ++#define BCM_63268_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 19) ++#define BCM_63268_USBD_TXDMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 4) ++#define BCM_63268_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 20) ++#define BCM_63268_USBD_TXDMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 5) ++#define BCM_63268_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 21) ++#define BCM_63268_USBD_TXDMA2_IRQ (BCM_63268_HIGH_IRQ_BASE + 6) ++#define BCM_63268_PCMCIA_IRQ 0 ++#define BCM_63268_ENET0_RXDMA_IRQ 0 ++#define BCM_63268_ENET0_TXDMA_IRQ 0 ++#define BCM_63268_ENET1_RXDMA_IRQ 0 ++#define BCM_63268_ENET1_TXDMA_IRQ 0 ++#define BCM_63268_PCI_IRQ (BCM_63268_HIGH_IRQ_BASE + 8) ++#define BCM_63268_ATM_IRQ 0 ++#define BCM_63268_ENETSW_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 1) ++#define BCM_63268_ENETSW_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 2) ++#define BCM_63268_ENETSW_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 3) ++#define BCM_63268_ENETSW_RXDMA3_IRQ (IRQ_INTERNAL_BASE + 4) ++#define BCM_63268_ENETSW_TXDMA0_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 0) ++#define BCM_63268_ENETSW_TXDMA1_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 1) ++#define BCM_63268_ENETSW_TXDMA2_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 2) ++#define BCM_63268_ENETSW_TXDMA3_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 3) ++#define BCM_63268_XTM_IRQ (BCM_63268_HIGH_IRQ_BASE + 17) ++#define BCM_63268_XTM_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) ++ ++#define BCM_63268_RING_OSC_IRQ (BCM_63268_HIGH_IRQ_BASE + 20) ++#define BCM_63268_WLAN_GPIO_IRQ (BCM_63268_HIGH_IRQ_BASE + 3) ++#define BCM_63268_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) ++#define BCM_63268_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) ++#define BCM_63268_NAND_IRQ (BCM_63268_HIGH_IRQ_BASE + 18) ++#define BCM_63268_PCM_IRQ (IRQ_INTERNAL_BASE + 13) ++#define BCM_63268_DG_IRQ (IRQ_INTERNAL_BASE + 15) ++#define BCM_63268_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) ++#define BCM_63268_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) ++#define BCM_63268_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) ++#define BCM_63268_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) ++#define BCM_63268_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 22) ++#define BCM_63268_IPSEC_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 7) ++#define BCM_63268_FAP0_IRQ (IRQ_INTERNAL_BASE + 24) ++#define BCM_63268_FAP1_IRQ (IRQ_INTERNAL_BASE + 25) ++#define BCM_63268_PCM_DMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 10) ++#define BCM_63268_PCM_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 11) ++#define BCM_63268_DECT0_IRQ (BCM_63268_HIGH_IRQ_BASE + 0) ++#define BCM_63268_DECT1_IRQ (BCM_63268_HIGH_IRQ_BASE + 1) ++#define BCM_63268_EXT_IRQ0 (BCM_63268_HIGH_IRQ_BASE + 12) ++#define BCM_63268_EXT_IRQ1 (BCM_63268_HIGH_IRQ_BASE + 13) ++#define BCM_63268_EXT_IRQ2 (BCM_63268_HIGH_IRQ_BASE + 14) ++#define BCM_63268_EXT_IRQ3 (BCM_63268_HIGH_IRQ_BASE + 15) ++ + extern const int *bcm63xx_irqs; + + #define __GEN_CPU_IRQ_TABLE(__cpu) \ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +@@ -22,6 +22,8 @@ static inline unsigned long bcm63xx_gpio + return 48; + case BCM6368_CPU_ID: + return 38; ++ case BCM63268_CPU_ID: ++ return 52; + case BCM6348_CPU_ID: + default: + return 37; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -9,6 +9,8 @@ + #define PERF_REV_REG 0x0 + #define REV_CHIPID_SHIFT 16 + #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) ++#define REV_LONG_CHIPID_SHIFT 12 ++#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) + #define REV_VARID_SHIFT 8 + #define REV_VARID_MASK (0xf << REV_VARID_SHIFT) + #define REV_REVID_SHIFT 0 +@@ -211,6 +213,52 @@ + CKCTL_6368_NAND_EN | \ + CKCTL_6368_IPSEC_EN) + ++#define CKCTL_63268_DISABLE_GLESS (1 << 0) ++#define CKCTL_63268_VDSL_QPROC_EN (1 << 1) ++#define CKCTL_63268_VDSL_AFE_EN (1 << 2) ++#define CKCTL_63268_VDSL_EN (1 << 3) ++#define CKCTL_63268_MIPS_EN (1 << 4) ++#define CKCTL_63268_WLAN_OCP_EN (1 << 5) ++#define CKCTL_63268_DECT_EN (1 << 6) ++#define CKCTL_63268_FAP0_EN (1 << 7) ++#define CKCTL_63268_FAP1_EN (1 << 8) ++#define CKCTL_63268_SAR_EN (1 << 9) ++#define CKCTL_63268_ROBOSW_EN (1 << 10) ++#define CKCTL_63268_PCM_EN (1 << 11) ++#define CKCTL_63268_USBD_EN (1 << 12) ++#define CKCTL_63268_USBH_EN (1 << 13) ++#define CKCTL_63268_IPSEC_EN (1 << 14) ++#define CKCTL_63268_SPI_EN (1 << 15) ++#define CKCTL_63268_HSSPI_EN (1 << 16) ++#define CKCTL_63268_PCIE_EN (1 << 17) ++#define CKCTL_63268_PHYMIPS_EN (1 << 18) ++#define CKCTL_63268_GMAC_EN (1 << 19) ++#define CKCTL_63268_NAND_EN (1 << 20) ++#define CKCTL_63268_TBUS_EN (1 << 27) ++#define CKCTL_63268_ROBOSW250_EN (1 << 31) ++ ++#define CKCTL_63268_ALL_SAFE_EN (CKCTL_63268_VDSL_QPROC_EN | \ ++ CKCTL_63268_VDSL_AFE_EN | \ ++ CKCTL_63268_VDSL_EN | \ ++ CKCTL_63268_WLAN_OCP_EN | \ ++ CKCTL_63268_DECT_EN | \ ++ CKCTL_63268_FAP0_EN | \ ++ CKCTL_63268_FAP1_EN | \ ++ CKCTL_63268_SAR_EN | \ ++ CKCTL_63268_ROBOSW_EN | \ ++ CKCTL_63268_PCM_EN | \ ++ CKCTL_63268_USBD_EN | \ ++ CKCTL_63268_USBH_EN | \ ++ CKCTL_63268_IPSEC_EN | \ ++ CKCTL_63268_SPI_EN | \ ++ CKCTL_63268_HSSPI_EN | \ ++ CKCTL_63268_PCIE_EN | \ ++ CKCTL_63268_PHYMIPS_EN | \ ++ CKCTL_63268_GMAC_EN | \ ++ CKCTL_63268_NAND_EN | \ ++ CKCTL_63268_TBUS_EN | \ ++ CKCTL_63268_ROBOSW250_EN) ++ + /* System PLL Control register */ + #define PERF_SYS_PLL_CTL_REG 0x8 + #define SYS_PLL_SOFT_RESET 0x1 +@@ -224,6 +272,7 @@ + #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c) + #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10) + #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10) ++#define PERF_IRQMASK_63268_REG(x) (0x20 + (x) * 0x20) + + /* Interrupt Status register */ + #define PERF_IRQSTAT_3368_REG 0x10 +@@ -234,6 +283,7 @@ + #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c) + #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10) + #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10) ++#define PERF_IRQSTAT_63268_REG(x) (0x30 + (x) * 0x20) + + /* External Interrupt Configuration register */ + #define PERF_EXTIRQ_CFG_REG_3368 0x14 +@@ -244,6 +294,7 @@ + #define PERF_EXTIRQ_CFG_REG_6358 0x14 + #define PERF_EXTIRQ_CFG_REG_6362 0x18 + #define PERF_EXTIRQ_CFG_REG_6368 0x18 ++#define PERF_EXTIRQ_CFG_REG_63268 0x18 + + #define PERF_EXTIRQ_CFG_REG2_6368 0x1c + +@@ -273,6 +324,7 @@ + #define PERF_SOFTRESET_6358_REG 0x34 + #define PERF_SOFTRESET_6362_REG 0x10 + #define PERF_SOFTRESET_6368_REG 0x10 ++#define PERF_SOFTRESET_63268_REG 0x10 + + #define SOFTRESET_3368_SPI_MASK (1 << 0) + #define SOFTRESET_3368_ENET_MASK (1 << 2) +@@ -366,6 +418,26 @@ + #define SOFTRESET_6368_USBH_MASK (1 << 12) + #define SOFTRESET_6368_PCM_MASK (1 << 13) + ++#define SOFTRESET_63268_SPI_MASK (1 << 0) ++#define SOFTRESET_63268_IPSEC_MASK (1 << 1) ++#define SOFTRESET_63268_EPHY_MASK (1 << 2) ++#define SOFTRESET_63268_SAR_MASK (1 << 3) ++#define SOFTRESET_63268_ENETSW_MASK (1 << 4) ++#define SOFTRESET_63268_USBS_MASK (1 << 5) ++#define SOFTRESET_63268_USBH_MASK (1 << 6) ++#define SOFTRESET_63268_PCM_MASK (1 << 7) ++#define SOFTRESET_63268_PCIE_CORE_MASK (1 << 8) ++#define SOFTRESET_63268_PCIE_MASK (1 << 9) ++#define SOFTRESET_63268_PCIE_EXT_MASK (1 << 10) ++#define SOFTRESET_63268_WLAN_SHIM_MASK (1 << 11) ++#define SOFTRESET_63268_DDR_PHY_MASK (1 << 12) ++#define SOFTRESET_63268_FAP0_MASK (1 << 13) ++#define SOFTRESET_63268_WLAN_UBUS_MASK (1 << 14) ++#define SOFTRESET_63268_DECT_MASK (1 << 15) ++#define SOFTRESET_63268_FAP1_MASK (1 << 16) ++#define SOFTRESET_63268_PCIE_HARD_MASK (1 << 17) ++#define SOFTRESET_63268_GPHY_MASK (1 << 18) ++ + /* MIPS PLL control register */ + #define PERF_MIPSPLLCTL_REG 0x34 + #define MIPSPLLCTL_N1_SHIFT 20 +@@ -1499,6 +1571,13 @@ + #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15) + #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15) + ++#define MISC_STRAPBUS_63268_REG 0x14 ++#define STRAPBUS_63268_HSSPI_CLK_FAST (1 << 9) ++#define STRAPBUS_63268_BOOT_SEL_SERIAL (1 << 11) ++#define STRAPBUS_63268_BOOT_SEL_NAND (0 << 11) ++#define STRAPBUS_63268_FCVO_SHIFT 21 ++#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) ++ + #define MISC_STRAPBUS_6328_REG 0x240 + #define STRAPBUS_6328_FCVO_SHIFT 7 + #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) +--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h ++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h +@@ -25,6 +25,7 @@ static inline int is_bcm63xx_internal_re + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: + case BCM6368_CPU_ID: ++ case BCM63268_CPU_ID: + if (offset >= 0xb0000000 && offset < 0xb1000000) + return 1; + break; +--- a/arch/mips/bcm63xx/dev-hsspi.c ++++ b/arch/mips/bcm63xx/dev-hsspi.c +@@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs + + int __init bcm63xx_hsspi_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362()) ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); +--- a/arch/mips/bcm63xx/dev-enet.c ++++ b/arch/mips/bcm63xx/dev-enet.c +@@ -176,7 +176,8 @@ static int __init register_shared(void) + else + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || ++ BCMCPU_IS_63268()) + chan_count = 32; + else if (BCMCPU_IS_6345()) + chan_count = 8; +@@ -276,7 +277,8 @@ bcm63xx_enetsw_register(const struct bcm + { + int ret; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && ++ !BCMCPU_IS_63268()) + return -ENODEV; + + ret = register_shared(); +@@ -295,8 +297,11 @@ bcm63xx_enetsw_register(const struct bcm + + if (BCMCPU_IS_6328()) + enetsw_pd.num_ports = ENETSW_PORTS_6328; +- else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) ++ else if (BCMCPU_IS_6362() || BCMCPU_IS_6368() || ++ BCMCPU_VARIANT_IS_63168() || BCMCPU_VARIANT_IS_63169()) + enetsw_pd.num_ports = ENETSW_PORTS_6368; ++ else if (BCMCPU_VARIANT_IS_63268() || BCMCPU_VARIANT_IS_63269()) ++ enetsw_pd.num_ports = ENETSW_PORTS_63268; + + enetsw_pd.dma_has_sram = true; + enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h +@@ -62,6 +62,7 @@ struct bcm63xx_enet_platform_data { + #define ENETSW_MAX_PORT 8 + #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */ + #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */ ++#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */ + + #define ENETSW_RGMII_PORT0 4 + diff --git a/target/linux/brcm63xx/patches-3.13/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.13/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch new file mode 100644 index 0000000000..4e8a090791 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch @@ -0,0 +1,55 @@ +From 5c290c81dbdb4433600593fe80c88eb4af86e791 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 8 Dec 2013 03:22:40 +0100 +Subject: [PATCH 50/53] MIPS: BCM63XX: add pcie support for BCM63268 + +--- + arch/mips/bcm63xx/reset.c | 3 ++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 5 +++++ + arch/mips/pci/pci-bcm63xx.c | 4 ++++ + 3 files changed, 11 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -136,7 +136,8 @@ + #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK + #define BCM63268_RESET_MPI 0 + #define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ +- SOFTRESET_63268_PCIE_CORE_MASK) ++ SOFTRESET_63268_PCIE_CORE_MASK | \ ++ SOFTRESET_63268_PCIE_HARD_MASK) + #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK + + /* +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -45,6 +45,11 @@ + #define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ + BCM_PCIE_MEM_SIZE_6328 - 1) + ++#define BCM_PCIE_MEM_BASE_PA_63268 0x11000000 ++#define BCM_PCIE_MEM_SIZE_63268 (15 * 1024 * 1024) ++#define BCM_PCIE_MEM_END_PA_63268 (BCM_PCIE_MEM_BASE_PA_63268 + \ ++ BCM_PCIE_MEM_SIZE_63268 - 1) ++ + /* + * Internal registers are accessed through KSEG3 + */ +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -337,11 +337,15 @@ static int __init bcm63xx_pci_init(void) + if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { + bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; + bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; ++ } else if (BCMCPU_IS_63268()) { ++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_63268; ++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_63268; + } + + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: ++ case BCM63268_CPU_ID: + return bcm63xx_register_pcie(); + case BCM3368_CPU_ID: + case BCM6348_CPU_ID: diff --git a/target/linux/brcm63xx/patches-3.13/341-MIPS-BCM63XX-add-support-for-BCM6318.patch b/target/linux/brcm63xx/patches-3.13/341-MIPS-BCM63XX-add-support-for-BCM6318.patch new file mode 100644 index 0000000000..8383ef718f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/341-MIPS-BCM63XX-add-support-for-BCM6318.patch @@ -0,0 +1,671 @@ +From 60c29522a8c77d96145d965589c56befda7d4c3d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 8 Dec 2013 01:24:09 +0100 +Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318 + +--- + arch/mips/bcm63xx/Kconfig | 5 + + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/clk.c | 8 +- + arch/mips/bcm63xx/cpu.c | 53 +++++++++++ + arch/mips/bcm63xx/dev-flash.c | 3 + + arch/mips/bcm63xx/dev-spi.c | 2 +- + arch/mips/bcm63xx/irq.c | 10 ++ + arch/mips/bcm63xx/prom.c | 2 +- + arch/mips/bcm63xx/reset.c | 24 +++++ + arch/mips/bcm63xx/setup.c | 5 +- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 107 ++++++++++++++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 75 ++++++++++++++- + arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + + 13 files changed, 291 insertions(+), 6 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -18,6 +18,11 @@ config BCM63XX_EHCI + select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD + select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD + ++config BCM63XX_CPU_6318 ++ bool "support 6318 CPU" ++ select SYS_HAS_CPU_BMIPS32_3300 ++ select HW_HAS_PCI ++ + config BCM63XX_CPU_6328 + bool "support 6328 CPU" + select SYS_HAS_CPU_BMIPS4350 +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -825,7 +825,7 @@ void __init board_prom_init(void) + /* read base address of boot chip select (0) + * 6328/6362 do not have MPI but boot from a fixed address + */ +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { + val = 0x18000000; + } else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -252,7 +252,9 @@ static void hsspi_set(struct clk *clk, i + { + u32 mask; + +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) ++ mask = CKCTL_6318_HSSPI_EN; ++ else if (BCMCPU_IS_6328()) + mask = CKCTL_6328_HSSPI_EN; + else if (BCMCPU_IS_6362()) + mask = CKCTL_6362_HSSPI_EN; +@@ -417,12 +419,16 @@ void clk_put(struct clk *clk) + + EXPORT_SYMBOL(clk_put); + ++#define HSSPI_PLL_HZ_6318 250000000 + #define HSSPI_PLL_HZ_6328 133333333 + #define HSSPI_PLL_HZ_6362 400000000 + + static int __init bcm63xx_clk_init(void) + { + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: ++ clk_hsspi.rate = HSSPI_PLL_HZ_6318; ++ break; + case BCM6328_CPU_ID: + clk_hsspi.rate = HSSPI_PLL_HZ_6328; + break; +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -41,6 +41,14 @@ static const int bcm3368_irqs[] = { + __GEN_CPU_IRQ_TABLE(3368) + }; + ++static const unsigned long bcm6318_regs_base[] = { ++ __GEN_CPU_REGS_TABLE(6318) ++}; ++ ++static const int bcm6318_irqs[] = { ++ __GEN_CPU_IRQ_TABLE(6318) ++}; ++ + static const unsigned long bcm6328_regs_base[] = { + __GEN_CPU_REGS_TABLE(6328) + }; +@@ -134,12 +142,38 @@ unsigned int bcm63xx_get_memory_size(voi + return bcm63xx_memory_size; + } + ++#define STRAP_OVERRIDE_BUS_REG 0x0 ++#define OVERRIDE_BUS_MIPS_FREQ_SHIFT 23 ++#define OVERRIDE_BUS_MIPS_FREQ_MASK (0x3 << OVERRIDE_BUS_MIPS_FREQ_SHIFT) ++ + static unsigned int detect_cpu_clock(void) + { + switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: + return 300000000; + ++ case BCM6318_CPU_ID: ++ { ++ unsigned int tmp, mips_pll_fcvo; ++ ++ tmp = bcm_readl(BCM_6318_STRAP_BASE + STRAP_OVERRIDE_BUS_REG); ++ ++ pr_info("strap_override_bus = %08x\n", tmp); ++ ++ mips_pll_fcvo = (tmp & OVERRIDE_BUS_MIPS_FREQ_MASK) ++ >> OVERRIDE_BUS_MIPS_FREQ_SHIFT; ++ ++ switch (mips_pll_fcvo) { ++ case 0: ++ return 166000000; ++ case 1: ++ return 400000000; ++ case 2: ++ return 250000000; ++ case 3: ++ return 333000000; ++ }; ++ } + case BCM6328_CPU_ID: + { + unsigned int tmp, mips_pll_fcvo; +@@ -295,6 +329,13 @@ static unsigned int detect_memory_size(v + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; + u32 val; + ++ if (BCMCPU_IS_6318()) { ++ val = bcm_sdram_readl(SDRAM_CFG_REG); ++ val = val & SDRAM_CFG_6318_SPACE_MASK; ++ val >>= SDRAM_CFG_6318_SPACE_SHIFT; ++ return 1 << (val + 20); ++ } ++ + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) + return bcm_ddr_readl(DDR_CSEND_REG) << 24; + +@@ -342,6 +383,12 @@ void __init bcm63xx_cpu_init(void) + + switch (c->cputype) { + case CPU_BMIPS3300: ++ if ((read_c0_prid() & 0xff) >= 0x33) { ++ /* BCM6318 */ ++ chipid_reg = BCM_6368_PERF_BASE; ++ break; ++ } ++ + if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT) + __cpu_name[cpu] = "Broadcom BCM6338"; + /* fall-through */ +@@ -389,6 +436,10 @@ void __init bcm63xx_cpu_init(void) + bcm63xx_cpu_variant = bcm63xx_cpu_id; + + switch (bcm63xx_cpu_id) { ++ case BCM6318_CPU_ID: ++ bcm63xx_regs_base = bcm6318_regs_base; ++ bcm63xx_irqs = bcm6318_irqs; ++ break; + case BCM3368_CPU_ID: + bcm63xx_regs_base = bcm3368_regs_base; + bcm63xx_irqs = bcm3368_irqs; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -60,6 +60,9 @@ static int __init bcm63xx_detect_flash_t + u32 val; + + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: ++ /* only support serial flash */ ++ return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6328_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); + if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) +--- a/arch/mips/bcm63xx/dev-spi.c ++++ b/arch/mips/bcm63xx/dev-spi.c +@@ -70,7 +70,7 @@ static struct platform_device bcm63xx_sp + + int __init bcm63xx_spi_register(void) + { +- if (BCMCPU_IS_6328() || BCMCPU_IS_6345()) ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI); +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -441,6 +441,16 @@ static void bcm63xx_init_irq(void) + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; + break; ++ case BCM6318_CPU_ID: ++ irq_stat_addr[0] += PERF_IRQSTAT_6318_REG; ++ irq_mask_addr[0] += PERF_IRQMASK_6318_REG; ++ irq_bits = 128; ++ ext_irq_count = 4; ++ is_ext_irq_cascaded = 1; ++ ext_irq_start = BCM_6318_EXT_IRQ0 - IRQ_INTERNAL_BASE; ++ ext_irq_end = BCM_6318_EXT_IRQ3 - IRQ_INTERNAL_BASE; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6318; ++ break; + case BCM6328_CPU_ID: + irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); + irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -72,7 +72,7 @@ void __init prom_init(void) + + if (reg & OTP_6328_REG3_TP1_DISABLED) + bmips_smp_enabled = 0; +- } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { ++ } else if (BCMCPU_IS_6318() || BCMCPU_IS_3368() || BCMCPU_IS_6358()) { + bmips_smp_enabled = 0; + } + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -43,6 +43,23 @@ + #define BCM3368_RESET_PCIE 0 + #define BCM3368_RESET_PCIE_EXT 0 + ++ ++#define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK ++#define BCM6318_RESET_ENET 0 ++#define BCM6318_RESET_USBH SOFTRESET_6318_USBH_MASK ++#define BCM6318_RESET_USBD SOFTRESET_6318_USBS_MASK ++#define BCM6318_RESET_DSL 0 ++#define BCM6318_RESET_SAR SOFTRESET_6318_SAR_MASK ++#define BCM6318_RESET_EPHY SOFTRESET_6318_EPHY_MASK ++#define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK ++#define BCM6318_RESET_PCM 0 ++#define BCM6318_RESET_MPI 0 ++#define BCM6318_RESET_PCIE \ ++ (SOFTRESET_6318_PCIE_MASK | \ ++ SOFTRESET_6318_PCIE_CORE_MASK | \ ++ SOFTRESET_6318_PCIE_HARD_MASK) ++#define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK ++ + #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK + #define BCM6328_RESET_ENET 0 + #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK +@@ -147,6 +164,10 @@ static const u32 bcm3368_reset_bits[] = + __GEN_RESET_BITS_TABLE(3368) + }; + ++static const u32 bcm6318_reset_bits[] = { ++ __GEN_RESET_BITS_TABLE(6318) ++}; ++ + static const u32 bcm6328_reset_bits[] = { + __GEN_RESET_BITS_TABLE(6328) + }; +@@ -183,6 +204,9 @@ static int __init bcm63xx_reset_bits_ini + if (BCMCPU_IS_3368()) { + reset_reg = PERF_SOFTRESET_6358_REG; + bcm63xx_reset_bits = bcm3368_reset_bits; ++ } else if (BCMCPU_IS_6318()) { ++ reset_reg = PERF_SOFTRESET_6318_REG; ++ bcm63xx_reset_bits = bcm6318_reset_bits; + } else if (BCMCPU_IS_6328()) { + reset_reg = PERF_SOFTRESET_6328_REG; + bcm63xx_reset_bits = bcm6328_reset_bits; +--- a/arch/mips/bcm63xx/setup.c ++++ b/arch/mips/bcm63xx/setup.c +@@ -71,6 +71,9 @@ void bcm63xx_machine_reboot(void) + case BCM3368_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368; + break; ++ case BCM6318_CPU_ID: ++ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6318; ++ break; + case BCM6328_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; + break; +@@ -110,7 +113,7 @@ void bcm63xx_machine_reboot(void) + bcm6348_a1_reboot(); + + printk(KERN_INFO "triggering watchdog soft-reset...\n"); +- if (BCMCPU_IS_6328()) { ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) { + bcm_wdt_writel(1, WDT_SOFTRESET_REG); + } else { + reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -10,6 +10,7 @@ + * arm mach-types) + */ + #define BCM3368_CPU_ID 0x3368 ++#define BCM6318_CPU_ID 0x6318 + #define BCM6328_CPU_ID 0x6328 + #define BCM63281_CPU_ID 0x63281 + #define BCM63283_CPU_ID 0x63283 +@@ -38,6 +39,10 @@ static inline u32 __pure __bcm63xx_get_c + case BCM3368_CPU_ID: + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6318 ++ case BCM6318_CPU_ID: ++#endif ++ + #ifdef CONFIG_BCM63XX_CPU_6328 + case BCM6328_CPU_ID: + #endif +@@ -87,6 +92,7 @@ static inline u32 __pure bcm63xx_get_cpu + } + + #define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) ++#define BCMCPU_IS_6318() (bcm63xx_get_cpu_id() == BCM6318_CPU_ID) + #define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) + #define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) + #define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) +@@ -98,6 +104,8 @@ static inline u32 __pure bcm63xx_get_cpu + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) ++#define BCMCPU_VARIANT_IS_6318() \ ++ (bcm63xx_get_cpu_variant() == BCM6318_CPU_ID) + #define BCMCPU_VARIANT_IS_63281() \ + (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID) + #define BCMCPU_VARIANT_IS_63283() \ +@@ -252,6 +260,56 @@ enum bcm63xx_regs_set { + #define BCM_3368_MISC_BASE (0xdeadbeef) + + /* ++ * 6318 register sets base address ++ */ ++#define BCM_6318_DSL_LMEM_BASE (0xdeadbeef) ++#define BCM_6318_PERF_BASE (0xb0000000) ++#define BCM_6318_TIMER_BASE (0xb0000040) ++#define BCM_6318_WDT_BASE (0xb0000068) ++#define BCM_6318_UART0_BASE (0xb0000100) ++#define BCM_6318_UART1_BASE (0xdeadbeef) ++#define BCM_6318_GPIO_BASE (0xb0000080) ++#define BCM_6318_SPI_BASE (0xdeadbeef) ++#define BCM_6318_HSSPI_BASE (0xb0003000) ++#define BCM_6318_UDC0_BASE (0xdeadbeef) ++#define BCM_6318_USBDMA_BASE (0xb0006800) ++#define BCM_6318_OHCI0_BASE (0xb0005100) ++#define BCM_6318_OHCI_PRIV_BASE (0xdeadbeef) ++#define BCM_6318_USBH_PRIV_BASE (0xb0005200) ++#define BCM_6318_USBD_BASE (0xb0006000) ++#define BCM_6318_MPI_BASE (0xdeadbeef) ++#define BCM_6318_PCMCIA_BASE (0xdeadbeef) ++#define BCM_6318_PCIE_BASE (0xb0010000) ++#define BCM_6318_SDRAM_REGS_BASE (0xdeadbeef) ++#define BCM_6318_DSL_BASE (0xdeadbeef) ++#define BCM_6318_UBUS_BASE (0xdeadbeef) ++#define BCM_6318_ENET0_BASE (0xdeadbeef) ++#define BCM_6318_ENET1_BASE (0xdeadbeef) ++#define BCM_6318_ENETDMA_BASE (0xb0088000) ++#define BCM_6318_ENETDMAC_BASE (0xb0088200) ++#define BCM_6318_ENETDMAS_BASE (0xb0088400) ++#define BCM_6318_ENETSW_BASE (0xb0080000) ++#define BCM_6318_EHCI0_BASE (0xb0005000) ++#define BCM_6318_SDRAM_BASE (0xb0004000) ++#define BCM_6318_MEMC_BASE (0xdeadbeef) ++#define BCM_6318_DDR_BASE (0xdeadbeef) ++#define BCM_6318_M2M_BASE (0xdeadbeef) ++#define BCM_6318_ATM_BASE (0xdeadbeef) ++#define BCM_6318_XTM_BASE (0xdeadbeef) ++#define BCM_6318_XTMDMA_BASE (0xb000c000) ++#define BCM_6318_XTMDMAC_BASE (0xdeadbeef) ++#define BCM_6318_XTMDMAS_BASE (0xdeadbeef) ++#define BCM_6318_PCM_BASE (0xdeadbeef) ++#define BCM_6318_PCMDMA_BASE (0xdeadbeef) ++#define BCM_6318_PCMDMAC_BASE (0xdeadbeef) ++#define BCM_6318_PCMDMAS_BASE (0xdeadbeef) ++#define BCM_6318_RNG_BASE (0xdeadbeef) ++#define BCM_6318_MISC_BASE (0xb0000280) ++#define BCM_6318_OTP_BASE (0xdeadbeef) ++ ++#define BCM_6318_STRAP_BASE (0xb0000900) ++ ++/* + * 6328 register sets base address + */ + #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) +@@ -819,6 +877,55 @@ enum bcm63xx_irq { + #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) + #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) + ++/* ++ * 6318 irqs ++ */ ++#define BCM_6318_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) ++#define BCM_6318_VERY_HIGH_IRQ_BASE (BCM_6318_HIGH_IRQ_BASE + 32) ++ ++#define BCM_6318_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) ++#define BCM_6318_SPI_IRQ 0 ++#define BCM_6318_UART0_IRQ (IRQ_INTERNAL_BASE + 28) ++#define BCM_6318_UART1_IRQ 0 ++#define BCM_6318_DSL_IRQ (IRQ_INTERNAL_BASE + 21) ++#define BCM_6318_UDC0_IRQ 0 ++#define BCM_6318_ENET0_IRQ 0 ++#define BCM_6318_ENET1_IRQ 0 ++#define BCM_6318_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) ++#define BCM_6318_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) ++#define BCM_6318_OHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 9) ++#define BCM_6318_EHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 10) ++#define BCM_6318_USBD_IRQ (IRQ_INTERNAL_BASE + 4) ++#define BCM_6318_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) ++#define BCM_6318_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) ++#define BCM_6318_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) ++#define BCM_6318_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) ++#define BCM_6318_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_6318_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) ++#define BCM_6318_PCMCIA_IRQ 0 ++#define BCM_6318_ENET0_RXDMA_IRQ 0 ++#define BCM_6318_ENET0_TXDMA_IRQ 0 ++#define BCM_6318_ENET1_RXDMA_IRQ 0 ++#define BCM_6318_ENET1_TXDMA_IRQ 0 ++#define BCM_6318_PCI_IRQ (IRQ_INTERNAL_BASE + 23) ++#define BCM_6318_ATM_IRQ 0 ++#define BCM_6318_ENETSW_RXDMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 0) ++#define BCM_6318_ENETSW_RXDMA1_IRQ (BCM_6318_HIGH_IRQ_BASE + 1) ++#define BCM_6318_ENETSW_RXDMA2_IRQ (BCM_6318_HIGH_IRQ_BASE + 2) ++#define BCM_6318_ENETSW_RXDMA3_IRQ (BCM_6318_HIGH_IRQ_BASE + 3) ++#define BCM_6318_ENETSW_TXDMA0_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 10) ++#define BCM_6318_ENETSW_TXDMA1_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 11) ++#define BCM_6318_ENETSW_TXDMA2_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 12) ++#define BCM_6318_ENETSW_TXDMA3_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 13) ++#define BCM_6318_XTM_IRQ (BCM_6318_HIGH_IRQ_BASE + 31) ++#define BCM_6318_XTM_DMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 11) ++ ++#define BCM_6318_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) ++#define BCM_6318_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) ++#define BCM_6318_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) ++#define BCM_6318_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) ++#define BCM_6318_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) ++#define BCM_6318_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) + + /* + * 6328 irqs +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -52,6 +52,39 @@ + CKCTL_3368_EMUSB_EN | \ + CKCTL_3368_USBU_EN) + ++#define CKCTL_6318_ADSL_ASB_EN (1 << 0) ++#define CKCTL_6318_USB_ASB_EN (1 << 1) ++#define CKCTL_6318_MIPS_ASB_EN (1 << 2) ++#define CKCTL_6318_PCIE_ASB_EN (1 << 3) ++#define CKCTL_6318_PHYMIPS_ASB_EN (1 << 4) ++#define CKCTL_6318_ROBOSW_ASB_EN (1 << 5) ++#define CKCTL_6318_SAR_ASB_EN (1 << 6) ++#define CKCTL_6318_SDR_ASB_EN (1 << 7) ++#define CKCTL_6318_SWREG_ASB_EN (1 << 8) ++#define CKCTL_6318_PERIPH_ASB_EN (1 << 9) ++#define CKCTL_6318_CPUBUS160_EN (1 << 10) ++#define CKCTL_6318_ADSL_EN (1 << 11) ++#define CKCTL_6318_SAR125_EN (1 << 12) ++#define CKCTL_6318_MIPS_EN (1 << 13) ++#define CKCTL_6318_PCIE_EN (1 << 14) ++#define CKCTL_6318_ROBOSW250_EN (1 << 16) ++#define CKCTL_6318_ROBOSW025_EN (1 << 17) ++#define CKCTL_6318_SDR_EN (1 << 19) ++#define CKCTL_6318_USB_EN (1 << 20) /* both device and host */ ++#define CKCTL_6318_HSSPI_EN (1 << 25) ++#define CKCTL_6318_PCIE25_EN (1 << 27) ++#define CKCTL_6318_PHYMIPS_EN (1 << 28) ++#define CKCTL_6318_ADSL_AFE_EN (1 << 29) ++#define CKCTL_6318_ADSL_QPROC_EN (1 << 30) ++ ++#define CKCTL_6318_ALL_SAFE_EN (CKCTL_6318_PHYMIPS_EN | \ ++ CKCTL_6318_ADSL_QPROC_EN | \ ++ CKCTL_6318_ADSL_AFE_EN | \ ++ CKCTL_6318_ADSL_EN | \ ++ CKCTL_6318_SAR_EN | \ ++ CKCTL_6318_USB_EN | \ ++ CKCTL_6318_PCIE_EN) ++ + #define CKCTL_6328_PHYMIPS_EN (1 << 0) + #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) + #define CKCTL_6328_ADSL_AFE_EN (1 << 2) +@@ -259,12 +292,27 @@ + CKCTL_63268_TBUS_EN | \ + CKCTL_63268_ROBOSW250_EN) + ++/* UBUS Clock Control register */ ++#define PERF_UB_CKCTL_REG 0x10 ++ ++#define UB_CKCTL_6318_ADSL_EN (1 << 0) ++#define UB_CKCTL_6318_ARB_EN (1 << 1) ++#define UB_CKCTL_6318_MIPS_EN (1 << 2) ++#define UB_CKCTL_6318_PCIE_EN (1 << 3) ++#define UB_CKCTL_6318_PERIPH_EN (1 << 4) ++#define UB_CKCTL_6318_PHYMIPS_EN (1 << 5) ++#define UB_CKCTL_6318_ROBOSW_EN (1 << 6) ++#define UB_CKCTL_6318_SAR_EN (1 << 7) ++#define UB_CKCTL_6318_SDR_EN (1 << 8) ++#define UB_CKCTL_6318_USB_EN (1 << 9) ++ + /* System PLL Control register */ + #define PERF_SYS_PLL_CTL_REG 0x8 + #define SYS_PLL_SOFT_RESET 0x1 + + /* Interrupt Mask register */ + #define PERF_IRQMASK_3368_REG 0xc ++#define PERF_IRQMASK_6318_REG 0x20 + #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10) + #define PERF_IRQMASK_6338_REG 0xc + #define PERF_IRQMASK_6345_REG 0xc +@@ -276,6 +324,7 @@ + + /* Interrupt Status register */ + #define PERF_IRQSTAT_3368_REG 0x10 ++#define PERF_IRQSTAT_6318_REG 0x30 + #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10) + #define PERF_IRQSTAT_6338_REG 0x10 + #define PERF_IRQSTAT_6345_REG 0x10 +@@ -287,6 +336,7 @@ + + /* External Interrupt Configuration register */ + #define PERF_EXTIRQ_CFG_REG_3368 0x14 ++#define PERF_EXTIRQ_CFG_REG_6318 0x18 + #define PERF_EXTIRQ_CFG_REG_6328 0x18 + #define PERF_EXTIRQ_CFG_REG_6338 0x14 + #define PERF_EXTIRQ_CFG_REG_6345 0x14 +@@ -320,6 +370,7 @@ + + /* Soft Reset register */ + #define PERF_SOFTRESET_REG 0x28 ++#define PERF_SOFTRESET_6318_REG 0x10 + #define PERF_SOFTRESET_6328_REG 0x10 + #define PERF_SOFTRESET_6358_REG 0x34 + #define PERF_SOFTRESET_6362_REG 0x10 +@@ -333,6 +384,18 @@ + #define SOFTRESET_3368_USBS_MASK (1 << 11) + #define SOFTRESET_3368_PCM_MASK (1 << 13) + ++#define SOFTRESET_6318_SPI_MASK (1 << 0) ++#define SOFTRESET_6318_EPHY_MASK (1 << 1) ++#define SOFTRESET_6318_SAR_MASK (1 << 2) ++#define SOFTRESET_6318_ENETSW_MASK (1 << 3) ++#define SOFTRESET_6318_USBS_MASK (1 << 4) ++#define SOFTRESET_6318_USBH_MASK (1 << 5) ++#define SOFTRESET_6318_PCIE_CORE_MASK (1 << 6) ++#define SOFTRESET_6318_PCIE_MASK (1 << 7) ++#define SOFTRESET_6318_PCIE_EXT_MASK (1 << 8) ++#define SOFTRESET_6318_PCIE_HARD_MASK (1 << 9) ++#define SOFTRESET_6318_ADSL_MASK (1 << 10) ++ + #define SOFTRESET_6328_SPI_MASK (1 << 0) + #define SOFTRESET_6328_EPHY_MASK (1 << 1) + #define SOFTRESET_6328_SAR_MASK (1 << 2) +@@ -504,8 +567,17 @@ + #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) + #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) + ++#define TIMER_IRQMASK_6318_REG 0x0 ++#define TIMER_IRQSTAT_6318_REG 0x4 ++#define IRQSTATMASK_TIMER0 (1 << 0) ++#define IRQSTATMASK_TIMER1 (1 << 1) ++#define IRQSTATMASK_TIMER2 (1 << 2) ++#define IRQSTATMASK_TIMER3 (1 << 3) ++#define IRQSTATMASK_WDT (1 << 4) ++ + /* Timer control register */ + #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) ++#define TIMER_CTRx_6318_REG(x) (0x8 + (x * 4)) + #define TIMER_CTL0_REG 0x4 + #define TIMER_CTL1_REG 0x8 + #define TIMER_CTL2_REG 0xC +@@ -1372,6 +1444,8 @@ + #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) + #define SDRAM_CFG_BANK_SHIFT 13 + #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) ++#define SDRAM_CFG_6318_SPACE_SHIFT 4 ++#define SDRAM_CFG_6318_SPACE_MASK (0xf << SDRAM_CFG_6318_SPACE_SHIFT) + + #define SDRAM_MBASE_REG 0xc + +--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h ++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h +@@ -22,6 +22,7 @@ static inline int is_bcm63xx_internal_re + if (offset >= 0xfff00000) + return 1; + break; ++ case BCM6318_CPU_ID: + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: + case BCM6368_CPU_ID: +--- a/arch/mips/bcm63xx/dev-hsspi.c ++++ b/arch/mips/bcm63xx/dev-hsspi.c +@@ -35,7 +35,8 @@ static struct platform_device bcm63xx_hs + + int __init bcm63xx_hsspi_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() && ++ !BCMCPU_IS_63268()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); +--- a/arch/mips/bcm63xx/dev-usb-usbd.c ++++ b/arch/mips/bcm63xx/dev-usb-usbd.c +@@ -41,7 +41,7 @@ int __init bcm63xx_usbd_register(const s + IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 }; + int i; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6368()) + return 0; + + usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD); +--- a/arch/mips/bcm63xx/dev-enet.c ++++ b/arch/mips/bcm63xx/dev-enet.c +@@ -176,8 +176,8 @@ static int __init register_shared(void) + else + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || +- BCMCPU_IS_63268()) ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || ++ BCMCPU_IS_6368() || BCMCPU_IS_63268()) + chan_count = 32; + else if (BCMCPU_IS_6345()) + chan_count = 8; +@@ -277,8 +277,8 @@ bcm63xx_enetsw_register(const struct bcm + { + int ret; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && +- !BCMCPU_IS_63268()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() && ++ !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) + return -ENODEV; + + ret = register_shared(); +@@ -295,7 +295,7 @@ bcm63xx_enetsw_register(const struct bcm + + memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd)); + +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) + enetsw_pd.num_ports = ENETSW_PORTS_6328; + else if (BCMCPU_IS_6362() || BCMCPU_IS_6368() || + BCMCPU_VARIANT_IS_63168() || BCMCPU_VARIANT_IS_63169()) +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void); + static inline unsigned long bcm63xx_gpio_count(void) + { + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: ++ return 50; + case BCM6328_CPU_ID: + return 32; + case BCM3368_CPU_ID: +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -81,7 +81,8 @@ static struct platform_device bcm63xx_eh + + int __init bcm63xx_ehci_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && ++ !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) + return 0; + + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); diff --git a/target/linux/brcm63xx/patches-3.13/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch b/target/linux/brcm63xx/patches-3.13/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch new file mode 100644 index 0000000000..71044f846e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch @@ -0,0 +1,156 @@ +From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 8 Dec 2013 14:17:50 +0100 +Subject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals + +--- + arch/mips/bcm63xx/reset.c | 39 ++++++++++++++-------- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 2 ++ + arch/mips/pci/pci-bcm63xx.c | 7 ++++ + 3 files changed, 34 insertions(+), 14 deletions(-) + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -28,7 +28,9 @@ + [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \ + [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \ + [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \ +- [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, ++ [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, \ ++ [BCM63XX_RESET_PCIE_CORE] = BCM## __cpu ##_RESET_PCIE_CORE, \ ++ [BCM63XX_RESET_PCIE_HARD] = BCM## __cpu ##_RESET_PCIE_HARD, + + #define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK + #define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK +@@ -42,6 +44,8 @@ + #define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK + #define BCM3368_RESET_PCIE 0 + #define BCM3368_RESET_PCIE_EXT 0 ++#define BCM3368_RESET_PCIE_CORE 0 ++#define BCM3368_RESET_PCIE_HARD 0 + + + #define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK +@@ -54,11 +58,10 @@ + #define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK + #define BCM6318_RESET_PCM 0 + #define BCM6318_RESET_MPI 0 +-#define BCM6318_RESET_PCIE \ +- (SOFTRESET_6318_PCIE_MASK | \ +- SOFTRESET_6318_PCIE_CORE_MASK | \ +- SOFTRESET_6318_PCIE_HARD_MASK) ++#define BCM6318_RESET_PCIE SOFTRESET_6318_PCIE_MASK + #define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK ++#define BCM6318_RESET_PCIE_CORE SOFTRESET_6318_PCIE_CORE_MASK ++#define BCM6318_RESET_PCIE_HARD SOFTRESET_6318_PCIE_HARD_MASK + + #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK + #define BCM6328_RESET_ENET 0 +@@ -70,11 +73,10 @@ + #define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK + #define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK + #define BCM6328_RESET_MPI 0 +-#define BCM6328_RESET_PCIE \ +- (SOFTRESET_6328_PCIE_MASK | \ +- SOFTRESET_6328_PCIE_CORE_MASK | \ +- SOFTRESET_6328_PCIE_HARD_MASK) ++#define BCM6328_RESET_PCIE SOFTRESET_6328_PCIE_MASK + #define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK ++#define BCM6328_RESET_PCIE_CORE SOFTRESET_6328_PCIE_CORE_MASK ++#define BCM6328_RESET_PCIE_HARD SOFTRESET_6328_PCIE_HARD_MASK + + #define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK + #define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK +@@ -88,6 +90,8 @@ + #define BCM6338_RESET_MPI 0 + #define BCM6338_RESET_PCIE 0 + #define BCM6338_RESET_PCIE_EXT 0 ++#define BCM6338_RESET_PCIE_CORE 0 ++#define BCM6338_RESET_PCIE_HARD 0 + + #define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK + #define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK +@@ -101,6 +105,8 @@ + #define BCM6348_RESET_MPI 0 + #define BCM6348_RESET_PCIE 0 + #define BCM6348_RESET_PCIE_EXT 0 ++#define BCM6348_RESET_PCIE_CORE 0 ++#define BCM6348_RESET_PCIE_HARD 0 + + #define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK + #define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK +@@ -114,6 +120,8 @@ + #define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK + #define BCM6358_RESET_PCIE 0 + #define BCM6358_RESET_PCIE_EXT 0 ++#define BCM6358_RESET_PCIE_CORE 0 ++#define BCM6358_RESET_PCIE_HARD 0 + + #define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK + #define BCM6362_RESET_ENET 0 +@@ -125,9 +133,10 @@ + #define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK + #define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK + #define BCM6362_RESET_MPI 0 +-#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \ +- SOFTRESET_6362_PCIE_CORE_MASK) ++#define BCM6362_RESET_PCIE SOFTRESET_6362_PCIE_MASK + #define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK ++#define BCM6362_RESET_PCIE_CORE SOFTRESET_6362_PCIE_CORE_MASK ++#define BCM6362_RESET_PCIE_HARD 0 + + #define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK + #define BCM6368_RESET_ENET 0 +@@ -141,6 +150,8 @@ + #define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK + #define BCM6368_RESET_PCIE 0 + #define BCM6368_RESET_PCIE_EXT 0 ++#define BCM6368_RESET_PCIE_CORE 0 ++#define BCM6368_RESET_PCIE_HARD 0 + + #define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK + #define BCM63268_RESET_ENET 0 +@@ -152,10 +163,10 @@ + #define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK + #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK + #define BCM63268_RESET_MPI 0 +-#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ +- SOFTRESET_63268_PCIE_CORE_MASK | \ +- SOFTRESET_63268_PCIE_HARD_MASK) ++#define BCM63268_RESET_PCIE SOFTRESET_63268_PCIE_MASK + #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK ++#define BCM63268_RESET_PCIE_CORE SOFTRESET_63268_PCIE_CORE_MASK ++#define BCM63268_RESET_PCIE_HARD SOFTRESET_63268_PCIE_HARD_MASK + + /* + * core reset bits +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h +@@ -14,6 +14,8 @@ enum bcm63xx_core_reset { + BCM63XX_RESET_MPI, + BCM63XX_RESET_PCIE, + BCM63XX_RESET_PCIE_EXT, ++ BCM63XX_RESET_PCIE_CORE, ++ BCM63XX_RESET_PCIE_HARD, + }; + + void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset); +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo + + /* reset the PCIe core */ + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1); + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); ++ if (BCMCPU_IS_6328() || BCMCPU_IS_63268()) { ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0); ++ } + mdelay(10); + ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0); + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); + mdelay(10); + diff --git a/target/linux/brcm63xx/patches-3.13/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch b/target/linux/brcm63xx/patches-3.13/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch new file mode 100644 index 0000000000..2225587f69 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch @@ -0,0 +1,342 @@ +From 11a8ab8dac4ef5d0d70199843043927edce1d4db Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 15 Dec 2013 20:47:34 +0100 +Subject: [PATCH 53/53] MIPS: BCM63XX: add PCIe support for BCM6318 + +--- + arch/mips/bcm63xx/clk.c | 25 ++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 ++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 60 +++++++++++- + arch/mips/pci/ops-bcm63xx.c | 16 +++- + arch/mips/pci/pci-bcm63xx.c | 106 ++++++++++++++++++---- + 5 files changed, 184 insertions(+), 29 deletions(-) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -50,6 +50,18 @@ static void bcm_hwclock_set(u32 mask, in + bcm_perf_writel(reg, PERF_CKCTL_REG); + } + ++static void bcm_ub_hwclock_set(u32 mask, int enable) ++{ ++ u32 reg; ++ ++ reg = bcm_perf_readl(PERF_UB_CKCTL_REG); ++ if (enable) ++ reg |= mask; ++ else ++ reg &= ~mask; ++ bcm_perf_writel(reg, PERF_UB_CKCTL_REG); ++} ++ + /* + * Ethernet MAC "misc" clock: dma clocks and main clock on 6348 + */ +@@ -317,12 +329,17 @@ static struct clk clk_ipsec = { + + static void pcie_set(struct clk *clk, int enable) + { +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) { ++ bcm_hwclock_set(CKCTL_6318_PCIE_EN, enable); ++ bcm_hwclock_set(CKCTL_6318_PCIE25_EN, enable); ++ bcm_ub_hwclock_set(UB_CKCTL_6318_PCIE_EN, enable); ++ } else if (BCMCPU_IS_6328()) { + bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable); +- else if (BCMCPU_IS_6362()) ++ } else if (BCMCPU_IS_6362()) { + bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable); +- else if (BCMCPU_IS_63268()) ++ } else if (BCMCPU_IS_63268()) { + bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable); ++ } + } + + static struct clk clk_pcie = { +@@ -405,7 +422,7 @@ struct clk *clk_get(struct device *dev, + if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) && + !strcmp(id, "ipsec")) + return &clk_ipsec; +- if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) && ++ if ((BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) && + !strcmp(id, "pcie")) + return &clk_pcie; + return ERR_PTR(-ENOENT); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -40,6 +40,12 @@ + #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ + BCM_CB_MEM_SIZE - 1) + ++#define BCM_PCIE_MEM_BASE_PA_6318 0x10200000 ++#define BCM_PCIE_MEM_SIZE_6318 (1 * 1024 * 1024) ++#define BCM_PCIE_MEM_END_PA_6318 (BCM_PCIE_MEM_BASE_PA_6318 + \ ++ BCM_PCIE_MEM_SIZE_6318 - 1) ++ ++ + #define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000 + #define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024) + #define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -1662,6 +1662,17 @@ + * _REG relative to RSET_PCIE + *************************************************************************/ + ++#define PCIE_SPECIFIC_REG 0x188 ++#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT 0 ++#define SPECIFIC_ENDIAN_MODE_BAR1_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT) ++#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT 2 ++#define SPECIFIC_ENDIAN_MODE_BAR2_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT) ++#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT 4 ++#define SPECIFIC_ENDIAN_MODE_BAR3_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT) ++#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN 0 ++#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1 ++#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN 2 ++ + #define PCIE_CONFIG2_REG 0x408 + #define CONFIG2_BAR1_SIZE_EN 1 + #define CONFIG2_BAR1_SIZE_MASK 0xf +@@ -1707,7 +1718,54 @@ + #define PCIE_RC_INT_C (1 << 2) + #define PCIE_RC_INT_D (1 << 3) + +-#define PCIE_DEVICE_OFFSET 0x8000 ++#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG 0x400c ++#define C2P_MEM_WIN_ENDIAN_MODE_MASK 0x3 ++#define C2P_MEM_WIN_ENDIAN_NO_SWAP 0 ++#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1 ++#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2 ++#define C2P_MEM_WIN_BASE_ADDR_SHIFT 20 ++#define C2P_MEM_WIN_BASE_ADDR_MASK (0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT) ++ ++#define PCIE_RC_BAR1_CONFIG_LO_REG 0x402c ++#define RC_BAR_CFG_LO_SIZE_256MB 0xd ++#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT 20 ++#define RC_BAR_CFG_LO_MATCH_ADDR_MASK (0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT) ++ ++#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070 ++#define C2P_BASELIMIT_LIMIT_SHIFT 20 ++#define C2P_BASELIMIT_LIMIT_MASK (0xfff << C2P_BASELIMIT_LIMIT_SHIFT) ++#define C2P_BASELIMIT_BASE_SHIFT 4 ++#define C2P_BASELIMIT_BASE_MASK (0xfff << C2P_BASELIMIT_BASE_SHIFT) ++ ++#define PCIE_UBUS_BAR1_CFG_REMAP_REG 0x4088 ++#define BAR1_CFG_REMAP_OFFSET_SHIFT 20 ++#define BAR1_CFG_REMAP_OFFSET_MASK (0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT) ++#define BAR1_CFG_REMAP_ACCESS_EN 1 ++ ++#define PCIE_HARD_DEBUG_REG 0x4204 ++#define HARD_DEBUG_SERDES_IDDQ (1 << 23) ++ ++#define PCIE_CPU_INT1_MASK_CLEAR_REG 0x830c ++#define CPU_INT_PCIE_ERR_ATTN_CPU (1 << 0) ++#define CPU_INT_PCIE_INTA (1 << 1) ++#define CPU_INT_PCIE_INTB (1 << 2) ++#define CPU_INT_PCIE_INTC (1 << 3) ++#define CPU_INT_PCIE_INTD (1 << 4) ++#define CPU_INT_PCIE_INTR (1 << 5) ++#define CPU_INT_PCIE_NMI (1 << 6) ++#define CPU_INT_PCIE_UBUS (1 << 7) ++#define CPU_INT_IPI (1 << 8) ++ ++#define PCIE_EXT_CFG_INDEX_REG 0x8400 ++#define EXT_CFG_FUNC_NUM_SHIFT 12 ++#define EXT_CFG_FUNC_NUM_MASK (0x7 << EXT_CFG_FUNC_NUM_SHIFT) ++#define EXT_CFG_DEV_NUM_SHIFT 15 ++#define EXT_CFG_DEV_NUM_MASK (0xf << EXT_CFG_DEV_NUM_SHIFT) ++#define EXT_CFG_BUS_NUM_SHIFT 20 ++#define EXT_CFG_BUS_NUM_MASK (0xff << EXT_CFG_BUS_NUM_SHIFT) ++ ++#define PCIE_DEVICE_OFFSET_6318 0x9000 ++#define PCIE_DEVICE_OFFSET_6328 0x8000 + + /************************************************************************* + * _REG relative to RSET_OTP +--- a/arch/mips/pci/ops-bcm63xx.c ++++ b/arch/mips/pci/ops-bcm63xx.c +@@ -489,8 +489,12 @@ static int bcm63xx_pcie_read(struct pci_ + if (!bcm63xx_pcie_can_access(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (bus->number == PCIE_BUS_DEVICE) +- reg += PCIE_DEVICE_OFFSET; ++ if (bus->number == PCIE_BUS_DEVICE) { ++ if (BCMCPU_IS_6318()) ++ reg += PCIE_DEVICE_OFFSET_6318; ++ else ++ reg += PCIE_DEVICE_OFFSET_6328; ++ } + + data = bcm_pcie_readl(reg); + +@@ -509,8 +513,12 @@ static int bcm63xx_pcie_write(struct pci + if (!bcm63xx_pcie_can_access(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (bus->number == PCIE_BUS_DEVICE) +- reg += PCIE_DEVICE_OFFSET; ++ if (bus->number == PCIE_BUS_DEVICE) { ++ if (BCMCPU_IS_6318()) ++ reg += PCIE_DEVICE_OFFSET_6318; ++ else ++ reg += PCIE_DEVICE_OFFSET_6328; ++ } + + + data = bcm_pcie_readl(reg); +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -118,7 +118,7 @@ static void bcm63xx_int_cfg_writel(u32 v + + void __iomem *pci_iospace_start; + +-static void __init bcm63xx_reset_pcie(void) ++static void __init bcm63xx_reset_pcie_gen1(void) + { + u32 val; + u32 reg; +@@ -152,20 +152,32 @@ static void __init bcm63xx_reset_pcie(vo + mdelay(200); + } + +-static struct clk *pcie_clk; +- +-static int __init bcm63xx_register_pcie(void) ++static void __init bcm63xx_reset_pcie_gen2(void) + { + u32 val; + +- /* enable clock */ +- pcie_clk = clk_get(NULL, "pcie"); +- if (IS_ERR_OR_NULL(pcie_clk)) +- return -ENODEV; ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0); + +- clk_prepare_enable(pcie_clk); ++ /* reset the PCIe core */ ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); ++ mdelay(10); ++ val = bcm_pcie_readl(PCIE_HARD_DEBUG_REG); ++ val &= ~HARD_DEBUG_SERDES_IDDQ; ++ bcm_pcie_writel(val, PCIE_HARD_DEBUG_REG); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0); ++ mdelay(200); ++} + +- bcm63xx_reset_pcie(); ++static void __init bcm63xx_init_pcie_gen1(void) ++{ ++ u32 val; + + /* configure the PCIe bridge */ + val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); +@@ -190,6 +202,65 @@ static int __init bcm63xx_register_pcie( + val |= OPT2_CFG_TYPE1_BD_SEL; + bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG); + ++ /* set bar0 to little endian */ ++ val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; ++ val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; ++ val |= BASEMASK_REMAP_EN; ++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); ++ ++ val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; ++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); ++} ++ ++static void __init bcm63xx_init_pcie_gen2(void) ++{ ++ u32 val; ++ ++ bcm_pcie_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB | ++ CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD, ++ PCIE_CPU_INT1_MASK_CLEAR_REG); ++ ++ val = bcm_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK; ++ val |= (bcm_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT) << ++ C2P_BASELIMIT_BASE_SHIFT; ++ ++ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG); ++ ++ /* set bar0 to little endian */ ++ val = bcm_pcie_readl(PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG); ++ val |= bcm_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK; ++ val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP; ++ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG); ++ ++ bcm_pcie_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN, PCIE_SPECIFIC_REG); ++ bcm_pcie_writel(RC_BAR_CFG_LO_SIZE_256MB, PCIE_RC_BAR1_CONFIG_LO_REG); ++ bcm_pcie_writel(BAR1_CFG_REMAP_ACCESS_EN, PCIE_UBUS_BAR1_CFG_REMAP_REG); ++ ++ bcm_pcie_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT, ++ PCIE_EXT_CFG_INDEX_REG); ++} ++ ++static struct clk *pcie_clk; ++ ++static int __init bcm63xx_register_pcie(void) ++{ ++ u32 val; ++ ++ /* enable clock */ ++ pcie_clk = clk_get(NULL, "pcie"); ++ if (IS_ERR_OR_NULL(pcie_clk)) ++ return -ENODEV; ++ ++ clk_prepare_enable(pcie_clk); ++ ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { ++ bcm63xx_reset_pcie_gen1(); ++ bcm63xx_init_pcie_gen1(); ++ } else { ++ bcm63xx_reset_pcie_gen2(); ++ bcm63xx_init_pcie_gen2(); ++ } ++ + /* setup class code as bridge */ + val = bcm_pcie_readl(PCIE_IDVAL3_REG); + val &= ~IDVAL3_CLASS_CODE_MASK; +@@ -201,15 +272,6 @@ static int __init bcm63xx_register_pcie( + val &= ~CONFIG2_BAR1_SIZE_MASK; + bcm_pcie_writel(val, PCIE_CONFIG2_REG); + +- /* set bar0 to little endian */ +- val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; +- val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; +- val |= BASEMASK_REMAP_EN; +- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); +- +- val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; +- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); +- + register_pci_controller(&bcm63xx_pcie_controller); + + return 0; +@@ -341,7 +403,10 @@ static int __init bcm63xx_pci_init(void) + if (!bcm63xx_pci_enabled) + return -ENODEV; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { ++ if (BCMCPU_IS_6318()) { ++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6318; ++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6318; ++ } if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { + bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; + bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; + } else if (BCMCPU_IS_63268()) { +@@ -350,6 +415,7 @@ static int __init bcm63xx_pci_init(void) + } + + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: + case BCM63268_CPU_ID: diff --git a/target/linux/brcm63xx/patches-3.13/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch b/target/linux/brcm63xx/patches-3.13/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch new file mode 100644 index 0000000000..a91a29b16c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch @@ -0,0 +1,74 @@ +From 9a97177b907330971aa7bf41855fafc2602e1c18 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 22 Dec 2013 12:26:57 +0100 +Subject: [PATCH 51/56] MIPS: BCM63XX: detect flash type early and store the + result + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/dev-flash.c | 10 +++++++--- + arch/mips/bcm63xx/prom.c | 4 ++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 ++ + 3 files changed, 13 insertions(+), 3 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -22,6 +22,8 @@ + #include <bcm63xx_regs.h> + #include <bcm63xx_io.h> + ++static int flash_type; ++ + static struct mtd_partition mtd_partitions[] = { + { + .name = "cfe", +@@ -108,13 +110,15 @@ static int __init bcm63xx_detect_flash_t + } + } + ++void __init bcm63xx_flash_detect(void) ++{ ++ flash_type = bcm63xx_detect_flash_type(); ++} ++ + int __init bcm63xx_flash_register(void) + { +- int flash_type; + u32 val; + +- flash_type = bcm63xx_detect_flash_type(); +- + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: + /* read base address of boot chip select (0) */ +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -18,6 +18,7 @@ + #include <bcm63xx_io.h> + #include <bcm63xx_regs.h> + #include <bcm63xx_gpio.h> ++#include <bcm63xx_dev_flash.h> + + void __init prom_init(void) + { +@@ -56,6 +57,9 @@ void __init prom_init(void) + /* register gpiochip */ + bcm63xx_gpio_init(); + ++ /* detect and setup flash access */ ++ bcm63xx_flash_detect(); ++ + /* do low level board init */ + board_prom_init(); + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -7,6 +7,8 @@ enum { + BCM63XX_FLASH_TYPE_NAND, + }; + ++void bcm63xx_flash_detect(void); ++ + int __init bcm63xx_flash_register(void); + + #endif /* __BCM63XX_FLASH_H */ diff --git a/target/linux/brcm63xx/patches-3.13/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch b/target/linux/brcm63xx/patches-3.13/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch new file mode 100644 index 0000000000..2b19600776 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch @@ -0,0 +1,63 @@ +From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sun, 22 Dec 2013 13:25:25 +0100 +Subject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot + +Some bootloaders leave the flash access in an invalid state with dual +read enabled; fix it by disabling it and falling back to simple fast +reads. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/dev-flash.c | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -110,9 +110,46 @@ static int __init bcm63xx_detect_flash_t + } + } + ++#define HSSPI_FLASH_CTRL_REG 0x14 ++#define FLASH_CTRL_READ_OPCODE_MASK 0xff ++#define FLASH_CTRL_ADDR_BYTES_MASK (0x3 << 8) ++#define FLASH_CTRL_ADDR_BYTES_2 (0 << 8) ++#define FLASH_CTRL_ADDR_BYTES_3 (1 << 8) ++#define FLASH_CTRL_ADDR_BYTES_4 (2 << 8) ++#define FLASH_CTRL_MB_EN (1 << 23) ++ + void __init bcm63xx_flash_detect(void) + { + flash_type = bcm63xx_detect_flash_type(); ++ ++ /* reduce flash mapping to single i/o reads for safety */ ++ if (flash_type == BCM63XX_FLASH_TYPE_SERIAL && ++ (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || ++ BCMCPU_IS_63268())) { ++ u32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG); ++ ++ if (!(val & FLASH_CTRL_MB_EN)) ++ return; ++ ++ val &= ~FLASH_CTRL_MB_EN; ++ val &= ~FLASH_CTRL_READ_OPCODE_MASK; ++ ++ switch (val & FLASH_CTRL_ADDR_BYTES_MASK) { ++ case FLASH_CTRL_ADDR_BYTES_3: ++ val |= 0x0b; /* OPCODE_FAST_READ */ ++ break; ++ case FLASH_CTRL_ADDR_BYTES_4: ++ val |= 0x0c; /* OPCODE_FAST_READ_4B */ ++ break; ++ case FLASH_CTRL_ADDR_BYTES_2: ++ default: ++ pr_warn("unsupported address byte mode (%x), not fixing up\n", ++ val & FLASH_CTRL_ADDR_BYTES_MASK); ++ return; ++ } ++ ++ bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG); ++ } + } + + int __init bcm63xx_flash_register(void) diff --git a/target/linux/brcm63xx/patches-3.13/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch b/target/linux/brcm63xx/patches-3.13/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch new file mode 100644 index 0000000000..384702c80f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -136,7 +136,11 @@ static struct clk clk_ephy = { + */ + static void enetsw_set(struct clk *clk, int enable) + { +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) { ++ bcm_hwclock_set(CKCTL_6318_ROBOSW250_EN | ++ CKCTL_6318_ROBOSW025_EN, enable); ++ bcm_ub_hwclock_set(UB_CKCTL_6318_ROBOSW_EN, enable); ++ } else if (BCMCPU_IS_6328()) + bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable); + else if (BCMCPU_IS_6362()) + bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable); +@@ -183,18 +187,22 @@ static struct clk clk_pcm = { + */ + static void usbh_set(struct clk *clk, int enable) + { +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) { ++ bcm_hwclock_set(CKCTL_6318_USB_EN, enable); ++ bcm_ub_hwclock_set(UB_CKCTL_6318_USB_EN, enable); ++ } else if (BCMCPU_IS_6328()) { + bcm_hwclock_set(CKCTL_6328_USBH_EN, enable); +- else if (BCMCPU_IS_6348()) ++ } else if (BCMCPU_IS_6348()) { + bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); +- else if (BCMCPU_IS_6362()) ++ } else if (BCMCPU_IS_6362()) { + bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); +- else if (BCMCPU_IS_6368()) ++ } else if (BCMCPU_IS_6368()) { + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); +- else if (BCMCPU_IS_63268()) ++ } else if (BCMCPU_IS_63268()) { + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); +- else ++ } else { + return; ++ } + + if (enable) + msleep(100); +@@ -405,9 +413,9 @@ struct clk *clk_get(struct device *dev, + return &clk_enetsw; + if (!strcmp(id, "ephy")) + return &clk_ephy; +- if (!strcmp(id, "usbh")) ++ if (!strcmp(id, "usbh") || (BCMCPU_IS_6318() && !strcmp(id, "usbd"))) + return &clk_usbh; +- if (!strcmp(id, "usbd")) ++ if (!strcmp(id, "usbd") && !BCMCPU_IS_6318()) + return &clk_usbd; + if (!strcmp(id, "spi")) + return &clk_spi; diff --git a/target/linux/brcm63xx/patches-3.13/347-MIPS-BCM6318-USB-support.patch b/target/linux/brcm63xx/patches-3.13/347-MIPS-BCM6318-USB-support.patch new file mode 100644 index 0000000000..cd4189be5e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/347-MIPS-BCM6318-USB-support.patch @@ -0,0 +1,124 @@ +--- a/arch/mips/bcm63xx/usb-common.c ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -109,6 +109,27 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_6318()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); ++ reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG); + } + + spin_unlock_irqrestore(&usb_priv_reg_lock, flags); +@@ -144,6 +165,27 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_6318()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); ++ reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG); + } + + spin_unlock_irqrestore(&usb_priv_reg_lock, flags); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -800,6 +800,12 @@ + #define GPIO_MODE_6368_SPI_SSN4 (1 << 30) + #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) + ++#define GPIO_PINMUX_SEL0_6318 0x1c ++#define GPIO_PINMUX_SEL0_GPIO13_SHIFT 26 ++#define GPIO_PINMUX_SEL0_GPIO13_MASK (0x3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) ++#define GPIO_PINMUX_SEL0_GPIO13_PWRON (1 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) ++#define GPIO_PINMUX_SEL0_GPIO13_LED (2 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) ++#define GPIO_PINMUX_SEL0_GPIO13_GPIO (3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) + + #define GPIO_PINMUX_OTHR_REG 0x24 + #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 +@@ -1118,6 +1124,7 @@ + + #define USBH_PRIV_SWAP_6358_REG 0x0 + #define USBH_PRIV_SWAP_6368_REG 0x1c ++#define USBH_PRIV_SWAP_6318_REG 0x0c + + #define USBH_PRIV_SWAP_USBD_SHIFT 6 + #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) +@@ -1143,6 +1150,13 @@ + #define USBH_PRIV_SETUP_IOC_SHIFT 4 + #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) + ++#define USBH_PRIV_SETUP_6318_REG 0x00 ++#define USBH_PRIV_PLL_CTRL1_6318_REG 0x04 ++#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27) ++#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31) ++#define USBH_PRIV_SIM_CTRL_6318_REG 0x20 ++#define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5) ++ + + /************************************************************************* + * _REG relative to RSET_USBD +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -914,6 +914,15 @@ void __init board_prom_init(void) + } + + bcm_gpio_writel(val, GPIO_MODE_REG); ++ ++#if IS_ENABLED(CONFIG_USB) ++ if (BCMCPU_IS_6318() && (board.has_ehci0 || board.has_ohci0)) { ++ val = bcm_gpio_readl(GPIO_PINMUX_SEL0_6318); ++ val &= ~GPIO_PINMUX_SEL0_GPIO13_MASK; ++ val |= GPIO_PINMUX_SEL0_GPIO13_PWRON; ++ bcm_gpio_writel(val, GPIO_PINMUX_SEL0_6318); ++ } ++#endif + } + + /* +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -22,6 +22,8 @@ config BCM63XX_CPU_6318 + bool "support 6318 CPU" + select SYS_HAS_CPU_BMIPS32_3300 + select HW_HAS_PCI ++ select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6328 + bool "support 6328 CPU" diff --git a/target/linux/brcm63xx/patches-3.13/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch b/target/linux/brcm63xx/patches-3.13/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch new file mode 100644 index 0000000000..90e3655613 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch @@ -0,0 +1,71 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -585,6 +585,9 @@ + #define TIMER_CTL_MONOTONIC_MASK (1 << 30) + #define TIMER_CTL_ENABLE_MASK (1 << 31) + ++/* Clock reset control (63268 only) */ ++#define TIMER_CLK_RST_CTL_REG 0x2c ++#define CLK_RST_CTL_USB_REF_CLK_EN (1 << 18) + + /************************************************************************* + * _REG relative to RSET_WDT +@@ -1666,6 +1669,11 @@ + #define STRAPBUS_63268_FCVO_SHIFT 21 + #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) + ++#define MISC_IDDQ_CTRL_6328_REG 0x48 ++#define MISC_IDDQ_CTRL_63268_REG 0x4c ++ ++#define IDDQ_CTRL_63268_USBH (1 << 4) ++ + #define MISC_STRAPBUS_6328_REG 0x240 + #define STRAPBUS_6328_FCVO_SHIFT 7 + #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -62,6 +62,26 @@ static void bcm_ub_hwclock_set(u32 mask, + bcm_perf_writel(reg, PERF_UB_CKCTL_REG); + } + ++static void bcm_misc_iddq_set(u32 mask, int enable) ++{ ++ u32 offset; ++ u32 reg; ++ ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) ++ offset = MISC_IDDQ_CTRL_6328_REG; ++ else if (BCMCPU_IS_63268()) ++ offset = MISC_IDDQ_CTRL_63268_REG; ++ else ++ return; ++ ++ reg = bcm_misc_readl(offset); ++ if (enable) ++ reg &= ~mask; ++ else ++ reg |= mask; ++ bcm_misc_writel(reg, offset); ++} ++ + /* + * Ethernet MAC "misc" clock: dma clocks and main clock on 6348 + */ +@@ -199,7 +219,17 @@ static void usbh_set(struct clk *clk, in + } else if (BCMCPU_IS_6368()) { + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); + } else if (BCMCPU_IS_63268()) { ++ u32 reg; ++ + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); ++ bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable); ++ bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable); ++ reg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG); ++ if (enable) ++ reg |= CLK_RST_CTL_USB_REF_CLK_EN; ++ else ++ reg &= ~CLK_RST_CTL_USB_REF_CLK_EN; ++ bcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG); + } else { + return; + } diff --git a/target/linux/brcm63xx/patches-3.13/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch b/target/linux/brcm63xx/patches-3.13/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch new file mode 100644 index 0000000000..9884ff6ebb --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch @@ -0,0 +1,117 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -1152,11 +1152,18 @@ + #define USBH_PRIV_SETUP_6368_REG 0x28 + #define USBH_PRIV_SETUP_IOC_SHIFT 4 + #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) ++#define USBH_PRIV_SETUP_IPP_SHIFT 5 ++#define USBH_PRIV_SETUP_IPP_MASK (1 << USBH_PRIV_SETUP_IPP_SHIFT) + + #define USBH_PRIV_SETUP_6318_REG 0x00 ++#define USBH_PRIV_PLL_CTRL1_6368_REG 0x18 + #define USBH_PRIV_PLL_CTRL1_6318_REG 0x04 +-#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27) +-#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31) ++ ++#define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN (1 << 27) ++#define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN (1 << 31) ++#define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN (1 << 9) ++#define USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY (1 << 10) ++ + #define USBH_PRIV_SIM_CTRL_6318_REG 0x20 + #define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -72,6 +72,8 @@ config BCM63XX_CPU_63268 + bool "support 63268 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI ++ select BCM63XX_EHCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -82,7 +82,7 @@ static struct platform_device bcm63xx_eh + int __init bcm63xx_ehci_register(void) + { + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && +- !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) + return 0; + + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); +--- a/arch/mips/bcm63xx/usb-common.c ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -109,9 +109,24 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_63268()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ reg &= ~USBH_PRIV_SETUP_IPP_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG); ++ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN | ++ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY); ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG); + } else if (BCMCPU_IS_6318()) { + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); +@@ -124,7 +139,7 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); +@@ -165,9 +180,24 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_63268()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ reg &= ~USBH_PRIV_SETUP_IPP_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG); ++ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN | ++ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY); ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG); + } else if (BCMCPU_IS_6318()) { + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); +@@ -180,7 +210,7 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); diff --git a/target/linux/brcm63xx/patches-3.13/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch b/target/linux/brcm63xx/patches-3.13/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch new file mode 100644 index 0000000000..43709afd2e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch @@ -0,0 +1,107 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -42,6 +42,7 @@ struct board_info { + + /* USB config */ + struct bcm63xx_usbd_platform_data usbd; ++ unsigned int num_usbh_ports:2; + + /* DSP config */ + struct bcm63xx_dsp_platform_data dsp; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h +@@ -1,6 +1,6 @@ + #ifndef BCM63XX_DEV_USB_EHCI_H_ + #define BCM63XX_DEV_USB_EHCI_H_ + +-int bcm63xx_ehci_register(void); ++int bcm63xx_ehci_register(unsigned int num_ports); + + #endif /* BCM63XX_DEV_USB_EHCI_H_ */ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h +@@ -1,6 +1,6 @@ + #ifndef BCM63XX_DEV_USB_OHCI_H_ + #define BCM63XX_DEV_USB_OHCI_H_ + +-int bcm63xx_ohci_register(void); ++int bcm63xx_ohci_register(unsigned int num_ports); + + #endif /* BCM63XX_DEV_USB_OHCI_H_ */ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -965,6 +965,7 @@ int __init board_register_devices(void) + { + int button_count = 0; + int led_count = 0; ++ int usbh_ports = 0; + + if (board.has_uart0) + bcm63xx_uart_register(0); +@@ -987,14 +988,21 @@ int __init board_register_devices(void) + !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr)) + bcm63xx_enetsw_register(&board.enetsw); + ++ if ((board.has_ohci0 || board.has_ehci0)) { ++ usbh_ports = board.num_usbh_ports; ++ ++ if (!usbh_ports || WARN_ON(usbh_ports > 1 && board.has_usbd)) ++ usbh_ports = 1; ++ } ++ + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + + if (board.has_ehci0) +- bcm63xx_ehci_register(); ++ bcm63xx_ehci_register(usbh_ports); + + if (board.has_ohci0) +- bcm63xx_ohci_register(); ++ bcm63xx_ohci_register(usbh_ports); + + if (board.has_dsp) + bcm63xx_dsp_register(&board.dsp); +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -79,12 +79,14 @@ static struct platform_device bcm63xx_eh + }, + }; + +-int __init bcm63xx_ehci_register(void) ++int __init bcm63xx_ehci_register(unsigned int num_ports) + { + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && + !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) + return 0; + ++ bcm63xx_ehci_pdata.num_ports = num_ports; ++ + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); + ehci_resources[0].end = ehci_resources[0].start; + ehci_resources[0].end += RSET_EHCI_SIZE - 1; +--- a/arch/mips/bcm63xx/dev-usb-ohci.c ++++ b/arch/mips/bcm63xx/dev-usb-ohci.c +@@ -62,7 +62,6 @@ static struct usb_ohci_pdata bcm63xx_ohc + .big_endian_desc = 1, + .big_endian_mmio = 1, + .no_big_frame_no = 1, +- .num_ports = 1, + .power_on = bcm63xx_ohci_power_on, + .power_off = bcm63xx_ohci_power_off, + .power_suspend = bcm63xx_ohci_power_off, +@@ -80,11 +79,13 @@ static struct platform_device bcm63xx_oh + }, + }; + +-int __init bcm63xx_ohci_register(void) ++int __init bcm63xx_ohci_register(unsigned int num_ports) + { + if (BCMCPU_IS_6345() || BCMCPU_IS_6338()) + return -ENODEV; + ++ bcm63xx_ohci_pdata.num_ports = num_ports; ++ + ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0); + ohci_resources[0].end = ohci_resources[0].start; + ohci_resources[0].end += RSET_OHCI_SIZE - 1; diff --git a/target/linux/brcm63xx/patches-3.13/351-set-board-usbh-ports.patch b/target/linux/brcm63xx/patches-3.13/351-set-board-usbh-ports.patch new file mode 100644 index 0000000000..e007ddd272 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/351-set-board-usbh-ports.patch @@ -0,0 +1,10 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -634,6 +634,7 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, ++ .num_usbh_ports = 2, + + .leds = { + { diff --git a/target/linux/brcm63xx/patches-3.13/400-bcm963xx_flashmap.patch b/target/linux/brcm63xx/patches-3.13/400-bcm963xx_flashmap.patch new file mode 100644 index 0000000000..1594a063aa --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/400-bcm963xx_flashmap.patch @@ -0,0 +1,65 @@ +From a4d005c91d403d9f3d0272db6cc46202c06ec774 Mon Sep 17 00:00:00 2001 +From: Axel Gembe <ago@bastart.eu.org> +Date: Mon, 12 May 2008 18:54:09 +0200 +Subject: [PATCH] bcm963xx: flashmap support + +Signed-off-by: Axel Gembe <ago@bastart.eu.org> +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 19 +---------------- + drivers/mtd/maps/bcm963xx-flash.c | 32 ++++++++++++++++++++++++---- + drivers/mtd/redboot.c | 13 +++++++++-- + 3 files changed, 38 insertions(+), 26 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -32,7 +32,7 @@ static struct mtd_partition mtd_partitio + } + }; + +-static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL }; ++static const char *bcm63xx_part_types[] = { "bcm63xxpart", "RedBoot", NULL }; + + static struct physmap_flash_data flash_data = { + .width = 2, +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -72,6 +72,7 @@ static int parse_redboot_partitions(stru + int nulllen = 0; + int numslots; + unsigned long offset; ++ unsigned long fis_origin = 0; + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; + #endif +@@ -176,6 +177,16 @@ static int parse_redboot_partitions(stru + goto out; + } + ++ if (data && data->origin) { ++ fis_origin = data->origin; ++ } else { ++ for (i = 0; i < numslots; i++) { ++ if (!strncmp(buf[i].name, "RedBoot", 8)) { ++ fis_origin = ((buf[i].flash_base & (master->size << 1)) - 1); ++ } ++ } ++ } ++ + for (i = 0; i < numslots; i++) { + struct fis_list *new_fl, **prev; + +@@ -196,10 +207,10 @@ static int parse_redboot_partitions(stru + goto out; + } + new_fl->img = &buf[i]; +- if (data && data->origin) +- buf[i].flash_base -= data->origin; +- else +- buf[i].flash_base &= master->size-1; ++ if (fis_origin) ++ buf[i].flash_base -= fis_origin; ++ ++ buf[i].flash_base &= (master->size << 1) - 1; + + /* I'm sure the JFFS2 code has done me permanent damage. + * I now think the following is _normal_ diff --git a/target/linux/brcm63xx/patches-3.13/401-bcm963xx_real_rootfs_length.patch b/target/linux/brcm63xx/patches-3.13/401-bcm963xx_real_rootfs_length.patch new file mode 100644 index 0000000000..caf8b9514d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/401-bcm963xx_real_rootfs_length.patch @@ -0,0 +1,27 @@ +--- a/include/uapi/linux/bcm963xx_tag.h ++++ b/include/uapi/linux/bcm963xx_tag.h +@@ -85,8 +85,10 @@ struct bcm_tag { + __u32 rootfs_crc; + /* 224-227: CRC32 of kernel partition */ + __u32 kernel_crc; +- /* 228-235: Unused at present */ +- char reserved1[8]; ++ /* 228-231: Image sequence number */ ++ char image_sequence[4]; ++ /* 222-235: Openwrt: real rootfs length */ ++ __u32 real_rootfs_length; + /* 236-239: CRC32 of header excluding last 20 bytes */ + __u32 header_crc; + /* 240-255: Unused at present */ +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -110,7 +110,8 @@ static int bcm63xx_parse_cfe_partitions( + } else { + /* OpenWrt layout */ + rootfsaddr = kerneladdr + kernellen; +- rootfslen = spareaddr - rootfsaddr; ++ rootfslen = buf->real_rootfs_length; ++ spareaddr = rootfsaddr + rootfslen; + } + } else { + pr_warn("CFE boot tag CRC invalid (expected %08x, actual %08x)\n", diff --git a/target/linux/brcm63xx/patches-3.13/402_bcm63xx_enet_vlan_incoming_fixed.patch b/target/linux/brcm63xx/patches-3.13/402_bcm63xx_enet_vlan_incoming_fixed.patch new file mode 100644 index 0000000000..fc2e8ab7a7 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/402_bcm63xx_enet_vlan_incoming_fixed.patch @@ -0,0 +1,11 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -1633,7 +1633,7 @@ static int compute_hw_mtu(struct bcm_ene + actual_mtu = mtu; + + /* add ethernet header + vlan tag size */ +- actual_mtu += VLAN_ETH_HLEN; ++ actual_mtu += VLAN_ETH_HLEN + VLAN_HLEN; + + if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU) + return -EINVAL; diff --git a/target/linux/brcm63xx/patches-3.13/403-6358-enet1-external-mii-clk.patch b/target/linux/brcm63xx/patches-3.13/403-6358-enet1-external-mii-clk.patch new file mode 100644 index 0000000000..6f4f8d926e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/403-6358-enet1-external-mii-clk.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -912,6 +912,8 @@ void __init board_prom_init(void) + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G3_EXT_MII | + GPIO_MODE_6348_G0_EXT_MII; ++ else if (BCMCPU_IS_6358()) ++ val |= GPIO_MODE_6358_ENET1_MII_CLK_INV; + } + + bcm_gpio_writel(val, GPIO_MODE_REG); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -770,6 +770,8 @@ + #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) + #define GPIO_MODE_6358_SERIAL_LED (1 << 10) + #define GPIO_MODE_6358_UTOPIA (1 << 12) ++#define GPIO_MODE_6358_ENET1_MII_CLK_INV (1 << 30) ++#define GPIO_MODE_6358_ENET0_MII_CLK_INV (1 << 31) + + #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0) + #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1) diff --git a/target/linux/brcm63xx/patches-3.13/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch b/target/linux/brcm63xx/patches-3.13/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch new file mode 100644 index 0000000000..d8405f58a0 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch @@ -0,0 +1,169 @@ +From b11218c750ab92cfab4408a0328f1b36ceec3f33 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Fri, 6 Jan 2012 12:24:18 +0100 +Subject: [PATCH 19/63] NET: bcm63xx_enet: move phy_(dis)connect into probe/remove + +Only connect/disconnect the phy during probe and remove, not during any +open/close. The phy seldom changes during the runtime, and disconnecting +the phy during close will prevent it from keeping any configuration over +a down/up cycle. + +Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> +--- + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 84 +++++++++++++------------- + 1 files changed, 41 insertions(+), 43 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -870,10 +870,8 @@ static int bcm_enet_open(struct net_devi + struct bcm_enet_priv *priv; + struct sockaddr addr; + struct device *kdev; +- struct phy_device *phydev; + int i, ret; + unsigned int size; +- char phy_id[MII_BUS_ID_SIZE + 3]; + void *p; + u32 val; + +@@ -881,40 +879,10 @@ static int bcm_enet_open(struct net_devi + kdev = &priv->pdev->dev; + + if (priv->has_phy) { +- /* connect to PHY */ +- snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, +- priv->mii_bus->id, priv->phy_id); +- +- phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, +- PHY_INTERFACE_MODE_MII); +- +- if (IS_ERR(phydev)) { +- dev_err(kdev, "could not attach to PHY\n"); +- return PTR_ERR(phydev); +- } +- +- /* mask with MAC supported features */ +- phydev->supported &= (SUPPORTED_10baseT_Half | +- SUPPORTED_10baseT_Full | +- SUPPORTED_100baseT_Half | +- SUPPORTED_100baseT_Full | +- SUPPORTED_Autoneg | +- SUPPORTED_Pause | +- SUPPORTED_MII); +- phydev->advertising = phydev->supported; +- +- if (priv->pause_auto && priv->pause_rx && priv->pause_tx) +- phydev->advertising |= SUPPORTED_Pause; +- else +- phydev->advertising &= ~SUPPORTED_Pause; +- +- dev_info(kdev, "attached PHY at address %d [%s]\n", +- phydev->addr, phydev->drv->name); +- ++ /* Reset state */ + priv->old_link = 0; + priv->old_duplex = -1; + priv->old_pause = -1; +- priv->phydev = phydev; + } + + /* mask all interrupts and request them */ +@@ -924,7 +892,7 @@ static int bcm_enet_open(struct net_devi + + ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev); + if (ret) +- goto out_phy_disconnect; ++ return ret; + + ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0, + dev->name, dev); +@@ -1127,9 +1095,6 @@ out_freeirq_rx: + out_freeirq: + free_irq(dev->irq, dev); + +-out_phy_disconnect: +- phy_disconnect(priv->phydev); +- + return ret; + } + +@@ -1234,12 +1199,6 @@ static int bcm_enet_stop(struct net_devi + free_irq(priv->irq_rx, dev); + free_irq(dev->irq, dev); + +- /* release phy */ +- if (priv->has_phy) { +- phy_disconnect(priv->phydev); +- priv->phydev = NULL; +- } +- + return 0; + } + +@@ -1834,6 +1793,8 @@ static int bcm_enet_probe(struct platfor + + /* MII bus registration */ + if (priv->has_phy) { ++ struct phy_device *phydev; ++ char phy_id[MII_BUS_ID_SIZE + 3]; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { +@@ -1871,6 +1832,38 @@ static int bcm_enet_probe(struct platfor + dev_err(&pdev->dev, "unable to register mdio bus\n"); + goto out_free_mdio; + } ++ ++ /* connect to PHY */ ++ snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, ++ priv->mii_bus->id, priv->phy_id); ++ ++ phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, ++ PHY_INTERFACE_MODE_MII); ++ ++ if (IS_ERR(phydev)) { ++ dev_err(&pdev->dev, "could not attach to PHY\n"); ++ goto out_unregister_mdio; ++ } ++ ++ /* mask with MAC supported features */ ++ phydev->supported &= (SUPPORTED_10baseT_Half | ++ SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | ++ SUPPORTED_100baseT_Full | ++ SUPPORTED_Autoneg | ++ SUPPORTED_Pause | ++ SUPPORTED_MII); ++ phydev->advertising = phydev->supported; ++ ++ if (priv->pause_auto && priv->pause_rx && priv->pause_tx) ++ phydev->advertising |= SUPPORTED_Pause; ++ else ++ phydev->advertising &= ~SUPPORTED_Pause; ++ ++ dev_info(&pdev->dev, "attached PHY at address %d [%s]\n", ++ phydev->addr, phydev->drv->name); ++ ++ priv->phydev = phydev; + } else { + + /* run platform code to initialize PHY device */ +@@ -1916,6 +1909,9 @@ static int bcm_enet_probe(struct platfor + return 0; + + out_unregister_mdio: ++ if (priv->phydev) ++ phy_disconnect(priv->phydev); ++ + if (priv->mii_bus) + mdiobus_unregister(priv->mii_bus); + +@@ -1957,6 +1953,8 @@ static int bcm_enet_remove(struct platfo + enet_writel(priv, 0, ENET_MIISC_REG); + + if (priv->has_phy) { ++ phy_disconnect(priv->phydev); ++ priv->phydev = NULL; + mdiobus_unregister(priv->mii_bus); + mdiobus_free(priv->mii_bus); + } else { diff --git a/target/linux/brcm63xx/patches-3.13/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch b/target/linux/brcm63xx/patches-3.13/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch new file mode 100644 index 0000000000..75890920f7 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch @@ -0,0 +1,53 @@ +From d8237d704fc25eb2fc25ef4403608b78c6a6d4be Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Sun, 15 Jul 2012 20:08:57 +0200 +Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports + +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 13 +++++++++++++ + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 12 ++++++++++++ + 2 files changed, 25 insertions(+), 0 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -1086,6 +1086,19 @@ + #define ENETSW_PORTOV_FDX_MASK (1 << 1) + #define ENETSW_PORTOV_LINKUP_MASK (1 << 0) + ++/* Port RGMII control register */ ++#define ENETSW_RGMII_CTRL_REG(x) (0x60 + (x)) ++#define ENETSW_RGMII_CTRL_GMII_CLK_EN (1 << 7) ++#define ENETSW_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6) ++#define ENETSW_RGMII_CTRL_MII_MODE_MASK (3 << 4) ++#define ENETSW_RGMII_CTRL_RGMII_MODE (0 << 4) ++#define ENETSW_RGMII_CTRL_MII_MODE (1 << 4) ++#define ENETSW_RGMII_CTRL_RVMII_MODE (2 << 4) ++#define ENETSW_RGMII_CTRL_TIMING_SEL_EN (1 << 0) ++ ++/* Port RGMII timing register */ ++#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x)) ++ + /* MDIO control register */ + #define ENETSW_MDIOC_REG (0xb0) + #define ENETSW_MDIOC_EXT_MASK (1 << 16) +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2228,6 +2228,18 @@ static int bcm_enetsw_open(struct net_de + priv->sw_port_link[i] = 0; + } + ++ /* enable external ports */ ++ for (i = ENETSW_RGMII_PORT0; i < priv->num_ports; i++) { ++ u8 rgmii_ctrl; ++ ++ if (!priv->used_ports[i].used) ++ continue; ++ ++ rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i)); ++ rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN; ++ enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); ++ } ++ + /* reset mib */ + val = enetsw_readb(priv, ENETSW_GMCR_REG); + val |= ENETSW_GMCR_RST_MIB_MASK; diff --git a/target/linux/brcm63xx/patches-3.13/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch b/target/linux/brcm63xx/patches-3.13/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch new file mode 100644 index 0000000000..76a8754ec5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch @@ -0,0 +1,133 @@ +From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Sun, 3 Jul 2011 15:00:38 +0200 +Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present + +Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> +--- + arch/mips/bcm63xx/dev-flash.c | 33 +++++++++++++++++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 + + 2 files changed, 33 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -16,9 +16,12 @@ + #include <linux/mtd/mtd.h> + #include <linux/mtd/partitions.h> + #include <linux/mtd/physmap.h> ++#include <linux/spi/spi.h> ++#include <linux/spi/flash.h> + + #include <bcm63xx_cpu.h> + #include <bcm63xx_dev_flash.h> ++#include <bcm63xx_dev_hsspi.h> + #include <bcm63xx_regs.h> + #include <bcm63xx_io.h> + +@@ -57,6 +60,21 @@ static struct platform_device mtd_dev = + }, + }; + ++static struct flash_platform_data bcm63xx_flash_data = { ++ .part_probe_types = bcm63xx_part_types, ++}; ++ ++static struct spi_board_info bcm63xx_spi_flash_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .mode = 0, ++ .max_speed_hz = 781000, ++ .modalias = "m25p80", ++ .platform_data = &bcm63xx_flash_data, ++ }, ++}; ++ + static int __init bcm63xx_detect_flash_type(void) + { + u32 val; +@@ -64,9 +82,15 @@ static int __init bcm63xx_detect_flash_t + switch (bcm63xx_get_cpu_id()) { + case BCM6318_CPU_ID: + /* only support serial flash */ ++ bcm63xx_spi_flash_info[0].max_speed_hz = 62500000; + return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6328_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); ++ if (val & STRAPBUS_6328_HSSPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 33333334; ++ else ++ bcm63xx_spi_flash_info[0].max_speed_hz = 16666667; ++ + if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else +@@ -85,12 +109,20 @@ static int __init bcm63xx_detect_flash_t + return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6362_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6362_REG); ++ if (val & STRAPBUS_6362_HSSPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 50000000; ++ else ++ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; ++ + if (val & STRAPBUS_6362_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else + return BCM63XX_FLASH_TYPE_NAND; + case BCM6368_CPU_ID: + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); ++ if (val & STRAPBUS_6368_SPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; ++ + switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { + case STRAPBUS_6368_BOOT_SEL_NAND: + return BCM63XX_FLASH_TYPE_NAND; +@@ -101,6 +133,11 @@ static int __init bcm63xx_detect_flash_t + } + case BCM63268_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_63268_REG); ++ if (val & STRAPBUS_63268_HSSPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 50000000; ++ else ++ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; ++ + if (val & STRAPBUS_63268_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else +@@ -167,8 +204,15 @@ int __init bcm63xx_flash_register(void) + + return platform_device_register(&mtd_dev); + case BCM63XX_FLASH_TYPE_SERIAL: +- pr_warn("unsupported serial flash detected\n"); +- return -ENODEV; ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || ++ BCMCPU_IS_63268()) ++ bcm63xx_spi_flash_info[0].bus_num = 1; ++ ++ if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) ++ bcm63xx_flash_data.max_transfer_len = SPI_6358_MSG_DATA_SIZE; ++ ++ return spi_register_board_info(bcm63xx_spi_flash_info, ++ ARRAY_SIZE(bcm63xx_spi_flash_info)); + case BCM63XX_FLASH_TYPE_NAND: + pr_warn("unsupported NAND flash detected\n"); + return -ENODEV; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -827,6 +827,7 @@ + #define GPIO_STRAPBUS_REG 0x40 + #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) + #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) ++#define STRAPBUS_6368_SPI_CLK_FAST (1 << 6) + #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 + #define STRAPBUS_6368_BOOT_SEL_NAND 0 + #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 +@@ -1697,6 +1698,7 @@ + #define IDDQ_CTRL_63268_USBH (1 << 4) + + #define MISC_STRAPBUS_6328_REG 0x240 ++#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4) + #define STRAPBUS_6328_FCVO_SHIFT 7 + #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) + #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) diff --git a/target/linux/brcm63xx/patches-3.13/412-MTD-physmap-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-3.13/412-MTD-physmap-allow-passing-pp_data.patch new file mode 100644 index 0000000000..3511120468 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/412-MTD-physmap-allow-passing-pp_data.patch @@ -0,0 +1,41 @@ +From 266c506f4b262bd6aba0776a03d82c98e65d9906 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Tue, 1 May 2012 17:32:36 +0200 +Subject: [PATCH 63/79] MTD: physmap: allow passing pp_data + +--- + drivers/mtd/maps/physmap.c | 4 +++- + include/linux/mtd/physmap.h | 1 + + 2 files changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/maps/physmap.c ++++ b/drivers/mtd/maps/physmap.c +@@ -96,6 +96,7 @@ static int physmap_flash_probe(struct pl + { + struct physmap_flash_data *physmap_data; + struct physmap_flash_info *info; ++ struct mtd_part_parser_data *pp_data; + const char * const *probe_type; + const char * const *part_types; + int err = 0; +@@ -187,8 +188,9 @@ static int physmap_flash_probe(struct pl + spin_lock_init(&info->vpp_lock); + + part_types = physmap_data->part_probe_types ? : part_probe_types; ++ pp_data = physmap_data->pp_data ? physmap_data->pp_data : NULL; + +- mtd_device_parse_register(info->cmtd, part_types, NULL, ++ mtd_device_parse_register(info->cmtd, part_types, pp_data, + physmap_data->parts, physmap_data->nr_parts); + return 0; + +--- a/include/linux/mtd/physmap.h ++++ b/include/linux/mtd/physmap.h +@@ -31,6 +31,7 @@ struct physmap_flash_data { + char *probe_type; + struct mtd_partition *parts; + const char * const *part_probe_types; ++ struct mtd_part_parser_data *pp_data; + }; + + #endif /* __LINUX_MTD_PHYSMAP__ */ diff --git a/target/linux/brcm63xx/patches-3.13/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch b/target/linux/brcm63xx/patches-3.13/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch new file mode 100644 index 0000000000..7991fad0e3 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch @@ -0,0 +1,81 @@ +From 8879e209111192c5e9752d7bd203cf7582693328 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Thu, 3 May 2012 14:40:03 +0200 +Subject: [PATCH 58/72] BCM63XX: allow providing fixup data in board data + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 9 ++++++++- + arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 10 ++++++++++ + 2 files changed, 18 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -33,6 +33,7 @@ + #include <bcm63xx_dev_usb_ohci.h> + #include <bcm63xx_dev_usb_usbd.h> + #include <board_bcm963xx.h> ++#include <pci_ath9k_fixup.h> + + #include <uapi/linux/bcm933xx_hcs.h> + #include <uapi/linux/bcm963xx_tag.h> +@@ -969,6 +970,7 @@ int __init board_register_devices(void) + int button_count = 0; + int led_count = 0; + int usbh_ports = 0; ++ int i; + + if (board.has_uart0) + bcm63xx_uart_register(0); +@@ -1014,7 +1016,8 @@ int __init board_register_devices(void) + * do this after registering enet devices + */ + #ifdef CONFIG_SSB_PCIHOST +- if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) { ++ if (!board.has_caldata && ++ !bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) { + memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); + if (ssb_arch_register_fallback_sprom( +@@ -1061,5 +1064,9 @@ int __init board_register_devices(void) + platform_device_register(&bcm63xx_gpio_keys_device); + } + ++ /* register any fixups */ ++ for (i = 0; i < board.has_caldata; i++) ++ pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset); ++ + return 0; + } +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -8,6 +8,7 @@ + #include <bcm63xx_dev_enet.h> + #include <bcm63xx_dev_usb_usbd.h> + #include <bcm63xx_dev_dsp.h> ++#include <pci_ath9k_fixup.h> + + /* + * flash mapping +@@ -15,6 +16,11 @@ + #define BCM963XX_CFE_VERSION_OFFSET 0x570 + #define BCM963XX_NVRAM_OFFSET 0x580 + ++struct ath9k_caldata { ++ unsigned int slot; ++ u32 caldata_offset; ++}; ++ + /* + * board definition + */ +@@ -34,6 +40,10 @@ struct board_info { + unsigned int has_dsp:1; + unsigned int has_uart0:1; + unsigned int has_uart1:1; ++ unsigned int has_caldata:2; ++ ++ /* wifi calibration data config */ ++ struct ath9k_caldata caldata[2]; + + /* ethernet config */ + struct bcm63xx_enet_platform_data enet0; diff --git a/target/linux/brcm63xx/patches-3.13/414-MTD-m25p80-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-3.13/414-MTD-m25p80-allow-passing-pp_data.patch new file mode 100644 index 0000000000..55bb37f51b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/414-MTD-m25p80-allow-passing-pp_data.patch @@ -0,0 +1,40 @@ +From 7f17dfe9009beb07a3de0e380932a725293829df Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Tue, 1 May 2012 17:33:03 +0200 +Subject: [PATCH 64/79] MTD: m25p80: allow passing pp_data + +--- + drivers/mtd/devices/m25p80.c | 3 +++ + include/linux/spi/flash.h | 2 ++ + 2 files changed, 5 insertions(+) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -992,6 +992,9 @@ static int m25p_probe(struct spi_device + dev_warn(&spi->dev, "unrecognized id %s\n", data->type); + } + ++ if (data && data->pp_data) ++ memcpy(&ppdata, data->pp_data, sizeof(ppdata)); ++ + info = (void *)id->driver_data; + + if (info->jedec_id) { +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -12,6 +12,7 @@ struct mtd_part_parser_data; + * with chips that can't be queried for JEDEC or other IDs + * @part_probe_types: optional list of MTD parser names to use for + * partitioning ++ * @pp_data: optional partition parser data. + * + * @max_transfer_len: option maximum read/write length limitation for + * SPI controllers not able to transfer any length commands. +@@ -30,6 +31,7 @@ struct flash_platform_data { + char *type; + + const char **part_probe_types; ++ struct mtd_part_parser_data *pp_data; + + unsigned int max_transfer_len; + /* we'll likely add more ... use JEDEC IDs, etc */ diff --git a/target/linux/brcm63xx/patches-3.13/415-MIPS-BCM63XX-export-the-attached-flash-type.patch b/target/linux/brcm63xx/patches-3.13/415-MIPS-BCM63XX-export-the-attached-flash-type.patch new file mode 100644 index 0000000000..bde8961ea2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/415-MIPS-BCM63XX-export-the-attached-flash-type.patch @@ -0,0 +1,31 @@ +From 066f1e37742ee434496d32a41a9284458de96742 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Mon, 13 Jan 2014 12:12:30 +0100 +Subject: [PATCH] MIPS: BCM63XX: export the attached flash type + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/dev-flash.c | 5 +++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 ++ + 2 files changed, 7 insertions(+) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -222,3 +222,8 @@ int __init bcm63xx_flash_register(void) + return -ENODEV; + } + } ++ ++int bcm63xx_flash_get_type(void) ++{ ++ return flash_type; ++} +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -11,4 +11,6 @@ void bcm63xx_flash_detect(void); + + int __init bcm63xx_flash_register(void); + ++int bcm63xx_flash_get_type(void); ++ + #endif /* __BCM63XX_FLASH_H */ diff --git a/target/linux/brcm63xx/patches-3.13/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch b/target/linux/brcm63xx/patches-3.13/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch new file mode 100644 index 0000000000..af06428565 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch @@ -0,0 +1,229 @@ +From bbebbf735a02b6d044ed928978ab4bd5f1833364 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Thu, 3 May 2012 14:36:11 +0200 +Subject: [PATCH 61/72] BCM63XX: add a fixup for ath9k devices + +--- + arch/mips/bcm63xx/Makefile | 3 +- + arch/mips/bcm63xx/pci-ath9k-fixup.c | 190 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/pci_ath9k_fixup.h | 7 + + 3 files changed, 199 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/pci-ath9k-fixup.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -2,7 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ + dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ +- usb-common.o ++ pci-ath9k-fixup.o usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c +@@ -0,0 +1,192 @@ ++/* ++ * Broadcom BCM63XX Ath9k EEPROM fixup helper. ++ * ++ * Copytight (C) 2012 Jonas Gorski <jonas.gorski@gmail.com> ++ * ++ * Based on ++ * ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include <linux/pci.h> ++#include <linux/delay.h> ++#include <linux/ath9k_platform.h> ++ ++#include <bcm63xx_cpu.h> ++#include <bcm63xx_io.h> ++#include <bcm63xx_nvram.h> ++#include <bcm63xx_dev_pci.h> ++#include <bcm63xx_dev_flash.h> ++#include <bcm63xx_dev_hsspi.h> ++#include <pci_ath9k_fixup.h> ++ ++#define bcm_hsspi_writel(v, o) bcm_rset_writel(RSET_HSSPI, (v), (o)) ++ ++struct ath9k_fixup { ++ unsigned slot; ++ u8 mac[ETH_ALEN]; ++ struct ath9k_platform_data pdata; ++}; ++ ++static int ath9k_num_fixups; ++static struct ath9k_fixup ath9k_fixups[2] = { ++ { ++ .slot = 255, ++ .pdata = { ++ .led_pin = -1, ++ }, ++ }, ++ { ++ .slot = 255, ++ .pdata = { ++ .led_pin = -1, ++ }, ++ }, ++}; ++ ++static u16 *bcm63xx_read_eeprom(u16 *eeprom, u32 offset) ++{ ++ u32 addr; ++ ++ if (BCMCPU_IS_6328()) { ++ addr = 0x18000000; ++ } else { ++ addr = bcm_mpi_readl(MPI_CSBASE_REG(0)); ++ addr &= MPI_CSBASE_BASE_MASK; ++ } ++ ++ switch (bcm63xx_flash_get_type()) { ++ case BCM63XX_FLASH_TYPE_PARALLEL: ++ memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); ++ return eeprom; ++ case BCM63XX_FLASH_TYPE_SERIAL: ++ /* the first megabyte is memory mapped */ ++ if (offset < 0x100000) { ++ memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); ++ return eeprom; ++ } ++ ++ if (BCMCPU_IS_6328()) { ++ /* we can change the memory mapped megabyte */ ++ bcm_hsspi_writel(offset & 0xf00000, 0x18); ++ memcpy(eeprom, (void *)KSEG1ADDR(addr + (offset & 0xfffff)), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); ++ bcm_hsspi_writel(0, 0x18); ++ return eeprom; ++ } ++ /* can't do anything here without talking to the SPI controller. */ ++ case BCM63XX_FLASH_TYPE_NAND: ++ default: ++ return NULL; ++ } ++} ++ ++static void ath9k_pci_fixup(struct pci_dev *dev) ++{ ++ void __iomem *mem; ++ struct ath9k_platform_data *pdata = NULL; ++ u16 *cal_data = NULL; ++ u16 cmd; ++ u32 bar0; ++ u32 val; ++ unsigned i; ++ ++ for (i = 0; i < ath9k_num_fixups; i++) { ++ if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn)) ++ continue; ++ ++ cal_data = ath9k_fixups[i].pdata.eeprom_data; ++ pdata = &ath9k_fixups[i].pdata; ++ break; ++ } ++ ++ if (cal_data == NULL) ++ return; ++ ++ if (*cal_data != 0xa55a) { ++ pr_err("pci %s: invalid calibration data\n", pci_name(dev)); ++ return; ++ } ++ ++ pr_info("pci %s: fixup device configuration\n", pci_name(dev)); ++ ++ switch (bcm63xx_get_cpu_id()) { ++ case BCM6328_CPU_ID: ++ val = BCM_PCIE_MEM_BASE_PA_6328; ++ break; ++ case BCM6348_CPU_ID: ++ case BCM6358_CPU_ID: ++ case BCM6368_CPU_ID: ++ val = BCM_PCI_MEM_BASE_PA; ++ break; ++ default: ++ BUG(); ++ } ++ ++ mem = ioremap(val, 0x10000); ++ if (!mem) { ++ pr_err("pci %s: ioremap error\n", pci_name(dev)); ++ return; ++ } ++ ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, val); ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ /* set offset to first reg address */ ++ cal_data += 3; ++ while(*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; ++ ++ writel(val, mem + reg); ++ udelay(100); ++ } ++ ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; ++ ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); ++ ++ iounmap(mem); ++ ++ dev->dev.platform_data = pdata; ++} ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); ++ ++void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset) ++{ ++ if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) ++ return; ++ ++ ath9k_fixups[ath9k_num_fixups].slot = slot; ++ ++ if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) ++ return; ++ ++ if (bcm63xx_nvram_get_mac_address(ath9k_fixups[ath9k_num_fixups].mac)) ++ return; ++ ++ ath9k_fixups[ath9k_num_fixups].pdata.macaddr = ath9k_fixups[ath9k_num_fixups].mac; ++ ath9k_num_fixups++; ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h +@@ -0,0 +1,7 @@ ++#ifndef _PCI_ATH9K_FIXUP ++#define _PCI_ATH9K_FIXUP ++ ++ ++void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init; ++ ++#endif /* _PCI_ATH9K_FIXUP */ diff --git a/target/linux/brcm63xx/patches-3.13/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch b/target/linux/brcm63xx/patches-3.13/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch new file mode 100644 index 0000000000..3b02c072cd --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch @@ -0,0 +1,120 @@ +Allow bcm63xxpart to receive a caldata offset if calibration data is +contained in flash. +--- + drivers/mtd/bcm63xxpart.c | 51 ++++++++++++++++++++++++++++++++++++--- + include/linux/mtd/partitions.h | 2 + + 2 files changed, 49 insertions(+), 4 deletions(-) + +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -53,10 +53,12 @@ static int bcm63xx_parse_cfe_partitions( + struct mtd_partition *parts; + int ret; + size_t retlen; +- unsigned int rootfsaddr, kerneladdr, spareaddr; ++ unsigned int rootfsaddr, kerneladdr, spareaddr, nvramaddr; + unsigned int rootfslen, kernellen, sparelen, totallen; + unsigned int cfelen, nvramlen; + unsigned int cfe_erasesize; ++ unsigned int caldatalen1 = 0, caldataaddr1 = 0; ++ unsigned int caldatalen2 = 0, caldataaddr2 = 0; + int i; + u32 computed_crc; + bool rootfs_first = false; +@@ -70,6 +72,24 @@ static int bcm63xx_parse_cfe_partitions( + cfelen = cfe_erasesize; + nvramlen = bcm63xx_nvram_get_psi_size() * SZ_1K; + nvramlen = roundup(nvramlen, cfe_erasesize); ++ nvramaddr = master->size - nvramlen; ++ ++ if (data) { ++ if (data->caldata[0]) { ++ caldatalen1 = cfe_erasesize; ++ caldataaddr1 = rounddown(data->caldata[0], ++ cfe_erasesize); ++ } ++ if (data->caldata[1]) { ++ caldatalen2 = cfe_erasesize; ++ caldataaddr2 = rounddown(data->caldata[1], ++ cfe_erasesize); ++ } ++ if (caldataaddr1 == caldataaddr2) { ++ caldataaddr2 = 0; ++ caldatalen2 = 0; ++ } ++ } + + /* Allocate memory for buffer */ + buf = vmalloc(sizeof(struct bcm_tag)); +@@ -121,7 +141,7 @@ static int bcm63xx_parse_cfe_partitions( + rootfsaddr = 0; + spareaddr = cfelen; + } +- sparelen = master->size - spareaddr - nvramlen; ++ sparelen = min_not_zero(nvramaddr, caldataaddr1) - spareaddr; + + /* Determine number of partitions */ + if (rootfslen > 0) +@@ -130,6 +150,12 @@ static int bcm63xx_parse_cfe_partitions( + if (kernellen > 0) + nrparts++; + ++ if (caldatalen1 > 0) ++ nrparts++; ++ ++ if (caldatalen2 > 0) ++ nrparts++; ++ + /* Ask kernel for more memory */ + parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL); + if (!parts) { +@@ -167,15 +193,32 @@ static int bcm63xx_parse_cfe_partitions( + curpart++; + } + ++ if (caldatalen1 > 0) { ++ if (caldatalen2 > 0) ++ parts[curpart].name = "cal_data1"; ++ else ++ parts[curpart].name = "cal_data"; ++ parts[curpart].offset = caldataaddr1; ++ parts[curpart].size = caldatalen1; ++ curpart++; ++ } ++ ++ if (caldatalen2 > 0) { ++ parts[curpart].name = "cal_data2"; ++ parts[curpart].offset = caldataaddr2; ++ parts[curpart].size = caldatalen2; ++ curpart++; ++ } ++ + parts[curpart].name = "nvram"; +- parts[curpart].offset = master->size - nvramlen; ++ parts[curpart].offset = nvramaddr; + parts[curpart].size = nvramlen; + curpart++; + + /* Global partition "linux" to make easy firmware upgrade */ + parts[curpart].name = "linux"; + parts[curpart].offset = cfelen; +- parts[curpart].size = master->size - cfelen - nvramlen; ++ parts[curpart].size = min_not_zero(nvramaddr, caldataaddr1) - cfelen; + + for (i = 0; i < nrparts; i++) + pr_info("Partition %d is %s offset %llx and length %llx\n", i, +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -56,10 +56,12 @@ struct device_node; + /** + * struct mtd_part_parser_data - used to pass data to MTD partition parsers. + * @origin: for RedBoot, start address of MTD device ++ * @caldata: for CFE, start address of wifi calibration data + * @of_node: for OF parsers, device node containing partitioning information + */ + struct mtd_part_parser_data { + unsigned long origin; ++ unsigned long caldata[2]; + struct device_node *of_node; + }; + diff --git a/target/linux/brcm63xx/patches-3.13/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch b/target/linux/brcm63xx/patches-3.13/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch new file mode 100644 index 0000000000..6f913dd073 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch @@ -0,0 +1,83 @@ +From 977f8a30103b9c4992cab8f49357fe0d4274004f Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Thu, 3 May 2012 14:55:26 +0200 +Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/dev-flash.c | 9 ++++++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 4 +++- + 3 files changed, 12 insertions(+), 3 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1036,7 +1036,7 @@ int __init board_register_devices(void) + if (board.num_spis) + spi_register_board_info(board.spis, board.num_spis); + +- bcm63xx_flash_register(); ++ bcm63xx_flash_register(board.has_caldata, board.caldata); + + /* count number of LEDs defined by this device */ + while (led_count < ARRAY_SIZE(board.leds) && board.leds[led_count].name) +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -35,12 +35,15 @@ static struct mtd_partition mtd_partitio + } + }; + ++static struct mtd_part_parser_data bcm63xx_parser_data; ++ + static const char *bcm63xx_part_types[] = { "bcm63xxpart", "RedBoot", NULL }; + + static struct physmap_flash_data flash_data = { + .width = 2, + .parts = mtd_partitions, + .part_probe_types = bcm63xx_part_types, ++ .pp_data = &bcm63xx_parser_data, + }; + + static struct resource mtd_resources[] = { +@@ -62,6 +65,7 @@ static struct platform_device mtd_dev = + + static struct flash_platform_data bcm63xx_flash_data = { + .part_probe_types = bcm63xx_part_types, ++ .pp_data = &bcm63xx_parser_data, + }; + + static struct spi_board_info bcm63xx_spi_flash_info[] = { +@@ -189,9 +193,13 @@ void __init bcm63xx_flash_detect(void) + } + } + +-int __init bcm63xx_flash_register(void) ++int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata) + { + u32 val; ++ unsigned int i; ++ ++ for (i = 0; i < num_caldata; i++) ++ bcm63xx_parser_data.caldata[i] = caldata[i].caldata_offset; + + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -1,6 +1,8 @@ + #ifndef __BCM63XX_FLASH_H + #define __BCM63XX_FLASH_H + ++#include <board_bcm963xx.h> ++ + enum { + BCM63XX_FLASH_TYPE_PARALLEL, + BCM63XX_FLASH_TYPE_SERIAL, +@@ -9,7 +11,7 @@ enum { + + void bcm63xx_flash_detect(void); + +-int __init bcm63xx_flash_register(void); ++int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata); + + int bcm63xx_flash_get_type(void); + diff --git a/target/linux/brcm63xx/patches-3.13/420-BCM63XX-add-endian-check-for-ath9k.patch b/target/linux/brcm63xx/patches-3.13/420-BCM63XX-add-endian-check-for-ath9k.patch new file mode 100644 index 0000000000..cbceaa9c4b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/420-BCM63XX-add-endian-check-for-ath9k.patch @@ -0,0 +1,51 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h +@@ -2,6 +2,7 @@ + #define _PCI_ATH9K_FIXUP + + +-void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init; ++void pci_enable_ath9k_fixup(unsigned slot, u32 offset, ++ unsigned endian_check) __init; + + #endif /* _PCI_ATH9K_FIXUP */ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -19,6 +19,7 @@ + struct ath9k_caldata { + unsigned int slot; + u32 caldata_offset; ++ unsigned int endian_check:1; + }; + + /* +--- a/arch/mips/bcm63xx/pci-ath9k-fixup.c ++++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c +@@ -174,12 +174,14 @@ static void ath9k_pci_fixup(struct pci_d + } + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); + +-void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset) ++void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset, ++ unsigned endian_check) + { + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) + return; + + ath9k_fixups[ath9k_num_fixups].slot = slot; ++ ath9k_fixups[ath9k_num_fixups].pdata.endian_check = endian_check; + + if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) + return; +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1066,7 +1066,8 @@ int __init board_register_devices(void) + + /* register any fixups */ + for (i = 0; i < board.has_caldata; i++) +- pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset); ++ pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset, ++ board.caldata[i].endian_check); + + return 0; + } diff --git a/target/linux/brcm63xx/patches-3.13/421-BCM63XX-add-led-pin-for-ath9k.patch b/target/linux/brcm63xx/patches-3.13/421-BCM63XX-add-led-pin-for-ath9k.patch new file mode 100644 index 0000000000..f4821b6744 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/421-BCM63XX-add-led-pin-for-ath9k.patch @@ -0,0 +1,49 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1067,7 +1067,7 @@ int __init board_register_devices(void) + /* register any fixups */ + for (i = 0; i < board.has_caldata; i++) + pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset, +- board.caldata[i].endian_check); ++ board.caldata[i].endian_check, board.caldata[i].led_pin); + + return 0; + } +--- a/arch/mips/bcm63xx/pci-ath9k-fixup.c ++++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c +@@ -175,13 +175,14 @@ static void ath9k_pci_fixup(struct pci_d + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); + + void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset, +- unsigned endian_check) ++ unsigned endian_check, int led_pin) + { + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) + return; + + ath9k_fixups[ath9k_num_fixups].slot = slot; + ath9k_fixups[ath9k_num_fixups].pdata.endian_check = endian_check; ++ ath9k_fixups[ath9k_num_fixups].pdata.led_pin = led_pin; + + if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) + return; +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -20,6 +20,7 @@ struct ath9k_caldata { + unsigned int slot; + u32 caldata_offset; + unsigned int endian_check:1; ++ int led_pin; + }; + + /* +--- a/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h +@@ -3,6 +3,6 @@ + + + void pci_enable_ath9k_fixup(unsigned slot, u32 offset, +- unsigned endian_check) __init; ++ unsigned endian_check, int led_pin) __init; + + #endif /* _PCI_ATH9K_FIXUP */ diff --git a/target/linux/brcm63xx/patches-3.13/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch b/target/linux/brcm63xx/patches-3.13/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch new file mode 100644 index 0000000000..877b5177b8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch @@ -0,0 +1,206 @@ +From 5ed5b5e9614fa5b02da699ab565af76c7e63d64d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Mon, 7 Jan 2013 17:45:39 +0100 +Subject: [PATCH 72/72] 446-BCM63XX-add-a-fixup-for-rt2x00-devices + +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 17 ++++- + arch/mips/bcm63xx/dev-flash.c | 2 +- + arch/mips/bcm63xx/pci-rt2x00-fixup.c | 71 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 +- + .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 9 ++- + .../include/asm/mach-bcm63xx/pci_rt2x00_fixup.h | 9 +++ + 7 files changed, 104 insertions(+), 8 deletions(-) + create mode 100644 arch/mips/bcm63xx/pci-rt2x00-fixup.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_rt2x00_fixup.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -2,7 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ + dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ +- pci-ath9k-fixup.o usb-common.o ++ pci-ath9k-fixup.o pci-rt2x00-fixup.o usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -34,6 +34,7 @@ + #include <bcm63xx_dev_usb_usbd.h> + #include <board_bcm963xx.h> + #include <pci_ath9k_fixup.h> ++#include <pci_rt2x00_fixup.h> + + #include <uapi/linux/bcm933xx_hcs.h> + #include <uapi/linux/bcm963xx_tag.h> +@@ -1065,9 +1066,19 @@ int __init board_register_devices(void) + } + + /* register any fixups */ +- for (i = 0; i < board.has_caldata; i++) +- pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset, +- board.caldata[i].endian_check, board.caldata[i].led_pin); ++ for (i = 0; i < board.has_caldata; i++) { ++ switch (board.caldata[i].vendor) { ++ case PCI_VENDOR_ID_ATHEROS: ++ pci_enable_ath9k_fixup(board.caldata[i].slot, ++ board.caldata[i].caldata_offset, board.caldata[i].endian_check, ++ board.caldata[i].led_pin); ++ break; ++ case PCI_VENDOR_ID_RALINK: ++ pci_enable_rt2x00_fixup(board.caldata[i].slot, ++ board.caldata[i].eeprom); ++ break; ++ } ++ } + + return 0; + } +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -193,7 +193,7 @@ void __init bcm63xx_flash_detect(void) + } + } + +-int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata) ++int __init bcm63xx_flash_register(int num_caldata, struct bcm63xx_caldata *caldata) + { + u32 val; + unsigned int i; +--- /dev/null ++++ b/arch/mips/bcm63xx/pci-rt2x00-fixup.c +@@ -0,0 +1,72 @@ ++/* ++ * Broadcom BCM63XX RT2x00 EEPROM fixup helper. ++ * ++ * Copyright (C) 2012 Álvaro Fernández Rojas <noltari@gmail.com> ++ * ++ * Based on ++ * ++ * Broadcom BCM63XX Ath9k EEPROM fixup helper. ++ * ++ * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include <linux/if_ether.h> ++#include <linux/pci.h> ++#include <linux/platform_device.h> ++#include <linux/rt2x00_platform.h> ++ ++#include <bcm63xx_nvram.h> ++#include <pci_rt2x00_fixup.h> ++ ++struct rt2x00_fixup { ++ unsigned slot; ++ u8 mac[ETH_ALEN]; ++ struct rt2x00_platform_data pdata; ++}; ++ ++static int rt2x00_num_fixups; ++static struct rt2x00_fixup rt2x00_fixups[2] = { ++ { ++ .slot = 255, ++ }, ++ { ++ .slot = 255, ++ }, ++}; ++ ++static void rt2x00_pci_fixup(struct pci_dev *dev) ++{ ++ unsigned i; ++ struct rt2x00_platform_data *pdata = NULL; ++ ++ for (i = 0; i < rt2x00_num_fixups; i++) { ++ if (rt2x00_fixups[i].slot != PCI_SLOT(dev->devfn)) ++ continue; ++ ++ pdata = &rt2x00_fixups[i].pdata; ++ break; ++ } ++ ++ dev->dev.platform_data = pdata; ++} ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RALINK, PCI_ANY_ID, rt2x00_pci_fixup); ++ ++void __init pci_enable_rt2x00_fixup(unsigned slot, char* eeprom) ++{ ++ if (rt2x00_num_fixups >= ARRAY_SIZE(rt2x00_fixups)) ++ return; ++ ++ rt2x00_fixups[rt2x00_num_fixups].slot = slot; ++ rt2x00_fixups[rt2x00_num_fixups].pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL); ++ ++ if (bcm63xx_nvram_get_mac_address(rt2x00_fixups[rt2x00_num_fixups].mac)) ++ return; ++ ++ rt2x00_fixups[rt2x00_num_fixups].pdata.mac_address = rt2x00_fixups[rt2x00_num_fixups].mac; ++ rt2x00_num_fixups++; ++} ++ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -11,7 +11,7 @@ enum { + + void bcm63xx_flash_detect(void); + +-int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata); ++int __init bcm63xx_flash_register(int num_caldata, struct bcm63xx_caldata *caldata); + + int bcm63xx_flash_get_type(void); + +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -9,6 +9,7 @@ + #include <bcm63xx_dev_usb_usbd.h> + #include <bcm63xx_dev_dsp.h> + #include <pci_ath9k_fixup.h> ++#include <pci_rt2x00_fixup.h> + + /* + * flash mapping +@@ -16,11 +17,15 @@ + #define BCM963XX_CFE_VERSION_OFFSET 0x570 + #define BCM963XX_NVRAM_OFFSET 0x580 + +-struct ath9k_caldata { ++struct bcm63xx_caldata { ++ unsigned int vendor; + unsigned int slot; + u32 caldata_offset; ++ /* Atheros */ + unsigned int endian_check:1; + int led_pin; ++ /* Ralink */ ++ char* eeprom; + }; + + /* +@@ -45,7 +50,7 @@ struct board_info { + unsigned int has_caldata:2; + + /* wifi calibration data config */ +- struct ath9k_caldata caldata[2]; ++ struct bcm63xx_caldata caldata[2]; + + /* ethernet config */ + struct bcm63xx_enet_platform_data enet0; +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_rt2x00_fixup.h +@@ -0,0 +1,9 @@ ++#ifndef _PCI_RT2X00_FIXUP ++#define _PCI_RT2X00_FIXUP ++ ++#define PCI_VENDOR_ID_RALINK 0x1814 ++ ++void pci_enable_rt2x00_fixup(unsigned slot, char* eeprom) __init; ++ ++#endif /* _PCI_RT2X00_FIXUP */ ++ diff --git a/target/linux/brcm63xx/patches-3.13/423-bcm63xx_enet_add_b53_support.patch b/target/linux/brcm63xx/patches-3.13/423-bcm63xx_enet_add_b53_support.patch new file mode 100644 index 0000000000..271119cf59 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/423-bcm63xx_enet_add_b53_support.patch @@ -0,0 +1,169 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h +@@ -336,6 +336,9 @@ struct bcm_enet_priv { + struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT]; + int sw_port_link[ENETSW_MAX_PORT]; + ++ /* platform device for associated switch */ ++ struct platform_device *b53_device; ++ + /* used to poll switch port state */ + struct timer_list swphy_poll; + spinlock_t enetsw_mdio_lock; +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -30,6 +30,7 @@ + #include <linux/dma-mapping.h> + #include <linux/platform_device.h> + #include <linux/if_vlan.h> ++#include <linux/platform_data/b53.h> + + #include <bcm63xx_dev_enet.h> + #include "bcm63xx_enet.h" +@@ -1978,7 +1979,8 @@ static int bcm_enet_remove(struct platfo + return 0; + } + +-struct platform_driver bcm63xx_enet_driver = { ++ ++static struct platform_driver bcm63xx_enet_driver = { + .probe = bcm_enet_probe, + .remove = bcm_enet_remove, + .driver = { +@@ -1987,6 +1989,42 @@ struct platform_driver bcm63xx_enet_driv + }, + }; + ++struct b53_platform_data bcm63xx_b53_pdata = { ++ .chip_id = 0x6300, ++ .big_endian = 1, ++}; ++ ++struct platform_device bcm63xx_b53_dev = { ++ .name = "b53-switch", ++ .id = -1, ++ .dev = { ++ .platform_data = &bcm63xx_b53_pdata, ++ }, ++}; ++ ++static int bcmenet_switch_register(struct bcm_enet_priv *priv, u16 port_mask) ++{ ++ int ret; ++ ++ bcm63xx_b53_pdata.regs = priv->base; ++ bcm63xx_b53_pdata.enabled_ports = port_mask; ++ bcm63xx_b53_pdata.alias = priv->net_dev->name; ++ ++ ret = platform_device_register(&bcm63xx_b53_dev); ++ if (!ret) ++ priv->b53_device = &bcm63xx_b53_dev; ++ ++ return ret; ++} ++ ++static void bcmenet_switch_unregister(struct bcm_enet_priv *priv) ++{ ++ if (priv->b53_device) ++ platform_device_unregister(&bcm63xx_b53_dev); ++ ++ priv->b53_device = NULL; ++} ++ + /* + * switch mii access callbacks + */ +@@ -2240,29 +2278,6 @@ static int bcm_enetsw_open(struct net_de + enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); + } + +- /* reset mib */ +- val = enetsw_readb(priv, ENETSW_GMCR_REG); +- val |= ENETSW_GMCR_RST_MIB_MASK; +- enetsw_writeb(priv, val, ENETSW_GMCR_REG); +- mdelay(1); +- val &= ~ENETSW_GMCR_RST_MIB_MASK; +- enetsw_writeb(priv, val, ENETSW_GMCR_REG); +- mdelay(1); +- +- /* force CPU port state */ +- val = enetsw_readb(priv, ENETSW_IMPOV_REG); +- val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; +- enetsw_writeb(priv, val, ENETSW_IMPOV_REG); +- +- /* enable switch forward engine */ +- val = enetsw_readb(priv, ENETSW_SWMODE_REG); +- val |= ENETSW_SWMODE_FWD_EN_MASK; +- enetsw_writeb(priv, val, ENETSW_SWMODE_REG); +- +- /* enable jumbo on all ports */ +- enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG); +- enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG); +- + /* initialize flow control buffer allocation */ + enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, + ENETDMA_BUFALLOC_REG(priv->rx_chan)); +@@ -2722,6 +2737,9 @@ static int bcm_enetsw_probe(struct platf + struct bcm63xx_enetsw_platform_data *pd; + struct resource *res_mem; + int ret, irq_rx, irq_tx; ++ unsigned i, num_ports = 0; ++ u16 port_mask = BIT(8); ++ u8 val; + + /* stop if shared driver failed, assume driver->probe will be + * called in the same order we register devices (correct ?) +@@ -2811,6 +2829,43 @@ static int bcm_enetsw_probe(struct platf + priv->pdev = pdev; + priv->net_dev = dev; + ++ /* reset mib */ ++ val = enetsw_readb(priv, ENETSW_GMCR_REG); ++ val |= ENETSW_GMCR_RST_MIB_MASK; ++ enetsw_writeb(priv, val, ENETSW_GMCR_REG); ++ mdelay(1); ++ val &= ~ENETSW_GMCR_RST_MIB_MASK; ++ enetsw_writeb(priv, val, ENETSW_GMCR_REG); ++ mdelay(1); ++ ++ /* force CPU port state */ ++ val = enetsw_readb(priv, ENETSW_IMPOV_REG); ++ val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; ++ enetsw_writeb(priv, val, ENETSW_IMPOV_REG); ++ ++ /* enable switch forward engine */ ++ val = enetsw_readb(priv, ENETSW_SWMODE_REG); ++ val |= ENETSW_SWMODE_FWD_EN_MASK; ++ enetsw_writeb(priv, val, ENETSW_SWMODE_REG); ++ ++ /* enable jumbo on all ports */ ++ enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG); ++ enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG); ++ ++ for (i = 0; i < priv->num_ports; i++) { ++ struct bcm63xx_enetsw_port *port = &priv->used_ports[i]; ++ ++ if (!port->used) ++ continue; ++ ++ num_ports++; ++ port_mask |= BIT(i); ++ } ++ ++ /* only register if there is more than one external port */ ++ if (num_ports > 1) ++ bcmenet_switch_register(priv, port_mask); ++ + return 0; + + out_put_clk: +@@ -2839,6 +2894,9 @@ static int bcm_enetsw_remove(struct plat + priv = netdev_priv(dev); + unregister_netdev(dev); + ++ /* remove switch */ ++ bcmenet_switch_unregister(priv); ++ + /* release device resources */ + iounmap(priv->base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/brcm63xx/patches-3.13/424-bcm63xx_enet_no_request_mem_region.patch b/target/linux/brcm63xx/patches-3.13/424-bcm63xx_enet_no_request_mem_region.patch new file mode 100644 index 0000000000..24dd27a292 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/424-bcm63xx_enet_no_request_mem_region.patch @@ -0,0 +1,15 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2784,12 +2784,6 @@ static int bcm_enetsw_probe(struct platf + if (ret) + goto out; + +- if (!request_mem_region(res_mem->start, resource_size(res_mem), +- "bcm63xx_enetsw")) { +- ret = -EBUSY; +- goto out; +- } +- + priv->base = ioremap(res_mem->start, resource_size(res_mem)); + if (priv->base == NULL) { + ret = -ENOMEM; diff --git a/target/linux/brcm63xx/patches-3.13/500-board-D4PW.patch b/target/linux/brcm63xx/patches-3.13/500-board-D4PW.patch new file mode 100644 index 0000000000..ffeb8c9c93 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/500-board-D4PW.patch @@ -0,0 +1,67 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -555,6 +555,56 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; ++ ++static struct board_info __initdata board_96348_D4PW = { ++ .name = "D-4P-W", ++ .expected_cpu_id = 0x6348, ++ ++ .has_enet1 = 1, ++ .has_pci = 1, ++ .has_uart0 = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "D-4P-W:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "D-4P-W::status", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "D-4P-W:green:internet", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "D-4P-W:red:internet", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 7, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; + #endif + + /* +@@ -733,6 +783,7 @@ static const struct board_info __initcon + &board_DV201AMR, + &board_96348gw_a, + &board_rta1025w_16, ++ &board_96348_D4PW, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 diff --git a/target/linux/brcm63xx/patches-3.13/501-board-NB4.patch b/target/linux/brcm63xx/patches-3.13/501-board-NB4.patch new file mode 100644 index 0000000000..20d398ca18 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/501-board-NB4.patch @@ -0,0 +1,655 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -15,6 +15,8 @@ + #include <linux/gpio_keys.h> + #include <linux/input.h> + #include <linux/spi/spi.h> ++#include <linux/spi/spi_gpio.h> ++#include <linux/spi/74x164.h> + #include <asm/addrspace.h> + #include <bcm63xx_board.h> + #include <bcm63xx_cpu.h> +@@ -49,6 +51,12 @@ + #define CFE_OFFSET_64K 0x10000 + #define CFE_OFFSET_128K 0x20000 + ++#define NB4_PID_OFFSET 0xff80 ++#define NB4_74X164_GPIO_BASE 64 ++#define NB4_SPI_GPIO_MOSI 7 ++#define NB4_SPI_GPIO_CLK 6 ++#define NB4_74HC64_GPIO(X) (NB4_74X164_GPIO_BASE + (X)) ++ + static struct board_info board; + + /* +@@ -755,6 +763,601 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; ++ ++struct spi_gpio_platform_data nb4_spi_gpio_data = { ++ .sck = NB4_SPI_GPIO_CLK, ++ .mosi = NB4_SPI_GPIO_MOSI, ++ .miso = SPI_GPIO_NO_MISO, ++ .num_chipselect = 1, ++}; ++ ++ ++static struct platform_device nb4_spi_gpio = { ++ .name = "spi_gpio", ++ .id = 1, ++ .dev = { ++ .platform_data = &nb4_spi_gpio_data, ++ }, ++}; ++ ++static struct platform_device * __initdata nb4_devices[] = { ++ &nb4_spi_gpio, ++}; ++ ++const struct gen_74x164_chip_platform_data nb4_74x164_platform_data = { ++ .base = NB4_74X164_GPIO_BASE ++}; ++ ++static struct spi_board_info nb4_spi_devices[] = { ++ { ++ .modalias = "74x164", ++ .max_speed_hz = 781000, ++ .bus_num = 1, ++ .controller_data = (void *) SPI_GPIO_NO_CHIPSELECT, ++ .mode = SPI_MODE_0, ++ .platform_data = &nb4_74x164_platform_data ++ } ++}; ++ ++static struct board_info __initdata board_nb4_ser_r0 = { ++ .name = "NB4-SER-r0", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .leds = { ++ { ++ .name = "NB4-SER-r0:white:adsl", ++ .gpio = NB4_74HC64_GPIO(4), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r0:white:traffic", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r0:white:tel", ++ .gpio = NB4_74HC64_GPIO(3), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r0:white:tv", ++ .gpio = NB4_74HC64_GPIO(2), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r0:white:wifi", ++ .gpio = 15, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r0:white:alarm", ++ .gpio = NB4_74HC64_GPIO(0), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r0:red:service", ++ .gpio = 29, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r0:green:service", ++ .gpio = 30, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r0:blue:service", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 34, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 37, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "service", ++ .gpio = 27, ++ .type = EV_KEY, ++ .code = BTN_0, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "clip", ++ .gpio = 31, ++ .type = EV_KEY, ++ .code = BTN_1, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++ .devs = nb4_devices, ++ .num_devs = ARRAY_SIZE(nb4_devices), ++ .spis = nb4_spi_devices, ++ .num_spis = ARRAY_SIZE(nb4_spi_devices), ++}; ++ ++static struct board_info __initdata board_nb4_ser_r1 = { ++ .name = "NB4-SER-r1", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .leds = { ++ { ++ .name = "NB4-SER-r1:white:adsl", ++ .gpio = NB4_74HC64_GPIO(4), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r1:white:traffic", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r1:white:tel", ++ .gpio = NB4_74HC64_GPIO(3), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r1:white:tv", ++ .gpio = NB4_74HC64_GPIO(2), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r1:white:wifi", ++ .gpio = 15, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r1:white:alarm", ++ .gpio = NB4_74HC64_GPIO(0), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r1:red:service", ++ .gpio = 29, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r1:green:service", ++ .gpio = 30, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r1:blue:service", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 34, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 37, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "service", ++ .gpio = 27, ++ .type = EV_KEY, ++ .code = BTN_0, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "clip", ++ .gpio = 31, ++ .type = EV_KEY, ++ .code = BTN_1, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++ .devs = nb4_devices, ++ .num_devs = ARRAY_SIZE(nb4_devices), ++ .spis = nb4_spi_devices, ++ .num_spis = ARRAY_SIZE(nb4_spi_devices), ++}; ++ ++static struct board_info __initdata board_nb4_ser_r2 = { ++ .name = "NB4-SER-r2", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .leds = { ++ { ++ .name = "NB4-SER-r2:white:adsl", ++ .gpio = NB4_74HC64_GPIO(4), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r2:white:traffic", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r2:white:tel", ++ .gpio = NB4_74HC64_GPIO(3), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r2:white:tv", ++ .gpio = NB4_74HC64_GPIO(2), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r2:white:wifi", ++ .gpio = 15, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r2:white:alarm", ++ .gpio = NB4_74HC64_GPIO(0), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r2:red:service", ++ .gpio = 29, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r2:green:service", ++ .gpio = 30, ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-SER-r2:blue:service", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 34, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 37, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "service", ++ .gpio = 27, ++ .type = EV_KEY, ++ .code = BTN_0, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "clip", ++ .gpio = 31, ++ .type = EV_KEY, ++ .code = BTN_1, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++ .devs = nb4_devices, ++ .num_devs = ARRAY_SIZE(nb4_devices), ++ .spis = nb4_spi_devices, ++ .num_spis = ARRAY_SIZE(nb4_spi_devices), ++}; ++ ++static struct board_info __initdata board_nb4_fxc_r1 = { ++ .name = "NB4-FXC-r1", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .leds = { ++ { ++ .name = "NB4-FXC-r1:white:adsl", ++ .gpio = NB4_74HC64_GPIO(4), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-FXC-r1:white:traffic", ++ .gpio = 2, ++ }, ++ { ++ .name = "NB4-FXC-r1:white:tel", ++ .gpio = NB4_74HC64_GPIO(3), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-FXC-r1:white:tv", ++ .gpio = NB4_74HC64_GPIO(2), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-FXC-r1:white:wifi", ++ .gpio = 15, ++ }, ++ { ++ .name = "NB4-FXC-r1:white:alarm", ++ .gpio = NB4_74HC64_GPIO(0), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-FXC-r1:red:service", ++ .gpio = 29, ++ }, ++ { ++ .name = "NB4-FXC-r1:green:service", ++ .gpio = 30, ++ }, ++ { ++ .name = "NB4-FXC-r1:blue:service", ++ .gpio = 4, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 34, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 37, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "service", ++ .gpio = 27, ++ .type = EV_KEY, ++ .code = BTN_0, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "clip", ++ .gpio = 31, ++ .type = EV_KEY, ++ .code = BTN_1, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++ .devs = nb4_devices, ++ .num_devs = ARRAY_SIZE(nb4_devices), ++ .spis = nb4_spi_devices, ++ .num_spis = ARRAY_SIZE(nb4_spi_devices), ++}; ++ ++static struct board_info __initdata board_nb4_fxc_r2 = { ++ .name = "NB4-FXC-r2", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .leds = { ++ { ++ .name = "NB4-FXC-r2:white:adsl", ++ .gpio = NB4_74HC64_GPIO(4), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-FXC-r2:white:traffic", ++ .gpio = 2, ++ }, ++ { ++ .name = "NB4-FXC-r2:white:tel", ++ .gpio = NB4_74HC64_GPIO(3), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-FXC-r2:white:tv", ++ .gpio = NB4_74HC64_GPIO(2), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-FXC-r2:white:wifi", ++ .gpio = 15, ++ }, ++ { ++ .name = "NB4-FXC-r2:white:alarm", ++ .gpio = NB4_74HC64_GPIO(0), ++ .active_low = 1, ++ }, ++ { ++ .name = "NB4-FXC-r2:red:service", ++ .gpio = 29, ++ }, ++ { ++ .name = "NB4-FXC-r2:green:service", ++ .gpio = 30, ++ }, ++ { ++ .name = "NB4-FXC-r2:blue:service", ++ .gpio = 4, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 34, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 37, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "service", ++ .gpio = 27, ++ .type = EV_KEY, ++ .code = BTN_0, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "clip", ++ .gpio = 31, ++ .type = EV_KEY, ++ .code = BTN_1, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++ .devs = nb4_devices, ++ .num_devs = ARRAY_SIZE(nb4_devices), ++ .spis = nb4_spi_devices, ++ .num_spis = ARRAY_SIZE(nb4_spi_devices), ++}; + #endif + + /* +@@ -791,6 +1394,11 @@ static const struct board_info __initcon + &board_96358vw2, + &board_AGPFS0, + &board_DWVS0, ++ &board_nb4_ser_r0, ++ &board_nb4_ser_r1, ++ &board_nb4_ser_r2, ++ &board_nb4_fxc_r1, ++ &board_nb4_fxc_r2, + #endif + }; + +@@ -845,6 +1453,16 @@ static void __init boardid_fixup(u8 *boo + struct bcm_tag *tag = (struct bcm_tag *)(boot_addr + CFE_OFFSET_64K); + char *board_name = (char *)bcm63xx_nvram_get_name(); + ++ if (BCMCPU_IS_6358() && (!strcmp(board_name, "96358VW"))) { ++ u8 *p = boot_addr + NB4_PID_OFFSET; ++ ++ /* Extract nb4 PID */ ++ if (!memcmp(p, "NB4-", 4)) { ++ memcpy(board_name, p, sizeof("NB4-XXX-rX")); ++ return; ++ } ++ } ++ + /* check if bcm_tag is at 64k offset */ + if (strncmp(board_name, tag->board_id, BOARDID_LEN) != 0) { + /* else try 128k */ diff --git a/target/linux/brcm63xx/patches-3.13/502-board-96338W2_E7T.patch b/target/linux/brcm63xx/patches-3.13/502-board-96338W2_E7T.patch new file mode 100644 index 0000000000..08f856b9db --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/502-board-96338W2_E7T.patch @@ -0,0 +1,51 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -226,6 +226,40 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_96338w2_e7t = { ++ .name = "96338W2_E7T", ++ .expected_cpu_id = 0x6338, ++ ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "96338W2_E7T:green:ppp", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "96338W2_E7T:green:ppp-fail", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "96338W2_E7T:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ ++ }, ++ }, ++}; + #endif + + /* +@@ -1373,6 +1407,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, + &board_96338w, ++ &board_96338w2_e7t, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, diff --git a/target/linux/brcm63xx/patches-3.13/503-board-CPVA642.patch b/target/linux/brcm63xx/patches-3.13/503-board-CPVA642.patch new file mode 100644 index 0000000000..fde7f8bacd --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/503-board-CPVA642.patch @@ -0,0 +1,109 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -754,6 +754,98 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_CPVA642 = { ++ .name = "CPVA642", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .leds = { ++ { ++ .name = "CPVA642:red:power", ++ .gpio = 14, ++ .active_low = 1, ++ }, ++ { ++ .name = "CPVA642:green:power", ++ .gpio = 11, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "CPVA642:red:wifi", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ { ++ .name = "CPVA642:green:wifi", ++ .gpio = 28, ++ .active_low = 0, ++ }, ++ { ++ .name = "CPVA642:red:link", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "CPVA642:green:link", ++ .gpio = 10, ++ .active_low = 1, ++ }, ++ { ++ .name = "CPVA642:green:ether", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "CPVA642:green:phone1", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "CPVA642:green:phone2", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "CPVA642:green:usb", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 36, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 37, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ ++ + static struct board_info __initdata board_AGPFS0 = { + .name = "AGPF-S0", + .expected_cpu_id = 0x6358, +@@ -1428,6 +1520,7 @@ static const struct board_info __initcon + &board_96358vw, + &board_96358vw2, + &board_AGPFS0, ++ &board_CPVA642, + &board_DWVS0, + &board_nb4_ser_r0, + &board_nb4_ser_r1, diff --git a/target/linux/brcm63xx/patches-3.13/504-board_dsl_274xb_rev_c.patch b/target/linux/brcm63xx/patches-3.13/504-board_dsl_274xb_rev_c.patch new file mode 100644 index 0000000000..a6fff9bbda --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/504-board_dsl_274xb_rev_c.patch @@ -0,0 +1,72 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -890,6 +890,61 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + }; + ++/* D-Link DSL-274xB revison C2/C3 */ ++static struct board_info __initdata board_dsl_274xb_rev_c = { ++ .name = "AW4139", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "dsl-274xb:green:power", ++ .gpio = 5, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "dsl-274xb:red:power", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "dsl-274xb:green:adsl", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "dsl-274xb:green:internet", ++ .gpio = 2, ++ }, ++ { ++ .name = "dsl-274xb:red:internet", ++ .gpio = 10, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 34, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + struct spi_gpio_platform_data nb4_spi_gpio_data = { + .sck = NB4_SPI_GPIO_CLK, + .mosi = NB4_SPI_GPIO_MOSI, +@@ -1522,6 +1577,7 @@ static const struct board_info __initcon + &board_AGPFS0, + &board_CPVA642, + &board_DWVS0, ++ &board_dsl_274xb_rev_c, + &board_nb4_ser_r0, + &board_nb4_ser_r1, + &board_nb4_ser_r2, diff --git a/target/linux/brcm63xx/patches-3.13/505-board_spw500v.patch b/target/linux/brcm63xx/patches-3.13/505-board_spw500v.patch new file mode 100644 index 0000000000..394506bdd5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/505-board_spw500v.patch @@ -0,0 +1,78 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -647,6 +647,67 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_spw500v = { ++ .name = "SPW500V", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 6, ++ .gpio_int = 34, ++ .ext_irq = 2, ++ .cs = 2, ++ }, ++ ++ .leds = { ++ { ++ .name = "SPW500V:red:power", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "SPW500V:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "SPW500V:green:ppp", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { .name = "SPW500V:green:pstn", ++ .gpio = 28, ++ .active_low = 1, ++ }, ++ { ++ .name = "SPW500V:green:voip", ++ .gpio = 32, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 33, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; + #endif + + /* +@@ -1569,6 +1630,7 @@ static const struct board_info __initcon + &board_96348gw_a, + &board_rta1025w_16, + &board_96348_D4PW, ++ &board_spw500v, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 diff --git a/target/linux/brcm63xx/patches-3.13/506-board_gw6200_gw6000.patch b/target/linux/brcm63xx/patches-3.13/506-board_gw6200_gw6000.patch new file mode 100644 index 0000000000..1f66a2dd9b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/506-board_gw6200_gw6000.patch @@ -0,0 +1,124 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -514,6 +514,112 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_gw6200 = { ++ .name = "GW6200", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 8, /* FIXME: What is real GPIO here? */ ++ .gpio_int = 34, ++ .ext_irq = 2, ++ .cs = 2, ++ }, ++ ++ .leds = { ++ { ++ .name = "GW6200:green:line1", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "GW6200:green:line2", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "GW6200:green:line3", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ { ++ .name = "GW6200:green:tel", ++ .gpio = 7, ++ .active_low = 1, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 36, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ ++static struct board_info __initdata board_gw6000 = { ++ .name = "GW6000", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 6, ++ .gpio_int = 34, ++ .ext_irq = 2, ++ .cs = 2, ++ }, ++ ++ /* GW6000 has no GPIO-controlled leds */ ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 36, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ ++ ++ + static struct board_info __initdata board_FAST2404 = { + .name = "F@ST2404", + .expected_cpu_id = 0x6348, +@@ -1623,6 +1729,8 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, + &board_96348gw, ++ &board_gw6000, ++ &board_gw6200, + &board_96348gw_10, + &board_96348gw_11, + &board_FAST2404, diff --git a/target/linux/brcm63xx/patches-3.13/507-board-MAGIC.patch b/target/linux/brcm63xx/patches-3.13/507-board-MAGIC.patch new file mode 100644 index 0000000000..55f976c8ab --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/507-board-MAGIC.patch @@ -0,0 +1,89 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -814,6 +814,78 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_96348sv = { ++ .name = "MAGIC", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ /* it has BP_ENET_EXTERNAL_PHY */ ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 25, ++ .gpio_int = 34, ++ .cs = 2, ++ .ext_irq = 2, ++ }, ++ ++ .leds = { ++ { ++ .name = "MAGIC:green:voip", ++ .gpio = 22, ++ .active_low = 1, ++ }, ++ { ++ .name = "MAGIC:green:adsl", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "MAGIC:green:wifi", ++ .gpio = 28, ++ }, ++ { ++ .name = "MAGIC:green:usb", ++ .gpio = 35, ++ .active_low = 1, ++ }, ++ { ++ .name = "MAGIC:green:hpna", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "MAGIC:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "MAGIC:green:stop", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ }, ++}; + #endif + + /* +@@ -1739,6 +1811,7 @@ static const struct board_info __initcon + &board_rta1025w_16, + &board_96348_D4PW, + &board_spw500v, ++ &board_96348sv, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 diff --git a/target/linux/brcm63xx/patches-3.13/508-board_hw553.patch b/target/linux/brcm63xx/patches-3.13/508-board_hw553.patch new file mode 100644 index 0000000000..b7506e0eca --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/508-board_hw553.patch @@ -0,0 +1,94 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1778,6 +1778,83 @@ static struct board_info __initdata boar + .spis = nb4_spi_devices, + .num_spis = ARRAY_SIZE(nb4_spi_devices), + }; ++ ++static struct board_info __initdata board_HW553 = { ++ .name = "HW553", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .leds = { ++ { ++ .name = "HW553:red:lan", ++ .gpio = 34, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW553:blue:lan", ++ .gpio = 35, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW553:red:adsl", ++ .gpio = 22, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW553:blue:adsl", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW553:red:power", ++ .gpio = 5, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ ++ { ++ .name = "HW553:blue:power", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW553:red:wifi", ++ .gpio = 25, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW553:red:internetkey", ++ .gpio = 12, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW553:blue:internetkey", ++ .gpio = 13, ++ .active_low = 1, ++ }, ++ }, ++}; + #endif + + /* +@@ -1826,6 +1903,7 @@ static const struct board_info __initcon + &board_nb4_ser_r2, + &board_nb4_fxc_r1, + &board_nb4_fxc_r2, ++ &board_HW553, + #endif + }; + diff --git a/target/linux/brcm63xx/patches-3.13/509-board_rta1320_16m.patch b/target/linux/brcm63xx/patches-3.13/509-board_rta1320_16m.patch new file mode 100644 index 0000000000..3683825619 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/509-board_rta1320_16m.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -260,6 +260,45 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_rta1320_16m = { ++ .name = "RTA1320_16M", ++ .expected_cpu_id = 0x6338, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "RTA1320_16M:green:adsl", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "RTA1320_16M:green:ppp", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "RTA1320_16M:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "RTA1320_16M:green:stop", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ }, ++}; + #endif + + /* +@@ -1871,6 +1910,7 @@ static const struct board_info __initcon + &board_96338gw, + &board_96338w, + &board_96338w2_e7t, ++ &board_rta1320_16m, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, diff --git a/target/linux/brcm63xx/patches-3.13/510-board_spw303v.patch b/target/linux/brcm63xx/patches-3.13/510-board_spw303v.patch new file mode 100644 index 0000000000..61ab794b4a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/510-board_spw303v.patch @@ -0,0 +1,83 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1894,6 +1894,72 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++ /* T-Home Speedport W 303V Typ B */ ++static struct board_info __initdata board_spw303v = { ++ .name = "96358-502V", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "spw303v:green:power+adsl", ++ .gpio = 22, ++ .active_low = 1, ++ }, ++ { ++ .name = "spw303v:red:power+adsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "spw303v:green:ppp", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "spw303v:green:ses", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "spw303v:green:voip", ++ .gpio = 27, ++ .active_low = 1, ++ }, ++ { ++ .name = "spw303v:green:pots", ++ .gpio = 31, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 11, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "ses", ++ .gpio = 37, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ } ++}; + #endif + + /* +@@ -1944,6 +2010,7 @@ static const struct board_info __initcon + &board_nb4_fxc_r1, + &board_nb4_fxc_r2, + &board_HW553, ++ &board_spw303v, + #endif + }; + diff --git a/target/linux/brcm63xx/patches-3.13/511-board_V2500V.patch b/target/linux/brcm63xx/patches-3.13/511-board_V2500V.patch new file mode 100644 index 0000000000..f4cfc6e66e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/511-board_V2500V.patch @@ -0,0 +1,123 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -925,6 +925,65 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_V2500V_BB = { ++ .name = "V2500V_BB", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "V2500V_BB:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "V2500V_BB:red:power", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "V2500V_BB:green:adsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { .name = "V2500V_BB:green:ppp", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "V2500V_BB:green:wireless", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 31, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; + #endif + + /* +@@ -1995,6 +2054,7 @@ static const struct board_info __initcon + &board_96348_D4PW, + &board_spw500v, + &board_96348sv, ++ &board_V2500V_BB, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -2116,6 +2176,22 @@ void __init board_prom_init(void) + val &= MPI_CSBASE_BASE_MASK; + } + boot_addr = (u8 *)KSEG1ADDR(val); ++ printk(KERN_INFO PFX "Boot address 0x%08x\n",(unsigned int)boot_addr); ++ ++ /* BT Voyager 2500V (RTA1046VW PCB) has 8 Meg flash used as two */ ++ /* banks of 4 Meg. The byte at 0xBF800000 identifies the back to use.*/ ++ /* Loading firmware from the CFE Prompt always loads to Bank 0 */ ++ /* Do an early check of CFE and then select bank 0 */ ++ ++ if (boot_addr == (u8 *)0xbf800000) { ++ u8 *tmp_boot_addr = (u8*)0xbfc00000; ++ ++ bcm63xx_nvram_init(tmp_boot_addr + BCM963XX_NVRAM_OFFSET); ++ if (!strcmp(bcm63xx_nvram_get_name(), "V2500V_BB")) { ++ printk(KERN_INFO PFX "V2500V: nvram bank 0\n"); ++ boot_addr = tmp_boot_addr; ++ } ++ } + + /* dump cfe version */ + cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -19,6 +19,7 @@ + #include <linux/spi/spi.h> + #include <linux/spi/flash.h> + ++#include <bcm63xx_board.h> + #include <bcm63xx_cpu.h> + #include <bcm63xx_dev_flash.h> + #include <bcm63xx_dev_hsspi.h> +@@ -207,6 +208,13 @@ int __init bcm63xx_flash_register(int nu + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + ++ /* BT Voyager 2500V has 8 Meg flash in two 4 Meg banks */ ++ /* Loading from CFE always uses Bank 0 */ ++ if (!strcmp(board_get_name(), "V2500V_BB")) { ++ pr_info("V2500V: Start in Bank 0\n"); ++ val = val + 0x400000; // Select Bank 0 start address ++ } ++ + mtd_resources[0].start = val; + mtd_resources[0].end = 0x1FFFFFFF; + diff --git a/target/linux/brcm63xx/patches-3.13/512-board_BTV2110.patch b/target/linux/brcm63xx/patches-3.13/512-board_BTV2110.patch new file mode 100644 index 0000000000..c68a48bf1b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/512-board_BTV2110.patch @@ -0,0 +1,75 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -485,6 +485,64 @@ static struct board_info __initdata boar + }, + }; + ++ ++/* BT Voyager 2110 */ ++static struct board_info __initdata board_V2110 = { ++ .name = "V2110", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "V2110:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "V2110:red:power", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "V2110:green:adsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { .name = "V2110:green:ppp", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "V2110:green:wireless", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 33, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ ++ + static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, +@@ -2055,6 +2113,7 @@ static const struct board_info __initcon + &board_spw500v, + &board_96348sv, + &board_V2500V_BB, ++ &board_V2110, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 diff --git a/target/linux/brcm63xx/patches-3.13/513-board_livebox.patch b/target/linux/brcm63xx/patches-3.13/513-board_livebox.patch new file mode 100644 index 0000000000..2323b5eef7 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/513-board_livebox.patch @@ -0,0 +1,390 @@ +--- a/arch/mips/bcm63xx/boards/Kconfig ++++ b/arch/mips/bcm63xx/boards/Kconfig +@@ -8,4 +8,10 @@ config BOARD_BCM963XX + select SSB + help + ++config BOARD_LIVEBOX ++ bool "Inventel Livebox(es) boards" ++ select SSB ++ help ++ Inventel Livebox boards using the RedBoot bootloader. ++ + endchoice +--- a/arch/mips/bcm63xx/boards/Makefile ++++ b/arch/mips/bcm63xx/boards/Makefile +@@ -1 +1,2 @@ + obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o ++obj-$(CONFIG_BOARD_LIVEBOX) += board_livebox.o +--- /dev/null ++++ b/arch/mips/bcm63xx/boards/board_livebox.c +@@ -0,0 +1,369 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> ++ */ ++ ++#include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/string.h> ++#include <linux/platform_device.h> ++#include <linux/mtd/mtd.h> ++#include <linux/mtd/partitions.h> ++#include <linux/mtd/physmap.h> ++#include <linux/ssb/ssb.h> ++#include <linux/gpio_keys.h> ++#include <linux/input.h> ++#include <linux/spi/spi.h> ++#include <asm/addrspace.h> ++#include <bcm63xx_board.h> ++#include <bcm63xx_cpu.h> ++#include <bcm63xx_dev_uart.h> ++#include <bcm63xx_regs.h> ++#include <bcm63xx_io.h> ++#include <bcm63xx_dev_pci.h> ++#include <bcm63xx_dev_enet.h> ++#include <bcm63xx_dev_dsp.h> ++#include <bcm63xx_dev_pcmcia.h> ++#include <bcm63xx_dev_usb_ohci.h> ++#include <bcm63xx_dev_usb_ehci.h> ++#include <bcm63xx_dev_spi.h> ++#include <board_bcm963xx.h> ++ ++#define PFX "board_livebox: " ++ ++#define LIVEBOX_KEYS_POLL_INTERVAL 20 ++#define LIVEBOX_KEYS_DEBOUNCE_INTERVAL (LIVEBOX_KEYS_POLL_INTERVAL * 3) ++ ++static unsigned int mac_addr_used = 0; ++static struct board_info board; ++ ++/* ++ * known 6348 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_6348 ++static struct board_info __initdata board_livebox_blue5g = { ++ .name = "Livebox-blue-5g", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 31, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ ++ .has_dsp = 0, /*TODO some Liveboxes have dsp*/ ++ .dsp = { ++ .gpio_rst = 6, /*FIXME eth1 shares gpio6 with dsp?*/ ++ .gpio_int = 35, ++ .cs = 2, ++ .ext_irq = 2, ++ }, ++ ++ .leds = { ++ { ++ .name = "Livebox-blue-5g::adsl-fail", ++ .gpio = 0, ++ .active_low = 0, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "Livebox-blue-5g::adsl", ++ .gpio = 1, ++ }, ++ { ++ .name = "Livebox-blue-5g::traffic", ++ .gpio = 2, ++ }, ++ { ++ .name = "Livebox-blue-5g::phone", ++ .gpio = 3, ++ }, ++ { ++ .name = "Livebox-blue-5g::wifi", ++ .gpio = 4, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "BTN_1", ++ .gpio = 36, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = BTN_1, ++ .debounce_interval = LIVEBOX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "BTN_2", ++ .gpio = 7, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = BTN_2, ++ .debounce_interval = LIVEBOX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ ++ }, ++}; ++#endif ++ ++/* ++ * all boards ++ */ ++static const struct board_info __initdata *bcm963xx_boards[] = { ++#ifdef CONFIG_BCM63XX_CPU_6348 ++ &board_livebox_blue5g ++#endif ++}; ++/* ++ * return board name for /proc/cpuinfo ++ */ ++const char *board_get_name(void) ++{ ++ return board.name; ++} ++ ++/* ++ * register & return a new board mac address ++ */ ++static int board_get_mac_address(u8 *mac) ++{ ++ u8 *p; ++ int count; ++ ++ memcpy(mac, (u8 *)0xBEBFF377, ETH_ALEN); ++ ++ p = mac + ETH_ALEN - 1; ++ count = mac_addr_used; ++ ++ while (count--) { ++ do { ++ (*p)++; ++ if (*p != 0) ++ break; ++ p--; ++ } while (p != mac); ++ } ++ ++ if (p == mac) { ++ printk(KERN_ERR PFX "unable to fetch mac address\n"); ++ return -ENODEV; ++ } ++ mac_addr_used++; ++ ++ return 0; ++} ++ ++/* ++ * early init callback ++ */ ++#define LIVEBOX_GPIO_DETECT_MASK 0x000000ff ++#define LIVEBOX_BOOT_ADDR 0x1e400000 ++ ++#define LIVEBOX_HW_BLUE5G_9 0x90 ++ ++void __init board_prom_init(void) ++{ ++ u32 val; ++ u8 hw_version; ++ ++ /* Get hardware version */ ++ val = bcm_gpio_readl(GPIO_CTL_LO_REG); ++ val &= ~LIVEBOX_GPIO_DETECT_MASK; ++ bcm_gpio_writel(val, GPIO_CTL_LO_REG); ++ ++ hw_version = bcm_gpio_readl(GPIO_DATA_LO_REG) & LIVEBOX_GPIO_DETECT_MASK; ++ switch (hw_version) { ++ case LIVEBOX_HW_BLUE5G_9: ++ printk(KERN_INFO PFX "Livebox BLUE5G.9\n"); ++ memcpy(&board, bcm963xx_boards[0], sizeof(board)); ++ break; ++ default: ++ printk(KERN_INFO PFX "Unknown livebox version: %02x\n", hw_version); ++ break; ++ } ++ ++ /* use default livebox configuration */ ++ memcpy(&board, bcm963xx_boards[0], sizeof(board)); ++ ++ /* setup pin multiplexing depending on board enabled device, ++ * this has to be done this early since PCI init is done ++ * inside arch_initcall */ ++ val = 0; ++ ++#ifdef CONFIG_PCI ++ if (board.has_pci) { ++ bcm63xx_pci_enabled = 1; ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G2_PCI; ++ } ++#endif ++ if (board.has_pccard) { ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G1_MII_PCCARD; ++ } ++ ++ if (board.has_enet0 && !board.enet0.use_internal_phy) { ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G3_EXT_MII | ++ GPIO_MODE_6348_G0_EXT_MII; ++ } ++ ++ if (board.has_enet1 && !board.enet1.use_internal_phy) { ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G3_EXT_MII | ++ GPIO_MODE_6348_G0_EXT_MII; ++ printk(KERN_INFO PFX "resetting gpio6 for eth1...\n"); ++ gpio_request(6, "dsp_eth_rst"); ++ gpio_direction_output(6, 0); ++ gpio_set_value(6, 1); ++ } ++ ++ bcm_gpio_writel(val, GPIO_MODE_REG); ++} ++ ++/* ++ * second stage init callback, good time to panic if we couldn't ++ * identify on which board we're running since early printk is working ++ */ ++void __init board_setup(void) ++{ ++ if (!board.name[0]) ++ panic("unable to detect bcm963xx board"); ++ printk(KERN_INFO PFX "board name: %s\n", board.name); ++ ++ /* make sure we're running on expected cpu */ ++ if (bcm63xx_get_cpu_id() != board.expected_cpu_id) ++ panic("unexpected CPU for bcm963xx board"); ++} ++ ++static struct physmap_flash_data flash_data = { ++ .width = 2, ++}; ++ ++static struct resource mtd_resources[] = { ++ { ++ .start = 0, /* filled at runtime */ ++ .end = 0, /* filled at runtime */ ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct platform_device mtd_dev = { ++ .name = "physmap-flash", ++ .resource = mtd_resources, ++ .num_resources = ARRAY_SIZE(mtd_resources), ++ .dev = { ++ .platform_data = &flash_data, ++ }, ++}; ++ ++static struct gpio_led_platform_data bcm63xx_led_data; ++ ++static struct platform_device bcm63xx_gpio_leds = { ++ .name = "leds-gpio", ++ .id = 0, ++ .dev.platform_data = &bcm63xx_led_data, ++}; ++ ++static struct gpio_keys_platform_data bcm63xx_gpio_keys_data = { ++ .poll_interval = LIVEBOX_KEYS_POLL_INTERVAL, ++}; ++ ++static struct platform_device bcm63xx_gpio_keys_device = { ++ .name = "gpio-keys-polled", ++ .id = 0, ++ .dev.platform_data = &bcm63xx_gpio_keys_data, ++}; ++ ++/* ++ * third stage init callback, register all board devices. ++ */ ++int __init board_register_devices(void) ++{ ++ u32 val; ++ int led_count = 0; ++ int button_count = 0; ++ ++ if (board.has_uart0) ++ bcm63xx_uart_register(0); ++ ++ if (board.has_uart1) ++ bcm63xx_uart_register(1); ++ ++ if (board.has_pccard) ++ bcm63xx_pcmcia_register(); ++ ++ if (board.has_enet0 && ++ !board_get_mac_address(board.enet0.mac_addr)) ++ bcm63xx_enet_register(0, &board.enet0); ++ ++ if (board.has_enet1 && ++ !board_get_mac_address(board.enet1.mac_addr)) ++ bcm63xx_enet_register(1, &board.enet1); ++ ++ if (board.has_ehci0) ++ bcm63xx_ehci_register(); ++ ++ if (board.has_ohci0) ++ bcm63xx_ohci_register(); ++ ++ if (board.has_dsp) ++ bcm63xx_dsp_register(&board.dsp); ++ ++ bcm63xx_spi_register(); ++ ++ if (board.num_devs) ++ platform_add_devices(board.devs, board.num_devs); ++ ++ if (board.num_spis) ++ spi_register_board_info(board.spis, board.num_spis); ++ ++ ++ /* read base address of boot chip select (0) */ ++ val = bcm_mpi_readl(MPI_CSBASE_REG(0)); ++ val &= MPI_CSBASE_BASE_MASK; ++ if (val != LIVEBOX_BOOT_ADDR) ++ printk(KERN_NOTICE PFX "flash address is: 0x%08x, forcing to: 0x%08x\n", ++ val, LIVEBOX_BOOT_ADDR); ++ mtd_resources[0].start = LIVEBOX_BOOT_ADDR; ++ mtd_resources[0].end = 0x1ebfffff; ++ ++ platform_device_register(&mtd_dev); ++ ++ /* count number of LEDs defined by this device */ ++ while (led_count < ARRAY_SIZE(board.leds) && board.leds[led_count].name) ++ led_count++; ++ ++ bcm63xx_led_data.num_leds = led_count; ++ bcm63xx_led_data.leds = board.leds; ++ ++ platform_device_register(&bcm63xx_gpio_leds); ++ ++ /* count number of BUTTONs defined by this device */ ++ while (button_count < ARRAY_SIZE(board.buttons) && board.buttons[button_count].desc) ++ button_count++; ++ ++ if (button_count) { ++ bcm63xx_gpio_keys_data.nbuttons = button_count; ++ bcm63xx_gpio_keys_data.buttons = board.buttons; ++ ++ platform_device_register(&bcm63xx_gpio_keys_device); ++ } ++ ++ return 0; ++} diff --git a/target/linux/brcm63xx/patches-3.13/514-board_ct536_ct5621.patch b/target/linux/brcm63xx/patches-3.13/514-board_ct536_ct5621.patch new file mode 100644 index 0000000000..10d0d47bc8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/514-board_ct536_ct5621.patch @@ -0,0 +1,62 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -543,6 +543,51 @@ static struct board_info __initdata boar + }; + + ++static struct board_info __initdata board_ct536_ct5621 = { ++ .name = "CT536_CT5621", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 0, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ ++ .leds = { ++ { ++ .name = "CT536_CT5621:green:adsl-fail", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "CT536_CT5621:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 33, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, +@@ -2114,6 +2159,7 @@ static const struct board_info __initcon + &board_96348sv, + &board_V2500V_BB, + &board_V2110, ++ &board_ct536_ct5621, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 diff --git a/target/linux/brcm63xx/patches-3.13/515-board_DWV-S0_fixes.patch b/target/linux/brcm63xx/patches-3.13/515-board_DWV-S0_fixes.patch new file mode 100644 index 0000000000..c8825c0e35 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/515-board_DWV-S0_fixes.patch @@ -0,0 +1,19 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1313,6 +1313,8 @@ static struct board_info __initdata boar + .name = "DWV-S0", + .expected_cpu_id = 0x6358, + ++ .has_uart0 = 1, ++ + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, +@@ -1328,6 +1330,7 @@ static struct board_info __initdata boar + }, + + .has_ohci0 = 1, ++ .has_ehci0 = 1, + }; + + /* D-Link DSL-274xB revison C2/C3 */ diff --git a/target/linux/brcm63xx/patches-3.13/516-board_96348A-122.patch b/target/linux/brcm63xx/patches-3.13/516-board_96348A-122.patch new file mode 100644 index 0000000000..d3017dcaa4 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/516-board_96348A-122.patch @@ -0,0 +1,80 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -588,6 +588,69 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_96348A_122 = { ++ .name = "96348A-122", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .leds = { ++ { ++ .name = "96348A-122:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "96348A-122:red:alarm", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "96348A-122:green:wps", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 33, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wlan", ++ .gpio = 34, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WLAN, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 35, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, +@@ -2163,6 +2226,7 @@ static const struct board_info __initcon + &board_V2500V_BB, + &board_V2110, + &board_ct536_ct5621, ++ &board_96348A_122, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 diff --git a/target/linux/brcm63xx/patches-3.13/517-RTA1205W_16_uart_fixes.patch b/target/linux/brcm63xx/patches-3.13/517-RTA1205W_16_uart_fixes.patch new file mode 100644 index 0000000000..c3756148c2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/517-RTA1205W_16_uart_fixes.patch @@ -0,0 +1,10 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -853,6 +853,7 @@ static struct board_info __initdata boar + .name = "RTA1025W_16", + .expected_cpu_id = 0x6348, + ++ .has_uart0 = 1, + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, diff --git a/target/linux/brcm63xx/patches-3.13/519_board_CPVA502plus.patch b/target/linux/brcm63xx/patches-3.13/519_board_CPVA502plus.patch new file mode 100644 index 0000000000..b5ae101c33 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/519_board_CPVA502plus.patch @@ -0,0 +1,57 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1151,6 +1151,46 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_CPVA502plus = { ++ .name = "CPVA502+", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "CPVA502+:green:phone", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "CPVA502+:green:link", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "CPVA502+:green:feth1", /* FIXME:does gpio4 enable eth1 phy? */ ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ }, ++}; ++ + #endif + + /* +@@ -2228,6 +2268,7 @@ static const struct board_info __initcon + &board_V2110, + &board_ct536_ct5621, + &board_96348A_122, ++ &board_CPVA502plus, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 diff --git a/target/linux/brcm63xx/patches-3.13/520-bcm63xx-add-support-for-96368MVWG-board.patch b/target/linux/brcm63xx/patches-3.13/520-bcm63xx-add-support-for-96368MVWG-board.patch new file mode 100644 index 0000000000..8ff14aefbb --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/520-bcm63xx-add-support-for-96368MVWG-board.patch @@ -0,0 +1,135 @@ +From eeacc2529942051504bc957726aa178671344421 Mon Sep 17 00:00:00 2001 +From: Maxime Bizon <mbizon@freebox.fr> +Date: Wed, 20 Jan 2010 16:21:30 +0100 +Subject: [PATCH 32/63] bcm63xx: add support for 96368MVWG board. + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 95 ++++++++++++++++++++ + .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 2 + + 2 files changed, 97 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2232,6 +2232,85 @@ static struct board_info __initdata boar + #endif + + /* ++ * known 6368 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_6368 ++static struct board_info __initdata board_96368mvwg = { ++ .name = "96368MVWG", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port1", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port2", ++ }, ++ ++ [4] = { ++ .used = 1, ++ .phy_id = 0x12, ++ .name = "port0", ++ }, ++ ++ [5] = { ++ .used = 1, ++ .phy_id = 0x11, ++ .name = "port3", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "96368MVWG:green:adsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "96368MVWG:green:ppp", ++ .gpio = 5, ++ }, ++ { ++ .name = "96368MVWG:green:power", ++ .gpio = 22, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "96368MVWG:green:wps", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "96368MVWG:red:ppp-fail", ++ .gpio = 31, ++ }, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++}; ++#endif ++ ++/* + * all boards + */ + static const struct board_info __initconst *bcm963xx_boards[] = { +@@ -2286,6 +2365,10 @@ static const struct board_info __initcon + &board_HW553, + &board_spw303v, + #endif ++ ++#ifdef CONFIG_BCM63XX_CPU_6368 ++ &board_96368mvwg, ++#endif + }; + + /* +@@ -2467,12 +2550,25 @@ void __init board_prom_init(void) + bcm63xx_pci_enabled = 1; + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G2_PCI; ++ ++ if (BCMCPU_IS_6368()) ++ val |= GPIO_MODE_6368_PCI_REQ1 | ++ GPIO_MODE_6368_PCI_GNT1 | ++ GPIO_MODE_6368_PCI_INTB | ++ GPIO_MODE_6368_PCI_REQ0 | ++ GPIO_MODE_6368_PCI_GNT0; + } + #endif + + if (board.has_pccard) { + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G1_MII_PCCARD; ++ ++ if (BCMCPU_IS_6368()) ++ val |= GPIO_MODE_6368_PCMCIA_CD1 | ++ GPIO_MODE_6368_PCMCIA_CD2 | ++ GPIO_MODE_6368_PCMCIA_VS1 | ++ GPIO_MODE_6368_PCMCIA_VS2; + } + + if (board.has_enet0 && !board.enet0.use_internal_phy) { diff --git a/target/linux/brcm63xx/patches-3.13/521-bcm63xx-add-support-for-96368MVNgr-board.patch b/target/linux/brcm63xx/patches-3.13/521-bcm63xx-add-support-for-96368MVNgr-board.patch new file mode 100644 index 0000000000..f29709692a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/521-bcm63xx-add-support-for-96368MVNgr-board.patch @@ -0,0 +1,92 @@ +From f457fc2eb9bb915b5a4d251c7c68d4694cf07b01 Mon Sep 17 00:00:00 2001 +From: Maxime Bizon <mbizon@freebox.fr> +Date: Fri, 4 Nov 2011 12:33:48 +0100 +Subject: [PATCH 33/63] bcm63xx: add support for 96368MVNgr board. + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 67 +++++++++++++++++++++++++++++ + 1 files changed, 67 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2308,6 +2308,72 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_ehci0 = 1, + }; ++ ++static struct board_info __initdata board_96368mvngr = { ++ .name = "96368MVNgr", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "96368MVNgr:green:adsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "96368MVNgr:green:inet", ++ .gpio = 5, ++ }, ++ { ++ .name = "96368MVNgr:green:power", ++ .gpio = 22, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "96368MVNgr:green:wps", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "96368MVNgr:green:inet-fail", ++ .gpio = 3, ++ }, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++}; + #endif + + /* +@@ -2368,6 +2434,7 @@ static const struct board_info __initcon + + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, ++ &board_96368mvngr, + #endif + }; + diff --git a/target/linux/brcm63xx/patches-3.13/522-MIPS-BCM63XX-add-96328avng-reference-board.patch b/target/linux/brcm63xx/patches-3.13/522-MIPS-BCM63XX-add-96328avng-reference-board.patch new file mode 100644 index 0000000000..c8c098d9e6 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/522-MIPS-BCM63XX-add-96328avng-reference-board.patch @@ -0,0 +1,67 @@ +From c93c2bbf0cc96da5a47d77f01daf6c983cfe4216 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Tue, 29 May 2012 10:52:25 +0200 +Subject: [PATCH] MIPS: BCM63XX: add 96328avng reference board + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 77 +++++++++++++++++++++++++++++ + 1 files changed, 77 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -108,13 +108,45 @@ static struct board_info __initdata boar + .port_no = 0, + }, + ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ + .leds = { + { +- .name = "96328avng::ppp-fail", ++ .name = "96328avng::internet-fail", + .gpio = 2, + .active_low = 1, + }, + { ++ .name = "96328avng::dsl", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { + .name = "96328avng::power", + .gpio = 4, + .active_low = 1, +@@ -131,7 +163,7 @@ static struct board_info __initdata boar + .active_low = 1, + }, + { +- .name = "96328avng::ppp", ++ .name = "96328avng::internet", + .gpio = 11, + .active_low = 1, + }, diff --git a/target/linux/brcm63xx/patches-3.13/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch b/target/linux/brcm63xx/patches-3.13/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch new file mode 100644 index 0000000000..114778d58f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch @@ -0,0 +1,96 @@ +From f0649f7b7c672cf452a1796a1422bf615e1973f8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Tue, 29 May 2012 11:01:12 +0200 +Subject: [PATCH] MIPS: BCM63XX: add 963281TAN reference board + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 71 +++++++++++++++++++++++++++++ + 1 files changed, 71 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -169,6 +169,76 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_963281TAN = { ++ .name = "963281TAN", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "963281TAN::internet", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281TAN::power", ++ .gpio = 4, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "963281TAN::internet-fail", ++ .gpio = 7, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281TAN::power-fail", ++ .gpio = 8, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281TAN::wps", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281TAN::dsl", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ ++ }, ++}; + #endif + + /* +@@ -2417,6 +2487,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, ++ &board_963281TAN, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, diff --git a/target/linux/brcm63xx/patches-3.13/524-board_dsl_274xb_rev_f.patch b/target/linux/brcm63xx/patches-3.13/524-board_dsl_274xb_rev_f.patch new file mode 100644 index 0000000000..3d5b5d1b4f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/524-board_dsl_274xb_rev_f.patch @@ -0,0 +1,132 @@ +From 66808f706b3dcd83a9f5157997ff478a880a2906 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Mon, 30 Apr 2012 09:10:51 +0200 +Subject: [PATCH 70/79] MIPS: BCM63XX: Add board definition for D-Link + DSL-274xB rev F1 + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 104 +++++++++++++++++++++++++++++ + 1 files changed, 104 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -239,6 +239,111 @@ static struct board_info __initdata boar + + }, + }; ++ ++static struct board_info __initdata board_dsl_274xb_f1 = { ++ .name = "AW4339U", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_ATHEROS, ++ .caldata_offset = 0x7d1000, ++ .slot = 0, ++ .led_pin = -1, ++ }, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 4", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 3", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 2", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 1", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "dsl-274xb:red:internet", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "dsl-274xb:green:dsl", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "dsl-274xb:green:power", ++ .gpio = 4, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "dsl-274xb:red:power", ++ .gpio = 8, ++ .active_low = 1, ++ }, ++ { ++ .name = "dsl-274xb:blue:wps", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "dsl-274xb:green:internet", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "wifi", ++ .gpio = 10, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "reset", ++ .gpio = 23, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 24, ++ .active_low = 1, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; + #endif + + /* +@@ -2488,6 +2593,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, + &board_963281TAN, ++ &board_dsl_274xb_f1, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, diff --git a/target/linux/brcm63xx/patches-3.13/525-board_96348w3.patch b/target/linux/brcm63xx/patches-3.13/525-board_96348w3.patch new file mode 100644 index 0000000000..52134d4109 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/525-board_96348w3.patch @@ -0,0 +1,70 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1398,6 +1398,59 @@ static struct board_info __initdata boar + }, + }; + ++/* NetGear DG834G v4 */ ++static struct board_info __initdata board_96348W3 = { ++ .name = "96348W3", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .leds = { ++ { ++ .name = "96348W3:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "96348W3:red:power", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "96348W3::adsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "96348W3::internet", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 6, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + #endif + + /* +@@ -2623,6 +2676,7 @@ static const struct board_info __initcon + &board_ct536_ct5621, + &board_96348A_122, + &board_CPVA502plus, ++ &board_96348W3, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 diff --git a/target/linux/brcm63xx/patches-3.13/526-board_CT6373-1.patch b/target/linux/brcm63xx/patches-3.13/526-board_CT6373-1.patch new file mode 100644 index 0000000000..cd0122bcfb --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/526-board_CT6373-1.patch @@ -0,0 +1,138 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -57,6 +57,13 @@ + #define NB4_SPI_GPIO_CLK 6 + #define NB4_74HC64_GPIO(X) (NB4_74X164_GPIO_BASE + (X)) + ++#define CT6373_PID_OFFSET 0xff80 ++#define CT6373_74X164_GPIO_BASE 64 ++#define CT6373_SPI_GPIO_MOSI 7 ++#define CT6373_SPI_GPIO_CLK 6 ++#define CT6373_74HC64_GPIO(X) (CT6373_74X164_GPIO_BASE + (X)) ++ ++ + static struct board_info board; + + /* +@@ -2347,6 +2354,113 @@ static struct board_info __initdata boar + .num_spis = ARRAY_SIZE(nb4_spi_devices), + }; + ++ ++struct spi_gpio_platform_data ct6373_spi_gpio_data = { ++ .sck = CT6373_SPI_GPIO_CLK, ++ .mosi = CT6373_SPI_GPIO_MOSI, ++ .miso = SPI_GPIO_NO_MISO, ++ .num_chipselect = 1, ++}; ++ ++static struct platform_device ct6373_spi_gpio = { ++ .name = "spi_gpio", ++ .id = 1, ++ .dev = { ++ .platform_data = &ct6373_spi_gpio_data, ++ }, ++}; ++ ++static struct platform_device * __initdata ct6373_devices[] = { ++ &ct6373_spi_gpio, ++}; ++ ++const struct gen_74x164_chip_platform_data ct6373_74x164_platform_data = { ++ .base = CT6373_74X164_GPIO_BASE ++}; ++ ++static struct spi_board_info ct6373_spi_devices[] = { ++ { ++ .modalias = "74x164", ++ .max_speed_hz = 781000, ++ .bus_num = 1, ++ .controller_data = (void *) SPI_GPIO_NO_CHIPSELECT, ++ .mode = SPI_MODE_0, ++ .platform_data = &ct6373_74x164_platform_data ++ } ++}; ++ ++static struct board_info __initdata board_ct6373_1 = { ++ .name = "CT6373-1", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "CT6373-1:green:power", ++ .gpio = 0, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "CT6373-1:green:usb", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "CT6373-1:green:wlan", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "CT6373-1:green:adsl", ++ .gpio = CT6373_74HC64_GPIO(0), ++ .active_low = 1, ++ }, ++ { ++ .name = "CT6373-1:green:line", ++ .gpio = CT6373_74HC64_GPIO(1), ++ .active_low = 1, ++ }, ++ { ++ .name = "CT6373-1:green:fxs1", ++ .gpio = CT6373_74HC64_GPIO(2), ++ .active_low = 1, ++ }, ++ { ++ .name = "CT6373-1:green:fxs2", ++ .gpio = CT6373_74HC64_GPIO(3), ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 35, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++ ++ .devs = ct6373_devices, ++ .num_devs = ARRAY_SIZE(ct6373_devices), ++ .spis = ct6373_spi_devices, ++ .num_spis = ARRAY_SIZE(ct6373_spi_devices), ++}; ++ + static struct board_info __initdata board_HW553 = { + .name = "HW553", + .expected_cpu_id = 0x6358, +@@ -2691,6 +2805,7 @@ static const struct board_info __initcon + &board_nb4_ser_r2, + &board_nb4_fxc_r1, + &board_nb4_fxc_r2, ++ &board_ct6373_1, + &board_HW553, + &board_spw303v, + #endif diff --git a/target/linux/brcm63xx/patches-3.13/527-board_dva-g3810bn-tl-1.patch b/target/linux/brcm63xx/patches-3.13/527-board_dva-g3810bn-tl-1.patch new file mode 100644 index 0000000000..a555298f03 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/527-board_dva-g3810bn-tl-1.patch @@ -0,0 +1,84 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2603,6 +2603,73 @@ static struct board_info __initdata boar + }, + } + }; ++ ++/* D-Link DVA-G3810BN/TL */ ++static struct board_info __initdata board_DVAG3810BN = { ++ .name = "DVAG3810BN", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 0, ++ .use_internal_phy = 1, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ ++ .leds = { ++ { ++ .name = "DVAG3810BN::voip", ++ .gpio = 1, ++ }, ++ { ++ .name = "DVAG3810BN::dsl", ++ .gpio = 22, ++ .active_low = 1, ++ }, ++ { ++ .name = "DVAG3810BN::internet", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "DVAG3810BN::power", ++ .gpio = 4, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "DVAG3810BN::stop", ++ .gpio = 5, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 34, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; + #endif + + /* +@@ -2808,6 +2875,7 @@ static const struct board_info __initcon + &board_ct6373_1, + &board_HW553, + &board_spw303v, ++ &board_DVAG3810BN, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6368 diff --git a/target/linux/brcm63xx/patches-3.13/528-board_nb6.patch b/target/linux/brcm63xx/patches-3.13/528-board_nb6.patch new file mode 100644 index 0000000000..66705fa6f3 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/528-board_nb6.patch @@ -0,0 +1,147 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -17,6 +17,7 @@ + #include <linux/spi/spi.h> + #include <linux/spi/spi_gpio.h> + #include <linux/spi/74x164.h> ++#include <linux/rtl8367.h> + #include <asm/addrspace.h> + #include <bcm63xx_board.h> + #include <bcm63xx_cpu.h> +@@ -56,6 +57,8 @@ + #define NB4_SPI_GPIO_MOSI 7 + #define NB4_SPI_GPIO_CLK 6 + #define NB4_74HC64_GPIO(X) (NB4_74X164_GPIO_BASE + (X)) ++#define NB6_GPIO_RTL8367_SDA 18 ++#define NB6_GPIO_RTL8367_SCK 20 + + #define CT6373_PID_OFFSET 0xff80 + #define CT6373_74X164_GPIO_BASE 64 +@@ -2672,6 +2675,104 @@ static struct board_info __initdata boar + }; + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6362 ++static struct rtl8367_extif_config nb6_rtl8367_extif0_cfg = { ++ .mode = RTL8367_EXTIF_MODE_RGMII, ++ .txdelay = 1, ++ .rxdelay = 5, ++ .ability = { ++ .force_mode = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ .link = 1, ++ .duplex = 1, ++ .speed = RTL8367_PORT_SPEED_1000, ++ }, ++}; ++ ++static struct rtl8367_platform_data nb6_rtl8367_data = { ++ .gpio_sda = NB6_GPIO_RTL8367_SDA, ++ .gpio_sck = NB6_GPIO_RTL8367_SCK, ++ .extif0_cfg = &nb6_rtl8367_extif0_cfg, ++}; ++ ++static struct platform_device nb6_rtl8367_device = { ++ .name = RTL8367_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &nb6_rtl8367_data, ++ } ++}; ++ ++static struct platform_device * __initdata nb6_devices[] = { ++ &nb6_rtl8367_device, ++}; ++ ++static struct board_info __initdata board_nb6 = { ++ .name = "NB6", ++ .expected_cpu_id = 0x6362, ++ ++ .has_uart0 = 1, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [4] = { ++ .used = 1, ++ .phy_id = 0xff, ++ .bypass_link = 1, ++ .force_speed = 1000, ++ .force_duplex_full = 1, ++ .name = "RGMII", ++ }, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 24, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ .active_low = 1, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 25, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ .active_low = 1, ++ }, ++ { ++ .desc = "wlan", ++ .gpio = 12, ++ .type = EV_KEY, ++ .code = KEY_WLAN, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ .active_low = 1, ++ }, ++ { ++ .desc = "service", ++ .gpio = 10, ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ .active_low = 1, ++ }, ++ }, ++ ++ .devs = nb6_devices, ++ .num_devs = ARRAY_SIZE(nb6_devices), ++}; ++#endif ++ + /* + * known 6368 boards + */ +@@ -2878,6 +2979,10 @@ static const struct board_info __initcon + &board_DVAG3810BN, + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6362 ++ &board_nb6, ++#endif ++ + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, +@@ -2945,6 +3050,11 @@ static void __init boardid_fixup(u8 *boo + } + } + ++ if (BCMCPU_IS_6362() && (!strncmp(board_name, "NB6-", sizeof("NB6-") - 1))) { ++ board_name[sizeof("NB6") - 1] = '\0'; ++ return ; ++ } ++ + /* check if bcm_tag is at 64k offset */ + if (strncmp(board_name, tag->board_id, BOARDID_LEN) != 0) { + /* else try 128k */ diff --git a/target/linux/brcm63xx/patches-3.13/529-board_fast2604.patch b/target/linux/brcm63xx/patches-3.13/529-board_fast2604.patch new file mode 100644 index 0000000000..9ebc02ae5c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/529-board_fast2604.patch @@ -0,0 +1,68 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1066,6 +1066,57 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + }; + ++static struct board_info __initdata board_FAST2604 = { ++ .name = "F@ST2604", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "F@ST2604:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "F@ST2604:red:power", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "F@ST2604:red:inet", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "F@ST2604:green:wps", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 33, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_rta1025w_16 = { + .name = "RTA1025W_16", + .expected_cpu_id = 0x6348, +@@ -2947,6 +2998,7 @@ static const struct board_info __initcon + &board_96348gw_10, + &board_96348gw_11, + &board_FAST2404, ++ &board_FAST2604, + &board_DV201AMR, + &board_96348gw_a, + &board_rta1025w_16, diff --git a/target/linux/brcm63xx/patches-3.13/530-board_963281T_TEF.patch b/target/linux/brcm63xx/patches-3.13/530-board_963281T_TEF.patch new file mode 100644 index 0000000000..d490f28df1 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/530-board_963281T_TEF.patch @@ -0,0 +1,137 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -250,6 +250,126 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_963281T_TEF = { ++ .name = "963281T_TEF", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "963281T_TEF:green:power", ++ .gpio = 4, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "963281T_TEF:red:power", ++ .gpio = 8, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:green:inet", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:red:inet", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:green:ppp", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:red:ppp", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:green:3g", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:red:3g", ++ .gpio = 7, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:green:wlan", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:red:wlan", ++ .gpio = 10, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:green:eth", ++ .gpio = 31, ++ .active_low = 1, ++ }, ++ { ++ .name = "963281T_TEF:red:eth", ++ .gpio = 20, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 23, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wlan", ++ .gpio = 24, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WLAN, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_dsl_274xb_f1 = { + .name = "AW4339U", + .expected_cpu_id = 0x6328, +@@ -2979,6 +3099,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, + &board_963281TAN, ++ &board_963281T_TEF, + &board_dsl_274xb_f1, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 diff --git a/target/linux/brcm63xx/patches-3.13/531-board_96328A-1441N1.patch b/target/linux/brcm63xx/patches-3.13/531-board_96328A-1441N1.patch new file mode 100644 index 0000000000..12a08873b5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/531-board_96328A-1441N1.patch @@ -0,0 +1,90 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -180,6 +180,79 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_96328A_1441N1 = { ++ .name = "96328A-1441N1", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "96328A-1441N1:green:power", ++ .gpio = 8, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "96328A-1441N1:red:power", ++ .gpio = 4, ++ }, ++ { ++ .name = "96328A-1441N1:green:inet", ++ .gpio = 7, ++ }, ++ { ++ .name = "96328A-1441N1:red:inet", ++ .gpio = 1, ++ }, ++ { ++ .name = "96328A-1441N1:green:dsl", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 23, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_963281TAN = { + .name = "963281TAN", + .expected_cpu_id = 0x6328, +@@ -3098,6 +3171,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, ++ &board_96328A_1441N1, + &board_963281TAN, + &board_963281T_TEF, + &board_dsl_274xb_f1, diff --git a/target/linux/brcm63xx/patches-3.13/532-board_96328a-1241N.patch b/target/linux/brcm63xx/patches-3.13/532-board_96328a-1241N.patch new file mode 100644 index 0000000000..3648b2aa4e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/532-board_96328a-1241N.patch @@ -0,0 +1,84 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -180,6 +180,73 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_96328A_1241N = { ++ .name = "96328A-1241N", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "96328A-1241N:green:power", ++ .gpio = 4, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "96328A-1241N:red:alarm", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "96328A-1241N:green:inet", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 23, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_96328A_1441N1 = { + .name = "96328A-1441N1", + .expected_cpu_id = 0x6328, +@@ -3171,6 +3238,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, ++ &board_96328A_1241N, + &board_96328A_1441N1, + &board_963281TAN, + &board_963281T_TEF, diff --git a/target/linux/brcm63xx/patches-3.13/533-board_rta770bw.patch b/target/linux/brcm63xx/patches-3.13/533-board_rta770bw.patch new file mode 100644 index 0000000000..60a670f8cb --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/533-board_rta770bw.patch @@ -0,0 +1,66 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -788,6 +788,55 @@ static struct board_info __initdata boar + + .has_uart0 = 1, + }; ++ ++static struct board_info __initdata board_rta770bw = { ++ .name = "RTA770BW", ++ .expected_cpu_id = 0x6345, ++ ++ .has_uart0 = 1, ++ ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "RTA770BW:green:usb", ++ .gpio = 7, ++ .active_low = 1, ++ }, ++ { ++ .name = "RTA770BW:green:adsl", ++ .gpio = 8, ++ }, ++ { ++ .name = "RTA770BW:green:diag", ++ .gpio = 10, ++ .active_low = 1, ++ }, ++ { ++ .name = "RTA770BW:green:wlan", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 13, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; + #endif + + /* +@@ -3252,6 +3301,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, ++ &board_rta770bw, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, diff --git a/target/linux/brcm63xx/patches-3.13/534-board_hw556.patch b/target/linux/brcm63xx/patches-3.13/534-board_hw556.patch new file mode 100644 index 0000000000..af8c9d4d28 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/534-board_hw556.patch @@ -0,0 +1,565 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2901,6 +2901,492 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_HW556 = { ++ .name = "HW556", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .caldata_offset = 0xe00000, ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "HW556:red:message", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:hspa", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:dsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:power", ++ .gpio = 3, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "HW556:red:all", ++ .gpio = 6, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "help", ++ .gpio = 8, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_HELP, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wlan", ++ .gpio = 9, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WLAN, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "restart", ++ .gpio = 10, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "reset", ++ .gpio = 11, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_CONFIG, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++static struct board_info __initdata board_HW556_A = { ++ .name = "HW556_A", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_RALINK, ++ .caldata_offset = 0xeffe00, ++ .slot = 1, ++ .eeprom = "rt2x00.eeprom", ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "HW556:green:lan1", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:green:lan2", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:dsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:power", ++ .gpio = 3, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "HW556:red:message", ++ .gpio = 12, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan1", ++ .gpio = 13, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:hspa", ++ .gpio = 15, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan2", ++ .gpio = 22, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:green:lan3", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan3", ++ .gpio = 26, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:green:lan4", ++ .gpio = 27, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan4", ++ .gpio = 28, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "help", ++ .gpio = 8, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_HELP, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wlan", ++ .gpio = 9, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WLAN, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "restart", ++ .gpio = 10, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "reset", ++ .gpio = 11, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_CONFIG, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++static struct board_info __initdata board_HW556_B = { ++ .name = "HW556_B", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_ATHEROS, ++ .caldata_offset = 0xf7e000, ++ .slot = 1, ++ .endian_check = 1, ++ .led_pin = 2, ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "HW556:red:message", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:hspa", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:dsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:power", ++ .gpio = 3, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "HW556:red:all", ++ .gpio = 6, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "HW556:green:lan1", ++ .gpio = 12, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan1", ++ .gpio = 13, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:green:lan2", ++ .gpio = 15, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan2", ++ .gpio = 22, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:green:lan3", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan3", ++ .gpio = 26, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:green:lan4", ++ .gpio = 27, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan4", ++ .gpio = 28, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "help", ++ .gpio = 8, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_HELP, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wlan", ++ .gpio = 9, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WLAN, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "restart", ++ .gpio = 10, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "reset", ++ .gpio = 11, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_CONFIG, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++static struct board_info __initdata board_HW556_C = { ++ .name = "HW556_C", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_ATHEROS, ++ .caldata_offset = 0xefe000, ++ .slot = 1, ++ .endian_check = 1, ++ .led_pin = 2, ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "HW556:red:message", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:hspa", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:dsl", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:power", ++ .gpio = 3, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "HW556:red:all", ++ .gpio = 6, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "HW556:green:lan1", ++ .gpio = 12, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan1", ++ .gpio = 13, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:green:lan2", ++ .gpio = 15, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan2", ++ .gpio = 22, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:green:lan3", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan3", ++ .gpio = 26, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:green:lan4", ++ .gpio = 27, ++ .active_low = 1, ++ }, ++ { ++ .name = "HW556:red:lan4", ++ .gpio = 28, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "help", ++ .gpio = 8, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_HELP, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wlan", ++ .gpio = 9, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WLAN, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "restart", ++ .gpio = 10, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "reset", ++ .gpio = 11, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_CONFIG, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + /* T-Home Speedport W 303V Typ B */ + static struct board_info __initdata board_spw303v = { + .name = "96358-502V", +@@ -3340,6 +3826,10 @@ static const struct board_info __initcon + &board_nb4_fxc_r2, + &board_ct6373_1, + &board_HW553, ++ &board_HW556, ++ &board_HW556_A, ++ &board_HW556_B, ++ &board_HW556_C, + &board_spw303v, + &board_DVAG3810BN, + #endif +@@ -3405,13 +3895,37 @@ static void __init boardid_fixup(u8 *boo + struct bcm_tag *tag = (struct bcm_tag *)(boot_addr + CFE_OFFSET_64K); + char *board_name = (char *)bcm63xx_nvram_get_name(); + +- if (BCMCPU_IS_6358() && (!strcmp(board_name, "96358VW"))) { +- u8 *p = boot_addr + NB4_PID_OFFSET; +- +- /* Extract nb4 PID */ +- if (!memcmp(p, "NB4-", 4)) { +- memcpy(board_name, p, sizeof("NB4-XXX-rX")); +- return; ++ if (BCMCPU_IS_6358()) { ++ if (!strcmp(board_name, "96358VW")) { ++ u8 *p = boot_addr + NB4_PID_OFFSET; ++ ++ /* Extract nb4 PID */ ++ if (!memcmp(p, "NB4-", 4)) { ++ memcpy(board_name, p, sizeof("NB4-XXX-rX")); ++ return; ++ } ++ } else if (!strcmp(board_name, "HW556")) { ++ /* ++ * HW556 has different wlan caldatas depending on ++ * hardware version. ++ * Detect hardware version and change board id ++ */ ++ u8 cal_data_ath9k[4] = { 0xa5, 0x5a, 0, 0 }; ++ u8 cal_data_rt3062[4] = { 0x62, 0x30, 1, 0 }; ++ ++ if (!memcmp(boot_addr + 0xeffe00, ++ &cal_data_rt3062, 4)) { ++ /* Ralink 0xeffe00 */ ++ memcpy(board_name, "HW556_A", 7); ++ } else if (!memcmp(boot_addr + 0xf7e000, ++ &cal_data_ath9k, 4)) { ++ /* Atheros 0xf7e000 */ ++ memcpy(board_name, "HW556_B", 7); ++ } else if (!memcmp(boot_addr + 0xefe000, ++ &cal_data_ath9k, 4)) { ++ /* Atheros 0xefe000 */ ++ memcpy(board_name, "HW556_C", 7); ++ } + } + } + +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -70,6 +70,11 @@ static int bcm63xx_parse_cfe_partitions( + BCM63XX_CFE_BLOCK_SIZE); + + cfelen = cfe_erasesize; ++ ++ /* Fix HW556 MX29LV128DB */ ++ if (!strncmp(bcm63xx_nvram_get_name(), "HW556", 5)) ++ cfelen = 0x20000; ++ + nvramlen = bcm63xx_nvram_get_psi_size() * SZ_1K; + nvramlen = roundup(nvramlen, cfe_erasesize); + nvramaddr = master->size - nvramlen; diff --git a/target/linux/brcm63xx/patches-3.13/535-board_rta770w.patch b/target/linux/brcm63xx/patches-3.13/535-board_rta770w.patch new file mode 100644 index 0000000000..6e0cd69a42 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/535-board_rta770w.patch @@ -0,0 +1,71 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -776,6 +776,60 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++// Actually this board is the very same as the rta770bw, ++// where the additional 'b' within the name just ++// just indicates 'Annex B'. The ADSL Modem itself is able ++// to handle both Annex A as well as Annex B - ++// the loaded firmware makes the only difference ++static struct board_info __initdata board_rta770w = { ++ .name = "RTA770W", ++ .expected_cpu_id = 0x6345, ++ ++ .has_uart0 = 1, ++ ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "RTA770W:green:usb", ++ .gpio = 7, ++ .active_low = 1, ++ }, ++ { ++ .name = "RTA770W:green:adsl", ++ .gpio = 8, ++ }, ++ { ++ .name = "RTA770W:green:diag", ++ .gpio = 10, ++ .active_low = 1, ++ }, ++ { ++ .name = "RTA770W:green:wlan", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 13, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .active_low = 1, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; + #endif + + /* +@@ -3788,6 +3842,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, + &board_rta770bw, ++ &board_rta770w, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, diff --git a/target/linux/brcm63xx/patches-3.13/536-board_fast2704.patch b/target/linux/brcm63xx/patches-3.13/536-board_fast2704.patch new file mode 100644 index 0000000000..bb035df581 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/536-board_fast2704.patch @@ -0,0 +1,145 @@ +From: Marcin Jurkowski <marcin1j@gmail.com> +Date: Thu, 31 Oct 2013 22:33:10 +0000 +Subject: [PATCH] bcm63xx: Add kernel support for Sagemcom F@ST2704V2 ADSL + router + +This adds kernel support support for Sagemcom F@st 2704 wireless ADSL +router. +It's a BCM6328-based 802.11n wireless router with USB port and ADSL2+ +modem equipped with 64 MiB RAM and 8 MiB flash. + +Signed-off-by: Marcin Jurkowski <marcin1j@gmail.com> +--- +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1480,6 +1480,122 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_FAST2704V2 = { ++ .name = "F@ST2704V2", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .has_usbd = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ /* front LEDs */ ++ { ++ .name = "F@ST2704V2:green:power", ++ .gpio = 4, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "F@ST2704V2:red:power", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "F@ST2704V2:red:inet", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "F@ST2704V2:green:dsl", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "F@ST2704V2:green:inet", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ { ++ .name = "F@ST2704V2:green:usb", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ ++ /* side button LEDs */ ++ { ++ .name = "F@ST2704V2:green:wps", ++ .gpio = 10, ++ .active_low = 1, ++ }, ++ ++ /* FIXME: can't control gpio0 line in "out" state, needs further investigation */ ++ /* ++ { ++ .name = "F@ST2704V2:green:rfkill", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ */ ++ ++ }, ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 23, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 24, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "rfkill", ++ .gpio = 15, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WLAN, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_rta1025w_16 = { + .name = "RTA1025W_16", + .expected_cpu_id = 0x6348, +@@ -3832,6 +3948,7 @@ static const struct board_info __initcon + &board_963281TAN, + &board_963281T_TEF, + &board_dsl_274xb_f1, ++ &board_FAST2704V2, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, diff --git a/target/linux/brcm63xx/patches-3.13/537-board_fast2504n.patch b/target/linux/brcm63xx/patches-3.13/537-board_fast2504n.patch new file mode 100644 index 0000000000..d8b65a57cd --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/537-board_fast2504n.patch @@ -0,0 +1,113 @@ +From: Max Staudt <openwrt.max@enpas.org> +Date: Wed, 15 Jan 2014 18:51:13 +0000 +Subject: [PATCH] brcm63xx: F@ST2504n board support (Linux-3.10.26) + +Signed-off-by: Max Staudt <openwrt.max@enpas.org> +--- +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -3787,6 +3787,96 @@ static struct board_info __initdata boar + .devs = nb6_devices, + .num_devs = ARRAY_SIZE(nb6_devices), + }; ++ ++static struct board_info __initdata board_fast2504n = { ++ .name = "F@ST2504n", ++ .expected_cpu_id = 0x6362, ++ ++ .has_uart0 = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "fast2504n:orange:power", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "fast2504n:green:power", ++ .gpio = 10, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "fast2504n:red:internet", ++ .gpio = 26, ++ .active_low = 1, ++ }, ++ { ++ .name = "fast2504n:green:ok", ++ .gpio = 28, ++ .active_low = 1, ++ }, ++ { ++ .name = "fast2504n:orange:ok", ++ .gpio = 29, ++ .active_low = 1, ++ }, ++ { ++ .name = "fast2504n:orange:wlan", ++ .gpio = 30, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 24, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ .active_low = 1, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 25, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ .active_low = 1, ++ }, ++ }, ++}; + #endif + + /* +@@ -4008,6 +4098,7 @@ static const struct board_info __initcon + + #ifdef CONFIG_BCM63XX_CPU_6362 + &board_nb6, ++ &board_fast2504n, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6368 diff --git a/target/linux/brcm63xx/patches-3.13/550-alice_gate2_leds.patch b/target/linux/brcm63xx/patches-3.13/550-alice_gate2_leds.patch new file mode 100644 index 0000000000..8235396954 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/550-alice_gate2_leds.patch @@ -0,0 +1,102 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2211,6 +2211,99 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + .has_ehci0 = 1, ++ ++ .leds = { ++ { ++ .name = "AGPF-S0:red:power", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:green:power", ++ .gpio = 4, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "AGPF-S0:red:service", ++ .gpio = 7, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:green:service", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:green:adsl", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:red:adsl", ++ .gpio = 10, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:red:wifi", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:green:wifi", ++ .gpio = 22, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:green:internet", ++ .gpio = 25, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:red:internet", ++ .gpio = 24, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:red:usr1", ++ .gpio = 27, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:green:usr1", ++ .gpio = 26, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:red:usr2", ++ .gpio = 30, ++ .active_low = 1, ++ }, ++ { ++ .name = "AGPF-S0:green:usr2", ++ .gpio = 29, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 37, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 34, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, + }; + + static struct board_info __initdata board_DWVS0 = { diff --git a/target/linux/brcm63xx/patches-3.13/551-96348gw_a_leds.patch b/target/linux/brcm63xx/patches-3.13/551-96348gw_a_leds.patch new file mode 100644 index 0000000000..07fceaaeb8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/551-96348gw_a_leds.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1655,6 +1655,19 @@ static struct board_info __initdata boar + }, + + .has_ohci0 = 1, ++ ++ .leds = { ++ { ++ .name = "96348GW-A::adsl", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "96348GW-A::usb", ++ .gpio = 0, ++ .active_low = 1, ++ } ++ }, + }; + + static struct board_info __initdata board_96348_D4PW = { diff --git a/target/linux/brcm63xx/patches-3.13/552-board_96348gw-10_reset_button.patch b/target/linux/brcm63xx/patches-3.13/552-board_96348gw-10_reset_button.patch new file mode 100644 index 0000000000..7a310390e2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/552-board_96348gw-10_reset_button.patch @@ -0,0 +1,20 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -999,6 +999,17 @@ static struct board_info __initdata boar + .active_low = 1, + }, + }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 6, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, + }; + + static struct board_info __initdata board_96348gw_11 = { diff --git a/target/linux/brcm63xx/patches-3.13/553-boards_probe_switch.patch b/target/linux/brcm63xx/patches-3.13/553-boards_probe_switch.patch new file mode 100644 index 0000000000..6d3072deef --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/553-boards_probe_switch.patch @@ -0,0 +1,105 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -627,6 +627,8 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_enet0 = 1, + .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -670,6 +672,8 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_enet0 = 1, + .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -955,6 +959,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -1027,6 +1033,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -1256,6 +1264,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -1431,6 +1441,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -1621,6 +1633,12 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .has_phy = 1, ++ .phy_id = 0, ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -2036,6 +2054,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -2088,6 +2108,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -2229,6 +2251,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -2346,6 +2370,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, diff --git a/target/linux/brcm63xx/patches-3.13/554-board_DWVS0_leds_buttons.patch b/target/linux/brcm63xx/patches-3.13/554-board_DWVS0_leds_buttons.patch new file mode 100644 index 0000000000..e21274c98a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/554-board_DWVS0_leds_buttons.patch @@ -0,0 +1,97 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2378,6 +2378,94 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + .has_ehci0 = 1, ++ ++ .leds = { ++ { ++ .name = "DWV-S0:red:power", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:green:power", ++ .gpio = 4, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ { ++ .name = "DWV-S0:red:internet", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:green:internet", ++ .gpio = 7, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:green:ADSL", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:red:ADSL", ++ .gpio = 12, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:red:wifi", ++ .gpio = 10, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:green:VoIP", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:red:VoIP", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:red:ethernet", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:green:ethernet", ++ .gpio = 8, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:red:USB", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ { ++ .name = "DWV-S0:green:USB", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 37, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 34, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, + }; + + /* D-Link DSL-274xB revison C2/C3 */ diff --git a/target/linux/brcm63xx/patches-3.13/555-board_96318ref.patch b/target/linux/brcm63xx/patches-3.13/555-board_96318ref.patch new file mode 100644 index 0000000000..5bcfc4cedc --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/555-board_96318ref.patch @@ -0,0 +1,106 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -102,6 +102,93 @@ static struct board_info __initdata boar + #endif + + /* ++ * known 6318 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_6318 ++static struct board_info __initdata board_96318ref = { ++ .name = "96318REF", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "96318REF:red:post-failed", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ { ++ .name = "96318REF:green:inet", ++ .gpio = 8, ++ .active_low = 1, ++ }, ++ { ++ .name = "96318REF:red:inet-fail", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "wps", ++ .gpio = 33, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "reset", ++ .gpio = 34, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++#endif ++ ++/* + * known 6328 boards + */ + #ifdef CONFIG_BCM63XX_CPU_6328 +@@ -4262,6 +4349,9 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_3368 + &board_cvg834g, + #endif ++#ifdef CONFIG_BCM63XX_CPU_6318 ++ &board_96318ref, ++#endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, + &board_96328A_1241N, diff --git a/target/linux/brcm63xx/patches-3.13/556-board_96318ref_p300.patch b/target/linux/brcm63xx/patches-3.13/556-board_96318ref_p300.patch new file mode 100644 index 0000000000..4cd8c9b1d9 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/556-board_96318ref_p300.patch @@ -0,0 +1,105 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -186,6 +186,94 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_96318ref_p300 = { ++ .name = "96318REF_P300", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "96318REF_P300:red:post-failed", ++ .gpio = 11, ++ .active_low = 1, ++ }, ++ { ++ .name = "96318REF_P300:green:inet", ++ .gpio = 8, ++ .active_low = 1, ++ }, ++ { ++ .name = "96318REF_P300:red:inet-fail", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "96318REF_P300::usb-pwron", ++ .gpio = 13, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "wps", ++ .gpio = 33, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "reset", ++ .gpio = 34, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; + #endif + + /* +@@ -4351,6 +4439,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6318 + &board_96318ref, ++ &board_96318ref_p300, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, diff --git a/target/linux/brcm63xx/patches-3.13/557-board_bcm963269bhr.patch b/target/linux/brcm63xx/patches-3.13/557-board_bcm963269bhr.patch new file mode 100644 index 0000000000..1e62d5651a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/557-board_bcm963269bhr.patch @@ -0,0 +1,88 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -4431,6 +4431,75 @@ static struct board_info __initdata boar + #endif + + /* ++ * known 63268/63269 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_63268 ++static struct board_info __initdata board_963269bhr = { ++ .name = "963269BHR", ++ .expected_cpu_id = 0x63268, ++ ++ .has_uart0 = 1, ++ ++ .has_pci = 1, ++ ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "963629BHR:green:usb1", ++ .gpio = 9, ++ .active_low = 1, ++ }, ++ { ++ .name = "963629BHR:green:usb2", ++ .gpio = 10, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 32, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++#endif ++ ++/* + * all boards + */ + static const struct board_info __initconst *bcm963xx_boards[] = { +@@ -4515,6 +4584,9 @@ static const struct board_info __initcon + &board_96368mvwg, + &board_96368mvngr, + #endif ++#ifdef CONFIG_BCM63XX_CPU_63268 ++ &board_963269bhr, ++#endif + }; + + /* diff --git a/target/linux/brcm63xx/patches-3.13/558-board_AR1004G.patch b/target/linux/brcm63xx/patches-3.13/558-board_AR1004G.patch new file mode 100644 index 0000000000..8b2b1ee04a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/558-board_AR1004G.patch @@ -0,0 +1,70 @@ +From: "mexit@o2.pl" <mexit@o2.pl> +Date: Sun, 24 Nov 2013 21:33:38 +0000 +Subject: [PATCH 4/5] brcm63xx: add support for Asmax AR 1004g router + +Support for Asmax AR 1004g router + +Signed-off-by: Adrian Feliks <mexit@o2.pl> +--- +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2208,6 +2208,51 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_96348gw_10_AR1004G = { ++ .name = "AR1004G", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .leds = { ++ { ++ .name = "AR1004G:green:inet", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "AR1004G:green:power", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "AR1004G:red:power", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 33, ++ .active_low = 1, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + #endif + + /* +@@ -4551,6 +4596,7 @@ static const struct board_info __initcon + &board_96348A_122, + &board_CPVA502plus, + &board_96348W3, ++ &board_96348gw_10_AR1004G, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 diff --git a/target/linux/brcm63xx/patches-3.13/559-board_vw6339gu.patch b/target/linux/brcm63xx/patches-3.13/559-board_vw6339gu.patch new file mode 100644 index 0000000000..298a04a252 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/559-board_vw6339gu.patch @@ -0,0 +1,119 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -4542,6 +4542,108 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_vw6339gu = { ++ .name = "VW6339GU", ++ .expected_cpu_id = 0x63268, ++ ++ .has_uart0 = 1, ++ ++ .has_ehci0 = 1, ++ .has_ohci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "LAN2", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "LAN3", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "LAN4", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "LAN1", ++ }, ++ ++ [4] = { ++ .used = 1, ++ .phy_id = 7, ++ .name = "WAN", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "VW6339GU:green:power", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "VW6339GU:red:power", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "VW6339GU:green:internet", ++ .gpio = 8, ++ .active_low = 1, ++ }, ++ { ++ .name = "VW6339GU:red:internet", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "VW6339GU:green:dsl", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "VW6339GU:green:wps", ++ .gpio = 7, ++ .active_low = 1, ++ }, ++ { ++ .name = "VW6339GU:green:usb", ++ .gpio = 15, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 32, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 34, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; + #endif + + /* +@@ -4632,6 +4734,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + &board_963269bhr, ++ &board_vw6339gu, + #endif + }; + diff --git a/target/linux/brcm63xx/patches-3.13/560-board_963268gu_p300.patch b/target/linux/brcm63xx/patches-3.13/560-board_963268gu_p300.patch new file mode 100644 index 0000000000..afaf983501 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/560-board_963268gu_p300.patch @@ -0,0 +1,142 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -4479,6 +4479,131 @@ static struct board_info __initdata boar + * known 63268/63269 boards + */ + #ifdef CONFIG_BCM63XX_CPU_63268 ++static struct board_info __initdata board_963268bu_p300 = { ++ .name = "963268BU_P300", ++ .expected_cpu_id = 0x63268, ++ ++ .has_uart0 = 1, ++ ++ .has_ehci0 = 1, ++ .has_ohci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 17, ++ .name = "FE1", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "GbE2", ++ }, ++ ++ [4] = { ++ .used = 1, ++ .phy_id = 0, ++ .name = "GbE3", ++ }, ++ ++ [5] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "GbE1", ++ }, ++ ++ [6] = { ++ .used = 1, ++ .phy_id = 24, ++ .name = "GbE4", ++ }, ++ ++ [7] = { ++ .used = 1, ++ .phy_id = 25, ++ .name = "GbE5", ++ }, ++ }, ++ }, ++ ++ .leds = { ++ { ++ .name = "963268BU_P300:green:power", ++ .gpio = 20, ++ .active_low = 1, ++ }, ++ { ++ .name = "963268BU_P300:red:power", ++ .gpio = 21, ++ .active_low = 1, ++ }, ++ { ++ .name = "963268BU_P300:green:internet", ++ .gpio = 8, ++ .active_low = 1, ++ }, ++ { ++ .name = "963268BU_P300:red:internet", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "963268BU_P300:green:adsl", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "963268BU_P300:green:wps", ++ .gpio = 7, ++ .active_low = 1, ++ }, ++ { ++ .name = "963268BU_P300:green:voip1", ++ .gpio = 4, ++ .active_low = 1, ++ }, ++ { ++ .name = "963268BU_P300:green:voip2", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "963268BU_P300:green:pots", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ }, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 32, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 33, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_963269bhr = { + .name = "963269BHR", + .expected_cpu_id = 0x63268, +@@ -4733,6 +4858,7 @@ static const struct board_info __initcon + &board_96368mvngr, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 ++ &board_963268bu_p300, + &board_963269bhr, + &board_vw6339gu, + #endif diff --git a/target/linux/brcm63xx/patches-3.13/800-wl_exports.patch b/target/linux/brcm63xx/patches-3.13/800-wl_exports.patch new file mode 100644 index 0000000000..0fa42fd77c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/800-wl_exports.patch @@ -0,0 +1,34 @@ +--- a/arch/mips/bcm63xx/nvram.c ++++ b/arch/mips/bcm63xx/nvram.c +@@ -40,6 +40,13 @@ struct bcm963xx_nvram { + static struct bcm963xx_nvram nvram; + static int mac_addr_used; + ++/* ++ * Required export for WL ++ */ ++#define NVRAM_SPACE 0x8000 ++char nvram_buf[NVRAM_SPACE]; ++EXPORT_SYMBOL(nvram_buf); ++ + void __init bcm63xx_nvram_init(void *addr) + { + unsigned int check_len; +@@ -48,6 +55,7 @@ void __init bcm63xx_nvram_init(void *add + + /* extract nvram data */ + memcpy(&nvram, addr, sizeof(nvram)); ++ memcpy(&nvram_buf, addr, NVRAM_SPACE); + + /* check checksum before using data */ + if (nvram.version <= 4) { +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -59,6 +59,7 @@ void (*_dma_cache_wback)(unsigned long s + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + + EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_inv); + + #endif /* CONFIG_DMA_NONCOHERENT */ + diff --git a/target/linux/brcm63xx/patches-3.13/801-ssb_export_fallback_sprom.patch b/target/linux/brcm63xx/patches-3.13/801-ssb_export_fallback_sprom.patch new file mode 100644 index 0000000000..b3ced8d5a2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/801-ssb_export_fallback_sprom.patch @@ -0,0 +1,27 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -14,6 +14,7 @@ + #include <linux/ssb/ssb.h> + #include <linux/gpio_keys.h> + #include <linux/input.h> ++#include <linux/export.h> + #include <linux/spi/spi.h> + #include <linux/spi/spi_gpio.h> + #include <linux/spi/74x164.h> +@@ -4869,7 +4870,7 @@ static const struct board_info __initcon + * bcm4318 WLAN work + */ + #ifdef CONFIG_SSB_PCIHOST +-static struct ssb_sprom bcm63xx_sprom = { ++struct ssb_sprom bcm63xx_sprom = { + .revision = 0x02, + .board_rev = 0x17, + .country_code = 0x0, +@@ -4889,6 +4890,7 @@ static struct ssb_sprom bcm63xx_sprom = + .boardflags_lo = 0x2848, + .boardflags_hi = 0x0000, + }; ++EXPORT_SYMBOL(bcm63xx_sprom); + + int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) + { diff --git a/target/linux/brcm63xx/patches-3.13/802-rtl8367r_fix_RGMII_support.patch b/target/linux/brcm63xx/patches-3.13/802-rtl8367r_fix_RGMII_support.patch new file mode 100644 index 0000000000..9037d8954a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.13/802-rtl8367r_fix_RGMII_support.patch @@ -0,0 +1,30 @@ +From e3208e6087642b95a5bab3101fc9c6e34892c861 Mon Sep 17 00:00:00 2001 +From: Miguel GAIO <miguel.gaio@efixo.com> +Date: Fri, 6 Jul 2012 14:12:33 +0200 +Subject: [PATCH 6/8] * [rtl8367r] Fix RGMII support + +--- + drivers/net/phy/rtl8367.c | 5 +++++ + 1 files changed, 5 insertions(+), 0 deletions(-) + +--- a/drivers/net/phy/rtl8367.c ++++ b/drivers/net/phy/rtl8367.c +@@ -146,6 +146,10 @@ + #define RTL8367_EXT_RGMXF_TXDELAY_MASK 1 + #define RTL8367_EXT_RGMXF_RXDELAY_MASK 0x7 + ++#define RTL8367_PHY_AD_REG 0x130f ++#define RTL8370_PHY_AD_DUMMY_1_OFFSET 5 ++#define RTL8370_PHY_AD_DUMMY_1_MASK 0xe0 ++ + #define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x)) + #define RTL8367_DI_FORCE_MODE BIT(12) + #define RTL8367_DI_FORCE_NWAY BIT(7) +@@ -894,6 +898,7 @@ static int rtl8367_extif_set_mode(struct + case RTL8367_EXTIF_MODE_RGMII_33V: + REG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367); + REG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777); ++ REG_RMW(smi, RTL8367_PHY_AD_REG, BIT(5), 0); + break; + + case RTL8367_EXTIF_MODE_TMII_MAC: |