package/boot/uboot-lantiq/patches/0017-tools-add-some-helper-tools-for-Lantiq-SoCs.patch

   1 From 1da5479d59b39d7931a2b0efabdfa314f6788b6d Mon Sep 17 00:00:00 2001
   2 From: Luka Perkov <luka@openwrt.org>
   3 Date: Sat, 2 Mar 2013 23:34:00 +0100
   4 Subject: tools: add some helper tools for Lantiq SoCs
   5
   6 Signed-off-by: Luka Perkov Luka Perkov <luka@openwrt.org>
   7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
   8
   9 diff --git a/tools/gct.pl b/tools/gct.pl
  10 new file mode 100755
  11 index 0000000..33fa6f7
  12 --- /dev/null
  13 +++ b/tools/gct.pl
  14 @@ -0,0 +1,155 @@
  15 +#!/usr/bin/perl
  16 +
  17 +#use strict;
  18 +#use Cwd;
  19 +#use Env;
  20 +
  21 +my $aline;
  22 +my $lineid;
  23 +my $length;
  24 +my $address;
  25 +my @bytes;
  26 +my $addstr;
  27 +my $chsum=0;
  28 +my $count=0;
  29 +my $firstime=1;
  30 +my $i;
  31 +my $currentaddr;
  32 +my $tmp;
  33 +my $holder="";
  34 +my $loadaddr;
  35 +
  36 +if(@ARGV < 2){
  37 +       die("\n Syntax: perl gct.pl uart_ddr_settings.conf u-boot.srec u-boot.asc\n");
  38 +}
  39 +
  40 +open(IN_UART_DDR_SETTINGS, "<$ARGV[0]") || die("failed to open uart_ddr_settings.conf\n");
  41 +open(IN_UART_SREC, "<$ARGV[1]") || die("failed to open u-boot.srec\n");
  42 +open(OUT_UBOOT_ASC, ">$ARGV[2]") || die("failed to open u-boot.asc\n");
  43 +
  44 +$i=0;
  45 +while ($line = <IN_UART_DDR_SETTINGS>){
  46 +       if($line=~/\w/){
  47 +               if($line!~/[;#\*]/){
  48 +                       if($i eq 0){
  49 +                               printf OUT_UBOOT_ASC ("33333333");
  50 +                       }
  51 +                       chomp($line);
  52 +                       $line=~s/\t//;
  53 +                       @array=split(/ +/,$line);
  54 +                       $j=0;
  55 +                       while(@array[$j]!~/\w/){
  56 +                               $j=$j+1;
  57 +                       }
  58 +                       $addr=@array[$j];
  59 +                       $regval=@array[$j+1];
  60 +                       $addr=~s/0x//;
  61 +                       $regval=~s/0x//;
  62 +                       printf OUT_UBOOT_ASC ("%08x%08x",hex($addr),hex($regval));
  63 +                       $i=$i+1;
  64 +                       if($i eq 8){
  65 +                               $i=0;
  66 +                               printf OUT_UBOOT_ASC ("\n");
  67 +                       }
  68 +               }
  69 +       }
  70 +}
  71 +
  72 +while($i lt 8 && $i gt 0){
  73 +       printf OUT_UBOOT_ASC "00"x8;
  74 +       $i=$i+1;
  75 +}
  76 +
  77 +if($i eq 8){
  78 +       printf OUT_UBOOT_ASC ("\n");
  79 +}
  80 +
  81 +while($aline=<IN_UART_SREC>){
  82 +       $aline=uc($aline);
  83 +       chomp($aline);
  84 +       next if(($aline=~/^S0/) || ($aline=~/^S7/));
  85 +       ($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline;
  86 +       $length = hex($length);
  87 +       $address = hex($address);
  88 +       $length -=5;
  89 +       $i=0;
  90 +
  91 +       while($length>0){
  92 +               if($firstime==1){
  93 +                       $addstr = sprintf("%x", $address);
  94 +                       $addstr = "0"x(8-length($addstr)).$addstr;
  95 +                       print OUT_UBOOT_ASC $addstr;
  96 +                       addchsum($addstr);
  97 +                       $firstime=0;
  98 +                       $currentaddr=$address;
  99 +                       $loadaddr = $addstr;
 100 +               }
 101 +               else{
 102 +                       if($count==64){
 103 +                               $addstr = sprintf("%x", $currentaddr);
 104 +                               $addstr = "0"x(8-length($addstr)).$addstr;
 105 +                               print OUT_UBOOT_ASC $addstr;
 106 +                               addchsum($addstr);
 107 +                               $count=0;
 108 +                       }
 109 +#printf("*** %x != %x\n", $address, $currentaddr) if $address != $currentaddr;
 110 +               }
 111 +               if($currentaddr < $address) {
 112 +                       print OUT_UBOOT_ASC "00";
 113 +                       addchsum("00");
 114 +                       $count++;
 115 +                       $currentaddr++;
 116 +               }
 117 +               else {
 118 +                       while($count<64){
 119 +                               $bytes[$i]=~tr/ABCDEF/abcdef/;
 120 +                               print OUT_UBOOT_ASC "$bytes[$i]";
 121 +                               addchsum($bytes[$i]);
 122 +                               $i++;
 123 +                               $count++;
 124 +                               $currentaddr++;
 125 +                               $length--;
 126 +                               last if($length==0);
 127 +                       }
 128 +               }
 129 +               if($count==64){
 130 +                       print OUT_UBOOT_ASC "\n";
 131 +               }
 132 +       }
 133 +}
 134 +if($count != 64){
 135 +       $tmp = "00";
 136 +       for($i=0;$i<(64-$count);$i++){
 137 +               print OUT_UBOOT_ASC "00";
 138 +               addchsum($tmp);
 139 +       }
 140 +       print OUT_UBOOT_ASC "\n";
 141 +}
 142 +
 143 +
 144 +print OUT_UBOOT_ASC "11"x4;
 145 +use integer;
 146 +$chsum=$chsum & 0xffffffff;
 147 +$chsum = sprintf("%X", $chsum);
 148 +$chsum = "0"x(8-length($chsum)).$chsum;
 149 +$chsum =~tr/ABCDEF/abcdef/;
 150 +print OUT_UBOOT_ASC $chsum;
 151 +print OUT_UBOOT_ASC "00"x60;
 152 +print OUT_UBOOT_ASC "\n";
 153 +
 154 +print OUT_UBOOT_ASC "99"x4;
 155 +print OUT_UBOOT_ASC $loadaddr;
 156 +print OUT_UBOOT_ASC "00"x60;
 157 +print OUT_UBOOT_ASC "\n";
 158 +
 159 +close OUT_UBOOT_ASC;
 160 +
 161 +sub addchsum{
 162 +       my $cc=$_[0];
 163 +       $holder=$holder.$cc;
 164 +       if(length($holder)==8){
 165 +               $holder = hex($holder);
 166 +               $chsum+=$holder;
 167 +               $holder="";
 168 +       }
 169 +}
 170 diff --git a/tools/lantiq_bdi_conf.awk b/tools/lantiq_bdi_conf.awk
 171 new file mode 100755
 172 index 0000000..c732289
 173 --- /dev/null
 174 +++ b/tools/lantiq_bdi_conf.awk
 175 @@ -0,0 +1,116 @@
 176 +#!/usr/bin/awk -f
 177 +#
 178 +# Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
 179 +# Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 180 +#
 181 +# Usage:
 182 +#  awk -f lantiq_bdi_conf.awk -v soc=ar9 board=<name> PATH_TO_BOARD/ddr_settings.h
 183 +#
 184 +# Additional information:
 185 +#  http://www.abatron.ch/fileadmin/user_upload/products/pdf/ManGDBR4K-3000.pdf
 186 +#
 187 +# SPDX-License-Identifier:     GPL-2.0+
 188 +#
 189 +
 190 +function print_header()
 191 +{
 192 +       print ";                                                                         "
 193 +       print "; Copyright (C) 2013 Luka Perkov <luka@openwrt.org>                       "
 194 +       print "; Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>    "
 195 +       print ";                                                                         "
 196 +       print "; This file has been generated with lantiq_bdi_conf.awk script.           "
 197 +       print ";                                                                         "
 198 +       print "; SPDX-License-Identifier:       GPL-2.0+                                 "
 199 +       print ";                                                                         "
 200 +       print ""
 201 +}
 202 +
 203 +function init_ar9_prologue()
 204 +{
 205 +       print "WM32 0xBF103010 0x80             ; CGU for CPU 333Mhz, DDR 167Mhz"
 206 +       print "WM32 0xBF103014 0x01             ; CGU update"
 207 +       print "WM32 0xBF800010 0x0              ; Clear error access log register"
 208 +       print "WM32 0xBF800020 0x0              ; Clear error access log register"
 209 +       print "WM32 0xBF800060 0xD              ; Enable FPI, DDR and SRAM module in memory controller"
 210 +       print "WM32 0xBF801030 0x0              ; Clear start bit of DDR memory controller"
 211 +}
 212 +
 213 +function init_ar9_epilogue()
 214 +{
 215 +       print "WM32 0xBE105360 0x4001D7FF       ; EBU setup"
 216 +}
 217 +
 218 +function init_ddr1_epilogue()
 219 +{
 220 +       print "WM32 0xBF801030 0x100            ; Set start bit of DDR memory controller"
 221 +}
 222 +
 223 +function ar9_target()
 224 +{
 225 +       print "CPUTYPE          M34K"
 226 +       print "ENDIAN           BIG"
 227 +       print "JTAGCLOCK        1"
 228 +       print "BDIMODE          AGENT           ; [ LOADONLY, AGENT ]"
 229 +       print "RESET            JTAG            ; [ NONE, JTAG, HARD ]"
 230 +       print "POWERUP          100"
 231 +       print "WAKEUP           100"
 232 +       print "BREAKMODE        HARD            ; [ SOFT, HARD ]"
 233 +       print  "STEPMODE        SWBP            ; [ JTAG, HWBP, SWBP ]"
 234 +       print "VECTOR           CATCH"
 235 +       print  "SCANSUCC        1 5"
 236 +}
 237 +
 238 +function flash_p2601hnfx()
 239 +{
 240 +       print "CHIPTYPE MIRRORX16"
 241 +       print "CHIPSIZE 0x1000000"
 242 +       print "BUSWIDTH 16"
 243 +}
 244 +
 245 +BEGIN {
 246 +       switch (soc) {
 247 +       case "ar9":
 248 +               reg_base = 0xbf801000
 249 +               print_header()
 250 +               print "[INIT]"
 251 +               init_ar9_prologue()
 252 +               break
 253 +       default:
 254 +               print "Invalid or no value for SoC specified!"
 255 +               exit 1
 256 +       }
 257 +}
 258 +
 259 +/^#define/ {
 260 +       /* DC03 contains MC enable bit and must not be set here */
 261 +       if (tolower($2) != "mc_dc03_value")
 262 +               printf("WM32 0x%x %s\n", reg_base, tolower($3))
 263 +
 264 +       reg_base += 0x10
 265 +}
 266 +
 267 +END {
 268 +       switch (soc) {
 269 +       case "ar9":
 270 +               init_ddr1_epilogue()
 271 +               init_ar9_epilogue()
 272 +               print ""
 273 +               print "[TARGET]"
 274 +               ar9_target()
 275 +               print ""
 276 +               print "[HOST]"
 277 +               print "PROMPT           \"ar9> \""
 278 +               print ""
 279 +               break
 280 +       default:
 281 +       }
 282 +
 283 +       switch (board) {
 284 +       case "p2601hnfx":
 285 +               print "[FLASH]"
 286 +               flash_p2601hnfx()
 287 +               print ""
 288 +               break
 289 +       default:
 290 +       }
 291 +}
 292 diff --git a/tools/lantiq_ram_extract_magic.awk b/tools/lantiq_ram_extract_magic.awk
 293 new file mode 100755
 294 index 0000000..64f1cbc
 295 --- /dev/null
 296 +++ b/tools/lantiq_ram_extract_magic.awk
 297 @@ -0,0 +1,69 @@
 298 +#
 299 +# Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
 300 +#
 301 +# Usage:
 302 +# mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk
 303 +#
 304 +# SPDX-License-Identifier:     GPL-2.0+
 305 +#
 306 +
 307 +BEGIN {
 308 +       print "/*                                                                            "
 309 +       print " * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>                     "
 310 +       print " *                                                                            "
 311 +       print " * This file has been generated with lantiq_ram_extract_magic.awk script.     "
 312 +       print " *                                                                            "
 313 +       print " * SPDX-License-Identifier:      GPL-2.0+                                     "
 314 +       print " */                                                                           "
 315 +       print ""
 316 +
 317 +       mc_dc_value=0
 318 +       mc_dc_number=0
 319 +       right_section=0
 320 +       mc_dc_value_print=0
 321 +       mc_dc_number_print=0
 322 +}
 323 +
 324 +/t2,[0-9]+$/ {
 325 +       if (right_section) {
 326 +               split($4, tmp, ",")
 327 +               mc_dc_value=sprintf("%X", tmp[2])
 328 +               mc_dc_value_print=1
 329 +       }
 330 +}
 331 +
 332 +/t2,0x[0-9a-f]+$/ {
 333 +       if (right_section) {
 334 +               split($4, tmp, ",0x")
 335 +               mc_dc_value=sprintf("%s", tmp[2])
 336 +               mc_dc_value=toupper(mc_dc_value)
 337 +               mc_dc_value_print=1
 338 +       }
 339 +}
 340 +
 341 +/t2,[0-9]+\(t1\)$/ {
 342 +       if (right_section) {
 343 +               split($4, tmp, ",")
 344 +               split(tmp[2], tmp, "(")
 345 +               mc_dc_number=tmp[1]/16
 346 +               mc_dc_number_print=1
 347 +       }
 348 +}
 349 +
 350 +{
 351 +       if (right_section && mc_dc_number_print && mc_dc_value_print) {
 352 +               if (mc_dc_number < 10)
 353 +                       print "#define MC_DC0" mc_dc_number "_VALUE\t0x" mc_dc_value
 354 +               else
 355 +                       print "#define MC_DC" mc_dc_number "_VALUE\t0x" mc_dc_value
 356 +               mc_dc_value_print=0
 357 +               mc_dc_number_print=0
 358 +       }
 359 +
 360 +       if ($4 == "t1,t1,0x1000")
 361 +               right_section=1
 362 +
 363 +
 364 +       if ($4 == "t2,736(t1)")
 365 +               right_section=0
 366 +}
 367 diff --git a/tools/lantiq_ram_init_uart.awk b/tools/lantiq_ram_init_uart.awk
 368 new file mode 100755
 369 index 0000000..dc82645
 370 --- /dev/null
 371 +++ b/tools/lantiq_ram_init_uart.awk
 372 @@ -0,0 +1,117 @@
 373 +#!/usr/bin/awk -f
 374 +#
 375 +# Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org>
 376 +# Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 377 +#
 378 +# Usage:
 379 +# awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h
 380 +#
 381 +# SPDX-License-Identifier:     GPL-2.0+
 382 +#
 383 +
 384 +function print_header()
 385 +{
 386 +       print ";                                                                            "
 387 +       print "; Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>                     "
 388 +       print "; Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>  "
 389 +       print ";                                                                            "
 390 +       print "; This file has been generated with lantiq_ram_init_uart.awk script.         "
 391 +       print ";                                                                            "
 392 +       print "; SPDX-License-Identifier:       GPL-2.0+                                    "
 393 +       print ""
 394 +}
 395 +
 396 +function mc_danube_prologue()
 397 +{
 398 +       /* Clear access error log registers */
 399 +       print "0xbf800010", "0x0"
 400 +       print "0xbf800020", "0x0"
 401 +
 402 +       /* Enable DDR and SRAM module in memory controller */
 403 +       print "0xbf800060", "0x5"
 404 +
 405 +       /* Clear start bit of DDR memory controller */
 406 +       print "0xbf801030", "0x0"
 407 +}
 408 +
 409 +function mc_ar9_prologue()
 410 +{
 411 +       /* Clear access error log registers */
 412 +       print "0xbf800010", "0x0"
 413 +       print "0xbf800020", "0x0"
 414 +
 415 +       /* Enable FPI, DDR and SRAM module in memory controller */
 416 +       print "0xbf800060", "0xD"
 417 +
 418 +       /* Clear start bit of DDR memory controller */
 419 +       print "0xbf801030", "0x0"
 420 +}
 421 +
 422 +function mc_ddr1_epilogue()
 423 +{
 424 +       /* Set start bit of DDR memory controller */
 425 +       print "0xbf801030", "0x100"
 426 +}
 427 +
 428 +function mc_ddr2_prologue()
 429 +{
 430 +       /* Put memory controller in inactive mode */
 431 +       print "0xbf401070", "0x0"
 432 +}
 433 +
 434 +function mc_ddr2_epilogue(mc_ccr07_value)
 435 +{
 436 +       /* Put memory controller in active mode */
 437 +       mc_ccr07_value = or(mc_ccr07_value, 0x100)
 438 +       printf("0xbf401070 0x%x\n", mc_ccr07_value)
 439 +}
 440 +
 441 +BEGIN {
 442 +       switch (soc) {
 443 +       case "danube":
 444 +               reg_base = 0xbf801000
 445 +               print_header()
 446 +               mc_danube_prologue()
 447 +               break
 448 +       case "ar9":
 449 +               reg_base = 0xbf801000
 450 +               print_header()
 451 +               mc_ar9_prologue()
 452 +               break
 453 +       case "vr9":
 454 +               reg_base = 0xbf401000
 455 +               print_header()
 456 +               mc_ddr2_prologue()
 457 +               break
 458 +       default:
 459 +               print "Invalid or no value for soc specified!"
 460 +               exit 1
 461 +       }
 462 +
 463 +       mc_ccr07_value = 0
 464 +}
 465 +
 466 +/^#define/ {
 467 +       /* CCR07 contains MC enable bit and must not be set here */
 468 +       if (tolower($2) == "mc_ccr07_value")
 469 +               mc_ccr07_value = strtonum($3)
 470 +       if (tolower($2) == "mc_dc03_value")
 471 +               /* CCR07 contains MC enable bit and must not be set here */
 472 +       else
 473 +               printf("0x%x %s\n", reg_base, tolower($3))
 474 +
 475 +       reg_base += 0x10
 476 +}
 477 +
 478 +END {
 479 +       switch (soc) {
 480 +       case "danube":
 481 +       case "ar9":
 482 +               mc_ddr1_epilogue()
 483 +               break
 484 +       case "vr9":
 485 +               mc_ddr2_epilogue(mc_ccr07_value)
 486 +               break
 487 +       default:
 488 +       }
 489 +}
 490 --
 491 1.8.3.2
 492