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From 03de60e7fd96c0d78d293dc859a2a9ad2d2f16c4 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 3 Aug 2012 10:22:41 +0200
Subject: [PATCH 03/25] svip hack
---
arch/mips/kernel/cevt-r4k.c | 2 ++
arch/mips/mm/c-r4k.c | 3 +++
2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 51095dd..db9070c 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -171,8 +171,10 @@ int __cpuinit r4k_clockevent_init(void)
if (!cpu_has_counter || !mips_hpt_frequency)
return -ENXIO;
+#ifndef CONFIG_SOC_SVIP
if (!c0_compare_int_usable())
return -ENXIO;
+#endif
/*
* With vectored interrupts things are getting platform specific.
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 4f9eb0b..de3475e 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1252,6 +1252,9 @@ static void __cpuinit setup_scache(void)
way_string[c->scache.ways], c->scache.linesz);
}
#else
+#ifdef CONFIG_SOC_SVIP
+ return;
+#endif
if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
#endif
--
1.7.9.1
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