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From 913c171ebfe0d589bdf6efb8fd607258c96ea54a Mon Sep 17 00:00:00 2001
From: Florian Fainelli <florian@openwrt.org>
Date: Wed, 25 Jan 2012 17:39:58 +0100
Subject: [PATCH 16/63] MIPS: BCM63XX: add TRNG peripheral definitions
Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 +++++++++
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 14 ++++++++++++++
2 files changed, 23 insertions(+), 0 deletions(-)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -129,6 +129,7 @@ enum bcm63xx_regs_set {
RSET_PCMDMA,
RSET_PCMDMAC,
RSET_PCMDMAS,
+ RSET_TRNG
};
#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
@@ -152,6 +153,7 @@ enum bcm63xx_regs_set {
#define RSET_XTMDMA_SIZE 256
#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
+#define RSET_TRNG_SIZE 20
/*
* 6338 register sets base address
@@ -195,6 +197,7 @@ enum bcm63xx_regs_set {
#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
+#define BCM_6338_TRNG_BASE (0xdeadbeef)
/*
* 6345 register sets base address
@@ -238,6 +241,7 @@ enum bcm63xx_regs_set {
#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
+#define BCM_6345_TRNG_BASE (0xdeadbeef)
/*
* 6348 register sets base address
@@ -278,6 +282,7 @@ enum bcm63xx_regs_set {
#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
+#define BCM_6348_TRNG_BASE (0xdeadbeef)
/*
* 6358 register sets base address
@@ -318,6 +323,7 @@ enum bcm63xx_regs_set {
#define BCM_6358_PCMDMA_BASE (0xfffe1800)
#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
+#define BCM_6358_TRNG_BASE (0xdeadbeef)
/*
@@ -359,6 +365,7 @@ enum bcm63xx_regs_set {
#define BCM_6368_PCMDMA_BASE (0xb0005800)
#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
+#define BCM_6368_TRNG_BASE (0xb0004180)
extern const unsigned long *bcm63xx_regs_base;
@@ -404,6 +411,7 @@ extern const unsigned long *bcm63xx_regs
__GEN_RSET_BASE(__cpu, PCMDMA) \
__GEN_RSET_BASE(__cpu, PCMDMAC) \
__GEN_RSET_BASE(__cpu, PCMDMAS) \
+ __GEN_RSET_BASE(__cpu, TRNG) \
}
#define __GEN_CPU_REGS_TABLE(__cpu) \
@@ -442,6 +450,7 @@ extern const unsigned long *bcm63xx_regs
[RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
[RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
+ [RSET_TRNG] = BCM_## __cpu ##_TRNG_BASE, \
static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -1092,4 +1092,18 @@
#define SPI_SSOFFTIME_SHIFT 3
#define SPI_BYTE_SWAP 0x80
+/*************************************************************************
+ * _REG relative to RSET_TRNG
+ *************************************************************************/
+
+#define TRNG_CTRL 0x00
+#define TRNG_EN (1 << 0)
+
+#define TRNG_STAT 0x04
+#define TRNG_AVAIL_MASK (0xff000000)
+
+#define TRNG_DATA 0x08
+#define TRNG_THRES 0x0c
+#define TRNG_MASK 0x10
+
#endif /* BCM63XX_REGS_H_ */
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