blob: 2a61d059764585e75ef68635eddbaf68070fa650 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
/*
* Atheros AR71xx SoC specific platform data definitions
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_AR71XX_PLATFORM_H
#define __ASM_MACH_AR71XX_PLATFORM_H
#include <linux/if_ether.h>
#include <linux/skbuff.h>
#include <linux/phy.h>
#include <linux/spi/spi.h>
struct ag71xx_platform_data {
phy_interface_t phy_if_mode;
u32 phy_mask;
int speed;
int duplex;
u32 reset_bit;
u8 mac_addr[ETH_ALEN];
struct device *mii_bus_dev;
u8 has_gbit:1;
u8 is_ar91xx:1;
u8 is_ar7240:1;
u8 is_ar724x:1;
u8 has_ar8216:1;
u8 has_ar7240_switch:1;
void (*ddr_flush)(void);
void (*set_pll)(int speed);
u32 fifo_cfg1;
u32 fifo_cfg2;
u32 fifo_cfg3;
};
struct ag71xx_mdio_platform_data {
u32 phy_mask;
int is_ar7240;
};
struct ar71xx_ehci_platform_data {
u8 is_ar91xx;
};
struct ar71xx_spi_platform_data {
unsigned bus_num;
unsigned num_chipselect;
u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on);
};
#define AR71XX_SPI_CS_INACTIVE 0
#define AR71XX_SPI_CS_ACTIVE 1
#endif /* __ASM_MACH_AR71XX_PLATFORM_H */
|