diff options
Diffstat (limited to 'toolchain/gcc/patches')
| -rw-r--r-- | toolchain/gcc/patches/4.5.2/002-fix_pr44392.patch | 70 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.5.2/995-fa526.patch | 257 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.5.2/999-coldfire.patch | 12 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/100-uclibc-conf.patch (renamed from toolchain/gcc/patches/4.5.2/100-uclibc-conf.patch) | 6 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/301-missing-execinfo_h.patch (renamed from toolchain/gcc/patches/4.5.2/301-missing-execinfo_h.patch) | 2 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/302-c99-snprintf.patch (renamed from toolchain/gcc/patches/4.5.2/302-c99-snprintf.patch) | 6 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/305-libmudflap-susv3-legacy.patch (renamed from toolchain/gcc/patches/4.5.2/305-libmudflap-susv3-legacy.patch) | 10 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/600-ubicom_support.patch (renamed from toolchain/gcc/patches/4.5.2/600-ubicom_support.patch) | 8 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/810-arm-softfloat-libgcc.patch (renamed from toolchain/gcc/patches/4.5.2/810-arm-softfloat-libgcc.patch) | 9 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/820-libgcc_pic.patch (renamed from toolchain/gcc/patches/4.5.2/820-libgcc_pic.patch) | 6 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/830-arm_unbreak_armv4t.patch | 13 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/840-armv4_pass_fix-v4bx_to_ld.patch | 20 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/910-mbsd_multi.patch (renamed from toolchain/gcc/patches/4.5.2/910-mbsd_multi.patch) | 128 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/993-arm_insn-opinit-RTX_CODE-fixup.patch (renamed from toolchain/gcc/patches/4.5.2/993-arm_insn-opinit-RTX_CODE-fixup.patch) | 9 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.6.1/999-coldfire.patch | 10 |
15 files changed, 136 insertions, 430 deletions
diff --git a/toolchain/gcc/patches/4.5.2/002-fix_pr44392.patch b/toolchain/gcc/patches/4.5.2/002-fix_pr44392.patch deleted file mode 100644 index 4ad6c448d9..0000000000 --- a/toolchain/gcc/patches/4.5.2/002-fix_pr44392.patch +++ /dev/null @@ -1,70 +0,0 @@ ->From d0557763b0713a4c006bd2405eede3924569cafd Mon Sep 17 00:00:00 2001 -From: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> -Date: Mon, 5 Jul 2010 11:28:49 +0100 -Subject: [PATCH 2/2] Fix PR44392 - ---- - gcc/config/arm/arm.md | 43 +++++++++++++++++++------------------------ - 1 files changed, 19 insertions(+), 24 deletions(-) - -diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md -index 2096ec6..f0348f3 100644 ---- a/gcc/config/arm/arm.md -+++ b/gcc/config/arm/arm.md -@@ -11318,34 +11318,29 @@ - (define_expand "bswapsi2" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))] --"TARGET_EITHER" -+"TARGET_EITHER && (arm_arch6 || !optimize_size)" - " -- if (!arm_arch6) -- { -- if (!optimize_size) -- { -- rtx op2 = gen_reg_rtx (SImode); -- rtx op3 = gen_reg_rtx (SImode); -+ if (!arm_arch6) -+ { -+ rtx op2 = gen_reg_rtx (SImode); -+ rtx op3 = gen_reg_rtx (SImode); - -- if (TARGET_THUMB) -- { -- rtx op4 = gen_reg_rtx (SImode); -- rtx op5 = gen_reg_rtx (SImode); -+ if (TARGET_THUMB) -+ { -+ rtx op4 = gen_reg_rtx (SImode); -+ rtx op5 = gen_reg_rtx (SImode); - -- emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], -- op2, op3, op4, op5)); -- } -- else -- { -- emit_insn (gen_arm_legacy_rev (operands[0], operands[1], -- op2, op3)); -- } -+ emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], -+ op2, op3, op4, op5)); -+ } -+ else -+ { -+ emit_insn (gen_arm_legacy_rev (operands[0], operands[1], -+ op2, op3)); -+ } - -- DONE; -- } -- else -- FAIL; -- } -+ DONE; -+ } - " - ) - --- -1.6.2 - diff --git a/toolchain/gcc/patches/4.5.2/995-fa526.patch b/toolchain/gcc/patches/4.5.2/995-fa526.patch deleted file mode 100644 index 508e1231be..0000000000 --- a/toolchain/gcc/patches/4.5.2/995-fa526.patch +++ /dev/null @@ -1,257 +0,0 @@ ---- a/gcc/config/arm/arm-cores.def -+++ b/gcc/config/arm/arm-cores.def -@@ -74,6 +74,7 @@ ARM_CORE("strongarm", strongarm, 4, - ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) - ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) - ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) -+ARM_CORE("fa526", fa526, 4, FL_LDSCHED, fastmul) - - /* V4T Architecture Processors */ - ARM_CORE("arm7tdmi", arm7tdmi, 4T, FL_CO_PROC , fastmul) ---- a/gcc/config/arm/arm.md -+++ b/gcc/config/arm/arm.md -@@ -417,7 +417,7 @@ - - (define_attr "generic_sched" "yes,no" - (const (if_then_else -- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9") -+ (ior (eq_attr "tune" "fa526,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4") - (eq_attr "tune_cortexr4" "yes")) - (const_string "no") - (const_string "yes")))) -@@ -435,6 +435,7 @@ - (include "arm1020e.md") - (include "arm1026ejs.md") - (include "arm1136jfs.md") -+(include "fa526.md") - (include "cortex-a8.md") - (include "cortex-a9.md") - (include "cortex-r4.md") ---- a/gcc/config/arm/arm-tune.md -+++ b/gcc/config/arm/arm-tune.md -@@ -1,5 +1,5 @@ - ;; -*- buffer-read-only: t -*- - ;; Generated automatically by gentune.sh from arm-cores.def - (define_attr "tune" -- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1,cortexm0" -+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0" - (const (symbol_ref "((enum attr_tune) arm_tune)"))) ---- a/gcc/config/arm/bpabi.h -+++ b/gcc/config/arm/bpabi.h -@@ -52,7 +52,8 @@ - /* The BPABI integer comparison routines return { -1, 0, 1 }. */ - #define TARGET_LIB_INT_CMP_BIASED !TARGET_BPABI - --#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}" -+#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*\ -+|march=armv4|mcpu=fa526:--fix-v4bx}" - - #define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5|mcpu=cortex-a8|mcpu=cortex-a9:%{!r:--be8}}}" - ---- /dev/null -+++ b/gcc/config/arm/fa526.md -@@ -0,0 +1,161 @@ -+;; Faraday FA526 Pipeline Description -+;; Copyright (C) 2010 Free Software Foundation, Inc. -+;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. -+ -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it under -+;; the terms of the GNU General Public License as published by the Free -+;; Software Foundation; either version 3, or (at your option) any later -+;; version. -+;; -+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY -+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or -+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+;; for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; <http://www.gnu.org/licenses/>. */ -+ -+;; These descriptions are based on the information contained in the -+;; FA526 Core Design Note, Copyright (c) 2010 Faraday Technology Corp. -+;; -+;; Modeled pipeline characteristics: -+;; LD -> any use: latency = 3 (2 cycle penalty). -+;; ALU -> any use: latency = 2 (1 cycle penalty). -+ -+;; This automaton provides a pipeline description for the Faraday -+;; FA526 core. -+;; -+;; The model given here assumes that the condition for all conditional -+;; instructions is "true", i.e., that all of the instructions are -+;; actually executed. -+ -+(define_automaton "fa526") -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; Pipelines -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+;; There is a single pipeline -+;; -+;; The ALU pipeline has fetch, decode, execute, memory, and -+;; write stages. We only need to model the execute, memory and write -+;; stages. -+ -+;; S E M W -+ -+(define_cpu_unit "fa526_core" "fa526") -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; ALU Instructions -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+;; ALU instructions require two cycles to execute, and use the ALU -+;; pipeline in each of the three stages. The results are available -+;; after the execute stage stage has finished. -+;; -+;; If the destination register is the PC, the pipelines are stalled -+;; for several cycles. That case is not modeled here. -+ -+;; ALU operations -+(define_insn_reservation "526_alu_op" 1 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "alu")) -+ "fa526_core") -+ -+(define_insn_reservation "526_alu_shift_op" 2 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "alu_shift,alu_shift_reg")) -+ "fa526_core") -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; Multiplication Instructions -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+(define_insn_reservation "526_mult1" 2 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "insn" "smlalxy,smulxy,smlaxy,smlalxy")) -+ "fa526_core") -+ -+(define_insn_reservation "526_mult2" 5 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "insn" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\ -+ umlals,smulls,smlals,smlawx")) -+ "fa526_core*4") -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; Load/Store Instructions -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+;; The models for load/store instructions do not accurately describe -+;; the difference between operations with a base register writeback -+;; (such as "ldm!"). These models assume that all memory references -+;; hit in dcache. -+ -+(define_insn_reservation "526_load1_op" 3 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "load1,load_byte")) -+ "fa526_core") -+ -+(define_insn_reservation "526_load2_op" 4 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "load2")) -+ "fa526_core*2") -+ -+(define_insn_reservation "526_load3_op" 5 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "load3")) -+ "fa526_core*3") -+ -+(define_insn_reservation "526_load4_op" 6 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "load4")) -+ "fa526_core*4") -+ -+(define_insn_reservation "526_store1_op" 0 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "store1")) -+ "fa526_core") -+ -+(define_insn_reservation "526_store2_op" 1 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "store2")) -+ "fa526_core*2") -+ -+(define_insn_reservation "526_store3_op" 2 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "store3")) -+ "fa526_core*3") -+ -+(define_insn_reservation "526_store4_op" 3 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "store4")) -+ "fa526_core*4") -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; Branch and Call Instructions -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+;; Branch instructions are difficult to model accurately. The FA526 -+;; core can predict most branches. If the branch is predicted -+;; correctly, and predicted early enough, the branch can be completely -+;; eliminated from the instruction stream. Some branches can -+;; therefore appear to require zero cycle to execute. We assume that -+;; all branches are predicted correctly, and that the latency is -+;; therefore the minimum value. -+ -+(define_insn_reservation "526_branch_op" 0 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "branch")) -+ "fa526_core") -+ -+;; The latency for a call is actually the latency when the result is available. -+;; i.e. R0 ready for int return value. For most cases, the return value is set -+;; by a mov instruction, which has 1 cycle latency. -+(define_insn_reservation "526_call_op" 1 -+ (and (eq_attr "tune" "fa526") -+ (eq_attr "type" "call")) -+ "fa526_core") -+ ---- a/gcc/config/arm/t-arm -+++ b/gcc/config/arm/t-arm -@@ -24,6 +24,7 @@ MD_INCLUDES= $(srcdir)/config/arm/arm-t - $(srcdir)/config/arm/arm1020e.md \ - $(srcdir)/config/arm/arm1026ejs.md \ - $(srcdir)/config/arm/arm1136jfs.md \ -+ $(srcdir)/config/arm/fa526.md \ - $(srcdir)/config/arm/arm926ejs.md \ - $(srcdir)/config/arm/cirrus.md \ - $(srcdir)/config/arm/fpa.md \ ---- a/gcc/config/arm/t-arm-elf -+++ b/gcc/config/arm/t-arm-elf -@@ -36,6 +36,10 @@ MULTILIB_DIRNAMES = arm thumb - MULTILIB_EXCEPTIONS = - MULTILIB_MATCHES = - -+#MULTILIB_OPTIONS += mcpu=fa526 -+#MULTILIB_DIRNAMES += fa526 -+#MULTILIB_EXCEPTIONS += *mthumb*/*mcpu=fa526 -+ - #MULTILIB_OPTIONS += march=armv7 - #MULTILIB_DIRNAMES += thumb2 - #MULTILIB_EXCEPTIONS += march=armv7* marm/*march=armv7* -@@ -52,6 +56,7 @@ MULTILIB_MATCHES = - MULTILIB_OPTIONS += mfloat-abi=hard - MULTILIB_DIRNAMES += fpu - MULTILIB_EXCEPTIONS += *mthumb/*mfloat-abi=hard* -+MULTILIB_EXCEPTIONS += *mcpu=fa526/*mfloat-abi=hard* - - # MULTILIB_OPTIONS += mcpu=ep9312 - # MULTILIB_DIRNAMES += ep9312 ---- a/gcc/doc/invoke.texi -+++ b/gcc/doc/invoke.texi -@@ -9900,7 +9900,8 @@ assembly code. Permissible names are: @ - @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3}, - @samp{cortex-m1}, - @samp{cortex-m0}, --@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. -+@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, -+@samp{fa526}. - - @item -mtune=@var{name} - @opindex mtune diff --git a/toolchain/gcc/patches/4.5.2/999-coldfire.patch b/toolchain/gcc/patches/4.5.2/999-coldfire.patch deleted file mode 100644 index 980e276947..0000000000 --- a/toolchain/gcc/patches/4.5.2/999-coldfire.patch +++ /dev/null @@ -1,12 +0,0 @@ -Index: gcc-4.4.2/gcc/config.gcc -=================================================================== ---- gcc-4.4.2.orig/gcc/config.gcc 2009-10-21 16:19:39.000000000 +0200 -+++ gcc-4.4.2/gcc/config.gcc 2009-10-21 16:19:40.000000000 +0200 -@@ -1506,6 +1506,7 @@ - if test x$sjlj != x1; then - tmake_file="$tmake_file m68k/t-slibgcc-elf-ver" - fi -+ tmake_file="m68k/t-floatlib m68k/t-m68kbare m68k/t-m68kelf" - ;; - m68k-*-rtems*) - default_m68k_cpu=68020 diff --git a/toolchain/gcc/patches/4.5.2/100-uclibc-conf.patch b/toolchain/gcc/patches/4.6.1/100-uclibc-conf.patch index 7c6b791162..ff9ad94f62 100644 --- a/toolchain/gcc/patches/4.5.2/100-uclibc-conf.patch +++ b/toolchain/gcc/patches/4.6.1/100-uclibc-conf.patch @@ -1,6 +1,6 @@ --- a/contrib/regression/objs-gcc.sh +++ b/contrib/regression/objs-gcc.sh -@@ -106,6 +106,10 @@ +@@ -106,6 +106,10 @@ if [ $H_REAL_TARGET = $H_REAL_HOST -a $H then make all-gdb all-dejagnu all-ld || exit 1 make install-gdb install-dejagnu install-ld || exit 1 @@ -13,7 +13,7 @@ make install || exit 1 --- a/libjava/classpath/ltconfig +++ b/libjava/classpath/ltconfig -@@ -603,7 +603,7 @@ +@@ -603,7 +603,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)- # Transform linux* to *-*-linux-gnu*, to support old configure scripts. case $host_os in @@ -22,7 +22,7 @@ linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'` esac -@@ -1251,7 +1251,7 @@ +@@ -1247,7 +1247,7 @@ linux-gnuoldld* | linux-gnuaout* | linux ;; # This must be Linux ELF. diff --git a/toolchain/gcc/patches/4.5.2/301-missing-execinfo_h.patch b/toolchain/gcc/patches/4.6.1/301-missing-execinfo_h.patch index 5a7aa4e47d..b3f1e68d3b 100644 --- a/toolchain/gcc/patches/4.5.2/301-missing-execinfo_h.patch +++ b/toolchain/gcc/patches/4.6.1/301-missing-execinfo_h.patch @@ -1,6 +1,6 @@ --- a/boehm-gc/include/gc.h +++ b/boehm-gc/include/gc.h -@@ -503,7 +503,7 @@ +@@ -503,7 +503,7 @@ GC_API GC_PTR GC_malloc_atomic_ignore_of #if defined(__linux__) || defined(__GLIBC__) # include <features.h> # if (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 1 || __GLIBC__ > 2) \ diff --git a/toolchain/gcc/patches/4.5.2/302-c99-snprintf.patch b/toolchain/gcc/patches/4.6.1/302-c99-snprintf.patch index f0ba5411ed..eda1854df1 100644 --- a/toolchain/gcc/patches/4.5.2/302-c99-snprintf.patch +++ b/toolchain/gcc/patches/4.6.1/302-c99-snprintf.patch @@ -1,8 +1,8 @@ --- a/libstdc++-v3/include/c_global/cstdio +++ b/libstdc++-v3/include/c_global/cstdio -@@ -139,7 +139,7 @@ - - _GLIBCXX_END_NAMESPACE +@@ -137,7 +137,7 @@ namespace std + using ::vsprintf; + } // namespace -#if _GLIBCXX_USE_C99 +#if _GLIBCXX_USE_C99 || defined __UCLIBC__ diff --git a/toolchain/gcc/patches/4.5.2/305-libmudflap-susv3-legacy.patch b/toolchain/gcc/patches/4.6.1/305-libmudflap-susv3-legacy.patch index 5bc4aebb67..8e2d15f81a 100644 --- a/toolchain/gcc/patches/4.5.2/305-libmudflap-susv3-legacy.patch +++ b/toolchain/gcc/patches/4.6.1/305-libmudflap-susv3-legacy.patch @@ -1,6 +1,6 @@ --- a/libmudflap/mf-hooks2.c +++ b/libmudflap/mf-hooks2.c -@@ -421,7 +421,7 @@ +@@ -421,7 +421,7 @@ WRAPPER2(void, bzero, void *s, size_t n) { TRACE ("%s\n", __PRETTY_FUNCTION__); MF_VALIDATE_EXTENT(s, n, __MF_CHECK_WRITE, "bzero region"); @@ -9,7 +9,7 @@ } -@@ -431,7 +431,7 @@ +@@ -431,7 +431,7 @@ WRAPPER2(void, bcopy, const void *src, v TRACE ("%s\n", __PRETTY_FUNCTION__); MF_VALIDATE_EXTENT(src, n, __MF_CHECK_READ, "bcopy src"); MF_VALIDATE_EXTENT(dest, n, __MF_CHECK_WRITE, "bcopy dest"); @@ -18,7 +18,7 @@ } -@@ -441,7 +441,7 @@ +@@ -441,7 +441,7 @@ WRAPPER2(int, bcmp, const void *s1, cons TRACE ("%s\n", __PRETTY_FUNCTION__); MF_VALIDATE_EXTENT(s1, n, __MF_CHECK_READ, "bcmp 1st arg"); MF_VALIDATE_EXTENT(s2, n, __MF_CHECK_READ, "bcmp 2nd arg"); @@ -27,7 +27,7 @@ } -@@ -450,7 +450,7 @@ +@@ -450,7 +450,7 @@ WRAPPER2(char *, index, const char *s, i size_t n = strlen (s); TRACE ("%s\n", __PRETTY_FUNCTION__); MF_VALIDATE_EXTENT(s, CLAMPADD(n, 1), __MF_CHECK_READ, "index region"); @@ -36,7 +36,7 @@ } -@@ -459,7 +459,7 @@ +@@ -459,7 +459,7 @@ WRAPPER2(char *, rindex, const char *s, size_t n = strlen (s); TRACE ("%s\n", __PRETTY_FUNCTION__); MF_VALIDATE_EXTENT(s, CLAMPADD(n, 1), __MF_CHECK_READ, "rindex region"); diff --git a/toolchain/gcc/patches/4.5.2/600-ubicom_support.patch b/toolchain/gcc/patches/4.6.1/600-ubicom_support.patch index a8dbaf466d..8268b5e922 100644 --- a/toolchain/gcc/patches/4.5.2/600-ubicom_support.patch +++ b/toolchain/gcc/patches/4.6.1/600-ubicom_support.patch @@ -1,6 +1,6 @@ --- a/configure +++ b/configure -@@ -2688,6 +2688,9 @@ case "${target}" in +@@ -3608,6 +3608,9 @@ case "${target}" in ip2k-*-*) noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 ${libgcj}" ;; @@ -9313,7 +9313,7 @@ +#define FATAL_EXIT_CODE 33 --- a/gcc/config.gcc +++ b/gcc/config.gcc -@@ -2314,6 +2314,34 @@ spu-*-elf*) +@@ -2662,6 +2662,34 @@ spu-*-elf*) c_target_objs="${c_target_objs} spu-c.o" cxx_target_objs="${cxx_target_objs} spu-c.o" ;; @@ -9347,10 +9347,10 @@ + ;; v850e1-*-*) target_cpu_default="TARGET_CPU_v850e1" - tm_file="dbxelf.h elfos.h svr4.h v850/v850.h" + tm_file="dbxelf.h elfos.h newlib-stdint.h v850/v850.h" --- a/libgcc/config.host +++ b/libgcc/config.host -@@ -551,6 +551,15 @@ sparc64-*-netbsd*) +@@ -572,6 +572,15 @@ sparc64-*-netbsd*) ;; spu-*-elf*) ;; diff --git a/toolchain/gcc/patches/4.5.2/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches/4.6.1/810-arm-softfloat-libgcc.patch index 4ca297a41a..60cfde4078 100644 --- a/toolchain/gcc/patches/4.5.2/810-arm-softfloat-libgcc.patch +++ b/toolchain/gcc/patches/4.6.1/810-arm-softfloat-libgcc.patch @@ -11,15 +11,16 @@ --- a/gcc/config/arm/t-linux +++ b/gcc/config/arm/t-linux -@@ -4,7 +4,10 @@ +@@ -23,7 +23,11 @@ TARGET_LIBGCC2_CFLAGS = -fomit-frame-poi LIB1ASMSRC = arm/lib1funcs.asm LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \ - _arm_addsubdf3 _arm_addsubsf3 + _arm_addsubdf3 _arm_addsubsf3 \ -+ _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \ -+ _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \ -+ _fixsfsi _fixunssfsi _floatdidf _floatundidf _floatdisf _floatundisf ++ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \ ++ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \ ++ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \ ++ _arm_fixsfsi _arm_fixunssfsi # MULTILIB_OPTIONS = mhard-float/msoft-float # MULTILIB_DIRNAMES = hard-float soft-float diff --git a/toolchain/gcc/patches/4.5.2/820-libgcc_pic.patch b/toolchain/gcc/patches/4.6.1/820-libgcc_pic.patch index 18386dfd42..3760ac2b9b 100644 --- a/toolchain/gcc/patches/4.5.2/820-libgcc_pic.patch +++ b/toolchain/gcc/patches/4.6.1/820-libgcc_pic.patch @@ -1,6 +1,6 @@ --- a/libgcc/Makefile.in +++ b/libgcc/Makefile.in -@@ -729,11 +729,12 @@ $(libgcov-objects): %$(objext): $(gcc_sr +@@ -747,11 +747,12 @@ $(libgcov-objects): %$(objext): $(gcc_sr # Static libraries. libgcc.a: $(libgcc-objects) @@ -14,7 +14,7 @@ -rm -f $@ objects="$(objects)"; \ -@@ -755,7 +756,7 @@ libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_E +@@ -773,7 +774,7 @@ libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_E endif ifeq ($(enable_shared),yes) @@ -23,7 +23,7 @@ ifneq ($(LIBUNWIND),) all: libunwind$(SHLIB_EXT) endif -@@ -928,6 +929,10 @@ install-shared: +@@ -954,6 +955,10 @@ install-shared: chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a diff --git a/toolchain/gcc/patches/4.6.1/830-arm_unbreak_armv4t.patch b/toolchain/gcc/patches/4.6.1/830-arm_unbreak_armv4t.patch new file mode 100644 index 0000000000..37f8f2a54d --- /dev/null +++ b/toolchain/gcc/patches/4.6.1/830-arm_unbreak_armv4t.patch @@ -0,0 +1,13 @@ +http://sourceware.org/ml/crossgcc/2008-05/msg00009.html + +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -45,7 +45,7 @@ + The ARM10TDMI core is the default for armv5t, so set + SUBTARGET_CPU_DEFAULT to achieve this. */ + #undef SUBTARGET_CPU_DEFAULT +-#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm10tdmi ++#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9tdmi + + /* TARGET_BIG_ENDIAN_DEFAULT is set in + config.gcc for big endian configurations. */ diff --git a/toolchain/gcc/patches/4.6.1/840-armv4_pass_fix-v4bx_to_ld.patch b/toolchain/gcc/patches/4.6.1/840-armv4_pass_fix-v4bx_to_ld.patch new file mode 100644 index 0000000000..e5a26c17d4 --- /dev/null +++ b/toolchain/gcc/patches/4.6.1/840-armv4_pass_fix-v4bx_to_ld.patch @@ -0,0 +1,20 @@ +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -64,12 +64,16 @@ + #undef GLIBC_DYNAMIC_LINKER + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.3" + ++/* For armv4 we pass --fix-v4bx to linker to support EABI */ ++#undef TARGET_FIX_V4BX_SPEC ++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}" ++ + /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to + use the GNU/Linux version, not the generic BPABI version. */ + #undef LINK_SPEC + #define LINK_SPEC BE8_LINK_SPEC \ + LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ +- LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) ++ LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) \ + + #undef CC1_SPEC + #define CC1_SPEC \ diff --git a/toolchain/gcc/patches/4.5.2/910-mbsd_multi.patch b/toolchain/gcc/patches/4.6.1/910-mbsd_multi.patch index 0d5815a546..5a1adc971e 100644 --- a/toolchain/gcc/patches/4.5.2/910-mbsd_multi.patch +++ b/toolchain/gcc/patches/4.6.1/910-mbsd_multi.patch @@ -17,20 +17,20 @@ This patch was authored by Thorsten Glaser <tg at mirbsd.de> with copyright assignment to the FSF in effect. ---- a/gcc/c-opts.c -+++ b/gcc/c-opts.c -@@ -105,6 +105,9 @@ +--- a/gcc/c-family/c-opts.c ++++ b/gcc/c-family/c-opts.c +@@ -103,6 +103,9 @@ static size_t deferred_count; /* Number of deferred options scanned for -include. */ static size_t include_cursor; +/* Check if a port honours COPTS. */ +static int honour_copts = 0; + - static void set_Wimplicit (int); static void handle_OPT_d (const char *); static void set_std_cxx98 (int); -@@ -454,6 +457,9 @@ - enable_warning_as_error ("implicit-function-declaration", value, CL_C | CL_ObjC); + static void set_std_cxx0x (int); +@@ -441,6 +444,9 @@ c_common_handle_option (size_t scode, co + global_dc->warning_as_error_requested = value; break; + case OPT_Werror_maybe_reset: @@ -39,20 +39,20 @@ case OPT_Wformat: set_Wformat (value); break; -@@ -690,6 +701,12 @@ - flag_exceptions = value; +@@ -584,6 +590,12 @@ c_common_handle_option (size_t scode, co + flag_no_builtin = !value; break; + case OPT_fhonour_copts: + if (c_language == clk_c) { -+ honour_copts++; ++ honour_copts++; + } + break; + - case OPT_fimplement_inlines: - flag_implement_inlines = value; + case OPT_fconstant_string_class_: + constant_string_class_name = arg; break; -@@ -1209,6 +1226,47 @@ +@@ -1058,6 +1070,47 @@ c_common_init (void) return false; } @@ -75,35 +75,35 @@ + } + if (evv == 1) { + if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in lenient mode"); -+ return false; ++ error ("someone does not honour COPTS at all in lenient mode"); ++ return false; + } else if (honour_copts != 1) { -+ warning (0, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); ++ warning (0, "someone does not honour COPTS correctly, passed %d times", ++ honour_copts); + } + } else if (evv == 2) { + if (honour_copts == 0) { -+ error ("someone does not honour COPTS at all in strict mode"); -+ return false; ++ error ("someone does not honour COPTS at all in strict mode"); ++ return false; + } else if (honour_copts != 1) { -+ error ("someone does not honour COPTS correctly, passed %d times", -+ honour_copts); -+ return false; ++ error ("someone does not honour COPTS correctly, passed %d times", ++ honour_copts); ++ return false; + } + } else if (evv == 0) { + if (honour_copts != 1) -+ inform (0, "someone does not honour COPTS correctly, passed %d times", -+ honour_copts); ++ inform (0, "someone does not honour COPTS correctly, passed %d times", ++ honour_copts); + } + } + return true; } ---- a/gcc/c.opt -+++ b/gcc/c.opt -@@ -215,6 +215,10 @@ - C ObjC RejectNegative Warning +--- a/gcc/c-family/c.opt ++++ b/gcc/c-family/c.opt +@@ -363,6 +363,10 @@ Werror-implicit-function-declaration + C ObjC RejectNegative Warning Alias(Werror=, implicit-function-declaration) This switch is deprecated; use -Werror=implicit-function-declaration instead +Werror-maybe-reset @@ -113,9 +113,9 @@ Wfloat-equal C ObjC C++ ObjC++ Var(warn_float_equal) Warning Warn if testing floating point numbers for equality -@@ -609,6 +613,9 @@ +@@ -794,6 +798,9 @@ C++ ObjC++ Optimization Alias(fexception fhonor-std - C++ ObjC++ + C++ ObjC++ Ignore Warn(switch %qs is no longer supported) +fhonour-copts +C ObjC C++ ObjC++ RejectNegative @@ -125,7 +125,7 @@ Assume normal C execution environment --- a/gcc/common.opt +++ b/gcc/common.opt -@@ -102,6 +102,10 @@ +@@ -520,6 +520,10 @@ Werror= Common Joined Treat specified warning as error @@ -134,9 +134,9 @@ +If environment variable GCC_NO_WERROR is set, act as -Wno-error + Wextra - Common Warning + Common Var(extra_warnings) Warning Print extra (possibly unwanted) warnings -@@ -573,6 +577,9 @@ +@@ -1156,6 +1160,9 @@ fguess-branch-probability Common Report Var(flag_guess_branch_prob) Optimization Enable guessing of branch probabilities @@ -148,33 +148,33 @@ ; On SVR4 targets, it also controls whether or not to emit a --- a/gcc/opts.c +++ b/gcc/opts.c -@@ -896,8 +896,6 @@ - flag_schedule_insns_after_reload = opt2; +@@ -477,8 +477,6 @@ static const struct default_options defa + { OPT_LEVELS_2_PLUS, OPT_fschedule_insns2, NULL, 1 }, #endif - flag_regmove = opt2; -- flag_strict_aliasing = opt2; -- flag_strict_overflow = opt2; - flag_reorder_blocks = opt2; - flag_reorder_functions = opt2; - flag_tree_vrp = opt2; -@@ -922,6 +919,8 @@ + { OPT_LEVELS_2_PLUS, OPT_fregmove, NULL, 1 }, +- { OPT_LEVELS_2_PLUS, OPT_fstrict_aliasing, NULL, 1 }, +- { OPT_LEVELS_2_PLUS, OPT_fstrict_overflow, NULL, 1 }, + { OPT_LEVELS_2_PLUS, OPT_freorder_blocks, NULL, 1 }, + { OPT_LEVELS_2_PLUS, OPT_freorder_functions, NULL, 1 }, + { OPT_LEVELS_2_PLUS, OPT_ftree_vrp, NULL, 1 }, +@@ -494,6 +492,8 @@ static const struct default_options defa + { OPT_LEVELS_2_PLUS, OPT_falign_functions, NULL, 1 }, - /* -O3 optimizations. */ - opt3 = (optimize >= 3); -+ flag_strict_aliasing = opt3; -+ flag_strict_overflow = opt3; - flag_predictive_commoning = opt3; - flag_inline_functions = opt3; - flag_unswitch_loops = opt3; -@@ -1601,6 +1601,17 @@ - enable_warning_as_error (arg, value, lang_mask); + /* -O3 optimizations. */ ++ { OPT_LEVELS_3_PLUS, OPT_fstrict_aliasing, NULL, 1 }, ++ { OPT_LEVELS_3_PLUS, OPT_fstrict_overflow, NULL, 1 }, + { OPT_LEVELS_3_PLUS, OPT_ftree_loop_distribute_patterns, NULL, 1 }, + { OPT_LEVELS_3_PLUS, OPT_fpredictive_commoning, NULL, 1 }, + /* Inlining of functions reducing size is a good idea with -Os +@@ -1399,6 +1399,17 @@ common_handle_option (struct gcc_options + opts, opts_set, loc, dc); break; + case OPT_Werror_maybe_reset: + { -+ char *ev = getenv ("GCC_NO_WERROR"); -+ if ((ev != NULL) && (*ev != '0')) -+ warnings_are_errors = 0; ++ char *ev = getenv ("GCC_NO_WERROR"); ++ if ((ev != NULL) && (*ev != '0')) ++ warnings_are_errors = 0; + } + break; + @@ -182,11 +182,11 @@ + break; + case OPT_Wlarger_than_: - /* This form corresponds to -Wlarger-than-. - Kept for backward compatibility. + opts->x_larger_than_size = value; + opts->x_warn_larger_than = value != -1; --- a/gcc/doc/cppopts.texi +++ b/gcc/doc/cppopts.texi -@@ -164,6 +164,11 @@ +@@ -164,6 +164,11 @@ in older programs. This warning is on b Make all warnings into hard errors. Source code which triggers warnings will be rejected. @@ -200,16 +200,16 @@ Issue warnings for code in system headers. These are normally unhelpful --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi -@@ -234,7 +234,7 @@ - -Wconversion -Wcoverage-mismatch -Wno-deprecated @gol +@@ -240,7 +240,7 @@ Objective-C and Objective-C++ Dialects}. + -Wconversion -Wcoverage-mismatch -Wno-cpp -Wno-deprecated @gol -Wno-deprecated-declarations -Wdisabled-optimization @gol - -Wno-div-by-zero -Wempty-body -Wenum-compare -Wno-endif-labels @gol ---Werror -Werror=* @gol -+-Werror -Werror=* -Werror-maybe-reset @gol + -Wno-div-by-zero -Wdouble-promotion -Wempty-body -Wenum-compare @gol +--Wno-endif-labels -Werror -Werror=* @gol ++-Wno-endif-labels -Werror -Werror=* -Werror-maybe-reset @gol -Wfatal-errors -Wfloat-equal -Wformat -Wformat=2 @gol -Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol -Wformat-security -Wformat-y2k @gol -@@ -4161,6 +4161,22 @@ +@@ -4495,6 +4495,22 @@ This option is only supported for C and @option{-Wall} and by @option{-pedantic}, which can be disabled with @option{-Wno-pointer-sign}. @@ -232,7 +232,7 @@ @item -Wstack-protector @opindex Wstack-protector @opindex Wno-stack-protector -@@ -5699,7 +5715,7 @@ +@@ -6317,7 +6333,7 @@ so, the first branch is redirected to ei second branch or a point immediately following it, depending on whether the condition is known to be true or false. @@ -243,7 +243,7 @@ @opindex fsplit-wide-types --- a/gcc/java/jvspec.c +++ b/gcc/java/jvspec.c -@@ -670,6 +670,7 @@ +@@ -627,6 +627,7 @@ lang_specific_pre_link (void) class name. Append dummy `.c' that can be stripped by set_input so %b is correct. */ set_input (concat (main_class_name, "main.c", NULL)); diff --git a/toolchain/gcc/patches/4.5.2/993-arm_insn-opinit-RTX_CODE-fixup.patch b/toolchain/gcc/patches/4.6.1/993-arm_insn-opinit-RTX_CODE-fixup.patch index 4c4be9f2a0..864f972d1c 100644 --- a/toolchain/gcc/patches/4.5.2/993-arm_insn-opinit-RTX_CODE-fixup.patch +++ b/toolchain/gcc/patches/4.6.1/993-arm_insn-opinit-RTX_CODE-fixup.patch @@ -1,14 +1,15 @@ ---- gcc-4.4.0/gcc/config/arm/arm-protos.h 2009-02-20 16:20:38.000000000 +0100 -+++ gcc-4.4.0.new/gcc/config/arm/arm-protos.h 2009-04-22 16:00:58.000000000 +0200 -@@ -43,10 +43,10 @@ +--- a/gcc/config/arm/arm-protos.h ++++ b/gcc/config/arm/arm-protos.h +@@ -41,11 +41,11 @@ extern unsigned int arm_dbx_register_num extern void arm_output_fn_unwind (FILE *, bool); -#ifdef RTX_CODE extern bool arm_vector_mode_supported_p (enum machine_mode); + extern bool arm_small_register_classes_for_mode_p (enum machine_mode); extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode); extern int const_ok_for_arm (HOST_WIDE_INT); +#ifdef RTX_CODE extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, HOST_WIDE_INT, rtx, rtx, int); - extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, enum machine_mode, + extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *); diff --git a/toolchain/gcc/patches/4.6.1/999-coldfire.patch b/toolchain/gcc/patches/4.6.1/999-coldfire.patch new file mode 100644 index 0000000000..cda4237b43 --- /dev/null +++ b/toolchain/gcc/patches/4.6.1/999-coldfire.patch @@ -0,0 +1,10 @@ +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -1791,6 +1791,7 @@ m68k-*-linux*) # Motorola m68k's runnin + if test x$sjlj != x1; then + tmake_file="$tmake_file m68k/t-slibgcc-elf-ver" + fi ++ tmake_file="m68k/t-floatlib m68k/t-m68kbare m68k/t-m68kelf" + ;; + m68k-*-rtems*) + default_m68k_cpu=68020 |