1 files changed, 48 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-3.12/137-1-dt-sun7i-add-hstimer.patch b/target/linux/sunxi/patches-3.12/137-1-dt-sun7i-add-hstimer.patch
new file mode 100644
index 0000000000..7112ff0bce
--- /dev/null
+++ b/target/linux/sunxi/patches-3.12/137-1-dt-sun7i-add-hstimer.patch
@@ -0,0 +1,48 @@
+From 6c23e1fa6bd220b8f5665c150c83d4c016d95482 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Thu, 7 Nov 2013 12:01:48 +0100
+Subject: [PATCH] ARM: sun7i: a20: Add support for the High Speed Timers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The Allwinner A20 has support for four high speed timers. Apart for the
+number of timers (4 vs 2), it's basically the same logic than the high
+speed timers found in the sun5i chips.
+
+Now that we have a driver to support it, we can enable them in the
+device tree.
+
+[dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Tested-by: Emilio López <emilio@elopez.com.ar>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
+index 93f7f96..c74147a 100644
+--- a/arch/arm/boot/dts/sun7i-a20.dtsi
++++ b/arch/arm/boot/dts/sun7i-a20.dtsi
+@@ -405,6 +405,16 @@
+ 			status = "disabled";
+ 		};
+ 
++		hstimer@01c60000 {
++			compatible = "allwinner,sun7i-a20-hstimer";
++			reg = <0x01c60000 0x1000>;
++			interrupts = <0 81 1>,
++				     <0 82 1>,
++				     <0 83 1>,
++				     <0 84 1>;
++			clocks = <&ahb_gates 28>;
++		};
++
+ 		gic: interrupt-controller@01c81000 {
+ 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ 			reg = <0x01c81000 0x1000>,
+-- 
+1.8.5.1
+