diff options
Diffstat (limited to 'target/linux/ixp4xx')
35 files changed, 7945 insertions, 0 deletions
diff --git a/target/linux/ixp4xx/config-default b/target/linux/ixp4xx/config-default index 9673dc75bc..f9cfe53233 100644 --- a/target/linux/ixp4xx/config-default +++ b/target/linux/ixp4xx/config-default @@ -353,6 +353,7 @@ CONFIG_PPP_MPPE=m CONFIG_RTC_CLASS=y # CONFIG_RTC_DEBUG is not set # CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set # CONFIG_RTC_DRV_DS1553 is not set CONFIG_RTC_DRV_DS1672=y # CONFIG_RTC_DRV_DS1742 is not set @@ -397,6 +398,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1337 is not set @@ -404,10 +406,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_SENSORS_DS1621 is not set CONFIG_SENSORS_EEPROM=y # CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_FSCHER is not set # CONFIG_SENSORS_FSCPOS is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM75 is not set diff --git a/target/linux/ixp4xx/patches-2.6.24/016-dsmg600_auto_power_on.patch b/target/linux/ixp4xx/patches-2.6.24/016-dsmg600_auto_power_on.patch new file mode 100644 index 0000000000..2a1f2415f7 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/016-dsmg600_auto_power_on.patch @@ -0,0 +1,111 @@ +Upgrade the power and reset button handling for the DSMG600: + * Remove the superfluous declaration of ctrl_alt_del(). + * Convert GPIO and IRQ handling to use the <asm/gpio.h> api. + * Perform the reset on the release of the power button, so that + NAS devices which have been set to auto-power-on (by bridging + the power button) do not continuously power cycle. + * Remove all superflous constants from dsmg600.h + +Signed-off-by: Rod Whitby <rod@whitby.id.au> + +--- + arch/arm/mach-ixp4xx/dsmg600-power.c | 24 ++++++++++++++---------- + include/asm-arm/arch-ixp4xx/dsmg600.h | 7 +------ + 2 files changed, 15 insertions(+), 16 deletions(-) + +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/dsmg600-power.c +=================================================================== +--- linux-2.6.23.12-armeb.orig/arch/arm/mach-ixp4xx/dsmg600-power.c 2008-01-11 16:20:26.000000000 +1030 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/dsmg600-power.c 2008-01-11 16:20:30.000000000 +1030 +@@ -26,10 +26,9 @@ + #include <linux/jiffies.h> + #include <linux/timer.h> + ++#include <asm/gpio.h> + #include <asm/mach-types.h> + +-extern void ctrl_alt_del(void); +- + /* This is used to make sure the power-button pusher is serious. The button + * must be held until the value of this counter reaches zero. + */ +@@ -47,9 +46,16 @@ + * state of the power button. + */ + +- if (*IXP4XX_GPIO_GPINR & DSMG600_PB_BM) { ++ if (gpio_get_value(DSMG600_PB_GPIO)) { + + /* IO Pin is 1 (button pushed) */ ++ if (power_button_countdown > 0) { ++ power_button_countdown--; ++ } ++ ++ } else { ++ ++ /* Done on button release, to allow for auto-power-on mods. */ + if (power_button_countdown == 0) { + /* Signal init to do the ctrlaltdel action, this will bypass + * init if it hasn't started and do a kernel_restart. +@@ -58,11 +64,9 @@ + + /* Change the state of the power LED to "blink" */ + gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW); ++ } else { ++ power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + } +- power_button_countdown--; +- +- } else { +- power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + } + + mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500)); +@@ -81,12 +85,12 @@ + if (!(machine_is_dsmg600())) + return 0; + +- if (request_irq(DSMG600_RB_IRQ, &dsmg600_reset_handler, ++ if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler, + IRQF_DISABLED | IRQF_TRIGGER_LOW, "DSM-G600 reset button", + NULL) < 0) { + + printk(KERN_DEBUG "Reset Button IRQ %d not available\n", +- DSMG600_RB_IRQ); ++ gpio_to_irq(DSMG600_RB_GPIO)); + + return -EIO; + } +@@ -114,7 +118,7 @@ + + del_timer_sync(&dsmg600_power_timer); + +- free_irq(DSMG600_RB_IRQ, NULL); ++ free_irq(gpio_to_irq(DSMG600_RB_GPIO), NULL); + } + + module_init(dsmg600_power_init); +Index: linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/dsmg600.h +=================================================================== +--- linux-2.6.23.12-armeb.orig/include/asm-arm/arch-ixp4xx/dsmg600.h 2008-01-11 16:20:26.000000000 +1030 ++++ linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/dsmg600.h 2008-01-11 16:20:30.000000000 +1030 +@@ -40,18 +40,13 @@ + /* Buttons */ + + #define DSMG600_PB_GPIO 15 /* power button */ +-#define DSMG600_PB_BM (1L << DSMG600_PB_GPIO) +- + #define DSMG600_RB_GPIO 3 /* reset button */ + +-#define DSMG600_RB_IRQ IRQ_IXP4XX_GPIO3 ++/* Power control */ + + #define DSMG600_PO_GPIO 2 /* power off */ + + /* LEDs */ + + #define DSMG600_LED_PWR_GPIO 0 +-#define DSMG600_LED_PWR_BM (1L << DSMG600_LED_PWR_GPIO) +- + #define DSMG600_LED_WLAN_GPIO 14 +-#define DSMG600_LED_WLAN_BM (1L << DSMG600_LED_WLAN_GPIO) diff --git a/target/linux/ixp4xx/patches-2.6.24/017-nas100d_auto_power_on.patch b/target/linux/ixp4xx/patches-2.6.24/017-nas100d_auto_power_on.patch new file mode 100644 index 0000000000..b77df4850b --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/017-nas100d_auto_power_on.patch @@ -0,0 +1,188 @@ +Upgrade the power and reset button handling for the NAS100D: + * Convert GPIO and IRQ handling to use the <asm/gpio.h> api. + * Perform the reset only after the power button has been held down + for at least two seconds. Do the reset on the release of the power + button, so that NAS devices which have been set to auto-power-on (by + bridging the power button) do not continuously power cycle. + * Remove all superflous constants from nas100d.h + * Add LED constants to nas100d.h while we're there. +Also, update the board LED setup code to use constants. + +Signed-off-by: Rod Whitby <rod@whitby.id.au> + +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/nas100d-power.c +=================================================================== +--- linux-2.6.23.12-armeb.orig/arch/arm/mach-ixp4xx/nas100d-power.c 2008-01-11 16:59:20.000000000 +1030 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/nas100d-power.c 2008-01-11 17:03:23.000000000 +1030 +@@ -21,15 +21,61 @@ + #include <linux/irq.h> + #include <linux/module.h> + #include <linux/reboot.h> ++#include <linux/jiffies.h> ++#include <linux/timer.h> + ++#include <asm/gpio.h> + #include <asm/mach-types.h> + +-static irqreturn_t nas100d_reset_handler(int irq, void *dev_id) ++extern void ctrl_alt_del(void); ++ ++/* This is used to make sure the power-button pusher is serious. The button ++ * must be held until the value of this counter reaches zero. ++ */ ++static volatile int power_button_countdown; ++ ++/* Must hold the button down for at least this many counts to be processed */ ++#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */ ++ ++static void nas100d_power_handler(unsigned long data); ++static DEFINE_TIMER(nas100d_power_timer, nas100d_power_handler, 0, 0); ++ ++static void nas100d_power_handler(unsigned long data) + { +- /* Signal init to do the ctrlaltdel action, this will bypass init if +- * it hasn't started and do a kernel_restart. ++ /* This routine is called twice per second to check the ++ * state of the power button. + */ +- ctrl_alt_del(); ++ ++ if (gpio_get_value(NAS100D_PB_GPIO)) { ++ ++ /* IO Pin is 1 (button pushed) */ ++ if (power_button_countdown > 0) { ++ power_button_countdown--; ++ } ++ ++ } else { ++ ++ /* Done on button release, to allow for auto-power-on mods. */ ++ if (power_button_countdown == 0) { ++ /* Signal init to do the ctrlaltdel action, this will bypass ++ * init if it hasn't started and do a kernel_restart. ++ */ ++ ctrl_alt_del(); ++ ++ /* Change the state of the power LED to "blink" */ ++ gpio_line_set(NAS100D_LED_PWR_GPIO, IXP4XX_GPIO_LOW); ++ } else { ++ power_button_countdown = PBUTTON_HOLDDOWN_COUNT; ++ } ++ } ++ ++ mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); ++} ++ ++static irqreturn_t nas100d_reset_handler(int irq, void *dev_id) ++{ ++ /* This is the paper-clip reset, it shuts the machine down directly. */ ++ machine_power_off(); + + return IRQ_HANDLED; + } +@@ -39,17 +85,30 @@ + if (!(machine_is_nas100d())) + return 0; + +- set_irq_type(NAS100D_RB_IRQ, IRQT_LOW); ++ set_irq_type(gpio_to_irq(NAS100D_RB_GPIO), IRQT_LOW); + +- if (request_irq(NAS100D_RB_IRQ, &nas100d_reset_handler, ++ if (request_irq(gpio_to_irq(NAS100D_RB_GPIO), &nas100d_reset_handler, + IRQF_DISABLED, "NAS100D reset button", NULL) < 0) { + + printk(KERN_DEBUG "Reset Button IRQ %d not available\n", +- NAS100D_RB_IRQ); ++ gpio_to_irq(NAS100D_RB_GPIO)); + + return -EIO; + } + ++ /* The power button on the Iomega NAS100d is on GPIO 14, but ++ * it cannot handle interrupts on that GPIO line. So we'll ++ * have to poll it with a kernel timer. ++ */ ++ ++ /* Make sure that the power button GPIO is set up as an input */ ++ gpio_line_config(NAS100D_PB_GPIO, IXP4XX_GPIO_IN); ++ ++ /* Set the initial value for the power button IRQ handler */ ++ power_button_countdown = PBUTTON_HOLDDOWN_COUNT; ++ ++ mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); ++ + return 0; + } + +@@ -58,7 +117,9 @@ + if (!(machine_is_nas100d())) + return; + +- free_irq(NAS100D_RB_IRQ, NULL); ++ del_timer_sync(&nas100d_power_timer); ++ ++ free_irq(gpio_to_irq(NAS100D_RB_GPIO), NULL); + } + + module_init(nas100d_power_init); +Index: linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/nas100d.h +=================================================================== +--- linux-2.6.23.12-armeb.orig/include/asm-arm/arch-ixp4xx/nas100d.h 2008-01-11 16:59:20.000000000 +1030 ++++ linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/nas100d.h 2008-01-11 17:03:23.000000000 +1030 +@@ -38,15 +38,15 @@ + + /* Buttons */ + +-#define NAS100D_PB_GPIO 14 +-#define NAS100D_RB_GPIO 4 ++#define NAS100D_PB_GPIO 14 /* power button */ ++#define NAS100D_RB_GPIO 4 /* reset button */ ++ ++/* Power control */ ++ + #define NAS100D_PO_GPIO 12 /* power off */ + +-#define NAS100D_PB_IRQ IRQ_IXP4XX_GPIO14 +-#define NAS100D_RB_IRQ IRQ_IXP4XX_GPIO4 ++/* LEDs */ + +-/* +-#define NAS100D_PB_BM (1L << NAS100D_PB_GPIO) +-#define NAS100D_PO_BM (1L << NAS100D_PO_GPIO) +-#define NAS100D_RB_BM (1L << NAS100D_RB_GPIO) +-*/ ++#define NAS100D_LED_WLAN_GPIO 0 ++#define NAS100D_LED_DISK_GPIO 3 ++#define NAS100D_LED_PWR_GPIO 15 +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/nas100d-setup.c +=================================================================== +--- linux-2.6.23.12-armeb.orig/arch/arm/mach-ixp4xx/nas100d-setup.c 2008-01-11 17:03:23.000000000 +1030 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/nas100d-setup.c 2008-01-11 17:06:15.000000000 +1030 +@@ -44,20 +44,20 @@ + static struct resource nas100d_led_resources[] = { + { + .name = "wlan", /* green led */ +- .start = 0, +- .end = 0, ++ .start = NAS100D_LED_WLAN_GPIO, ++ .end = NAS100D_LED_WLAN_GPIO, + .flags = IXP4XX_GPIO_LOW, + }, + { +- .name = "ready", /* blue power led (off is flashing!) */ +- .start = 15, +- .end = 15, ++ .name = "power", /* blue power led (off is flashing!) */ ++ .start = NAS100D_LED_PWR_GPIO, ++ .end = NAS100D_LED_PWR_GPIO, + .flags = IXP4XX_GPIO_LOW, + }, + { + .name = "disk", /* yellow led */ +- .start = 3, +- .end = 3, ++ .start = NAS100D_LED_DISK_GPIO, ++ .end = NAS100D_LED_DISK_GPIO, + .flags = IXP4XX_GPIO_LOW, + }, + }; diff --git a/target/linux/ixp4xx/patches-2.6.24/020-ixp4xx_i2c_gpio.patch b/target/linux/ixp4xx/patches-2.6.24/020-ixp4xx_i2c_gpio.patch new file mode 100644 index 0000000000..b1b5612320 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/020-ixp4xx_i2c_gpio.patch @@ -0,0 +1,232 @@ +Migrate all ixp4xx devices to the bitbanging I2C bus driver utilizing +the arch-neutral GPIO API (linux/i2c-gpio.h). + +Tested by the nslu2-linux and openwrt projects in public firmware releases. + +Acked-by: Rod Whitby <rod@whitby.id.au> +Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk> + +Index: linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/nslu2-setup.c +=================================================================== +--- linux-2.6.24-rc6-armeb.orig/arch/arm/mach-ixp4xx/nslu2-setup.c 2008-01-05 18:10:05.000000000 +1030 ++++ linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/nslu2-setup.c 2008-01-05 18:10:10.000000000 +1030 +@@ -18,6 +18,7 @@ + #include <linux/serial.h> + #include <linux/serial_8250.h> + #include <linux/leds.h> ++#include <linux/i2c-gpio.h> + + #include <asm/mach-types.h> + #include <asm/mach/arch.h> +@@ -41,7 +42,7 @@ + .resource = &nslu2_flash_resource, + }; + +-static struct ixp4xx_i2c_pins nslu2_i2c_gpio_pins = { ++static struct i2c_gpio_platform_data nslu2_i2c_gpio_data = { + .sda_pin = NSLU2_SDA_PIN, + .scl_pin = NSLU2_SCL_PIN, + }; +@@ -82,11 +83,12 @@ + }; + #endif + +-static struct platform_device nslu2_i2c_controller = { +- .name = "IXP4XX-I2C", ++static struct platform_device nslu2_i2c_gpio = { ++ .name = "i2c-gpio", + .id = 0, +- .dev.platform_data = &nslu2_i2c_gpio_pins, +- .num_resources = 0, ++ .dev = { ++ .platform_data = &nslu2_i2c_gpio_data, ++ }, + }; + + static struct platform_device nslu2_beeper = { +@@ -139,7 +141,7 @@ + }; + + static struct platform_device *nslu2_devices[] __initdata = { +- &nslu2_i2c_controller, ++ &nslu2_i2c_gpio, + &nslu2_flash, + &nslu2_beeper, + #ifdef CONFIG_LEDS_IXP4XX +Index: linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/nas100d-setup.c +=================================================================== +--- linux-2.6.24-rc6-armeb.orig/arch/arm/mach-ixp4xx/nas100d-setup.c 2008-01-05 18:10:05.000000000 +1030 ++++ linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/nas100d-setup.c 2008-01-05 18:10:10.000000000 +1030 +@@ -16,6 +16,7 @@ + #include <linux/serial.h> + #include <linux/serial_8250.h> + #include <linux/leds.h> ++#include <linux/i2c-gpio.h> + + #include <asm/mach-types.h> + #include <asm/mach/arch.h> +@@ -68,16 +69,17 @@ + }; + #endif + +-static struct ixp4xx_i2c_pins nas100d_i2c_gpio_pins = { ++static struct i2c_gpio_platform_data nas100d_i2c_gpio_data = { + .sda_pin = NAS100D_SDA_PIN, + .scl_pin = NAS100D_SCL_PIN, + }; + +-static struct platform_device nas100d_i2c_controller = { +- .name = "IXP4XX-I2C", ++static struct platform_device nas100d_i2c_gpio = { ++ .name = "i2c-gpio", + .id = 0, +- .dev.platform_data = &nas100d_i2c_gpio_pins, +- .num_resources = 0, ++ .dev = { ++ .platform_data = &nas100d_i2c_gpio_data, ++ }, + }; + + static struct resource nas100d_uart_resources[] = { +@@ -124,7 +126,7 @@ + }; + + static struct platform_device *nas100d_devices[] __initdata = { +- &nas100d_i2c_controller, ++ &nas100d_i2c_gpio, + &nas100d_flash, + #ifdef CONFIG_LEDS_IXP4XX + &nas100d_leds, +Index: linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/avila-setup.c +=================================================================== +--- linux-2.6.24-rc6-armeb.orig/arch/arm/mach-ixp4xx/avila-setup.c 2008-01-05 18:10:05.000000000 +1030 ++++ linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/avila-setup.c 2008-01-05 18:10:10.000000000 +1030 +@@ -18,6 +18,7 @@ + #include <linux/tty.h> + #include <linux/serial_8250.h> + #include <linux/slab.h> ++#include <linux/i2c-gpio.h> + + #include <asm/types.h> + #include <asm/setup.h> +@@ -47,18 +48,17 @@ + .resource = &avila_flash_resource, + }; + +-static struct ixp4xx_i2c_pins avila_i2c_gpio_pins = { ++static struct i2c_gpio_platform_data avila_i2c_gpio_data = { + .sda_pin = AVILA_SDA_PIN, + .scl_pin = AVILA_SCL_PIN, + }; + +-static struct platform_device avila_i2c_controller = { +- .name = "IXP4XX-I2C", ++static struct platform_device avila_i2c_gpio = { ++ .name = "i2c-gpio", + .id = 0, +- .dev = { +- .platform_data = &avila_i2c_gpio_pins, ++ .dev = { ++ .platform_data = &avila_i2c_gpio_data, + }, +- .num_resources = 0 + }; + + static struct resource avila_uart_resources[] = { +@@ -133,7 +133,7 @@ + }; + + static struct platform_device *avila_devices[] __initdata = { +- &avila_i2c_controller, ++ &avila_i2c_gpio, + &avila_flash, + &avila_uart + }; +Index: linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c +=================================================================== +--- linux-2.6.24-rc6-armeb.orig/arch/arm/mach-ixp4xx/dsmg600-setup.c 2008-01-05 18:10:05.000000000 +1030 ++++ linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c 2008-01-05 18:10:10.000000000 +1030 +@@ -14,6 +14,7 @@ + #include <linux/kernel.h> + #include <linux/serial.h> + #include <linux/serial_8250.h> ++#include <linux/i2c-gpio.h> + + #include <asm/mach-types.h> + #include <asm/mach/arch.h> +@@ -37,15 +38,17 @@ + .resource = &dsmg600_flash_resource, + }; + +-static struct ixp4xx_i2c_pins dsmg600_i2c_gpio_pins = { ++static struct i2c_gpio_platform_data dsmg600_i2c_gpio_data = { + .sda_pin = DSMG600_SDA_PIN, + .scl_pin = DSMG600_SCL_PIN, + }; + +-static struct platform_device dsmg600_i2c_controller = { +- .name = "IXP4XX-I2C", ++static struct platform_device dsmg600_i2c_gpio = { ++ .name = "i2c-gpio", + .id = 0, +- .dev.platform_data = &dsmg600_i2c_gpio_pins, ++ .dev = { ++ .platform_data = &dsmg600_i2c_gpio_data, ++ }, + }; + + #ifdef CONFIG_LEDS_CLASS +@@ -116,7 +119,7 @@ + }; + + static struct platform_device *dsmg600_devices[] __initdata = { +- &dsmg600_i2c_controller, ++ &dsmg600_i2c_gpio, + &dsmg600_flash, + }; + +Index: linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/ixdp425-setup.c +=================================================================== +--- linux-2.6.24-rc6-armeb.orig/arch/arm/mach-ixp4xx/ixdp425-setup.c 2008-01-05 18:10:05.000000000 +1030 ++++ linux-2.6.24-rc6-armeb/arch/arm/mach-ixp4xx/ixdp425-setup.c 2008-01-05 18:10:10.000000000 +1030 +@@ -15,6 +15,7 @@ + #include <linux/tty.h> + #include <linux/serial_8250.h> + #include <linux/slab.h> ++#include <linux/i2c-gpio.h> + #include <linux/io.h> + #include <linux/mtd/mtd.h> + #include <linux/mtd/nand.h> +@@ -120,18 +121,17 @@ + }; + #endif /* CONFIG_MTD_NAND_PLATFORM */ + +-static struct ixp4xx_i2c_pins ixdp425_i2c_gpio_pins = { ++static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = { + .sda_pin = IXDP425_SDA_PIN, + .scl_pin = IXDP425_SCL_PIN, + }; + +-static struct platform_device ixdp425_i2c_controller = { +- .name = "IXP4XX-I2C", ++static struct platform_device ixdp425_i2c_gpio = { ++ .name = "i2c-gpio", + .id = 0, +- .dev = { +- .platform_data = &ixdp425_i2c_gpio_pins, ++ .dev = { ++ .platform_data = &ixdp425_i2c_gpio_data, + }, +- .num_resources = 0 + }; + + static struct resource ixdp425_uart_resources[] = { +@@ -178,7 +178,7 @@ + }; + + static struct platform_device *ixdp425_devices[] __initdata = { +- &ixdp425_i2c_controller, ++ &ixdp425_i2c_gpio, + &ixdp425_flash, + #if defined(CONFIG_MTD_NAND_PLATFORM) || \ + defined(CONFIG_MTD_NAND_PLATFORM_MODULE) diff --git a/target/linux/ixp4xx/patches-2.6.24/030-ixp4xx_fsg_board_support.patch b/target/linux/ixp4xx/patches-2.6.24/030-ixp4xx_fsg_board_support.patch new file mode 100644 index 0000000000..c133034e50 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/030-ixp4xx_fsg_board_support.patch @@ -0,0 +1,794 @@ +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-pci.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-pci.c 2008-01-11 17:06:33.000000000 +1030 +@@ -0,0 +1,71 @@ ++/* ++ * arch/arch/mach-ixp4xx/fsg-pci.c ++ * ++ * FSG board-level PCI initialization ++ * ++ * Author: Rod Whitby <rod@whitby.id.au> ++ * Maintainer: http://www.nslu2-linux.org/ ++ * ++ * based on ixdp425-pci.c: ++ * Copyright (C) 2002 Intel Corporation. ++ * Copyright (C) 2003-2004 MontaVista Software, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/pci.h> ++#include <linux/init.h> ++#include <linux/irq.h> ++ ++#include <asm/mach/pci.h> ++#include <asm/mach-types.h> ++ ++void __init fsg_pci_preinit(void) ++{ ++ set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW); ++ set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW); ++ set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ static int pci_irq_table[FSG_PCI_IRQ_LINES] = { ++ IRQ_FSG_PCI_INTC, ++ IRQ_FSG_PCI_INTB, ++ IRQ_FSG_PCI_INTA, ++ }; ++ ++ int irq = -1; ++ slot = slot - 11; ++ ++ if (slot >= 1 && slot <= FSG_PCI_MAX_DEV && ++ pin >= 1 && pin <= FSG_PCI_IRQ_LINES) { ++ irq = pci_irq_table[(slot - 1)]; ++ } ++ printk("%s: Mapped slot %d pin %d to IRQ %d\n", __FUNCTION__,slot, pin, irq); ++ ++ return irq; ++} ++ ++struct hw_pci fsg_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = fsg_pci_preinit, ++ .swizzle = pci_std_swizzle, ++ .setup = ixp4xx_setup, ++ .scan = ixp4xx_scan_bus, ++ .map_irq = fsg_map_irq, ++}; ++ ++int __init fsg_pci_init(void) ++{ ++ if (machine_is_fsg()) ++ pci_common_init(&fsg_pci); ++ return 0; ++} ++ ++subsys_initcall(fsg_pci_init); +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-setup.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-setup.c 2008-01-11 17:06:33.000000000 +1030 +@@ -0,0 +1,220 @@ ++/* ++ * arch/arm/mach-ixp4xx/fsg-setup.c ++ * ++ * FSG board-setup ++ * ++ * based ixdp425-setup.c: ++ * Copyright (C) 2003-2004 MontaVista Software, Inc. ++ * ++ * Author: Rod Whitby <rod@whitby.id.au> ++ * Maintainers: http://www.nslu2-linux.org/ ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/serial.h> ++#include <linux/serial_8250.h> ++#include <linux/leds.h> ++#include <linux/reboot.h> ++#include <linux/i2c-gpio.h> ++ ++#include <asm/mach-types.h> ++#include <asm/mach/arch.h> ++#include <asm/mach/flash.h> ++#include <asm/io.h> ++ ++static struct flash_platform_data fsg_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource fsg_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device fsg_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev.platform_data = &fsg_flash_data, ++ .num_resources = 1, ++ .resource = &fsg_flash_resource, ++}; ++ ++static struct i2c_gpio_platform_data fsg_i2c_gpio_data = { ++ .sda_pin = FSG_SDA_PIN, ++ .scl_pin = FSG_SCL_PIN, ++}; ++ ++static struct platform_device fsg_i2c_gpio = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &fsg_i2c_gpio_data, ++ }, ++}; ++ ++static struct resource fsg_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct plat_serial8250_port fsg_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { } ++}; ++ ++static struct platform_device fsg_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = fsg_uart_data, ++ .num_resources = ARRAY_SIZE(fsg_uart_resources), ++ .resource = fsg_uart_resources, ++}; ++ ++static struct platform_device fsg_leds = { ++ .name = "fsg-led", ++ .id = -1, ++}; ++ ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info fsg_plat_eth[] = { ++ { ++ .phy = 5, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 4, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device fsg_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = fsg_plat_eth, ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = fsg_plat_eth + 1, ++ } ++}; ++ ++static struct platform_device *fsg_devices[] __initdata = { ++ &fsg_i2c_gpio, ++ &fsg_flash, ++ &fsg_leds, ++ &fsg_eth[0], ++ &fsg_eth[1], ++}; ++ ++static void fsg_power_off(void) ++{ ++ printk("Restarting system.\n"); ++ machine_restart(NULL); ++} ++ ++static void __init fsg_init(void) ++{ ++ uint8_t __iomem *f; ++ int i; ++ ++ ixp4xx_sys_init(); ++ ++ pm_power_off = fsg_power_off; ++ ++ fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ fsg_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ /* Configure CS2 for operation, 8bit and writable */ ++ *IXP4XX_EXP_CS2 = 0xbfff0002; ++ ++ /* This is only useful on a modified machine, but it is valuable ++ * to have it first in order to see debug messages, and so that ++ * it does *not* get removed if platform_add_devices fails! ++ */ ++ (void)platform_device_register(&fsg_uart); ++ ++ platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices)); ++ ++ ++ /* ++ * Map in a portion of the flash and read the MAC addresses. ++ * Since it is stored in BE in the flash itself, we need to ++ * byteswap it if we're in LE mode. ++ */ ++ if ((f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x400000))) { ++#ifdef __ARMEB__ ++ for (i = 0; i < 6; i++) { ++ fsg_plat_eth[0].hwaddr[i] = readb(f + 0x3C0422 + i); ++ fsg_plat_eth[1].hwaddr[i] = readb(f + 0x3C043B + i); ++ } ++#else ++ fsg_plat_eth[0].hwaddr[0] = readb(f + 0x3C0422 + 3); ++ fsg_plat_eth[0].hwaddr[1] = readb(f + 0x3C0422 + 2); ++ fsg_plat_eth[0].hwaddr[2] = readb(f + 0x3C0422 + 1); ++ fsg_plat_eth[0].hwaddr[3] = readb(f + 0x3C0422 + 0); ++ fsg_plat_eth[0].hwaddr[4] = readb(f + 0x3C0422 + 7); ++ fsg_plat_eth[0].hwaddr[5] = readb(f + 0x3C0422 + 6); ++ ++ fsg_plat_eth[1].hwaddr[0] = readb(f + 0x3C0422 + 3); ++ fsg_plat_eth[1].hwaddr[1] = readb(f + 0x3C0422 + 2); ++ fsg_plat_eth[1].hwaddr[2] = readb(f + 0x3C0422 + 1); ++ fsg_plat_eth[1].hwaddr[3] = readb(f + 0x3C0422 + 0); ++ fsg_plat_eth[1].hwaddr[4] = readb(f + 0x3C0422 + 7); ++ fsg_plat_eth[1].hwaddr[5] = readb(f + 0x3C0422 + 6); ++#endif ++ iounmap(f); ++ } ++ printk(KERN_INFO "FSG: Using MAC address %.2x:%.2x:%.2x:%.2x:%.2x:%.2x for port 0\n", ++ fsg_plat_eth[0].hwaddr[0], fsg_plat_eth[0].hwaddr[1], ++ fsg_plat_eth[0].hwaddr[2], fsg_plat_eth[0].hwaddr[3], ++ fsg_plat_eth[0].hwaddr[4], fsg_plat_eth[0].hwaddr[5]); ++ printk(KERN_INFO "FSG: Using MAC address %.2x:%.2x:%.2x:%.2x:%.2x:%.2x for port 1\n", ++ fsg_plat_eth[1].hwaddr[0], fsg_plat_eth[1].hwaddr[1], ++ fsg_plat_eth[1].hwaddr[2], fsg_plat_eth[1].hwaddr[3], ++ fsg_plat_eth[1].hwaddr[4], fsg_plat_eth[1].hwaddr[5]); ++ ++} ++ ++MACHINE_START(FSG, "Freecom FSG-3") ++ /* Maintainer: www.nslu2-linux.org */ ++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, ++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .timer = &ixp4xx_timer, ++ .boot_params = 0x0100, ++ .init_machine = fsg_init, ++MACHINE_END ++ +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/Kconfig +=================================================================== +--- linux-2.6.23.12-armeb.orig/arch/arm/mach-ixp4xx/Kconfig 2008-01-11 17:05:08.000000000 +1030 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/Kconfig 2008-01-11 17:06:33.000000000 +1030 +@@ -125,6 +125,15 @@ + depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435 + default y + ++config MACH_FSG ++ bool ++ prompt "Freecom FSG-3" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Freecom's ++ FSG-3 device. For more information on this platform, ++ see http://www.nslu2-linux.org/wiki/FSG3/HomePage ++ + # + # Certain registers and IRQs are only enabled if supporting IXP465 CPUs + # +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/Makefile +=================================================================== +--- linux-2.6.23.12-armeb.orig/arch/arm/mach-ixp4xx/Makefile 2008-01-11 17:05:08.000000000 +1030 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/Makefile 2008-01-11 17:06:33.000000000 +1030 +@@ -15,6 +15,7 @@ + obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o + obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o + obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o ++obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + + obj-y += common.o + +@@ -28,6 +29,7 @@ + obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o dsmg600-power.o + obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o + obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o ++obj-$(CONFIG_MACH_FSG) += fsg-setup.o fsg-power.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +Index: linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/fsg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/fsg.h 2008-01-11 17:06:33.000000000 +1030 +@@ -0,0 +1,50 @@ ++/* ++ * include/asm-arm/arch-ixp4xx/fsg.h ++ * ++ * Freecom FSG-3 platform specific definitions ++ * ++ * Author: Rod Whitby <rod@whitby.id.au> ++ * Author: Tomasz Chmielewski <mangoo@wpkg.org> ++ * Maintainers: http://www.nslu2-linux.org ++ * ++ * Based on coyote.h by ++ * Copyright 2004 (c) MontaVista, Software, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __ASM_ARCH_HARDWARE_H__ ++#error "Do not include this directly, instead #include <asm/hardware.h>" ++#endif ++ ++#define FSG_SDA_PIN 12 ++#define FSG_SCL_PIN 13 ++ ++/* ++ * FSG PCI IRQs ++ */ ++#define FSG_PCI_MAX_DEV 3 ++#define FSG_PCI_IRQ_LINES 3 ++ ++ ++/* PCI controller GPIO to IRQ pin mappings */ ++#define FSG_PCI_INTA_PIN 6 ++#define FSG_PCI_INTB_PIN 7 ++#define FSG_PCI_INTC_PIN 5 ++ ++/* Buttons */ ++ ++#define FSG_SB_GPIO 4 /* sync button */ ++#define FSG_RB_GPIO 9 /* reset button */ ++#define FSG_UB_GPIO 10 /* usb button */ ++ ++/* LEDs */ ++ ++#define FSG_LED_WLAN_BIT 0 ++#define FSG_LED_WAN_BIT 1 ++#define FSG_LED_SATA_BIT 2 ++#define FSG_LED_USB_BIT 4 ++#define FSG_LED_RING_BIT 5 ++#define FSG_LED_SYNC_BIT 7 +Index: linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/hardware.h +=================================================================== +--- linux-2.6.23.12-armeb.orig/include/asm-arm/arch-ixp4xx/hardware.h 2008-01-11 17:05:08.000000000 +1030 ++++ linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/hardware.h 2008-01-11 17:06:33.000000000 +1030 +@@ -45,5 +45,6 @@ + #include "nslu2.h" + #include "nas100d.h" + #include "dsmg600.h" ++#include "fsg.h" + + #endif /* _ASM_ARCH_HARDWARE_H */ +Index: linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/irqs.h +=================================================================== +--- linux-2.6.23.12-armeb.orig/include/asm-arm/arch-ixp4xx/irqs.h 2008-01-11 17:05:08.000000000 +1030 ++++ linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/irqs.h 2008-01-11 17:06:33.000000000 +1030 +@@ -128,4 +128,11 @@ + #define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 + #define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 + ++/* ++ * Freecom FSG-3 Board IRQs ++ */ ++#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 ++#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 ++#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 ++ + #endif +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-power.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-power.c 2008-01-11 17:06:33.000000000 +1030 +@@ -0,0 +1,89 @@ ++/* ++ * arch/arm/mach-ixp4xx/fsg-power.c ++ * ++ * FSG Power/Reset driver ++ * ++ * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au> ++ * ++ * based on nslu2-power.c ++ * Copyright (C) 2005 Tower Technologies ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/module.h> ++#include <linux/reboot.h> ++#include <linux/interrupt.h> ++#include <linux/irq.h> ++#include <linux/jiffies.h> ++#include <linux/timer.h> ++ ++#include <asm/gpio.h> ++#include <asm/mach-types.h> ++ ++static irqreturn_t fsg_power_handler(int irq, void *dev_id) ++{ ++ /* Signal init to do the ctrlaltdel action, this will bypass init if ++ * it hasn't started and do a kernel_restart. ++ */ ++ ctrl_alt_del(); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t fsg_reset_handler(int irq, void *dev_id) ++{ ++ /* This is the paper-clip reset, it shuts the machine down directly. ++ */ ++ machine_power_off(); ++ ++ return IRQ_HANDLED; ++} ++ ++static int __init fsg_power_init(void) ++{ ++ if (!(machine_is_fsg())) ++ return 0; ++ ++ set_irq_type(gpio_to_irq(FSG_RB_GPIO), IRQT_LOW); ++ set_irq_type(gpio_to_irq(FSG_SB_GPIO), IRQT_LOW); ++ ++ if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler, ++ IRQF_DISABLED, "FSG reset button", NULL) < 0) { ++ ++ printk(KERN_DEBUG "Reset Button IRQ %d not available\n", ++ gpio_to_irq(FSG_RB_GPIO)); ++ ++ return -EIO; ++ } ++ ++ if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler, ++ IRQF_DISABLED, "FSG power button", NULL) < 0) { ++ ++ printk(KERN_DEBUG "Power Button IRQ %d not available\n", ++ gpio_to_irq(FSG_SB_GPIO)); ++ ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static void __exit fsg_power_exit(void) ++{ ++ if (!(machine_is_fsg())) ++ return; ++ ++ free_irq(gpio_to_irq(FSG_SB_GPIO), NULL); ++ free_irq(gpio_to_irq(FSG_RB_GPIO), NULL); ++} ++ ++module_init(fsg_power_init); ++module_exit(fsg_power_exit); ++ ++MODULE_AUTHOR("Rod Whitby <rod@whitby.id.au>"); ++MODULE_DESCRIPTION("FSG Power/Reset driver"); ++MODULE_LICENSE("GPL"); +Index: linux-2.6.23.12-armeb/drivers/leds/Kconfig +=================================================================== +--- linux-2.6.23.12-armeb.orig/drivers/leds/Kconfig 2008-01-11 17:05:08.000000000 +1030 ++++ linux-2.6.23.12-armeb/drivers/leds/Kconfig 2008-01-11 17:06:33.000000000 +1030 +@@ -48,6 +48,12 @@ + particular board must have LEDs and they must be connected + to the GPIO lines. If unsure, say Y. + ++config LEDS_FSG ++ tristate "LED Support for the Freecom FSG-3" ++ depends on LEDS_CLASS && MACH_FSG ++ help ++ This option enables support for the LEDs on the Freecom FSG-3. ++ + config LEDS_TOSA + tristate "LED Support for the Sharp SL-6000 series" + depends on LEDS_CLASS && PXA_SHARPSL +Index: linux-2.6.23.12-armeb/drivers/leds/Makefile +=================================================================== +--- linux-2.6.23.12-armeb.orig/drivers/leds/Makefile 2008-01-11 17:05:08.000000000 +1030 ++++ linux-2.6.23.12-armeb/drivers/leds/Makefile 2008-01-11 17:06:33.000000000 +1030 +@@ -9,6 +9,7 @@ + obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o + obj-$(CONFIG_LEDS_SPITZ) += leds-spitz.o + obj-$(CONFIG_LEDS_IXP4XX) += leds-ixp4xx-gpio.o ++obj-$(CONFIG_LEDS_FSG) += leds-fsg.o + obj-$(CONFIG_LEDS_TOSA) += leds-tosa.o + obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o + obj-$(CONFIG_LEDS_AMS_DELTA) += leds-ams-delta.o +Index: linux-2.6.23.12-armeb/drivers/leds/leds-fsg.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12-armeb/drivers/leds/leds-fsg.c 2008-01-11 17:06:33.000000000 +1030 +@@ -0,0 +1,243 @@ ++/* ++ * LED Driver for the Freecom FSG-3 ++ * ++ * Copyright (c) 2008 Rod Whitby <rod@whitby.id.au> ++ * ++ * Author: Rod Whitby <rod@whitby.id.au> ++ * ++ * Based on leds-spitz.c ++ * Copyright 2005-2006 Openedhand Ltd. ++ * Author: Richard Purdie <rpurdie@openedhand.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/platform_device.h> ++#include <linux/leds.h> ++#include <asm/arch/hardware.h> ++#include <asm/io.h> ++ ++static short __iomem *latch_address; ++static unsigned short latch_value; ++ ++ ++static void fsg_led_wlan_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ if (value) { ++ latch_value &= ~(1 << FSG_LED_WLAN_BIT); ++ *latch_address = latch_value; ++ } ++ else { ++ latch_value |= (1 << FSG_LED_WLAN_BIT); ++ *latch_address = latch_value; ++ } ++} ++ ++static void fsg_led_wan_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ if (value) { ++ latch_value &= ~(1 << FSG_LED_WAN_BIT); ++ *latch_address = latch_value; ++ } ++ else { ++ latch_value |= (1 << FSG_LED_WAN_BIT); ++ *latch_address = latch_value; ++ } ++} ++ ++static void fsg_led_sata_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ if (value) { ++ latch_value &= ~(1 << FSG_LED_SATA_BIT); ++ *latch_address = latch_value; ++ } ++ else { ++ latch_value |= (1 << FSG_LED_SATA_BIT); ++ *latch_address = latch_value; ++ } ++} ++ ++static void fsg_led_usb_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ if (value) { ++ latch_value &= ~(1 << FSG_LED_USB_BIT); ++ *latch_address = latch_value; ++ } ++ else { ++ latch_value |= (1 << FSG_LED_USB_BIT); ++ *latch_address = latch_value; ++ } ++} ++ ++static void fsg_led_sync_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ if (value) { ++ latch_value &= ~(1 << FSG_LED_SYNC_BIT); ++ *latch_address = latch_value; ++ } ++ else { ++ latch_value |= (1 << FSG_LED_SYNC_BIT); ++ *latch_address = latch_value; ++ } ++} ++ ++static void fsg_led_ring_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ if (value) { ++ latch_value &= ~(1 << FSG_LED_RING_BIT); ++ *latch_address = latch_value; ++ } ++ else { ++ latch_value |= (1 << FSG_LED_RING_BIT); ++ *latch_address = latch_value; ++ } ++} ++ ++ ++ ++static struct led_classdev fsg_wlan_led = { ++ .name = "fsg:wlan", ++ .brightness_set = fsg_led_wlan_set, ++}; ++ ++static struct led_classdev fsg_wan_led = { ++ .name = "fsg:wan", ++ .brightness_set = fsg_led_wan_set, ++}; ++ ++static struct led_classdev fsg_sata_led = { ++ .name = "fsg:sata", ++ .brightness_set = fsg_led_sata_set, ++}; ++ ++static struct led_classdev fsg_usb_led = { ++ .name = "fsg:usb", ++ .brightness_set = fsg_led_usb_set, ++}; ++ ++static struct led_classdev fsg_sync_led = { ++ .name = "fsg:sync", ++ .brightness_set = fsg_led_sync_set, ++}; ++ ++static struct led_classdev fsg_ring_led = { ++ .name = "fsg:ring", ++ .brightness_set = fsg_led_ring_set, ++}; ++ ++ ++ ++#ifdef CONFIG_PM ++static int fsg_led_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ led_classdev_suspend(&fsg_wlan_led); ++ led_classdev_suspend(&fsg_wan_led); ++ led_classdev_suspend(&fsg_sata_led); ++ led_classdev_suspend(&fsg_usb_led); ++ led_classdev_suspend(&fsg_sync_led); ++ led_classdev_suspend(&fsg_ring_led); ++ return 0; ++} ++ ++static int fsg_led_resume(struct platform_device *dev) ++{ ++ led_classdev_resume(&fsg_wlan_led); ++ led_classdev_resume(&fsg_wan_led); ++ led_classdev_resume(&fsg_sata_led); ++ led_classdev_resume(&fsg_usb_led); ++ led_classdev_resume(&fsg_sync_led); ++ led_classdev_resume(&fsg_ring_led); ++ return 0; ++} ++#endif ++ ++ ++static int fsg_led_probe(struct platform_device *pdev) ++{ ++ int ret; ++ ++ /* FIXME: Need to work out how to handle failure below */ ++ ++ ret = led_classdev_register(&pdev->dev, &fsg_wlan_led); ++ if (ret < 0) ++ return ret; ++ ++ ret = led_classdev_register(&pdev->dev, &fsg_wan_led); ++ if (ret < 0) ++ return ret; ++ ++ ret = led_classdev_register(&pdev->dev, &fsg_sata_led); ++ if (ret < 0) ++ return ret; ++ ++ ret = led_classdev_register(&pdev->dev, &fsg_usb_led); ++ if (ret < 0) ++ return ret; ++ ++ ret = led_classdev_register(&pdev->dev, &fsg_sync_led); ++ if (ret < 0) ++ return ret; ++ ++ ret = led_classdev_register(&pdev->dev, &fsg_ring_led); ++ if (ret < 0) ++ return ret; ++ ++ return ret; ++} ++ ++static int fsg_led_remove(struct platform_device *pdev) ++{ ++ led_classdev_unregister(&fsg_wlan_led); ++ led_classdev_unregister(&fsg_wan_led); ++ led_classdev_unregister(&fsg_sata_led); ++ led_classdev_unregister(&fsg_usb_led); ++ led_classdev_unregister(&fsg_sync_led); ++ led_classdev_unregister(&fsg_ring_led); ++ ++ return 0; ++} ++ ++ ++static struct platform_driver fsg_led_driver = { ++ .probe = fsg_led_probe, ++ .remove = fsg_led_remove, ++#ifdef CONFIG_PM ++ .suspend = fsg_led_suspend, ++ .resume = fsg_led_resume, ++#endif ++ .driver = { ++ .name = "fsg-led", ++ }, ++}; ++ ++ ++static int __init fsg_led_init(void) ++{ ++ /* Map the LED chip select address space */ ++ latch_address = (unsigned short *) ioremap(IXP4XX_EXP_BUS_BASE(2), 512); ++ if (!latch_address) ++ return -ENOMEM; ++ latch_value = 0xffff; ++ *latch_address = latch_value; ++ /* FIXME: We leak memory if the next line fails */ ++ return platform_driver_register(&fsg_led_driver); ++} ++ ++static void __exit fsg_led_exit(void) ++{ ++ platform_driver_unregister(&fsg_led_driver); ++ iounmap(latch_address); ++} ++ ++ ++module_init(fsg_led_init); ++module_exit(fsg_led_exit); ++ ++MODULE_AUTHOR("Rod Whitby <rod@whitby.id.au>"); ++MODULE_DESCRIPTION("Freecom FSG-3 LED driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/ixp4xx/patches-2.6.24/031-ixp4xx-net-drivers-nslu2.patch b/target/linux/ixp4xx/patches-2.6.24/031-ixp4xx-net-drivers-nslu2.patch new file mode 100644 index 0000000000..d4c710c049 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/031-ixp4xx-net-drivers-nslu2.patch @@ -0,0 +1,88 @@ +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/nslu2-setup.c +=================================================================== +--- linux-2.6.23.12-armeb.orig/arch/arm/mach-ixp4xx/nslu2-setup.c 2008-01-08 15:28:13.000000000 +1030 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/nslu2-setup.c 2008-01-08 15:28:32.000000000 +1030 +@@ -24,6 +24,7 @@ + #include <asm/mach/arch.h> + #include <asm/mach/flash.h> + #include <asm/mach/time.h> ++#include <asm/io.h> + + static struct flash_platform_data nslu2_flash_data = { + .map_name = "cfi_probe", +@@ -140,6 +141,23 @@ + .resource = nslu2_uart_resources, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info nslu2_plat_eth[] = { ++ { ++ .phy = 1, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device nslu2_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = nslu2_plat_eth, ++ } ++}; ++ + static struct platform_device *nslu2_devices[] __initdata = { + &nslu2_i2c_gpio, + &nslu2_flash, +@@ -147,6 +165,7 @@ + #ifdef CONFIG_LEDS_IXP4XX + &nslu2_leds, + #endif ++ &nslu2_eth[0], + }; + + static void nslu2_power_off(void) +@@ -175,6 +194,9 @@ + + static void __init nslu2_init(void) + { ++ uint8_t __iomem *f; ++ int i; ++ + ixp4xx_sys_init(); + + nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); +@@ -191,6 +213,33 @@ + (void)platform_device_register(&nslu2_uart); + + platform_add_devices(nslu2_devices, ARRAY_SIZE(nslu2_devices)); ++ ++ ++ /* ++ * Map in a portion of the flash and read the MAC address. ++ * Since it is stored in BE in the flash itself, we need to ++ * byteswap it if we're in LE mode. ++ */ ++ if ((f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x40000))) { ++#ifdef __ARMEB__ ++ for (i = 0; i < 6; i++) { ++ nslu2_plat_eth[0].hwaddr[i] = readb(f + 0x3FFB0 + i); ++ } ++#else ++ nslu2_plat_eth[0].hwaddr[0] = readb(f + 0x3FFB0 + 3); ++ nslu2_plat_eth[0].hwaddr[1] = readb(f + 0x3FFB0 + 2); ++ nslu2_plat_eth[0].hwaddr[2] = readb(f + 0x3FFB0 + 1); ++ nslu2_plat_eth[0].hwaddr[3] = readb(f + 0x3FFB0 + 0); ++ nslu2_plat_eth[0].hwaddr[4] = readb(f + 0x3FFB0 + 7); ++ nslu2_plat_eth[0].hwaddr[5] = readb(f + 0x3FFB0 + 6); ++#endif ++ iounmap(f); ++ } ++ printk(KERN_INFO "NSLU2: Using MAC address %.2x:%.2x:%.2x:%.2x:%.2x:%.2x for port 0\n", ++ nslu2_plat_eth[0].hwaddr[0], nslu2_plat_eth[0].hwaddr[1], ++ nslu2_plat_eth[0].hwaddr[2], nslu2_plat_eth[0].hwaddr[3], ++ nslu2_plat_eth[0].hwaddr[4], nslu2_plat_eth[0].hwaddr[5]); ++ + } + + MACHINE_START(NSLU2, "Linksys NSLU2") diff --git a/target/linux/ixp4xx/patches-2.6.24/032-ixp4xx-net-drivers-nas100d.patch b/target/linux/ixp4xx/patches-2.6.24/032-ixp4xx-net-drivers-nas100d.patch new file mode 100644 index 0000000000..143473378e --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/032-ixp4xx-net-drivers-nas100d.patch @@ -0,0 +1,87 @@ +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/nas100d-setup.c +=================================================================== +--- linux-2.6.23.12-armeb.orig/arch/arm/mach-ixp4xx/nas100d-setup.c 2008-01-08 15:22:07.000000000 +1030 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/nas100d-setup.c 2008-01-08 15:32:32.000000000 +1030 +@@ -21,6 +21,7 @@ + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + #include <asm/mach/flash.h> ++#include <asm/io.h> + + static struct flash_platform_data nas100d_flash_data = { + .map_name = "cfi_probe", +@@ -125,12 +126,30 @@ + .resource = nas100d_uart_resources, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info nas100d_plat_eth[] = { ++ { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device nas100d_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = nas100d_plat_eth, ++ } ++}; ++ + static struct platform_device *nas100d_devices[] __initdata = { + &nas100d_i2c_gpio, + &nas100d_flash, + #ifdef CONFIG_LEDS_IXP4XX + &nas100d_leds, + #endif ++ &nas100d_eth[0], + }; + + static void nas100d_power_off(void) +@@ -146,6 +165,9 @@ + + static void __init nas100d_init(void) + { ++ uint8_t __iomem *f; ++ int i; ++ + ixp4xx_sys_init(); + + /* gpio 14 and 15 are _not_ clocks */ +@@ -165,6 +187,33 @@ + (void)platform_device_register(&nas100d_uart); + + platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices)); ++ ++ ++ /* ++ * Map in a portion of the flash and read the MAC address. ++ * Since it is stored in BE in the flash itself, we need to ++ * byteswap it if we're in LE mode. ++ */ ++ if ((f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x1000000))) { ++#ifdef __ARMEB__ ++ for (i = 0; i < 6; i++) { ++ nas100d_plat_eth[0].hwaddr[i] = readb(f + 0xFC0FD8 + i); ++ } ++#else ++ nas100d_plat_eth[0].hwaddr[0] = readb(f + 0xFC0FD8 + 3); ++ nas100d_plat_eth[0].hwaddr[1] = readb(f + 0xFC0FD8 + 2); ++ nas100d_plat_eth[0].hwaddr[2] = readb(f + 0xFC0FD8 + 1); ++ nas100d_plat_eth[0].hwaddr[3] = readb(f + 0xFC0FD8 + 0); ++ nas100d_plat_eth[0].hwaddr[4] = readb(f + 0xFC0FD8 + 7); ++ nas100d_plat_eth[0].hwaddr[5] = readb(f + 0xFC0FD8 + 6); ++#endif ++ iounmap(f); ++ } ++ printk(KERN_INFO "NAS100D: Using MAC address %.2x:%.2x:%.2x:%.2x:%.2x:%.2x for port 0\n", ++ nas100d_plat_eth[0].hwaddr[0], nas100d_plat_eth[0].hwaddr[1], ++ nas100d_plat_eth[0].hwaddr[2], nas100d_plat_eth[0].hwaddr[3], ++ nas100d_plat_eth[0].hwaddr[4], nas100d_plat_eth[0].hwaddr[5]); ++ + } + + MACHINE_START(NAS100D, "Iomega NAS 100d") diff --git a/target/linux/ixp4xx/patches-2.6.24/090-increase_entropy_pools.patch b/target/linux/ixp4xx/patches-2.6.24/090-increase_entropy_pools.patch new file mode 100644 index 0000000000..9a322a714a --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/090-increase_entropy_pools.patch @@ -0,0 +1,17 @@ +Index: linux-2.6.19/drivers/char/random.c +=================================================================== +--- linux-2.6.19.orig/drivers/char/random.c ++++ linux-2.6.19/drivers/char/random.c +@@ -248,9 +248,9 @@ + /* + * Configuration information + */ +-#define INPUT_POOL_WORDS 128 +-#define OUTPUT_POOL_WORDS 32 +-#define SEC_XFER_SIZE 512 ++#define INPUT_POOL_WORDS 256 ++#define OUTPUT_POOL_WORDS 64 ++#define SEC_XFER_SIZE 1024 + + /* + * The minimum number of bits of entropy before we wake up a read on diff --git a/target/linux/ixp4xx/patches-2.6.24/091-nslu2_rtc_fixup.patch b/target/linux/ixp4xx/patches-2.6.24/091-nslu2_rtc_fixup.patch new file mode 100644 index 0000000000..49ca1e2dc9 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/091-nslu2_rtc_fixup.patch @@ -0,0 +1,55 @@ +diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/nslu2-setup.c linux-2.6.23/arch/arm/mach-ixp4xx/nslu2-setup.c +--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/nslu2-setup.c 2007-10-09 15:31:38.000000000 -0500 ++++ linux-2.6.23/arch/arm/mach-ixp4xx/nslu2-setup.c 2007-10-11 01:04:46.000000000 -0500 +@@ -19,6 +19,7 @@ + #include <linux/serial_8250.h> + #include <linux/leds.h> + ++#include <asm/setup.h> + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + #include <asm/mach/flash.h> +@@ -171,6 +172,35 @@ static struct sys_timer nslu2_timer = { + .init = nslu2_timer_init, + }; + ++static char nslu2_rtc_probe[] __initdata = "rtc-isl1208.ignore=0,0x6f rtc-x1205.probe=0,0x6f "; ++ ++static void __init nslu2_fixup(struct machine_desc *desc, ++ struct tag *tags, char **cmdline, struct meminfo *mi) ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(nslu2_rtc_probe) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, nslu2_rtc_probe, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(nslu2_rtc_probe), p, ++ COMMAND_LINE_SIZE - strlen(nslu2_rtc_probe)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ + static void __init nslu2_init(void) + { + ixp4xx_sys_init(); +@@ -196,6 +226,7 @@ MACHINE_START(NSLU2, "Linksys NSLU2") + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC, + .boot_params = 0x00000100, ++ .fixup = nslu2_fixup, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &nslu2_timer, diff --git a/target/linux/ixp4xx/patches-2.6.24/092-nas100d_rtc_fixup.patch b/target/linux/ixp4xx/patches-2.6.24/092-nas100d_rtc_fixup.patch new file mode 100644 index 0000000000..a6fda86276 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/092-nas100d_rtc_fixup.patch @@ -0,0 +1,55 @@ +diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/nas100d-setup.c linux-2.6.23/arch/arm/mach-ixp4xx/nas100d-setup.c +--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/nas100d-setup.c 2007-10-09 15:31:38.000000000 -0500 ++++ linux-2.6.23/arch/arm/mach-ixp4xx/nas100d-setup.c 2007-10-11 01:06:33.000000000 -0500 +@@ -17,6 +17,7 @@ + #include <linux/serial_8250.h> + #include <linux/leds.h> + ++#include <asm/setup.h> + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + #include <asm/mach/flash.h> +@@ -142,6 +143,35 @@ static void nas100d_power_off(void) + gpio_line_set(NAS100D_PO_GPIO, IXP4XX_GPIO_HIGH); + } + ++static char nas100d_rtc_probe[] __initdata = "rtc-pcf8563.probe=0,0x51 "; ++ ++static void __init nas100d_fixup(struct machine_desc *desc, ++ struct tag *tags, char **cmdline, struct meminfo *mi) ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(nas100d_rtc_probe) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, nas100d_rtc_probe, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(nas100d_rtc_probe), p, ++ COMMAND_LINE_SIZE - strlen(nas100d_rtc_probe)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ + static void __init nas100d_init(void) + { + ixp4xx_sys_init(); +@@ -170,6 +200,7 @@ MACHINE_START(NAS100D, "Iomega NAS 100d" + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC, + .boot_params = 0x00000100, ++ .fixup = nas100d_fixup, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, diff --git a/target/linux/ixp4xx/patches-2.6.24/095-dsmg600_rtc_fixup.patch b/target/linux/ixp4xx/patches-2.6.24/095-dsmg600_rtc_fixup.patch new file mode 100644 index 0000000000..3d13501156 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/095-dsmg600_rtc_fixup.patch @@ -0,0 +1,56 @@ +Index: linux-2.6.22-rc4-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c +=================================================================== +--- linux-2.6.22-rc4-armeb.orig/arch/arm/mach-ixp4xx/dsmg600-setup.c ++++ linux-2.6.22-rc4-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c +@@ -16,6 +16,7 @@ + #include <linux/serial_8250.h> + #include <linux/i2c-gpio.h> + ++#include <asm/setup.h> + #include <asm/mach-types.h> + #include <asm/mach/arch.h> + #include <asm/mach/flash.h> +@@ -145,6 +146,35 @@ static struct sys_timer dsmg600_timer = + .init = dsmg600_timer_init, + }; + ++static char dsmg600_rtc_probe[] __initdata = "rtc-pcf8563.probe=0,0x51 "; ++ ++static void __init dsmg600_fixup(struct machine_desc *desc, ++ struct tag *tags, char **cmdline, struct meminfo *mi) ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(dsmg600_rtc_probe) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, dsmg600_rtc_probe, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(dsmg600_rtc_probe), p, ++ COMMAND_LINE_SIZE - strlen(dsmg600_rtc_probe)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ + static void __init dsmg600_init(void) + { + ixp4xx_sys_init(); +@@ -177,6 +207,7 @@ MACHINE_START(DSMG600, "D-Link DSM-G600 + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC, + .boot_params = 0x00000100, ++ .fixup = dsmg600_fixup, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &dsmg600_timer, diff --git a/target/linux/ixp4xx/patches-2.6.24/100-gateway7001_mac_plat_info.patch b/target/linux/ixp4xx/patches-2.6.24/100-gateway7001_mac_plat_info.patch new file mode 100644 index 0000000000..c7169ce2fb --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/100-gateway7001_mac_plat_info.patch @@ -0,0 +1,41 @@ +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/gateway7001-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/gateway7001-setup.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/gateway7001-setup.c 2007-10-09 22:31:38.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/gateway7001-setup.c 2007-10-22 15:09:33.000000000 +0200 +@@ -76,9 +76,36 @@ + .resource = &gateway7001_uart_resource, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info gateway7001_plat_eth[] = { ++ { ++ .phy = 1, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 2, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device gateway7001_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = gateway7001_plat_eth, ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = gateway7001_plat_eth + 1, ++ } ++}; ++ + static struct platform_device *gateway7001_devices[] __initdata = { + &gateway7001_flash, +- &gateway7001_uart ++ &gateway7001_uart, ++ &gateway7001_eth[0], ++ &gateway7001_eth[1], + }; + + static void __init gateway7001_init(void) diff --git a/target/linux/ixp4xx/patches-2.6.24/101-wg302_mac_plat_info.patch b/target/linux/ixp4xx/patches-2.6.24/101-wg302_mac_plat_info.patch new file mode 100644 index 0000000000..5209e72d5c --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/101-wg302_mac_plat_info.patch @@ -0,0 +1,31 @@ +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/wg302v2-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wg302v2-setup.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/wg302v2-setup.c 2007-10-09 22:31:38.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wg302v2-setup.c 2007-10-22 15:02:20.000000000 +0200 +@@ -77,9 +77,27 @@ + .resource = &wg302v2_uart_resource, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info wg302_plat_eth[] = { ++ { ++ .phy = 8, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device wg302_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = wg302_plat_eth, ++ } ++}; ++ + static struct platform_device *wg302v2_devices[] __initdata = { + &wg302v2_flash, + &wg302v2_uart, ++ &wg302_eth[0], + }; + + static void __init wg302v2_init(void) diff --git a/target/linux/ixp4xx/patches-2.6.24/110-pronghorn_metro_support.patch b/target/linux/ixp4xx/patches-2.6.24/110-pronghorn_metro_support.patch new file mode 100644 index 0000000000..80115b8401 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/110-pronghorn_metro_support.patch @@ -0,0 +1,297 @@ +Index: linux-2.6.23.12/arch/arm/mach-ixp4xx/Kconfig +=================================================================== +--- linux-2.6.23.12.orig/arch/arm/mach-ixp4xx/Kconfig 2008-01-05 13:30:14.000000000 +1030 ++++ linux-2.6.23.12/arch/arm/mach-ixp4xx/Kconfig 2008-01-05 13:37:05.000000000 +1030 +@@ -57,6 +57,14 @@ + WG302 v2 or WAG302 v2 Access Points. For more information + on this platform, see http://openwrt.org + ++config MACH_PRONGHORNMETRO ++ bool "Pronghorn Metro" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the ADI ++ Engineering Pronghorn Metro Platform. For more ++ information on this platform, see <file:Documentation/arm/IXP4xx>. ++ + config ARCH_IXDP425 + bool "IXDP425" + help +Index: linux-2.6.23.12/arch/arm/mach-ixp4xx/Makefile +=================================================================== +--- linux-2.6.23.12.orig/arch/arm/mach-ixp4xx/Makefile 2008-01-05 13:32:45.000000000 +1030 ++++ linux-2.6.23.12/arch/arm/mach-ixp4xx/Makefile 2008-01-05 13:37:37.000000000 +1030 +@@ -16,6 +16,7 @@ + obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o + obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o ++obj-pci-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-pci.o + + obj-y += common.o + +@@ -30,5 +31,6 @@ + obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o + obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o + obj-$(CONFIG_MACH_FSG) += fsg-setup.o fsg-power.o ++obj-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o +Index: linux-2.6.23.12/arch/arm/mach-ixp4xx/pronghornmetro-pci.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12/arch/arm/mach-ixp4xx/pronghornmetro-pci.c 2008-01-05 13:37:05.000000000 +1030 +@@ -0,0 +1,74 @@ ++/* ++ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c ++ * ++ * PCI setup routines for ADI Engineering Pronghorn Metro ++ * ++ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org> ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz <kaloz@openwrt.org> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/pci.h> ++#include <linux/init.h> ++#include <linux/irq.h> ++ ++#include <asm/mach-types.h> ++#include <asm/hardware.h> ++#include <asm/irq.h> ++ ++#include <asm/mach/pci.h> ++ ++extern void ixp4xx_pci_preinit(void); ++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); ++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); ++ ++void __init pronghornmetro_pci_preinit(void) ++{ ++ set_irq_type(IRQ_IXP4XX_GPIO4, IRQT_LOW); ++ set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW); ++ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW); ++ set_irq_type(IRQ_IXP4XX_GPIO1, IRQT_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init pronghornmetro_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 13) ++ return IRQ_IXP4XX_GPIO4; ++ else if (slot == 14) ++ return IRQ_IXP4XX_GPIO6; ++ else if (slot == 15) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 16) ++ return IRQ_IXP4XX_GPIO1; ++ else return -1; ++} ++ ++struct hw_pci pronghornmetro_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = pronghornmetro_pci_preinit, ++ .swizzle = pci_std_swizzle, ++ .setup = ixp4xx_setup, ++ .scan = ixp4xx_scan_bus, ++ .map_irq = pronghornmetro_map_irq, ++}; ++ ++int __init pronghornmetro_pci_init(void) ++{ ++ if (machine_is_pronghorn_metro()) ++ pci_common_init(&pronghornmetro_pci); ++ return 0; ++} ++ ++subsys_initcall(pronghornmetro_pci_init); +Index: linux-2.6.23.12/arch/arm/mach-ixp4xx/pronghornmetro-setup.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12/arch/arm/mach-ixp4xx/pronghornmetro-setup.c 2008-01-05 13:37:05.000000000 +1030 +@@ -0,0 +1,147 @@ ++/* ++ * arch/arm/mach-ixp4xx/pronghornmetro-setup.c ++ * ++ * Board setup for the ADI Engineering Pronghorn Metro ++ * ++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org> ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz <Kaloz@openwrt.org> ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/device.h> ++#include <linux/serial.h> ++#include <linux/tty.h> ++#include <linux/serial_8250.h> ++#include <linux/slab.h> ++ ++#include <asm/types.h> ++#include <asm/setup.h> ++#include <asm/memory.h> ++#include <asm/hardware.h> ++#include <asm/irq.h> ++#include <asm/mach-types.h> ++#include <asm/mach/arch.h> ++#include <asm/mach/flash.h> ++ ++static struct flash_platform_data pronghornmetro_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource pronghornmetro_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device pronghornmetro_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &pronghornmetro_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &pronghornmetro_flash_resource, ++}; ++ ++static struct resource pronghornmetro_uart_resource = { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port pronghornmetro_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device pronghornmetro_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = pronghornmetro_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &pronghornmetro_uart_resource, ++}; ++ ++static struct resource pronghornmetro_pata_resources[] = { ++ { ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "intrq", ++ .start = IRQ_IXP4XX_GPIO0, ++ .end = IRQ_IXP4XX_GPIO0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct ixp4xx_pata_data pronghornmetro_pata_data = { ++ .cs0_bits = 0xbfff0043, ++ .cs1_bits = 0xbfff0043, ++}; ++ ++static struct platform_device pronghornmetro_pata = { ++ .name = "pata_ixp4xx_cf", ++ .id = 0, ++ .dev.platform_data = &pronghornmetro_pata_data, ++ .num_resources = ARRAY_SIZE(pronghornmetro_pata_resources), ++ .resource = pronghornmetro_pata_resources, ++}; ++ ++static struct platform_device *pronghornmetro_devices[] __initdata = { ++ &pronghornmetro_flash, ++ &pronghornmetro_uart, ++}; ++ ++static void __init pronghornmetro_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ pronghornmetro_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ pronghornmetro_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_16M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(pronghornmetro_devices, ARRAY_SIZE(pronghornmetro_devices)); ++ ++ pronghornmetro_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1); ++ pronghornmetro_pata_resources[0].end = IXP4XX_EXP_BUS_END(1); ++ ++ pronghornmetro_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2); ++ pronghornmetro_pata_resources[1].end = IXP4XX_EXP_BUS_END(2); ++ ++ pronghornmetro_pata_data.cs0_cfg = IXP4XX_EXP_CS1; ++ pronghornmetro_pata_data.cs1_cfg = IXP4XX_EXP_CS2; ++ ++ platform_device_register(&pronghornmetro_pata); ++} ++ ++#ifdef CONFIG_MACH_PRONGHORNMETRO ++MACHINE_START(PRONGHORNMETRO, "ADI Engineering Pronghorn Metro") ++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ ++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, ++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .timer = &ixp4xx_timer, ++ .boot_params = 0x0100, ++ .init_machine = pronghornmetro_init, ++MACHINE_END ++#endif +Index: linux-2.6.23.12/Documentation/arm/IXP4xx +=================================================================== +--- linux-2.6.23.12.orig/Documentation/arm/IXP4xx 2008-01-05 13:30:14.000000000 +1030 ++++ linux-2.6.23.12/Documentation/arm/IXP4xx 2008-01-05 13:37:05.000000000 +1030 +@@ -111,6 +111,9 @@ + the platform has two mini-PCI slots used for 802.11[bga] cards. + Finally, there is an IDE port hanging off the expansion bus. + ++ADI Engineering Pronghorn Metro Platform ++http://www.adiengineering.com/php-bin/ecomm4/productDisplay.php?category_id=30&product_id=85 ++ + Gateworks Avila Network Platform + http://www.gateworks.com/avila_sbc.htm + +Index: linux-2.6.23.12/include/asm-arm/arch-ixp4xx/uncompress.h +=================================================================== +--- linux-2.6.23.12.orig/include/asm-arm/arch-ixp4xx/uncompress.h 2008-01-05 13:30:14.000000000 +1030 ++++ linux-2.6.23.12/include/asm-arm/arch-ixp4xx/uncompress.h 2008-01-05 13:37:05.000000000 +1030 +@@ -41,7 +41,8 @@ + * Some boards are using UART2 as console + */ + if (machine_is_adi_coyote() || machine_is_gtwx5715() || +- machine_is_gateway7001() || machine_is_wg302v2()) ++ machine_is_gateway7001() || machine_is_wg302v2() || ++ machine_is_pronghorn_metro()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; diff --git a/target/linux/ixp4xx/patches-2.6.24/111-pronghorn_metro_mac_plat_info.patch b/target/linux/ixp4xx/patches-2.6.24/111-pronghorn_metro_mac_plat_info.patch new file mode 100644 index 0000000000..2fb376982a --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/111-pronghorn_metro_mac_plat_info.patch @@ -0,0 +1,40 @@ +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/pronghornmetro-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/pronghornmetro-setup.c 2007-10-22 15:41:27.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c 2007-10-22 15:43:30.000000000 +0200 +@@ -104,9 +104,36 @@ + .resource = pronghornmetro_pata_resources, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info pronghornmetro_plat_eth[] = { ++ { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device pronghornmetro_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = pronghornmetro_plat_eth, ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = pronghornmetro_plat_eth + 1, ++ } ++}; ++ + static struct platform_device *pronghornmetro_devices[] __initdata = { + &pronghornmetro_flash, + &pronghornmetro_uart, ++ &pronghornmetro_eth[0], ++ &pronghornmetro_eth[1], + }; + + static void __init pronghornmetro_init(void) diff --git a/target/linux/ixp4xx/patches-2.6.24/120-compex_support.patch b/target/linux/ixp4xx/patches-2.6.24/120-compex_support.patch new file mode 100644 index 0000000000..2488cb49d8 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/120-compex_support.patch @@ -0,0 +1,185 @@ +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig +--- linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 18:03:34.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 18:22:41.000000000 +0200 +@@ -65,6 +65,14 @@ + Engineering Pronghorn Metro Platform. For more + information on this platform, see <file:Documentation/arm/IXP4xx>. + ++config MACH_COMPEX ++ bool "Compex WP18 / NP18A" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Compex' ++ WP18 or NP18A boards. For more information on this ++ platform, see http://openwrt.org ++ + config ARCH_IXDP425 + bool "IXDP425" + help +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Makefile linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile +--- linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-23 18:03:34.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile 2007-10-23 18:22:41.000000000 +0200 +@@ -17,6 +17,7 @@ + obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-pci.o ++obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o + + obj-y += common.o + +@@ -32,6 +33,7 @@ + obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o + obj-$(CONFIG_MACH_FSG) += fsg-setup.o + obj-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-setup.o ++obj-$(CONFIG_MACH_COMPEX) += compex-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/compex-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/compex-setup.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/compex-setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/compex-setup.c 2007-10-23 18:22:41.000000000 +0200 +@@ -0,0 +1,120 @@ ++/* ++ * arch/arm/mach-ixp4xx/compex-setup.c ++ * ++ * Ccompex WP18 / NP18A board-setup ++ * ++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org> ++ * ++ * based on ixdp425-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz <Kaloz@openwrt.org> ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/device.h> ++#include <linux/serial.h> ++#include <linux/tty.h> ++#include <linux/serial_8250.h> ++#include <linux/slab.h> ++ ++#include <asm/types.h> ++#include <asm/setup.h> ++#include <asm/memory.h> ++#include <asm/hardware.h> ++#include <asm/mach-types.h> ++#include <asm/irq.h> ++#include <asm/mach/arch.h> ++#include <asm/mach/flash.h> ++ ++static struct flash_platform_data compex_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource compex_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device compex_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &compex_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &compex_flash_resource, ++}; ++ ++static struct resource compex_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port compex_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device compex_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = compex_uart_data, ++ .num_resources = 2, ++ .resource = compex_uart_resources, ++}; ++ ++static struct platform_device *compex_devices[] __initdata = { ++ &compex_flash, ++ &compex_uart ++}; ++ ++static void __init compex_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ compex_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ compex_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ platform_add_devices(compex_devices, ARRAY_SIZE(compex_devices)); ++} ++ ++#ifdef CONFIG_MACH_COMPEX ++MACHINE_START(COMPEX, "Compex WP18 / NP18A") ++ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */ ++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, ++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .timer = &ixp4xx_timer, ++ .boot_params = 0x0100, ++ .init_machine = compex_init, ++MACHINE_END ++#endif +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-pci.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-pci.c 2007-10-09 22:31:38.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c 2007-10-23 18:22:41.000000000 +0200 +@@ -66,7 +66,7 @@ + int __init ixdp425_pci_init(void) + { + if (machine_is_ixdp425() || machine_is_ixcdp1100() || +- machine_is_ixdp465() || machine_is_kixrp435()) ++ machine_is_ixdp465() || machine_is_kixrp435() || machine_is_compex()) + pci_common_init(&ixdp425_pci); + return 0; + } +diff -Nur linux-2.6.23/arch/arm/tools/mach-types linux-2.6.23-owrt/arch/arm/tools/mach-types +--- linux-2.6.23/arch/arm/tools/mach-types 2007-10-09 22:31:38.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/tools/mach-types 2007-10-23 18:22:41.000000000 +0200 +@@ -1278,7 +1278,7 @@ + smdk6400 MACH_SMDK6400 SMDK6400 1270 + nokia_n800 MACH_NOKIA_N800 NOKIA_N800 1271 + greenphone MACH_GREENPHONE GREENPHONE 1272 +-compex42x MACH_COMPEXWP18 COMPEXWP18 1273 ++compex MACH_COMPEX COMPEX 1273 + xmate MACH_XMATE XMATE 1274 + energizer MACH_ENERGIZER ENERGIZER 1275 + ime1 MACH_IME1 IME1 1276 diff --git a/target/linux/ixp4xx/patches-2.6.24/121-compex_mac_plat_info.patch b/target/linux/ixp4xx/patches-2.6.24/121-compex_mac_plat_info.patch new file mode 100644 index 0000000000..081349ad3d --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/121-compex_mac_plat_info.patch @@ -0,0 +1,41 @@ +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/compex-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/compex-setup.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/compex-setup.c 2007-10-23 18:39:29.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/compex-setup.c 2007-10-23 18:45:34.000000000 +0200 +@@ -90,9 +90,36 @@ + .resource = compex_uart_resources, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info compex_plat_eth[] = { ++ { ++ .phy = -1, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 3, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device compex_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = compex_plat_eth, ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = compex_plat_eth + 1, ++ } ++}; ++ + static struct platform_device *compex_devices[] __initdata = { + &compex_flash, +- &compex_uart ++ &compex_uart, ++ &compex_eth[0], ++ &compex_eth[1], + }; + + static void __init compex_init(void) diff --git a/target/linux/ixp4xx/patches-2.6.24/130-wrt300nv2_support.patch b/target/linux/ixp4xx/patches-2.6.24/130-wrt300nv2_support.patch new file mode 100644 index 0000000000..78e525d309 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/130-wrt300nv2_support.patch @@ -0,0 +1,230 @@ +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig +--- linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 18:39:29.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 19:11:31.000000000 +0200 +@@ -73,6 +73,14 @@ + WP18 or NP18A boards. For more information on this + platform, see http://openwrt.org + ++config MACH_WRT300NV2 ++ bool "Linksys WRT300N v2" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Linksys' ++ WRT300N v2 router. For more information on this ++ platform, see http://openwrt.org ++ + config ARCH_IXDP425 + bool "IXDP425" + help +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Makefile linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile +--- linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-23 18:39:29.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile 2007-10-23 19:11:31.000000000 +0200 +@@ -18,6 +18,7 @@ + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-pci.o + obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o ++obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + + obj-y += common.o + +@@ -34,6 +35,7 @@ + obj-$(CONFIG_MACH_FSG) += fsg-setup.o + obj-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-setup.o + obj-$(CONFIG_MACH_COMPEX) += compex-setup.o ++obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-pci.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-pci.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-pci.c 2007-10-23 19:11:31.000000000 +0200 +@@ -0,0 +1,65 @@ ++/* ++ * arch/arch/mach-ixp4xx/wrt300nv2-pci.c ++ * ++ * PCI setup routines for Linksys WRT300N v2 ++ * ++ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org> ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz <kaloz@openwrt.org> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/pci.h> ++#include <linux/init.h> ++#include <linux/irq.h> ++ ++#include <asm/mach-types.h> ++#include <asm/hardware.h> ++#include <asm/irq.h> ++ ++#include <asm/mach/pci.h> ++ ++extern void ixp4xx_pci_preinit(void); ++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); ++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); ++ ++void __init wrt300nv2_pci_preinit(void) ++{ ++ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init wrt300nv2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO8; ++ else return -1; ++} ++ ++struct hw_pci wrt300nv2_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = wrt300nv2_pci_preinit, ++ .swizzle = pci_std_swizzle, ++ .setup = ixp4xx_setup, ++ .scan = ixp4xx_scan_bus, ++ .map_irq = wrt300nv2_map_irq, ++}; ++ ++int __init wrt300nv2_pci_init(void) ++{ ++ if (machine_is_wrt300nv2()) ++ pci_common_init(&wrt300nv2_pci); ++ return 0; ++} ++ ++subsys_initcall(wrt300nv2_pci_init); +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c 2007-10-23 19:11:31.000000000 +0200 +@@ -0,0 +1,108 @@ ++/* ++ * arch/arm/mach-ixp4xx/wrt300nv2-setup.c ++ * ++ * Board setup for the Linksys WRT300N v2 ++ * ++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org> ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz <Kaloz@openwrt.org> ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/device.h> ++#include <linux/serial.h> ++#include <linux/tty.h> ++#include <linux/serial_8250.h> ++#include <linux/slab.h> ++ ++#include <asm/types.h> ++#include <asm/setup.h> ++#include <asm/memory.h> ++#include <asm/hardware.h> ++#include <asm/irq.h> ++#include <asm/mach-types.h> ++#include <asm/mach/arch.h> ++#include <asm/mach/flash.h> ++ ++static struct flash_platform_data wrt300nv2_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource wrt300nv2_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device wrt300nv2_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &wrt300nv2_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &wrt300nv2_flash_resource, ++}; ++ ++static struct resource wrt300nv2_uart_resource = { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port wrt300nv2_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device wrt300nv2_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = wrt300nv2_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &wrt300nv2_uart_resource, ++}; ++ ++static struct platform_device *wrt300nv2_devices[] __initdata = { ++ &wrt300nv2_flash, ++ &wrt300nv2_uart ++}; ++ ++static void __init wrt300nv2_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ wrt300nv2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices)); ++} ++ ++#ifdef CONFIG_MACH_WRT300NV2 ++MACHINE_START(WRT300NV2, "Linksys WRT300N v2") ++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ ++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, ++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .timer = &ixp4xx_timer, ++ .boot_params = 0x0100, ++ .init_machine = wrt300nv2_init, ++MACHINE_END ++#endif +diff -Nur linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h linux-2.6.23-owrt/include/asm-arm/arch-ixp4xx/uncompress.h +--- linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-23 18:03:35.000000000 +0200 ++++ linux-2.6.23-owrt/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-23 19:12:30.000000000 +0200 +@@ -42,7 +42,7 @@ + */ + if (machine_is_adi_coyote() || machine_is_gtwx5715() || + machine_is_gateway7001() || machine_is_wg302v2() || +- machine_is_pronghorn_metro()) ++ machine_is_pronghorn_metro() || machine_is_wrt300nv2()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; diff --git a/target/linux/ixp4xx/patches-2.6.24/131-wrt300nv2_mac_plat_info.patch b/target/linux/ixp4xx/patches-2.6.24/131-wrt300nv2_mac_plat_info.patch new file mode 100644 index 0000000000..24dad0aea9 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/131-wrt300nv2_mac_plat_info.patch @@ -0,0 +1,41 @@ +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-setup.c 2007-10-23 19:20:08.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c 2007-10-23 19:22:19.000000000 +0200 +@@ -76,9 +76,36 @@ + .resource = &wrt300nv2_uart_resource, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info wrt300nv2_plat_eth[] = { ++ { ++ .phy = -1, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device wrt300nv2_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = wrt300nv2_plat_eth, ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = wrt300nv2_plat_eth + 1, ++ } ++}; ++ + static struct platform_device *wrt300nv2_devices[] __initdata = { + &wrt300nv2_flash, +- &wrt300nv2_uart ++ &wrt300nv2_uart, ++ &wrt300nv2_eth[0], ++ &wrt300nv2_eth[1], + }; + + static void __init wrt300nv2_init(void) diff --git a/target/linux/ixp4xx/patches-2.6.24/140-sidewinder_support.patch b/target/linux/ixp4xx/patches-2.6.24/140-sidewinder_support.patch new file mode 100644 index 0000000000..48d567f6f4 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/140-sidewinder_support.patch @@ -0,0 +1,240 @@ +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig +--- linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 19:20:08.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 19:26:46.000000000 +0200 +@@ -65,6 +65,14 @@ + Engineering Pronghorn Metro Platform. For more + information on this platform, see <file:Documentation/arm/IXP4xx>. + ++config MACH_SIDEWINDER ++ bool "Sidewinder" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the ADI ++ Engineering Sidewinder Platform. For more ++ information on this platform, see <file:Documentation/arm/IXP4xx>. ++ + config MACH_COMPEX + bool "Compex WP18 / NP18A" + select PCI +@@ -163,7 +171,7 @@ + # + config CPU_IXP46X + bool +- depends on MACH_IXDP465 ++ depends on MACH_IXDP465 || MACH_SIDEWINDER + default y + + config CPU_IXP43X +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Makefile linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile +--- linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-23 19:20:08.000000000 +0200 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile 2007-10-23 19:23:52.000000000 +0200 +@@ -19,6 +19,7 @@ + obj-pci-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-pci.o + obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o ++obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o + + obj-y += common.o + +@@ -36,6 +37,7 @@ + obj-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-setup.o + obj-$(CONFIG_MACH_COMPEX) += compex-setup.o + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o ++obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/sidewinder-pci.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/sidewinder-pci.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/sidewinder-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/sidewinder-pci.c 2007-10-23 19:23:52.000000000 +0200 +@@ -0,0 +1,71 @@ ++/* ++ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c ++ * ++ * PCI setup routines for ADI Engineering Sidewinder ++ * ++ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org> ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz <kaloz@openwrt.org> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/pci.h> ++#include <linux/init.h> ++#include <linux/irq.h> ++ ++#include <asm/mach-types.h> ++#include <asm/hardware.h> ++#include <asm/irq.h> ++ ++#include <asm/mach/pci.h> ++ ++extern void ixp4xx_pci_preinit(void); ++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); ++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); ++ ++void __init sidewinder_pci_preinit(void) ++{ ++ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW); ++ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW); ++ set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init sidewinder_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else if (slot == 3) ++ return IRQ_IXP4XX_GPIO9; ++ else return -1; ++} ++ ++struct hw_pci sidewinder_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = sidewinder_pci_preinit, ++ .swizzle = pci_std_swizzle, ++ .setup = ixp4xx_setup, ++ .scan = ixp4xx_scan_bus, ++ .map_irq = sidewinder_map_irq, ++}; ++ ++int __init sidewinder_pci_init(void) ++{ ++ if (machine_is_sidewinder()) ++ pci_common_init(&sidewinder_pci); ++ return 0; ++} ++ ++subsys_initcall(sidewinder_pci_init); +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/sidewinder-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/sidewinder-setup.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/sidewinder-setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/sidewinder-setup.c 2007-10-23 19:23:52.000000000 +0200 +@@ -0,0 +1,115 @@ ++/* ++ * arch/arm/mach-ixp4xx/sidewinder-setup.c ++ * ++ * Board setup for the ADI Engineering Sidewinder ++ * ++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org> ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz <Kaloz@openwrt.org> ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/serial.h> ++#include <linux/serial_8250.h> ++ ++#include <asm/mach-types.h> ++#include <asm/mach/arch.h> ++#include <asm/mach/flash.h> ++ ++static struct flash_platform_data sidewinder_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource sidewinder_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device sidewinder_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &sidewinder_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &sidewinder_flash_resource, ++}; ++ ++static struct resource sidewinder_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct plat_serial8250_port sidewinder_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device sidewinder_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = sidewinder_uart_data, ++ }, ++ .num_resources = 2, ++ .resource = &sidewinder_uart_resources, ++}; ++ ++static struct platform_device *sidewinder_devices[] __initdata = { ++ &sidewinder_flash, ++ &sidewinder_uart, ++}; ++ ++static void __init sidewinder_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ sidewinder_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ sidewinder_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_64M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(sidewinder_devices, ARRAY_SIZE(sidewinder_devices)); ++} ++ ++#ifdef CONFIG_MACH_SIDEWINDER ++MACHINE_START(SIDEWINDER, "ADI Engineering Sidewinder") ++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ ++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, ++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .timer = &ixp4xx_timer, ++ .boot_params = 0x0100, ++ .init_machine = sidewinder_init, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-2.6.24/150-lanready_ap1000_support.patch b/target/linux/ixp4xx/patches-2.6.24/150-lanready_ap1000_support.patch new file mode 100644 index 0000000000..4070da1d04 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/150-lanready_ap1000_support.patch @@ -0,0 +1,212 @@ +diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c +--- linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c 2007-11-14 13:58:58.000000000 +0100 +@@ -0,0 +1,151 @@ ++/* ++ * arch/arm/mach-ixp4xx/ap1000-setup.c ++ * ++ * Lanready AP-1000 ++ * ++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org> ++ * ++ * based on ixdp425-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz <Kaloz@openwrt.org> ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/device.h> ++#include <linux/serial.h> ++#include <linux/tty.h> ++#include <linux/serial_8250.h> ++#include <linux/slab.h> ++ ++#include <asm/types.h> ++#include <asm/setup.h> ++#include <asm/memory.h> ++#include <asm/hardware.h> ++#include <asm/mach-types.h> ++#include <asm/irq.h> ++#include <asm/mach/arch.h> ++#include <asm/mach/flash.h> ++ ++static struct flash_platform_data ap1000_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource ap1000_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device ap1000_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &ap1000_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &ap1000_flash_resource, ++}; ++ ++static struct resource ap1000_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port ap1000_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device ap1000_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = ap1000_uart_data, ++ .num_resources = 2, ++ .resource = ap1000_uart_resources ++}; ++ ++static struct platform_device *ap1000_devices[] __initdata = { ++ &ap1000_flash, ++ &ap1000_uart ++}; ++ ++static char ap1000_mem_fixup[] __initdata = "mem=64M "; ++ ++static void __init ap1000_fixup(struct machine_desc *desc, ++ struct tag *tags, char **cmdline, struct meminfo *mi) ++ ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(ap1000_mem_fixup) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, ap1000_mem_fixup, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(ap1000_mem_fixup), p, ++ COMMAND_LINE_SIZE - strlen(ap1000_mem_fixup)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ ++static void __init ap1000_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ ap1000_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ ap1000_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; ++ ++ platform_add_devices(ap1000_devices, ARRAY_SIZE(ap1000_devices)); ++} ++ ++#ifdef CONFIG_MACH_AP1000 ++MACHINE_START(AP1000, "Lanready AP-1000") ++ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */ ++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, ++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .fixup = ap1000_fixup, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .timer = &ixp4xx_timer, ++ .boot_params = 0x0100, ++ .init_machine = ap1000_init, ++MACHINE_END ++#endif +diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/ixdp425-pci.c linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c +--- linux-2.6.23.1/arch/arm/mach-ixp4xx/ixdp425-pci.c 2007-11-14 13:15:50.000000000 +0100 ++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c 2007-11-14 13:27:16.000000000 +0100 +@@ -66,7 +66,8 @@ + int __init ixdp425_pci_init(void) + { + if (machine_is_ixdp425() || machine_is_ixcdp1100() || +- machine_is_ixdp465() || machine_is_kixrp435() || machine_is_compex()) ++ machine_is_ixdp465() || machine_is_kixrp435() || ++ machine_is_compex() || machine_is_ap1000()) + pci_common_init(&ixdp425_pci); + return 0; + } +diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/Kconfig +--- linux-2.6.23.1/arch/arm/mach-ixp4xx/Kconfig 2007-11-14 13:15:50.000000000 +0100 ++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/Kconfig 2007-11-14 13:25:07.000000000 +0100 +@@ -89,6 +89,14 @@ + WRT300N v2 router. For more information on this + platform, see http://openwrt.org + ++config MACH_AP1000 ++ bool "Lanready AP-1000" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Lanready's ++ AP1000 board. For more information on this ++ platform, see http://openwrt.org ++ + config ARCH_IXDP425 + bool "IXDP425" + help +diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/Makefile linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/Makefile +--- linux-2.6.23.1/arch/arm/mach-ixp4xx/Makefile 2007-11-14 13:15:50.000000000 +0100 ++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/Makefile 2007-11-14 13:31:29.000000000 +0100 +@@ -20,6 +20,7 @@ + obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o ++obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o + + obj-y += common.o + +@@ -38,5 +39,6 @@ + obj-$(CONFIG_MACH_COMPEX) += compex-setup.o + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o ++obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o +diff -Nur linux-2.6.23.1/arch/arm/tools/mach-types linux-2.6.23.1-owrt/arch/arm/tools/mach-types +--- linux-2.6.23.1/arch/arm/tools/mach-types 2007-11-14 13:15:50.000000000 +0100 ++++ linux-2.6.23.1-owrt/arch/arm/tools/mach-types 2007-11-14 13:26:06.000000000 +0100 +@@ -1367,3 +1367,4 @@ + csb726 MACH_CSB726 CSB726 1359 + tik27 MACH_TIK27 TIK27 1360 + mx_uc7420 MACH_MX_UC7420 MX_UC7420 1361 ++ap1000 MACH_AP1000 AP1000 1543 diff --git a/target/linux/ixp4xx/patches-2.6.24/151-lanready_ap1000_mac_plat_info.patch b/target/linux/ixp4xx/patches-2.6.24/151-lanready_ap1000_mac_plat_info.patch new file mode 100644 index 0000000000..4259ff971b --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/151-lanready_ap1000_mac_plat_info.patch @@ -0,0 +1,41 @@ +diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c +--- linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c 2007-11-14 14:11:10.000000000 +0100 ++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c 2007-11-14 14:09:30.000000000 +0100 +@@ -90,9 +90,36 @@ + .resource = ap1000_uart_resources + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info ap1000_plat_eth[] = { ++ { ++ .phy = 4, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 5, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device ap1000_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = ap1000_plat_eth, ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = ap1000_plat_eth + 1, ++ } ++}; ++ + static struct platform_device *ap1000_devices[] __initdata = { + &ap1000_flash, +- &ap1000_uart ++ &ap1000_uart, ++ &ap1000_eth[0], ++ &ap1000_eth[1], + }; + + static char ap1000_mem_fixup[] __initdata = "mem=64M "; diff --git a/target/linux/ixp4xx/patches-2.6.24/160-wg302v1_support.patch b/target/linux/ixp4xx/patches-2.6.24/160-wg302v1_support.patch new file mode 100644 index 0000000000..129e5ca8e1 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/160-wg302v1_support.patch @@ -0,0 +1,217 @@ +diff -Nur linux-2.6.23.12/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/Kconfig +--- linux-2.6.23.12/arch/arm/mach-ixp4xx/Kconfig 2008-01-14 22:08:42.000000000 +0100 ++++ linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/Kconfig 2008-01-14 22:12:21.000000000 +0100 +@@ -49,6 +49,14 @@ + 7001 Access Point. For more information on this platform, + see http://openwrt.org + ++config MACH_WG302V1 ++ bool "Netgear WG302 v1 / WAG302 v1" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Netgear's ++ WG302 v1 or WAG302 v1 Access Points. For more information ++ on this platform, see http://openwrt.org ++ + config MACH_WG302V2 + bool "Netgear WG302 v2 / WAG302 v2" + select PCI +diff -Nur linux-2.6.23.12/arch/arm/mach-ixp4xx/Makefile linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/Makefile +--- linux-2.6.23.12/arch/arm/mach-ixp4xx/Makefile 2008-01-14 22:08:42.000000000 +0100 ++++ linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/Makefile 2008-01-14 22:11:47.000000000 +0100 +@@ -14,6 +14,7 @@ + obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o + obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o + obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o ++obj-pci-$(CONFIG_MACH_WG302V1) += wg302v1-pci.o + obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-pci.o +@@ -33,6 +34,7 @@ + obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o nas100d-power.o + obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o dsmg600-power.o + obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o ++obj-$(CONFIG_MACH_WG302V1) += wg302v1-setup.o + obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o + obj-$(CONFIG_MACH_FSG) += fsg-setup.o fsg-power.o + obj-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-setup.o +diff -Nur linux-2.6.23.12/arch/arm/mach-ixp4xx/wg302v1-pci.c linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/wg302v1-pci.c +--- linux-2.6.23.12/arch/arm/mach-ixp4xx/wg302v1-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/wg302v1-pci.c 2008-01-14 22:33:52.000000000 +0100 +@@ -0,0 +1,63 @@ ++/* ++ * arch/arch/mach-ixp4xx/wg302v1-pci.c ++ * ++ * PCI setup routines for the Netgear WG302 v1 and WAG302 v1 ++ * ++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Software, Inc. ++ * ++ * Maintainer: Imre Kaloz <kaloz@openwrt.org> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/pci.h> ++#include <linux/init.h> ++#include <linux/irq.h> ++ ++#include <asm/mach-types.h> ++#include <asm/hardware.h> ++ ++#include <asm/mach/pci.h> ++ ++void __init wg302v1_pci_preinit(void) ++{ ++ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW); ++ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init wg302v1_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO8; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else return -1; ++} ++ ++struct hw_pci wg302v1_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = wg302v1_pci_preinit, ++ .swizzle = pci_std_swizzle, ++ .setup = ixp4xx_setup, ++ .scan = ixp4xx_scan_bus, ++ .map_irq = wg302v1_map_irq, ++}; ++ ++int __init wg302v1_pci_init(void) ++{ ++ if (machine_is_wg302v1()) ++ pci_common_init(&wg302v1_pci); ++ return 0; ++} ++ ++subsys_initcall(wg302v1_pci_init); +diff -Nur linux-2.6.23.12/arch/arm/mach-ixp4xx/wg302v1-setup.c linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/wg302v1-setup.c +--- linux-2.6.23.12/arch/arm/mach-ixp4xx/wg302v1-setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/wg302v1-setup.c 2008-01-14 23:04:01.000000000 +0100 +@@ -0,0 +1,109 @@ ++/* ++ * arch/arm/mach-ixp4xx/wg302v1-setup.c ++ * ++ * Board setup for the Netgear WG302 v1 and WAG302 v1 ++ * ++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz <kaloz@openwrt.org> ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/device.h> ++#include <linux/serial.h> ++#include <linux/tty.h> ++#include <linux/serial_8250.h> ++#include <linux/slab.h> ++ ++#include <asm/types.h> ++#include <asm/setup.h> ++#include <asm/memory.h> ++#include <asm/hardware.h> ++#include <asm/irq.h> ++#include <asm/mach-types.h> ++#include <asm/mach/arch.h> ++#include <asm/mach/flash.h> ++ ++static struct flash_platform_data wg302v1_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource wg302v1_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device wg302v1_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &wg302v1_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &wg302v1_flash_resource, ++}; ++ ++static struct resource wg302v1_uart_resource = { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port wg302v1_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device wg302v1_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = wg302v1_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &wg302v1_uart_resource, ++}; ++ ++static struct platform_device *wg302v1_devices[] __initdata = { ++ &wg302v1_flash, ++ &wg302v1_uart, ++}; ++ ++static void __init wg302v1_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ wg302v1_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ wg302v1_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(wg302v1_devices, ARRAY_SIZE(wg302v1_devices)); ++} ++ ++#ifdef CONFIG_MACH_WG302V1 ++MACHINE_START(WG302V1, "Netgear WG302 v1 / WAG302 v1") ++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ ++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, ++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .timer = &ixp4xx_timer, ++ .boot_params = 0x0100, ++ .init_machine = wg302v1_init, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-2.6.24/161-wg302v1_mac_plat_info.patch b/target/linux/ixp4xx/patches-2.6.24/161-wg302v1_mac_plat_info.patch new file mode 100644 index 0000000000..250d85e6d9 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/161-wg302v1_mac_plat_info.patch @@ -0,0 +1,31 @@ +diff -Nur linux-2.6.23.12/arch/arm/mach-ixp4xx/wg302v1-setup.c linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/wg302v1-setup.c +--- linux-2.6.23.12/arch/arm/mach-ixp4xx/wg302v1-setup.c 2008-01-14 23:06:42.000000000 +0100 ++++ linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/wg302v1-setup.c 2008-01-14 23:03:16.000000000 +0100 +@@ -77,9 +77,27 @@ + .resource = &wg302v1_uart_resource, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info wg302_plat_eth[] = { ++ { ++ .phy = 30, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device wg302_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = wg302_plat_eth, ++ } ++}; ++ + static struct platform_device *wg302v1_devices[] __initdata = { + &wg302v1_flash, + &wg302v1_uart, ++ &wg302_eth[0], + }; + + static void __init wg302v1_init(void) diff --git a/target/linux/ixp4xx/patches-2.6.24/162-wg302v1_mem_fixup.patch b/target/linux/ixp4xx/patches-2.6.24/162-wg302v1_mem_fixup.patch new file mode 100644 index 0000000000..b370088aec --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/162-wg302v1_mem_fixup.patch @@ -0,0 +1,48 @@ +diff -Nur linux-2.6.23.12/arch/arm/mach-ixp4xx/wg302v1-setup.c linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/wg302v1-setup.c +--- linux-2.6.23.12/arch/arm/mach-ixp4xx/wg302v1-setup.c 2008-01-14 23:12:03.000000000 +0100 ++++ linux-2.6.23.12-owrt/arch/arm/mach-ixp4xx/wg302v1-setup.c 2008-01-14 23:11:34.000000000 +0100 +@@ -100,6 +100,36 @@ + &wg302_eth[0], + }; + ++static char wg302v1_mem_fixup[] __initdata = "mem=32M "; ++ ++static void __init wg302v1_fixup(struct machine_desc *desc, ++ struct tag *tags, char **cmdline, struct meminfo *mi) ++ ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(wg302v1_mem_fixup) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, wg302v1_mem_fixup, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(wg302v1_mem_fixup), p, ++ COMMAND_LINE_SIZE - strlen(wg302v1_mem_fixup)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ + static void __init wg302v1_init(void) + { + ixp4xx_sys_init(); +@@ -118,6 +148,7 @@ + /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .fixup = wg302v1_fixup, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, diff --git a/target/linux/ixp4xx/patches-2.6.24/200-npe_driver.patch b/target/linux/ixp4xx/patches-2.6.24/200-npe_driver.patch new file mode 100644 index 0000000000..8be7af7b54 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/200-npe_driver.patch @@ -0,0 +1,4050 @@ +diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c +index 4de432e..c4c810b 100644 +--- a/arch/arm/kernel/setup.c ++++ b/arch/arm/kernel/setup.c +@@ -61,6 +61,7 @@ extern int root_mountflags; + extern void _stext, _text, _etext, __data_start, _edata, _end; + + unsigned int processor_id; ++EXPORT_SYMBOL(processor_id); + unsigned int __machine_arch_type; + EXPORT_SYMBOL(__machine_arch_type); + +diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig +index 61b2dfc..e774447 100644 +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -189,6 +189,20 @@ config IXP4XX_INDIRECT_PCI + need to use the indirect method instead. If you don't know + what you need, leave this option unselected. + ++config IXP4XX_QMGR ++ tristate "IXP4xx Queue Manager support" ++ help ++ This driver supports IXP4xx built-in hardware queue manager ++ and is automatically selected by Ethernet and HSS drivers. ++ ++config IXP4XX_NPE ++ tristate "IXP4xx Network Processor Engine support" ++ select HOTPLUG ++ select FW_LOADER ++ help ++ This driver supports IXP4xx built-in network coprocessors ++ and is automatically selected by Ethernet and HSS drivers. ++ + endmenu + + endif +diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile +index 77e00ad..4bb97e1 100644 +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -30,3 +30,5 @@ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o + obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o ++obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o ++obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o +diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c +index d5008d8..10b41c6 100644 +--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c ++++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c +@@ -177,6 +177,31 @@ static struct platform_device ixdp425_uart = { + .resource = ixdp425_uart_resources + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info ixdp425_plat_eth[] = { ++ { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device ixdp425_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = ixdp425_plat_eth, ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = ixdp425_plat_eth + 1, ++ } ++}; ++ + static struct platform_device *ixdp425_devices[] __initdata = { + &ixdp425_i2c_controller, + &ixdp425_flash, +@@ -184,7 +209,9 @@ static struct platform_device *ixdp425_devices[] __initdata = { + defined(CONFIG_MTD_NAND_PLATFORM_MODULE) + &ixdp425_flash_nand, + #endif +- &ixdp425_uart ++ &ixdp425_uart, ++ &ixdp425_eth[0], ++ &ixdp425_eth[1], + }; + + static void __init ixdp425_init(void) +diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c +new file mode 100644 +index 0000000..83c137e +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c +@@ -0,0 +1,741 @@ ++/* ++ * Intel IXP4xx Network Processor Engine driver for Linux ++ * ++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License ++ * as published by the Free Software Foundation. ++ * ++ * The code is based on publicly available information: ++ * - Intel IXP4xx Developer's Manual and other e-papers ++ * - Intel IXP400 Access Library Software (BSD license) ++ * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com> ++ * Thanks, Christian. ++ */ ++ ++#include <linux/delay.h> ++#include <linux/dma-mapping.h> ++#include <linux/firmware.h> ++#include <linux/io.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/slab.h> ++#include <asm/arch/npe.h> ++ ++#define DEBUG_MSG 0 ++#define DEBUG_FW 0 ++ ++#define NPE_COUNT 3 ++#define MAX_RETRIES 1000 /* microseconds */ ++#define NPE_42X_DATA_SIZE 0x800 /* in dwords */ ++#define NPE_46X_DATA_SIZE 0x1000 ++#define NPE_A_42X_INSTR_SIZE 0x1000 ++#define NPE_B_AND_C_42X_INSTR_SIZE 0x800 ++#define NPE_46X_INSTR_SIZE 0x1000 ++#define REGS_SIZE 0x1000 ++ ++#define NPE_PHYS_REG 32 ++ ++#define FW_MAGIC 0xFEEDF00D ++#define FW_BLOCK_TYPE_INSTR 0x0 ++#define FW_BLOCK_TYPE_DATA 0x1 ++#define FW_BLOCK_TYPE_EOF 0xF ++ ++/* NPE exec status (read) and command (write) */ ++#define CMD_NPE_STEP 0x01 ++#define CMD_NPE_START 0x02 ++#define CMD_NPE_STOP 0x03 ++#define CMD_NPE_CLR_PIPE 0x04 ++#define CMD_CLR_PROFILE_CNT 0x0C ++#define CMD_RD_INS_MEM 0x10 /* instruction memory */ ++#define CMD_WR_INS_MEM 0x11 ++#define CMD_RD_DATA_MEM 0x12 /* data memory */ ++#define CMD_WR_DATA_MEM 0x13 ++#define CMD_RD_ECS_REG 0x14 /* exec access register */ ++#define CMD_WR_ECS_REG 0x15 ++ ++#define STAT_RUN 0x80000000 ++#define STAT_STOP 0x40000000 ++#define STAT_CLEAR 0x20000000 ++#define STAT_ECS_K 0x00800000 /* pipeline clean */ ++ ++#define NPE_STEVT 0x1B ++#define NPE_STARTPC 0x1C ++#define NPE_REGMAP 0x1E ++#define NPE_CINDEX 0x1F ++ ++#define INSTR_WR_REG_SHORT 0x0000C000 ++#define INSTR_WR_REG_BYTE 0x00004000 ++#define INSTR_RD_FIFO 0x0F888220 ++#define INSTR_RESET_MBOX 0x0FAC8210 ++ ++#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */ ++#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */ ++#define ECS_BG_CTXT_REG_2 0x02 ++#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */ ++#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */ ++#define ECS_PRI_1_CTXT_REG_2 0x06 ++#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */ ++#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */ ++#define ECS_PRI_2_CTXT_REG_2 0x0A ++#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */ ++#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */ ++#define ECS_DBG_CTXT_REG_2 0x0E ++#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */ ++ ++#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */ ++#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */ ++#define ECS_REG_0_LDUR_BITS 8 ++#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */ ++#define ECS_REG_1_CCTXT_BITS 16 ++#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */ ++#define ECS_REG_1_SELCTXT_BITS 0 ++#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */ ++#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */ ++#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */ ++ ++/* NPE watchpoint_fifo register bit */ ++#define WFIFO_VALID 0x80000000 ++ ++/* NPE messaging_status register bit definitions */ ++#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */ ++#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */ ++#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */ ++#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */ ++#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */ ++#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */ ++#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */ ++#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */ ++ ++/* NPE messaging_control register bit definitions */ ++#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */ ++#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */ ++#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */ ++#define MSGCTL_IN_FIFO_WRITE 0x02000000 ++ ++/* NPE mailbox_status value for reset */ ++#define RESET_MBOX_STAT 0x0000F0F0 ++ ++const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" }; ++ ++#define print_npe(pri, npe, fmt, ...) \ ++ printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__) ++ ++#if DEBUG_MSG ++#define debug_msg(npe, fmt, ...) \ ++ print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__) ++#else ++#define debug_msg(npe, fmt, ...) ++#endif ++ ++static struct { ++ u32 reg, val; ++} ecs_reset[] = { ++ { ECS_BG_CTXT_REG_0, 0xA0000000 }, ++ { ECS_BG_CTXT_REG_1, 0x01000000 }, ++ { ECS_BG_CTXT_REG_2, 0x00008000 }, ++ { ECS_PRI_1_CTXT_REG_0, 0x20000080 }, ++ { ECS_PRI_1_CTXT_REG_1, 0x01000000 }, ++ { ECS_PRI_1_CTXT_REG_2, 0x00008000 }, ++ { ECS_PRI_2_CTXT_REG_0, 0x20000080 }, ++ { ECS_PRI_2_CTXT_REG_1, 0x01000000 }, ++ { ECS_PRI_2_CTXT_REG_2, 0x00008000 }, ++ { ECS_DBG_CTXT_REG_0, 0x20000000 }, ++ { ECS_DBG_CTXT_REG_1, 0x00000000 }, ++ { ECS_DBG_CTXT_REG_2, 0x001E0000 }, ++ { ECS_INSTRUCT_REG, 0x1003C00F }, ++}; ++ ++static struct npe npe_tab[NPE_COUNT] = { ++ { ++ .id = 0, ++ .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT, ++ .regs_phys = IXP4XX_NPEA_BASE_PHYS, ++ }, { ++ .id = 1, ++ .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT, ++ .regs_phys = IXP4XX_NPEB_BASE_PHYS, ++ }, { ++ .id = 2, ++ .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT, ++ .regs_phys = IXP4XX_NPEC_BASE_PHYS, ++ } ++}; ++ ++int npe_running(struct npe *npe) ++{ ++ return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0; ++} ++ ++static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data) ++{ ++ __raw_writel(data, &npe->regs->exec_data); ++ __raw_writel(addr, &npe->regs->exec_addr); ++ __raw_writel(cmd, &npe->regs->exec_status_cmd); ++} ++ ++static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd) ++{ ++ __raw_writel(addr, &npe->regs->exec_addr); ++ __raw_writel(cmd, &npe->regs->exec_status_cmd); ++ /* Iintroduce extra read cycles after issuing read command to NPE ++ so that we read the register after the NPE has updated it. ++ This is to overcome race condition between XScale and NPE */ ++ __raw_readl(&npe->regs->exec_data); ++ __raw_readl(&npe->regs->exec_data); ++ return __raw_readl(&npe->regs->exec_data); ++} ++ ++static void npe_clear_active(struct npe *npe, u32 reg) ++{ ++ u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG); ++ npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE); ++} ++ ++static void npe_start(struct npe *npe) ++{ ++ /* ensure only Background Context Stack Level is active */ ++ npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0); ++ npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0); ++ npe_clear_active(npe, ECS_DBG_CTXT_REG_0); ++ ++ __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); ++ __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd); ++} ++ ++static void npe_stop(struct npe *npe) ++{ ++ __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd); ++ __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/ ++} ++ ++static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx, ++ u32 ldur) ++{ ++ u32 wc; ++ int i; ++ ++ /* set the Active bit, and the LDUR, in the debug level */ ++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, ++ ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS)); ++ ++ /* set CCTXT at ECS DEBUG L3 to specify in which context to execute ++ the instruction, and set SELCTXT at ECS DEBUG Level to specify ++ which context store to access. ++ Debug ECS Level Reg 1 has form 0x000n000n, where n = context number ++ */ ++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG, ++ (ctx << ECS_REG_1_CCTXT_BITS) | ++ (ctx << ECS_REG_1_SELCTXT_BITS)); ++ ++ /* clear the pipeline */ ++ __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); ++ ++ /* load NPE instruction into the instruction register */ ++ npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr); ++ ++ /* we need this value later to wait for completion of NPE execution ++ step */ ++ wc = __raw_readl(&npe->regs->watch_count); ++ ++ /* issue a Step One command via the Execution Control register */ ++ __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd); ++ ++ /* Watch Count register increments when NPE completes an instruction */ ++ for (i = 0; i < MAX_RETRIES; i++) { ++ if (wc != __raw_readl(&npe->regs->watch_count)) ++ return 0; ++ udelay(1); ++ } ++ ++ print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n"); ++ return -ETIMEDOUT; ++} ++ ++static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr, ++ u8 val, u32 ctx) ++{ ++ /* here we build the NPE assembler instruction: mov8 d0, #0 */ ++ u32 instr = INSTR_WR_REG_BYTE | /* OpCode */ ++ addr << 9 | /* base Operand */ ++ (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ ++ (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */ ++ return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ ++} ++ ++static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr, ++ u16 val, u32 ctx) ++{ ++ /* here we build the NPE assembler instruction: mov16 d0, #0 */ ++ u32 instr = INSTR_WR_REG_SHORT | /* OpCode */ ++ addr << 9 | /* base Operand */ ++ (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ ++ (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */ ++ return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ ++} ++ ++static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr, ++ u32 val, u32 ctx) ++{ ++ /* write in 16 bit steps first the high and then the low value */ ++ if (npe_logical_reg_write16(npe, addr, val >> 16, ctx)) ++ return -ETIMEDOUT; ++ return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx); ++} ++ ++static int npe_reset(struct npe *npe) ++{ ++ u32 val, ctl, exec_count, ctx_reg2; ++ int i; ++ ++ ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) & ++ 0x3F3FFFFF; ++ ++ /* disable parity interrupt */ ++ __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control); ++ ++ /* pre exec - debug instruction */ ++ /* turn off the halt bit by clearing Execution Count register. */ ++ exec_count = __raw_readl(&npe->regs->exec_count); ++ __raw_writel(0, &npe->regs->exec_count); ++ /* ensure that IF and IE are on (temporarily), so that we don't end up ++ stepping forever */ ++ ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG); ++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 | ++ ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE); ++ ++ /* clear the FIFOs */ ++ while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID) ++ ; ++ while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) ++ /* read from the outFIFO until empty */ ++ print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n", ++ __raw_readl(&npe->regs->in_out_fifo)); ++ ++ while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) ++ /* step execution of the NPE intruction to read inFIFO using ++ the Debug Executing Context stack */ ++ if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0)) ++ return -ETIMEDOUT; ++ ++ /* reset the mailbox reg from the XScale side */ ++ __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status); ++ /* from NPE side */ ++ if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0)) ++ return -ETIMEDOUT; ++ ++ /* Reset the physical registers in the NPE register file */ ++ for (val = 0; val < NPE_PHYS_REG; val++) { ++ if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0)) ++ return -ETIMEDOUT; ++ /* address is either 0 or 4 */ ++ if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0)) ++ return -ETIMEDOUT; ++ } ++ ++ /* Reset the context store = each context's Context Store registers */ ++ ++ /* Context 0 has no STARTPC. Instead, this value is used to set NextPC ++ for Background ECS, to set where NPE starts executing code */ ++ val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG); ++ val &= ~ECS_REG_0_NEXTPC_MASK; ++ val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK; ++ npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val); ++ ++ for (i = 0; i < 16; i++) { ++ if (i) { /* Context 0 has no STEVT nor STARTPC */ ++ /* STEVT = off, 0x80 */ ++ if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i)) ++ return -ETIMEDOUT; ++ if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i)) ++ return -ETIMEDOUT; ++ } ++ /* REGMAP = d0->p0, d8->p2, d16->p4 */ ++ if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i)) ++ return -ETIMEDOUT; ++ if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i)) ++ return -ETIMEDOUT; ++ } ++ ++ /* post exec */ ++ /* clear active bit in debug level */ ++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0); ++ /* clear the pipeline */ ++ __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); ++ /* restore previous values */ ++ __raw_writel(exec_count, &npe->regs->exec_count); ++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2); ++ ++ /* write reset values to Execution Context Stack registers */ ++ for (val = 0; val < ARRAY_SIZE(ecs_reset); val++) ++ npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG, ++ ecs_reset[val].val); ++ ++ /* clear the profile counter */ ++ __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd); ++ ++ __raw_writel(0, &npe->regs->exec_count); ++ __raw_writel(0, &npe->regs->action_points[0]); ++ __raw_writel(0, &npe->regs->action_points[1]); ++ __raw_writel(0, &npe->regs->action_points[2]); ++ __raw_writel(0, &npe->regs->action_points[3]); ++ __raw_writel(0, &npe->regs->watch_count); ++ ++ val = ixp4xx_read_feature_bits(); ++ /* reset the NPE */ ++ ixp4xx_write_feature_bits(val & ++ ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); ++ for (i = 0; i < MAX_RETRIES; i++) { ++ if (!(ixp4xx_read_feature_bits() & ++ (IXP4XX_FEATURE_RESET_NPEA << npe->id))) ++ break; /* reset completed */ ++ udelay(1); ++ } ++ if (i == MAX_RETRIES) ++ return -ETIMEDOUT; ++ ++ /* deassert reset */ ++ ixp4xx_write_feature_bits(val | ++ (IXP4XX_FEATURE_RESET_NPEA << npe->id)); ++ for (i = 0; i < MAX_RETRIES; i++) { ++ if (ixp4xx_read_feature_bits() & ++ (IXP4XX_FEATURE_RESET_NPEA << npe->id)) ++ break; /* NPE is back alive */ ++ udelay(1); ++ } ++ if (i == MAX_RETRIES) ++ return -ETIMEDOUT; ++ ++ npe_stop(npe); ++ ++ /* restore NPE configuration bus Control Register - parity settings */ ++ __raw_writel(ctl, &npe->regs->messaging_control); ++ return 0; ++} ++ ++ ++int npe_send_message(struct npe *npe, const void *msg, const char *what) ++{ ++ const u32 *send = msg; ++ int cycles = 0; ++ ++ debug_msg(npe, "Trying to send message %s [%08X:%08X]\n", ++ what, send[0], send[1]); ++ ++ if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) { ++ debug_msg(npe, "NPE input FIFO not empty\n"); ++ return -EIO; ++ } ++ ++ __raw_writel(send[0], &npe->regs->in_out_fifo); ++ ++ if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) { ++ debug_msg(npe, "NPE input FIFO full\n"); ++ return -EIO; ++ } ++ ++ __raw_writel(send[1], &npe->regs->in_out_fifo); ++ ++ while ((cycles < MAX_RETRIES) && ++ (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) { ++ udelay(1); ++ cycles++; ++ } ++ ++ if (cycles == MAX_RETRIES) { ++ debug_msg(npe, "Timeout sending message\n"); ++ return -ETIMEDOUT; ++ } ++ ++ debug_msg(npe, "Sending a message took %i cycles\n", cycles); ++ return 0; ++} ++ ++int npe_recv_message(struct npe *npe, void *msg, const char *what) ++{ ++ u32 *recv = msg; ++ int cycles = 0, cnt = 0; ++ ++ debug_msg(npe, "Trying to receive message %s\n", what); ++ ++ while (cycles < MAX_RETRIES) { ++ if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) { ++ recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo); ++ if (cnt == 2) ++ break; ++ } else { ++ udelay(1); ++ cycles++; ++ } ++ } ++ ++ switch(cnt) { ++ case 1: ++ debug_msg(npe, "Received [%08X]\n", recv[0]); ++ break; ++ case 2: ++ debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]); ++ break; ++ } ++ ++ if (cycles == MAX_RETRIES) { ++ debug_msg(npe, "Timeout waiting for message\n"); ++ return -ETIMEDOUT; ++ } ++ ++ debug_msg(npe, "Receiving a message took %i cycles\n", cycles); ++ return 0; ++} ++ ++int npe_send_recv_message(struct npe *npe, void *msg, const char *what) ++{ ++ int result; ++ u32 *send = msg, recv[2]; ++ ++ if ((result = npe_send_message(npe, msg, what)) != 0) ++ return result; ++ if ((result = npe_recv_message(npe, recv, what)) != 0) ++ return result; ++ ++ if ((recv[0] != send[0]) || (recv[1] != send[1])) { ++ debug_msg(npe, "Message %s: unexpected message received\n", ++ what); ++ return -EIO; ++ } ++ return 0; ++} ++ ++ ++int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) ++{ ++ const struct firmware *fw_entry; ++ ++ struct dl_block { ++ u32 type; ++ u32 offset; ++ } *blk; ++ ++ struct dl_image { ++ u32 magic; ++ u32 id; ++ u32 size; ++ union { ++ u32 data[0]; ++ struct dl_block blocks[0]; ++ }; ++ } *image; ++ ++ struct dl_codeblock { ++ u32 npe_addr; ++ u32 size; ++ u32 data[0]; ++ } *cb; ++ ++ int i, j, err, data_size, instr_size, blocks, table_end; ++ u32 cmd; ++ ++ if ((err = request_firmware(&fw_entry, name, dev)) != 0) ++ return err; ++ ++ err = -EINVAL; ++ if (fw_entry->size < sizeof(struct dl_image)) { ++ print_npe(KERN_ERR, npe, "incomplete firmware file\n"); ++ goto err; ++ } ++ image = (struct dl_image*)fw_entry->data; ++ ++#if DEBUG_FW ++ print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n", ++ image->magic, image->id, image->size, image->size * 4); ++#endif ++ ++ if (image->magic == swab32(FW_MAGIC)) { /* swapped file */ ++ image->id = swab32(image->id); ++ image->size = swab32(image->size); ++ } else if (image->magic != FW_MAGIC) { ++ print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n", ++ image->magic); ++ goto err; ++ } ++ if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) { ++ print_npe(KERN_ERR, npe, ++ "inconsistent size of firmware file\n"); ++ goto err; ++ } ++ if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) { ++ print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n"); ++ goto err; ++ } ++ if (image->magic == swab32(FW_MAGIC)) ++ for (i = 0; i < image->size; i++) ++ image->data[i] = swab32(image->data[i]); ++ ++ if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) { ++ print_npe(KERN_INFO, npe, "IXP46x firmware ignored on " ++ "IXP42x\n"); ++ goto err; ++ } ++ ++ if (npe_running(npe)) { ++ print_npe(KERN_INFO, npe, "unable to load firmware, NPE is " ++ "already running\n"); ++ err = -EBUSY; ++ goto err; ++ } ++#if 0 ++ npe_stop(npe); ++ npe_reset(npe); ++#endif ++ ++ print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " ++ "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, ++ (image->id >> 8) & 0xFF, image->id & 0xFF); ++ ++ if (!cpu_is_ixp46x()) { ++ if (!npe->id) ++ instr_size = NPE_A_42X_INSTR_SIZE; ++ else ++ instr_size = NPE_B_AND_C_42X_INSTR_SIZE; ++ data_size = NPE_42X_DATA_SIZE; ++ } else { ++ instr_size = NPE_46X_INSTR_SIZE; ++ data_size = NPE_46X_DATA_SIZE; ++ } ++ ++ for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size; ++ blocks++) ++ if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF) ++ break; ++ if (blocks * sizeof(struct dl_block) / 4 >= image->size) { ++ print_npe(KERN_INFO, npe, "firmware EOF block marker not " ++ "found\n"); ++ goto err; ++ } ++ ++#if DEBUG_FW ++ print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks); ++#endif ++ ++ table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */; ++ for (i = 0, blk = image->blocks; i < blocks; i++, blk++) { ++ if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4 ++ || blk->offset < table_end) { ++ print_npe(KERN_INFO, npe, "invalid offset 0x%X of " ++ "firmware block #%i\n", blk->offset, i); ++ goto err; ++ } ++ ++ cb = (struct dl_codeblock*)&image->data[blk->offset]; ++ if (blk->type == FW_BLOCK_TYPE_INSTR) { ++ if (cb->npe_addr + cb->size > instr_size) ++ goto too_big; ++ cmd = CMD_WR_INS_MEM; ++ } else if (blk->type == FW_BLOCK_TYPE_DATA) { ++ if (cb->npe_addr + cb->size > data_size) ++ goto too_big; ++ cmd = CMD_WR_DATA_MEM; ++ } else { ++ print_npe(KERN_INFO, npe, "invalid firmware block #%i " ++ "type 0x%X\n", i, blk->type); ++ goto err; ++ } ++ if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) { ++ print_npe(KERN_INFO, npe, "firmware block #%i doesn't " ++ "fit in firmware image: type %c, start 0x%X," ++ " length 0x%X\n", i, ++ blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', ++ cb->npe_addr, cb->size); ++ goto err; ++ } ++ ++ for (j = 0; j < cb->size; j++) ++ npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]); ++ } ++ ++ npe_start(npe); ++ if (!npe_running(npe)) ++ print_npe(KERN_ERR, npe, "unable to start\n"); ++ release_firmware(fw_entry); ++ return 0; ++ ++too_big: ++ print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE " ++ "memory: type %c, start 0x%X, length 0x%X\n", i, ++ blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', ++ cb->npe_addr, cb->size); ++err: ++ release_firmware(fw_entry); ++ return err; ++} ++ ++ ++struct npe *npe_request(int id) ++{ ++ if (id < NPE_COUNT) ++ if (npe_tab[id].valid) ++ if (try_module_get(THIS_MODULE)) ++ return &npe_tab[id]; ++ return NULL; ++} ++ ++void npe_release(struct npe *npe) ++{ ++ module_put(THIS_MODULE); ++} ++ ++ ++static int __init npe_init_module(void) ++{ ++ ++ int i, found = 0; ++ ++ for (i = 0; i < NPE_COUNT; i++) { ++ struct npe *npe = &npe_tab[i]; ++ if (!(ixp4xx_read_feature_bits() & ++ (IXP4XX_FEATURE_RESET_NPEA << i))) ++ continue; /* NPE already disabled or not present */ ++ if (!(npe->mem_res = request_mem_region(npe->regs_phys, ++ REGS_SIZE, ++ npe_name(npe)))) { ++ print_npe(KERN_ERR, npe, ++ "failed to request memory region\n"); ++ continue; ++ } ++ ++ if (npe_reset(npe)) ++ continue; ++ npe->valid = 1; ++ found++; ++ } ++ ++ if (!found) ++ return -ENOSYS; ++ return 0; ++} ++ ++static void __exit npe_cleanup_module(void) ++{ ++ int i; ++ ++ for (i = 0; i < NPE_COUNT; i++) ++ if (npe_tab[i].mem_res) { ++ npe_reset(&npe_tab[i]); ++ release_resource(npe_tab[i].mem_res); ++ } ++} ++ ++module_init(npe_init_module); ++module_exit(npe_cleanup_module); ++ ++MODULE_AUTHOR("Krzysztof Halasa"); ++MODULE_LICENSE("GPL v2"); ++ ++EXPORT_SYMBOL(npe_names); ++EXPORT_SYMBOL(npe_running); ++EXPORT_SYMBOL(npe_request); ++EXPORT_SYMBOL(npe_release); ++EXPORT_SYMBOL(npe_load_firmware); ++EXPORT_SYMBOL(npe_send_message); ++EXPORT_SYMBOL(npe_recv_message); ++EXPORT_SYMBOL(npe_send_recv_message); +diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c +new file mode 100644 +index 0000000..e833013 +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c +@@ -0,0 +1,274 @@ ++/* ++ * Intel IXP4xx Queue Manager driver for Linux ++ * ++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License ++ * as published by the Free Software Foundation. ++ */ ++ ++#include <linux/ioport.h> ++#include <linux/interrupt.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <asm/arch/qmgr.h> ++ ++#define DEBUG 0 ++ ++struct qmgr_regs __iomem *qmgr_regs; ++static struct resource *mem_res; ++static spinlock_t qmgr_lock; ++static u32 used_sram_bitmap[4]; /* 128 16-dword pages */ ++static void (*irq_handlers[HALF_QUEUES])(void *pdev); ++static void *irq_pdevs[HALF_QUEUES]; ++ ++void qmgr_set_irq(unsigned int queue, int src, ++ void (*handler)(void *pdev), void *pdev) ++{ ++ u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */ ++ int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */ ++ unsigned long flags; ++ ++ src &= 7; ++ spin_lock_irqsave(&qmgr_lock, flags); ++ __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg); ++ irq_handlers[queue] = handler; ++ irq_pdevs[queue] = pdev; ++ spin_unlock_irqrestore(&qmgr_lock, flags); ++} ++ ++ ++static irqreturn_t qmgr_irq1(int irq, void *pdev) ++{ ++ int i; ++ u32 val = __raw_readl(&qmgr_regs->irqstat[0]); ++ __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */ ++ ++ for (i = 0; i < HALF_QUEUES; i++) ++ if (val & (1 << i)) ++ irq_handlers[i](irq_pdevs[i]); ++ ++ return val ? IRQ_HANDLED : 0; ++} ++ ++ ++void qmgr_enable_irq(unsigned int queue) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&qmgr_lock, flags); ++ __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue), ++ &qmgr_regs->irqen[0]); ++ spin_unlock_irqrestore(&qmgr_lock, flags); ++} ++ ++void qmgr_disable_irq(unsigned int queue) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&qmgr_lock, flags); ++ __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue), ++ &qmgr_regs->irqen[0]); ++ spin_unlock_irqrestore(&qmgr_lock, flags); ++} ++ ++static inline void shift_mask(u32 *mask) ++{ ++ mask[3] = mask[3] << 1 | mask[2] >> 31; ++ mask[2] = mask[2] << 1 | mask[1] >> 31; ++ mask[1] = mask[1] << 1 | mask[0] >> 31; ++ mask[0] <<= 1; ++} ++ ++int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, ++ unsigned int nearly_empty_watermark, ++ unsigned int nearly_full_watermark) ++{ ++ u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ ++ int err; ++ ++ if (queue >= HALF_QUEUES) ++ return -ERANGE; ++ ++ if ((nearly_empty_watermark | nearly_full_watermark) & ~7) ++ return -EINVAL; ++ ++ switch (len) { ++ case 16: ++ cfg = 0 << 24; ++ mask[0] = 0x1; ++ break; ++ case 32: ++ cfg = 1 << 24; ++ mask[0] = 0x3; ++ break; ++ case 64: ++ cfg = 2 << 24; ++ mask[0] = 0xF; ++ break; ++ case 128: ++ cfg = 3 << 24; ++ mask[0] = 0xFF; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ cfg |= nearly_empty_watermark << 26; ++ cfg |= nearly_full_watermark << 29; ++ len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */ ++ mask[1] = mask[2] = mask[3] = 0; ++ ++ if (!try_module_get(THIS_MODULE)) ++ return -ENODEV; ++ ++ spin_lock_irq(&qmgr_lock); ++ if (__raw_readl(&qmgr_regs->sram[queue])) { ++ err = -EBUSY; ++ goto err; ++ } ++ ++ while (1) { ++ if (!(used_sram_bitmap[0] & mask[0]) && ++ !(used_sram_bitmap[1] & mask[1]) && ++ !(used_sram_bitmap[2] & mask[2]) && ++ !(used_sram_bitmap[3] & mask[3])) ++ break; /* found free space */ ++ ++ addr++; ++ shift_mask(mask); ++ if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) { ++ printk(KERN_ERR "qmgr: no free SRAM space for" ++ " queue %i\n", queue); ++ err = -ENOMEM; ++ goto err; ++ } ++ } ++ ++ used_sram_bitmap[0] |= mask[0]; ++ used_sram_bitmap[1] |= mask[1]; ++ used_sram_bitmap[2] |= mask[2]; ++ used_sram_bitmap[3] |= mask[3]; ++ __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]); ++ spin_unlock_irq(&qmgr_lock); ++ ++#if DEBUG ++ printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n", ++ queue, addr); ++#endif ++ return 0; ++ ++err: ++ spin_unlock_irq(&qmgr_lock); ++ module_put(THIS_MODULE); ++ return err; ++} ++ ++void qmgr_release_queue(unsigned int queue) ++{ ++ u32 cfg, addr, mask[4]; ++ ++ BUG_ON(queue >= HALF_QUEUES); /* not in valid range */ ++ ++ spin_lock_irq(&qmgr_lock); ++ cfg = __raw_readl(&qmgr_regs->sram[queue]); ++ addr = (cfg >> 14) & 0xFF; ++ ++ BUG_ON(!addr); /* not requested */ ++ ++ switch ((cfg >> 24) & 3) { ++ case 0: mask[0] = 0x1; break; ++ case 1: mask[0] = 0x3; break; ++ case 2: mask[0] = 0xF; break; ++ case 3: mask[0] = 0xFF; break; ++ } ++ ++ while (addr--) ++ shift_mask(mask); ++ ++ __raw_writel(0, &qmgr_regs->sram[queue]); ++ ++ used_sram_bitmap[0] &= ~mask[0]; ++ used_sram_bitmap[1] &= ~mask[1]; ++ used_sram_bitmap[2] &= ~mask[2]; ++ used_sram_bitmap[3] &= ~mask[3]; ++ irq_handlers[queue] = NULL; /* catch IRQ bugs */ ++ spin_unlock_irq(&qmgr_lock); ++ ++ module_put(THIS_MODULE); ++#if DEBUG ++ printk(KERN_DEBUG "qmgr: released queue %i\n", queue); ++#endif ++} ++ ++static int qmgr_init(void) ++{ ++ int i, err; ++ mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS, ++ IXP4XX_QMGR_REGION_SIZE, ++ "IXP4xx Queue Manager"); ++ if (mem_res == NULL) ++ return -EBUSY; ++ ++ qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); ++ if (qmgr_regs == NULL) { ++ err = -ENOMEM; ++ goto error_map; ++ } ++ ++ /* reset qmgr registers */ ++ for (i = 0; i < 4; i++) { ++ __raw_writel(0x33333333, &qmgr_regs->stat1[i]); ++ __raw_writel(0, &qmgr_regs->irqsrc[i]); ++ } ++ for (i = 0; i < 2; i++) { ++ __raw_writel(0, &qmgr_regs->stat2[i]); ++ __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */ ++ __raw_writel(0, &qmgr_regs->irqen[i]); ++ } ++ ++ for (i = 0; i < QUEUES; i++) ++ __raw_writel(0, &qmgr_regs->sram[i]); ++ ++ err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0, ++ "IXP4xx Queue Manager", NULL); ++ if (err) { ++ printk(KERN_ERR "qmgr: failed to request IRQ%i\n", ++ IRQ_IXP4XX_QM1); ++ goto error_irq; ++ } ++ ++ used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */ ++ spin_lock_init(&qmgr_lock); ++ ++ printk(KERN_INFO "IXP4xx Queue Manager initialized.\n"); ++ return 0; ++ ++error_irq: ++ iounmap(qmgr_regs); ++error_map: ++ release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); ++ return err; ++} ++ ++static void qmgr_remove(void) ++{ ++ free_irq(IRQ_IXP4XX_QM1, NULL); ++ synchronize_irq(IRQ_IXP4XX_QM1); ++ iounmap(qmgr_regs); ++ release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); ++} ++ ++module_init(qmgr_init); ++module_exit(qmgr_remove); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Krzysztof Halasa"); ++ ++EXPORT_SYMBOL(qmgr_regs); ++EXPORT_SYMBOL(qmgr_set_irq); ++EXPORT_SYMBOL(qmgr_enable_irq); ++EXPORT_SYMBOL(qmgr_disable_irq); ++EXPORT_SYMBOL(qmgr_request_queue); ++EXPORT_SYMBOL(qmgr_release_queue); +diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig +index f9cc2b6..9274d3f 100644 +--- a/drivers/net/arm/Kconfig ++++ b/drivers/net/arm/Kconfig +@@ -47,3 +47,13 @@ config EP93XX_ETH + help + This is a driver for the ethernet hardware included in EP93xx CPUs. + Say Y if you are building a kernel for EP93xx based devices. ++ ++config IXP4XX_ETH ++ tristate "IXP4xx Ethernet support" ++ depends on NET_ETHERNET && ARM && ARCH_IXP4XX ++ select IXP4XX_NPE ++ select IXP4XX_QMGR ++ select MII ++ help ++ Say Y here if you want to use built-in Ethernet ports ++ on IXP4xx processor. +diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile +index a4c8682..7c812ac 100644 +--- a/drivers/net/arm/Makefile ++++ b/drivers/net/arm/Makefile +@@ -9,3 +9,4 @@ obj-$(CONFIG_ARM_ETHER3) += ether3.o + obj-$(CONFIG_ARM_ETHER1) += ether1.o + obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o + obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o ++obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o +diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c +new file mode 100644 +index 0000000..2c23f50 +--- /dev/null ++++ b/drivers/net/arm/ixp4xx_eth.c +@@ -0,0 +1,1259 @@ ++/* ++ * Intel IXP4xx Ethernet driver for Linux ++ * ++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License ++ * as published by the Free Software Foundation. ++ * ++ * Ethernet port config (0x00 is not present on IXP42X): ++ * ++ * logical port 0x00 0x10 0x20 ++ * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) ++ * physical PortId 2 0 1 ++ * TX queue 23 24 25 ++ * RX-free queue 26 27 28 ++ * TX-done queue is always 31, per-port RX and TX-ready queues are configurable ++ * ++ * ++ * Queue entries: ++ * bits 0 -> 1 - NPE ID (RX and TX-done) ++ * bits 0 -> 2 - priority (TX, per 802.1D) ++ * bits 3 -> 4 - port ID (user-set?) ++ * bits 5 -> 31 - physical descriptor address ++ */ ++ ++#include <linux/delay.h> ++#include <linux/dma-mapping.h> ++#include <linux/dmapool.h> ++#include <linux/etherdevice.h> ++#include <linux/io.h> ++#include <linux/kernel.h> ++#include <linux/mii.h> ++#include <linux/platform_device.h> ++#include <asm/arch/npe.h> ++#include <asm/arch/qmgr.h> ++ ++#define DEBUG_QUEUES 0 ++#define DEBUG_DESC 0 ++#define DEBUG_RX 0 ++#define DEBUG_TX 0 ++#define DEBUG_PKT_BYTES 0 ++#define DEBUG_MDIO 0 ++#define DEBUG_CLOSE 0 ++ ++#define DRV_NAME "ixp4xx_eth" ++ ++#define MAX_NPES 3 ++ ++#define RX_DESCS 64 /* also length of all RX queues */ ++#define TX_DESCS 16 /* also length of all TX queues */ ++#define TXDONE_QUEUE_LEN 64 /* dwords */ ++ ++#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) ++#define REGS_SIZE 0x1000 ++#define MAX_MRU 1536 /* 0x600 */ ++ ++#define MDIO_INTERVAL (3 * HZ) ++#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ ++#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */ ++#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ ++ ++#define NPE_ID(port_id) ((port_id) >> 4) ++#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) ++#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) ++#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) ++#define TXDONE_QUEUE 31 ++ ++/* TX Control Registers */ ++#define TX_CNTRL0_TX_EN 0x01 ++#define TX_CNTRL0_HALFDUPLEX 0x02 ++#define TX_CNTRL0_RETRY 0x04 ++#define TX_CNTRL0_PAD_EN 0x08 ++#define TX_CNTRL0_APPEND_FCS 0x10 ++#define TX_CNTRL0_2DEFER 0x20 ++#define TX_CNTRL0_RMII 0x40 /* reduced MII */ ++#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ ++ ++/* RX Control Registers */ ++#define RX_CNTRL0_RX_EN 0x01 ++#define RX_CNTRL0_PADSTRIP_EN 0x02 ++#define RX_CNTRL0_SEND_FCS 0x04 ++#define RX_CNTRL0_PAUSE_EN 0x08 ++#define RX_CNTRL0_LOOP_EN 0x10 ++#define RX_CNTRL0_ADDR_FLTR_EN 0x20 ++#define RX_CNTRL0_RX_RUNT_EN 0x40 ++#define RX_CNTRL0_BCAST_DIS 0x80 ++#define RX_CNTRL1_DEFER_EN 0x01 ++ ++/* Core Control Register */ ++#define CORE_RESET 0x01 ++#define CORE_RX_FIFO_FLUSH 0x02 ++#define CORE_TX_FIFO_FLUSH 0x04 ++#define CORE_SEND_JAM 0x08 ++#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ ++ ++#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ ++ TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ ++ TX_CNTRL0_2DEFER) ++#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN ++#define DEFAULT_CORE_CNTRL CORE_MDC_EN ++ ++ ++/* NPE message codes */ ++#define NPE_GETSTATUS 0x00 ++#define NPE_EDB_SETPORTADDRESS 0x01 ++#define NPE_EDB_GETMACADDRESSDATABASE 0x02 ++#define NPE_EDB_SETMACADDRESSSDATABASE 0x03 ++#define NPE_GETSTATS 0x04 ++#define NPE_RESETSTATS 0x05 ++#define NPE_SETMAXFRAMELENGTHS 0x06 ++#define NPE_VLAN_SETRXTAGMODE 0x07 ++#define NPE_VLAN_SETDEFAULTRXVID 0x08 ++#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 ++#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A ++#define NPE_VLAN_SETRXQOSENTRY 0x0B ++#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C ++#define NPE_STP_SETBLOCKINGSTATE 0x0D ++#define NPE_FW_SETFIREWALLMODE 0x0E ++#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F ++#define NPE_PC_SETAPMACTABLE 0x11 ++#define NPE_SETLOOPBACK_MODE 0x12 ++#define NPE_PC_SETBSSIDTABLE 0x13 ++#define NPE_ADDRESS_FILTER_CONFIG 0x14 ++#define NPE_APPENDFCSCONFIG 0x15 ++#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 ++#define NPE_MAC_RECOVERY_START 0x17 ++ ++ ++#ifdef __ARMEB__ ++typedef struct sk_buff buffer_t; ++#define free_buffer dev_kfree_skb ++#define free_buffer_irq dev_kfree_skb_irq ++#else ++typedef void buffer_t; ++#define free_buffer kfree ++#define free_buffer_irq kfree ++#endif ++ ++struct eth_regs { ++ u32 tx_control[2], __res1[2]; /* 000 */ ++ u32 rx_control[2], __res2[2]; /* 010 */ ++ u32 random_seed, __res3[3]; /* 020 */ ++ u32 partial_empty_threshold, __res4; /* 030 */ ++ u32 partial_full_threshold, __res5; /* 038 */ ++ u32 tx_start_bytes, __res6[3]; /* 040 */ ++ u32 tx_deferral, rx_deferral,__res7[2]; /* 050 */ ++ u32 tx_2part_deferral[2], __res8[2]; /* 060 */ ++ u32 slot_time, __res9[3]; /* 070 */ ++ u32 mdio_command[4]; /* 080 */ ++ u32 mdio_status[4]; /* 090 */ ++ u32 mcast_mask[6], __res10[2]; /* 0A0 */ ++ u32 mcast_addr[6], __res11[2]; /* 0C0 */ ++ u32 int_clock_threshold, __res12[3]; /* 0E0 */ ++ u32 hw_addr[6], __res13[61]; /* 0F0 */ ++ u32 core_control; /* 1FC */ ++}; ++ ++struct port { ++ struct resource *mem_res; ++ struct eth_regs __iomem *regs; ++ struct npe *npe; ++ struct net_device *netdev; ++ struct net_device_stats stat; ++ struct mii_if_info mii; ++ struct delayed_work mdio_thread; ++ struct eth_plat_info *plat; ++ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; ++ struct desc *desc_tab; /* coherent */ ++ u32 desc_tab_phys; ++ int id; /* logical port ID */ ++ u16 mii_bmcr; ++}; ++ ++/* NPE message structure */ ++struct msg { ++#ifdef __ARMEB__ ++ u8 cmd, eth_id, byte2, byte3; ++ u8 byte4, byte5, byte6, byte7; ++#else ++ u8 byte3, byte2, eth_id, cmd; ++ u8 byte7, byte6, byte5, byte4; ++#endif ++}; ++ ++/* Ethernet packet descriptor */ ++struct desc { ++ u32 next; /* pointer to next buffer, unused */ ++ ++#ifdef __ARMEB__ ++ u16 buf_len; /* buffer length */ ++ u16 pkt_len; /* packet length */ ++ u32 data; /* pointer to data buffer in RAM */ ++ u8 dest_id; ++ u8 src_id; ++ u16 flags; ++ u8 qos; ++ u8 padlen; ++ u16 vlan_tci; ++#else ++ u16 pkt_len; /* packet length */ ++ u16 buf_len; /* buffer length */ ++ u32 data; /* pointer to data buffer in RAM */ ++ u16 flags; ++ u8 src_id; ++ u8 dest_id; ++ u16 vlan_tci; ++ u8 padlen; ++ u8 qos; ++#endif ++ ++#ifdef __ARMEB__ ++ u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; ++ u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; ++ u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; ++#else ++ u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; ++ u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; ++ u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; ++#endif ++}; ++ ++ ++#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ ++ (n) * sizeof(struct desc)) ++#define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) ++ ++#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ ++ ((n) + RX_DESCS) * sizeof(struct desc)) ++#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) ++ ++#ifndef __ARMEB__ ++static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) ++{ ++ int i; ++ for (i = 0; i < cnt; i++) ++ dest[i] = swab32(src[i]); ++} ++#endif ++ ++static spinlock_t mdio_lock; ++static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ ++static int ports_open; ++static struct port *npe_port_tab[MAX_NPES]; ++static struct dma_pool *dma_pool; ++ ++ ++static u16 mdio_cmd(struct net_device *dev, int phy_id, int location, ++ int write, u16 cmd) ++{ ++ int cycles = 0; ++ ++ if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { ++ printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name); ++ return 0; ++ } ++ ++ if (write) { ++ __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); ++ __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); ++ } ++ __raw_writel(((phy_id << 5) | location) & 0xFF, ++ &mdio_regs->mdio_command[2]); ++ __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, ++ &mdio_regs->mdio_command[3]); ++ ++ while ((cycles < MAX_MDIO_RETRIES) && ++ (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { ++ udelay(1); ++ cycles++; ++ } ++ ++ if (cycles == MAX_MDIO_RETRIES) { ++ printk(KERN_ERR "%s: MII write failed\n", dev->name); ++ return 0; ++ } ++ ++#if DEBUG_MDIO ++ printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name, ++ cycles); ++#endif ++ ++ if (write) ++ return 0; ++ ++ if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { ++ printk(KERN_ERR "%s: MII read failed\n", dev->name); ++ return 0; ++ } ++ ++ return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | ++ (__raw_readl(&mdio_regs->mdio_status[1]) << 8); ++} ++ ++static int mdio_read(struct net_device *dev, int phy_id, int location) ++{ ++ unsigned long flags; ++ u16 val; ++ ++ spin_lock_irqsave(&mdio_lock, flags); ++ val = mdio_cmd(dev, phy_id, location, 0, 0); ++ spin_unlock_irqrestore(&mdio_lock, flags); ++ return val; ++} ++ ++static void mdio_write(struct net_device *dev, int phy_id, int location, ++ int val) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&mdio_lock, flags); ++ mdio_cmd(dev, phy_id, location, 1, val); ++ spin_unlock_irqrestore(&mdio_lock, flags); ++} ++ ++static void phy_reset(struct net_device *dev, int phy_id) ++{ ++ struct port *port = netdev_priv(dev); ++ int cycles = 0; ++ ++ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET); ++ ++ while (cycles < MAX_MII_RESET_RETRIES) { ++ if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) { ++#if DEBUG_MDIO ++ printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n", ++ dev->name, cycles); ++#endif ++ return; ++ } ++ udelay(1); ++ cycles++; ++ } ++ ++ printk(KERN_ERR "%s: MII reset failed\n", dev->name); ++} ++ ++static void eth_set_duplex(struct port *port) ++{ ++ if (port->mii.full_duplex) ++ __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, ++ &port->regs->tx_control[0]); ++ else ++ __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, ++ &port->regs->tx_control[0]); ++} ++ ++ ++static void phy_check_media(struct port *port, int init) ++{ ++ if (mii_check_media(&port->mii, 1, init)) ++ eth_set_duplex(port); ++ if (port->mii.force_media) { /* mii_check_media() doesn't work */ ++ struct net_device *dev = port->netdev; ++ int cur_link = mii_link_ok(&port->mii); ++ int prev_link = netif_carrier_ok(dev); ++ ++ if (!prev_link && cur_link) { ++ printk(KERN_INFO "%s: link up\n", dev->name); ++ netif_carrier_on(dev); ++ } else if (prev_link && !cur_link) { ++ printk(KERN_INFO "%s: link down\n", dev->name); ++ netif_carrier_off(dev); ++ } ++ } ++} ++ ++ ++static void mdio_thread(struct work_struct *work) ++{ ++ struct port *port = container_of(work, struct port, mdio_thread.work); ++ ++ phy_check_media(port, 0); ++ schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL); ++} ++ ++ ++static inline void debug_pkt(struct net_device *dev, const char *func, ++ u8 *data, int len) ++{ ++#if DEBUG_PKT_BYTES ++ int i; ++ ++ printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len); ++ for (i = 0; i < len; i++) { ++ if (i >= DEBUG_PKT_BYTES) ++ break; ++ printk("%s%02X", ++ ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", ++ data[i]); ++ } ++ printk("\n"); ++#endif ++} ++ ++ ++static inline void debug_desc(u32 phys, struct desc *desc) ++{ ++#if DEBUG_DESC ++ printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" ++ " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", ++ phys, desc->next, desc->buf_len, desc->pkt_len, ++ desc->data, desc->dest_id, desc->src_id, desc->flags, ++ desc->qos, desc->padlen, desc->vlan_tci, ++ desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, ++ desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, ++ desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, ++ desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); ++#endif ++} ++ ++static inline void debug_queue(unsigned int queue, int is_get, u32 phys) ++{ ++#if DEBUG_QUEUES ++ static struct { ++ int queue; ++ char *name; ++ } names[] = { ++ { TX_QUEUE(0x10), "TX#0 " }, ++ { TX_QUEUE(0x20), "TX#1 " }, ++ { TX_QUEUE(0x00), "TX#2 " }, ++ { RXFREE_QUEUE(0x10), "RX-free#0 " }, ++ { RXFREE_QUEUE(0x20), "RX-free#1 " }, ++ { RXFREE_QUEUE(0x00), "RX-free#2 " }, ++ { TXDONE_QUEUE, "TX-done " }, ++ }; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(names); i++) ++ if (names[i].queue == queue) ++ break; ++ ++ printk(KERN_DEBUG "Queue %i %s%s %X\n", queue, ++ i < ARRAY_SIZE(names) ? names[i].name : "", ++ is_get ? "->" : "<-", phys); ++#endif ++} ++ ++static inline u32 queue_get_entry(unsigned int queue) ++{ ++ u32 phys = qmgr_get_entry(queue); ++ debug_queue(queue, 1, phys); ++ return phys; ++} ++ ++static inline int queue_get_desc(unsigned int queue, struct port *port, ++ int is_tx) ++{ ++ u32 phys, tab_phys, n_desc; ++ struct desc *tab; ++ ++ if (!(phys = queue_get_entry(queue))) ++ return -1; ++ ++ phys &= ~0x1F; /* mask out non-address bits */ ++ tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); ++ tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); ++ n_desc = (phys - tab_phys) / sizeof(struct desc); ++ BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); ++ debug_desc(phys, &tab[n_desc]); ++ BUG_ON(tab[n_desc].next); ++ return n_desc; ++} ++ ++static inline void queue_put_desc(unsigned int queue, u32 phys, ++ struct desc *desc) ++{ ++ debug_queue(queue, 0, phys); ++ debug_desc(phys, desc); ++ BUG_ON(phys & 0x1F); ++ qmgr_put_entry(queue, phys); ++ BUG_ON(qmgr_stat_overflow(queue)); ++} ++ ++ ++static inline void dma_unmap_tx(struct port *port, struct desc *desc) ++{ ++#ifdef __ARMEB__ ++ dma_unmap_single(&port->netdev->dev, desc->data, ++ desc->buf_len, DMA_TO_DEVICE); ++#else ++ dma_unmap_single(&port->netdev->dev, desc->data & ~3, ++ ALIGN((desc->data & 3) + desc->buf_len, 4), ++ DMA_TO_DEVICE); ++#endif ++} ++ ++ ++static void eth_rx_irq(void *pdev) ++{ ++ struct net_device *dev = pdev; ++ struct port *port = netdev_priv(dev); ++ ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); ++#endif ++ qmgr_disable_irq(port->plat->rxq); ++ netif_rx_schedule(dev); ++} ++ ++static int eth_poll(struct net_device *dev, int *budget) ++{ ++ struct port *port = netdev_priv(dev); ++ unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); ++ int quota = dev->quota, received = 0; ++ ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: eth_poll\n", dev->name); ++#endif ++ ++ while (quota) { ++ struct sk_buff *skb; ++ struct desc *desc; ++ int n; ++#ifdef __ARMEB__ ++ struct sk_buff *temp; ++ u32 phys; ++#endif ++ ++ if ((n = queue_get_desc(rxq, port, 0)) < 0) { ++ dev->quota -= received; /* No packet received */ ++ *budget -= received; ++ received = 0; ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n", ++ dev->name); ++#endif ++ netif_rx_complete(dev); ++ qmgr_enable_irq(rxq); ++ if (!qmgr_stat_empty(rxq) && ++ netif_rx_reschedule(dev, 0)) { ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: eth_poll" ++ " netif_rx_reschedule successed\n", ++ dev->name); ++#endif ++ qmgr_disable_irq(rxq); ++ continue; ++ } ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: eth_poll all done\n", ++ dev->name); ++#endif ++ return 0; /* all work done */ ++ } ++ ++ desc = rx_desc_ptr(port, n); ++ ++#ifdef __ARMEB__ ++ if ((skb = netdev_alloc_skb(dev, MAX_MRU)) != NULL) { ++ phys = dma_map_single(&dev->dev, skb->data, ++ MAX_MRU, DMA_FROM_DEVICE); ++ if (dma_mapping_error(phys)) { ++ dev_kfree_skb(skb); ++ skb = NULL; ++ } ++ } ++#else ++ skb = netdev_alloc_skb(dev, desc->pkt_len); ++#endif ++ ++ if (!skb) { ++ port->stat.rx_dropped++; ++ /* put the desc back on RX-ready queue */ ++ desc->buf_len = MAX_MRU; ++ desc->pkt_len = 0; ++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); ++ continue; ++ } ++ ++ /* process received frame */ ++#ifdef __ARMEB__ ++ temp = skb; ++ skb = port->rx_buff_tab[n]; ++ dma_unmap_single(&dev->dev, desc->data, ++ MAX_MRU, DMA_FROM_DEVICE); ++#else ++ dma_sync_single(&dev->dev, desc->data, ++ MAX_MRU, DMA_FROM_DEVICE); ++ memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], ++ ALIGN(desc->pkt_len, 4) / 4); ++#endif ++ skb_put(skb, desc->pkt_len); ++ ++ debug_pkt(dev, "eth_poll", skb->data, skb->len); ++ ++ skb->protocol = eth_type_trans(skb, dev); ++ dev->last_rx = jiffies; ++ port->stat.rx_packets++; ++ port->stat.rx_bytes += skb->len; ++ netif_receive_skb(skb); ++ ++ /* put the new buffer on RX-free queue */ ++#ifdef __ARMEB__ ++ port->rx_buff_tab[n] = temp; ++ desc->data = phys; ++#endif ++ desc->buf_len = MAX_MRU; ++ desc->pkt_len = 0; ++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); ++ quota--; ++ received++; ++ } ++ dev->quota -= received; ++ *budget -= received; ++#if DEBUG_RX ++ printk(KERN_DEBUG "eth_poll(): end, not all work done\n"); ++#endif ++ return 1; /* not all work done */ ++} ++ ++ ++static void eth_txdone_irq(void *unused) ++{ ++ u32 phys; ++ ++#if DEBUG_TX ++ printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); ++#endif ++ while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) { ++ u32 npe_id, n_desc; ++ struct port *port; ++ struct desc *desc; ++ int start; ++ ++ npe_id = phys & 3; ++ BUG_ON(npe_id >= MAX_NPES); ++ port = npe_port_tab[npe_id]; ++ BUG_ON(!port); ++ phys &= ~0x1F; /* mask out non-address bits */ ++ n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); ++ BUG_ON(n_desc >= TX_DESCS); ++ desc = tx_desc_ptr(port, n_desc); ++ debug_desc(phys, desc); ++ ++ if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ ++ port->stat.tx_packets++; ++ port->stat.tx_bytes += desc->pkt_len; ++ ++ dma_unmap_tx(port, desc); ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", ++ port->netdev->name, port->tx_buff_tab[n_desc]); ++#endif ++ free_buffer_irq(port->tx_buff_tab[n_desc]); ++ port->tx_buff_tab[n_desc] = NULL; ++ } ++ ++ start = qmgr_stat_empty(port->plat->txreadyq); ++ queue_put_desc(port->plat->txreadyq, phys, desc); ++ if (start) { ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", ++ port->netdev->name); ++#endif ++ netif_wake_queue(port->netdev); ++ } ++ } ++} ++ ++static int eth_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ unsigned int txreadyq = port->plat->txreadyq; ++ int len, offset, bytes, n; ++ void *mem; ++ u32 phys; ++ struct desc *desc; ++ ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: eth_xmit\n", dev->name); ++#endif ++ ++ if (unlikely(skb->len > MAX_MRU)) { ++ dev_kfree_skb(skb); ++ port->stat.tx_errors++; ++ return NETDEV_TX_OK; ++ } ++ ++ debug_pkt(dev, "eth_xmit", skb->data, skb->len); ++ ++ len = skb->len; ++#ifdef __ARMEB__ ++ offset = 0; /* no need to keep alignment */ ++ bytes = len; ++ mem = skb->data; ++#else ++ offset = (int)skb->data & 3; /* keep 32-bit alignment */ ++ bytes = ALIGN(offset + len, 4); ++ if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { ++ dev_kfree_skb(skb); ++ port->stat.tx_dropped++; ++ return NETDEV_TX_OK; ++ } ++ memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); ++ dev_kfree_skb(skb); ++#endif ++ ++ phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); ++ if (dma_mapping_error(phys)) { ++#ifdef __ARMEB__ ++ dev_kfree_skb(skb); ++#else ++ kfree(mem); ++#endif ++ port->stat.tx_dropped++; ++ return NETDEV_TX_OK; ++ } ++ ++ n = queue_get_desc(txreadyq, port, 1); ++ BUG_ON(n < 0); ++ desc = tx_desc_ptr(port, n); ++ ++#ifdef __ARMEB__ ++ port->tx_buff_tab[n] = skb; ++#else ++ port->tx_buff_tab[n] = mem; ++#endif ++ desc->data = phys + offset; ++ desc->buf_len = desc->pkt_len = len; ++ ++ /* NPE firmware pads short frames with zeros internally */ ++ wmb(); ++ queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); ++ dev->trans_start = jiffies; ++ ++ if (qmgr_stat_empty(txreadyq)) { ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name); ++#endif ++ netif_stop_queue(dev); ++ /* we could miss TX ready interrupt */ ++ if (!qmgr_stat_empty(txreadyq)) { ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: eth_xmit ready again\n", ++ dev->name); ++#endif ++ netif_wake_queue(dev); ++ } ++ } ++ ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name); ++#endif ++ return NETDEV_TX_OK; ++} ++ ++ ++static struct net_device_stats *eth_stats(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ return &port->stat; ++} ++ ++static void eth_set_mcast_list(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ struct dev_mc_list *mclist = dev->mc_list; ++ u8 diffs[ETH_ALEN], *addr; ++ int cnt = dev->mc_count, i; ++ ++ if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) { ++ __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, ++ &port->regs->rx_control[0]); ++ return; ++ } ++ ++ memset(diffs, 0, ETH_ALEN); ++ addr = mclist->dmi_addr; /* first MAC address */ ++ ++ while (--cnt && (mclist = mclist->next)) ++ for (i = 0; i < ETH_ALEN; i++) ++ diffs[i] |= addr[i] ^ mclist->dmi_addr[i]; ++ ++ for (i = 0; i < ETH_ALEN; i++) { ++ __raw_writel(addr[i], &port->regs->mcast_addr[i]); ++ __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); ++ } ++ ++ __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, ++ &port->regs->rx_control[0]); ++} ++ ++ ++static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) ++{ ++ struct port *port = netdev_priv(dev); ++ unsigned int duplex_chg; ++ int err; ++ ++ if (!netif_running(dev)) ++ return -EINVAL; ++ err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg); ++ if (duplex_chg) ++ eth_set_duplex(port); ++ return err; ++} ++ ++ ++static int request_queues(struct port *port) ++{ ++ int err; ++ ++ err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0); ++ if (err) ++ return err; ++ ++ err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0); ++ if (err) ++ goto rel_rxfree; ++ ++ err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0); ++ if (err) ++ goto rel_rx; ++ ++ err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0); ++ if (err) ++ goto rel_tx; ++ ++ /* TX-done queue handles skbs sent out by the NPEs */ ++ if (!ports_open) { ++ err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0); ++ if (err) ++ goto rel_txready; ++ } ++ return 0; ++ ++rel_txready: ++ qmgr_release_queue(port->plat->txreadyq); ++rel_tx: ++ qmgr_release_queue(TX_QUEUE(port->id)); ++rel_rx: ++ qmgr_release_queue(port->plat->rxq); ++rel_rxfree: ++ qmgr_release_queue(RXFREE_QUEUE(port->id)); ++ printk(KERN_DEBUG "%s: unable to request hardware queues\n", ++ port->netdev->name); ++ return err; ++} ++ ++static void release_queues(struct port *port) ++{ ++ qmgr_release_queue(RXFREE_QUEUE(port->id)); ++ qmgr_release_queue(port->plat->rxq); ++ qmgr_release_queue(TX_QUEUE(port->id)); ++ qmgr_release_queue(port->plat->txreadyq); ++ ++ if (!ports_open) ++ qmgr_release_queue(TXDONE_QUEUE); ++} ++ ++static int init_queues(struct port *port) ++{ ++ int i; ++ ++ if (!ports_open) ++ if (!(dma_pool = dma_pool_create(DRV_NAME, NULL, ++ POOL_ALLOC_SIZE, 32, 0))) ++ return -ENOMEM; ++ ++ if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, ++ &port->desc_tab_phys))) ++ return -ENOMEM; ++ memset(port->desc_tab, 0, POOL_ALLOC_SIZE); ++ memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ ++ memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); ++ ++ /* Setup RX buffers */ ++ for (i = 0; i < RX_DESCS; i++) { ++ struct desc *desc = rx_desc_ptr(port, i); ++ buffer_t *buff; ++ void *data; ++#ifdef __ARMEB__ ++ if (!(buff = netdev_alloc_skb(port->netdev, MAX_MRU))) ++ return -ENOMEM; ++ data = buff->data; ++#else ++ if (!(buff = kmalloc(MAX_MRU, GFP_KERNEL))) ++ return -ENOMEM; ++ data = buff; ++#endif ++ desc->buf_len = MAX_MRU; ++ desc->data = dma_map_single(&port->netdev->dev, data, ++ MAX_MRU, DMA_FROM_DEVICE); ++ if (dma_mapping_error(desc->data)) { ++ free_buffer(buff); ++ return -EIO; ++ } ++ port->rx_buff_tab[i] = buff; ++ } ++ ++ return 0; ++} ++ ++static void destroy_queues(struct port *port) ++{ ++ int i; ++ ++ if (port->desc_tab) { ++ for (i = 0; i < RX_DESCS; i++) { ++ struct desc *desc = rx_desc_ptr(port, i); ++ buffer_t *buff = port->rx_buff_tab[i]; ++ if (buff) { ++ dma_unmap_single(&port->netdev->dev, ++ desc->data, MAX_MRU, ++ DMA_FROM_DEVICE); ++ free_buffer(buff); ++ } ++ } ++ for (i = 0; i < TX_DESCS; i++) { ++ struct desc *desc = tx_desc_ptr(port, i); ++ buffer_t *buff = port->tx_buff_tab[i]; ++ if (buff) { ++ dma_unmap_tx(port, desc); ++ free_buffer(buff); ++ } ++ } ++ dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); ++ port->desc_tab = NULL; ++ } ++ ++ if (!ports_open && dma_pool) { ++ dma_pool_destroy(dma_pool); ++ dma_pool = NULL; ++ } ++} ++ ++static int eth_open(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ struct npe *npe = port->npe; ++ struct msg msg; ++ int i, err; ++ ++ if (!npe_running(npe)) { ++ err = npe_load_firmware(npe, npe_name(npe), &dev->dev); ++ if (err) ++ return err; ++ ++ if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { ++ printk(KERN_ERR "%s: %s not responding\n", dev->name, ++ npe_name(npe)); ++ return -EIO; ++ } ++ } ++ ++ mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr); ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = NPE_VLAN_SETRXQOSENTRY; ++ msg.eth_id = port->id; ++ msg.byte5 = port->plat->rxq | 0x80; ++ msg.byte7 = port->plat->rxq << 4; ++ for (i = 0; i < 8; i++) { ++ msg.byte3 = i; ++ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) ++ return -EIO; ++ } ++ ++ msg.cmd = NPE_EDB_SETPORTADDRESS; ++ msg.eth_id = PHYSICAL_ID(port->id); ++ msg.byte2 = dev->dev_addr[0]; ++ msg.byte3 = dev->dev_addr[1]; ++ msg.byte4 = dev->dev_addr[2]; ++ msg.byte5 = dev->dev_addr[3]; ++ msg.byte6 = dev->dev_addr[4]; ++ msg.byte7 = dev->dev_addr[5]; ++ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) ++ return -EIO; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = NPE_FW_SETFIREWALLMODE; ++ msg.eth_id = port->id; ++ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) ++ return -EIO; ++ ++ if ((err = request_queues(port)) != 0) ++ return err; ++ ++ if ((err = init_queues(port)) != 0) { ++ destroy_queues(port); ++ release_queues(port); ++ return err; ++ } ++ ++ for (i = 0; i < ETH_ALEN; i++) ++ __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); ++ __raw_writel(0x08, &port->regs->random_seed); ++ __raw_writel(0x12, &port->regs->partial_empty_threshold); ++ __raw_writel(0x30, &port->regs->partial_full_threshold); ++ __raw_writel(0x08, &port->regs->tx_start_bytes); ++ __raw_writel(0x15, &port->regs->tx_deferral); ++ __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); ++ __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); ++ __raw_writel(0x80, &port->regs->slot_time); ++ __raw_writel(0x01, &port->regs->int_clock_threshold); ++ ++ /* Populate queues with buffers, no failure after this point */ ++ for (i = 0; i < TX_DESCS; i++) ++ queue_put_desc(port->plat->txreadyq, ++ tx_desc_phys(port, i), tx_desc_ptr(port, i)); ++ ++ for (i = 0; i < RX_DESCS; i++) ++ queue_put_desc(RXFREE_QUEUE(port->id), ++ rx_desc_phys(port, i), rx_desc_ptr(port, i)); ++ ++ __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); ++ __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); ++ __raw_writel(0, &port->regs->rx_control[1]); ++ __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); ++ ++ phy_check_media(port, 1); ++ eth_set_mcast_list(dev); ++ netif_start_queue(dev); ++ schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL); ++ ++ qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, ++ eth_rx_irq, dev); ++ if (!ports_open) { ++ qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, ++ eth_txdone_irq, NULL); ++ qmgr_enable_irq(TXDONE_QUEUE); ++ } ++ ports_open++; ++ netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */ ++ return 0; ++} ++ ++static int eth_close(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ struct msg msg; ++ int buffs = RX_DESCS; /* allocated RX buffers */ ++ int i; ++ ++ ports_open--; ++ qmgr_disable_irq(port->plat->rxq); ++ netif_stop_queue(dev); ++ ++ while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) ++ buffs--; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = NPE_SETLOOPBACK_MODE; ++ msg.eth_id = port->id; ++ msg.byte3 = 1; ++ if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) ++ printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name); ++ ++ i = 0; ++ do { /* drain RX buffers */ ++ while (queue_get_desc(port->plat->rxq, port, 0) >= 0) ++ buffs--; ++ if (!buffs) ++ break; ++ if (qmgr_stat_empty(TX_QUEUE(port->id))) { ++ /* we have to inject some packet */ ++ struct desc *desc; ++ u32 phys; ++ int n = queue_get_desc(port->plat->txreadyq, port, 1); ++ BUG_ON(n < 0); ++ desc = tx_desc_ptr(port, n); ++ phys = tx_desc_phys(port, n); ++ desc->buf_len = desc->pkt_len = 1; ++ wmb(); ++ queue_put_desc(TX_QUEUE(port->id), phys, desc); ++ } ++ udelay(1); ++ } while (++i < MAX_CLOSE_WAIT); ++ ++ if (buffs) ++ printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" ++ " left in NPE\n", dev->name, buffs); ++#if DEBUG_CLOSE ++ if (!buffs) ++ printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i); ++#endif ++ ++ buffs = TX_DESCS; ++ while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) ++ buffs--; /* cancel TX */ ++ ++ i = 0; ++ do { ++ while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) ++ buffs--; ++ if (!buffs) ++ break; ++ } while (++i < MAX_CLOSE_WAIT); ++ ++ if (buffs) ++ printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " ++ "left in NPE\n", dev->name, buffs); ++#if DEBUG_CLOSE ++ if (!buffs) ++ printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); ++#endif ++ ++ msg.byte3 = 0; ++ if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) ++ printk(KERN_CRIT "%s: unable to disable loopback\n", ++ dev->name); ++ ++ port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) & ++ ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */ ++ mdio_write(dev, port->plat->phy, MII_BMCR, ++ port->mii_bmcr | BMCR_PDOWN); ++ ++ if (!ports_open) ++ qmgr_disable_irq(TXDONE_QUEUE); ++ cancel_rearming_delayed_work(&port->mdio_thread); ++ destroy_queues(port); ++ release_queues(port); ++ return 0; ++} ++ ++static int __devinit eth_init_one(struct platform_device *pdev) ++{ ++ struct port *port; ++ struct net_device *dev; ++ struct eth_plat_info *plat = pdev->dev.platform_data; ++ u32 regs_phys; ++ int err; ++ ++ if (!(dev = alloc_etherdev(sizeof(struct port)))) ++ return -ENOMEM; ++ ++ SET_MODULE_OWNER(dev); ++ SET_NETDEV_DEV(dev, &pdev->dev); ++ port = netdev_priv(dev); ++ port->netdev = dev; ++ port->id = pdev->id; ++ ++ switch (port->id) { ++ case IXP4XX_ETH_NPEA: ++ port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT; ++ regs_phys = IXP4XX_EthA_BASE_PHYS; ++ break; ++ case IXP4XX_ETH_NPEB: ++ port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; ++ regs_phys = IXP4XX_EthB_BASE_PHYS; ++ break; ++ case IXP4XX_ETH_NPEC: ++ port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; ++ regs_phys = IXP4XX_EthC_BASE_PHYS; ++ break; ++ default: ++ err = -ENOSYS; ++ goto err_free; ++ } ++ ++ dev->open = eth_open; ++ dev->hard_start_xmit = eth_xmit; ++ dev->poll = eth_poll; ++ dev->stop = eth_close; ++ dev->get_stats = eth_stats; ++ dev->do_ioctl = eth_ioctl; ++ dev->set_multicast_list = eth_set_mcast_list; ++ dev->weight = 16; ++ dev->tx_queue_len = 100; ++ ++ if (!(port->npe = npe_request(NPE_ID(port->id)))) { ++ err = -EIO; ++ goto err_free; ++ } ++ ++ if (register_netdev(dev)) { ++ err = -EIO; ++ goto err_npe_rel; ++ } ++ ++ port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name); ++ if (!port->mem_res) { ++ err = -EBUSY; ++ goto err_unreg; ++ } ++ ++ port->plat = plat; ++ npe_port_tab[NPE_ID(port->id)] = port; ++ memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN); ++ ++ platform_set_drvdata(pdev, dev); ++ ++ __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, ++ &port->regs->core_control); ++ udelay(50); ++ __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); ++ udelay(50); ++ ++ port->mii.dev = dev; ++ port->mii.mdio_read = mdio_read; ++ port->mii.mdio_write = mdio_write; ++ port->mii.phy_id = plat->phy; ++ port->mii.phy_id_mask = 0x1F; ++ port->mii.reg_num_mask = 0x1F; ++ ++ printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, ++ npe_name(port->npe)); ++ ++ phy_reset(dev, plat->phy); ++ port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) & ++ ~(BMCR_RESET | BMCR_PDOWN); ++ mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN); ++ ++ INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread); ++ return 0; ++ ++err_unreg: ++ unregister_netdev(dev); ++err_npe_rel: ++ npe_release(port->npe); ++err_free: ++ free_netdev(dev); ++ return err; ++} ++ ++static int __devexit eth_remove_one(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct port *port = netdev_priv(dev); ++ ++ unregister_netdev(dev); ++ npe_port_tab[NPE_ID(port->id)] = NULL; ++ platform_set_drvdata(pdev, NULL); ++ npe_release(port->npe); ++ release_resource(port->mem_res); ++ free_netdev(dev); ++ return 0; ++} ++ ++static struct platform_driver drv = { ++ .driver.name = DRV_NAME, ++ .probe = eth_init_one, ++ .remove = eth_remove_one, ++}; ++ ++static int __init eth_init_module(void) ++{ ++ if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) ++ return -ENOSYS; ++ ++ /* All MII PHY accesses use NPE-B Ethernet registers */ ++ spin_lock_init(&mdio_lock); ++ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; ++ __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); ++ ++ return platform_driver_register(&drv); ++} ++ ++static void __exit eth_cleanup_module(void) ++{ ++ platform_driver_unregister(&drv); ++} ++ ++MODULE_AUTHOR("Krzysztof Halasa"); ++MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); ++MODULE_LICENSE("GPL v2"); ++module_init(eth_init_module); ++module_exit(eth_cleanup_module); +diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig +index a3df09e..94e7aa7 100644 +--- a/drivers/net/wan/Kconfig ++++ b/drivers/net/wan/Kconfig +@@ -334,6 +334,15 @@ config DSCC4_PCI_RST + + Say Y if your card supports this feature. + ++config IXP4XX_HSS ++ tristate "IXP4xx HSS (synchronous serial port) support" ++ depends on HDLC && ARM && ARCH_IXP4XX ++ select IXP4XX_NPE ++ select IXP4XX_QMGR ++ help ++ Say Y here if you want to use built-in HSS ports ++ on IXP4xx processor. ++ + config DLCI + tristate "Frame Relay DLCI support" + ---help--- +diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile +index d61fef3..1b1d116 100644 +--- a/drivers/net/wan/Makefile ++++ b/drivers/net/wan/Makefile +@@ -42,6 +42,7 @@ obj-$(CONFIG_C101) += c101.o + obj-$(CONFIG_WANXL) += wanxl.o + obj-$(CONFIG_PCI200SYN) += pci200syn.o + obj-$(CONFIG_PC300TOO) += pc300too.o ++obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o + + clean-files := wanxlfw.inc + $(obj)/wanxl.o: $(obj)/wanxlfw.inc +diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c +new file mode 100644 +index 0000000..c4cdace +--- /dev/null ++++ b/drivers/net/wan/ixp4xx_hss.c +@@ -0,0 +1,1270 @@ ++/* ++ * Intel IXP4xx HSS (synchronous serial port) driver for Linux ++ * ++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License ++ * as published by the Free Software Foundation. ++ */ ++ ++#include <linux/dma-mapping.h> ++#include <linux/dmapool.h> ++#include <linux/io.h> ++#include <linux/kernel.h> ++#include <linux/hdlc.h> ++#include <linux/platform_device.h> ++#include <asm/arch/npe.h> ++#include <asm/arch/qmgr.h> ++ ++#define DEBUG_QUEUES 0 ++#define DEBUG_DESC 0 ++#define DEBUG_RX 0 ++#define DEBUG_TX 0 ++#define DEBUG_PKT_BYTES 0 ++#define DEBUG_CLOSE 0 ++ ++#define DRV_NAME "ixp4xx_hss" ++ ++#define PKT_EXTRA_FLAGS 0 /* orig 1 */ ++#define FRAME_SYNC_OFFSET 0 /* unused, channelized only */ ++#define FRAME_SYNC_SIZE 1024 ++#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */ ++#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */ ++ ++#define RX_DESCS 16 /* also length of all RX queues */ ++#define TX_DESCS 16 /* also length of all TX queues */ ++ ++#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) ++#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */ ++#define MAX_CLOSE_WAIT 1000 /* microseconds */ ++ ++/* Queue IDs */ ++#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */ ++#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */ ++#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */ ++#define HSS0_PKT_TX1_QUEUE 15 ++#define HSS0_PKT_TX2_QUEUE 16 ++#define HSS0_PKT_TX3_QUEUE 17 ++#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */ ++#define HSS0_PKT_RXFREE1_QUEUE 19 ++#define HSS0_PKT_RXFREE2_QUEUE 20 ++#define HSS0_PKT_RXFREE3_QUEUE 21 ++#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */ ++ ++#define HSS1_CHL_RXTRIG_QUEUE 10 ++#define HSS1_PKT_RX_QUEUE 0 ++#define HSS1_PKT_TX0_QUEUE 5 ++#define HSS1_PKT_TX1_QUEUE 6 ++#define HSS1_PKT_TX2_QUEUE 7 ++#define HSS1_PKT_TX3_QUEUE 8 ++#define HSS1_PKT_RXFREE0_QUEUE 1 ++#define HSS1_PKT_RXFREE1_QUEUE 2 ++#define HSS1_PKT_RXFREE2_QUEUE 3 ++#define HSS1_PKT_RXFREE3_QUEUE 4 ++#define HSS1_PKT_TXDONE_QUEUE 9 ++ ++#define NPE_PKT_MODE_HDLC 0 ++#define NPE_PKT_MODE_RAW 1 ++#define NPE_PKT_MODE_56KMODE 2 ++#define NPE_PKT_MODE_56KENDIAN_MSB 4 ++ ++/* PKT_PIPE_HDLC_CFG_WRITE flags */ ++#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */ ++#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */ ++#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */ ++ ++ ++/* hss_config, PCRs */ ++/* Frame sync sampling, default = active low */ ++#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000 ++#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000 ++#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000 ++ ++/* Frame sync pin: input (default) or output generated off a given clk edge */ ++#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000 ++#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000 ++ ++/* Frame and data clock sampling on edge, default = falling */ ++#define PCR_FCLK_EDGE_RISING 0x08000000 ++#define PCR_DCLK_EDGE_RISING 0x04000000 ++ ++/* Clock direction, default = input */ ++#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000 ++ ++/* Generate/Receive frame pulses, default = enabled */ ++#define PCR_FRM_PULSE_DISABLED 0x01000000 ++ ++ /* Data rate is full (default) or half the configured clk speed */ ++#define PCR_HALF_CLK_RATE 0x00200000 ++ ++/* Invert data between NPE and HSS FIFOs? (default = no) */ ++#define PCR_DATA_POLARITY_INVERT 0x00100000 ++ ++/* TX/RX endianness, default = LSB */ ++#define PCR_MSB_ENDIAN 0x00080000 ++ ++/* Normal (default) / open drain mode (TX only) */ ++#define PCR_TX_PINS_OPEN_DRAIN 0x00040000 ++ ++/* No framing bit transmitted and expected on RX? (default = framing bit) */ ++#define PCR_SOF_NO_FBIT 0x00020000 ++ ++/* Drive data pins? */ ++#define PCR_TX_DATA_ENABLE 0x00010000 ++ ++/* Voice 56k type: drive the data pins low (default), high, high Z */ ++#define PCR_TX_V56K_HIGH 0x00002000 ++#define PCR_TX_V56K_HIGH_IMP 0x00004000 ++ ++/* Unassigned type: drive the data pins low (default), high, high Z */ ++#define PCR_TX_UNASS_HIGH 0x00000800 ++#define PCR_TX_UNASS_HIGH_IMP 0x00001000 ++ ++/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */ ++#define PCR_TX_FB_HIGH_IMP 0x00000400 ++ ++/* 56k data endiannes - which bit unused: high (default) or low */ ++#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200 ++ ++/* 56k data transmission type: 32/8 bit data (default) or 56K data */ ++#define PCR_TX_56KS_56K_DATA 0x00000100 ++ ++/* hss_config, cCR */ ++/* Number of packetized clients, default = 1 */ ++#define CCR_NPE_HFIFO_2_HDLC 0x04000000 ++#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000 ++ ++/* default = no loopback */ ++#define CCR_LOOPBACK 0x02000000 ++ ++/* HSS number, default = 0 (first) */ ++#define CCR_SECOND_HSS 0x01000000 ++ ++ ++/* hss_config, clkCR: main:10, num:10, denom:12 */ ++#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/ ++ ++#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15) ++#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47) ++#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192) ++#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63) ++#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127) ++#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255) ++ ++#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127) ++#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383) ++#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385) ++#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511) ++#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023) ++#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047) ++ ++ ++/* hss_config, LUT entries */ ++#define TDMMAP_UNASSIGNED 0 ++#define TDMMAP_HDLC 1 /* HDLC - packetized */ ++#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */ ++#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */ ++ ++#define TIMESLOTS 128 ++#define LUT_BITS 2 ++ ++/* offsets into HSS config */ ++#define HSS_CONFIG_TX_PCR 0x00 ++#define HSS_CONFIG_RX_PCR 0x04 ++#define HSS_CONFIG_CORE_CR 0x08 ++#define HSS_CONFIG_CLOCK_CR 0x0C ++#define HSS_CONFIG_TX_FCR 0x10 ++#define HSS_CONFIG_RX_FCR 0x14 ++#define HSS_CONFIG_TX_LUT 0x18 ++#define HSS_CONFIG_RX_LUT 0x38 ++ ++ ++/* NPE command codes */ ++/* writes the ConfigWord value to the location specified by offset */ ++#define PORT_CONFIG_WRITE 0x40 ++ ++/* triggers the NPE to load the contents of the configuration table */ ++#define PORT_CONFIG_LOAD 0x41 ++ ++/* triggers the NPE to return an HssErrorReadResponse message */ ++#define PORT_ERROR_READ 0x42 ++ ++/* reset NPE internal status and enable the HssChannelized operation */ ++#define CHAN_FLOW_ENABLE 0x43 ++#define CHAN_FLOW_DISABLE 0x44 ++#define CHAN_IDLE_PATTERN_WRITE 0x45 ++#define CHAN_NUM_CHANS_WRITE 0x46 ++#define CHAN_RX_BUF_ADDR_WRITE 0x47 ++#define CHAN_RX_BUF_CFG_WRITE 0x48 ++#define CHAN_TX_BLK_CFG_WRITE 0x49 ++#define CHAN_TX_BUF_ADDR_WRITE 0x4A ++#define CHAN_TX_BUF_SIZE_WRITE 0x4B ++#define CHAN_TSLOTSWITCH_ENABLE 0x4C ++#define CHAN_TSLOTSWITCH_DISABLE 0x4D ++ ++/* downloads the gainWord value for a timeslot switching channel associated ++ with bypassNum */ ++#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E ++ ++/* triggers the NPE to reset internal status and enable the HssPacketized ++ operation for the flow specified by pPipe */ ++#define PKT_PIPE_FLOW_ENABLE 0x50 ++#define PKT_PIPE_FLOW_DISABLE 0x51 ++#define PKT_NUM_PIPES_WRITE 0x52 ++#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53 ++#define PKT_PIPE_HDLC_CFG_WRITE 0x54 ++#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55 ++#define PKT_PIPE_RX_SIZE_WRITE 0x56 ++#define PKT_PIPE_MODE_WRITE 0x57 ++ ++/* HDLC packet status values - desc->status */ ++#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */ ++#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */ ++#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */ ++#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving ++ this packet (if buf_len < pkt_len) */ ++#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */ ++#define ERR_HDLC_ABORT 6 /* abort sequence received */ ++#define ERR_DISCONNECTING 7 /* disconnect is in progress */ ++ ++ ++#ifdef __ARMEB__ ++typedef struct sk_buff buffer_t; ++#define free_buffer dev_kfree_skb ++#define free_buffer_irq dev_kfree_skb_irq ++#else ++typedef void buffer_t; ++#define free_buffer kfree ++#define free_buffer_irq kfree ++#endif ++ ++struct port { ++ struct npe *npe; ++ struct net_device *netdev; ++ struct hss_plat_info *plat; ++ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; ++ struct desc *desc_tab; /* coherent */ ++ u32 desc_tab_phys; ++ int id; ++ unsigned int clock_type, clock_rate, loopback; ++ u8 hdlc_cfg; ++}; ++ ++/* NPE message structure */ ++struct msg { ++#ifdef __ARMEB__ ++ u8 cmd, unused, hss_port, index; ++ union { ++ struct { u8 data8a, data8b, data8c, data8d; }; ++ struct { u16 data16a, data16b; }; ++ struct { u32 data32; }; ++ }; ++#else ++ u8 index, hss_port, unused, cmd; ++ union { ++ struct { u8 data8d, data8c, data8b, data8a; }; ++ struct { u16 data16b, data16a; }; ++ struct { u32 data32; }; ++ }; ++#endif ++}; ++ ++/* HDLC packet descriptor */ ++struct desc { ++ u32 next; /* pointer to next buffer, unused */ ++ ++#ifdef __ARMEB__ ++ u16 buf_len; /* buffer length */ ++ u16 pkt_len; /* packet length */ ++ u32 data; /* pointer to data buffer in RAM */ ++ u8 status; ++ u8 error_count; ++ u16 __reserved; ++#else ++ u16 pkt_len; /* packet length */ ++ u16 buf_len; /* buffer length */ ++ u32 data; /* pointer to data buffer in RAM */ ++ u16 __reserved; ++ u8 error_count; ++ u8 status; ++#endif ++ u32 __reserved1[4]; ++}; ++ ++ ++#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ ++ (n) * sizeof(struct desc)) ++#define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) ++ ++#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ ++ ((n) + RX_DESCS) * sizeof(struct desc)) ++#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) ++ ++/***************************************************************************** ++ * global variables ++ ****************************************************************************/ ++ ++static int ports_open; ++static struct dma_pool *dma_pool; ++ ++static const struct { ++ int tx, txdone, rx, rxfree; ++}queue_ids[2] = {{ HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, ++ HSS0_PKT_RX_QUEUE, HSS0_PKT_RXFREE0_QUEUE }, ++ { HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, ++ HSS1_PKT_RX_QUEUE, HSS1_PKT_RXFREE0_QUEUE }, ++}; ++ ++/***************************************************************************** ++ * utility functions ++ ****************************************************************************/ ++ ++static inline struct port* dev_to_port(struct net_device *dev) ++{ ++ return dev_to_hdlc(dev)->priv; ++} ++ ++#ifndef __ARMEB__ ++static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) ++{ ++ int i; ++ for (i = 0; i < cnt; i++) ++ dest[i] = swab32(src[i]); ++} ++#endif ++ ++static inline void debug_pkt(struct net_device *dev, const char *func, ++ u8 *data, int len) ++{ ++#if DEBUG_PKT_BYTES ++ int i; ++ ++ printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len); ++ for (i = 0; i < len; i++) { ++ if (i >= DEBUG_PKT_BYTES) ++ break; ++ printk("%s%02X", !(i % 4) ? " " : "", data[i]); ++ } ++ printk("\n"); ++#endif ++} ++ ++ ++static inline void debug_desc(u32 phys, struct desc *desc) ++{ ++#if DEBUG_DESC ++ printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n", ++ phys, desc->next, desc->buf_len, desc->pkt_len, ++ desc->data, desc->status, desc->error_count); ++#endif ++} ++ ++static inline void debug_queue(unsigned int queue, int is_get, u32 phys) ++{ ++#if DEBUG_QUEUES ++ static struct { ++ int queue; ++ char *name; ++ } names[] = { ++ { HSS0_PKT_TX0_QUEUE, "TX#0 " }, ++ { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " }, ++ { HSS0_PKT_RX_QUEUE, "RX#0 " }, ++ { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " }, ++ { HSS1_PKT_TX0_QUEUE, "TX#1 " }, ++ { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " }, ++ { HSS1_PKT_RX_QUEUE, "RX#1 " }, ++ { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " }, ++ }; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(names); i++) ++ if (names[i].queue == queue) ++ break; ++ ++ printk(KERN_DEBUG "Queue %i %s%s %X\n", queue, ++ i < ARRAY_SIZE(names) ? names[i].name : "", ++ is_get ? "->" : "<-", phys); ++#endif ++} ++ ++static inline u32 queue_get_entry(unsigned int queue) ++{ ++ u32 phys = qmgr_get_entry(queue); ++ debug_queue(queue, 1, phys); ++ return phys; ++} ++ ++static inline int queue_get_desc(unsigned int queue, struct port *port, ++ int is_tx) ++{ ++ u32 phys, tab_phys, n_desc; ++ struct desc *tab; ++ ++ if (!(phys = queue_get_entry(queue))) ++ return -1; ++ ++ BUG_ON(phys & 0x1F); ++ tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); ++ tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); ++ n_desc = (phys - tab_phys) / sizeof(struct desc); ++ BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); ++ debug_desc(phys, &tab[n_desc]); ++ BUG_ON(tab[n_desc].next); ++ return n_desc; ++} ++ ++static inline void queue_put_desc(unsigned int queue, u32 phys, ++ struct desc *desc) ++{ ++ debug_queue(queue, 0, phys); ++ debug_desc(phys, desc); ++ BUG_ON(phys & 0x1F); ++ qmgr_put_entry(queue, phys); ++ BUG_ON(qmgr_stat_overflow(queue)); ++} ++ ++ ++static inline void dma_unmap_tx(struct port *port, struct desc *desc) ++{ ++#ifdef __ARMEB__ ++ dma_unmap_single(&port->netdev->dev, desc->data, ++ desc->buf_len, DMA_TO_DEVICE); ++#else ++ dma_unmap_single(&port->netdev->dev, desc->data & ~3, ++ ALIGN((desc->data & 3) + desc->buf_len, 4), ++ DMA_TO_DEVICE); ++#endif ++} ++ ++ ++static void hss_hdlc_set_carrier(void *pdev, int carrier) ++{ ++ struct net_device *dev = pdev; ++ if (carrier) ++ netif_carrier_on(dev); ++ else ++ netif_carrier_off(dev); ++} ++ ++static void hss_hdlc_rx_irq(void *pdev) ++{ ++ struct net_device *dev = pdev; ++ struct port *port = dev_to_port(dev); ++ ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name); ++#endif ++ qmgr_disable_irq(queue_ids[port->id].rx); ++ netif_rx_schedule(dev); ++} ++ ++static int hss_hdlc_poll(struct net_device *dev, int *budget) ++{ ++ struct port *port = dev_to_port(dev); ++ unsigned int rxq = queue_ids[port->id].rx; ++ unsigned int rxfreeq = queue_ids[port->id].rxfree; ++ struct net_device_stats *stats = hdlc_stats(dev); ++ int quota = dev->quota, received = 0; ++ ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name); ++#endif ++ ++ while (quota) { ++ struct sk_buff *skb; ++ struct desc *desc; ++ int n; ++#ifdef __ARMEB__ ++ struct sk_buff *temp; ++ u32 phys; ++#endif ++ ++ if ((n = queue_get_desc(rxq, port, 0)) < 0) { ++ dev->quota -= received; /* No packet received */ ++ *budget -= received; ++ received = 0; ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: hss_hdlc_poll" ++ " netif_rx_complete\n", dev->name); ++#endif ++ netif_rx_complete(dev); ++ qmgr_enable_irq(rxq); ++ if (!qmgr_stat_empty(rxq) && ++ netif_rx_reschedule(dev, 0)) { ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: hss_hdlc_poll" ++ " netif_rx_reschedule successed\n", ++ dev->name); ++#endif ++ qmgr_disable_irq(rxq); ++ continue; ++ } ++#if DEBUG_RX ++ printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n", ++ dev->name); ++#endif ++ return 0; /* all work done */ ++ } ++ ++ desc = rx_desc_ptr(port, n); ++ ++ if (desc->error_count) /* FIXME - remove printk */ ++ printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X" ++ " errors %u\n", dev->name, desc->status, ++ desc->error_count); ++ ++ skb = NULL; ++ switch (desc->status) { ++ case 0: ++#ifdef __ARMEB__ ++ if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) { ++ phys = dma_map_single(&dev->dev, skb->data, ++ RX_SIZE, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(phys)) { ++ dev_kfree_skb(skb); ++ skb = NULL; ++ } ++ } ++#else ++ skb = netdev_alloc_skb(dev, desc->pkt_len); ++#endif ++ if (!skb) ++ stats->rx_dropped++; ++ break; ++ case ERR_HDLC_ALIGN: ++ case ERR_HDLC_ABORT: ++ stats->rx_frame_errors++; ++ stats->rx_errors++; ++ break; ++ case ERR_HDLC_FCS: ++ stats->rx_crc_errors++; ++ stats->rx_errors++; ++ break; ++ case ERR_HDLC_TOO_LONG: ++ stats->rx_length_errors++; ++ stats->rx_errors++; ++ break; ++ default: /* FIXME - remove printk */ ++ printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X" ++ " errors %u\n", dev->name, desc->status, ++ desc->error_count); ++ stats->rx_errors++; ++ } ++ ++ if (!skb) { ++ /* put the desc back on RX-ready queue */ ++ desc->buf_len = RX_SIZE; ++ desc->pkt_len = desc->status = 0; ++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); ++ continue; ++ } ++ ++ /* process received frame */ ++#ifdef __ARMEB__ ++ temp = skb; ++ skb = port->rx_buff_tab[n]; ++ dma_unmap_single(&dev->dev, desc->data, ++ RX_SIZE, DMA_FROM_DEVICE); ++#else ++ dma_sync_single(&dev->dev, desc->data, ++ RX_SIZE, DMA_FROM_DEVICE); ++ memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], ++ ALIGN(desc->pkt_len, 4) / 4); ++#endif ++ skb_put(skb, desc->pkt_len); ++ ++ debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len); ++ ++ skb->protocol = hdlc_type_trans(skb, dev); ++ dev->last_rx = jiffies; ++ stats->rx_packets++; ++ stats->rx_bytes += skb->len; ++ netif_receive_skb(skb); ++ ++ /* put the new buffer on RX-free queue */ ++#ifdef __ARMEB__ ++ port->rx_buff_tab[n] = temp; ++ desc->data = phys; ++#endif ++ desc->buf_len = RX_SIZE; ++ desc->pkt_len = 0; ++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); ++ quota--; ++ received++; ++ } ++ dev->quota -= received; ++ *budget -= received; ++#if DEBUG_RX ++ printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n"); ++#endif ++ return 1; /* not all work done */ ++} ++ ++ ++static void hss_hdlc_txdone_irq(void *pdev) ++{ ++ struct net_device *dev = pdev; ++ struct port *port = dev_to_port(dev); ++ struct net_device_stats *stats = hdlc_stats(dev); ++ int n_desc; ++ ++#if DEBUG_TX ++ printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n"); ++#endif ++ while ((n_desc = queue_get_desc(queue_ids[port->id].txdone, ++ port, 1)) >= 0) { ++ struct desc *desc; ++ int start; ++ ++ desc = tx_desc_ptr(port, n_desc); ++ ++ stats->tx_packets++; ++ stats->tx_bytes += desc->pkt_len; ++ ++ dma_unmap_tx(port, desc); ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n", ++ port->netdev->name, port->tx_buff_tab[n_desc]); ++#endif ++ free_buffer_irq(port->tx_buff_tab[n_desc]); ++ port->tx_buff_tab[n_desc] = NULL; ++ ++ start = qmgr_stat_empty(port->plat->txreadyq); ++ queue_put_desc(port->plat->txreadyq, ++ tx_desc_phys(port, n_desc), desc); ++ if (start) { ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit" ++ " ready\n", port->netdev->name); ++#endif ++ netif_wake_queue(port->netdev); ++ } ++ } ++} ++ ++static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct port *port = dev_to_port(dev); ++ struct net_device_stats *stats = hdlc_stats(dev); ++ unsigned int txreadyq = port->plat->txreadyq; ++ int len, offset, bytes, n; ++ void *mem; ++ u32 phys; ++ struct desc *desc; ++ ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name); ++#endif ++ ++ if (unlikely(skb->len > HDLC_MAX_MRU)) { ++ dev_kfree_skb(skb); ++ stats->tx_errors++; ++ return NETDEV_TX_OK; ++ } ++ ++ debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len); ++ ++ len = skb->len; ++#ifdef __ARMEB__ ++ offset = 0; /* no need to keep alignment */ ++ bytes = len; ++ mem = skb->data; ++#else ++ offset = (int)skb->data & 3; /* keep 32-bit alignment */ ++ bytes = ALIGN(offset + len, 4); ++ if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { ++ dev_kfree_skb(skb); ++ stats->tx_dropped++; ++ return NETDEV_TX_OK; ++ } ++ memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); ++ dev_kfree_skb(skb); ++#endif ++ ++ phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); ++ if (dma_mapping_error(phys)) { ++#ifdef __ARMEB__ ++ dev_kfree_skb(skb); ++#else ++ kfree(mem); ++#endif ++ stats->tx_dropped++; ++ return NETDEV_TX_OK; ++ } ++ ++ n = queue_get_desc(txreadyq, port, 1); ++ BUG_ON(n < 0); ++ desc = tx_desc_ptr(port, n); ++ ++#ifdef __ARMEB__ ++ port->tx_buff_tab[n] = skb; ++#else ++ port->tx_buff_tab[n] = mem; ++#endif ++ desc->data = phys + offset; ++ desc->buf_len = desc->pkt_len = len; ++ ++ wmb(); ++ queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc); ++ dev->trans_start = jiffies; ++ ++ if (qmgr_stat_empty(txreadyq)) { ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name); ++#endif ++ netif_stop_queue(dev); ++ /* we could miss TX ready interrupt */ ++ if (!qmgr_stat_empty(txreadyq)) { ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n", ++ dev->name); ++#endif ++ netif_wake_queue(dev); ++ } ++ } ++ ++#if DEBUG_TX ++ printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name); ++#endif ++ return NETDEV_TX_OK; ++} ++ ++ ++static int request_hdlc_queues(struct port *port) ++{ ++ int err; ++ ++ err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0); ++ if (err) ++ return err; ++ ++ err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0); ++ if (err) ++ goto rel_rxfree; ++ ++ err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0); ++ if (err) ++ goto rel_rx; ++ ++ err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0); ++ if (err) ++ goto rel_tx; ++ ++ err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0); ++ if (err) ++ goto rel_txready; ++ return 0; ++ ++rel_txready: ++ qmgr_release_queue(port->plat->txreadyq); ++rel_tx: ++ qmgr_release_queue(queue_ids[port->id].tx); ++rel_rx: ++ qmgr_release_queue(queue_ids[port->id].rx); ++rel_rxfree: ++ qmgr_release_queue(queue_ids[port->id].rxfree); ++ printk(KERN_DEBUG "%s: unable to request hardware queues\n", ++ port->netdev->name); ++ return err; ++} ++ ++static void release_hdlc_queues(struct port *port) ++{ ++ qmgr_release_queue(queue_ids[port->id].rxfree); ++ qmgr_release_queue(queue_ids[port->id].rx); ++ qmgr_release_queue(queue_ids[port->id].txdone); ++ qmgr_release_queue(queue_ids[port->id].tx); ++ qmgr_release_queue(port->plat->txreadyq); ++} ++ ++static int init_hdlc_queues(struct port *port) ++{ ++ int i; ++ ++ if (!ports_open) ++ if (!(dma_pool = dma_pool_create(DRV_NAME, NULL, ++ POOL_ALLOC_SIZE, 32, 0))) ++ return -ENOMEM; ++ ++ if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, ++ &port->desc_tab_phys))) ++ return -ENOMEM; ++ memset(port->desc_tab, 0, POOL_ALLOC_SIZE); ++ memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ ++ memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); ++ ++ /* Setup RX buffers */ ++ for (i = 0; i < RX_DESCS; i++) { ++ struct desc *desc = rx_desc_ptr(port, i); ++ buffer_t *buff; ++ void *data; ++#ifdef __ARMEB__ ++ if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE))) ++ return -ENOMEM; ++ data = buff->data; ++#else ++ if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL))) ++ return -ENOMEM; ++ data = buff; ++#endif ++ desc->buf_len = RX_SIZE; ++ desc->data = dma_map_single(&port->netdev->dev, data, ++ RX_SIZE, DMA_FROM_DEVICE); ++ if (dma_mapping_error(desc->data)) { ++ free_buffer(buff); ++ return -EIO; ++ } ++ port->rx_buff_tab[i] = buff; ++ } ++ ++ return 0; ++} ++ ++static void destroy_hdlc_queues(struct port *port) ++{ ++ int i; ++ ++ if (port->desc_tab) { ++ for (i = 0; i < RX_DESCS; i++) { ++ struct desc *desc = rx_desc_ptr(port, i); ++ buffer_t *buff = port->rx_buff_tab[i]; ++ if (buff) { ++ dma_unmap_single(&port->netdev->dev, ++ desc->data, RX_SIZE, ++ DMA_FROM_DEVICE); ++ free_buffer(buff); ++ } ++ } ++ for (i = 0; i < TX_DESCS; i++) { ++ struct desc *desc = tx_desc_ptr(port, i); ++ buffer_t *buff = port->tx_buff_tab[i]; ++ if (buff) { ++ dma_unmap_tx(port, desc); ++ free_buffer(buff); ++ } ++ } ++ dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); ++ port->desc_tab = NULL; ++ } ++ ++ if (!ports_open && dma_pool) { ++ dma_pool_destroy(dma_pool); ++ dma_pool = NULL; ++ } ++} ++ ++static int hss_hdlc_open(struct net_device *dev) ++{ ++ struct port *port = dev_to_port(dev); ++ struct npe *npe = port->npe; ++ struct msg msg; ++ int i, err; ++ ++ if (!npe_running(npe)) { ++ err = npe_load_firmware(npe, npe_name(npe), &dev->dev); ++ if (err) ++ return err; ++ } ++ ++ if ((err = hdlc_open(dev)) != 0) ++ return err; ++ ++ if (port->plat->open) ++ if ((err = port->plat->open(port->id, port->netdev, ++ hss_hdlc_set_carrier)) != 0) ++ goto err_hdlc_close; ++ ++ /* HSS main configuration */ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = 0; /* offset in HSS config */ ++ ++ msg.data32 = PCR_FRM_PULSE_DISABLED | ++ PCR_SOF_NO_FBIT | ++ PCR_MSB_ENDIAN | ++ PCR_TX_DATA_ENABLE; ++ ++ if (port->clock_type == CLOCK_INT) ++ msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT; ++ ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_PCR") != 0)) ++ goto err_plat_close; /* 0: TX PCR */ ++ ++ msg.index = 4; ++ msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING; ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_PCR") != 0)) ++ goto err_plat_close; /* 4: RX PCR */ ++ ++ msg.index = 8; ++ msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) | ++ (port->id ? CCR_SECOND_HSS : 0); ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_CORE_CR") != 0)) ++ goto err_plat_close; /* 8: Core CR */ ++ ++ msg.index = 12; ++ msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */; ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_CLK_CR") != 0)) ++ goto err_plat_close; /* 12: CLK CR */ ++ ++ msg.data32 = (FRAME_SYNC_OFFSET << 16) | (FRAME_SYNC_SIZE - 1); ++ msg.index = 16; ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_FCR") != 0)) ++ goto err_plat_close; /* 16: TX FCR */ ++ ++ msg.index = 20; ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_FCR") != 0)) ++ goto err_plat_close; /* 20: RX FCR */ ++ ++ msg.data32 = 0; /* Fill LUT with HDLC timeslots */ ++ for (i = 0; i < 32 / LUT_BITS; i++) ++ msg.data32 |= TDMMAP_HDLC << (LUT_BITS * i); ++ ++ for (i = 0; i < 2 /* TX and RX */ * TIMESLOTS * LUT_BITS / 8; i += 4) { ++ msg.index = 24 + i; /* 24 - 55: TX LUT, 56 - 87: RX LUT */ ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_LUT") != 0)) ++ goto err_plat_close; ++ } ++ ++ /* HDLC mode configuration */ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PKT_NUM_PIPES_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = PKT_NUM_PIPES; ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_PIPES") != 0)) ++ goto err_plat_close; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = PKT_PIPE_FIFO_SIZEW; ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_FIFO") != 0)) ++ goto err_plat_close; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE; ++ msg.hss_port = port->id; ++ msg.data32 = 0x7F7F7F7F; ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_IDLE") != 0)) ++ goto err_plat_close; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_LOAD; ++ msg.hss_port = port->id; ++ if ((err = npe_send_message(npe, &msg, "HSS_LOAD_CONFIG") != 0)) ++ goto err_plat_close; ++ if ((err = npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG") != 0)) ++ goto err_plat_close; ++ ++ /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */ ++ if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) { ++ printk(KERN_DEBUG "%s: unexpected message received in" ++ " response to HSS_LOAD_CONFIG\n", npe_name(npe)); ++ err = EIO; ++ goto err_plat_close; ++ } ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PKT_PIPE_HDLC_CFG_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = port->hdlc_cfg; /* rx_cfg */ ++ msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */ ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_HDLC_CFG") != 0)) ++ goto err_plat_close; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PKT_PIPE_MODE_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = NPE_PKT_MODE_HDLC; ++ /* msg.data8b = inv_mask */ ++ /* msg.data8c = or_mask */ ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_MODE") != 0)) ++ goto err_plat_close; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PKT_PIPE_RX_SIZE_WRITE; ++ msg.hss_port = port->id; ++ msg.data16a = HDLC_MAX_MRU; ++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_RX_SIZE") != 0)) ++ goto err_plat_close; ++ ++ if ((err = request_hdlc_queues(port)) != 0) ++ goto err_plat_close; ++ ++ if ((err = init_hdlc_queues(port)) != 0) ++ goto err_destroy_queues; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PKT_PIPE_FLOW_ENABLE; ++ msg.hss_port = port->id; ++ if ((err = npe_send_message(npe, &msg, "HSS_ENABLE_PKT_PIPE") != 0)) ++ goto err_destroy_queues; ++ ++ /* Populate queues with buffers, no failure after this point */ ++ for (i = 0; i < TX_DESCS; i++) ++ queue_put_desc(port->plat->txreadyq, ++ tx_desc_phys(port, i), tx_desc_ptr(port, i)); ++ ++ for (i = 0; i < RX_DESCS; i++) ++ queue_put_desc(queue_ids[port->id].rxfree, ++ rx_desc_phys(port, i), rx_desc_ptr(port, i)); ++ ++ netif_start_queue(dev); ++ ++ qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY, ++ hss_hdlc_rx_irq, dev); ++ ++ qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY, ++ hss_hdlc_txdone_irq, dev); ++ qmgr_enable_irq(queue_ids[port->id].txdone); ++ ++ ports_open++; ++ netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */ ++ return 0; ++ ++err_destroy_queues: ++ destroy_hdlc_queues(port); ++ release_hdlc_queues(port); ++err_plat_close: ++ if (port->plat->close) ++ port->plat->close(port->id, port->netdev); ++err_hdlc_close: ++ hdlc_close(dev); ++ return err; ++} ++ ++static int hss_hdlc_close(struct net_device *dev) ++{ ++ struct port *port = dev_to_port(dev); ++ struct npe *npe = port->npe; ++ struct msg msg; ++ int buffs = RX_DESCS; /* allocated RX buffers */ ++ int i; ++ ++ ports_open--; ++ qmgr_disable_irq(queue_ids[port->id].rx); ++ netif_stop_queue(dev); ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PKT_PIPE_FLOW_DISABLE; ++ msg.hss_port = port->id; ++ if (npe_send_message(npe, &msg, "HSS_DISABLE_PKT_PIPE")) { ++ printk(KERN_CRIT "HSS-%i: unable to stop HDLC flow\n", ++ port->id); ++ /* The upper level would ignore the error anyway */ ++ } ++ ++ while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0) ++ buffs--; ++ while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0) ++ buffs--; ++ ++ if (buffs) ++ printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" ++ " left in NPE\n", dev->name, buffs); ++ ++ buffs = TX_DESCS; ++ while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0) ++ buffs--; /* cancel TX */ ++ ++ i = 0; ++ do { ++ while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) ++ buffs--; ++ if (!buffs) ++ break; ++ } while (++i < MAX_CLOSE_WAIT); ++ ++ if (buffs) ++ printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " ++ "left in NPE\n", dev->name, buffs); ++#if DEBUG_CLOSE ++ if (!buffs) ++ printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); ++#endif ++ qmgr_disable_irq(queue_ids[port->id].txdone); ++ destroy_hdlc_queues(port); ++ release_hdlc_queues(port); ++ ++ if (port->plat->close) ++ port->plat->close(port->id, port->netdev); ++ hdlc_close(dev); ++ return 0; ++} ++ ++ ++static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding, ++ unsigned short parity) ++{ ++ struct port *port = dev_to_port(dev); ++ ++ if (encoding != ENCODING_NRZ) ++ return -EINVAL; ++ ++ switch(parity) { ++ case PARITY_CRC16_PR1_CCITT: ++ port->hdlc_cfg = 0; ++ return 0; ++ ++ case PARITY_CRC32_PR1_CCITT: ++ port->hdlc_cfg = PKT_HDLC_CRC_32; ++ return 0; ++ ++ default: ++ return -EINVAL; ++ } ++} ++ ++ ++static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ const size_t size = sizeof(sync_serial_settings); ++ sync_serial_settings new_line; ++ int clk; ++ sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; ++ struct port *port = dev_to_port(dev); ++ ++ if (cmd != SIOCWANDEV) ++ return hdlc_ioctl(dev, ifr, cmd); ++ ++ switch(ifr->ifr_settings.type) { ++ case IF_GET_IFACE: ++ ifr->ifr_settings.type = IF_IFACE_V35; ++ if (ifr->ifr_settings.size < size) { ++ ifr->ifr_settings.size = size; /* data size wanted */ ++ return -ENOBUFS; ++ } ++ memset(&new_line, 0, sizeof(new_line)); ++ new_line.clock_type = port->clock_type; ++ new_line.clock_rate = port->clock_rate; ++ new_line.loopback = port->loopback; ++ if (copy_to_user(line, &new_line, size)) ++ return -EFAULT; ++ return 0; ++ ++ case IF_IFACE_SYNC_SERIAL: ++ case IF_IFACE_V35: ++ if(!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ if (dev->flags & IFF_UP) ++ return -EBUSY; /* Cannot change parameters when open */ ++ ++ if (copy_from_user(&new_line, line, size)) ++ return -EFAULT; ++ ++ clk = new_line.clock_type; ++ if (port->plat->set_clock) ++ clk = port->plat->set_clock(port->id, clk); ++ ++ if (clk != CLOCK_EXT && clk != CLOCK_INT) ++ return -EINVAL; /* No such clock setting */ ++ ++ if (new_line.loopback != 0 && new_line.loopback != 1) ++ return -EINVAL; ++ ++ port->clock_type = clk; /* Update settings */ ++ port->clock_rate = new_line.clock_rate; ++ port->loopback = new_line.loopback; ++ return 0; ++ ++ default: ++ return hdlc_ioctl(dev, ifr, cmd); ++ } ++} ++ ++ ++static int __devinit hss_init_one(struct platform_device *pdev) ++{ ++ struct port *port; ++ struct net_device *dev; ++ hdlc_device *hdlc; ++ int err; ++ ++ if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL) ++ return -ENOMEM; ++ platform_set_drvdata(pdev, port); ++ port->id = pdev->id; ++ ++ if ((port->npe = npe_request(0)) == NULL) { ++ err = -ENOSYS; ++ goto err_free; ++ } ++ ++ port->plat = pdev->dev.platform_data; ++ if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) { ++ err = -ENOMEM; ++ goto err_plat; ++ } ++ ++ SET_MODULE_OWNER(net); ++ SET_NETDEV_DEV(dev, &pdev->dev); ++ hdlc = dev_to_hdlc(dev); ++ hdlc->attach = hss_hdlc_attach; ++ hdlc->xmit = hss_hdlc_xmit; ++ dev->open = hss_hdlc_open; ++ dev->poll = hss_hdlc_poll; ++ dev->stop = hss_hdlc_close; ++ dev->do_ioctl = hss_hdlc_ioctl; ++ dev->weight = 16; ++ dev->tx_queue_len = 100; ++ port->clock_type = CLOCK_EXT; ++ port->clock_rate = 2048000; ++ ++ if (register_hdlc_device(dev)) { ++ printk(KERN_ERR "HSS-%i: unable to register HDLC device\n", ++ port->id); ++ err = -ENOBUFS; ++ goto err_free_netdev; ++ } ++ printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id); ++ return 0; ++ ++err_free_netdev: ++ free_netdev(dev); ++err_plat: ++ npe_release(port->npe); ++ platform_set_drvdata(pdev, NULL); ++err_free: ++ kfree(port); ++ return err; ++} ++ ++static int __devexit hss_remove_one(struct platform_device *pdev) ++{ ++ struct port *port = platform_get_drvdata(pdev); ++ ++ unregister_hdlc_device(port->netdev); ++ free_netdev(port->netdev); ++ npe_release(port->npe); ++ platform_set_drvdata(pdev, NULL); ++ kfree(port); ++ return 0; ++} ++ ++static struct platform_driver drv = { ++ .driver.name = DRV_NAME, ++ .probe = hss_init_one, ++ .remove = hss_remove_one, ++}; ++ ++static int __init hss_init_module(void) ++{ ++ if ((ixp4xx_read_feature_bits() & ++ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) != ++ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) ++ return -ENOSYS; ++ return platform_driver_register(&drv); ++} ++ ++static void __exit hss_cleanup_module(void) ++{ ++ platform_driver_unregister(&drv); ++} ++ ++MODULE_AUTHOR("Krzysztof Halasa"); ++MODULE_DESCRIPTION("Intel IXP4xx HSS driver"); ++MODULE_LICENSE("GPL v2"); ++module_init(hss_init_module); ++module_exit(hss_cleanup_module); +diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h +index d2523b3..2fa3d6b 100644 +--- a/include/asm-arm/arch-ixp4xx/cpu.h ++++ b/include/asm-arm/arch-ixp4xx/cpu.h +@@ -28,4 +28,19 @@ extern unsigned int processor_id; + #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ + IXP465_PROCESSOR_ID_VALUE) + ++static inline u32 ixp4xx_read_feature_bits(void) ++{ ++ unsigned int val = ~*IXP4XX_EXP_CFG2; ++ val &= ~IXP4XX_FEATURE_RESERVED; ++ if (!cpu_is_ixp46x()) ++ val &= ~IXP4XX_FEATURE_IXP46X_ONLY; ++ ++ return val; ++} ++ ++static inline void ixp4xx_write_feature_bits(u32 value) ++{ ++ *IXP4XX_EXP_CFG2 = ~value; ++} ++ + #endif /* _ASM_ARCH_CPU_H */ +diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h +index 297ceda..73e8dc3 100644 +--- a/include/asm-arm/arch-ixp4xx/hardware.h ++++ b/include/asm-arm/arch-ixp4xx/hardware.h +@@ -27,13 +27,13 @@ + + #define pcibios_assign_all_busses() 1 + ++/* Register locations and bits */ ++#include "ixp4xx-regs.h" ++ + #ifndef __ASSEMBLER__ + #include <asm/arch/cpu.h> + #endif + +-/* Register locations and bits */ +-#include "ixp4xx-regs.h" +- + /* Platform helper functions and definitions */ + #include "platform.h" + +diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +index 5d949d7..c704fe8 100644 +--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h ++++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +@@ -15,10 +15,6 @@ + * + */ + +-#ifndef __ASM_ARCH_HARDWARE_H__ +-#error "Do not include this directly, instead #include <asm/hardware.h>" +-#endif +- + #ifndef _ASM_ARM_IXP4XX_H_ + #define _ASM_ARM_IXP4XX_H_ + +@@ -607,4 +603,36 @@ + + #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ + ++/* "fuse" bits of IXP_EXP_CFG2 */ ++#define IXP4XX_FEATURE_RCOMP (1 << 0) ++#define IXP4XX_FEATURE_USB_DEVICE (1 << 1) ++#define IXP4XX_FEATURE_HASH (1 << 2) ++#define IXP4XX_FEATURE_AES (1 << 3) ++#define IXP4XX_FEATURE_DES (1 << 4) ++#define IXP4XX_FEATURE_HDLC (1 << 5) ++#define IXP4XX_FEATURE_AAL (1 << 6) ++#define IXP4XX_FEATURE_HSS (1 << 7) ++#define IXP4XX_FEATURE_UTOPIA (1 << 8) ++#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9) ++#define IXP4XX_FEATURE_NPEC_ETH (1 << 10) ++#define IXP4XX_FEATURE_RESET_NPEA (1 << 11) ++#define IXP4XX_FEATURE_RESET_NPEB (1 << 12) ++#define IXP4XX_FEATURE_RESET_NPEC (1 << 13) ++#define IXP4XX_FEATURE_PCI (1 << 14) ++#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) ++#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) ++#define IXP4XX_FEATURE_USB_HOST (1 << 18) ++#define IXP4XX_FEATURE_NPEA_ETH (1 << 19) ++#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) ++#define IXP4XX_FEATURE_RSA (1 << 21) ++#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) ++#define IXP4XX_FEATURE_RESERVED (0xFF << 24) ++ ++#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ ++ IXP4XX_FEATURE_USB_HOST | \ ++ IXP4XX_FEATURE_NPEA_ETH | \ ++ IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ ++ IXP4XX_FEATURE_RSA | \ ++ IXP4XX_FEATURE_XSCALE_MAX_FREQ) ++ + #endif +diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h +new file mode 100644 +index 0000000..37d0511 +--- /dev/null ++++ b/include/asm-arm/arch-ixp4xx/npe.h +@@ -0,0 +1,39 @@ ++#ifndef __IXP4XX_NPE_H ++#define __IXP4XX_NPE_H ++ ++#include <linux/kernel.h> ++ ++extern const char *npe_names[]; ++ ++struct npe_regs { ++ u32 exec_addr, exec_data, exec_status_cmd, exec_count; ++ u32 action_points[4]; ++ u32 watchpoint_fifo, watch_count; ++ u32 profile_count; ++ u32 messaging_status, messaging_control; ++ u32 mailbox_status, /*messaging_*/ in_out_fifo; ++}; ++ ++struct npe { ++ struct resource *mem_res; ++ struct npe_regs __iomem *regs; ++ u32 regs_phys; ++ int id; ++ int valid; ++}; ++ ++ ++static inline const char *npe_name(struct npe *npe) ++{ ++ return npe_names[npe->id]; ++} ++ ++int npe_running(struct npe *npe); ++int npe_send_message(struct npe *npe, const void *msg, const char *what); ++int npe_recv_message(struct npe *npe, void *msg, const char *what); ++int npe_send_recv_message(struct npe *npe, void *msg, const char *what); ++int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); ++struct npe *npe_request(int id); ++void npe_release(struct npe *npe); ++ ++#endif /* __IXP4XX_NPE_H */ +diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h +index 2a44d3d..695b9c4 100644 +--- a/include/asm-arm/arch-ixp4xx/platform.h ++++ b/include/asm-arm/arch-ixp4xx/platform.h +@@ -77,8 +77,7 @@ extern unsigned long ixp4xx_exp_bus_size; + + /* + * The IXP4xx chips do not have an I2C unit, so GPIO lines are just +- * used to +- * Used as platform_data to provide GPIO pin information to the ixp42x ++ * used as platform_data to provide GPIO pin information to the ixp42x + * I2C driver. + */ + struct ixp4xx_i2c_pins { +@@ -86,6 +85,27 @@ struct ixp4xx_i2c_pins { + unsigned long scl_pin; + }; + ++#define IXP4XX_ETH_NPEA 0x00 ++#define IXP4XX_ETH_NPEB 0x10 ++#define IXP4XX_ETH_NPEC 0x20 ++ ++/* Information about built-in Ethernet MAC interfaces */ ++struct eth_plat_info { ++ u8 phy; /* MII PHY ID, 0 - 31 */ ++ u8 rxq; /* configurable, currently 0 - 31 only */ ++ u8 txreadyq; ++ u8 hwaddr[6]; ++}; ++ ++/* Information about built-in HSS (synchronous serial) interfaces */ ++struct hss_plat_info { ++ int (*set_clock)(int port, unsigned int clock_type); ++ int (*open)(int port, void *pdev, ++ void (*set_carrier_cb)(void *pdev, int carrier)); ++ void (*close)(int port, void *pdev); ++ u8 txreadyq; ++}; ++ + /* + * This structure provide a means for the board setup code + * to give information to th pata_ixp4xx driver. It is +diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h +new file mode 100644 +index 0000000..1e52b95 +--- /dev/null ++++ b/include/asm-arm/arch-ixp4xx/qmgr.h +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License ++ * as published by the Free Software Foundation. ++ */ ++ ++#ifndef IXP4XX_QMGR_H ++#define IXP4XX_QMGR_H ++ ++#include <linux/io.h> ++#include <linux/kernel.h> ++ ++#define HALF_QUEUES 32 ++#define QUEUES 64 /* only 32 lower queues currently supported */ ++#define MAX_QUEUE_LENGTH 4 /* in dwords */ ++ ++#define QUEUE_STAT1_EMPTY 1 /* queue status bits */ ++#define QUEUE_STAT1_NEARLY_EMPTY 2 ++#define QUEUE_STAT1_NEARLY_FULL 4 ++#define QUEUE_STAT1_FULL 8 ++#define QUEUE_STAT2_UNDERFLOW 1 ++#define QUEUE_STAT2_OVERFLOW 2 ++ ++#define QUEUE_WATERMARK_0_ENTRIES 0 ++#define QUEUE_WATERMARK_1_ENTRY 1 ++#define QUEUE_WATERMARK_2_ENTRIES 2 ++#define QUEUE_WATERMARK_4_ENTRIES 3 ++#define QUEUE_WATERMARK_8_ENTRIES 4 ++#define QUEUE_WATERMARK_16_ENTRIES 5 ++#define QUEUE_WATERMARK_32_ENTRIES 6 ++#define QUEUE_WATERMARK_64_ENTRIES 7 ++ ++/* queue interrupt request conditions */ ++#define QUEUE_IRQ_SRC_EMPTY 0 ++#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1 ++#define QUEUE_IRQ_SRC_NEARLY_FULL 2 ++#define QUEUE_IRQ_SRC_FULL 3 ++#define QUEUE_IRQ_SRC_NOT_EMPTY 4 ++#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5 ++#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6 ++#define QUEUE_IRQ_SRC_NOT_FULL 7 ++ ++struct qmgr_regs { ++ u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */ ++ u32 stat1[4]; /* 0x400 - 0x40F */ ++ u32 stat2[2]; /* 0x410 - 0x417 */ ++ u32 statne_h; /* 0x418 - queue nearly empty */ ++ u32 statf_h; /* 0x41C - queue full */ ++ u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */ ++ u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */ ++ u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */ ++ u32 reserved[1776]; ++ u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */ ++}; ++ ++void qmgr_set_irq(unsigned int queue, int src, ++ void (*handler)(void *pdev), void *pdev); ++void qmgr_enable_irq(unsigned int queue); ++void qmgr_disable_irq(unsigned int queue); ++ ++/* request_ and release_queue() must be called from non-IRQ context */ ++int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, ++ unsigned int nearly_empty_watermark, ++ unsigned int nearly_full_watermark); ++void qmgr_release_queue(unsigned int queue); ++ ++ ++static inline void qmgr_put_entry(unsigned int queue, u32 val) ++{ ++ extern struct qmgr_regs __iomem *qmgr_regs; ++ __raw_writel(val, &qmgr_regs->acc[queue][0]); ++} ++ ++static inline u32 qmgr_get_entry(unsigned int queue) ++{ ++ extern struct qmgr_regs __iomem *qmgr_regs; ++ return __raw_readl(&qmgr_regs->acc[queue][0]); ++} ++ ++static inline int qmgr_get_stat1(unsigned int queue) ++{ ++ extern struct qmgr_regs __iomem *qmgr_regs; ++ return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) ++ >> ((queue & 7) << 2)) & 0xF; ++} ++ ++static inline int qmgr_get_stat2(unsigned int queue) ++{ ++ extern struct qmgr_regs __iomem *qmgr_regs; ++ return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) ++ >> ((queue & 0xF) << 1)) & 0x3; ++} ++ ++static inline int qmgr_stat_empty(unsigned int queue) ++{ ++ return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY); ++} ++ ++static inline int qmgr_stat_nearly_empty(unsigned int queue) ++{ ++ return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY); ++} ++ ++static inline int qmgr_stat_nearly_full(unsigned int queue) ++{ ++ return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL); ++} ++ ++static inline int qmgr_stat_full(unsigned int queue) ++{ ++ return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL); ++} ++ ++static inline int qmgr_stat_underflow(unsigned int queue) ++{ ++ return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW); ++} ++ ++static inline int qmgr_stat_overflow(unsigned int queue) ++{ ++ return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW); ++} ++ ++#endif +diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h +index f7a35b7..34ef48f 100644 +--- a/include/asm-arm/arch-ixp4xx/uncompress.h ++++ b/include/asm-arm/arch-ixp4xx/uncompress.h +@@ -13,7 +13,7 @@ + #ifndef _ARCH_UNCOMPRESS_H_ + #define _ARCH_UNCOMPRESS_H_ + +-#include <asm/hardware.h> ++#include "ixp4xx-regs.h" + #include <asm/mach-types.h> + #include <linux/serial_reg.h> + diff --git a/target/linux/ixp4xx/patches-2.6.24/201-npe_driver_print_license_location.patch b/target/linux/ixp4xx/patches-2.6.24/201-npe_driver_print_license_location.patch new file mode 100644 index 0000000000..fad4033419 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/201-npe_driver_print_license_location.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_npe.c linux-2.6.23-openwrt/arch/arm/mach-ixp4xx/ixp4xx_npe.c +--- linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_npe.c 2007-10-22 22:18:15.000000000 +0200 ++++ linux-2.6.23-openwrt/arch/arm/mach-ixp4xx/ixp4xx_npe.c 2007-10-22 22:32:48.000000000 +0200 +@@ -585,6 +585,8 @@ + npe_reset(npe); + #endif + ++ print_npe(KERN_INFO, npe, "firmware's license can be found in /usr/share/doc/LICENSE.IPL\n"); ++ + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, + (image->id >> 8) & 0xFF, image->id & 0xFF); diff --git a/target/linux/ixp4xx/patches-2.6.24/294-eeprom_new_notifier.patch b/target/linux/ixp4xx/patches-2.6.24/294-eeprom_new_notifier.patch new file mode 100644 index 0000000000..4aa7a988be --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/294-eeprom_new_notifier.patch @@ -0,0 +1,187 @@ +diff -uprN linux-2.6.23.orig/drivers/i2c/chips/eeprom.c linux-2.6.23/drivers/i2c/chips/eeprom.c +--- linux-2.6.23.orig/drivers/i2c/chips/eeprom.c 2007-10-09 15:31:38.000000000 -0500 ++++ linux-2.6.23/drivers/i2c/chips/eeprom.c 2007-10-11 00:57:25.000000000 -0500 +@@ -33,6 +33,8 @@ + #include <linux/jiffies.h> + #include <linux/i2c.h> + #include <linux/mutex.h> ++#include <linux/notifier.h> ++#include <linux/eeprom.h> + + /* Addresses to scan */ + static unsigned short normal_i2c[] = { 0x50, 0x51, 0x52, 0x53, 0x54, +@@ -41,26 +43,7 @@ static unsigned short normal_i2c[] = { 0 + /* Insmod parameters */ + I2C_CLIENT_INSMOD_1(eeprom); + +- +-/* Size of EEPROM in bytes */ +-#define EEPROM_SIZE 256 +- +-/* possible types of eeprom devices */ +-enum eeprom_nature { +- UNKNOWN, +- VAIO, +-}; +- +-/* Each client has this additional data */ +-struct eeprom_data { +- struct i2c_client client; +- struct mutex update_lock; +- u8 valid; /* bitfield, bit!=0 if slice is valid */ +- unsigned long last_updated[8]; /* In jiffies, 8 slices */ +- u8 data[EEPROM_SIZE]; /* Register values */ +- enum eeprom_nature nature; +-}; +- ++ATOMIC_NOTIFIER_HEAD(eeprom_chain); + + static int eeprom_attach_adapter(struct i2c_adapter *adapter); + static int eeprom_detect(struct i2c_adapter *adapter, int address, int kind); +@@ -191,6 +174,7 @@ static int eeprom_detect(struct i2c_adap + data->valid = 0; + mutex_init(&data->update_lock); + data->nature = UNKNOWN; ++ data->attr = &eeprom_attr; + + /* Tell the I2C layer a new client has arrived */ + if ((err = i2c_attach_client(new_client))) +@@ -214,6 +198,9 @@ static int eeprom_detect(struct i2c_adap + if (err) + goto exit_detach; + ++ /* call the notifier chain */ ++ atomic_notifier_call_chain(&eeprom_chain, EEPROM_REGISTER, data); ++ + return 0; + + exit_detach: +@@ -239,6 +226,41 @@ static int eeprom_detach_client(struct i + return 0; + } + ++/** ++ * register_eeprom_notifier - register a 'user' of EEPROM devices. ++ * @nb: pointer to notifier info structure ++ * ++ * Registers a callback function to be called upon detection ++ * of an EEPROM device. Detection invokes the 'add' callback ++ * with the kobj of the mutex and a bin_attribute which allows ++ * read from the EEPROM. The intention is that the notifier ++ * will be able to read system configuration from the notifier. ++ * ++ * Only EEPROMs detected *after* the addition of the notifier ++ * are notified. I.e. EEPROMs already known to the system ++ * will not be notified - add the notifier from board level ++ * code! ++ */ ++int register_eeprom_notifier(struct notifier_block *nb) ++{ ++ return atomic_notifier_chain_register(&eeprom_chain, nb); ++} ++ ++/** ++ * unregister_eeprom_notifier - unregister a 'user' of EEPROM devices. ++ * @old: pointer to notifier info structure ++ * ++ * Removes a callback function from the list of 'users' to be ++ * notified upon detection of EEPROM devices. ++ */ ++int unregister_eeprom_notifier(struct notifier_block *nb) ++{ ++ return atomic_notifier_chain_unregister(&eeprom_chain, nb); ++} ++ ++EXPORT_SYMBOL_GPL(register_eeprom_notifier); ++EXPORT_SYMBOL_GPL(unregister_eeprom_notifier); ++ + static int __init eeprom_init(void) + { + return i2c_add_driver(&eeprom_driver); +diff -uprN linux-2.6.23.orig/include/linux/eeprom.h linux-2.6.23/include/linux/eeprom.h +--- linux-2.6.23.orig/include/linux/eeprom.h 1969-12-31 18:00:00.000000000 -0600 ++++ linux-2.6.23/include/linux/eeprom.h 2007-10-11 00:57:25.000000000 -0500 +@@ -0,0 +1,71 @@ ++#ifndef _LINUX_EEPROM_H ++#define _LINUX_EEPROM_H ++/* ++ * EEPROM notifier header ++ * ++ * Copyright (C) 2006 John Bowler ++ */ ++ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __KERNEL__ ++#error This is a kernel header ++#endif ++ ++#include <linux/list.h> ++#include <linux/kobject.h> ++#include <linux/sysfs.h> ++ ++/* Size of EEPROM in bytes */ ++#define EEPROM_SIZE 256 ++ ++/* possible types of eeprom devices */ ++enum eeprom_nature { ++ UNKNOWN, ++ VAIO, ++}; ++ ++/* Each client has this additional data */ ++struct eeprom_data { ++ struct i2c_client client; ++ struct mutex update_lock; ++ u8 valid; /* bitfield, bit!=0 if slice is valid */ ++ unsigned long last_updated[8]; /* In jiffies, 8 slices */ ++ u8 data[EEPROM_SIZE]; /* Register values */ ++ enum eeprom_nature nature; ++ struct bin_attribute *attr; ++}; ++ ++/* ++ * This is very basic. ++ * ++ * If an EEPROM is detected on the I2C bus (this only works for ++ * I2C EEPROMs) the notifier chain is called with ++ * both the I2C information and the kobject for the sysfs ++ * device which has been registers. It is then possible to ++ * read from the device via the bin_attribute::read method ++ * to extract configuration information. ++ * ++ * Register the notifier in the board level code, there is no ++ * need to unregister it but you can if you want (it will save ++ * a little bit or kernel memory to do so). ++ */ ++ ++extern int register_eeprom_notifier(struct notifier_block *nb); ++extern int unregister_eeprom_notifier(struct notifier_block *nb); ++ ++#endif /* _LINUX_EEPROM_H */ +diff -uprN linux-2.6.23.orig/include/linux/notifier.h linux-2.6.23/include/linux/notifier.h +--- linux-2.6.23.orig/include/linux/notifier.h 2007-10-09 15:31:38.000000000 -0500 ++++ linux-2.6.23/include/linux/notifier.h 2007-10-11 00:57:25.000000000 -0500 +@@ -231,5 +231,8 @@ static inline int notifier_to_errno(int + #define PM_SUSPEND_PREPARE 0x0003 /* Going to suspend the system */ + #define PM_POST_SUSPEND 0x0004 /* Suspend finished */ + ++/* eeprom notifier chain */ ++#define EEPROM_REGISTER 0x0001 ++ + #endif /* __KERNEL__ */ + #endif /* _LINUX_NOTIFIER_H */ diff --git a/target/linux/ixp4xx/patches-2.6.24/296-avila_mac_plat_info.patch b/target/linux/ixp4xx/patches-2.6.24/296-avila_mac_plat_info.patch new file mode 100644 index 0000000000..e4813fe2c9 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/296-avila_mac_plat_info.patch @@ -0,0 +1,43 @@ +diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c +index e38f45f..10ed5d6 100644 +--- a/arch/arm/mach-ixp4xx/avila-setup.c ++++ b/arch/arm/mach-ixp4xx/avila-setup.c +@@ -132,10 +132,37 @@ static struct platform_device avila_pata = { + .resource = avila_pata_resources, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info avila_plat_eth[] = { ++ { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device avila_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = avila_plat_eth, ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = avila_plat_eth + 1, ++ } ++}; ++ + static struct platform_device *avila_devices[] __initdata = { + &avila_i2c_gpio, + &avila_flash, +- &avila_uart ++ &avila_uart, ++ &avila_eth[0], ++ &avila_eth[1], + }; + + static void __init avila_init(void) diff --git a/target/linux/ixp4xx/patches-2.6.24/298-avila_rtc_fixup.patch b/target/linux/ixp4xx/patches-2.6.24/298-avila_rtc_fixup.patch new file mode 100644 index 0000000000..f706c100a8 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/298-avila_rtc_fixup.patch @@ -0,0 +1,55 @@ +diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/avila-setup.c linux-2.6.23/arch/arm/mach-ixp4xx/avila-setup.c +--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/avila-setup.c 2007-10-09 15:31:38.000000000 -0500 ++++ linux-2.6.23/arch/arm/mach-ixp4xx/avila-setup.c 2007-10-11 01:08:21.000000000 -0500 +@@ -138,6 +138,35 @@ static struct platform_device *avila_dev + &avila_uart + }; + ++static char avila_rtc_probe[] __initdata = "rtc-ds1672.probe=0,0x68 "; ++ ++static void __init avila_fixup(struct machine_desc *desc, ++ struct tag *tags, char **cmdline, struct meminfo *mi) ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(avila_rtc_probe) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, avila_rtc_probe, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(avila_rtc_probe), p, ++ COMMAND_LINE_SIZE - strlen(avila_rtc_probe)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ + static void __init avila_init(void) + { + ixp4xx_sys_init(); +@@ -165,6 +194,7 @@ MACHINE_START(AVILA, "Gateworks Avila Ne + /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */ + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .fixup = avila_fixup, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, +@@ -182,6 +212,7 @@ MACHINE_START(LOFT, "Giant Shoulder Inc + /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */ + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .fixup = avila_fixup, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, diff --git a/target/linux/ixp4xx/patches-2.6.24/300-avila_fetch_mac.patch b/target/linux/ixp4xx/patches-2.6.24/300-avila_fetch_mac.patch new file mode 100644 index 0000000000..2a987588b7 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/300-avila_fetch_mac.patch @@ -0,0 +1,72 @@ +diff -r -u linux-2.6.23.12/arch/arm/mach-ixp4xx/avila-setup.c ../../../../trunk/build_dir/linux-ixp4xx_generic/linux-2.6.23.12/arch/arm/mach-ixp4xx/avila-setup.c +--- linux-2.6.23.12/arch/arm/mach-ixp4xx/avila-setup.c 2008-01-04 01:28:24.134925761 +0100 ++++ ../../../../trunk/build_dir/linux-ixp4xx_generic/linux-2.6.23.12/arch/arm/mach-ixp4xx/avila-setup.c 2008-01-04 01:23:27.874042817 +0100 +@@ -14,10 +14,18 @@ + #include <linux/kernel.h> + #include <linux/init.h> + #include <linux/device.h> ++#include <linux/if_ether.h> ++#include <linux/socket.h> ++#include <linux/netdevice.h> + #include <linux/serial.h> + #include <linux/tty.h> + #include <linux/serial_8250.h> + #include <linux/slab.h> ++#ifdef CONFIG_SENSORS_EEPROM ++# include <linux/i2c.h> ++# include <linux/eeprom.h> ++#endif ++ + #include <linux/i2c-gpio.h> + + #include <asm/types.h> +@@ -194,9 +202,48 @@ + t->hdr.size = 0; + } + ++#ifdef CONFIG_SENSORS_EEPROM ++static int loft_eeprom_do(struct notifier_block *self, unsigned long event, void *t) ++{ ++ struct eeprom_data *data = t; ++ struct sockaddr address; ++ struct net_device * netdev ; ++ ++ char macs[12]; ++ ++ /* The MACs are the first 12 bytes in the eeprom at address 0x51 */ ++ if (event == EEPROM_REGISTER && data->client.addr == 0x51) { ++ data->attr->read(&data->client.dev.kobj, data->attr, macs, 0, 12); ++ /*eth0*/ ++ /* using dev_get_by_name here is really ugly and can cause ++ * confusion if other ethernet devices are present. FIXME */ ++ ++ memcpy(address.sa_data, macs, ETH_ALEN); ++ memcpy(&avila_plat_eth[0].hwaddr, macs, ETH_ALEN); ++ if ( (netdev = dev_get_by_name(&init_net, "eth0")) ) ++ netdev->set_mac_address(netdev, &address); ++ ++ /*same for eth1*/ ++ memcpy(address.sa_data, macs + ETH_ALEN, ETH_ALEN); ++ memcpy(&avila_plat_eth[1].hwaddr, macs + ETH_ALEN, ETH_ALEN); ++ if ( (netdev = dev_get_by_name(&init_net, "eth1")) ) ++ netdev->set_mac_address(netdev, &address); ++ } ++ ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block loft_eeprom_notifier = { ++ .notifier_call = loft_eeprom_do ++}; ++#endif ++ + static void __init avila_init(void) + { + ixp4xx_sys_init(); ++#ifdef CONFIG_SENSORS_EEPROM ++ register_eeprom_notifier(&loft_eeprom_notifier); ++#endif + + avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); + avila_flash_resource.end = + diff --git a/target/linux/ixp4xx/patches-2.6.24/301-avila_led.patch b/target/linux/ixp4xx/patches-2.6.24/301-avila_led.patch new file mode 100644 index 0000000000..b82ed7df57 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/301-avila_led.patch @@ -0,0 +1,50 @@ +Index: linux-2.6.23.14/arch/arm/mach-ixp4xx/avila-setup.c +=================================================================== +--- linux-2.6.23.14.orig/arch/arm/mach-ixp4xx/avila-setup.c 2008-01-25 18:26:06.000000000 +0100 ++++ linux-2.6.23.14/arch/arm/mach-ixp4xx/avila-setup.c 2008-01-25 18:44:02.000000000 +0100 +@@ -165,12 +165,34 @@ + } + }; + ++#ifdef CONFIG_LEDS_IXP4XX ++static struct resource avila_led_resources[] = { ++ { ++ .name = "user", ++ .start = AVILA_LED_USER_GPIO, ++ .end = AVILA_LED_USER_GPIO, ++ .flags = IXP4XX_GPIO_LOW, ++ }, ++}; ++ ++static struct platform_device avila_leds = { ++ .name = "IXP4XX-GPIO-LED", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(avila_led_resources), ++ .resource = avila_led_resources, ++}; ++#endif ++ ++ + static struct platform_device *avila_devices[] __initdata = { + &avila_i2c_gpio, + &avila_flash, + &avila_uart, + &avila_eth[0], + &avila_eth[1], ++#ifdef CONFIG_LEDS_IXP4XX ++ &avila_leds, ++#endif + }; + + static char avila_rtc_probe[] __initdata = "rtc-ds1672.probe=0,0x68 "; +Index: linux-2.6.23.14/include/asm-arm/arch-ixp4xx/avila.h +=================================================================== +--- linux-2.6.23.14.orig/include/asm-arm/arch-ixp4xx/avila.h 2008-01-25 18:26:02.000000000 +0100 ++++ linux-2.6.23.14/include/asm-arm/arch-ixp4xx/avila.h 2008-01-25 18:26:06.000000000 +0100 +@@ -36,4 +36,5 @@ + #define AVILA_PCI_INTC_PIN 9 + #define AVILA_PCI_INTD_PIN 8 + +- ++/* User LED */ ++#define AVILA_LED_USER_GPIO 3 diff --git a/target/linux/ixp4xx/patches-2.6.24/302-gpio_device.patch b/target/linux/ixp4xx/patches-2.6.24/302-gpio_device.patch new file mode 100644 index 0000000000..0a1831b4fc --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/302-gpio_device.patch @@ -0,0 +1,49 @@ +Index: linux-2.6.23.14/arch/arm/mach-ixp4xx/avila-setup.c +=================================================================== +--- linux-2.6.23.14.orig/arch/arm/mach-ixp4xx/avila-setup.c 2008-01-26 02:59:30.000000000 +0100 ++++ linux-2.6.23.14/arch/arm/mach-ixp4xx/avila-setup.c 2008-01-26 03:03:07.000000000 +0100 +@@ -183,6 +183,23 @@ + }; + #endif + ++#ifdef CONFIG_GPIO_DEVICE ++static struct resource avila_gpio_resources[] = { ++ { ++ .name = "gpio", ++ .start = AVILA_GPIO_MASK, ++ .end = AVILA_GPIO_MASK, ++ .flags = 0, ++ }, ++}; ++ ++static struct platform_device avila_gpio = { ++ .name = "GPIODEV", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(avila_gpio_resources), ++ .resource = avila_gpio_resources, ++}; ++#endif + + static struct platform_device *avila_devices[] __initdata = { + &avila_i2c_gpio, +@@ -193,6 +210,9 @@ + #ifdef CONFIG_LEDS_IXP4XX + &avila_leds, + #endif ++#ifdef CONFIG_GPIO_DEVICE ++ &avila_gpio, ++#endif + }; + + static char avila_rtc_probe[] __initdata = "rtc-ds1672.probe=0,0x68 "; +Index: linux-2.6.23.14/include/asm-arm/arch-ixp4xx/avila.h +=================================================================== +--- linux-2.6.23.14.orig/include/asm-arm/arch-ixp4xx/avila.h 2008-01-26 03:03:27.000000000 +0100 ++++ linux-2.6.23.14/include/asm-arm/arch-ixp4xx/avila.h 2008-01-26 03:07:02.000000000 +0100 +@@ -38,3 +38,6 @@ + + /* User LED */ + #define AVILA_LED_USER_GPIO 3 ++ ++/* gpio mask used by platform device */ ++#define AVILA_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) | (1 << 9) diff --git a/target/linux/ixp4xx/patches-2.6.24/400-dmabounce.patch b/target/linux/ixp4xx/patches-2.6.24/400-dmabounce.patch new file mode 100644 index 0000000000..f4910261e3 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/400-dmabounce.patch @@ -0,0 +1,31 @@ +Index: linux-2.6.23.14/arch/arm/common/dmabounce.c +=================================================================== +--- linux-2.6.23.14.orig/arch/arm/common/dmabounce.c 2008-01-24 22:03:28.475500801 +0100 ++++ linux-2.6.23.14/arch/arm/common/dmabounce.c 2008-01-24 22:17:36.415822168 +0100 +@@ -116,6 +116,10 @@ + } else if (size <= device_info->large.size) { + pool = &device_info->large; + } else { ++#ifdef CONFIG_DMABOUNCE_DEBUG ++ printk(KERN_INFO "A dma bounce buffer outside the pool size was requested. Requested size was 0x%08X\nThe calling code was :\n", size); ++ dump_stack(); ++#endif + pool = NULL; + } + +Index: linux-2.6.23.14/arch/arm/mach-ixp4xx/Kconfig +=================================================================== +--- linux-2.6.23.14.orig/arch/arm/mach-ixp4xx/Kconfig 2008-01-24 22:10:29.331484012 +0100 ++++ linux-2.6.23.14/arch/arm/mach-ixp4xx/Kconfig 2008-01-24 22:11:42.891675973 +0100 +@@ -220,6 +220,11 @@ + default y + depends on PCI + ++config DMABOUNCE_DEBUG ++ bool "Enable DMABounce debuging" ++ default n ++ depends on DMABOUNCE ++ + config IXP4XX_INDIRECT_PCI + bool "Use indirect PCI memory access" + depends on PCI diff --git a/target/linux/ixp4xx/patches-2.6.24/401-avila_pci_dev.patch b/target/linux/ixp4xx/patches-2.6.24/401-avila_pci_dev.patch new file mode 100644 index 0000000000..db76d15da4 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.24/401-avila_pci_dev.patch @@ -0,0 +1,13 @@ +Index: linux-2.6.23.14/include/asm-arm/arch-ixp4xx/avila.h +=================================================================== +--- linux-2.6.23.14.orig/include/asm-arm/arch-ixp4xx/avila.h 2008-01-31 17:40:36.000000000 +0100 ++++ linux-2.6.23.14/include/asm-arm/arch-ixp4xx/avila.h 2008-01-31 17:40:42.000000000 +0100 +@@ -25,7 +25,7 @@ + /* + * AVILA PCI IRQs + */ +-#define AVILA_PCI_MAX_DEV 4 ++#define AVILA_PCI_MAX_DEV 6 + #define LOFT_PCI_MAX_DEV 6 + #define AVILA_PCI_IRQ_LINES 4 + |