diff options
Diffstat (limited to 'target/linux/generic/patches-3.1/020-ssb_update.patch')
| -rw-r--r-- | target/linux/generic/patches-3.1/020-ssb_update.patch | 223 |
1 files changed, 223 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.1/020-ssb_update.patch b/target/linux/generic/patches-3.1/020-ssb_update.patch new file mode 100644 index 0000000000..9dc63adfa2 --- /dev/null +++ b/target/linux/generic/patches-3.1/020-ssb_update.patch @@ -0,0 +1,223 @@ +--- a/drivers/ssb/b43_pci_bridge.c ++++ b/drivers/ssb/b43_pci_bridge.c +@@ -11,6 +11,7 @@ + */ + + #include <linux/pci.h> ++#include <linux/module.h> + #include <linux/ssb/ssb.h> + + #include "ssb_private.h" +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -516,10 +516,14 @@ static void ssb_pcicore_pcie_setup_worka + + static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) + { +- ssb_pcicore_fix_sprom_core_index(pc); ++ struct ssb_device *pdev = pc->dev; ++ struct ssb_bus *bus = pdev->bus; ++ ++ if (bus->bustype == SSB_BUSTYPE_PCI) ++ ssb_pcicore_fix_sprom_core_index(pc); + + /* Disable PCI interrupts. */ +- ssb_write32(pc->dev, SSB_INTVEC, 0); ++ ssb_write32(pdev, SSB_INTVEC, 0); + + /* Additional PCIe always once-executed workarounds */ + if (pc->dev->id.coreid == SSB_DEV_PCIE) { +--- a/drivers/ssb/main.c ++++ b/drivers/ssb/main.c +@@ -12,6 +12,7 @@ + + #include <linux/delay.h> + #include <linux/io.h> ++#include <linux/module.h> + #include <linux/ssb/ssb.h> + #include <linux/ssb/ssb_regs.h> + #include <linux/ssb/ssb_driver_gige.h> +@@ -1260,16 +1261,34 @@ void ssb_device_disable(struct ssb_devic + } + EXPORT_SYMBOL(ssb_device_disable); + ++/* Some chipsets need routing known for PCIe and 64-bit DMA */ ++static bool ssb_dma_translation_special_bit(struct ssb_device *dev) ++{ ++ u16 chip_id = dev->bus->chip_id; ++ ++ if (dev->id.coreid == SSB_DEV_80211) { ++ return (chip_id == 0x4322 || chip_id == 43221 || ++ chip_id == 43231 || chip_id == 43222); ++ } ++ ++ return 0; ++} ++ + u32 ssb_dma_translation(struct ssb_device *dev) + { + switch (dev->bus->bustype) { + case SSB_BUSTYPE_SSB: + return 0; + case SSB_BUSTYPE_PCI: +- if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) ++ if (pci_is_pcie(dev->bus->host_pci) && ++ ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { + return SSB_PCIE_DMA_H32; +- else +- return SSB_PCI_DMA; ++ } else { ++ if (ssb_dma_translation_special_bit(dev)) ++ return SSB_PCIE_DMA_H32; ++ else ++ return SSB_PCI_DMA; ++ } + default: + __ssb_dma_not_implemented(dev); + } +--- a/drivers/ssb/pci.c ++++ b/drivers/ssb/pci.c +@@ -607,6 +607,29 @@ static void sprom_extract_r8(struct ssb_ + memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, + sizeof(out->antenna_gain.ghz5)); + ++ /* Extract FEM info */ ++ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ ++ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ + sprom_extract_r458(out, in); + + /* TODO - get remaining rev 8 stuff needed */ +--- a/include/linux/ssb/ssb.h ++++ b/include/linux/ssb/ssb.h +@@ -25,7 +25,7 @@ struct ssb_sprom { + u8 et1phyaddr; /* MII address for enet1 */ + u8 et0mdcport; /* MDIO for enet0 */ + u8 et1mdcport; /* MDIO for enet1 */ +- u8 board_rev; /* Board revision number from SPROM. */ ++ u16 board_rev; /* Board revision number from SPROM. */ + u8 country_code; /* Country Code */ + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */ + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ +@@ -94,6 +94,15 @@ struct ssb_sprom { + } ghz5; /* 5GHz band */ + } antenna_gain; + ++ struct { ++ struct { ++ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; ++ } ghz2; ++ struct { ++ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; ++ } ghz5; ++ } fem; ++ + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */ + }; + +@@ -231,10 +240,9 @@ struct ssb_driver { + #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv) + + extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner); +-static inline int ssb_driver_register(struct ssb_driver *drv) +-{ +- return __ssb_driver_register(drv, THIS_MODULE); +-} ++#define ssb_driver_register(drv) \ ++ __ssb_driver_register(drv, THIS_MODULE) ++ + extern void ssb_driver_unregister(struct ssb_driver *drv); + + +--- a/include/linux/ssb/ssb_regs.h ++++ b/include/linux/ssb/ssb_regs.h +@@ -432,6 +432,23 @@ + #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ + #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ + #define SSB_SPROM8_RXPO5G_SHIFT 8 ++#define SSB_SPROM8_FEM2G 0x00AE ++#define SSB_SPROM8_FEM5G 0x00B0 ++#define SSB_SROM8_FEM_TSSIPOS 0x0001 ++#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0 ++#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006 ++#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1 ++#define SSB_SROM8_FEM_PDET_RANGE 0x00F8 ++#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3 ++#define SSB_SROM8_FEM_TR_ISO 0x0700 ++#define SSB_SROM8_FEM_TR_ISO_SHIFT 8 ++#define SSB_SROM8_FEM_ANTSWLUT 0xF800 ++#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11 ++#define SSB_SPROM8_THERMAL 0x00B2 ++#define SSB_SPROM8_MPWR_RAWTS 0x00B4 ++#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6 ++#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8 ++#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA + #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ + #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ + #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ +@@ -462,6 +479,46 @@ + #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */ + #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */ + ++/* Values for boardflags_lo read from SPROM */ ++#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ ++#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ ++#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ ++#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ ++#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ ++#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ ++#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ ++#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */ ++#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */ ++#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ ++#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */ ++#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */ ++#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */ ++#define SSB_BFL_HGPA 0x2000 /* had high gain PA */ ++#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ ++#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ ++ ++/* Values for boardflags_hi read from SPROM */ ++#define SSB_BFH_NOPA 0x0001 /* has no PA */ ++#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */ ++#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */ ++#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */ ++#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */ ++#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */ ++#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */ ++ ++/* Values for boardflags2_lo read from SPROM */ ++#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */ ++#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */ ++#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */ ++#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */ ++#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */ ++#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */ ++#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */ ++#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */ ++#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */ ++#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */ ++#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */ ++ + /* Values for SSB_SPROM1_BINF_CCODE */ + enum { + SSB_SPROM1CCODE_WORLD = 0, |