diff options
Diffstat (limited to 'target/linux/generic/patches-2.6.32')
| -rw-r--r-- | target/linux/generic/patches-2.6.32/025-bcma_backport.patch | 1607 | ||||
| -rw-r--r-- | target/linux/generic/patches-2.6.32/975-ssb_update.patch | 441 |
2 files changed, 1808 insertions, 240 deletions
diff --git a/target/linux/generic/patches-2.6.32/025-bcma_backport.patch b/target/linux/generic/patches-2.6.32/025-bcma_backport.patch index 4d73540a09..3571bd1984 100644 --- a/target/linux/generic/patches-2.6.32/025-bcma_backport.patch +++ b/target/linux/generic/patches-2.6.32/025-bcma_backport.patch @@ -71,7 +71,7 @@ obj-y += platform/ --- /dev/null +++ b/drivers/bcma/Kconfig -@@ -0,0 +1,44 @@ +@@ -0,0 +1,57 @@ +config BCMA_POSSIBLE + bool + depends on HAS_IOMEM && HAS_DMA @@ -107,6 +107,19 @@ + help + PCI core hostmode operation (external PCI bus). + ++config BCMA_HOST_SOC ++ bool ++ depends on BCMA_DRIVER_MIPS ++ ++config BCMA_DRIVER_MIPS ++ bool "BCMA Broadcom MIPS core driver" ++ depends on BCMA && MIPS ++ help ++ Driver for the Broadcom MIPS core attached to Broadcom specific ++ Advanced Microcontroller Bus. ++ ++ If unsure, say N ++ +config BCMA_DEBUG + bool "BCMA debugging" + depends on BCMA @@ -118,12 +131,14 @@ +endmenu --- /dev/null +++ b/drivers/bcma/Makefile -@@ -0,0 +1,8 @@ +@@ -0,0 +1,10 @@ +bcma-y += main.o scan.o core.o sprom.o +bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o +bcma-y += driver_pci.o +bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o ++bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o +bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o ++bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o +obj-$(CONFIG_BCMA) += bcma.o + +ccflags-$(CONFIG_BCMA_DEBUG) := -DDEBUG @@ -157,7 +172,7 @@ +- Create kernel Documentation (use info from README) --- /dev/null +++ b/drivers/bcma/bcma_private.h -@@ -0,0 +1,35 @@ +@@ -0,0 +1,54 @@ +#ifndef LINUX_BCMA_PRIVATE_H_ +#define LINUX_BCMA_PRIVATE_H_ + @@ -175,13 +190,32 @@ +/* main.c */ +int bcma_bus_register(struct bcma_bus *bus); +void bcma_bus_unregister(struct bcma_bus *bus); ++int __init bcma_bus_early_register(struct bcma_bus *bus, ++ struct bcma_device *core_cc, ++ struct bcma_device *core_mips); ++#ifdef CONFIG_PM ++int bcma_bus_resume(struct bcma_bus *bus); ++#endif + +/* scan.c */ +int bcma_bus_scan(struct bcma_bus *bus); ++int __init bcma_bus_scan_early(struct bcma_bus *bus, ++ struct bcma_device_id *match, ++ struct bcma_device *core); ++void bcma_init_bus(struct bcma_bus *bus); + +/* sprom.c */ +int bcma_sprom_get(struct bcma_bus *bus); + ++/* driver_chipcommon.c */ ++#ifdef CONFIG_BCMA_DRIVER_MIPS ++void bcma_chipco_serial_init(struct bcma_drv_cc *cc); ++#endif /* CONFIG_BCMA_DRIVER_MIPS */ ++ ++/* driver_chipcommon_pmu.c */ ++u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc); ++u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc); ++ +#ifdef CONFIG_BCMA_HOST_PCI +/* host_pci.c */ +extern int __init bcma_host_pci_init(void); @@ -195,7 +229,7 @@ +#endif --- /dev/null +++ b/drivers/bcma/core.c -@@ -0,0 +1,124 @@ +@@ -0,0 +1,126 @@ +/* + * Broadcom specific AMBA + * Core ops @@ -308,6 +342,8 @@ +u32 bcma_core_dma_translation(struct bcma_device *core) +{ + switch (core->bus->hosttype) { ++ case BCMA_HOSTTYPE_SOC: ++ return 0; + case BCMA_HOSTTYPE_PCI: + if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64) + return BCMA_DMA_TRANSLATION_DMA64_CMT; @@ -322,13 +358,13 @@ +EXPORT_SYMBOL(bcma_core_dma_translation); --- /dev/null +++ b/drivers/bcma/driver_chipcommon.c -@@ -0,0 +1,103 @@ +@@ -0,0 +1,156 @@ +/* + * Broadcom specific AMBA + * ChipCommon core driver + * + * Copyright 2005, Broadcom Corporation -+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2006, 2007, Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -351,6 +387,9 @@ + u32 leddc_on = 10; + u32 leddc_off = 90; + ++ if (cc->setup_done) ++ return; ++ + if (cc->core->id.rev >= 11) + cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); + cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); @@ -377,6 +416,8 @@ + ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | + (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); + } ++ ++ cc->setup_done = true; +} + +/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ @@ -426,14 +467,62 @@ +{ + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); +} ++ ++#ifdef CONFIG_BCMA_DRIVER_MIPS ++void bcma_chipco_serial_init(struct bcma_drv_cc *cc) ++{ ++ unsigned int irq; ++ u32 baud_base; ++ u32 i; ++ unsigned int ccrev = cc->core->id.rev; ++ struct bcma_serial_port *ports = cc->serial_ports; ++ ++ if (ccrev >= 11 && ccrev != 15) { ++ /* Fixed ALP clock */ ++ baud_base = bcma_pmu_alp_clock(cc); ++ if (ccrev >= 21) { ++ /* Turn off UART clock before switching clocksource. */ ++ bcma_cc_write32(cc, BCMA_CC_CORECTL, ++ bcma_cc_read32(cc, BCMA_CC_CORECTL) ++ & ~BCMA_CC_CORECTL_UARTCLKEN); ++ } ++ /* Set the override bit so we don't divide it */ ++ bcma_cc_write32(cc, BCMA_CC_CORECTL, ++ bcma_cc_read32(cc, BCMA_CC_CORECTL) ++ | BCMA_CC_CORECTL_UARTCLK0); ++ if (ccrev >= 21) { ++ /* Re-enable the UART clock. */ ++ bcma_cc_write32(cc, BCMA_CC_CORECTL, ++ bcma_cc_read32(cc, BCMA_CC_CORECTL) ++ | BCMA_CC_CORECTL_UARTCLKEN); ++ } ++ } else { ++ pr_err("serial not supported on this device ccrev: 0x%x\n", ++ ccrev); ++ return; ++ } ++ ++ irq = bcma_core_mips_irq(cc->core); ++ ++ /* Determine the registers of the UARTs */ ++ cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); ++ for (i = 0; i < cc->nr_serial_ports; i++) { ++ ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + ++ (i * 256); ++ ports[i].irq = irq; ++ ports[i].baud_base = baud_base; ++ ports[i].reg_shift = 0; ++ } ++} ++#endif /* CONFIG_BCMA_DRIVER_MIPS */ --- /dev/null +++ b/drivers/bcma/driver_chipcommon_pmu.c -@@ -0,0 +1,138 @@ +@@ -0,0 +1,309 @@ +/* + * Broadcom specific AMBA + * ChipCommon Power Management Unit driver + * -+ * Copyright 2009, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2009, Michael Buesch <m@bues.ch> + * Copyright 2007, Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. @@ -442,20 +531,47 @@ +#include "bcma_private.h" +#include <linux/bcma/bcma.h> + -+static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, -+ u32 offset, u32 mask, u32 set) ++static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) +{ -+ u32 value; ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); ++ bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); ++ return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); ++} + -+ bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR); ++void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) ++{ ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); ++ bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value); ++} ++EXPORT_SYMBOL_GPL(bcma_chipco_pll_write); ++ ++void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, ++ u32 set) ++{ ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); ++ bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); ++ bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set); ++} ++EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset); ++ ++void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, ++ u32 offset, u32 mask, u32 set) ++{ + bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset); + bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR); -+ value = bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA); -+ value &= mask; -+ value |= set; -+ bcma_cc_write32(cc, BCMA_CC_CHIPCTL_DATA, value); -+ bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA); ++ bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set); +} ++EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset); ++ ++void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, ++ u32 set) ++{ ++ bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset); ++ bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR); ++ bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set); ++} ++EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset); + +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc) +{ @@ -514,6 +630,24 @@ + } +} + ++/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */ ++void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable) ++{ ++ struct bcma_bus *bus = cc->core->bus; ++ u32 val; ++ ++ val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL); ++ if (enable) { ++ val |= BCMA_CHIPCTL_4331_EXTPA_EN; ++ if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11) ++ val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; ++ } else { ++ val &= ~BCMA_CHIPCTL_4331_EXTPA_EN; ++ val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; ++ } ++ bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); ++} ++ +void bcma_pmu_workarounds(struct bcma_drv_cc *cc) +{ + struct bcma_bus *bus = cc->core->bus; @@ -523,7 +657,7 @@ + bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7); + break; + case 0x4331: -+ pr_err("Enabling Ext PA lines not implemented\n"); ++ /* BCM4331 workaround is SPROM-related, we put it in sprom.c */ + break; + case 43224: + if (bus->chipinfo.rev == 0) { @@ -567,15 +701,141 @@ + bcma_pmu_swreg_init(cc); + bcma_pmu_workarounds(cc); +} ++ ++u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc) ++{ ++ struct bcma_bus *bus = cc->core->bus; ++ ++ switch (bus->chipinfo.id) { ++ case 0x4716: ++ case 0x4748: ++ case 47162: ++ case 0x4313: ++ case 0x5357: ++ case 0x4749: ++ case 53572: ++ /* always 20Mhz */ ++ return 20000 * 1000; ++ case 0x5356: ++ case 0x5300: ++ /* always 25Mhz */ ++ return 25000 * 1000; ++ default: ++ pr_warning("No ALP clock specified for %04X device, " ++ "pmu rev. %d, using default %d Hz\n", ++ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); ++ } ++ return BCMA_CC_PMU_ALP_CLOCK; ++} ++ ++/* Find the output of the "m" pll divider given pll controls that start with ++ * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. ++ */ ++static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) ++{ ++ u32 tmp, div, ndiv, p1, p2, fc; ++ struct bcma_bus *bus = cc->core->bus; ++ ++ BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); ++ ++ BUG_ON(!m || m > 4); ++ ++ if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) { ++ /* Detect failure in clock setting */ ++ tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); ++ if (tmp & 0x40000) ++ return 133 * 1000000; ++ } ++ ++ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); ++ p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT; ++ p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT; ++ ++ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); ++ div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) & ++ BCMA_CC_PPL_MDIV_MASK; ++ ++ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF); ++ ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; ++ ++ /* Do calculation in Mhz */ ++ fc = bcma_pmu_alp_clock(cc) / 1000000; ++ fc = (p1 * ndiv * fc) / p2; ++ ++ /* Return clock in Hertz */ ++ return (fc / div) * 1000000; ++} ++ ++/* query bus clock frequency for PMU-enabled chipcommon */ ++u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) ++{ ++ struct bcma_bus *bus = cc->core->bus; ++ ++ switch (bus->chipinfo.id) { ++ case 0x4716: ++ case 0x4748: ++ case 47162: ++ return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, ++ BCMA_CC_PMU5_MAINPLL_SSB); ++ case 0x5356: ++ return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, ++ BCMA_CC_PMU5_MAINPLL_SSB); ++ case 0x5357: ++ case 0x4749: ++ return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, ++ BCMA_CC_PMU5_MAINPLL_SSB); ++ case 0x5300: ++ return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0, ++ BCMA_CC_PMU5_MAINPLL_SSB); ++ case 53572: ++ return 75000000; ++ default: ++ pr_warning("No backplane clock specified for %04X device, " ++ "pmu rev. %d, using default %d Hz\n", ++ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK); ++ } ++ return BCMA_CC_PMU_HT_CLOCK; ++} ++ ++/* query cpu clock frequency for PMU-enabled chipcommon */ ++u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc) ++{ ++ struct bcma_bus *bus = cc->core->bus; ++ ++ if (bus->chipinfo.id == 53572) ++ return 300000000; ++ ++ if (cc->pmu.rev >= 5) { ++ u32 pll; ++ switch (bus->chipinfo.id) { ++ case 0x5356: ++ pll = BCMA_CC_PMU5356_MAINPLL_PLL0; ++ break; ++ case 0x5357: ++ case 0x4749: ++ pll = BCMA_CC_PMU5357_MAINPLL_PLL0; ++ break; ++ default: ++ pll = BCMA_CC_PMU4716_MAINPLL_PLL0; ++ break; ++ } ++ ++ /* TODO: if (bus->chipinfo.id == 0x5300) ++ return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */ ++ return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); ++ } ++ ++ return bcma_pmu_get_clockcontrol(cc); ++} --- /dev/null +++ b/drivers/bcma/driver_pci.c -@@ -0,0 +1,223 @@ +@@ -0,0 +1,237 @@ +/* + * Broadcom specific AMBA + * PCI Core + * + * Copyright 2005, Broadcom Corporation -+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2006, 2007, Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -744,8 +1004,10 @@ + chipid_top != 0x5300) + return false; + -+ if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI) ++#ifdef CONFIG_SSB_DRIVER_PCICORE ++ if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI) + return false; ++#endif /* CONFIG_SSB_DRIVER_PCICORE */ + +#if 0 + /* TODO: on BCMA we use address from EROM instead of magic formula */ @@ -759,6 +1021,9 @@ + +void bcma_core_pci_init(struct bcma_drv_pci *pc) +{ ++ if (pc->setup_done) ++ return; ++ + if (bcma_core_pci_is_in_hostmode(pc)) { +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE + bcma_core_pci_hostmode_init(pc); @@ -768,6 +1033,8 @@ + } else { + bcma_core_pci_clientmode_init(pc); + } ++ ++ pc->setup_done = true; +} + +int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, @@ -775,7 +1042,14 @@ +{ + struct pci_dev *pdev = pc->core->bus->host_pci; + u32 coremask, tmp; -+ int err; ++ int err = 0; ++ ++ if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) { ++ /* This bcma device is not on a PCI host-bus. So the IRQs are ++ * not routed through the PCI core. ++ * So we must not enable routing through the PCI core. */ ++ goto out; ++ } + + err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); + if (err) @@ -795,7 +1069,7 @@ +EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl); --- /dev/null +++ b/drivers/bcma/host_pci.c -@@ -0,0 +1,251 @@ +@@ -0,0 +1,299 @@ +/* + * Broadcom specific AMBA + * PCI Host @@ -807,6 +1081,7 @@ +#include <linux/slab.h> +#include <linux/bcma/bcma.h> +#include <linux/pci.h> ++#include <linux/module.h> + +static void bcma_host_pci_switch_core(struct bcma_device *core) +{ @@ -818,48 +1093,58 @@ + pr_debug("Switched to core: 0x%X\n", core->id.id); +} + -+static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset) ++/* Provides access to the requested core. Returns base offset that has to be ++ * used. It makes use of fixed windows when possible. */ ++static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core) +{ ++ switch (core->id.id) { ++ case BCMA_CORE_CHIPCOMMON: ++ return 3 * BCMA_CORE_SIZE; ++ case BCMA_CORE_PCIE: ++ return 2 * BCMA_CORE_SIZE; ++ } ++ + if (core->bus->mapped_core != core) + bcma_host_pci_switch_core(core); ++ return 0; ++} ++ ++static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset) ++{ ++ offset += bcma_host_pci_provide_access_to_core(core); + return ioread8(core->bus->mmio + offset); +} + +static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset) +{ -+ if (core->bus->mapped_core != core) -+ bcma_host_pci_switch_core(core); ++ offset += bcma_host_pci_provide_access_to_core(core); + return ioread16(core->bus->mmio + offset); +} + +static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset) +{ -+ if (core->bus->mapped_core != core) -+ bcma_host_pci_switch_core(core); ++ offset += bcma_host_pci_provide_access_to_core(core); + return ioread32(core->bus->mmio + offset); +} + +static void bcma_host_pci_write8(struct bcma_device *core, u16 offset, + u8 value) +{ -+ if (core->bus->mapped_core != core) -+ bcma_host_pci_switch_core(core); ++ offset += bcma_host_pci_provide_access_to_core(core); + iowrite8(value, core->bus->mmio + offset); +} + +static void bcma_host_pci_write16(struct bcma_device *core, u16 offset, + u16 value) +{ -+ if (core->bus->mapped_core != core) -+ bcma_host_pci_switch_core(core); ++ offset += bcma_host_pci_provide_access_to_core(core); + iowrite16(value, core->bus->mmio + offset); +} + +static void bcma_host_pci_write32(struct bcma_device *core, u16 offset, + u32 value) +{ -+ if (core->bus->mapped_core != core) -+ bcma_host_pci_switch_core(core); ++ offset += bcma_host_pci_provide_access_to_core(core); + iowrite32(value, core->bus->mmio + offset); +} + @@ -1021,6 +1306,41 @@ + pci_set_drvdata(dev, NULL); +} + ++#ifdef CONFIG_PM ++static int bcma_host_pci_suspend(struct pci_dev *dev, pm_message_t state) ++{ ++ /* Host specific */ ++ pci_save_state(dev); ++ pci_disable_device(dev); ++ pci_set_power_state(dev, pci_choose_state(dev, state)); ++ ++ return 0; ++} ++ ++static int bcma_host_pci_resume(struct pci_dev *dev) ++{ ++ struct bcma_bus *bus = pci_get_drvdata(dev); ++ int err; ++ ++ /* Host specific */ ++ pci_set_power_state(dev, 0); ++ err = pci_enable_device(dev); ++ if (err) ++ return err; ++ pci_restore_state(dev); ++ ++ /* Bus specific */ ++ err = bcma_bus_resume(bus); ++ if (err) ++ return err; ++ ++ return 0; ++} ++#else /* CONFIG_PM */ ++# define bcma_host_pci_suspend NULL ++# define bcma_host_pci_resume NULL ++#endif /* CONFIG_PM */ ++ +static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = { + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) }, @@ -1036,6 +1356,8 @@ + .id_table = bcma_pci_bridge_tbl, + .probe = bcma_host_pci_probe, + .remove = bcma_host_pci_remove, ++ .suspend = bcma_host_pci_suspend, ++ .resume = bcma_host_pci_resume, +}; + +int __init bcma_host_pci_init(void) @@ -1049,7 +1371,7 @@ +} --- /dev/null +++ b/drivers/bcma/main.c -@@ -0,0 +1,257 @@ +@@ -0,0 +1,354 @@ +/* + * Broadcom specific AMBA + * Bus subsystem @@ -1058,6 +1380,7 @@ + */ + +#include "bcma_private.h" ++#include <linux/module.h> +#include <linux/bcma/bcma.h> +#include <linux/slab.h> + @@ -1067,6 +1390,7 @@ +static int bcma_bus_match(struct device *dev, struct device_driver *drv); +static int bcma_device_probe(struct device *dev); +static int bcma_device_remove(struct device *dev); ++static int bcma_device_uevent(struct device *dev, struct kobj_uevent_env *env); + +static ssize_t manuf_show(struct device *dev, struct device_attribute *attr, char *buf) +{ @@ -1101,6 +1425,7 @@ + .match = bcma_bus_match, + .probe = bcma_device_probe, + .remove = bcma_device_remove, ++ .uevent = bcma_device_uevent, + .dev_attrs = bcma_device_attrs, +}; + @@ -1118,6 +1443,10 @@ +static void bcma_release_core_dev(struct device *dev) +{ + struct bcma_device *core = container_of(dev, struct bcma_device, dev); ++ if (core->io_addr) ++ iounmap(core->io_addr); ++ if (core->io_wrap) ++ iounmap(core->io_wrap); + kfree(core); +} + @@ -1132,6 +1461,7 @@ + case BCMA_CORE_CHIPCOMMON: + case BCMA_CORE_PCI: + case BCMA_CORE_PCIE: ++ case BCMA_CORE_MIPS_74K: + continue; + } + @@ -1145,7 +1475,10 @@ + core->dma_dev = &bus->host_pci->dev; + core->irq = bus->host_pci->irq; + break; -+ case BCMA_HOSTTYPE_NONE: ++ case BCMA_HOSTTYPE_SOC: ++ core->dev.dma_mask = &core->dev.coherent_dma_mask; ++ core->dma_dev = &core->dev; ++ break; + case BCMA_HOSTTYPE_SDIO: + break; + } @@ -1192,6 +1525,13 @@ + bcma_core_chipcommon_init(&bus->drv_cc); + } + ++ /* Init MIPS core */ ++ core = bcma_find_core(bus, BCMA_CORE_MIPS_74K); ++ if (core) { ++ bus->drv_mips.core = core; ++ bcma_core_mips_init(&bus->drv_mips); ++ } ++ + /* Init PCIE core */ + core = bcma_find_core(bus, BCMA_CORE_PCIE); + if (core) { @@ -1221,6 +1561,75 @@ + bcma_unregister_cores(bus); +} + ++int __init bcma_bus_early_register(struct bcma_bus *bus, ++ struct bcma_device *core_cc, ++ struct bcma_device *core_mips) ++{ ++ int err; ++ struct bcma_device *core; ++ struct bcma_device_id match; ++ ++ bcma_init_bus(bus); ++ ++ match.manuf = BCMA_MANUF_BCM; ++ match.id = BCMA_CORE_CHIPCOMMON; ++ match.class = BCMA_CL_SIM; ++ match.rev = BCMA_ANY_REV; ++ ++ /* Scan for chip common core */ ++ err = bcma_bus_scan_early(bus, &match, core_cc); ++ if (err) { ++ pr_err("Failed to scan for common core: %d\n", err); ++ return -1; ++ } ++ ++ match.manuf = BCMA_MANUF_MIPS; ++ match.id = BCMA_CORE_MIPS_74K; ++ match.class = BCMA_CL_SIM; ++ match.rev = BCMA_ANY_REV; ++ ++ /* Scan for mips core */ ++ err = bcma_bus_scan_early(bus, &match, core_mips); ++ if (err) { ++ pr_err("Failed to scan for mips core: %d\n", err); ++ return -1; ++ } ++ ++ /* Init CC core */ ++ core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON); ++ if (core) { ++ bus->drv_cc.core = core; ++ bcma_core_chipcommon_init(&bus->drv_cc); ++ } ++ ++ /* Init MIPS core */ ++ core = bcma_find_core(bus, BCMA_CORE_MIPS_74K); ++ if (core) { ++ bus->drv_mips.core = core; ++ bcma_core_mips_init(&bus->drv_mips); ++ } ++ ++ pr_info("Early bus registered\n"); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++int bcma_bus_resume(struct bcma_bus *bus) ++{ ++ struct bcma_device *core; ++ ++ /* Init CC core */ ++ core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON); ++ if (core) { ++ bus->drv_cc.setup_done = false; ++ bcma_core_chipcommon_init(&bus->drv_cc); ++ } ++ ++ return 0; ++} ++#endif ++ +int __bcma_driver_register(struct bcma_driver *drv, struct module *owner) +{ + drv->drv.name = drv->name; @@ -1279,6 +1688,16 @@ + return 0; +} + ++static int bcma_device_uevent(struct device *dev, struct kobj_uevent_env *env) ++{ ++ struct bcma_device *core = container_of(dev, struct bcma_device, dev); ++ ++ return add_uevent_var(env, ++ "MODALIAS=bcma:m%04Xid%04Xrev%02Xcl%02X", ++ core->id.manuf, core->id.id, ++ core->id.rev, core->id.class); ++} ++ +static int __init bcma_modinit(void) +{ + int err; @@ -1309,7 +1728,7 @@ +module_exit(bcma_modexit) --- /dev/null +++ b/drivers/bcma/scan.c -@@ -0,0 +1,360 @@ +@@ -0,0 +1,486 @@ +/* + * Broadcom specific AMBA + * Bus scanning @@ -1512,18 +1931,162 @@ + return addrl; +} + -+int bcma_bus_scan(struct bcma_bus *bus) ++static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus, ++ u16 index) +{ -+ u32 erombase; -+ u32 __iomem *eromptr, *eromend; ++ struct bcma_device *core; ++ ++ list_for_each_entry(core, &bus->cores, list) { ++ if (core->core_index == index) ++ return core; ++ } ++ return NULL; ++} + ++static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, ++ struct bcma_device_id *match, int core_num, ++ struct bcma_device *core) ++{ ++ s32 tmp; ++ u8 i, j; + s32 cia, cib; + u8 ports[2], wrappers[2]; + ++ /* get CIs */ ++ cia = bcma_erom_get_ci(bus, eromptr); ++ if (cia < 0) { ++ bcma_erom_push_ent(eromptr); ++ if (bcma_erom_is_end(bus, eromptr)) ++ return -ESPIPE; ++ return -EILSEQ; ++ } ++ cib = bcma_erom_get_ci(bus, eromptr); ++ if (cib < 0) ++ return -EILSEQ; ++ ++ /* parse CIs */ ++ core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT; ++ core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT; ++ core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT; ++ ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT; ++ ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT; ++ wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT; ++ wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT; ++ core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT; ++ ++ if (((core->id.manuf == BCMA_MANUF_ARM) && ++ (core->id.id == 0xFFF)) || ++ (ports[1] == 0)) { ++ bcma_erom_skip_component(bus, eromptr); ++ return -ENXIO; ++ } ++ ++ /* check if component is a core at all */ ++ if (wrappers[0] + wrappers[1] == 0) { ++ /* we could save addrl of the router ++ if (cid == BCMA_CORE_OOB_ROUTER) ++ */ ++ bcma_erom_skip_component(bus, eromptr); ++ return -ENXIO; ++ } ++ ++ if (bcma_erom_is_bridge(bus, eromptr)) { ++ bcma_erom_skip_component(bus, eromptr); ++ return -ENXIO; ++ } ++ ++ if (bcma_find_core_by_index(bus, core_num)) { ++ bcma_erom_skip_component(bus, eromptr); ++ return -ENODEV; ++ } ++ ++ if (match && ((match->manuf != BCMA_ANY_MANUF && ++ match->manuf != core->id.manuf) || ++ (match->id != BCMA_ANY_ID && match->id != core->id.id) || ++ (match->rev != BCMA_ANY_REV && match->rev != core->id.rev) || ++ (match->class != BCMA_ANY_CLASS && match->class != core->id.class) ++ )) { ++ bcma_erom_skip_component(bus, eromptr); ++ return -ENODEV; ++ } ++ ++ /* get & parse master ports */ ++ for (i = 0; i < ports[0]; i++) { ++ s32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr); ++ if (mst_port_d < 0) ++ return -EILSEQ; ++ } ++ ++ /* get & parse slave ports */ ++ for (i = 0; i < ports[1]; i++) { ++ for (j = 0; ; j++) { ++ tmp = bcma_erom_get_addr_desc(bus, eromptr, ++ SCAN_ADDR_TYPE_SLAVE, i); ++ if (tmp < 0) { ++ /* no more entries for port _i_ */ ++ /* pr_debug("erom: slave port %d " ++ * "has %d descriptors\n", i, j); */ ++ break; ++ } else { ++ if (i == 0 && j == 0) ++ core->addr = tmp; ++ } ++ } ++ } ++ ++ /* get & parse master wrappers */ ++ for (i = 0; i < wrappers[0]; i++) { ++ for (j = 0; ; j++) { ++ tmp = bcma_erom_get_addr_desc(bus, eromptr, ++ SCAN_ADDR_TYPE_MWRAP, i); ++ if (tmp < 0) { ++ /* no more entries for port _i_ */ ++ /* pr_debug("erom: master wrapper %d " ++ * "has %d descriptors\n", i, j); */ ++ break; ++ } else { ++ if (i == 0 && j == 0) ++ core->wrap = tmp; ++ } ++ } ++ } ++ ++ /* get & parse slave wrappers */ ++ for (i = 0; i < wrappers[1]; i++) { ++ u8 hack = (ports[1] == 1) ? 0 : 1; ++ for (j = 0; ; j++) { ++ tmp = bcma_erom_get_addr_desc(bus, eromptr, ++ SCAN_ADDR_TYPE_SWRAP, i + hack); ++ if (tmp < 0) { ++ /* no more entries for port _i_ */ ++ /* pr_debug("erom: master wrapper %d " ++ * has %d descriptors\n", i, j); */ ++ break; ++ } else { ++ if (wrappers[0] == 0 && !i && !j) ++ core->wrap = tmp; ++ } ++ } ++ } ++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) { ++ core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE); ++ if (!core->io_addr) ++ return -ENOMEM; ++ core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE); ++ if (!core->io_wrap) { ++ iounmap(core->io_addr); ++ return -ENOMEM; ++ } ++ } ++ return 0; ++} ++ ++void bcma_init_bus(struct bcma_bus *bus) ++{ + s32 tmp; -+ u8 i, j; + -+ int err; ++ if (bus->init_done) ++ return; + + INIT_LIST_HEAD(&bus->cores); + bus->nr_cores = 0; @@ -1534,9 +2097,27 @@ + bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT; + bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT; + bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT; ++ bus->init_done = true; ++} ++ ++int bcma_bus_scan(struct bcma_bus *bus) ++{ ++ u32 erombase; ++ u32 __iomem *eromptr, *eromend; ++ ++ int err, core_num = 0; ++ ++ bcma_init_bus(bus); + + erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM); -+ eromptr = bus->mmio; ++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) { ++ eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE); ++ if (!eromptr) ++ return -ENOMEM; ++ } else { ++ eromptr = bus->mmio; ++ } ++ + eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32); + + bcma_scan_switch_core(bus, erombase); @@ -1548,127 +2129,91 @@ + INIT_LIST_HEAD(&core->list); + core->bus = bus; + -+ /* get CIs */ -+ cia = bcma_erom_get_ci(bus, &eromptr); -+ if (cia < 0) { -+ bcma_erom_push_ent(&eromptr); -+ if (bcma_erom_is_end(bus, &eromptr)) -+ break; -+ err= -EILSEQ; -+ goto out; -+ } -+ cib = bcma_erom_get_ci(bus, &eromptr); -+ if (cib < 0) { -+ err= -EILSEQ; -+ goto out; -+ } -+ -+ /* parse CIs */ -+ core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT; -+ core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT; -+ core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT; -+ ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT; -+ ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT; -+ wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT; -+ wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT; -+ core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT; -+ -+ if (((core->id.manuf == BCMA_MANUF_ARM) && -+ (core->id.id == 0xFFF)) || -+ (ports[1] == 0)) { -+ bcma_erom_skip_component(bus, &eromptr); ++ err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core); ++ if (err == -ENODEV) { ++ core_num++; + continue; -+ } -+ -+ /* check if component is a core at all */ -+ if (wrappers[0] + wrappers[1] == 0) { -+ /* we could save addrl of the router -+ if (cid == BCMA_CORE_OOB_ROUTER) -+ */ -+ bcma_erom_skip_component(bus, &eromptr); ++ } else if (err == -ENXIO) + continue; -+ } ++ else if (err == -ESPIPE) ++ break; ++ else if (err < 0) ++ return err; + -+ if (bcma_erom_is_bridge(bus, &eromptr)) { -+ bcma_erom_skip_component(bus, &eromptr); -+ continue; -+ } ++ core->core_index = core_num++; ++ bus->nr_cores++; + -+ /* get & parse master ports */ -+ for (i = 0; i < ports[0]; i++) { -+ u32 mst_port_d = bcma_erom_get_mst_port(bus, &eromptr); -+ if (mst_port_d < 0) { -+ err= -EILSEQ; -+ goto out; -+ } -+ } ++ pr_info("Core %d found: %s " ++ "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", ++ core->core_index, bcma_device_name(&core->id), ++ core->id.manuf, core->id.id, core->id.rev, ++ core->id.class); + -+ /* get & parse slave ports */ -+ for (i = 0; i < ports[1]; i++) { -+ for (j = 0; ; j++) { -+ tmp = bcma_erom_get_addr_desc(bus, &eromptr, -+ SCAN_ADDR_TYPE_SLAVE, i); -+ if (tmp < 0) { -+ /* no more entries for port _i_ */ -+ /* pr_debug("erom: slave port %d " -+ * "has %d descriptors\n", i, j); */ -+ break; -+ } else { -+ if (i == 0 && j == 0) -+ core->addr = tmp; -+ } -+ } -+ } ++ list_add(&core->list, &bus->cores); ++ } + -+ /* get & parse master wrappers */ -+ for (i = 0; i < wrappers[0]; i++) { -+ for (j = 0; ; j++) { -+ tmp = bcma_erom_get_addr_desc(bus, &eromptr, -+ SCAN_ADDR_TYPE_MWRAP, i); -+ if (tmp < 0) { -+ /* no more entries for port _i_ */ -+ /* pr_debug("erom: master wrapper %d " -+ * "has %d descriptors\n", i, j); */ -+ break; -+ } else { -+ if (i == 0 && j == 0) -+ core->wrap = tmp; -+ } -+ } -+ } ++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) ++ iounmap(eromptr); + -+ /* get & parse slave wrappers */ -+ for (i = 0; i < wrappers[1]; i++) { -+ u8 hack = (ports[1] == 1) ? 0 : 1; -+ for (j = 0; ; j++) { -+ tmp = bcma_erom_get_addr_desc(bus, &eromptr, -+ SCAN_ADDR_TYPE_SWRAP, i + hack); -+ if (tmp < 0) { -+ /* no more entries for port _i_ */ -+ /* pr_debug("erom: master wrapper %d " -+ * has %d descriptors\n", i, j); */ -+ break; -+ } else { -+ if (wrappers[0] == 0 && !i && !j) -+ core->wrap = tmp; -+ } -+ } -+ } ++ return 0; ++} ++ ++int __init bcma_bus_scan_early(struct bcma_bus *bus, ++ struct bcma_device_id *match, ++ struct bcma_device *core) ++{ ++ u32 erombase; ++ u32 __iomem *eromptr, *eromend; ++ ++ int err = -ENODEV; ++ int core_num = 0; ++ ++ erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM); ++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) { ++ eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE); ++ if (!eromptr) ++ return -ENOMEM; ++ } else { ++ eromptr = bus->mmio; ++ } + ++ eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32); ++ ++ bcma_scan_switch_core(bus, erombase); ++ ++ while (eromptr < eromend) { ++ memset(core, 0, sizeof(*core)); ++ INIT_LIST_HEAD(&core->list); ++ core->bus = bus; ++ ++ err = bcma_get_next_core(bus, &eromptr, match, core_num, core); ++ if (err == -ENODEV) { ++ core_num++; ++ continue; ++ } else if (err == -ENXIO) ++ continue; ++ else if (err == -ESPIPE) ++ break; ++ else if (err < 0) ++ return err; ++ ++ core->core_index = core_num++; ++ bus->nr_cores++; + pr_info("Core %d found: %s " + "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", -+ bus->nr_cores, bcma_device_name(&core->id), ++ core->core_index, bcma_device_name(&core->id), + core->id.manuf, core->id.id, core->id.rev, + core->id.class); + -+ core->core_index = bus->nr_cores++; + list_add(&core->list, &bus->cores); -+ continue; -+out: -+ return err; ++ err = 0; ++ break; + } + -+ return 0; ++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) ++ iounmap(eromptr); ++ ++ return err; +} --- /dev/null +++ b/drivers/bcma/scan.h @@ -1731,7 +2276,7 @@ +#endif /* BCMA_SCAN_H_ */ --- /dev/null +++ b/include/linux/bcma/bcma.h -@@ -0,0 +1,271 @@ +@@ -0,0 +1,298 @@ +#ifndef LINUX_BCMA_H_ +#define LINUX_BCMA_H_ + @@ -1740,6 +2285,7 @@ + +#include <linux/bcma/bcma_driver_chipcommon.h> +#include <linux/bcma/bcma_driver_pci.h> ++#include <linux/bcma/bcma_driver_mips.h> +#include <linux/ssb/ssb.h> /* SPROM sharing */ + +#include "bcma_regs.h" @@ -1748,9 +2294,9 @@ +struct bcma_bus; + +enum bcma_hosttype { -+ BCMA_HOSTTYPE_NONE, + BCMA_HOSTTYPE_PCI, + BCMA_HOSTTYPE_SDIO, ++ BCMA_HOSTTYPE_SOC, +}; + +struct bcma_chipinfo { @@ -1864,6 +2410,7 @@ + + struct device dev; + struct device *dma_dev; ++ + unsigned int irq; + bool dev_registered; + @@ -1872,6 +2419,9 @@ + u32 addr; + u32 wrap; + ++ void __iomem *io_addr; ++ void __iomem *io_wrap; ++ + void *drvdata; + struct list_head list; +}; @@ -1899,10 +2449,9 @@ +}; +extern +int __bcma_driver_register(struct bcma_driver *drv, struct module *owner); -+static inline int bcma_driver_register(struct bcma_driver *drv) -+{ -+ return __bcma_driver_register(drv, THIS_MODULE); -+} ++#define bcma_driver_register(drv) \ ++ __bcma_driver_register(drv, THIS_MODULE) ++ +extern void bcma_driver_unregister(struct bcma_driver *drv); + +struct bcma_bus { @@ -1924,70 +2473,93 @@ + struct bcma_device *mapped_core; + struct list_head cores; + u8 nr_cores; ++ u8 init_done:1; + + struct bcma_drv_cc drv_cc; + struct bcma_drv_pci drv_pci; ++ struct bcma_drv_mips drv_mips; + + /* We decided to share SPROM struct with SSB as long as we do not need + * any hacks for BCMA. This simplifies drivers code. */ + struct ssb_sprom sprom; +}; + -+extern inline u32 bcma_read8(struct bcma_device *core, u16 offset) ++static inline u32 bcma_read8(struct bcma_device *core, u16 offset) +{ + return core->bus->ops->read8(core, offset); +} -+extern inline u32 bcma_read16(struct bcma_device *core, u16 offset) ++static inline u32 bcma_read16(struct bcma_device *core, u16 offset) +{ + return core->bus->ops->read16(core, offset); +} -+extern inline u32 bcma_read32(struct bcma_device *core, u16 offset) ++static inline u32 bcma_read32(struct bcma_device *core, u16 offset) +{ + return core->bus->ops->read32(core, offset); +} -+extern inline ++static inline +void bcma_write8(struct bcma_device *core, u16 offset, u32 value) +{ + core->bus->ops->write8(core, offset, value); +} -+extern inline ++static inline +void bcma_write16(struct bcma_device *core, u16 offset, u32 value) +{ + core->bus->ops->write16(core, offset, value); +} -+extern inline ++static inline +void bcma_write32(struct bcma_device *core, u16 offset, u32 value) +{ + core->bus->ops->write32(core, offset, value); +} +#ifdef CONFIG_BCMA_BLOCKIO -+extern inline void bcma_block_read(struct bcma_device *core, void *buffer, ++static inline void bcma_block_read(struct bcma_device *core, void *buffer, + size_t count, u16 offset, u8 reg_width) +{ + core->bus->ops->block_read(core, buffer, count, offset, reg_width); +} -+extern inline void bcma_block_write(struct bcma_device *core, const void *buffer, -+ size_t count, u16 offset, u8 reg_width) ++static inline void bcma_block_write(struct bcma_device *core, ++ const void *buffer, size_t count, ++ u16 offset, u8 reg_width) +{ + core->bus->ops->block_write(core, buffer, count, offset, reg_width); +} +#endif -+extern inline u32 bcma_aread32(struct bcma_device *core, u16 offset) ++static inline u32 bcma_aread32(struct bcma_device *core, u16 offset) +{ + return core->bus->ops->aread32(core, offset); +} -+extern inline ++static inline +void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value) +{ + core->bus->ops->awrite32(core, offset, value); +} + -+#define bcma_mask32(cc, offset, mask) \ -+ bcma_write32(cc, offset, bcma_read32(cc, offset) & (mask)) -+#define bcma_set32(cc, offset, set) \ -+ bcma_write32(cc, offset, bcma_read32(cc, offset) | (set)) -+#define bcma_maskset32(cc, offset, mask, set) \ -+ bcma_write32(cc, offset, (bcma_read32(cc, offset) & (mask)) | (set)) ++static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask) ++{ ++ bcma_write32(cc, offset, bcma_read32(cc, offset) & mask); ++} ++static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set) ++{ ++ bcma_write32(cc, offset, bcma_read32(cc, offset) | set); ++} ++static inline void bcma_maskset32(struct bcma_device *cc, ++ u16 offset, u32 mask, u32 set) ++{ ++ bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set); ++} ++static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask) ++{ ++ bcma_write16(cc, offset, bcma_read16(cc, offset) & mask); ++} ++static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set) ++{ ++ bcma_write16(cc, offset, bcma_read16(cc, offset) | set); ++} ++static inline void bcma_maskset16(struct bcma_device *cc, ++ u16 offset, u16 mask, u16 set) ++{ ++ bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set); ++} + +extern bool bcma_core_is_enabled(struct bcma_device *core); +extern void bcma_core_disable(struct bcma_device *core, u32 flags); @@ -2005,7 +2577,7 @@ +#endif /* LINUX_BCMA_H_ */ --- /dev/null +++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -0,0 +1,296 @@ +@@ -0,0 +1,391 @@ +#ifndef LINUX_BCMA_DRIVER_CC_H_ +#define LINUX_BCMA_DRIVER_CC_H_ + @@ -2032,6 +2604,7 @@ +#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ +#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */ +#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ ++#define BCMA_CC_FLASHT_NFLASH 0x00000200 +#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ +#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ +#define BCMA_PLLTYPE_NONE 0x00000000 @@ -2186,6 +2759,7 @@ +#define BCMA_CC_PROG_CFG 0x0120 +#define BCMA_CC_PROG_WAITCNT 0x0124 +#define BCMA_CC_FLASH_CFG 0x0128 ++#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ +#define BCMA_CC_FLASH_WAITCNT 0x012C +/* 0x1E0 is defined as shared BCMA_CLKCTLST */ +#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ @@ -2209,6 +2783,7 @@ +#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */ +#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ +#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16 ++#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400 +#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ +#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ +#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ @@ -2247,6 +2822,64 @@ +#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ +#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */ + ++/* Divider allocation in 4716/47162/5356 */ ++#define BCMA_CC_PMU5_MAINPLL_CPU 1 ++#define BCMA_CC_PMU5_MAINPLL_MEM 2 ++#define BCMA_CC_PMU5_MAINPLL_SSB 3 ++ ++/* PLL usage in 4716/47162 */ ++#define BCMA_CC_PMU4716_MAINPLL_PLL0 12 ++ ++/* PLL usage in 5356/5357 */ ++#define BCMA_CC_PMU5356_MAINPLL_PLL0 0 ++#define BCMA_CC_PMU5357_MAINPLL_PLL0 0 ++ ++/* 4706 PMU */ ++#define BCMA_CC_PMU4706_MAINPLL_PLL0 0 ++ ++/* ALP clock on pre-PMU chips */ ++#define BCMA_CC_PMU_ALP_CLOCK 20000000 ++/* HT clock for systems with PMU-enabled chipcommon */ ++#define BCMA_CC_PMU_HT_CLOCK 80000000 ++ ++/* PMU rev 5 (& 6) */ ++#define BCMA_CC_PPL_P1P2_OFF 0 ++#define BCMA_CC_PPL_P1_MASK 0x0f000000 ++#define BCMA_CC_PPL_P1_SHIFT 24 ++#define BCMA_CC_PPL_P2_MASK 0x00f00000 ++#define BCMA_CC_PPL_P2_SHIFT 20 ++#define BCMA_CC_PPL_M14_OFF 1 ++#define BCMA_CC_PPL_MDIV_MASK 0x000000ff ++#define BCMA_CC_PPL_MDIV_WIDTH 8 ++#define BCMA_CC_PPL_NM5_OFF 2 ++#define BCMA_CC_PPL_NDIV_MASK 0xfff00000 ++#define BCMA_CC_PPL_NDIV_SHIFT 20 ++#define BCMA_CC_PPL_FMAB_OFF 3 ++#define BCMA_CC_PPL_MRAT_MASK 0xf0000000 ++#define BCMA_CC_PPL_MRAT_SHIFT 28 ++#define BCMA_CC_PPL_ABRAT_MASK 0x08000000 ++#define BCMA_CC_PPL_ABRAT_SHIFT 27 ++#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff ++#define BCMA_CC_PPL_PLLCTL_OFF 4 ++#define BCMA_CC_PPL_PCHI_OFF 5 ++#define BCMA_CC_PPL_PCHI_MASK 0x0000003f ++ ++/* BCM4331 ChipControl numbers. */ ++#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ ++#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ ++#define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */ ++#define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */ ++#define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */ ++#define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */ ++#define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */ ++#define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */ ++#define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */ ++#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ ++#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ ++#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ ++#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ ++#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ ++ +/* Data for the PMU, if available. + * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) + */ @@ -2255,14 +2888,37 @@ + u32 crystalfreq; /* The active crystal frequency (in kHz) */ +}; + ++#ifdef CONFIG_BCMA_DRIVER_MIPS ++struct bcma_pflash { ++ u8 buswidth; ++ u32 window; ++ u32 window_size; ++}; ++ ++struct bcma_serial_port { ++ void *regs; ++ unsigned long clockspeed; ++ unsigned int irq; ++ unsigned int baud_base; ++ unsigned int reg_shift; ++}; ++#endif /* CONFIG_BCMA_DRIVER_MIPS */ ++ +struct bcma_drv_cc { + struct bcma_device *core; + u32 status; + u32 capabilities; + u32 capabilities_ext; ++ u8 setup_done:1; + /* Fast Powerup Delay constant */ + u16 fast_pwrup_delay; + struct bcma_chipcommon_pmu pmu; ++#ifdef CONFIG_BCMA_DRIVER_MIPS ++ struct bcma_pflash pflash; ++ ++ int nr_serial_ports; ++ struct bcma_serial_port serial_ports[4]; ++#endif /* CONFIG_BCMA_DRIVER_MIPS */ +}; + +/* Register access */ @@ -2283,6 +2939,8 @@ +extern void bcma_chipco_suspend(struct bcma_drv_cc *cc); +extern void bcma_chipco_resume(struct bcma_drv_cc *cc); + ++void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); ++ +extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, + u32 ticks); + @@ -2301,6 +2959,15 @@ +/* PMU support */ +extern void bcma_pmu_init(struct bcma_drv_cc *cc); + ++extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, ++ u32 value); ++extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, ++ u32 mask, u32 set); ++extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, ++ u32 offset, u32 mask, u32 set); ++extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, ++ u32 offset, u32 mask, u32 set); ++ +#endif /* LINUX_BCMA_DRIVER_CC_H_ */ --- /dev/null +++ b/include/linux/bcma/bcma_driver_pci.h @@ -2524,7 +3191,7 @@ sizeof(struct virtio_device_id), "virtio", --- /dev/null +++ b/drivers/bcma/sprom.c -@@ -0,0 +1,171 @@ +@@ -0,0 +1,247 @@ +/* + * Broadcom specific AMBA + * SPROM reading @@ -2656,10 +3323,80 @@ + u16 v; + int i; + ++ bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & ++ SSB_SPROM_REVISION_REV; ++ + for (i = 0; i < 3; i++) { + v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i]; + *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v); + } ++ ++ bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)]; ++ ++ bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] & ++ SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT; ++ bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] & ++ SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT; ++ bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] & ++ SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT; ++ bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] & ++ SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT; ++ ++ bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] & ++ SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT; ++ bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] & ++ SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT; ++ bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] & ++ SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT; ++ bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] & ++ SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT; ++ ++ bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] & ++ SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT; ++ bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] & ++ SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT; ++ bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] & ++ SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT; ++ bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] & ++ SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT; ++ ++ bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] & ++ SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT; ++ bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] & ++ SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT; ++ bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] & ++ SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT; ++ bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] & ++ SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT; ++ ++ bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)]; ++ bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)]; ++ bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)]; ++ bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)]; ++ ++ bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)]; ++ ++ bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & ++ SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT; ++ bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & ++ SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT; ++ bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & ++ SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT; ++ bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & ++ SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT; ++ bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & ++ SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT; ++ ++ bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & ++ SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT; ++ bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & ++ SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT; ++ bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & ++ SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT; ++ bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & ++ SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT; ++ bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & ++ SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT; +} + +int bcma_sprom_get(struct bcma_bus *bus) @@ -2679,6 +3416,9 @@ + if (!sprom) + return -ENOMEM; + ++ if (bus->chipinfo.id == 0x4331) ++ bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false); ++ + /* Most cards have SPROM moved by additional offset 0x30 (48 dwords). + * According to brcm80211 this applies to cards with PCIe rev >= 6 + * TODO: understand this condition and use it */ @@ -2686,6 +3426,9 @@ + BCMA_CC_SPROM_PCIE6; + bcma_sprom_read(bus, offset, sprom); + ++ if (bus->chipinfo.id == 0x4331) ++ bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true); ++ + err = bcma_sprom_valid(sprom); + if (err) + goto out; @@ -2713,3 +3456,521 @@ +{ + pr_err("No support for PCI core in hostmode yet\n"); +} +--- /dev/null ++++ b/drivers/bcma/driver_mips.c +@@ -0,0 +1,256 @@ ++/* ++ * Broadcom specific AMBA ++ * Broadcom MIPS32 74K core driver ++ * ++ * Copyright 2009, Broadcom Corporation ++ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com> ++ * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include "bcma_private.h" ++ ++#include <linux/bcma/bcma.h> ++ ++#include <linux/serial.h> ++#include <linux/serial_core.h> ++#include <linux/serial_reg.h> ++#include <linux/time.h> ++ ++/* The 47162a0 hangs when reading MIPS DMP registers registers */ ++static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev) ++{ ++ return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 && ++ dev->id.id == BCMA_CORE_MIPS_74K; ++} ++ ++/* The 5357b0 hangs when reading USB20H DMP registers */ ++static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev) ++{ ++ return (dev->bus->chipinfo.id == 0x5357 || ++ dev->bus->chipinfo.id == 0x4749) && ++ dev->bus->chipinfo.pkg == 11 && ++ dev->id.id == BCMA_CORE_USB20_HOST; ++} ++ ++static inline u32 mips_read32(struct bcma_drv_mips *mcore, ++ u16 offset) ++{ ++ return bcma_read32(mcore->core, offset); ++} ++ ++static inline void mips_write32(struct bcma_drv_mips *mcore, ++ u16 offset, ++ u32 value) ++{ ++ bcma_write32(mcore->core, offset, value); ++} ++ ++static const u32 ipsflag_irq_mask[] = { ++ 0, ++ BCMA_MIPS_IPSFLAG_IRQ1, ++ BCMA_MIPS_IPSFLAG_IRQ2, ++ BCMA_MIPS_IPSFLAG_IRQ3, ++ BCMA_MIPS_IPSFLAG_IRQ4, ++}; ++ ++static const u32 ipsflag_irq_shift[] = { ++ 0, ++ BCMA_MIPS_IPSFLAG_IRQ1_SHIFT, ++ BCMA_MIPS_IPSFLAG_IRQ2_SHIFT, ++ BCMA_MIPS_IPSFLAG_IRQ3_SHIFT, ++ BCMA_MIPS_IPSFLAG_IRQ4_SHIFT, ++}; ++ ++static u32 bcma_core_mips_irqflag(struct bcma_device *dev) ++{ ++ u32 flag; ++ ++ if (bcma_core_mips_bcm47162a0_quirk(dev)) ++ return dev->core_index; ++ if (bcma_core_mips_bcm5357b0_quirk(dev)) ++ return dev->core_index; ++ flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30); ++ ++ return flag & 0x1F; ++} ++ ++/* Get the MIPS IRQ assignment for a specified device. ++ * If unassigned, 0 is returned. ++ */ ++unsigned int bcma_core_mips_irq(struct bcma_device *dev) ++{ ++ struct bcma_device *mdev = dev->bus->drv_mips.core; ++ u32 irqflag; ++ unsigned int irq; ++ ++ irqflag = bcma_core_mips_irqflag(dev); ++ ++ for (irq = 1; irq <= 4; irq++) ++ if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) & ++ (1 << irqflag)) ++ return irq; ++ ++ return 0; ++} ++EXPORT_SYMBOL(bcma_core_mips_irq); ++ ++static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) ++{ ++ unsigned int oldirq = bcma_core_mips_irq(dev); ++ struct bcma_bus *bus = dev->bus; ++ struct bcma_device *mdev = bus->drv_mips.core; ++ u32 irqflag; ++ ++ irqflag = bcma_core_mips_irqflag(dev); ++ BUG_ON(oldirq == 6); ++ ++ dev->irq = irq + 2; ++ ++ /* clear the old irq */ ++ if (oldirq == 0) ++ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), ++ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & ++ ~(1 << irqflag)); ++ else ++ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0); ++ ++ /* assign the new one */ ++ if (irq == 0) { ++ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), ++ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) | ++ (1 << irqflag)); ++ } else { ++ u32 oldirqflag = bcma_read32(mdev, ++ BCMA_MIPS_MIPS74K_INTMASK(irq)); ++ if (oldirqflag) { ++ struct bcma_device *core; ++ ++ /* backplane irq line is in use, find out who uses ++ * it and set user to irq 0 ++ */ ++ list_for_each_entry_reverse(core, &bus->cores, list) { ++ if ((1 << bcma_core_mips_irqflag(core)) == ++ oldirqflag) { ++ bcma_core_mips_set_irq(core, 0); ++ break; ++ } ++ } ++ } ++ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), ++ 1 << irqflag); ++ } ++ ++ pr_info("set_irq: core 0x%04x, irq %d => %d\n", ++ dev->id.id, oldirq + 2, irq + 2); ++} ++ ++static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) ++{ ++ int i; ++ static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; ++ printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); ++ for (i = 0; i <= 6; i++) ++ printk(" %s%s", irq_name[i], i == irq ? "*" : " "); ++ printk("\n"); ++} ++ ++static void bcma_core_mips_dump_irq(struct bcma_bus *bus) ++{ ++ struct bcma_device *core; ++ ++ list_for_each_entry_reverse(core, &bus->cores, list) { ++ bcma_core_mips_print_irq(core, bcma_core_mips_irq(core)); ++ } ++} ++ ++u32 bcma_cpu_clock(struct bcma_drv_mips *mcore) ++{ ++ struct bcma_bus *bus = mcore->core->bus; ++ ++ if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) ++ return bcma_pmu_get_clockcpu(&bus->drv_cc); ++ ++ pr_err("No PMU available, need this to get the cpu clock\n"); ++ return 0; ++} ++EXPORT_SYMBOL(bcma_cpu_clock); ++ ++static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) ++{ ++ struct bcma_bus *bus = mcore->core->bus; ++ ++ switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) { ++ case BCMA_CC_FLASHT_STSER: ++ case BCMA_CC_FLASHT_ATSER: ++ pr_err("Serial flash not supported.\n"); ++ break; ++ case BCMA_CC_FLASHT_PARA: ++ pr_info("found parallel flash.\n"); ++ bus->drv_cc.pflash.window = 0x1c000000; ++ bus->drv_cc.pflash.window_size = 0x02000000; ++ ++ if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) & ++ BCMA_CC_FLASH_CFG_DS) == 0) ++ bus->drv_cc.pflash.buswidth = 1; ++ else ++ bus->drv_cc.pflash.buswidth = 2; ++ break; ++ default: ++ pr_err("flash not supported.\n"); ++ } ++} ++ ++void bcma_core_mips_init(struct bcma_drv_mips *mcore) ++{ ++ struct bcma_bus *bus; ++ struct bcma_device *core; ++ bus = mcore->core->bus; ++ ++ pr_info("Initializing MIPS core...\n"); ++ ++ if (!mcore->setup_done) ++ mcore->assigned_irqs = 1; ++ ++ /* Assign IRQs to all cores on the bus */ ++ list_for_each_entry_reverse(core, &bus->cores, list) { ++ int mips_irq; ++ if (core->irq) ++ continue; ++ ++ mips_irq = bcma_core_mips_irq(core); ++ if (mips_irq > 4) ++ core->irq = 0; ++ else ++ core->irq = mips_irq + 2; ++ if (core->irq > 5) ++ continue; ++ switch (core->id.id) { ++ case BCMA_CORE_PCI: ++ case BCMA_CORE_PCIE: ++ case BCMA_CORE_ETHERNET: ++ case BCMA_CORE_ETHERNET_GBIT: ++ case BCMA_CORE_MAC_GBIT: ++ case BCMA_CORE_80211: ++ case BCMA_CORE_USB20_HOST: ++ /* These devices get their own IRQ line if available, ++ * the rest goes on IRQ0 ++ */ ++ if (mcore->assigned_irqs <= 4) ++ bcma_core_mips_set_irq(core, ++ mcore->assigned_irqs++); ++ break; ++ } ++ } ++ pr_info("IRQ reconfiguration done\n"); ++ bcma_core_mips_dump_irq(bus); ++ ++ if (mcore->setup_done) ++ return; ++ ++ bcma_chipco_serial_init(&bus->drv_cc); ++ bcma_core_mips_flash_detect(mcore); ++ mcore->setup_done = true; ++} +--- /dev/null ++++ b/drivers/bcma/host_soc.c +@@ -0,0 +1,183 @@ ++/* ++ * Broadcom specific AMBA ++ * System on Chip (SoC) Host ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include "bcma_private.h" ++#include "scan.h" ++#include <linux/bcma/bcma.h> ++#include <linux/bcma/bcma_soc.h> ++ ++static u8 bcma_host_soc_read8(struct bcma_device *core, u16 offset) ++{ ++ return readb(core->io_addr + offset); ++} ++ ++static u16 bcma_host_soc_read16(struct bcma_device *core, u16 offset) ++{ ++ return readw(core->io_addr + offset); ++} ++ ++static u32 bcma_host_soc_read32(struct bcma_device *core, u16 offset) ++{ ++ return readl(core->io_addr + offset); ++} ++ ++static void bcma_host_soc_write8(struct bcma_device *core, u16 offset, ++ u8 value) ++{ ++ writeb(value, core->io_addr + offset); ++} ++ ++static void bcma_host_soc_write16(struct bcma_device *core, u16 offset, ++ u16 value) ++{ ++ writew(value, core->io_addr + offset); ++} ++ ++static void bcma_host_soc_write32(struct bcma_device *core, u16 offset, ++ u32 value) ++{ ++ writel(value, core->io_addr + offset); ++} ++ ++#ifdef CONFIG_BCMA_BLOCKIO ++static void bcma_host_soc_block_read(struct bcma_device *core, void *buffer, ++ size_t count, u16 offset, u8 reg_width) ++{ ++ void __iomem *addr = core->io_addr + offset; ++ ++ switch (reg_width) { ++ case sizeof(u8): { ++ u8 *buf = buffer; ++ ++ while (count) { ++ *buf = __raw_readb(addr); ++ buf++; ++ count--; ++ } ++ break; ++ } ++ case sizeof(u16): { ++ __le16 *buf = buffer; ++ ++ WARN_ON(count & 1); ++ while (count) { ++ *buf = (__force __le16)__raw_readw(addr); ++ buf++; ++ count -= 2; ++ } ++ break; ++ } ++ case sizeof(u32): { ++ __le32 *buf = buffer; ++ ++ WARN_ON(count & 3); ++ while (count) { ++ *buf = (__force __le32)__raw_readl(addr); ++ buf++; ++ count -= 4; ++ } ++ break; ++ } ++ default: ++ WARN_ON(1); ++ } ++} ++ ++static void bcma_host_soc_block_write(struct bcma_device *core, ++ const void *buffer, ++ size_t count, u16 offset, u8 reg_width) ++{ ++ void __iomem *addr = core->io_addr + offset; ++ ++ switch (reg_width) { ++ case sizeof(u8): { ++ const u8 *buf = buffer; ++ ++ while (count) { ++ __raw_writeb(*buf, addr); ++ buf++; ++ count--; ++ } ++ break; ++ } ++ case sizeof(u16): { ++ const __le16 *buf = buffer; ++ ++ WARN_ON(count & 1); ++ while (count) { ++ __raw_writew((__force u16)(*buf), addr); ++ buf++; ++ count -= 2; ++ } ++ break; ++ } ++ case sizeof(u32): { ++ const __le32 *buf = buffer; ++ ++ WARN_ON(count & 3); ++ while (count) { ++ __raw_writel((__force u32)(*buf), addr); ++ buf++; ++ count -= 4; ++ } ++ break; ++ } ++ default: ++ WARN_ON(1); ++ } ++} ++#endif /* CONFIG_BCMA_BLOCKIO */ ++ ++static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset) ++{ ++ return readl(core->io_wrap + offset); ++} ++ ++static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset, ++ u32 value) ++{ ++ writel(value, core->io_wrap + offset); ++} ++ ++const struct bcma_host_ops bcma_host_soc_ops = { ++ .read8 = bcma_host_soc_read8, ++ .read16 = bcma_host_soc_read16, ++ .read32 = bcma_host_soc_read32, ++ .write8 = bcma_host_soc_write8, ++ .write16 = bcma_host_soc_write16, ++ .write32 = bcma_host_soc_write32, ++#ifdef CONFIG_BCMA_BLOCKIO ++ .block_read = bcma_host_soc_block_read, ++ .block_write = bcma_host_soc_block_write, ++#endif ++ .aread32 = bcma_host_soc_aread32, ++ .awrite32 = bcma_host_soc_awrite32, ++}; ++ ++int __init bcma_host_soc_register(struct bcma_soc *soc) ++{ ++ struct bcma_bus *bus = &soc->bus; ++ int err; ++ ++ /* iomap only first core. We have to read some register on this core ++ * to scan the bus. ++ */ ++ bus->mmio = ioremap_nocache(BCMA_ADDR_BASE, BCMA_CORE_SIZE * 1); ++ if (!bus->mmio) ++ return -ENOMEM; ++ ++ /* Host specific */ ++ bus->hosttype = BCMA_HOSTTYPE_SOC; ++ bus->ops = &bcma_host_soc_ops; ++ ++ /* Register */ ++ err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips); ++ if (err) ++ iounmap(bus->mmio); ++ ++ return err; ++} +--- /dev/null ++++ b/include/linux/bcma/bcma_driver_mips.h +@@ -0,0 +1,51 @@ ++#ifndef LINUX_BCMA_DRIVER_MIPS_H_ ++#define LINUX_BCMA_DRIVER_MIPS_H_ ++ ++#define BCMA_MIPS_IPSFLAG 0x0F08 ++/* which sbflags get routed to mips interrupt 1 */ ++#define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F ++#define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0 ++/* which sbflags get routed to mips interrupt 2 */ ++#define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00 ++#define BCMA_MIPS_IPSFLAG_IRQ2_SHIFT 8 ++/* which sbflags get routed to mips interrupt 3 */ ++#define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000 ++#define BCMA_MIPS_IPSFLAG_IRQ3_SHIFT 16 ++/* which sbflags get routed to mips interrupt 4 */ ++#define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000 ++#define BCMA_MIPS_IPSFLAG_IRQ4_SHIFT 24 ++ ++/* MIPS 74K core registers */ ++#define BCMA_MIPS_MIPS74K_CORECTL 0x0000 ++#define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004 ++#define BCMA_MIPS_MIPS74K_BIST 0x000C ++#define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014 ++#define BCMA_MIPS_MIPS74K_INTMASK(int) \ ++ ((int) * 4 + BCMA_MIPS_MIPS74K_INTMASK_INT0) ++#define BCMA_MIPS_MIPS74K_NMIMASK 0x002C ++#define BCMA_MIPS_MIPS74K_GPIOSEL 0x0040 ++#define BCMA_MIPS_MIPS74K_GPIOOUT 0x0044 ++#define BCMA_MIPS_MIPS74K_GPIOEN 0x0048 ++#define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0 ++ ++#define BCMA_MIPS_OOBSELOUTA30 0x100 ++ ++struct bcma_device; ++ ++struct bcma_drv_mips { ++ struct bcma_device *core; ++ u8 setup_done:1; ++ unsigned int assigned_irqs; ++}; ++ ++#ifdef CONFIG_BCMA_DRIVER_MIPS ++extern void bcma_core_mips_init(struct bcma_drv_mips *mcore); ++#else ++static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { } ++#endif ++ ++extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore); ++ ++extern unsigned int bcma_core_mips_irq(struct bcma_device *dev); ++ ++#endif /* LINUX_BCMA_DRIVER_MIPS_H_ */ +--- /dev/null ++++ b/include/linux/bcma/bcma_soc.h +@@ -0,0 +1,16 @@ ++#ifndef LINUX_BCMA_SOC_H_ ++#define LINUX_BCMA_SOC_H_ ++ ++#include <linux/bcma/bcma.h> ++ ++struct bcma_soc { ++ struct bcma_bus bus; ++ struct bcma_device core_cc; ++ struct bcma_device core_mips; ++}; ++ ++int __init bcma_host_soc_register(struct bcma_soc *soc); ++ ++int bcma_bus_register(struct bcma_bus *bus); ++ ++#endif /* LINUX_BCMA_SOC_H_ */ diff --git a/target/linux/generic/patches-2.6.32/975-ssb_update.patch b/target/linux/generic/patches-2.6.32/975-ssb_update.patch index 0dc9bafb5c..a619e6cc6b 100644 --- a/target/linux/generic/patches-2.6.32/975-ssb_update.patch +++ b/target/linux/generic/patches-2.6.32/975-ssb_update.patch @@ -1,5 +1,14 @@ --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c +@@ -3,7 +3,7 @@ + * Broadcom ChipCommon core driver + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2006, 2007, Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb if (!ccdev) return; @@ -146,6 +155,15 @@ { --- a/drivers/ssb/driver_chipcommon_pmu.c +++ b/drivers/ssb/driver_chipcommon_pmu.c +@@ -2,7 +2,7 @@ + * Sonics Silicon Backplane + * Broadcom ChipCommon Power Management Unit driver + * +- * Copyright 2009, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2009, Michael Buesch <m@bues.ch> + * Copyright 2007, Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_ case 0x5354: ssb_pmu0_pllinit_r0(cc, crystalfreq); @@ -212,6 +230,15 @@ } --- a/drivers/ssb/driver_gige.c +++ b/drivers/ssb/driver_gige.c +@@ -3,7 +3,7 @@ + * Broadcom Gigabit Ethernet core driver + * + * Copyright 2008, Broadcom Corporation +- * Copyright 2008, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2008, Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -12,6 +12,7 @@ #include <linux/ssb/ssb_driver_gige.h> #include <linux/pci.h> @@ -256,6 +283,15 @@ u32 base, tmslow, tmshigh; --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c +@@ -3,7 +3,7 @@ + * Broadcom MIPS core driver + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2006, 2007, Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco set_irq(dev, irq++); } @@ -277,6 +313,15 @@ ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); --- a/drivers/ssb/driver_pcicore.c +++ b/drivers/ssb/driver_pcicore.c +@@ -3,7 +3,7 @@ + * Broadcom PCI-core driver + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2006, 2007, Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -15,6 +15,11 @@ #include "ssb_private.h" @@ -356,7 +401,7 @@ { struct ssb_bus *bus = pc->dev->bus; u16 chipid_top; -@@ -432,25 +408,133 @@ static int pcicore_is_in_hostmode(struct +@@ -432,25 +408,137 @@ static int pcicore_is_in_hostmode(struct } #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ @@ -469,10 +514,15 @@ -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) { -+ ssb_pcicore_fix_sprom_core_index(pc); ++ struct ssb_device *pdev = pc->dev; ++ struct ssb_bus *bus = pdev->bus; ++ ++ if (bus->bustype == SSB_BUSTYPE_PCI) ++ ssb_pcicore_fix_sprom_core_index(pc); + /* Disable PCI interrupts. */ - ssb_write32(pc->dev, SSB_INTVEC, 0); +- ssb_write32(pc->dev, SSB_INTVEC, 0); ++ ssb_write32(pdev, SSB_INTVEC, 0); + + /* Additional PCIe always once-executed workarounds */ + if (pc->dev->id.coreid == SSB_DEV_PCIE) { @@ -494,7 +544,7 @@ if (!ssb_device_is_enabled(dev)) ssb_device_enable(dev, 0); -@@ -475,58 +559,104 @@ static void ssb_pcie_write(struct ssb_pc +@@ -475,58 +563,104 @@ static void ssb_pcie_write(struct ssb_pc pcicore_write32(pc, 0x134, data); } @@ -624,7 +674,7 @@ } int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, -@@ -551,13 +681,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc +@@ -551,13 +685,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc might_sleep_if(pdev->id.coreid != SSB_DEV_PCI); /* Enable interrupts for this device. */ @@ -640,7 +690,7 @@ err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); if (err) goto out; -@@ -579,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc +@@ -579,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc if (pc->setup_done) goto out; if (pdev->id.coreid == SSB_DEV_PCI) { @@ -693,7 +743,23 @@ out: --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c -@@ -18,6 +18,7 @@ +@@ -3,7 +3,7 @@ + * Subsystem core + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2006, 2007, Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +@@ -12,12 +12,14 @@ + + #include <linux/delay.h> + #include <linux/io.h> ++#include <linux/module.h> + #include <linux/ssb/ssb.h> + #include <linux/ssb/ssb_regs.h> + #include <linux/ssb/ssb_driver_gige.h> #include <linux/dma-mapping.h> #include <linux/pci.h> #include <linux/mmc/sdio_func.h> @@ -701,7 +767,7 @@ #include <pcmcia/cs_types.h> #include <pcmcia/cs.h> -@@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de +@@ -140,6 +142,19 @@ static void ssb_device_put(struct ssb_de put_device(dev->dev); } @@ -721,7 +787,7 @@ static int ssb_device_resume(struct device *dev) { struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); -@@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus) +@@ -210,90 +225,81 @@ int ssb_bus_suspend(struct ssb_bus *bus) EXPORT_SYMBOL(ssb_bus_suspend); #ifdef CONFIG_SSB_SPROM @@ -776,13 +842,13 @@ - if (!dev->dev || - !dev->dev->driver || - !device_is_registered(dev->dev)) -- continue; -- drv = drv_to_ssb_drv(dev->dev->driver); -- if (!drv) + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver)); + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) { + ssb_device_put(sdev); continue; +- drv = drv_to_ssb_drv(dev->dev->driver); +- if (!drv) +- continue; - err = drv->suspend(dev, state); - if (err) { - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n", @@ -864,7 +930,7 @@ } #endif /* CONFIG_SSB_SPROM */ -@@ -380,6 +385,35 @@ static int ssb_device_uevent(struct devi +@@ -380,6 +386,35 @@ static int ssb_device_uevent(struct devi ssb_dev->id.revision); } @@ -900,7 +966,7 @@ static struct bus_type ssb_bustype = { .name = "ssb", .match = ssb_bus_match, -@@ -389,6 +423,7 @@ static struct bus_type ssb_bustype = { +@@ -389,6 +424,7 @@ static struct bus_type ssb_bustype = { .suspend = ssb_device_suspend, .resume = ssb_device_resume, .uevent = ssb_device_uevent, @@ -908,7 +974,7 @@ }; static void ssb_buses_lock(void) -@@ -481,6 +516,7 @@ static int ssb_devices_register(struct s +@@ -481,6 +517,7 @@ static int ssb_devices_register(struct s #ifdef CONFIG_SSB_PCIHOST sdev->irq = bus->host_pci->irq; dev->parent = &bus->host_pci->dev; @@ -916,7 +982,7 @@ #endif break; case SSB_BUSTYPE_PCMCIA: -@@ -490,13 +526,13 @@ static int ssb_devices_register(struct s +@@ -490,13 +527,13 @@ static int ssb_devices_register(struct s #endif break; case SSB_BUSTYPE_SDIO: @@ -932,7 +998,7 @@ break; } -@@ -523,7 +559,7 @@ error: +@@ -523,7 +560,7 @@ error: } /* Needs ssb_buses_lock() */ @@ -941,7 +1007,7 @@ { struct ssb_bus *bus, *n; int err = 0; -@@ -734,9 +770,9 @@ out: +@@ -734,9 +771,9 @@ out: return err; } @@ -954,7 +1020,7 @@ { int err; -@@ -817,8 +853,8 @@ err_disable_xtal: +@@ -817,8 +854,8 @@ err_disable_xtal: } #ifdef CONFIG_SSB_PCIHOST @@ -965,7 +1031,7 @@ { int err; -@@ -830,6 +866,9 @@ int ssb_bus_pcibus_register(struct ssb_b +@@ -830,6 +867,9 @@ int ssb_bus_pcibus_register(struct ssb_b if (!err) { ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " "PCI device %s\n", dev_name(&host_pci->dev)); @@ -975,7 +1041,7 @@ } return err; -@@ -838,9 +877,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register); +@@ -838,9 +878,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register); #endif /* CONFIG_SSB_PCIHOST */ #ifdef CONFIG_SSB_PCMCIAHOST @@ -988,7 +1054,7 @@ { int err; -@@ -860,8 +899,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register +@@ -860,8 +900,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register #endif /* CONFIG_SSB_PCMCIAHOST */ #ifdef CONFIG_SSB_SDIOHOST @@ -1000,7 +1066,7 @@ { int err; -@@ -881,9 +921,9 @@ int ssb_bus_sdiobus_register(struct ssb_ +@@ -881,9 +922,9 @@ int ssb_bus_sdiobus_register(struct ssb_ EXPORT_SYMBOL(ssb_bus_sdiobus_register); #endif /* CONFIG_SSB_PCMCIAHOST */ @@ -1013,7 +1079,7 @@ { int err; -@@ -964,8 +1004,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 +@@ -964,8 +1005,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 switch (plltype) { case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ if (m & SSB_CHIPCO_CLK_T6_MMASK) @@ -1024,7 +1090,7 @@ case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ -@@ -1080,23 +1120,22 @@ static u32 ssb_tmslow_reject_bitmask(str +@@ -1080,23 +1121,22 @@ static u32 ssb_tmslow_reject_bitmask(str { u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; @@ -1055,7 +1121,7 @@ } int ssb_device_is_enabled(struct ssb_device *dev) -@@ -1155,10 +1194,10 @@ void ssb_device_enable(struct ssb_device +@@ -1155,10 +1195,10 @@ void ssb_device_enable(struct ssb_device } EXPORT_SYMBOL(ssb_device_enable); @@ -1069,7 +1135,7 @@ { int i; u32 val; -@@ -1166,7 +1205,7 @@ static int ssb_wait_bit(struct ssb_devic +@@ -1166,7 +1206,7 @@ static int ssb_wait_bit(struct ssb_devic for (i = 0; i < timeout; i++) { val = ssb_read32(dev, reg); if (set) { @@ -1078,7 +1144,7 @@ return 0; } else { if (!(val & bitmask)) -@@ -1183,20 +1222,38 @@ static int ssb_wait_bit(struct ssb_devic +@@ -1183,20 +1223,38 @@ static int ssb_wait_bit(struct ssb_devic void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) { @@ -1126,19 +1192,43 @@ ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_RESET | -@@ -1211,7 +1268,10 @@ u32 ssb_dma_translation(struct ssb_devic +@@ -1205,13 +1263,34 @@ void ssb_device_disable(struct ssb_devic + } + EXPORT_SYMBOL(ssb_device_disable); + ++/* Some chipsets need routing known for PCIe and 64-bit DMA */ ++static bool ssb_dma_translation_special_bit(struct ssb_device *dev) ++{ ++ u16 chip_id = dev->bus->chip_id; ++ ++ if (dev->id.coreid == SSB_DEV_80211) { ++ return (chip_id == 0x4322 || chip_id == 43221 || ++ chip_id == 43231 || chip_id == 43222); ++ } ++ ++ return 0; ++} ++ + u32 ssb_dma_translation(struct ssb_device *dev) + { + switch (dev->bus->bustype) { case SSB_BUSTYPE_SSB: return 0; case SSB_BUSTYPE_PCI: - return SSB_PCI_DMA; -+ if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) ++ if (dev->bus->host_pci->is_pcie && ++ ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { + return SSB_PCIE_DMA_H32; -+ else -+ return SSB_PCI_DMA; ++ } else { ++ if (ssb_dma_translation_special_bit(dev)) ++ return SSB_PCIE_DMA_H32; ++ else ++ return SSB_PCI_DMA; ++ } default: __ssb_dma_not_implemented(dev); } -@@ -1328,20 +1388,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown); +@@ -1328,20 +1407,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown); int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) { @@ -1163,7 +1253,7 @@ return 0; error: ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); -@@ -1349,6 +1409,37 @@ error: +@@ -1349,6 +1428,37 @@ error: } EXPORT_SYMBOL(ssb_bus_powerup); @@ -1203,6 +1293,15 @@ u32 base = 0; --- a/drivers/ssb/pci.c +++ b/drivers/ssb/pci.c +@@ -1,7 +1,7 @@ + /* + * Sonics Silicon Backplane PCI-Hostbus related functions. + * +- * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de> ++ * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch> + * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> + * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> + * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> @@ -17,6 +17,7 @@ #include <linux/ssb/ssb.h> @@ -1291,16 +1390,39 @@ /* TODO - get remaining rev 4 stuff needed */ } -@@ -560,6 +607,8 @@ static void sprom_extract_r8(struct ssb_ +@@ -560,6 +607,31 @@ static void sprom_extract_r8(struct ssb_ memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, sizeof(out->antenna_gain.ghz5)); ++ /* Extract FEM info */ ++ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ ++ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ + sprom_extract_r458(out, in); + /* TODO - get remaining rev 8 stuff needed */ } -@@ -572,37 +621,34 @@ static int sprom_extract(struct ssb_bus +@@ -572,37 +644,34 @@ static int sprom_extract(struct ssb_bus ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision); memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ memset(out->et1mac, 0xFF, 6); @@ -1359,7 +1481,7 @@ } if (out->boardflags_lo == 0xFFFF) -@@ -616,15 +662,14 @@ static int sprom_extract(struct ssb_bus +@@ -616,15 +685,14 @@ static int sprom_extract(struct ssb_bus static int ssb_pci_sprom_get(struct ssb_bus *bus, struct ssb_sprom *sprom) { @@ -1377,7 +1499,7 @@ /* * get SPROM offset: SSB_SPROM_BASE1 except for * chipcommon rev >= 31 or chip ID is 0x4312 and -@@ -644,7 +689,7 @@ static int ssb_pci_sprom_get(struct ssb_ +@@ -644,7 +712,7 @@ static int ssb_pci_sprom_get(struct ssb_ buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); if (!buf) @@ -1386,7 +1508,7 @@ bus->sprom_size = SSB_SPROMSIZE_WORDS_R123; sprom_do_read(bus, buf); err = sprom_check_crc(buf, bus->sprom_size); -@@ -654,17 +699,24 @@ static int ssb_pci_sprom_get(struct ssb_ +@@ -654,17 +722,24 @@ static int ssb_pci_sprom_get(struct ssb_ buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), GFP_KERNEL); if (!buf) @@ -1416,7 +1538,7 @@ err = 0; goto out_free; } -@@ -676,19 +728,15 @@ static int ssb_pci_sprom_get(struct ssb_ +@@ -676,19 +751,15 @@ static int ssb_pci_sprom_get(struct ssb_ out_free: kfree(buf); @@ -1441,7 +1563,14 @@ int ssb_pci_get_invariants(struct ssb_bus *bus, --- a/drivers/ssb/pcihost_wrapper.c +++ b/drivers/ssb/pcihost_wrapper.c -@@ -12,6 +12,7 @@ +@@ -6,12 +6,13 @@ + * Copyright (c) 2005 Stefano Brivio <st3@riseup.net> + * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> + * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> +- * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de> ++ * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. */ #include <linux/pci.h> @@ -1489,6 +1618,15 @@ driver->remove = ssb_pcihost_remove; --- a/drivers/ssb/pcmcia.c +++ b/drivers/ssb/pcmcia.c +@@ -3,7 +3,7 @@ + * PCMCIA-Hostbus related functions + * + * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> +- * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de> ++ * Copyright 2007-2008 Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co } \ } while (0) @@ -1498,10 +1636,7 @@ +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev, + tuple_t *tuple, + void *priv) - { -- tuple_t tuple; -- int res; -- unsigned char buf[32]; ++{ + struct ssb_sprom *sprom = priv; + + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID) @@ -1517,7 +1652,10 @@ +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev, + tuple_t *tuple, + void *priv) -+{ + { +- tuple_t tuple; +- int res; +- unsigned char buf[32]; + struct ssb_init_invariants *iv = priv; struct ssb_sprom *sprom = &iv->sprom; struct ssb_boardinfo *bi = &iv->boardinfo; @@ -1746,6 +1884,15 @@ --- a/drivers/ssb/scan.c +++ b/drivers/ssb/scan.c +@@ -2,7 +2,7 @@ + * Sonics Silicon Backplane + * Bus scanning + * +- * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de> ++ * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch> + * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> + * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> + * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> @@ -260,7 +260,10 @@ static int we_support_multiple_80211_cor #ifdef CONFIG_SSB_PCIHOST if (bus->bustype == SSB_BUSTYPE_PCI) { @@ -1796,6 +1943,15 @@ } --- a/drivers/ssb/sprom.c +++ b/drivers/ssb/sprom.c +@@ -2,7 +2,7 @@ + * Sonics Silicon Backplane + * Common SPROM support routines + * +- * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de> ++ * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch> + * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> + * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> + * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> @@ -14,9 +14,10 @@ #include "ssb_private.h" @@ -1842,34 +1998,36 @@ /** - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found. +- * +- * @sprom: The SPROM data structure to register. + * ssb_arch_register_fallback_sprom - Registers a method providing a + * fallback SPROM if no SPROM is found. * -- * @sprom: The SPROM data structure to register. -+ * @sprom_callback: The callback function. - * - * With this function the architecture implementation may register a fallback - * SPROM data structure. The fallback is only used for PCI based SSB devices, - * where no valid SPROM can be found in the shadow registers. ++ * @sprom_callback: The callback function. + * +- * This function is useful for weird architectures that have a half-assed SSB device +- * hardwired to their PCI bus. + * With this function the architecture implementation may register a + * callback handler which fills the SPROM data structure. The fallback is + * only used for PCI based SSB devices, where no valid SPROM can be found + * in the shadow registers. - * -- * This function is useful for weird architectures that have a half-assed SSB device -- * hardwired to their PCI bus. ++ * + * This function is useful for weird architectures that have a half-assed + * SSB device hardwired to their PCI bus. - * -- * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently -- * don't use this fallback. -- * Architectures must provide the SPROM for native SSB devices anyway, -- * so the fallback also isn't used for native devices. ++ * + * Note that it does only work with PCI attached SSB devices. PCMCIA + * devices currently don't use this fallback. + * Architectures must provide the SPROM for native SSB devices anyway, so + * the fallback also isn't used for native devices. * +- * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently +- * don't use this fallback. +- * Architectures must provide the SPROM for native SSB devices anyway, +- * so the fallback also isn't used for native devices. +- * - * This function is available for architecture code, only. So it is not exported. + * This function is available for architecture code, only. So it is not + * exported. @@ -1957,9 +2115,12 @@ #endif /* LINUX_SSB_PRIVATE_H_ */ --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h -@@ -27,6 +27,8 @@ struct ssb_sprom { +@@ -25,8 +25,10 @@ struct ssb_sprom { + u8 et1phyaddr; /* MII address for enet1 */ + u8 et0mdcport; /* MDIO for enet0 */ u8 et1mdcport; /* MDIO for enet1 */ - u8 board_rev; /* Board revision number from SPROM. */ +- u8 board_rev; /* Board revision number from SPROM. */ ++ u16 board_rev; /* Board revision number from SPROM. */ u8 country_code; /* Country Code */ + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */ + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ @@ -1977,7 +2138,23 @@ u8 rxpo2g; /* 2GHz RX power offset */ u8 rxpo5g; /* 5GHz RX power offset */ u8 rssisav2g; /* 2GHz RSSI params */ -@@ -95,7 +101,7 @@ struct ssb_sprom { +@@ -88,6 +94,15 @@ struct ssb_sprom { + } ghz5; /* 5GHz band */ + } antenna_gain; + ++ struct { ++ struct { ++ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; ++ } ghz2; ++ struct { ++ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; ++ } ghz5; ++ } fem; ++ + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */ + }; + +@@ -95,7 +110,7 @@ struct ssb_sprom { struct ssb_boardinfo { u16 vendor; u16 type; @@ -1986,7 +2163,7 @@ }; -@@ -167,7 +173,7 @@ struct ssb_device { +@@ -167,7 +182,7 @@ struct ssb_device { * is an optimization. */ const struct ssb_bus_ops *ops; @@ -1995,7 +2172,21 @@ struct ssb_bus *bus; struct ssb_device_id id; -@@ -269,7 +275,8 @@ struct ssb_bus { +@@ -225,10 +240,9 @@ struct ssb_driver { + #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv) + + extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner); +-static inline int ssb_driver_register(struct ssb_driver *drv) +-{ +- return __ssb_driver_register(drv, THIS_MODULE); +-} ++#define ssb_driver_register(drv) \ ++ __ssb_driver_register(drv, THIS_MODULE) ++ + extern void ssb_driver_unregister(struct ssb_driver *drv); + + +@@ -269,7 +283,8 @@ struct ssb_bus { const struct ssb_bus_ops *ops; @@ -2005,7 +2196,7 @@ struct ssb_device *mapped_device; union { /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */ -@@ -281,14 +288,17 @@ struct ssb_bus { +@@ -281,14 +296,17 @@ struct ssb_bus { * On PCMCIA-host busses this is used to protect the whole MMIO access. */ spinlock_t bar_lock; @@ -2030,7 +2221,7 @@ /* See enum ssb_quirks */ unsigned int quirks; -@@ -300,7 +310,7 @@ struct ssb_bus { +@@ -300,7 +318,7 @@ struct ssb_bus { /* ID information about the Chip. */ u16 chip_id; @@ -2039,7 +2230,7 @@ u16 sprom_offset; u16 sprom_size; /* number of words in sprom */ u8 chip_package; -@@ -396,7 +406,9 @@ extern bool ssb_is_sprom_available(struc +@@ -396,7 +414,9 @@ extern bool ssb_is_sprom_available(struc /* Set a fallback SPROM. * See kdoc at the function definition for complete documentation. */ @@ -2050,7 +2241,7 @@ /* Suspend a SSB bus. * Call this from the parent bus suspend routine. */ -@@ -667,6 +679,7 @@ extern int ssb_bus_may_powerdown(struct +@@ -667,6 +687,7 @@ extern int ssb_bus_may_powerdown(struct * Otherwise static always-on powercontrol will be used. */ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl); @@ -2416,7 +2607,7 @@ #define SSB_SPROM8_RSSISMF5G 0x000F #define SSB_SPROM8_RSSISMC5G 0x00F0 #define SSB_SPROM8_RSSISMC5G_SHIFT 4 -@@ -374,47 +420,47 @@ +@@ -374,47 +420,104 @@ #define SSB_SPROM8_RSSISAV5G_SHIFT 8 #define SSB_SPROM8_BXA5G 0x1800 #define SSB_SPROM8_BXA5G_SHIFT 11 @@ -2436,6 +2627,23 @@ #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ #define SSB_SPROM8_RXPO5G_SHIFT 8 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */ ++#define SSB_SPROM8_FEM2G 0x00AE ++#define SSB_SPROM8_FEM5G 0x00B0 ++#define SSB_SROM8_FEM_TSSIPOS 0x0001 ++#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0 ++#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006 ++#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1 ++#define SSB_SROM8_FEM_PDET_RANGE 0x00F8 ++#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3 ++#define SSB_SROM8_FEM_TR_ISO 0x0700 ++#define SSB_SROM8_FEM_TR_ISO_SHIFT 8 ++#define SSB_SROM8_FEM_ANTSWLUT 0xF800 ++#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11 ++#define SSB_SPROM8_THERMAL 0x00B2 ++#define SSB_SPROM8_MPWR_RAWTS 0x00B4 ++#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6 ++#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8 ++#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ @@ -2484,11 +2692,60 @@ +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */ +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */ +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */ ++ ++/* Values for boardflags_lo read from SPROM */ ++#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ ++#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ ++#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ ++#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ ++#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ ++#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ ++#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ ++#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */ ++#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */ ++#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ ++#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */ ++#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */ ++#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */ ++#define SSB_BFL_HGPA 0x2000 /* had high gain PA */ ++#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ ++#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ ++ ++/* Values for boardflags_hi read from SPROM */ ++#define SSB_BFH_NOPA 0x0001 /* has no PA */ ++#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */ ++#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */ ++#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */ ++#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */ ++#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */ ++#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */ ++ ++/* Values for boardflags2_lo read from SPROM */ ++#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */ ++#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */ ++#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */ ++#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */ ++#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */ ++#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */ ++#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */ ++#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */ ++#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */ ++#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */ ++#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */ /* Values for SSB_SPROM1_BINF_CCODE */ enum { --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h +@@ -8,7 +8,7 @@ + * gpio interface, extbus, and support for serial and parallel flashes. + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2006, Michael Buesch <m@bues.ch> + * + * Licensed under the GPL version 2. See COPYING for details. + */ @@ -123,6 +123,8 @@ #define SSB_CHIPCO_FLASHDATA 0x0048 #define SSB_CHIPCO_BCAST_ADDR 0x0050 @@ -2521,3 +2778,53 @@ #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ #define SSB_CHIPCO_UART0_DATA 0x0300 #define SSB_CHIPCO_UART0_IMR 0x0304 +--- a/drivers/ssb/b43_pci_bridge.c ++++ b/drivers/ssb/b43_pci_bridge.c +@@ -5,12 +5,13 @@ + * because of its small size we include it in the SSB core + * instead of creating a standalone module. + * +- * Copyright 2007 Michael Buesch <mb@bu3sch.de> ++ * Copyright 2007 Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + + #include <linux/pci.h> ++#include <linux/module.h> + #include <linux/ssb/ssb.h> + + #include "ssb_private.h" +--- a/drivers/ssb/driver_extif.c ++++ b/drivers/ssb/driver_extif.c +@@ -3,7 +3,7 @@ + * Broadcom EXTIF core driver + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2006, 2007, Michael Buesch <m@bues.ch> + * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org> + * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net> + * +--- a/drivers/ssb/embedded.c ++++ b/drivers/ssb/embedded.c +@@ -3,7 +3,7 @@ + * Embedded systems support code + * + * Copyright 2005-2008, Broadcom Corporation +- * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de> ++ * Copyright 2006-2008, Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +--- a/drivers/ssb/sdio.c ++++ b/drivers/ssb/sdio.c +@@ -6,7 +6,7 @@ + * + * Based on drivers/ssb/pcmcia.c + * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> +- * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de> ++ * Copyright 2007-2008 Michael Buesch <m@bues.ch> + * + * Licensed under the GNU/GPL. See COPYING for details. + * |