diff options
Diffstat (limited to 'target/linux/ar71xx')
11 files changed, 238 insertions, 32 deletions
diff --git a/target/linux/ar71xx/patches-3.3/137-MIPS-ath79-fix-CPU-DDR-frequency-calculation-for-SRI.patch b/target/linux/ar71xx/patches-3.3/137-MIPS-ath79-fix-CPU-DDR-frequency-calculation-for-SRI.patch new file mode 100644 index 0000000000..a2fa4db56c --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/137-MIPS-ath79-fix-CPU-DDR-frequency-calculation-for-SRI.patch @@ -0,0 +1,205 @@ +From 3f735e202d5099a5b7c621443bea365b87b0e3bb Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sat, 8 Sep 2012 12:12:50 +0200 +Subject: [PATCH] MIPS: ath79: fix CPU/DDR frequency calculation for SRIF PLLs + +Besides the CPU and DDR PLLs, the CPU and DDR frequencies +can be derived from other PLLs in the SRIF block on the +AR934x SoCs. The current code does not checks if the SRIF +PLLs are used and this can lead to incorrectly calculated +CPU/DDR frequencies. + +Fix it by calculating the frequencies from SRIF PLLs if +those are used on a given board. + +Cc: <stable@vger.kernel.org> +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- +This depends on the following patch: +'MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x' +https://patchwork.linux-mips.org/patch/4305/ + + arch/mips/ath79/clock.c | 109 ++++++++++++++++++------ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 23 +++++ + 2 files changed, 104 insertions(+), 28 deletions(-) + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -17,6 +17,8 @@ + #include <linux/err.h> + #include <linux/clk.h> + ++#include <asm/div64.h> ++ + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/ar71xx_regs.h> + #include "common.h" +@@ -166,11 +168,34 @@ static void __init ar933x_clocks_init(vo + ath79_uart_clk.rate = ath79_ref_clk.rate; + } + ++static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, ++ u32 frac, u32 out_div) ++{ ++ u64 t; ++ u32 ret; ++ ++ t = ath79_ref_clk.rate; ++ t *= nint; ++ do_div(t, ref_div); ++ ret = t; ++ ++ t = ath79_ref_clk.rate; ++ t *= nfrac; ++ do_div(t, ref_div * frac); ++ ret += t; ++ ++ ret /= (1 << out_div); ++ return ret; ++} ++ + static void __init ar934x_clocks_init(void) + { +- u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; + u32 cpu_pll, ddr_pll; + u32 bootstrap; ++ void __iomem *dpll_base; ++ ++ dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE); + + bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); + if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) +@@ -178,33 +203,59 @@ static void __init ar934x_clocks_init(vo + else + ath79_ref_clk.rate = 25 * 1000 * 1000; + +- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); +- out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & +- AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; +- ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & +- AR934X_PLL_CPU_CONFIG_REFDIV_MASK; +- nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & +- AR934X_PLL_CPU_CONFIG_NINT_MASK; +- frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & +- AR934X_PLL_CPU_CONFIG_NFRAC_MASK; +- +- cpu_pll = nint * ath79_ref_clk.rate / ref_div; +- cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); +- cpu_pll /= (1 << out_div); +- +- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); +- out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & +- AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; +- ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & +- AR934X_PLL_DDR_CONFIG_REFDIV_MASK; +- nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & +- AR934X_PLL_DDR_CONFIG_NINT_MASK; +- frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & +- AR934X_PLL_DDR_CONFIG_NFRAC_MASK; +- +- ddr_pll = nint * ath79_ref_clk.rate / ref_div; +- ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); +- ddr_pll /= (1 << out_div); ++ pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); ++ if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { ++ out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & ++ AR934X_SRIF_DPLL2_OUTDIV_MASK; ++ pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); ++ nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & ++ AR934X_SRIF_DPLL1_NINT_MASK; ++ nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; ++ ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & ++ AR934X_SRIF_DPLL1_REFDIV_MASK; ++ frac = 1 << 18; ++ } else { ++ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_REFDIV_MASK; ++ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_NINT_MASK; ++ nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_NFRAC_MASK; ++ frac = 1 << 6; ++ } ++ ++ cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, ++ nfrac, frac, out_div); ++ ++ pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); ++ if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { ++ out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & ++ AR934X_SRIF_DPLL2_OUTDIV_MASK; ++ pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); ++ nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & ++ AR934X_SRIF_DPLL1_NINT_MASK; ++ nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; ++ ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & ++ AR934X_SRIF_DPLL1_REFDIV_MASK; ++ frac = 1 << 18; ++ } else { ++ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_REFDIV_MASK; ++ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_NINT_MASK; ++ nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_NFRAC_MASK; ++ frac = 1 << 10; ++ } ++ ++ ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, ++ nfrac, frac, out_div); + + clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); + +@@ -240,6 +291,8 @@ static void __init ar934x_clocks_init(vo + + ath79_wdt_clk.rate = ath79_ref_clk.rate; + ath79_uart_clk.rate = ath79_ref_clk.rate; ++ ++ iounmap(dpll_base); + } + + void __init ath79_clocks_init(void) +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -65,6 +65,8 @@ + #define AR934X_WMAC_SIZE 0x20000 + #define AR934X_EHCI_BASE 0x1b000000 + #define AR934X_EHCI_SIZE 0x200 ++#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) ++#define AR934X_SRIF_SIZE 0x1000 + + /* + * DDR_CTRL block +@@ -405,4 +407,25 @@ + #define AR933X_GPIO_COUNT 30 + #define AR934X_GPIO_COUNT 23 + ++/* ++ * SRIF block ++ */ ++#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 ++#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 ++#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 ++ ++#define AR934X_SRIF_DDR_DPLL1_REG 0x240 ++#define AR934X_SRIF_DDR_DPLL2_REG 0x244 ++#define AR934X_SRIF_DDR_DPLL3_REG 0x248 ++ ++#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 ++#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f ++#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 ++#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff ++#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff ++ ++#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) ++#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 ++#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 ++ + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch b/target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch index 4f781ede34..7f1f2302f9 100644 --- a/target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch +++ b/target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch @@ -21,7 +21,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -368,6 +368,7 @@ +@@ -370,6 +370,7 @@ #define REV_ID_MAJOR_AR9341 0x0120 #define REV_ID_MAJOR_AR9342 0x1120 #define REV_ID_MAJOR_AR9344 0x2120 diff --git a/target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch b/target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch index e9b18e6563..1d9dd4beb4 100644 --- a/target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch +++ b/target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch @@ -53,7 +53,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -389,6 +389,8 @@ +@@ -391,6 +391,8 @@ #define AR934X_REV_ID_REVISION_MASK 0xf diff --git a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch index ff8be83888..289ec6d296 100644 --- a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch +++ b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch @@ -11,8 +11,8 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c -@@ -242,6 +242,82 @@ static void __init ar934x_clocks_init(vo - ath79_uart_clk.rate = ath79_ref_clk.rate; +@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo + iounmap(dpll_base); } +static void __init qca955x_clocks_init(void) @@ -94,7 +94,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> void __init ath79_clocks_init(void) { if (soc_is_ar71xx()) -@@ -254,6 +330,8 @@ void __init ath79_clocks_init(void) +@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void) ar933x_clocks_init(); else if (soc_is_ar934x()) ar934x_clocks_init(); @@ -105,7 +105,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -223,6 +223,41 @@ +@@ -225,6 +225,41 @@ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) @@ -147,7 +147,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> /* * USB_CONFIG block */ -@@ -262,6 +297,8 @@ +@@ -264,6 +299,8 @@ #define AR934X_RESET_REG_BOOTSTRAP 0xb0 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac @@ -156,7 +156,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) #define MISC_INT_TIMER3 BIT(9) -@@ -339,6 +376,8 @@ +@@ -341,6 +378,8 @@ #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) #define AR934X_BOOTSTRAP_DDR1 BIT(0) diff --git a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch index e4e2c30d94..8d24c742d3 100644 --- a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch +++ b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch @@ -165,7 +165,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> } --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -298,6 +298,7 @@ +@@ -300,6 +300,7 @@ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 @@ -173,7 +173,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) -@@ -396,6 +397,37 @@ +@@ -398,6 +399,37 @@ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ AR934X_PCIE_WMAC_INT_PCIE_RC3) diff --git a/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch index 9dba29a28d..dc4251be93 100644 --- a/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch +++ b/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch @@ -29,10 +29,11 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> } --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -504,5 +504,6 @@ +@@ -506,6 +506,7 @@ #define AR913X_GPIO_COUNT 22 #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_COUNT 23 +#define QCA955X_GPIO_COUNT 24 - #endif /* __ASM_MACH_AR71XX_REGS_H */ + /* + * SRIF block diff --git a/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch index 386d57c738..dd79296f60 100644 --- a/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch +++ b/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch @@ -80,9 +80,9 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> } --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -92,6 +92,10 @@ - #define AR934X_EHCI_BASE 0x1b000000 - #define AR934X_EHCI_SIZE 0x200 +@@ -94,6 +94,10 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 diff --git a/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch b/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch index 6ff1034faa..5f88238267 100644 --- a/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch +++ b/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch @@ -59,9 +59,9 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -92,6 +92,8 @@ - #define AR934X_EHCI_BASE 0x1b000000 - #define AR934X_EHCI_SIZE 0x200 +@@ -94,6 +94,8 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 diff --git a/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch index c503a0da52..0c3889fdb9 100644 --- a/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch +++ b/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch @@ -81,9 +81,9 @@ Subject: [PATCH 26/34] MIPS: ath79: add PCI controller registration code for the return -ENODEV; --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -92,6 +92,19 @@ - #define AR934X_EHCI_BASE 0x1b000000 - #define AR934X_EHCI_SIZE 0x200 +@@ -94,6 +94,19 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch index 7166475e35..ce1b9c50af 100644 --- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch @@ -36,7 +36,7 @@ #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) #define AR934X_WMAC_SIZE 0x20000 #define AR934X_EHCI_BASE 0x1b000000 -@@ -110,6 +120,8 @@ +@@ -112,6 +122,8 @@ #define QCA955X_EHCI0_BASE 0x1b000000 #define QCA955X_EHCI1_BASE 0x1b400000 #define QCA955X_EHCI_SIZE 0x1000 @@ -45,7 +45,7 @@ /* * DDR_CTRL block -@@ -165,6 +177,9 @@ +@@ -167,6 +179,9 @@ #define AR71XX_AHB_DIV_SHIFT 20 #define AR71XX_AHB_DIV_MASK 0x7 @@ -55,7 +55,7 @@ #define AR724X_PLL_REG_CPU_CONFIG 0x00 #define AR724X_PLL_REG_PCIE_CONFIG 0x18 -@@ -177,6 +192,8 @@ +@@ -179,6 +194,8 @@ #define AR724X_DDR_DIV_SHIFT 22 #define AR724X_DDR_DIV_MASK 0x3 @@ -64,7 +64,7 @@ #define AR913X_PLL_REG_CPU_CONFIG 0x00 #define AR913X_PLL_REG_ETH_CONFIG 0x04 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 -@@ -189,6 +206,9 @@ +@@ -191,6 +208,9 @@ #define AR913X_AHB_DIV_SHIFT 19 #define AR913X_AHB_DIV_MASK 0x1 @@ -74,7 +74,7 @@ #define AR933X_PLL_CPU_CONFIG_REG 0x00 #define AR933X_PLL_CLOCK_CTRL_REG 0x08 -@@ -210,6 +230,7 @@ +@@ -212,6 +232,7 @@ #define AR934X_PLL_CPU_CONFIG_REG 0x00 #define AR934X_PLL_DDR_CONFIG_REG 0x04 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 @@ -82,7 +82,7 @@ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -368,16 +389,50 @@ +@@ -370,16 +391,50 @@ #define AR913X_RESET_USB_HOST BIT(5) #define AR913X_RESET_USB_PHY BIT(4) @@ -133,7 +133,7 @@ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -518,6 +573,14 @@ +@@ -520,6 +575,14 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 @@ -148,9 +148,9 @@ #define AR71XX_GPIO_COUNT 16 #define AR724X_GPIO_COUNT 18 #define AR913X_GPIO_COUNT 22 -@@ -525,4 +588,133 @@ - #define AR934X_GPIO_COUNT 23 - #define QCA955X_GPIO_COUNT 24 +@@ -548,4 +611,133 @@ + #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 + #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) diff --git a/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch index 0c24ff5b57..2ff6c3af57 100644 --- a/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch +++ b/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch @@ -149,7 +149,7 @@ #endif /* _ATH79_DEV_WMAC_H */ --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -123,6 +123,14 @@ +@@ -125,6 +125,14 @@ #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) #define QCA955X_GMAC_SIZE 0x40 |