diff options
| -rw-r--r-- | target/linux/brcm47xx/patches-2.6.23/220-bcm5354.patch | 58 | ||||
| -rw-r--r-- | target/linux/brcm47xx/patches-2.6.23/225-bcm5354_ssbrev.patch | 20 |
2 files changed, 78 insertions, 0 deletions
diff --git a/target/linux/brcm47xx/patches-2.6.23/220-bcm5354.patch b/target/linux/brcm47xx/patches-2.6.23/220-bcm5354.patch new file mode 100644 index 0000000000..ca31af912a --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.23/220-bcm5354.patch @@ -0,0 +1,58 @@ +--- files/drivers/ssb/driver_chipcommon.c 2007-10-24 16:57:38.000000000 -0700 ++++ linux-2.6.23.1/drivers/ssb/driver_chipcommon.c 2007-10-27 13:27:06.000000000 -0700 +@@ -268,6 +268,8 @@ + void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, + u32 *plltype, u32 *n, u32 *m) + { ++ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354) ++ return; + *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); + *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); + switch (*plltype) { +@@ -291,6 +293,8 @@ + void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, + u32 *plltype, u32 *n, u32 *m) + { ++ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354) ++ return; + *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); + *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); + switch (*plltype) { +@@ -387,7 +376,14 @@ + chipco_read32(cc, SSB_CHIPCO_CLOCK_M2)); + div = 1; + } else { +- if (cc->dev->id.revision >= 11) { ++ if (cc->dev->id.revision == 20) { ++ /* BCM5354 uses constant 25MHz clock */ ++ baud_base = 25000000; ++ div = 48; ++ /* Set the override bit so we don't divide it */ ++ chipco_write32(cc, SSB_CHIPCO_CORECTL, ++ SSB_CHIPCO_CORECTL_UARTCLK0); ++ } else if (cc->dev->id.revision >= 11) { + /* Fixed ALP clock */ + baud_base = 20000000; + div = 1; +--- files/drivers/ssb/driver_mipscore.c 2007-10-24 16:57:38.000000000 -0700 ++++ linux-2.6.23.1/drivers/ssb/driver_mipscore.c 2007-10-27 13:29:36.000000000 -0700 +@@ -160,6 +160,8 @@ + + if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) { + rate = 200000000; ++ } else if (bus->chip_id == 0x5354) { ++ rate = 240000000; + } else { + rate = ssb_calc_clock_rate(pll_type, n, m); + } +--- files/drivers/ssb/main.c 2007-10-24 16:57:38.000000000 -0700 ++++ linux-2.6.23.1/drivers/ssb/main.c 2007-10-27 13:30:59.000000000 -0700 +@@ -864,6 +864,8 @@ + + if (bus->chip_id == 0x5365) { + rate = 100000000; ++ } else if (bus->chip_id == 0x5354) { ++ rate = 120000000; + } else { + rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); + if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ diff --git a/target/linux/brcm47xx/patches-2.6.23/225-bcm5354_ssbrev.patch b/target/linux/brcm47xx/patches-2.6.23/225-bcm5354_ssbrev.patch new file mode 100644 index 0000000000..55209b395d --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.23/225-bcm5354_ssbrev.patch @@ -0,0 +1,20 @@ +--- a/drivers/ssb/main.c 2007-11-05 05:59:43.000000000 -0800 ++++ b/drivers/ssb/main.c 2007-11-05 08:59:13.000000000 -0800 +@@ -882,6 +884,7 @@ + case SSB_IDLOW_SSBREV_22: + return SSB_TMSLOW_REJECT_22; + case SSB_IDLOW_SSBREV_23: ++ case SSB_IDLOW_SSBREV_5354: + return SSB_TMSLOW_REJECT_23; + default: + WARN_ON(1); +--- a/include/linux/ssb/ssb_regs.h 2007-11-05 05:59:42.000000000 -0800 ++++ b/include/linux/ssb/ssb_regs.h 2007-11-05 09:00:45.000000000 -0800 +@@ -147,6 +147,7 @@ + #define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */ + #define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */ + #define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */ ++#define SSB_IDLOW_SSBREV_5354 0x60000000 /* 5354 */ + #define SSB_IDHIGH 0x0FFC /* SB Identification High */ + #define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ + #define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */ |