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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-07-24 20:37:50 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-07-24 20:37:50 +0000
commitea6e386f6f5bbad234c1ec138ba71e01b23ff77e (patch)
tree0c5f16afaac5b361c18502777986bb81167f234e /target
parentfe61983ee0c32dccd5343176d38845a694f320c3 (diff)
[ramips] uart_clk on Rt3352F is always 40MHz
Currently, sys_clk/10 is used which is just wrong. cpu_clk/10 would work for systems with 400MHz CPU clock. Signed-off-by: Daniel Golle <dgolle@allnet.de> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32812 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target')
-rw-r--r--target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
index 4a99cf39e2..958547611b 100644
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
@@ -60,7 +60,7 @@ void __init rt305x_clocks_init(void)
break;
}
rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
- rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10;
+ rt305x_uart_clk.rate = 40000000;
rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
} else {
BUG();