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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-10 20:26:15 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-10 20:26:15 +0000
commit77ce46e9f814db04fe1ea880f4446943cf40d28c (patch)
tree5a24ce8499858dc3fb45ddd472021c0709ee4d75 /target
parent80484c397265bbac637938c0505082641adf6cb1 (diff)
added CONFIG_DANUBE_PCI_HW_SWAP
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9705 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target')
-rw-r--r--target/linux/danube/files/arch/mips/danube/pci.c19
1 files changed, 17 insertions, 2 deletions
diff --git a/target/linux/danube/files/arch/mips/danube/pci.c b/target/linux/danube/files/arch/mips/danube/pci.c
index 3f7b7f8b87..1896336d81 100644
--- a/target/linux/danube/files/arch/mips/danube/pci.c
+++ b/target/linux/danube/files/arch/mips/danube/pci.c
@@ -77,15 +77,25 @@ danube_pci_config_access(unsigned char access_type,
/* Perform access */
if (access_type == PCI_ACCESS_WRITE)
{
+#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+ writel(swab32(*data), ((u32*)cfg_base));
+#else
writel(*data, ((u32*)cfg_base));
+#endif
} else {
*data = readl(((u32*)(cfg_base)));
+#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+ *data = swab32(*data);
+#endif
}
wmb();
/* clean possible Master abort */
cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
temp = readl(((u32*)(cfg_base)));
+#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+ temp = swab32 (temp);
+#endif
cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
writel(temp, ((u32*)cfg_base));
@@ -250,9 +260,14 @@ static void __init danube_pci_startup (void){
writel(0x0e000008, PCI_CR_BAR11MASK);
writel(0, PCI_CR_PCI_ADDR_MAP11);
writel(0, PCI_CS_BASE_ADDR1);
+#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+ /* both TX and RX endian swap are enabled */
+ DANUBE_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
+ wmb ();
+#endif
/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
- // writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
- // writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
+ writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
+ writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
/*use 8 dw burse length */
writel(0x303, PCI_CR_FCI_BURST_LENGTH);