diff options
| author | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-04-19 12:39:40 +0000 |
|---|---|---|
| committer | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-04-19 12:39:40 +0000 |
| commit | 01ca6e26f97769bf7e81ca0d0311d726ed0c00f3 (patch) | |
| tree | 1154d32bae6311f288b651ef5e23df029de445c9 /target/linux | |
| parent | 53ef695f50ba613668f815a3ca38d9f59877c3f3 (diff) | |
kernel: backport SSB/BCMA changes in preparation for a compat-wireless update
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@36367 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux')
15 files changed, 1264 insertions, 194 deletions
diff --git a/target/linux/brcm47xx/patches-3.6/060-ssb-add-serial-flash-driver.patch b/target/linux/brcm47xx/patches-3.6/060-ssb-add-serial-flash-driver.patch index c40a58ecaa..1dfb35dc21 100644 --- a/target/linux/brcm47xx/patches-3.6/060-ssb-add-serial-flash-driver.patch +++ b/target/linux/brcm47xx/patches-3.6/060-ssb-add-serial-flash-driver.patch @@ -476,7 +476,7 @@ #define SSB_CHIPCO_BCAST_ADDR 0x0050 #define SSB_CHIPCO_BCAST_DATA 0x0054 #define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */ -@@ -503,7 +516,7 @@ +@@ -504,7 +517,7 @@ #define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */ #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */ #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */ @@ -485,7 +485,7 @@ #define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */ #define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */ #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */ -@@ -594,6 +607,9 @@ struct ssb_chipcommon { +@@ -595,6 +608,9 @@ struct ssb_chipcommon { struct ssb_chipcommon_pmu pmu; u32 ticks_per_ms; u32 max_timer_ms; diff --git a/target/linux/brcm47xx/patches-3.6/070-bcma-add-functions-to-write-to-serial-flash.patch b/target/linux/brcm47xx/patches-3.6/070-bcma-add-functions-to-write-to-serial-flash.patch index 98cd795a52..9775879691 100644 --- a/target/linux/brcm47xx/patches-3.6/070-bcma-add-functions-to-write-to-serial-flash.patch +++ b/target/linux/brcm47xx/patches-3.6/070-bcma-add-functions-to-write-to-serial-flash.patch @@ -292,7 +292,7 @@ u32 id, id2; switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { -@@ -150,6 +375,12 @@ int bcma_sflash_init(struct bcma_drv_cc +@@ -150,6 +375,12 @@ int bcma_sflash_init(struct bcma_drv_cc sflash->numblocks = e->numblocks; sflash->size = sflash->blocksize * sflash->numblocks; sflash->present = true; @@ -316,7 +316,7 @@ /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF -@@ -519,17 +521,6 @@ struct bcma_pflash { +@@ -520,17 +522,6 @@ struct bcma_pflash { u32 window_size; }; @@ -334,7 +334,7 @@ #ifdef CONFIG_BCMA_NFLASH struct mtd_info; -@@ -564,7 +555,7 @@ struct bcma_drv_cc { +@@ -565,7 +556,7 @@ struct bcma_drv_cc { #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_pflash pflash; #ifdef CONFIG_BCMA_SFLASH diff --git a/target/linux/brcm47xx/patches-3.6/071-bcma-add-functions-to-write-to-nand-flash.patch b/target/linux/brcm47xx/patches-3.6/071-bcma-add-functions-to-write-to-nand-flash.patch index 7a21298236..60f27d9ea9 100644 --- a/target/linux/brcm47xx/patches-3.6/071-bcma-add-functions-to-write-to-nand-flash.patch +++ b/target/linux/brcm47xx/patches-3.6/071-bcma-add-functions-to-write-to-nand-flash.patch @@ -25,7 +25,7 @@ .num_resources = 0, }; -@@ -31,6 +38,11 @@ int bcma_nflash_init(struct bcma_drv_cc +@@ -31,6 +38,11 @@ int bcma_nflash_init(struct bcma_drv_cc return -ENODEV; } @@ -37,7 +37,7 @@ cc->nflash.present = true; if (cc->core->id.rev == 38 && (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) -@@ -42,3 +54,141 @@ int bcma_nflash_init(struct bcma_drv_cc +@@ -42,3 +54,141 @@ int bcma_nflash_init(struct bcma_drv_cc return 0; } @@ -189,7 +189,7 @@ /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 -@@ -522,17 +523,6 @@ struct bcma_pflash { +@@ -523,17 +524,6 @@ struct bcma_pflash { }; @@ -207,7 +207,7 @@ struct bcma_serial_port { void *regs; unsigned long clockspeed; -@@ -558,7 +548,7 @@ struct bcma_drv_cc { +@@ -559,7 +549,7 @@ struct bcma_drv_cc { struct bcm47xx_sflash sflash; #endif #ifdef CONFIG_BCMA_NFLASH @@ -216,7 +216,7 @@ #endif int nr_serial_ports; -@@ -625,4 +615,13 @@ extern void bcma_chipco_regctl_maskset(s +@@ -628,4 +618,13 @@ extern void bcma_chipco_regctl_maskset(s u32 offset, u32 mask, u32 set); extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid); diff --git a/target/linux/brcm47xx/patches-3.6/235-bcma-dont-expose-mips-irq.patch b/target/linux/brcm47xx/patches-3.6/235-bcma-dont-expose-mips-irq.patch index d06eb8f0a6..073ac42051 100644 --- a/target/linux/brcm47xx/patches-3.6/235-bcma-dont-expose-mips-irq.patch +++ b/target/linux/brcm47xx/patches-3.6/235-bcma-dont-expose-mips-irq.patch @@ -10,7 +10,7 @@ #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */ --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c -@@ -329,7 +329,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -332,7 +332,7 @@ void bcma_chipco_serial_init(struct bcma return; } @@ -65,7 +65,7 @@ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); return 0; -@@ -596,6 +596,6 @@ int bcma_core_pci_pcibios_map_irq(const +@@ -596,6 +596,6 @@ int bcma_core_pci_pcibios_map_irq(const pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, pci_ops); diff --git a/target/linux/brcm47xx/patches-3.6/750-bgmac.patch b/target/linux/brcm47xx/patches-3.6/750-bgmac.patch index b8fd0bae28..989a3f28e0 100644 --- a/target/linux/brcm47xx/patches-3.6/750-bgmac.patch +++ b/target/linux/brcm47xx/patches-3.6/750-bgmac.patch @@ -43,7 +43,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net> --- a/drivers/bcma/driver_chipcommon_pmu.c +++ b/drivers/bcma/driver_chipcommon_pmu.c -@@ -264,7 +264,7 @@ static u32 bcma_pmu_pll_clock_bcm4706(st +@@ -280,7 +280,7 @@ static u32 bcma_pmu_pll_clock_bcm4706(st } /* query bus clock frequency for PMU-enabled chipcommon */ @@ -52,7 +52,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net> { struct bcma_bus *bus = cc->core->bus; -@@ -293,6 +293,7 @@ static u32 bcma_pmu_get_bus_clock(struct +@@ -309,6 +309,7 @@ static u32 bcma_pmu_get_bus_clock(struct } return BCMA_CC_PMU_HT_CLOCK; } @@ -1969,7 +1969,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net> +#endif /* _BGMAC_H */ --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -624,4 +624,6 @@ int bcma_nflash_erase(struct bcma_drv_cc +@@ -627,4 +627,6 @@ int bcma_nflash_erase(struct bcma_drv_cc int bcma_nflash_commit(struct bcma_drv_cc *cc, u32 offset, u32 len, const u8 *buf); #endif diff --git a/target/linux/generic/patches-3.3/020-ssb_update.patch b/target/linux/generic/patches-3.3/020-ssb_update.patch index 3a3afd020e..6a4dbe7e13 100644 --- a/target/linux/generic/patches-3.3/020-ssb_update.patch +++ b/target/linux/generic/patches-3.3/020-ssb_update.patch @@ -404,7 +404,7 @@ /* We keep the default settings: * min_msk = 0xCBB * max_msk = 0x7FFFF -@@ -607,3 +617,61 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch +@@ -607,3 +617,90 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage); EXPORT_SYMBOL(ssb_pmu_set_ldo_paref); @@ -466,6 +466,35 @@ + return 0; + } +} ++ ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid) ++{ ++ u32 pmu_ctl = 0; ++ ++ switch (cc->dev->bus->chip_id) { ++ case 0x4322: ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854); ++ if (spuravoid == 1) ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828); ++ else ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828); ++ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; ++ break; ++ case 43222: ++ /* TODO: BCM43222 requires updating PLLs too */ ++ return; ++ default: ++ ssb_printk(KERN_ERR PFX ++ "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", ++ cc->dev->bus->chip_id); ++ return; ++ } ++ ++ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl); ++} ++EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate); --- /dev/null +++ b/drivers/ssb/driver_chipcommon_sflash.c @@ -0,0 +1,18 @@ @@ -765,7 +794,7 @@ +} --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c -@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct +@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct { struct ssb_bus *bus = mcore->dev->bus; @@ -1031,7 +1060,26 @@ static inline u8 ssb_crc8(u8 crc, u8 data) { -@@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss +@@ -327,11 +339,25 @@ static s8 r123_extract_antgain(u8 sprom_ + return (s8)gain; + } + ++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); ++ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); ++ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); ++ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, ++ SSB_SPROM2_MAXP_A_LO_SHIFT); ++} ++ + static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) { int i; u16 v; @@ -1039,7 +1087,7 @@ u16 loc[3]; if (out->revision == 3) /* rev 3 moved MAC */ -@@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss +@@ -361,8 +387,9 @@ static void sprom_extract_r123(struct ss SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14); SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15); SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0); @@ -1051,10 +1099,13 @@ SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA, SSB_SPROM1_BINF_ANTA_SHIFT); SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG, -@@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss +@@ -386,24 +413,19 @@ static void sprom_extract_r123(struct ss + SSB_SPROM1_ITSSI_A_SHIFT); + SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); - if (out->revision >= 2) - SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); +- if (out->revision >= 2) +- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); @@ -1079,10 +1130,12 @@ + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_A, + SSB_SPROM1_AGAIN_A_SHIFT); ++ if (out->revision >= 2) ++ sprom_extract_r23(out, in); } /* Revs 4 5 and 8 have partially shared layout */ -@@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb +@@ -464,14 +486,17 @@ static void sprom_extract_r45(struct ssb SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0); SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A, SSB_SPROM4_ETHPHY_ET1A_SHIFT); @@ -1102,7 +1155,7 @@ SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0); SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0); SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0); -@@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb +@@ -504,16 +529,14 @@ static void sprom_extract_r45(struct ssb } /* Extract the antenna gain values. */ @@ -1123,7 +1176,7 @@ sprom_extract_r458(out, in); -@@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb +@@ -523,14 +546,22 @@ static void sprom_extract_r45(struct ssb static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in) { int i; @@ -1148,7 +1201,7 @@ SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0); SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0); SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0); -@@ -596,16 +611,46 @@ static void sprom_extract_r8(struct ssb_ +@@ -596,16 +627,46 @@ static void sprom_extract_r8(struct ssb_ SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0); /* Extract the antenna gain values. */ @@ -1201,7 +1254,7 @@ /* Extract FEM info */ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, -@@ -630,6 +675,63 @@ static void sprom_extract_r8(struct ssb_ +@@ -630,6 +691,63 @@ static void sprom_extract_r8(struct ssb_ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); @@ -1265,7 +1318,7 @@ sprom_extract_r458(out, in); /* TODO - get remaining rev 8 stuff needed */ -@@ -759,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct +@@ -759,7 +877,6 @@ static void ssb_pci_get_boardinfo(struct { bi->vendor = bus->host_pci->subsystem_vendor; bi->type = bus->host_pci->subsystem_device; @@ -1610,7 +1663,15 @@ struct list_head list; --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h -@@ -504,7 +504,9 @@ +@@ -219,6 +219,7 @@ + #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16 ++#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400 + #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ + #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ + #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ +@@ -504,7 +505,9 @@ #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */ #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */ #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */ @@ -1621,7 +1682,7 @@ /* Status register bits for ST flashes */ #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */ -@@ -588,7 +590,10 @@ struct ssb_chipcommon { +@@ -588,7 +591,10 @@ struct ssb_chipcommon { u32 status; /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; @@ -1632,7 +1693,7 @@ }; static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) -@@ -628,8 +633,7 @@ enum ssb_clkmode { +@@ -628,8 +634,7 @@ enum ssb_clkmode { extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, enum ssb_clkmode mode); @@ -1642,7 +1703,7 @@ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); -@@ -642,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi +@@ -642,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); @@ -1651,6 +1712,13 @@ #ifdef CONFIG_SSB_SERIAL extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, +@@ -661,5 +668,6 @@ enum ssb_pmu_ldo_volt_id { + void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, + enum ssb_pmu_ldo_volt_id id, u32 voltage); + void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on); ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid); + + #endif /* LINUX_SSB_CHIPCO_H_ */ --- a/include/linux/ssb/ssb_driver_extif.h +++ b/include/linux/ssb/ssb_driver_extif.h @@ -152,12 +152,16 @@ @@ -1789,6 +1857,23 @@ #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */ #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */ #define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */ +@@ -287,11 +289,11 @@ + #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ +-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 +-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 ++#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */ ++#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0 ++#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8 + #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM4_AGAIN0_SHIFT 0 @@ -389,6 +391,11 @@ #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ @@ -1945,3 +2030,15 @@ + return wdt->driver_data; +} +#endif /* LINUX_BCM47XX_WDT_H_ */ +--- a/drivers/net/wireless/b43/phy_n.c ++++ b/drivers/net/wireless/b43/phy_n.c +@@ -4259,7 +4259,8 @@ static void b43_nphy_pmu_spur_avoid(stru + #endif + #ifdef CONFIG_B43_SSB + case B43_BUS_SSB: +- /* FIXME */ ++ ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, ++ avoid); + break; + #endif + } diff --git a/target/linux/generic/patches-3.3/025-bcma_backport.patch b/target/linux/generic/patches-3.3/025-bcma_backport.patch index a00bec30e2..6875a5eb8b 100644 --- a/target/linux/generic/patches-3.3/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.3/025-bcma_backport.patch @@ -224,12 +224,12 @@ #include <linux/bcma/bcma.h> static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, -@@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked +@@ -22,20 +25,120 @@ static inline u32 bcma_cc_write32_masked return value; } -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) -+static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) ++u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) { - u32 leddc_on = 10; - u32 leddc_off = 90; @@ -239,6 +239,7 @@ - if (cc->setup_done) + return 20000000; +} ++EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); + +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) +{ @@ -348,7 +349,7 @@ if (cc->core->id.rev >= 20) { bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); -@@ -44,7 +146,7 @@ void bcma_core_chipcommon_init(struct bc +@@ -44,7 +147,7 @@ void bcma_core_chipcommon_init(struct bc if (cc->capabilities & BCMA_CC_CAP_PMU) bcma_pmu_init(cc); if (cc->capabilities & BCMA_CC_CAP_PCTL) @@ -357,7 +358,7 @@ if (cc->core->id.rev >= 16) { if (cc->core->bus->sprom.leddc_on_time && -@@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc +@@ -56,15 +159,33 @@ void bcma_core_chipcommon_init(struct bc ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } @@ -394,7 +395,7 @@ } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) -@@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ +@@ -84,28 +205,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) { @@ -408,6 +409,7 @@ + + return res; } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) { @@ -421,6 +423,7 @@ + + return res; } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); +/* + * If the bit is set to 0, chipcommon controlls this GPIO, @@ -497,7 +500,7 @@ } #ifdef CONFIG_BCMA_DRIVER_MIPS -@@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -118,8 +310,7 @@ void bcma_chipco_serial_init(struct bcma struct bcma_serial_port *ports = cc->serial_ports; if (ccrev >= 11 && ccrev != 15) { @@ -507,7 +510,7 @@ if (ccrev >= 21) { /* Turn off UART clock before switching clocksource. */ bcma_cc_write32(cc, BCMA_CC_CORECTL, -@@ -137,8 +325,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -137,8 +328,7 @@ void bcma_chipco_serial_init(struct bcma | BCMA_CC_CORECTL_UARTCLKEN); } } else { @@ -748,7 +751,7 @@ if (cc->pmu.rev == 1) bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, ~BCMA_CC_PMU_CTL_NOILPONW); -@@ -174,37 +165,31 @@ void bcma_pmu_init(struct bcma_drv_cc *c +@@ -174,37 +165,47 @@ void bcma_pmu_init(struct bcma_drv_cc *c bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_NOILPONW); @@ -774,21 +777,37 @@ - case 0x5357: - case 0x4749: - case 53572: ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43421: ++ case BCMA_CHIP_ID_BCM43428: ++ case BCMA_CHIP_ID_BCM43431: + case BCMA_CHIP_ID_BCM4716: -+ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM47162: -+ case BCMA_CHIP_ID_BCM4313: -+ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM6362: /* always 20Mhz */ return 20000 * 1000; - case 0x5356: - case 0x5300: -+ case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM4706: ++ case BCMA_CHIP_ID_BCM5356: /* always 25Mhz */ return 25000 * 1000; ++ case BCMA_CHIP_ID_BCM43460: ++ case BCMA_CHIP_ID_BCM4352: ++ case BCMA_CHIP_ID_BCM4360: ++ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) ++ return 40000 * 1000; ++ else ++ return 20000 * 1000; default: - pr_warn("No ALP clock specified for %04X device, " - "pmu rev. %d, using default %d Hz\n", @@ -798,7 +817,7 @@ } return BCMA_CC_PMU_ALP_CLOCK; } -@@ -212,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c +@@ -212,7 +213,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c /* Find the output of the "m" pll divider given pll controls that start with * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. */ @@ -807,7 +826,7 @@ { u32 tmp, div, ndiv, p1, p2, fc; struct bcma_bus *bus = cc->core->bus; -@@ -221,7 +206,8 @@ static u32 bcma_pmu_clock(struct bcma_dr +@@ -221,7 +222,8 @@ static u32 bcma_pmu_clock(struct bcma_dr BUG_ON(!m || m > 4); @@ -817,7 +836,7 @@ /* Detect failure in clock setting */ tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); if (tmp & 0x40000) -@@ -240,60 +226,95 @@ static u32 bcma_pmu_clock(struct bcma_dr +@@ -240,60 +242,95 @@ static u32 bcma_pmu_clock(struct bcma_dr ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; /* Do calculation in Mhz */ @@ -939,7 +958,7 @@ pll = BCMA_CC_PMU5357_MAINPLL_PLL0; break; default: -@@ -301,10 +322,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr +@@ -301,10 +338,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr break; } @@ -996,7 +1015,7 @@ + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); + -+ tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4331: @@ -1017,7 +1036,7 @@ + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, + 0x03000a08); + } -+ tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM43224: @@ -1050,7 +1069,7 @@ + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } -+ tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4716: @@ -1084,7 +1103,7 @@ + 0x88888815); + } + -+ tmp = 3 << 9; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; + break; + + case BCMA_CHIP_ID_BCM43227: @@ -1120,7 +1139,7 @@ + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } -+ tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + default: + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", @@ -1555,7 +1574,7 @@ bcma_core_mips_print_irq(core, bcma_core_mips_irq(core)); } } -@@ -171,9 +194,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips +@@ -171,9 +194,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips struct bcma_bus *bus = mcore->core->bus; if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) @@ -1913,7 +1932,7 @@ } /************************************************** -@@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct +@@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc) { @@ -2771,7 +2790,7 @@ { struct bcma_bus *bus = pci_get_drvdata(dev); -@@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct +@@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct pci_set_drvdata(dev, NULL); } @@ -3212,12 +3231,12 @@ + break; + default: + return "UNKNOWN"; - } ++ } + + for (i = 0; i < size; i++) { + if (names[i].id == id->id) + return names[i].name; -+ } + } + return "UNKNOWN"; } @@ -3601,71 +3620,7 @@ + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0); + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0); + } - -- bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] & -- SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT; -- bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] & -- SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT; -- bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] & -- SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT; -- bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] & -- SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT; -- -- bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] & -- SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT; -- bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] & -- SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT; -- bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] & -- SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT; -- bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] & -- SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT; -- -- bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] & -- SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT; -- bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] & -- SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT; -- bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] & -- SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT; -- bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] & -- SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT; -- -- bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] & -- SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT; -- bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] & -- SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT; -- bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] & -- SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT; -- bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] & -- SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT; -- -- bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)]; -- bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)]; -- bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)]; -- bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)]; -- -- bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)]; -- -- bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & -- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT; -- bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & -- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT; -- bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & -- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT; -- bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & -- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT; -- bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & -- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT; -- -- bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & -- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT; -- bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & -- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT; -- bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & -- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT; -- bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & -- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT; -- bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & -- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT; ++ + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS, + SSB_SROM8_FEM_TSSIPOS_SHIFT); + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN, @@ -3847,7 +3802,71 @@ + case BCMA_CHIP_ID_BCM4331: + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT; + break; -+ + +- bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] & +- SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT; +- bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] & +- SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT; +- bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] & +- SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT; +- bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] & +- SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT; +- +- bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] & +- SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT; +- bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] & +- SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT; +- bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] & +- SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT; +- bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] & +- SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT; +- +- bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] & +- SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT; +- bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] & +- SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT; +- bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] & +- SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT; +- bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] & +- SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT; +- +- bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] & +- SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT; +- bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] & +- SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT; +- bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] & +- SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT; +- bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] & +- SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT; +- +- bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)]; +- bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)]; +- bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)]; +- bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)]; +- +- bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)]; +- +- bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT; +- bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT; +- bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT; +- bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT; +- bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT; +- +- bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT; +- bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT; +- bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT; +- bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT; +- bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT; + default: + return true; + } @@ -4176,7 +4195,7 @@ #define BCMA_CC_IRQSTAT 0x0020 #define BCMA_CC_IRQMASK 0x0024 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */ -@@ -79,6 +88,22 @@ +@@ -79,6 +88,23 @@ #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */ #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */ @@ -4196,10 +4215,11 @@ +#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ +#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ ++#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ #define BCMA_CC_JCMD_START 0x80000000 #define BCMA_CC_JCMD_BUSY 0x80000000 -@@ -108,10 +133,58 @@ +@@ -108,10 +134,58 @@ #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */ #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */ #define BCMA_CC_FLASHCTL 0x0040 @@ -4258,7 +4278,7 @@ #define BCMA_CC_BCAST_ADDR 0x0050 #define BCMA_CC_BCAST_DATA 0x0054 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */ -@@ -181,6 +254,45 @@ +@@ -181,6 +255,45 @@ #define BCMA_CC_FLASH_CFG 0x0128 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ #define BCMA_CC_FLASH_WAITCNT 0x012C @@ -4304,7 +4324,7 @@ /* 0x1E0 is defined as shared BCMA_CLKCTLST */ #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ #define BCMA_CC_UART0_DATA 0x0300 -@@ -240,7 +352,60 @@ +@@ -240,7 +353,60 @@ #define BCMA_CC_PLLCTL_ADDR 0x0660 #define BCMA_CC_PLLCTL_DATA 0x0664 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ @@ -4366,7 +4386,7 @@ /* Divider allocation in 4716/47162/5356 */ #define BCMA_CC_PMU5_MAINPLL_CPU 1 -@@ -256,6 +421,15 @@ +@@ -256,6 +422,15 @@ /* 4706 PMU */ #define BCMA_CC_PMU4706_MAINPLL_PLL0 0 @@ -4382,7 +4402,7 @@ /* ALP clock on pre-PMU chips */ #define BCMA_CC_PMU_ALP_CLOCK 20000000 -@@ -284,6 +458,19 @@ +@@ -284,6 +459,19 @@ #define BCMA_CC_PPL_PCHI_OFF 5 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f @@ -4402,7 +4422,7 @@ /* BCM4331 ChipControl numbers. */ #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ -@@ -297,9 +484,25 @@ +@@ -297,9 +485,25 @@ #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ @@ -4428,7 +4448,7 @@ /* Data for the PMU, if available. * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) */ -@@ -310,11 +513,35 @@ struct bcma_chipcommon_pmu { +@@ -310,11 +514,35 @@ struct bcma_chipcommon_pmu { #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_pflash { @@ -4464,7 +4484,7 @@ struct bcma_serial_port { void *regs; unsigned long clockspeed; -@@ -330,15 +557,30 @@ struct bcma_drv_cc { +@@ -330,15 +558,30 @@ struct bcma_drv_cc { u32 capabilities; u32 capabilities_ext; u8 setup_done:1; @@ -4495,7 +4515,7 @@ }; /* Register access */ -@@ -355,14 +597,14 @@ struct bcma_drv_cc { +@@ -355,14 +598,16 @@ struct bcma_drv_cc { bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); @@ -4509,10 +4529,12 @@ -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, - u32 ticks); +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); ++ ++extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); -@@ -375,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d +@@ -375,9 +620,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); @@ -4525,7 +4547,7 @@ extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value); -@@ -387,5 +632,6 @@ extern void bcma_chipco_chipctl_maskset( +@@ -387,5 +635,6 @@ extern void bcma_chipco_chipctl_maskset( u32 offset, u32 mask, u32 set); extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, u32 set); diff --git a/target/linux/generic/patches-3.6/020-ssb_update.patch b/target/linux/generic/patches-3.6/020-ssb_update.patch index 4113c17097..2f4cdad449 100644 --- a/target/linux/generic/patches-3.6/020-ssb_update.patch +++ b/target/linux/generic/patches-3.6/020-ssb_update.patch @@ -384,6 +384,39 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc) { struct ssb_bus *bus = cc->dev->bus; +@@ -645,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_ + return 0; + } + } ++ ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid) ++{ ++ u32 pmu_ctl = 0; ++ ++ switch (cc->dev->bus->chip_id) { ++ case 0x4322: ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854); ++ if (spuravoid == 1) ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828); ++ else ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828); ++ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; ++ break; ++ case 43222: ++ /* TODO: BCM43222 requires updating PLLs too */ ++ return; ++ default: ++ ssb_printk(KERN_ERR PFX ++ "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", ++ cc->dev->bus->chip_id); ++ return; ++ } ++ ++ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl); ++} ++EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate); --- /dev/null +++ b/drivers/ssb/driver_chipcommon_sflash.c @@ -0,0 +1,18 @@ @@ -683,7 +716,7 @@ +} --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c -@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct +@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct { struct ssb_bus *bus = mcore->dev->bus; @@ -974,7 +1007,15 @@ struct list_head list; --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h -@@ -504,7 +504,9 @@ +@@ -219,6 +219,7 @@ + #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16 ++#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400 + #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ + #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ + #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ +@@ -504,7 +505,9 @@ #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */ #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */ #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */ @@ -985,7 +1026,7 @@ /* Status register bits for ST flashes */ #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */ -@@ -588,7 +590,10 @@ struct ssb_chipcommon { +@@ -588,7 +591,10 @@ struct ssb_chipcommon { u32 status; /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; @@ -996,7 +1037,7 @@ }; static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) -@@ -628,8 +633,7 @@ enum ssb_clkmode { +@@ -628,8 +634,7 @@ enum ssb_clkmode { extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, enum ssb_clkmode mode); @@ -1006,7 +1047,7 @@ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); -@@ -642,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi +@@ -642,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); @@ -1015,6 +1056,13 @@ #ifdef CONFIG_SSB_SERIAL extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, +@@ -661,5 +668,6 @@ enum ssb_pmu_ldo_volt_id { + void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, + enum ssb_pmu_ldo_volt_id id, u32 voltage); + void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on); ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid); + + #endif /* LINUX_SSB_CHIPCO_H_ */ --- a/include/linux/ssb/ssb_driver_extif.h +++ b/include/linux/ssb/ssb_driver_extif.h @@ -152,12 +152,16 @@ @@ -1127,6 +1175,23 @@ extern void ssb_mipscore_init(struct ssb_mipscore *mcore); --- a/include/linux/ssb/ssb_regs.h +++ b/include/linux/ssb/ssb_regs.h +@@ -289,11 +289,11 @@ + #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ +-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 +-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 ++#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */ ++#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0 ++#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8 + #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM4_AGAIN0_SHIFT 0 @@ -485,7 +485,7 @@ #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020 @@ -1158,3 +1223,58 @@ + return wdt->driver_data; +} +#endif /* LINUX_BCM47XX_WDT_H_ */ +--- a/drivers/net/wireless/b43/phy_n.c ++++ b/drivers/net/wireless/b43/phy_n.c +@@ -4583,7 +4583,8 @@ static void b43_nphy_pmu_spur_avoid(stru + #endif + #ifdef CONFIG_B43_SSB + case B43_BUS_SSB: +- /* FIXME */ ++ ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, ++ avoid); + break; + #endif + } +--- a/drivers/ssb/pci.c ++++ b/drivers/ssb/pci.c +@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_ + return (s8)gain; + } + ++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); ++ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); ++ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); ++ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, ++ SSB_SPROM2_MAXP_A_LO_SHIFT); ++} ++ + static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) + { + int i; +@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss + SSB_SPROM1_ITSSI_A_SHIFT); + SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); + SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); +- if (out->revision >= 2) +- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); + +@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_A, + SSB_SPROM1_AGAIN_A_SHIFT); ++ if (out->revision >= 2) ++ sprom_extract_r23(out, in); + } + + /* Revs 4 5 and 8 have partially shared layout */ diff --git a/target/linux/generic/patches-3.6/025-bcma_backport.patch b/target/linux/generic/patches-3.6/025-bcma_backport.patch index 15b5c6f5e7..36f30de015 100644 --- a/target/linux/generic/patches-3.6/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.6/025-bcma_backport.patch @@ -126,12 +126,12 @@ #include <linux/bcma/bcma.h> static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, -@@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked +@@ -22,20 +25,120 @@ static inline u32 bcma_cc_write32_masked return value; } -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) -+static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) ++u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) { - u32 leddc_on = 10; - u32 leddc_off = 90; @@ -141,6 +141,7 @@ - if (cc->setup_done) + return 20000000; +} ++EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); + +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) +{ @@ -250,7 +251,7 @@ if (cc->core->id.rev >= 20) { bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); -@@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc +@@ -56,15 +159,33 @@ void bcma_core_chipcommon_init(struct bc ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } @@ -287,7 +288,7 @@ } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) -@@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ +@@ -84,28 +205,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) { @@ -301,6 +302,7 @@ + + return res; } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) { @@ -314,6 +316,7 @@ + + return res; } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); +/* + * If the bit is set to 0, chipcommon controlls this GPIO, @@ -390,7 +393,7 @@ } #ifdef CONFIG_BCMA_DRIVER_MIPS -@@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -118,8 +310,7 @@ void bcma_chipco_serial_init(struct bcma struct bcma_serial_port *ports = cc->serial_ports; if (ccrev >= 11 && ccrev != 15) { @@ -504,7 +507,7 @@ if (cc->pmu.rev == 1) bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, ~BCMA_CC_PMU_CTL_NOILPONW); -@@ -162,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c +@@ -162,24 +169,40 @@ void bcma_pmu_init(struct bcma_drv_cc *c bcma_pmu_workarounds(cc); } @@ -513,7 +516,44 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -190,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43421: ++ case BCMA_CHIP_ID_BCM43428: ++ case BCMA_CHIP_ID_BCM43431: + case BCMA_CHIP_ID_BCM4716: +- case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM47162: +- case BCMA_CHIP_ID_BCM4313: +- case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM6362: + /* always 20Mhz */ + return 20000 * 1000; +- case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM4706: ++ case BCMA_CHIP_ID_BCM5356: + /* always 25Mhz */ + return 25000 * 1000; ++ case BCMA_CHIP_ID_BCM43460: ++ case BCMA_CHIP_ID_BCM4352: ++ case BCMA_CHIP_ID_BCM4360: ++ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) ++ return 40000 * 1000; ++ else ++ return 20000 * 1000; + default: + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); +@@ -190,7 +213,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c /* Find the output of the "m" pll divider given pll controls that start with * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. */ @@ -522,7 +562,7 @@ { u32 tmp, div, ndiv, p1, p2, fc; struct bcma_bus *bus = cc->core->bus; -@@ -219,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_dr +@@ -219,14 +242,14 @@ static u32 bcma_pmu_clock(struct bcma_dr ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; /* Do calculation in Mhz */ @@ -539,7 +579,7 @@ { u32 tmp, ndiv, p1div, p2div; u32 clock; -@@ -257,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct +@@ -257,7 +280,7 @@ static u32 bcma_pmu_clock_bcm4706(struct } /* query bus clock frequency for PMU-enabled chipcommon */ @@ -548,7 +588,7 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -265,40 +272,42 @@ u32 bcma_pmu_get_clockcontrol(struct bcm +@@ -265,40 +288,42 @@ u32 bcma_pmu_get_clockcontrol(struct bcm case BCMA_CHIP_ID_BCM4716: case BCMA_CHIP_ID_BCM4748: case BCMA_CHIP_ID_BCM47162: @@ -602,7 +642,7 @@ BCMA_CC_PMU4706_MAINPLL_PLL0, BCMA_CC_PMU5_MAINPLL_CPU); case BCMA_CHIP_ID_BCM5356: -@@ -313,10 +322,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr +@@ -313,10 +338,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr break; } @@ -616,6 +656,51 @@ } static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset, +@@ -362,7 +388,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); + +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4331: +@@ -383,7 +409,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, + 0x03000a08); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM43224: +@@ -416,7 +442,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4716: +@@ -450,7 +476,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + 0x88888815); + } + +- tmp = 3 << 9; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; + break; + + case BCMA_CHIP_ID_BCM43227: +@@ -486,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + default: + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", --- a/drivers/bcma/driver_chipcommon_sflash.c +++ b/drivers/bcma/driver_chipcommon_sflash.c @@ -5,15 +5,161 @@ @@ -990,7 +1075,7 @@ for (i = 0; i <= 6; i++) printk(" %s%s", irq_name[i], i == irq ? "*" : " "); printk("\n"); -@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips +@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips struct bcma_bus *bus = mcore->core->bus; if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) @@ -1176,7 +1261,7 @@ } pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); return ret; -@@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct +@@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) break; @@ -1613,15 +1698,16 @@ /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF -@@ -100,6 +103,7 @@ +@@ -100,6 +103,8 @@ #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ ++#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ #define BCMA_CC_JCMD_START 0x80000000 #define BCMA_CC_JCMD_BUSY 0x80000000 -@@ -266,6 +270,29 @@ +@@ -266,6 +271,29 @@ #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 @@ -1651,7 +1737,7 @@ /* 0x1E0 is defined as shared BCMA_CLKCTLST */ #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ #define BCMA_CC_UART0_DATA 0x0300 -@@ -325,6 +352,60 @@ +@@ -325,6 +353,60 @@ #define BCMA_CC_PLLCTL_ADDR 0x0660 #define BCMA_CC_PLLCTL_DATA 0x0664 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ @@ -1712,7 +1798,7 @@ /* Divider allocation in 4716/47162/5356 */ #define BCMA_CC_PMU5_MAINPLL_CPU 1 -@@ -415,6 +496,13 @@ +@@ -415,6 +497,13 @@ /* 4313 Chip specific ChipControl register bits */ #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ @@ -1726,7 +1812,7 @@ /* Data for the PMU, if available. * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) */ -@@ -425,11 +513,35 @@ struct bcma_chipcommon_pmu { +@@ -425,11 +514,35 @@ struct bcma_chipcommon_pmu { #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_pflash { @@ -1762,7 +1848,7 @@ struct bcma_serial_port { void *regs; unsigned long clockspeed; -@@ -445,15 +557,30 @@ struct bcma_drv_cc { +@@ -445,15 +558,30 @@ struct bcma_drv_cc { u32 capabilities; u32 capabilities_ext; u8 setup_done:1; @@ -1793,7 +1879,7 @@ }; /* Register access */ -@@ -470,14 +597,14 @@ struct bcma_drv_cc { +@@ -470,14 +598,16 @@ struct bcma_drv_cc { bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); @@ -1807,10 +1893,12 @@ -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, - u32 ticks); +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); ++ ++extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); -@@ -490,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d +@@ -490,9 +620,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); diff --git a/target/linux/generic/patches-3.7/020-ssb_update.patch b/target/linux/generic/patches-3.7/020-ssb_update.patch index dec684239f..73c3830602 100644 --- a/target/linux/generic/patches-3.7/020-ssb_update.patch +++ b/target/linux/generic/patches-3.7/020-ssb_update.patch @@ -384,6 +384,39 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc) { struct ssb_bus *bus = cc->dev->bus; +@@ -645,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_ + return 0; + } + } ++ ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid) ++{ ++ u32 pmu_ctl = 0; ++ ++ switch (cc->dev->bus->chip_id) { ++ case 0x4322: ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854); ++ if (spuravoid == 1) ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828); ++ else ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828); ++ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; ++ break; ++ case 43222: ++ /* TODO: BCM43222 requires updating PLLs too */ ++ return; ++ default: ++ ssb_printk(KERN_ERR PFX ++ "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", ++ cc->dev->bus->chip_id); ++ return; ++ } ++ ++ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl); ++} ++EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate); --- /dev/null +++ b/drivers/ssb/driver_chipcommon_sflash.c @@ -0,0 +1,18 @@ @@ -683,7 +716,7 @@ +} --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c -@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct +@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct { struct ssb_bus *bus = mcore->dev->bus; @@ -973,7 +1006,15 @@ struct list_head list; --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h -@@ -590,7 +590,10 @@ struct ssb_chipcommon { +@@ -219,6 +219,7 @@ + #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16 ++#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400 + #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ + #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ + #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ +@@ -590,7 +591,10 @@ struct ssb_chipcommon { u32 status; /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; @@ -984,7 +1025,7 @@ }; static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) -@@ -630,8 +633,7 @@ enum ssb_clkmode { +@@ -630,8 +634,7 @@ enum ssb_clkmode { extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, enum ssb_clkmode mode); @@ -994,7 +1035,7 @@ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); -@@ -644,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi +@@ -644,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); @@ -1003,6 +1044,13 @@ #ifdef CONFIG_SSB_SERIAL extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, +@@ -663,5 +668,6 @@ enum ssb_pmu_ldo_volt_id { + void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, + enum ssb_pmu_ldo_volt_id id, u32 voltage); + void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on); ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid); + + #endif /* LINUX_SSB_CHIPCO_H_ */ --- a/include/linux/ssb/ssb_driver_extif.h +++ b/include/linux/ssb/ssb_driver_extif.h @@ -152,12 +152,16 @@ @@ -1115,6 +1163,23 @@ extern void ssb_mipscore_init(struct ssb_mipscore *mcore); --- a/include/linux/ssb/ssb_regs.h +++ b/include/linux/ssb/ssb_regs.h +@@ -289,11 +289,11 @@ + #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ +-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 +-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 ++#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */ ++#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0 ++#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8 + #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM4_AGAIN0_SHIFT 0 @@ -485,7 +485,7 @@ #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020 @@ -1146,3 +1211,58 @@ + return wdt->driver_data; +} +#endif /* LINUX_BCM47XX_WDT_H_ */ +--- a/drivers/net/wireless/b43/phy_n.c ++++ b/drivers/net/wireless/b43/phy_n.c +@@ -5165,7 +5165,8 @@ static void b43_nphy_pmu_spur_avoid(stru + #endif + #ifdef CONFIG_B43_SSB + case B43_BUS_SSB: +- /* FIXME */ ++ ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, ++ avoid); + break; + #endif + } +--- a/drivers/ssb/pci.c ++++ b/drivers/ssb/pci.c +@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_ + return (s8)gain; + } + ++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); ++ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); ++ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); ++ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, ++ SSB_SPROM2_MAXP_A_LO_SHIFT); ++} ++ + static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) + { + int i; +@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss + SSB_SPROM1_ITSSI_A_SHIFT); + SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); + SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); +- if (out->revision >= 2) +- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); + +@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_A, + SSB_SPROM1_AGAIN_A_SHIFT); ++ if (out->revision >= 2) ++ sprom_extract_r23(out, in); + } + + /* Revs 4 5 and 8 have partially shared layout */ diff --git a/target/linux/generic/patches-3.7/025-bcma_backport.patch b/target/linux/generic/patches-3.7/025-bcma_backport.patch index 4bd1b11f39..94be7ae8e5 100644 --- a/target/linux/generic/patches-3.7/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.7/025-bcma_backport.patch @@ -87,12 +87,12 @@ #include <linux/bcma/bcma.h> static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, -@@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked +@@ -22,20 +25,120 @@ static inline u32 bcma_cc_write32_masked return value; } -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) -+static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) ++u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) { - u32 leddc_on = 10; - u32 leddc_off = 90; @@ -102,6 +102,7 @@ - if (cc->setup_done) + return 20000000; +} ++EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); + +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) +{ @@ -211,7 +212,7 @@ if (cc->core->id.rev >= 20) { bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); -@@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc +@@ -56,15 +159,33 @@ void bcma_core_chipcommon_init(struct bc ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } @@ -248,7 +249,7 @@ } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) -@@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ +@@ -84,28 +205,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) { @@ -262,6 +263,7 @@ + + return res; } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) { @@ -275,6 +277,7 @@ + + return res; } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); +/* + * If the bit is set to 0, chipcommon controlls this GPIO, @@ -351,7 +354,7 @@ } #ifdef CONFIG_BCMA_DRIVER_MIPS -@@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -118,8 +310,7 @@ void bcma_chipco_serial_init(struct bcma struct bcma_serial_port *ports = cc->serial_ports; if (ccrev >= 11 && ccrev != 15) { @@ -363,7 +366,7 @@ bcma_cc_write32(cc, BCMA_CC_CORECTL, --- a/drivers/bcma/driver_chipcommon_nflash.c +++ b/drivers/bcma/driver_chipcommon_nflash.c -@@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc +@@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc } cc->nflash.present = true; @@ -390,7 +393,7 @@ void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) { -@@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct +@@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct } } @@ -410,7 +413,7 @@ if (cc->pmu.rev == 1) bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, ~BCMA_CC_PMU_CTL_NOILPONW); -@@ -165,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c +@@ -165,24 +169,40 @@ void bcma_pmu_init(struct bcma_drv_cc *c bcma_pmu_workarounds(cc); } @@ -419,7 +422,44 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -193,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43421: ++ case BCMA_CHIP_ID_BCM43428: ++ case BCMA_CHIP_ID_BCM43431: + case BCMA_CHIP_ID_BCM4716: +- case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM47162: +- case BCMA_CHIP_ID_BCM4313: +- case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM6362: + /* always 20Mhz */ + return 20000 * 1000; +- case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM4706: ++ case BCMA_CHIP_ID_BCM5356: + /* always 25Mhz */ + return 25000 * 1000; ++ case BCMA_CHIP_ID_BCM43460: ++ case BCMA_CHIP_ID_BCM4352: ++ case BCMA_CHIP_ID_BCM4360: ++ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) ++ return 40000 * 1000; ++ else ++ return 20000 * 1000; + default: + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); +@@ -193,7 +213,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c /* Find the output of the "m" pll divider given pll controls that start with * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. */ @@ -428,7 +468,7 @@ { u32 tmp, div, ndiv, p1, p2, fc; struct bcma_bus *bus = cc->core->bus; -@@ -222,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_dr +@@ -222,14 +242,14 @@ static u32 bcma_pmu_clock(struct bcma_dr ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; /* Do calculation in Mhz */ @@ -445,7 +485,7 @@ { u32 tmp, ndiv, p1div, p2div; u32 clock; -@@ -260,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct +@@ -260,7 +280,7 @@ static u32 bcma_pmu_clock_bcm4706(struct } /* query bus clock frequency for PMU-enabled chipcommon */ @@ -454,7 +494,7 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -268,40 +272,42 @@ static u32 bcma_pmu_get_clockcontrol(str +@@ -268,40 +288,42 @@ static u32 bcma_pmu_get_clockcontrol(str case BCMA_CHIP_ID_BCM4716: case BCMA_CHIP_ID_BCM4748: case BCMA_CHIP_ID_BCM47162: @@ -508,7 +548,7 @@ BCMA_CC_PMU4706_MAINPLL_PLL0, BCMA_CC_PMU5_MAINPLL_CPU); case BCMA_CHIP_ID_BCM5356: -@@ -316,10 +322,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr +@@ -316,10 +338,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr break; } @@ -522,6 +562,51 @@ } static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset, +@@ -365,7 +388,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); + +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4331: +@@ -386,7 +409,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, + 0x03000a08); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM43224: +@@ -419,7 +442,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4716: +@@ -453,7 +476,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + 0x88888815); + } + +- tmp = 3 << 9; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; + break; + + case BCMA_CHIP_ID_BCM43227: +@@ -489,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + default: + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", --- a/drivers/bcma/driver_chipcommon_sflash.c +++ b/drivers/bcma/driver_chipcommon_sflash.c @@ -12,7 +12,7 @@ @@ -577,7 +662,7 @@ { 0 }, }; -@@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc +@@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc break; } break; @@ -586,7 +671,7 @@ default: for (e = bcma_sflash_st_tbl; e->name; e++) { if (e->id == id) -@@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc +@@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc return -ENOTSUPP; } @@ -800,7 +885,7 @@ for (i = 0; i <= 6; i++) printk(" %s%s", irq_name[i], i == irq ? "*" : " "); printk("\n"); -@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips +@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips struct bcma_bus *bus = mcore->core->bus; if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) @@ -1252,7 +1337,15 @@ /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF -@@ -510,6 +513,7 @@ struct bcma_chipcommon_pmu { +@@ -101,6 +104,7 @@ + #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ + #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ + #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ ++#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 + #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ + #define BCMA_CC_JCMD_START 0x80000000 + #define BCMA_CC_JCMD_BUSY 0x80000000 +@@ -510,6 +514,7 @@ struct bcma_chipcommon_pmu { #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_pflash { @@ -1260,7 +1353,7 @@ u8 buswidth; u32 window; u32 window_size; -@@ -532,6 +536,7 @@ struct mtd_info; +@@ -532,6 +537,7 @@ struct mtd_info; struct bcma_nflash { bool present; @@ -1268,7 +1361,7 @@ struct mtd_info *mtd; }; -@@ -552,6 +557,7 @@ struct bcma_drv_cc { +@@ -552,6 +558,7 @@ struct bcma_drv_cc { u32 capabilities; u32 capabilities_ext; u8 setup_done:1; @@ -1276,7 +1369,7 @@ /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; struct bcma_chipcommon_pmu pmu; -@@ -567,6 +573,14 @@ struct bcma_drv_cc { +@@ -567,6 +574,14 @@ struct bcma_drv_cc { int nr_serial_ports; struct bcma_serial_port serial_ports[4]; #endif /* CONFIG_BCMA_DRIVER_MIPS */ @@ -1291,7 +1384,7 @@ }; /* Register access */ -@@ -583,14 +597,14 @@ struct bcma_drv_cc { +@@ -583,14 +598,16 @@ struct bcma_drv_cc { bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); @@ -1305,10 +1398,12 @@ -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, - u32 ticks); +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); ++ ++extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); -@@ -603,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d +@@ -603,9 +620,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); diff --git a/target/linux/generic/patches-3.8/020-ssb_update.patch b/target/linux/generic/patches-3.8/020-ssb_update.patch index 6cdfd2f730..d3cc6f1595 100644 --- a/target/linux/generic/patches-3.8/020-ssb_update.patch +++ b/target/linux/generic/patches-3.8/020-ssb_update.patch @@ -167,7 +167,7 @@ +} --- a/drivers/ssb/driver_gpio.c +++ b/drivers/ssb/driver_gpio.c -@@ -74,6 +74,16 @@ static void ssb_gpio_chipco_free(struct +@@ -74,6 +74,16 @@ static void ssb_gpio_chipco_free(struct ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0); } @@ -253,7 +253,7 @@ static inline u32 mips_read32(struct ssb_mipscore *mcore, u16 offset) -@@ -189,34 +209,43 @@ static void ssb_mips_serial_init(struct +@@ -189,34 +209,43 @@ static void ssb_mips_serial_init(struct static void ssb_mips_flash_detect(struct ssb_mipscore *mcore) { struct ssb_bus *bus = mcore->dev->bus; @@ -363,3 +363,129 @@ #endif /* CONFIG_SSB_DRIVER_MIPS */ #endif /* LINUX_SSB_MIPSCORE_H_ */ +--- a/drivers/net/wireless/b43/phy_n.c ++++ b/drivers/net/wireless/b43/phy_n.c +@@ -5165,7 +5165,8 @@ static void b43_nphy_pmu_spur_avoid(stru + #endif + #ifdef CONFIG_B43_SSB + case B43_BUS_SSB: +- /* FIXME */ ++ ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, ++ avoid); + break; + #endif + } +--- a/drivers/ssb/driver_chipcommon_pmu.c ++++ b/drivers/ssb/driver_chipcommon_pmu.c +@@ -675,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_ + return 0; + } + } ++ ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid) ++{ ++ u32 pmu_ctl = 0; ++ ++ switch (cc->dev->bus->chip_id) { ++ case 0x4322: ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854); ++ if (spuravoid == 1) ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828); ++ else ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828); ++ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; ++ break; ++ case 43222: ++ /* TODO: BCM43222 requires updating PLLs too */ ++ return; ++ default: ++ ssb_printk(KERN_ERR PFX ++ "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", ++ cc->dev->bus->chip_id); ++ return; ++ } ++ ++ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl); ++} ++EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate); +--- a/drivers/ssb/pci.c ++++ b/drivers/ssb/pci.c +@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_ + return (s8)gain; + } + ++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); ++ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); ++ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); ++ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, ++ SSB_SPROM2_MAXP_A_LO_SHIFT); ++} ++ + static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) + { + int i; +@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss + SSB_SPROM1_ITSSI_A_SHIFT); + SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); + SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); +- if (out->revision >= 2) +- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); + +@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_A, + SSB_SPROM1_AGAIN_A_SHIFT); ++ if (out->revision >= 2) ++ sprom_extract_r23(out, in); + } + + /* Revs 4 5 and 8 have partially shared layout */ +--- a/include/linux/ssb/ssb_driver_chipcommon.h ++++ b/include/linux/ssb/ssb_driver_chipcommon.h +@@ -219,6 +219,7 @@ + #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16 ++#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400 + #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ + #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ + #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ +@@ -667,5 +668,6 @@ enum ssb_pmu_ldo_volt_id { + void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, + enum ssb_pmu_ldo_volt_id id, u32 voltage); + void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on); ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid); + + #endif /* LINUX_SSB_CHIPCO_H_ */ +--- a/include/linux/ssb/ssb_regs.h ++++ b/include/linux/ssb/ssb_regs.h +@@ -289,11 +289,11 @@ + #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ +-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 +-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 ++#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */ ++#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0 ++#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8 + #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM4_AGAIN0_SHIFT 0 diff --git a/target/linux/generic/patches-3.8/025-bcma_backport.patch b/target/linux/generic/patches-3.8/025-bcma_backport.patch index 5a919a783a..bdb3a23904 100644 --- a/target/linux/generic/patches-3.8/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.8/025-bcma_backport.patch @@ -30,7 +30,39 @@ /* driver_chipcommon_pmu.c */ --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c -@@ -329,7 +329,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked + return value; + } + +-static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) ++u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) + { + if (cc->capabilities & BCMA_CC_CAP_PMU) + return bcma_pmu_get_alp_clock(cc); + + return 20000000; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); + + static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) + { +@@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv + + return res; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); + + u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +@@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d + + return res; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); + + /* + * If the bit is set to 0, chipcommon controlls this GPIO, +@@ -329,7 +332,7 @@ void bcma_chipco_serial_init(struct bcma return; } @@ -526,7 +558,7 @@ return cap_ptr; /* check if the capability pointer field exists */ -@@ -426,7 +429,7 @@ void bcma_core_pci_hostmode_init(struct +@@ -426,7 +429,7 @@ void bcma_core_pci_hostmode_init(struct /* Reset RC */ usleep_range(3000, 5000); pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); @@ -535,7 +567,7 @@ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | BCMA_CORE_PCI_CTL_RST_OE); -@@ -488,6 +491,17 @@ void bcma_core_pci_hostmode_init(struct +@@ -488,6 +491,17 @@ void bcma_core_pci_hostmode_init(struct bcma_core_pci_enable_crs(pc); @@ -562,7 +594,7 @@ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); return 0; -@@ -595,6 +609,6 @@ int bcma_core_pci_pcibios_map_irq(const +@@ -595,6 +609,6 @@ int bcma_core_pci_pcibios_map_irq(const pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, pci_ops); @@ -609,6 +641,23 @@ #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ #define BCMA_PLLTYPE_NONE 0x00000000 +@@ -104,6 +104,7 @@ + #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ + #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ + #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ ++#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 + #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ + #define BCMA_CC_JCMD_START 0x80000000 + #define BCMA_CC_JCMD_BUSY 0x80000000 +@@ -606,6 +607,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct + + extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); + ++extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); ++ + void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); + + u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); --- a/include/linux/bcma/bcma_driver_mips.h +++ b/include/linux/bcma/bcma_driver_mips.h @@ -28,6 +28,7 @@ @@ -657,3 +706,90 @@ /* PCIE Root Capability Register bits (Host mode only) */ #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 +--- a/drivers/bcma/driver_chipcommon_pmu.c ++++ b/drivers/bcma/driver_chipcommon_pmu.c +@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d + struct bcma_bus *bus = cc->core->bus; + + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43421: ++ case BCMA_CHIP_ID_BCM43428: ++ case BCMA_CHIP_ID_BCM43431: + case BCMA_CHIP_ID_BCM4716: +- case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM47162: +- case BCMA_CHIP_ID_BCM4313: +- case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM6362: + /* always 20Mhz */ + return 20000 * 1000; +- case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM4706: ++ case BCMA_CHIP_ID_BCM5356: + /* always 25Mhz */ + return 25000 * 1000; ++ case BCMA_CHIP_ID_BCM43460: ++ case BCMA_CHIP_ID_BCM4352: ++ case BCMA_CHIP_ID_BCM4360: ++ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) ++ return 40000 * 1000; ++ else ++ return 20000 * 1000; + default: + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); +@@ -372,7 +388,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); + +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4331: +@@ -393,7 +409,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, + 0x03000a08); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM43224: +@@ -426,7 +442,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4716: +@@ -460,7 +476,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + 0x88888815); + } + +- tmp = 3 << 9; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; + break; + + case BCMA_CHIP_ID_BCM43227: +@@ -496,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + default: + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", diff --git a/target/linux/generic/patches-3.9/020-ssb_backport.patch b/target/linux/generic/patches-3.9/020-ssb_backport.patch new file mode 100644 index 0000000000..db9cfdd1e0 --- /dev/null +++ b/target/linux/generic/patches-3.9/020-ssb_backport.patch @@ -0,0 +1,126 @@ +--- a/drivers/net/wireless/b43/phy_n.c ++++ b/drivers/net/wireless/b43/phy_n.c +@@ -5165,7 +5165,8 @@ static void b43_nphy_pmu_spur_avoid(stru + #endif + #ifdef CONFIG_B43_SSB + case B43_BUS_SSB: +- /* FIXME */ ++ ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, ++ avoid); + break; + #endif + } +--- a/drivers/ssb/driver_chipcommon_pmu.c ++++ b/drivers/ssb/driver_chipcommon_pmu.c +@@ -675,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_ + return 0; + } + } ++ ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid) ++{ ++ u32 pmu_ctl = 0; ++ ++ switch (cc->dev->bus->chip_id) { ++ case 0x4322: ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854); ++ if (spuravoid == 1) ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828); ++ else ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828); ++ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; ++ break; ++ case 43222: ++ /* TODO: BCM43222 requires updating PLLs too */ ++ return; ++ default: ++ ssb_printk(KERN_ERR PFX ++ "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", ++ cc->dev->bus->chip_id); ++ return; ++ } ++ ++ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl); ++} ++EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate); +--- a/drivers/ssb/pci.c ++++ b/drivers/ssb/pci.c +@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_ + return (s8)gain; + } + ++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); ++ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); ++ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); ++ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, ++ SSB_SPROM2_MAXP_A_LO_SHIFT); ++} ++ + static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) + { + int i; +@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss + SSB_SPROM1_ITSSI_A_SHIFT); + SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); + SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); +- if (out->revision >= 2) +- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); + +@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_A, + SSB_SPROM1_AGAIN_A_SHIFT); ++ if (out->revision >= 2) ++ sprom_extract_r23(out, in); + } + + /* Revs 4 5 and 8 have partially shared layout */ +--- a/include/linux/ssb/ssb_driver_chipcommon.h ++++ b/include/linux/ssb/ssb_driver_chipcommon.h +@@ -219,6 +219,7 @@ + #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ + #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16 ++#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400 + #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ + #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ + #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ +@@ -667,5 +668,6 @@ enum ssb_pmu_ldo_volt_id { + void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, + enum ssb_pmu_ldo_volt_id id, u32 voltage); + void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on); ++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid); + + #endif /* LINUX_SSB_CHIPCO_H_ */ +--- a/include/linux/ssb/ssb_regs.h ++++ b/include/linux/ssb/ssb_regs.h +@@ -289,11 +289,11 @@ + #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ +-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 +-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 ++#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */ ++#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0 ++#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8 + #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM4_AGAIN0_SHIFT 0 diff --git a/target/linux/generic/patches-3.9/021-bcma_backport.patch b/target/linux/generic/patches-3.9/021-bcma_backport.patch new file mode 100644 index 0000000000..2885aea389 --- /dev/null +++ b/target/linux/generic/patches-3.9/021-bcma_backport.patch @@ -0,0 +1,140 @@ +--- a/drivers/bcma/driver_chipcommon.c ++++ b/drivers/bcma/driver_chipcommon.c +@@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked + return value; + } + +-static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) ++u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) + { + if (cc->capabilities & BCMA_CC_CAP_PMU) + return bcma_pmu_get_alp_clock(cc); + + return 20000000; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); + + static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) + { +@@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv + + return res; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); + + u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +@@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d + + return res; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); + + /* + * If the bit is set to 0, chipcommon controlls this GPIO, +--- a/drivers/bcma/driver_chipcommon_pmu.c ++++ b/drivers/bcma/driver_chipcommon_pmu.c +@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d + struct bcma_bus *bus = cc->core->bus; + + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43421: ++ case BCMA_CHIP_ID_BCM43428: ++ case BCMA_CHIP_ID_BCM43431: + case BCMA_CHIP_ID_BCM4716: +- case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM47162: +- case BCMA_CHIP_ID_BCM4313: +- case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM6362: + /* always 20Mhz */ + return 20000 * 1000; +- case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM4706: ++ case BCMA_CHIP_ID_BCM5356: + /* always 25Mhz */ + return 25000 * 1000; ++ case BCMA_CHIP_ID_BCM43460: ++ case BCMA_CHIP_ID_BCM4352: ++ case BCMA_CHIP_ID_BCM4360: ++ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) ++ return 40000 * 1000; ++ else ++ return 20000 * 1000; + default: + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); +@@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); + +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4331: +@@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, + 0x03000a08); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM43224: +@@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4716: +@@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + 0x88888815); + } + +- tmp = 3 << 9; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; + break; + + case BCMA_CHIP_ID_BCM43227: +@@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + default: + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -104,6 +104,7 @@ + #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ + #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ + #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ ++#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 + #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ + #define BCMA_CC_JCMD_START 0x80000000 + #define BCMA_CC_JCMD_BUSY 0x80000000 +@@ -607,6 +608,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct + + extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); + ++extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); ++ + void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); + + u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); |