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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-04-25 19:02:42 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-04-25 19:02:42 +0000
commita151168be27d24c80e5bb959040bae801965dbcf (patch)
treee4e39019b8f731972de25b14e1f093c8eaaf3713 /target/linux/ramips/patches-3.8/0111-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch
parente8ac3affe018cbf45e8a8354631bfa600421fac0 (diff)
ramips: sync kernel patches with the mips-next tree
Signed-off-by: John Crispin <blogic@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@36431 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/patches-3.8/0111-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch')
-rw-r--r--target/linux/ramips/patches-3.8/0111-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch264
1 files changed, 264 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.8/0111-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch b/target/linux/ramips/patches-3.8/0111-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch
new file mode 100644
index 0000000000..9cfa509e54
--- /dev/null
+++ b/target/linux/ramips/patches-3.8/0111-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch
@@ -0,0 +1,264 @@
+From cccb9a7b42227a442ca42d590c838c8b6fa0eba1 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jan 2013 09:17:20 +0100
+Subject: [PATCH 111/137] MIPS: ralink: adds support for RT2880 SoC family
+
+Add support code for rt2880 SOC.
+
+The code detects the SoC and registers the clk / pinmux settings.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5176/
+---
+ arch/mips/Kconfig | 2 +-
+ arch/mips/include/asm/mach-ralink/rt288x.h | 49 ++++++++++
+ arch/mips/ralink/Kconfig | 3 +
+ arch/mips/ralink/Makefile | 1 +
+ arch/mips/ralink/Platform | 5 +
+ arch/mips/ralink/rt288x.c | 139 ++++++++++++++++++++++++++++
+ 6 files changed, 198 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
+ create mode 100644 arch/mips/ralink/rt288x.c
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1189,7 +1189,7 @@ config BOOT_ELF32
+
+ config MIPS_L1_CACHE_SHIFT
+ int
+- default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
++ default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
+ default "6" if MIPS_CPU_SCACHE
+ default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
+ default "5"
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/rt288x.h
+@@ -0,0 +1,49 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _RT288X_REGS_H_
++#define _RT288X_REGS_H_
++
++#define RT2880_SYSC_BASE 0x00300000
++
++#define SYSC_REG_CHIP_NAME0 0x00
++#define SYSC_REG_CHIP_NAME1 0x04
++#define SYSC_REG_CHIP_ID 0x0c
++#define SYSC_REG_SYSTEM_CONFIG 0x10
++#define SYSC_REG_CLKCFG 0x30
++
++#define RT2880_CHIP_NAME0 0x38325452
++#define RT2880_CHIP_NAME1 0x20203038
++
++#define CHIP_ID_ID_MASK 0xff
++#define CHIP_ID_ID_SHIFT 8
++#define CHIP_ID_REV_MASK 0xff
++
++#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
++#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
++#define SYSTEM_CONFIG_CPUCLK_250 0x0
++#define SYSTEM_CONFIG_CPUCLK_266 0x1
++#define SYSTEM_CONFIG_CPUCLK_280 0x2
++#define SYSTEM_CONFIG_CPUCLK_300 0x3
++
++#define RT2880_GPIO_MODE_I2C BIT(0)
++#define RT2880_GPIO_MODE_UART0 BIT(1)
++#define RT2880_GPIO_MODE_SPI BIT(2)
++#define RT2880_GPIO_MODE_UART1 BIT(3)
++#define RT2880_GPIO_MODE_JTAG BIT(4)
++#define RT2880_GPIO_MODE_MDIO BIT(5)
++#define RT2880_GPIO_MODE_SDRAM BIT(6)
++#define RT2880_GPIO_MODE_PCI BIT(7)
++
++#define CLKCFG_SRAM_CS_N_WDT BIT(9)
++
++#endif
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -6,6 +6,9 @@ choice
+ help
+ Select Ralink MIPS SoC type.
+
++ config SOC_RT288X
++ bool "RT288x"
++
+ config SOC_RT305X
+ bool "RT305x"
+ select USB_ARCH_HAS_HCD
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -8,6 +8,7 @@
+
+ obj-y := prom.o of.o reset.o clk.o irq.o
+
++obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+--- a/arch/mips/ralink/Platform
++++ b/arch/mips/ralink/Platform
+@@ -5,6 +5,11 @@ core-$(CONFIG_RALINK) += arch/mips/rali
+ cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
+
+ #
++# Ralink RT288x
++#
++load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
++
++#
+ # Ralink RT305x
+ #
+ load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
+--- /dev/null
++++ b/arch/mips/ralink/rt288x.c
+@@ -0,0 +1,139 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++
++#include <asm/mipsregs.h>
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/rt288x.h>
++
++#include "common.h"
++
++static struct ralink_pinmux_grp mode_mux[] = {
++ {
++ .name = "i2c",
++ .mask = RT2880_GPIO_MODE_I2C,
++ .gpio_first = 1,
++ .gpio_last = 2,
++ }, {
++ .name = "spi",
++ .mask = RT2880_GPIO_MODE_SPI,
++ .gpio_first = 3,
++ .gpio_last = 6,
++ }, {
++ .name = "uartlite",
++ .mask = RT2880_GPIO_MODE_UART0,
++ .gpio_first = 7,
++ .gpio_last = 14,
++ }, {
++ .name = "jtag",
++ .mask = RT2880_GPIO_MODE_JTAG,
++ .gpio_first = 17,
++ .gpio_last = 21,
++ }, {
++ .name = "mdio",
++ .mask = RT2880_GPIO_MODE_MDIO,
++ .gpio_first = 22,
++ .gpio_last = 23,
++ }, {
++ .name = "sdram",
++ .mask = RT2880_GPIO_MODE_SDRAM,
++ .gpio_first = 24,
++ .gpio_last = 39,
++ }, {
++ .name = "pci",
++ .mask = RT2880_GPIO_MODE_PCI,
++ .gpio_first = 40,
++ .gpio_last = 71,
++ }, {0}
++};
++
++static void rt288x_wdt_reset(void)
++{
++ u32 t;
++
++ /* enable WDT reset output on pin SRAM_CS_N */
++ t = rt_sysc_r32(SYSC_REG_CLKCFG);
++ t |= CLKCFG_SRAM_CS_N_WDT;
++ rt_sysc_w32(t, SYSC_REG_CLKCFG);
++}
++
++struct ralink_pinmux rt_gpio_pinmux = {
++ .mode = mode_mux,
++ .wdt_reset = rt288x_wdt_reset,
++};
++
++void __init ralink_clk_init(void)
++{
++ unsigned long cpu_rate;
++ u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
++ t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
++
++ switch (t) {
++ case SYSTEM_CONFIG_CPUCLK_250:
++ cpu_rate = 250000000;
++ break;
++ case SYSTEM_CONFIG_CPUCLK_266:
++ cpu_rate = 266666667;
++ break;
++ case SYSTEM_CONFIG_CPUCLK_280:
++ cpu_rate = 280000000;
++ break;
++ case SYSTEM_CONFIG_CPUCLK_300:
++ cpu_rate = 300000000;
++ break;
++ }
++
++ ralink_clk_add("cpu", cpu_rate);
++ ralink_clk_add("300100.timer", cpu_rate / 2);
++ ralink_clk_add("300120.watchdog", cpu_rate / 2);
++ ralink_clk_add("300500.uart", cpu_rate / 2);
++ ralink_clk_add("300c00.uartlite", cpu_rate / 2);
++ ralink_clk_add("400000.ethernet", cpu_rate / 2);
++}
++
++void __init ralink_of_remap(void)
++{
++ rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
++ rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
++
++ if (!rt_sysc_membase || !rt_memc_membase)
++ panic("Failed to remap core resources");
++}
++
++void prom_soc_init(struct ralink_soc_info *soc_info)
++{
++ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
++ const char *name;
++ u32 n0;
++ u32 n1;
++ u32 id;
++
++ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
++ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
++ id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
++
++ if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
++ soc_info->compatible = "ralink,r2880-soc";
++ name = "RT2880";
++ } else {
++ panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
++ }
++
++ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
++ "Ralink %s id:%u rev:%u",
++ name,
++ (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
++ (id & CHIP_ID_REV_MASK));
++}