diff options
| author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-07-15 10:06:55 +0000 |
|---|---|---|
| committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-07-15 10:06:55 +0000 |
| commit | ff4e0c1d0851ea6a073c03b8f2502cfee2ff68ae (patch) | |
| tree | faa96127d83945d5237ce1c294b2316754727325 /target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch | |
| parent | f64b0644d8f3ea912f76c3123b92bdd9b4aeb13c (diff) | |
ramips: add ralink v3.10 support
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37331 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch new file mode 100644 index 0000000000..c2d959d354 --- /dev/null +++ b/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch @@ -0,0 +1,64 @@ +From 74339d6eab7a37f7c629b737bf686d30e5014ce2 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 20 May 2013 20:57:09 +0200 +Subject: [PATCH 06/33] MIPS: ralink: add verbose pmu info + +Print the PMU and LDO settings on boot. + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index ccdec5a..62356a0 100644 +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -20,6 +20,22 @@ + + #include "common.h" + ++/* analog */ ++#define PMU0_CFG 0x88 ++#define PMU_SW_SET BIT(28) ++#define A_DCDC_EN BIT(24) ++#define A_SSC_PERI BIT(19) ++#define A_SSC_GEN BIT(18) ++#define A_SSC_M 0x3 ++#define A_SSC_S 16 ++#define A_DLY_M 0x7 ++#define A_DLY_S 8 ++#define A_VTUNE_M 0xff ++ ++/* digital */ ++#define PMU1_CFG 0x8C ++#define DIG_SW_SEL BIT(25) ++ + /* does the board have sdram or ddram */ + static int dram_type; + +@@ -187,6 +203,8 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + u32 n1; + u32 rev; + u32 cfg0; ++ u32 pmu0; ++ u32 pmu1; + + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); +@@ -234,4 +252,12 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + BUG(); + } + soc_info->mem_base = MT7620_DRAM_BASE; ++ ++ pmu0 = __raw_readl(sysc + PMU0_CFG); ++ pmu1 = __raw_readl(sysc + PMU1_CFG); ++ ++ pr_info("Analog PMU set to %s control\n", ++ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); ++ pr_info("Digital PMU set to %s control\n", ++ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); + } +-- +1.7.10.4 + |