diff options
author | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-01-26 20:48:35 +0000 |
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committer | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-01-26 20:48:35 +0000 |
commit | 86f7e2834ff8cc45f639d4a22a8af4cfdff015df (patch) | |
tree | 20fe12b60542a5d3ea43bd1ce7234242e0407183 /target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c | |
parent | b2dc6c86ee3e55b3bad7b3f69ed2b39fb894fa0a (diff) |
ramips: implement clock API for RT305X
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25124 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c')
-rw-r--r-- | target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c | 33 |
1 files changed, 26 insertions, 7 deletions
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c index 19f340bd47..6913006f7e 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c @@ -1,7 +1,7 @@ /* * Ralink RT305x SoC specific setup * - * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> * * Parts of this file are based on Ralink's 2.6.21 BSP * @@ -13,6 +13,8 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/err.h> +#include <linux/clk.h> #include <asm/mips_machine.h> #include <asm/reboot.h> @@ -21,6 +23,7 @@ #include <asm/mach-ralink/common.h> #include <asm/mach-ralink/rt305x.h> #include <asm/mach-ralink/rt305x_regs.h> +#include "common.h" static void rt305x_restart(char *command) { @@ -44,27 +47,43 @@ unsigned int __cpuinit get_c0_compare_irq(void) void __init ramips_soc_setup(void) { + struct clk *clk; + rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE); rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE); rt305x_detect_sys_type(); - rt305x_detect_sys_freq(); + rt305x_clocks_init(); + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type, - rt305x_cpu_freq / 1000000, - (rt305x_cpu_freq % 1000000) * 100 / 1000000); + clk_get_rate(clk) / 1000000, + (clk_get_rate(clk) % 1000000) * 100 / 1000000); _machine_restart = rt305x_restart; _machine_halt = rt305x_halt; pm_power_off = rt305x_halt; - ramips_early_serial_setup(0, RT305X_UART0_BASE, rt305x_sys_freq, + clk = clk_get(NULL, "uart"); + if (IS_ERR(clk)) + panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); + + ramips_early_serial_setup(0, RT305X_UART0_BASE, clk_get_rate(clk), RT305X_INTC_IRQ_UART0); - ramips_early_serial_setup(1, RT305X_UART1_BASE, rt305x_sys_freq, + ramips_early_serial_setup(1, RT305X_UART1_BASE, clk_get_rate(clk), RT305X_INTC_IRQ_UART1); } void __init plat_time_init(void) { - mips_hpt_frequency = rt305x_cpu_freq / 2; + struct clk *clk; + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + mips_hpt_frequency = clk_get_rate(clk) / 2; } |