diff options
| author | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2009-08-31 18:53:26 +0000 |
|---|---|---|
| committer | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2009-08-31 18:53:26 +0000 |
| commit | a43a8c98647194afa5528fd3afe26ea0b0781403 (patch) | |
| tree | 644c8852e34e991c4362fc771ca255c08ae37312 /target/linux/ramips/files/arch/mips/include | |
| parent | ab0a79714f445ae17d1ad601ff0628e75f31a430 (diff) | |
[ramips] share memory size detection code
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17454 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include')
| -rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/ralink_soc.h | 4 | ||||
| -rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/ralink_soc.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/ralink_soc.h index c379f39195..60ca647d8c 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/ralink_soc.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/ralink_soc.h @@ -11,6 +11,10 @@ #ifndef __RT288X_RALINK_SOC_H #define __RT288X_RALINK_SOC_H +#define RALINK_SOC_SDRAM_BASE 0x08000000 +#define RALINK_SOC_MEM_SIZE_MIN (2 * 1024 * 1024) +#define RALINK_SOC_MEM_SIZE_MAX (128 * 1024 * 1024) + #define RALINK_SOC_GPIO_BASE 0x300600 #define RALINK_SOC_GPIO0_COUNT 24 diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h index 144cc4ea46..fd0e8b3048 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h @@ -11,6 +11,10 @@ #ifndef __RT288X_RALINK_SOC_H #define __RT288X_RALINK_SOC_H +#define RALINK_SOC_SDRAM_BASE 0 +#define RALINK_SOC_MEM_SIZE_MIN (2 * 1024 * 1024) +#define RALINK_SOC_MEM_SIZE_MAX (64 * 1024 * 1024) + #define RALINK_SOC_GPIO_BASE 0x10000600 #define RALINK_SOC_GPIO0_COUNT 24 |