This patch adds a target for the IBM PowerXCell Accelerator Board.

(aka mvXCell-8i from MatrixVision or GigaAccel 180 from Fixstars)

http://us.fixstars.com/products/gigaaccel/

This build will create zImage suitable for TFTP boot image.

* v2
- add axonram device driver
- switch to 2.6.30.1

Signed-off-by: Akinobu Mita <mita@fixstars.com>


git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16860 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 107 insertions, 0 deletions

diff --git a/target/linux/pxcab/patches-2.6.30/0001-powerpc-mpic-Fix-mapping-of-DCR-based-MPIC-variants.patch b/target/linux/pxcab/patches-2.6.30/0001-powerpc-mpic-Fix-mapping-of-DCR-based-MPIC-variants.patch
new file mode 100644
index 0000000000..c546919279
--- /dev/null
+++ b/target/linux/pxcab/patches-2.6.30/0001-powerpc-mpic-Fix-mapping-of-DCR-based-MPIC-variants.patch
@@ -0,0 +1,107 @@
+commit 5a2642f620eb6e40792822fa0eafe23046fbb55e
+Author: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Date:   Mon Jun 22 16:47:59 2009 +0000
+
+    powerpc/mpic: Fix mapping of "DCR" based MPIC variants
+    
+    Commit 31207dab7d2e63795eb15823947bd2f7025b08e2
+    "Fix incorrect allocation of interrupt rev-map"
+    introduced a regression crashing on boot on machines using
+    a "DCR" based MPIC, such as the Cell blades.
+    
+    The reason is that the irq host data structure is initialized
+    much later as a result of that patch, causing our calls to
+    mpic_map() do be done before we have a host setup.
+    
+    Unfortunately, this breaks _mpic_map_dcr() which uses the
+    mpic->irqhost to get to the device node.
+    
+    This fixes it by, instead, passing the device node explicitely
+    to mpic_map().
+    
+    Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+    Acked-by: Akira Tsukamoto <akirat@rd.scei.sony.co.jp>
+
+diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
+index 9c3af50..32a2e95 100644
+--- a/arch/powerpc/sysdev/mpic.c
++++ b/arch/powerpc/sysdev/mpic.c
+@@ -279,28 +279,29 @@ static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
+ }
+ 
+ #ifdef CONFIG_PPC_DCR
+-static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
++static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
++			  struct mpic_reg_bank *rb,
+ 			  unsigned int offset, unsigned int size)
+ {
+ 	const u32 *dbasep;
+ 
+-	dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL);
++	dbasep = of_get_property(node, "dcr-reg", NULL);
+ 
+-	rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size);
++	rb->dhost = dcr_map(node, *dbasep + offset, size);
+ 	BUG_ON(!DCR_MAP_OK(rb->dhost));
+ }
+ 
+-static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr,
+-			    struct mpic_reg_bank *rb, unsigned int offset,
+-			    unsigned int size)
++static inline void mpic_map(struct mpic *mpic, struct device_node *node,
++			    phys_addr_t phys_addr, struct mpic_reg_bank *rb,
++			    unsigned int offset, unsigned int size)
+ {
+ 	if (mpic->flags & MPIC_USES_DCR)
+-		_mpic_map_dcr(mpic, rb, offset, size);
++		_mpic_map_dcr(mpic, node, rb, offset, size);
+ 	else
+ 		_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
+ }
+ #else /* CONFIG_PPC_DCR */
+-#define mpic_map(m,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
++#define mpic_map(m,n,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
+ #endif /* !CONFIG_PPC_DCR */
+ 
+ 
+@@ -1152,8 +1153,8 @@ struct mpic * __init mpic_alloc(struct device_node *node,
+ 	}
+ 
+ 	/* Map the global registers */
+-	mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
+-	mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
++	mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
++	mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
+ 
+ 	/* Reset */
+ 	if (flags & MPIC_WANTS_RESET) {
+@@ -1194,7 +1195,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
+ 
+ 	/* Map the per-CPU registers */
+ 	for (i = 0; i < mpic->num_cpus; i++) {
+-		mpic_map(mpic, paddr, &mpic->cpuregs[i],
++		mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
+ 			 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
+ 			 0x1000);
+ 	}
+@@ -1202,7 +1203,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
+ 	/* Initialize main ISU if none provided */
+ 	if (mpic->isu_size == 0) {
+ 		mpic->isu_size = mpic->num_sources;
+-		mpic_map(mpic, paddr, &mpic->isus[0],
++		mpic_map(mpic, node, paddr, &mpic->isus[0],
+ 			 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
+ 	}
+ 	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
+@@ -1256,8 +1257,10 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
+ 
+ 	BUG_ON(isu_num >= MPIC_MAX_ISU);
+ 
+-	mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
++	mpic_map(mpic, mpic->irqhost->of_node,
++		 paddr, &mpic->isus[isu_num], 0,
+ 		 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
++
+ 	if ((isu_first + mpic->isu_size) > mpic->num_sources)
+ 		mpic->num_sources = isu_first + mpic->isu_size;
+ }