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authorflorian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-01-17 22:29:13 +0000
committerflorian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-01-17 22:29:13 +0000
commit0356f8631af0de5023269a7073b52ad6f98debd9 (patch)
tree28aaf81b887b4bcd8212e99aee3297f411265556 /target/linux/mvebu/patches-3.8/037-arm_mvebu_add_pcie_dt_a370.patch
parent47411308694ea2ad590808f778b5736e4ebd58b1 (diff)
mvebu: add preliminary support for PCI express
Signed-off-by: Florian Fainelli <florian@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35211 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/mvebu/patches-3.8/037-arm_mvebu_add_pcie_dt_a370.patch')
-rw-r--r--target/linux/mvebu/patches-3.8/037-arm_mvebu_add_pcie_dt_a370.patch40
1 files changed, 40 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-3.8/037-arm_mvebu_add_pcie_dt_a370.patch b/target/linux/mvebu/patches-3.8/037-arm_mvebu_add_pcie_dt_a370.patch
new file mode 100644
index 0000000000..2cb8a17f07
--- /dev/null
+++ b/target/linux/mvebu/patches-3.8/037-arm_mvebu_add_pcie_dt_a370.patch
@@ -0,0 +1,40 @@
+The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
+necessary Device Tree informations to make these interfaces availabel.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/boot/dts/armada-370.dtsi | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+--- a/arch/arm/boot/dts/armada-370.dtsi
++++ b/arch/arm/boot/dts/armada-370.dtsi
+@@ -153,5 +153,29 @@
+ clocks = <&coreclk 0>;
+ };
+
++ pcie-controller {
++ compatible = "marvell,armada-370-xp-pcie";
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0xd0040000 0x2000
++ 0x2000 0xd0080000 0x2000>;
++
++ pcie0@0xd0040000 {
++ reg = <0x0 0x2000>;
++ interrupts = <58>;
++ clocks = <&gateclk 5>;
++ status = "disabled";
++ marvell,pcie-port = <0>;
++ };
++
++ pcie1@0xd0080000 {
++ reg = <0x2000 0x2000>;
++ interrupts = <62>;
++ clocks = <&gateclk 9>;
++ status = "disabled";
++ marvell,pcie-port = <1>;
++ };
++ };
+ };
+ };