mvebu: backport mainline patches from kernel 3.13

This is a backport of the patches accepted to the Linux mainline related to
mvebu SoC (Armada XP and Armada 370) between Linux v3.12, and Linux v3.13.
This work mainly covers:

* Finishes work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c)
  between the PXA family, and the Armada family.
* timer initialization update, and access function for the Armada family.
* Generic IRQ handling backporting.
* Some bug fixes.

Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com>
CC: Luka Perkov <luka@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39566 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 32 insertions, 0 deletions

diff --git a/target/linux/mvebu/patches-3.10/0146-mtd-nand-pxa3xx-Remove-READ0-switch-case-falltrough.patch b/target/linux/mvebu/patches-3.10/0146-mtd-nand-pxa3xx-Remove-READ0-switch-case-falltrough.patch
new file mode 100644
index 0000000000..0631b926b1
--- /dev/null
+++ b/target/linux/mvebu/patches-3.10/0146-mtd-nand-pxa3xx-Remove-READ0-switch-case-falltrough.patch
@@ -0,0 +1,32 @@
+From 11532c10a29e4faef29b5f3b354391d1e2f90213 Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
+Date: Thu, 14 Nov 2013 18:25:32 -0300
+Subject: [PATCH 146/203] mtd: nand: pxa3xx: Remove READ0 switch/case
+ falltrough
+
+READ0 and READOOB command preparation has a falltrough to SEQIN
+case, where the command address is specified.
+This is certainly confusing and makes the code less readable with
+no added value. Let's remove it.
+
+Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
+Tested-by: Daniel Mack <zonque@gmail.com>
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+---
+ drivers/mtd/nand/pxa3xx_nand.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/mtd/nand/pxa3xx_nand.c
++++ b/drivers/mtd/nand/pxa3xx_nand.c
+@@ -669,6 +669,11 @@ static int prepare_command_pool(struct p
+ 		if (mtd->writesize >= PAGE_CHUNK_SIZE)
+ 			info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
+ 
++		set_command_address(info, mtd->writesize, column, page_addr);
++		info->buf_count = mtd->writesize + mtd->oobsize;
++		memset(info->data_buff, 0xFF, info->buf_count);
++		break;
++
+ 	case NAND_CMD_SEQIN:
+ 
+ 		set_command_address(info, mtd->writesize, column, page_addr);