diff options
| author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-06-29 16:33:18 +0000 |
|---|---|---|
| committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-06-29 16:33:18 +0000 |
| commit | 80d298a68a096c8d13e09768cf52de99c35f1110 (patch) | |
| tree | 517824532009d825fa6026c3ba41c6445d4c7608 /target/linux/lantiq/patches-3.7/0126-lantiq_etop-Change-MDIO-clock.patch | |
| parent | 9928212701af94fc1852517b73c9de744ca5bbc7 (diff) | |
lantiq: remove 3.7 kernel patches
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37084 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/patches-3.7/0126-lantiq_etop-Change-MDIO-clock.patch')
| -rw-r--r-- | target/linux/lantiq/patches-3.7/0126-lantiq_etop-Change-MDIO-clock.patch | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/target/linux/lantiq/patches-3.7/0126-lantiq_etop-Change-MDIO-clock.patch b/target/linux/lantiq/patches-3.7/0126-lantiq_etop-Change-MDIO-clock.patch deleted file mode 100644 index b9488a125e..0000000000 --- a/target/linux/lantiq/patches-3.7/0126-lantiq_etop-Change-MDIO-clock.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 2f9f0ec1ff013934a86a7303c9194f6dc05620c3 Mon Sep 17 00:00:00 2001 -From: Sebastian Mayr <sebastian.mayr@student.uibk.ac.at> -Date: Thu, 20 Dec 2012 18:34:45 +0100 -Subject: [PATCH 1/2] lantiq_etop: Change MDIO clock - -This patch sets the MDC clock to 2.5MHz which fixes the MDIO communication -with the ar8316 switch. ---- - drivers/net/ethernet/lantiq_etop.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -83,6 +83,7 @@ - #define LTQ_GBIT_PMAC_HD_CTL 0x8c - #define LTQ_GBIT_P0_CTL 0x4 - #define LTQ_GBIT_PMAC_RX_IPG 0xa8 -+#define LTQ_GBIT_RGMII_CTL 0x78 - - #define PMAC_HD_CTL_AS (1 << 19) - #define PMAC_HD_CTL_RXSH (1 << 22) -@@ -92,6 +93,10 @@ - /* Disable MDIO auto polling (0=disable, 1=enable) */ - #define PX_CTL_DMDIO 0x00400000 - -+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ -+#define MDC_CLOCK_MASK 0xff000000 -+#define MDC_CLOCK_OFFSET 24 -+ - /* register information for the gbit's MDIO bus */ - #define MDIO_XR9_REQUEST 0x00008000 - #define MDIO_XR9_READ 0x00000800 -@@ -329,6 +334,9 @@ ltq_etop_gbit_init(struct net_device *de - /* Due to traffic halt when burst length 8, - replace default IPG value with 0x3B */ - ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); -+ /* set mdc clock to 2.5 MHz */ -+ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, -+ LTQ_GBIT_RGMII_CTL); - } - - static int |