[lantiq] update 3.2 patches

sync with lantiq kernel series

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31260 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 88 insertions, 0 deletions

diff --git a/target/linux/lantiq/patches-3.2/0071-MIPS-lantiq-stp-fix-for-ase-add-get-clock-disabled.patch b/target/linux/lantiq/patches-3.2/0071-MIPS-lantiq-stp-fix-for-ase-add-get-clock-disabled.patch
new file mode 100644
index 0000000000..7aeaa1de82
--- /dev/null
+++ b/target/linux/lantiq/patches-3.2/0071-MIPS-lantiq-stp-fix-for-ase-add-get-clock-disabled.patch
@@ -0,0 +1,88 @@
+From d8e3038c520ea6c7619d3f5339c47ca0c2aa7fe3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 11 Apr 2012 18:47:53 +0200
+Subject: [PATCH 71/73] MIPS: lantiq: stp, fix for ase, add get, clock
+ disabled
+
+Lantiq serial-to-parallel hardware gpio module
+Added gpio pins as used for amazon se (ase)
+Added get to enable reporting of gpio status
+Changed to use software update, as hw clock was not running on ase. Clock
+really only needed if hw flashing was implemented.
+
+Signed-off-by: Conor O'Gorman <i@conorogorman.net>
+---
+ arch/mips/lantiq/xway/gpio_stp.c |   22 +++++++++++++---------
+ 1 files changed, 13 insertions(+), 9 deletions(-)
+
+diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
+index 9610c10..791beeb 100644
+--- a/arch/mips/lantiq/xway/gpio_stp.c
++++ b/arch/mips/lantiq/xway/gpio_stp.c
+@@ -27,6 +27,7 @@
+ #define LTQ_STP_AR		0x10
+ 
+ #define LTQ_STP_CON_SWU		(1 << 31)
++#define LTQ_STP_SWU_MASK	(1 << 31)
+ #define LTQ_STP_2HZ		0
+ #define LTQ_STP_4HZ		(1 << 23)
+ #define LTQ_STP_8HZ		(2 << 23)
+@@ -60,6 +61,12 @@ static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
+ 	else
+ 		ltq_stp_shadow &= ~(1 << offset);
+ 	ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0);
++	ltq_stp_w32_mask(LTQ_STP_SWU_MASK, LTQ_STP_CON_SWU, LTQ_STP_CON0);
++}
++
++static int ltq_stp_get(struct gpio_chip *chip, unsigned offset)
++{
++	return !!(ltq_stp_r32(LTQ_STP_CPU0) & (1<<offset));
+ }
+ 
+ static int ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset,
+@@ -74,6 +81,7 @@ static struct gpio_chip ltq_stp_chip = {
+ 	.label = "ltq_stp",
+ 	.direction_output = ltq_stp_direction_output,
+ 	.set = ltq_stp_set,
++	.get = ltq_stp_get,
+ 	.base = 200,
+ 	.ngpio = 24,
+ 	.owner = THIS_MODULE,
+@@ -97,12 +105,6 @@ static int ltq_stp_hw_init(struct device *dev)
+ 	ltq_stp_w32_mask(0, LTQ_STP_GROUP0 | LTQ_STP_GROUP1 | LTQ_STP_GROUP2,
+ 		LTQ_STP_CON1);
+ 
+-	/* stp are update periodically by the FPI bus */
+-	ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
+-
+-	/* set stp update speed */
+-	ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1);
+-
+ 	/* tell the hardware that pin (led) 0 and 1 are controlled
+ 	 *  by the dsl arc
+ 	 */
+@@ -118,6 +120,7 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev)
+ {
+ 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	int ret = 0;
++	int pin;
+ 
+ 	if (!res)
+ 		return -ENOENT;
+@@ -135,9 +138,10 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/* the 3 pins used to control the external stp */
+-	if (ltq_gpio_request(&pdev->dev, 4, 2, 1, "stp-st") ||
+-			ltq_gpio_request(&pdev->dev, 5, 2, 1, "stp-d") ||
+-			ltq_gpio_request(&pdev->dev, 6, 2, 1, "stp-sh")) {
++	pin = ltq_is_ase() ? 1 : 4;
++	if (ltq_gpio_request(&pdev->dev, pin, 2, 1, "stp-st") ||
++			ltq_gpio_request(&pdev->dev, pin+1, 2, 1, "stp-d") ||
++			ltq_gpio_request(&pdev->dev, pin+2, 2, 1, "stp-sh")) {
+ 		dev_err(&pdev->dev, "failed to request needed gpios\n");
+ 		return -EBUSY;
+ 	}
+-- 
+1.7.9.1
+