diff options
| author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-11-02 20:07:02 +0000 |
|---|---|---|
| committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-11-02 20:07:02 +0000 |
| commit | 1048c7b452f060c290d973d8a50ec4d178c937e6 (patch) | |
| tree | 9042a707f9a1efd86b4873f9ad1e0116e209f93c /target/linux/lantiq/files/arch/mips | |
| parent | 961508b717febc5478ec5b780897d348b054fd74 (diff) | |
[lantiq] move files/ -> files-3.3/
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34060 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/files/arch/mips')
90 files changed, 0 insertions, 23969 deletions
diff --git a/target/linux/lantiq/files/arch/mips/configs/ase_defconfig b/target/linux/lantiq/files/arch/mips/configs/ase_defconfig deleted file mode 100644 index 5bb1d93ebd..0000000000 --- a/target/linux/lantiq/files/arch/mips/configs/ase_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_LANTIQ=y -CONFIG_SOC_AMAZON_SE=y -CONFIG_CPU_MIPS32_R2=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_EXPERIMENTAL=y -CONFIG_DEFAULT_HOSTNAME="amazon_se" -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" -CONFIG_INITRAMFS_ROOT_UID=1000 -CONFIG_INITRAMFS_ROOT_GID=1000 -+# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_DEFAULT_DEADLINE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_MROUTE=y -CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -CONFIG_ARPD=y -CONFIG_SYN_COOKIES=y -CONFIG_NETFILTER=y -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=y -CONFIG_NET_SCHED=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_LANTIQ=y -CONFIG_MISC_DEVICES=y -CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_LANTIQ_ETOP=y -CONFIG_PHYLIB=y -CONFIG_SERIAL_LANTIQ=y -CONFIG_PINCTRL=y -CONFIG_GPIO_SYSFS=y -CONFIG_WATCHDOG=y -CONFIG_LANTIQ_WDT=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_XZ=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_FS=y diff --git a/target/linux/lantiq/files/arch/mips/configs/falcon_defconfig b/target/linux/lantiq/files/arch/mips/configs/falcon_defconfig deleted file mode 100644 index ce242a88ed..0000000000 --- a/target/linux/lantiq/files/arch/mips/configs/falcon_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_LANTIQ=y -CONFIG_SOC_FALCON=y -CONFIG_CPU_MIPS32_R2=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_EXPERIMENTAL=y -CONFIG_DEFAULT_HOSTNAME="falcon" -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" -CONFIG_INITRAMFS_ROOT_UID=1000 -CONFIG_INITRAMFS_ROOT_GID=1000 -+# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_DEFAULT_DEADLINE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_MROUTE=y -CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -CONFIG_ARPD=y -CONFIG_SYN_COOKIES=y -CONFIG_NETFILTER=y -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=y -CONFIG_NET_SCHED=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_LANTIQ=y -CONFIG_MTD_M25P80=y -CONFIG_MISC_DEVICES=y -CONFIG_EEPROM_AT24=y -CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_PHYLIB=y -CONFIG_SERIAL_LANTIQ=y -CONFIG_I2C=y -CONFIG_I2C_FALCON=y -CONFIG_SPI=y -CONFIG_SPI_FALCON=y -CONFIG_PINCTRL=y -CONFIG_GPIO_SYSFS=y -CONFIG_WATCHDOG=y -CONFIG_LANTIQ_WDT=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_XZ=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_FS=y diff --git a/target/linux/lantiq/files/arch/mips/configs/xway_defconfig b/target/linux/lantiq/files/arch/mips/configs/xway_defconfig deleted file mode 100644 index 510a9641d3..0000000000 --- a/target/linux/lantiq/files/arch/mips/configs/xway_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_LANTIQ=y -CONFIG_CPU_MIPS32_R2=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_EXPERIMENTAL=y -CONFIG_DEFAULT_HOSTNAME="danube" -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" -CONFIG_INITRAMFS_ROOT_UID=1000 -CONFIG_INITRAMFS_ROOT_GID=1000 -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_DEFAULT_DEADLINE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_MROUTE=y -CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -CONFIG_ARPD=y -CONFIG_SYN_COOKIES=y -CONFIG_NETFILTER=y -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=y -CONFIG_NET_SCHED=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_LANTIQ=y -CONFIG_MISC_DEVICES=y -CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_LANTIQ_ETOP=y -CONFIG_PHYLIB=y -CONFIG_SERIAL_LANTIQ=y -CONFIG_PINCTRL=y -CONFIG_GPIO_SYSFS=y -CONFIG_WATCHDOG=y -CONFIG_LANTIQ_WDT=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_XZ=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_FS=y diff --git a/target/linux/lantiq/files/arch/mips/include/asm/clkdev.h b/target/linux/lantiq/files/arch/mips/include/asm/clkdev.h deleted file mode 100644 index 262475414e..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/clkdev.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * based on arch/arm/include/asm/clkdev.h - * - * Copyright (C) 2008 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Helper for the clk API to assist looking up a struct clk. - */ -#ifndef __ASM_CLKDEV_H -#define __ASM_CLKDEV_H - -#include <linux/slab.h> - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) -{ - return kzalloc(size, GFP_KERNEL); -} - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-buttons.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-buttons.h deleted file mode 100644 index adb531c39b..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-buttons.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Lantiq GPIO button support - * - * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _LANTIQ_DEV_GPIO_BUTTONS_H -#define _LANTIQ_DEV_GPIO_BUTTONS_H - -#include <linux/input.h> -#include <linux/gpio_keys.h> - -#define LTQ_KEYS_POLL_INTERVAL 20 /* msecs */ -#define LTQ_KEYS_DEBOUNCE_INTERVAL (3 * LTQ_KEYS_POLL_INTERVAL) - -void ltq_register_gpio_keys_polled(int id, - unsigned poll_interval, - unsigned nbuttons, - struct gpio_keys_button *buttons); - -#endif /* _LANTIQ_DEV_GPIO_BUTTONS_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-leds.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-leds.h deleted file mode 100644 index d51e496d14..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-leds.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Lantiq GPIO LED device support - * - * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _LANTIQ_DEV_LEDS_GPIO_H -#define _LANTIQ_DEV_LEDS_GPIO_H - -#include <linux/leds.h> - -void ltq_add_device_gpio_leds(int id, - unsigned num_leds, - struct gpio_led *leds) __init; - -#endif /* _LANTIQ_DEV_LEDS_GPIO_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h deleted file mode 100644 index 4dc6466e84..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> - */ - -#ifndef _FALCON_IRQ__ -#define _FALCON_IRQ__ - -#define INT_NUM_IRQ0 8 -#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) -#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) -#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) -#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) -#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) -#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) -#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) - -#define MIPS_CPU_TIMER_IRQ 7 - -/* HOST IF Event Interrupt */ -#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0) -/* HOST IF Mailbox0 Receive Interrupt */ -#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1) -/* HOST IF Mailbox0 Transmit Interrupt */ -#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2) -/* HOST IF Mailbox1 Receive Interrupt */ -#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3) -/* HOST IF Mailbox1 Transmit Interrupt */ -#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4) -/* I2C Last Single Data Transfer Request */ -#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8) -/* I2C Single Data Transfer Request */ -#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9) -/* I2C Last Burst Data Transfer Request */ -#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10) -/* I2C Burst Data Transfer Request */ -#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11) -/* I2C Error Interrupt */ -#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12) -/* I2C Protocol Interrupt */ -#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13) -/* SSC Transmit Interrupt */ -#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14) -/* SSC Receive Interrupt */ -#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15) -/* SSC Error Interrupt */ -#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16) -/* SSC Frame Interrupt */ -#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17) -/* Advanced Encryption Standard Interrupt */ -#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27) -/* Secure Hash Algorithm Interrupt */ -#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28) -/* PCM Receive Interrupt */ -#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29) -/* PCM Transmit Interrupt */ -#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30) -/* PCM Transmit Crash Interrupt */ -#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31) - -/* EBU Serial Flash Command Error */ -#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0) -/* EBU Serial Flash Command Overwrite Error */ -#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1) -/* EBU Serial Flash Busy */ -#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2) -/* External Interrupt from GPIO P0 */ -#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4) -/* External Interrupt from GPIO P1 */ -#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5) -/* External Interrupt from GPIO P2 */ -#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6) -/* External Interrupt from GPIO P3 */ -#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7) -/* External Interrupt from GPIO P4 */ -#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8) -/* 8kHz backup interrupt derived from core-PLL */ -#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10) -/* FSC Timer Interrupt 0 */ -#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11) -/* FSC Timer Interrupt 1 */ -#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12) -/* 8kHz root interrupt derived from GPON interface */ -#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13) -/* Time of Day */ -#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14) -/* PMA Interrupt from IntNode of the 200MHz Domain */ -#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15) -/* PMA Interrupt from IntNode of the TX Clk Domain */ -#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16) -/* PMA Interrupt from IntNode of the RX Clk Domain */ -#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17) -/* SYS1 Interrupt */ -#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20) -/* SYS GPE Interrupt */ -#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21) -/* Watchdog Access Error Interrupt */ -#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24) -/* Watchdog Prewarning Interrupt */ -#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25) -/* SBIU interrupt */ -#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27) -/* FPI Bus Control Unit Interrupt */ -#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29) -/* DDR Controller Interrupt */ -#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30) -/* Crossbar Error Interrupt */ -#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31) - -/* ICTRLL 0 Interrupt */ -#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0) -/* ICTRLL 1 Interrupt */ -#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1) -/* ICTRLL 2 Interrupt */ -#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2) -/* ICTRLL 3 Interrupt */ -#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3) -/* OCTRLL 0 Interrupt */ -#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4) -/* OCTRLL 1 Interrupt */ -#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5) -/* OCTRLL 2 Interrupt */ -#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6) -/* OCTRLL 3 Interrupt */ -#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7) -/* OCTRLG Interrupt */ -#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9) -/* IQM Interrupt */ -#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10) -/* FSQM Interrupt */ -#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11) -/* TMU Interrupt */ -#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12) -/* LINK1 Interrupt */ -#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14) -/* ICTRLC 0 Interrupt */ -#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16) -/* ICTRLC 1 Interrupt */ -#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17) -/* OCTRLC Interrupt */ -#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18) -/* CONFIG Break Interrupt */ -#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19) -/* CONFIG Interrupt */ -#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20) -/* Dispatcher Interrupt */ -#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21) -/* TBM Interrupt */ -#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22) -/* GTC Downstream Interrupt */ -#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29) -/* GTC Upstream Interrupt */ -#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30) -/* EIM Interrupt */ -#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31) - -/* ASC0 Transmit Interrupt */ -#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0) -/* ASC0 Receive Interrupt */ -#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1) -/* ASC0 Error Interrupt */ -#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2) -/* ASC0 Transmit Buffer Interrupt */ -#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3) -/* ASC0 Autobaud Start Interrupt */ -#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4) -/* ASC0 Autobaud Detection Interrupt */ -#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5) -/* ASC1 Modem Status Interrupt */ -#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6) -/* ASC0 Soft Flow Control Interrupt */ -#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7) -/* ASC1 Transmit Interrupt */ -#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8) -/* ASC1 Receive Interrupt */ -#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9) -/* ASC1 Error Interrupt */ -#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10) -/* ASC1 Transmit Buffer Interrupt */ -#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11) -/* ASC1 Autobaud Start Interrupt */ -#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12) -/* ASC1 Autobaud Detection Interrupt */ -#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13) -/* ASC1 Modem Status Interrupt */ -#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14) -/* ASC1 Soft Flow Control Interrupt */ -#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15) -/* GPTC Timer/Counter 1A Interrupt */ -#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16) -/* GPTC Timer/Counter 1B Interrupt */ -#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17) -/* GPTC Timer/Counter 2A Interrupt */ -#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18) -/* GPTC Timer/Counter 2B Interrupt */ -#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19) -/* GPTC Timer/Counter 3A Interrupt */ -#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20) -/* GPTC Timer/Counter 3B Interrupt */ -#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21) -/* DFEV0, Channel 1 Transmit Interrupt */ -#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26) -/* DFEV0, Channel 1 Receive Interrupt */ -#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27) -/* DFEV0, Channel 1 General Purpose Interrupt */ -#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28) -/* DFEV0, Channel 0 Transmit Interrupt */ -#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29) -/* DFEV0, Channel 0 Receive Interrupt */ -#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30) -/* DFEV0, Channel 0 General Purpose Interrupt */ -#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31) - -/* ICTRLL 0 Error */ -#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0) -/* ICTRLL 1 Error */ -#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1) -/* ICTRLL 2 Error */ -#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2) -/* ICTRLL 3 Error */ -#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3) -/* OCTRLL 0 Error */ -#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4) -/* OCTRLL 1 Error */ -#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5) -/* OCTRLL 2 Error */ -#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6) -/* OCTRLL 3 Error */ -#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7) -/* ICTRLG Error */ -#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8) -/* OCTRLG Error */ -#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9) -/* IQM Error */ -#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10) -/* FSQM Error */ -#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11) -/* TMU Error */ -#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12) -/* MPS Status Interrupt #0 (VPE1 to VPE0) */ -#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14) -/* MPS Status Interrupt #1 (VPE1 to VPE0) */ -#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15) -/* MPS Status Interrupt #2 (VPE1 to VPE0) */ -#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16) -/* MPS Status Interrupt #3 (VPE1 to VPE0) */ -#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17) -/* MPS Status Interrupt #4 (VPE1 to VPE0) */ -#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18) -/* MPS Status Interrupt #5 (VPE1 to VPE0) */ -#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19) -/* MPS Status Interrupt #6 (VPE1 to VPE0) */ -#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20) -/* MPS Status Interrupt #7 (VPE1 to VPE0) */ -#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21) -/* MPS Status Interrupt #8 (VPE1 to VPE0) */ -#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22) -/* VPE0 Exception Level Flag Interrupt */ -#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29) -/* VPE0 Error Level Flag Interrupt */ -#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30) -/* VPE0 Performance Monitoring Counter Interrupt */ -#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31) - -#endif /* _FALCON_IRQ__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h deleted file mode 100644 index 2caccd9f9d..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> - */ - -#ifndef __FALCON_IRQ_H -#define __FALCON_IRQ_H - -#include <falcon_irq.h> - -#define NR_IRQS 328 - -#include_next <irq.h> - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h deleted file mode 100644 index fff5ecdbea..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#ifndef _LTQ_FALCON_H__ -#define _LTQ_FALCON_H__ - -#ifdef CONFIG_SOC_FALCON - -#include <lantiq.h> - -/* Chip IDs */ -#define SOC_ID_FALCON 0x01B8 - -/* SoC Types */ -#define SOC_TYPE_FALCON 0x01 - -/* ASC0/1 - serial port */ -#define LTQ_ASC0_BASE_ADDR 0x1E100C00 -#define LTQ_ASC1_BASE_ADDR 0x1E100B00 -#define LTQ_ASC_SIZE 0x100 - -#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) -#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) -#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) - -/* - * during early_printk no ioremap possible at this early stage - * lets use KSEG1 instead - */ -#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) - -/* ICU - interrupt control unit */ -#define LTQ_ICU_BASE_ADDR 0x1F880200 -#define LTQ_ICU_SIZE 0x100 - -/* WDT */ -#define LTQ_WDT_BASE_ADDR 0x1F8803F0 -#define LTQ_WDT_SIZE 0x10 - -#define LTQ_RST_CAUSE_WDTRST 0x0002 - -/* EBU - external bus unit */ -#define LTQ_EBU_BASE_ADDR 0x18000000 -#define LTQ_EBU_SIZE 0x0100 - -#define LTQ_EBU_MODCON 0x000C - -/* GPIO */ -#define LTQ_GPIO0_BASE_ADDR 0x1D810000 -#define LTQ_GPIO0_SIZE 0x0080 -#define LTQ_GPIO1_BASE_ADDR 0x1E800100 -#define LTQ_GPIO1_SIZE 0x0080 -#define LTQ_GPIO2_BASE_ADDR 0x1D810100 -#define LTQ_GPIO2_SIZE 0x0080 -#define LTQ_GPIO3_BASE_ADDR 0x1E800200 -#define LTQ_GPIO3_SIZE 0x0080 -#define LTQ_GPIO4_BASE_ADDR 0x1E800300 -#define LTQ_GPIO4_SIZE 0x0080 -#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000 -#define LTQ_PADCTRL0_SIZE 0x0100 -#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400 -#define LTQ_PADCTRL1_SIZE 0x0100 -#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000 -#define LTQ_PADCTRL2_SIZE 0x0100 -#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500 -#define LTQ_PADCTRL3_SIZE 0x0100 -#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600 -#define LTQ_PADCTRL4_SIZE 0x0100 - -/* I2C */ -#define GPON_I2C_BASE 0x1E200000 -#define GPON_I2C_SIZE 0x00010000 - -/* CHIP ID */ -#define LTQ_STATUS_BASE_ADDR 0x1E802000 - -#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) -#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) -#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) - -/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ -#define LTQ_SYS1_BASE_ADDR 0x1EF00000 -#define LTQ_SYS1_SIZE 0x0100 -#define LTQ_STATUS_BASE_ADDR 0x1E802000 -#define LTQ_STATUS_SIZE 0x0080 -#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000 -#define LTQ_SYS_ETH_SIZE 0x0100 -#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000 -#define LTQ_SYS_GPE_SIZE 0x0100 - -#define SYSCTL_SYS1 0 -#define SYSCTL_SYSETH 1 -#define SYSCTL_SYSGPE 2 - -/* Activation Status Register */ -#define ACTS_ASC1_ACT 0x00000800 -#define ACTS_I2C_ACT 0x00004000 -#define ACTS_P0 0x00010000 -#define ACTS_P1 0x00010000 -#define ACTS_P2 0x00020000 -#define ACTS_P3 0x00020000 -#define ACTS_P4 0x00040000 -#define ACTS_PADCTRL0 0x00100000 -#define ACTS_PADCTRL1 0x00100000 -#define ACTS_PADCTRL2 0x00200000 -#define ACTS_PADCTRL3 0x00200000 -#define ACTS_PADCTRL4 0x00400000 -#define ACTS_I2C_ACT 0x00004000 - -/* global register ranges */ -extern __iomem void *ltq_ebu_membase; -extern __iomem void *ltq_sys1_membase; -#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) -#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) -#define ltq_ebu_w32_mask(clear, set, reg) \ - ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg) - -#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y)) -#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x)) -#define ltq_sys1_w32_mask(clear, set, reg) \ - ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) - -/* gpio wrapper to help configure the pin muxing */ -extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); - -/* to keep the irq code generic we need to define these to 0 as falcon - has no EIU/EBU */ -#define LTQ_EIU_BASE_ADDR 0 -#define LTQ_EBU_PCC_ISTAT 0 - -static inline int ltq_is_ar9(void) -{ - return 0; -} - -static inline int ltq_is_vr9(void) -{ - return 0; -} - -static inline int ltq_is_falcon(void) -{ - return 1; -} - -#endif /* CONFIG_SOC_FALCON */ -#endif /* _LTQ_XWAY_H__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h deleted file mode 100644 index ef564abc3a..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ - - -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - - -/* - * #################################### - * Definition - * #################################### - */ - -/* - * Available Timer/Counter Index - */ -#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) -#define TIMER_ANY 0x00 -#define TIMER1A TIMER(1, 0) -#define TIMER1B TIMER(1, 1) -#define TIMER2A TIMER(2, 0) -#define TIMER2B TIMER(2, 1) -#define TIMER3A TIMER(3, 0) -#define TIMER3B TIMER(3, 1) - -/* - * Flag of Timer/Counter - * These flags specify the way in which timer is configured. - */ -/* Bit size of timer/counter. */ -#define TIMER_FLAG_16BIT 0x0000 -#define TIMER_FLAG_32BIT 0x0001 -/* Switch between timer and counter. */ -#define TIMER_FLAG_TIMER 0x0000 -#define TIMER_FLAG_COUNTER 0x0002 -/* Stop or continue when overflowing/underflowing. */ -#define TIMER_FLAG_ONCE 0x0000 -#define TIMER_FLAG_CYCLIC 0x0004 -/* Count up or counter down. */ -#define TIMER_FLAG_UP 0x0000 -#define TIMER_FLAG_DOWN 0x0008 -/* Count on specific level or edge. */ -#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 -#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 -#define TIMER_FLAG_RISE_EDGE 0x0010 -#define TIMER_FLAG_FALL_EDGE 0x0020 -#define TIMER_FLAG_ANY_EDGE 0x0030 -/* Signal is syncronous to module clock or not. */ -#define TIMER_FLAG_UNSYNC 0x0000 -#define TIMER_FLAG_SYNC 0x0080 -/* Different interrupt handle type. */ -#define TIMER_FLAG_NO_HANDLE 0x0000 -#if defined(__KERNEL__) - #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 -#endif // defined(__KERNEL__) -#define TIMER_FLAG_SIGNAL 0x0300 -/* Internal clock source or external clock source */ -#define TIMER_FLAG_INT_SRC 0x0000 -#define TIMER_FLAG_EXT_SRC 0x1000 - - -/* - * ioctl Command - */ -#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ -#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ -#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ -#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ -#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ -#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ -#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ -#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ - -/* - * Data Type Used to Call ioctl - */ -struct gptu_ioctl_param { - unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * - * GPTU_SET_COUNTER, this field is ID of expected * - * timer/counter. If it's zero, a timer/counter would * - * be dynamically allocated and ID would be stored in * - * this field. * - * In command GPTU_GET_COUNT_VALUE, this field is * - * ignored. * - * In other command, this field is ID of timer/counter * - * allocated. */ - unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * - * GPTU_SET_COUNTER, this field contains flags to * - * specify how to configure timer/counter. * - * In command GPTU_START_TIMER, zero indicate start * - * and non-zero indicate resume timer/counter. * - * In other command, this field is ignored. */ - unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * - * init/reload value. * - * In command GPTU_SET_TIMER, this field contains * - * frequency (0.001Hz) of timer. * - * In command GPTU_GET_COUNT_VALUE, current count * - * value would be stored in this field. * - * In command GPTU_CALCULATE_DIVIDER, this field * - * contains frequency wanted, and after calculation, * - * divider would be stored in this field to overwrite * - * the frequency. * - * In other command, this field is ignored. */ - int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * - * if signal is required, this field contains process * - * ID to which signal would be sent. * - * In other command, this field is ignored. */ - int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * - * if signal is required, this field contains signal * - * number which would be sent. * - * In other command, this field is ignored. */ -}; - -/* - * #################################### - * Data Type - * #################################### - */ -typedef void (*timer_callback)(unsigned long arg); - -extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); -extern int lq_free_timer(unsigned int); -extern int lq_start_timer(unsigned int, int); -extern int lq_stop_timer(unsigned int); -extern int lq_reset_counter_flags(u32 timer, u32 flags); -extern int lq_get_count_value(unsigned int, unsigned long *); -extern u32 lq_cal_divider(unsigned long); -extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -extern int lq_set_counter(unsigned int timer, unsigned int flag, - u32 reload, unsigned long arg1, unsigned long arg2); - -#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h deleted file mode 100644 index 8149f1204e..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h +++ /dev/null @@ -1,56 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __BASE_REG_H -#define __BASE_REG_H - -#ifndef KSEG1 -#define KSEG1 0xA0000000 -#endif - -#define LTQ_EBU_SEG1_BASE (KSEG1 + 0x10000000) -#define LTQ_EBU_SEG2_BASE (KSEG1 + 0x11000000) -#define LTQ_EBU_SEG3_BASE (KSEG1 + 0x12000000) -#define LTQ_EBU_SEG4_BASE (KSEG1 + 0x13000000) - -#define LTQ_ASC0_BASE (KSEG1 + 0x14100100) -#define LTQ_ASC1_BASE (KSEG1 + 0x14100200) - -#define LTQ_SSC0_BASE (0x14100300) -#define LTQ_SSC1_BASE (0x14100400) - -#define LTQ_PORT_P0_BASE (KSEG1 + 0x14100600) -#define LTQ_PORT_P1_BASE (KSEG1 + 0x14108100) -#define LTQ_PORT_P2_BASE (KSEG1 + 0x14100800) -#define LTQ_PORT_P3_BASE (KSEG1 + 0x14100900) -#define LTQ_PORT_P4_BASE (KSEG1 + 0x1E000400) - -#define LTQ_EBU_BASE (KSEG1 + 0x14102000) -#define LTQ_DMA_BASE (KSEG1 + 0x14104000) - -#define LTQ_ICU0_IM3_IM2_BASE (KSEG1 + 0x1E016000) -#define LTQ_ICU0_IM5_IM4_IM1_IM0_BASE (KSEG1 + 0x14106000) - -#define LTQ_ES_BASE (KSEG1 + 0x18000000) - -#define LTQ_SYS0_BASE (KSEG1 + 0x1C000000) -#define LTQ_SYS1_BASE (KSEG1 + 0x1C000800) -#define LTQ_SYS2_BASE (KSEG1 + 0x1E400000) - -#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000) - -#define LTQ_SWINT_BASE (KSEG1 + 0x1E000100) -#define LTQ_MBS_BASE (KSEG1 + 0x1E000200) - -#define LTQ_STATUS_BASE (KSEG1 + 0x1E000500) - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h deleted file mode 100644 index 9c33516e8a..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h +++ /dev/null @@ -1,37 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - -******************************************************************************/ - -#ifndef __BOOT_REG_H -#define __BOOT_REG_H - -#define LTQ_BOOT_CPU_OFFSET 0x20 - -#define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x00) -#define LTQ_BOOT_NVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x04) -#define LTQ_BOOT_EVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x08) -#define LTQ_BOOT_CP0_STATUS(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x0C) -#define LTQ_BOOT_CP0_EPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x10) -#define LTQ_BOOT_CP0_EEPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x14) -#define LTQ_BOOT_SIZE(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP1 */ -#define LTQ_BOOT_RCU_SR(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP0 */ -#define LTQ_BOOT_CFG_STAT(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x1C) - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h deleted file mode 100644 index 9fde2f6dd3..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h +++ /dev/null @@ -1,308 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __DMA_REG_H -#define __DMA_REG_H - -#define dma_r32(reg) ltq_r32(&dma->reg) -#define dma_w32(val, reg) ltq_w32(val, &dma->reg) -#define dma_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &dma->reg) - -/** DMA register structure */ -struct svip_reg_dma { - volatile unsigned long clc; /* 0x00 */ - volatile unsigned long reserved0; /* 0x04 */ - volatile unsigned long id; /* 0x08 */ - volatile unsigned long reserved1; /* 0x0c */ - volatile unsigned long ctrl; /* 0x10 */ - volatile unsigned long cpoll; /* 0x14 */ - volatile unsigned long cs; /* 0x18 */ - volatile unsigned long cctrl; /* 0x1C */ - volatile unsigned long cdba; /* 0x20 */ - volatile unsigned long cdlen; /* 0x24 */ - volatile unsigned long cis; /* 0x28 */ - volatile unsigned long cie; /* 0x2C */ - volatile unsigned long cgbl; /* 0x30 */ - volatile unsigned long reserved2[3]; /* 0x34 */ - volatile unsigned long ps; /* 0x40 */ - volatile unsigned long pctrl; /* 0x44 */ - volatile unsigned long reserved3[43]; /* 0x48 */ - volatile unsigned long irnen; /* 0xF4 */ - volatile unsigned long irncr; /* 0xF8 */ - volatile unsigned long irnicr; /* 0xFC */ -}; - -/******************************************************************************* - * CLC Register - ******************************************************************************/ - -/* Fast Shut-Off Enable Bit (5) */ -#define DMA_CLC_FSOE (0x1 << 5) -#define DMA_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) -#define DMA_CLC_FSOE_GET(val) ((((val) & DMA_CLC_FSOE) >> 5) & 0x1) -#define DMA_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~DMA_CLC_FSOE) | (((val) & 0x1) << 5)) -/* Suspend Bit Write Enable for OCDS (4) */ -#define DMA_CLC_SBWE (0x1 << 4) -#define DMA_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) -#define DMA_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~DMA_CLC_SBWE) | (val) & 1) << 4) -/* External Request Disable (3) */ -#define DMA_CLC_EDIS (0x1 << 3) -#define DMA_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) -#define DMA_CLC_EDIS_GET(val) ((((val) & DMA_CLC_EDIS) >> 3) & 0x1) -#define DMA_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~DMA_CLC_EDIS) | (((val) & 0x1) << 3)) -/* Suspend Enable Bit for OCDS (2) */ -#define DMA_CLC_SPEN (0x1 << 2) -#define DMA_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) -#define DMA_CLC_SPEN_GET(val) ((((val) & DMA_CLC_SPEN) >> 2) & 0x1) -#define DMA_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~DMA_CLC_SPEN) | (((val) & 0x1) << 2)) -/* Disable Status Bit (1) */ -#define DMA_CLC_DISS (0x1 << 1) -#define DMA_CLC_DISS_GET(val) ((((val) & DMA_CLC_DISS) >> 1) & 0x1) -/* Disable Request Bit (0) */ -#define DMA_CLC_DISR (0x1) -#define DMA_CLC_DISR_VAL(val) (((val) & 0x1) << 0) -#define DMA_CLC_DISR_GET(val) ((((val) & DMA_CLC_DISR) >> 0) & 0x1) -#define DMA_CLC_DISR_SET(reg,val) (reg) = ((reg & ~DMA_CLC_DISR) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * ID Register - ******************************************************************************/ - -/* Number of Channels (25:20) */ -#define DMA_ID_CHNR (0x3f << 20) -#define DMA_ID_CHNR_GET(val) ((((val) & DMA_ID_CHNR) >> 20) & 0x3f) -/* Number of Ports (19:16) */ -#define DMA_ID_PRTNR (0xf << 16) -#define DMA_ID_PRTNR_GET(val) ((((val) & DMA_ID_PRTNR) >> 16) & 0xf) -/* Module ID (15:8) */ -#define DMA_ID_ID (0xff << 8) -#define DMA_ID_ID_GET(val) ((((val) & DMA_ID_ID) >> 8) & 0xff) -/* Revision (4:0) */ -#define DMA_ID_REV (0x1f) -#define DMA_ID_REV_GET(val) ((((val) & DMA_ID_REV) >> 0) & 0x1f) - -/******************************************************************************* - * Control Register - ******************************************************************************/ - -/* Global Software Reset (0) */ -#define DMA_CTRL_RST (0x1) -#define DMA_CTRL_RST_GET(val) ((((val) & DMA_CTRL_RST) >> 0) & 0x1) - -/******************************************************************************* - * Channel Polling Register - ******************************************************************************/ - -/* Enable (31) */ -#define DMA_CPOLL_EN (0x1 << 31) -#define DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) -#define DMA_CPOLL_EN_GET(val) ((((val) & DMA_CPOLL_EN) >> 31) & 0x1) -#define DMA_CPOLL_EN_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_EN) | (((val) & 0x1) << 31)) -/* Counter (15:4) */ -#define DMA_CPOLL_CNT (0xfff << 4) -#define DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) -#define DMA_CPOLL_CNT_GET(val) ((((val) & DMA_CPOLL_CNT) >> 4) & 0xfff) -#define DMA_CPOLL_CNT_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_CNT) | (((val) & 0xfff) << 4)) - -/******************************************************************************* - * Global Buffer Length Register - ******************************************************************************/ - -/* Global Buffer Length (15:0) */ -#define DMA_CGBL_GBL (0xffff) -#define DMA_CGBL_GBL_VAL(val) (((val) & 0xffff) << 0) -#define DMA_CGBL_GBL_GET(val) ((((val) & DMA_CGBL_GBL) >> 0) & 0xffff) -#define DMA_CGBL_GBL_SET(reg,val) (reg) = ((reg & ~DMA_CGBL_GBL) | (((val) & 0xffff) << 0)) - -/******************************************************************************* - * Channel Select Register - ******************************************************************************/ - -/* Channel Selection (4:0) */ -#define DMA_CS_CS (0x1f) -#define DMA_CS_CS_VAL(val) (((val) & 0x1f) << 0) -#define DMA_CS_CS_GET(val) ((((val) & DMA_CS_CS) >> 0) & 0x1f) -#define DMA_CS_CS_SET(reg,val) (reg) = ((reg & ~DMA_CS_CS) | (((val) & 0x1f) << 0)) - -/******************************************************************************* - * Channel Control Register - ******************************************************************************/ - -/* Peripheral to Peripheral Copy (24) */ -#define DMA_CCTRL_P2PCPY (0x1 << 24) -#define DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) -#define DMA_CCTRL_P2PCPY_GET(val) ((((val) & DMA_CCTRL_P2PCPY) >> 24) & 0x1) -#define DMA_CCTRL_P2PCPY_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_P2PCPY) | (((val) & 0x1) << 24)) -/* Channel Weight for Transmit Direction (17:16) */ -#define DMA_CCTRL_TXWGT (0x3 << 16) -#define DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) -#define DMA_CCTRL_TXWGT_GET(val) ((((val) & DMA_CCTRL_TXWGT) >> 16) & 0x3) -#define DMA_CCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_TXWGT) | (((val) & 0x3) << 16)) -/* Port Assignment (13:11) */ -#define DMA_CCTRL_PRTNR (0x7 << 11) -#define DMA_CCTRL_PRTNR_GET(val) ((((val) & DMA_CCTRL_PRTNR) >> 11) & 0x7) -/* Class (10:9) */ -#define DMA_CCTRL_CLASS (0x3 << 9) -#define DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) -#define DMA_CCTRL_CLASS_GET(val) ((((val) & DMA_CCTRL_CLASS) >> 9) & 0x3) -#define DMA_CCTRL_CLASS_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_CLASS) | (((val) & 0x3) << 9)) -/* Direction (8) */ -#define DMA_CCTRL_DIR (0x1 << 8) -#define DMA_CCTRL_DIR_GET(val) ((((val) & DMA_CCTRL_DIR) >> 8) & 0x1) -/* Reset (1) */ -#define DMA_CCTRL_RST (0x1 << 1) -#define DMA_CCTRL_RST_VAL(val) (((val) & 0x1) << 1) -#define DMA_CCTRL_RST_GET(val) ((((val) & DMA_CCTRL_RST) >> 1) & 0x1) -#define DMA_CCTRL_RST_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_RST) | (((val) & 0x1) << 1)) -/* Channel On or Off (0) */ -#define DMA_CCTRL_ON_OFF (0x1) -#define DMA_CCTRL_ON_OFF_VAL(val) (((val) & 0x1) << 0) -#define DMA_CCTRL_ON_OFF_GET(val) ((((val) & DMA_CCTRL_ON_OFF) >> 0) & 0x1) -#define DMA_CCTRL_ON_OFF_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_ON_OFF) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Channel Descriptor Base Address Register - ******************************************************************************/ - -/* Channel Descriptor Base Address (29:3) */ -#define DMA_CDBA_CDBA (0x7ffffff << 3) -#define DMA_CDBA_CDBA_VAL(val) (((val) & 0x7ffffff) << 3) -#define DMA_CDBA_CDBA_GET(val) ((((val) & DMA_CDBA_CDBA) >> 3) & 0x7ffffff) -#define DMA_CDBA_CDBA_SET(reg,val) (reg) = ((reg & ~DMA_CDBA_CDBA) | (((val) & 0x7ffffff) << 3)) - -/******************************************************************************* - * Channel Descriptor Length Register - ******************************************************************************/ - -/* Channel Descriptor Length (7:0) */ -#define DMA_CDLEN_CDLEN (0xff) -#define DMA_CDLEN_CDLEN_VAL(val) (((val) & 0xff) << 0) -#define DMA_CDLEN_CDLEN_GET(val) ((((val) & DMA_CDLEN_CDLEN) >> 0) & 0xff) -#define DMA_CDLEN_CDLEN_SET(reg,val) (reg) = ((reg & ~DMA_CDLEN_CDLEN) | (((val) & 0xff) << 0)) - -/******************************************************************************* - * Channel Interrupt Status Register - ******************************************************************************/ - -/* SAI Read Error Interrupt (5) */ -#define DMA_CIS_RDERR (0x1 << 5) -#define DMA_CIS_RDERR_GET(val) ((((val) & DMA_CIS_RDERR) >> 5) & 0x1) -/* Channel Off Interrupt (4) */ -#define DMA_CIS_CHOFF (0x1 << 4) -#define DMA_CIS_CHOFF_GET(val) ((((val) & DMA_CIS_CHOFF) >> 4) & 0x1) -/* Descriptor Complete Interrupt (3) */ -#define DMA_CIS_DESCPT (0x1 << 3) -#define DMA_CIS_DESCPT_GET(val) ((((val) & DMA_CIS_DESCPT) >> 3) & 0x1) -/* Descriptor Under-Run Interrupt (2) */ -#define DMA_CIS_DUR (0x1 << 2) -#define DMA_CIS_DUR_GET(val) ((((val) & DMA_CIS_DUR) >> 2) & 0x1) -/* End of Packet Interrupt (1) */ -#define DMA_CIS_EOP (0x1 << 1) -#define DMA_CIS_EOP_GET(val) ((((val) & DMA_CIS_EOP) >> 1) & 0x1) - -/******************************************************************************* - * Channel Interrupt Enable Register - ******************************************************************************/ - -/* SAI Read Error Interrupt (5) */ -#define DMA_CIE_RDERR (0x1 << 5) -#define DMA_CIE_RDERR_GET(val) ((((val) & DMA_CIE_RDERR) >> 5) & 0x1) -/* Channel Off Interrupt (4) */ -#define DMA_CIE_CHOFF (0x1 << 4) -#define DMA_CIE_CHOFF_GET(val) ((((val) & DMA_CIE_CHOFF) >> 4) & 0x1) -/* Descriptor Complete Interrupt Enable (3) */ -#define DMA_CIE_DESCPT (0x1 << 3) -#define DMA_CIE_DESCPT_GET(val) ((((val) & DMA_CIE_DESCPT) >> 3) & 0x1) -/* Descriptor Under Run Interrupt Enable (2) */ -#define DMA_CIE_DUR (0x1 << 2) -#define DMA_CIE_DUR_GET(val) ((((val) & DMA_CIE_DUR) >> 2) & 0x1) -/* End of Packet Interrupt Enable (1) */ -#define DMA_CIE_EOP (0x1 << 1) -#define DMA_CIE_EOP_GET(val) ((((val) & DMA_CIE_EOP) >> 1) & 0x1) - -/******************************************************************************* - * Port Select Register - ******************************************************************************/ - -/* Port Selection (2:0) */ -#define DMA_PS_PS (0x7) -#define DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) -#define DMA_PS_PS_GET(val) ((((val) & DMA_PS_PS) >> 0) & 0x7) -#define DMA_PS_PS_SET(reg,val) (reg) = ((reg & ~DMA_PS_PS) | (((val) & 0x7) << 0)) - -/******************************************************************************* - * Port Control Register - ******************************************************************************/ - -/* General Purpose Control (16) */ -#define DMA_PCTRL_GPC (0x1 << 16) -#define DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) -#define DMA_PCTRL_GPC_GET(val) ((((val) & DMA_PCTRL_GPC) >> 16) & 0x1) -#define DMA_PCTRL_GPC_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_GPC) | (((val) & 0x1) << 16)) -/* Port Weight for Transmit Direction (14:12) */ -#define DMA_PCTRL_TXWGT (0x7 << 12) -#define DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) -#define DMA_PCTRL_TXWGT_GET(val) ((((val) & DMA_PCTRL_TXWGT) >> 12) & 0x7) -#define DMA_PCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXWGT) | (((val) & 0x7) << 12)) -/* Endianness for Transmit Direction (11:10) */ -#define DMA_PCTRL_TXENDI (0x3 << 10) -#define DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) -#define DMA_PCTRL_TXENDI_GET(val) ((((val) & DMA_PCTRL_TXENDI) >> 10) & 0x3) -#define DMA_PCTRL_TXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXENDI) | (((val) & 0x3) << 10)) -/* Endianness for Receive Direction (9:8) */ -#define DMA_PCTRL_RXENDI (0x3 << 8) -#define DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) -#define DMA_PCTRL_RXENDI_GET(val) ((((val) & DMA_PCTRL_RXENDI) >> 8) & 0x3) -#define DMA_PCTRL_RXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXENDI) | (((val) & 0x3) << 8)) -/* Packet Drop Enable (6) */ -#define DMA_PCTRL_PDEN (0x1 << 6) -#define DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) -#define DMA_PCTRL_PDEN_GET(val) ((((val) & DMA_PCTRL_PDEN) >> 6) & 0x1) -#define DMA_PCTRL_PDEN_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_PDEN) | (((val) & 0x1) << 6)) -/* Burst Length for Transmit Direction (5:4) */ -#define DMA_PCTRL_TXBL (0x3 << 4) -#define DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) -#define DMA_PCTRL_TXBL_GET(val) ((((val) & DMA_PCTRL_TXBL) >> 4) & 0x3) -#define DMA_PCTRL_TXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXBL) | (((val) & 0x3) << 4)) -/* Burst Length for Receive Direction (3:2) */ -#define DMA_PCTRL_RXBL (0x3 << 2) -#define DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) -#define DMA_PCTRL_RXBL_GET(val) ((((val) & DMA_PCTRL_RXBL) >> 2) & 0x3) -#define DMA_PCTRL_RXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXBL) | (((val) & 0x3) << 2)) - -/******************************************************************************* - * DMA_IRNEN Register - ******************************************************************************/ - -/* Channel x Interrupt Request Enable (23) */ -#define DMA_IRNEN_CH23 (0x1 << 23) -#define DMA_IRNEN_CH23_VAL(val) (((val) & 0x1) << 23) -#define DMA_IRNEN_CH23_GET(val) ((((val) & DMA_IRNEN_CH23) >> 23) & 0x1) -#define DMA_IRNEN_CH23_SET(reg,val) (reg) = ((reg & ~DMA_IRNEN_CH23) | (((val) & 0x1) << 23)) - -/******************************************************************************* - * DMA_IRNCR Register - ******************************************************************************/ - -/* Channel x Interrupt (23) */ -#define DMA_IRNCR_CH23 (0x1 << 23) -#define DMA_IRNCR_CH23_GET(val) ((((val) & DMA_IRNCR_CH23) >> 23) & 0x1) - -/******************************************************************************* - * DMA_IRNICR Register - ******************************************************************************/ - -/* Channel x Interrupt Request (23) */ -#define DMA_IRNICR_CH23 (0x1 << 23) -#define DMA_IRNICR_CH23_GET(val) ((((val) & DMA_IRNICR_CH23) >> 23) & 0x1) - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h deleted file mode 100644 index 4e00d01bae..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h +++ /dev/null @@ -1,615 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __EBU_REG_H -#define __EBU_REG_H - -#define ebu_r32(reg) ltq_r32(&ebu->reg) -#define ebu_w32(val, reg) ltq_w32(val, &ebu->reg) -#define ebu_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &ebu->reg) - -/** EBU register structure */ -struct svip_reg_ebu { - volatile unsigned long clc; /* 0x0000 */ - volatile unsigned long reserved0; /* 0x04 */ - volatile unsigned long id; /* 0x0008 */ - volatile unsigned long reserved1; /* 0x0c */ - volatile unsigned long con; /* 0x0010 */ - volatile unsigned long reserved2[3]; /* 0x14 */ - volatile unsigned long addr_sel_0; /* 0x0020 */ - volatile unsigned long addr_sel_1; /* 0x0024 */ - volatile unsigned long addr_sel_2; /* 0x0028 */ - volatile unsigned long addr_sel_3; /* 0x002c */ - volatile unsigned long reserved3[12]; /* 0x30 */ - volatile unsigned long con_0; /* 0x0060 */ - volatile unsigned long con_1; /* 0x0064 */ - volatile unsigned long con_2; /* 0x0068 */ - volatile unsigned long con_3; /* 0x006c */ - volatile unsigned long reserved4[4]; /* 0x70 */ - volatile unsigned long emu_addr; /* 0x0080 */ - volatile unsigned long emu_bc; /* 0x0084 */ - volatile unsigned long emu_con; /* 0x0088 */ - volatile unsigned long reserved5; /* 0x8c */ - volatile unsigned long pcc_con; /* 0x0090 */ - volatile unsigned long pcc_stat; /* 0x0094 */ - volatile unsigned long reserved6[2]; /* 0x98 */ - volatile unsigned long pcc_istat; /* 0x00A0 */ - volatile unsigned long pcc_ien; /* 0x00A4 */ - volatile unsigned long pcc_int_out; /* 0x00A8 */ - volatile unsigned long pcc_irs; /* 0x00AC */ - volatile unsigned long nand_con; /* 0x00B0 */ - volatile unsigned long nand_wait; /* 0x00B4 */ - volatile unsigned long nand_ecc0; /* 0x00B8 */ - volatile unsigned long nand_ecc_ac; /* 0x00BC */ -}; - -/******************************************************************************* - * EBU - ******************************************************************************/ -#define LTQ_EBU_CLC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0000)) -#define LTQ_EBU_ID ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0008)) -#define LTQ_EBU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0010)) -#define LTQ_EBU_ADDR_SEL_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0020)) -#define LTQ_EBU_ADDR_SEL_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0024)) -#define LTQ_EBU_ADDR_SEL_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0028)) -#define LTQ_EBU_ADDR_SEL_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x002c)) -#define LTQ_EBU_CON_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0060)) -#define LTQ_EBU_CON_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0064)) -#define LTQ_EBU_CON_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0068)) -#define LTQ_EBU_CON_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x006c)) -#define LTQ_EBU_EMU_BC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0084)) -#define LTQ_EBU_PCC_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0090)) -#define LTQ_EBU_PCC_STAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0094)) -#define LTQ_EBU_PCC_ISTAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A0)) -#define LTQ_EBU_PCC_IEN ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A4)) -#define LTQ_EBU_PCC_INT_OUT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A8)) -#define LTQ_EBU_PCC_IRS ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00AC)) -#define LTQ_EBU_NAND_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B0)) -#define LTQ_EBU_NAND_WAIT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B4)) -#define LTQ_EBU_NAND_ECC0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B8)) -#define LTQ_EBU_NAND_ECC_AC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00BC)) -#define LTQ_EBU_EMU_ADDR ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0080)) -#define LTQ_EBU_EMU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0088)) - -/******************************************************************************* - * EBU Clock Control Register - ******************************************************************************/ - -/* EBU Disable Status Bit (1) */ -#define LTQ_EBU_CLC_DISS (0x1 << 1) -#define LTQ_EBU_CLC_DISS_GET(val) ((((val) & LTQ_EBU_CLC_DISS) >> 1) & 0x1) -/* Used for Enable/disable Control of the EBU (0) */ -#define LTQ_EBU_CLC_DISR (0x1) -#define LTQ_EBU_CLC_DISR_VAL(val) (((val) & 0x1) << 0) -#define LTQ_EBU_CLC_DISR_GET(val) ((((val) & LTQ_EBU_CLC_DISR) >> 0) & 0x1) -#define LTQ_EBU_CLC_DISR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CLC_DISR) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * EBU Identification Register (Internal) - ******************************************************************************/ - -/* Module Number (31:8) */ -#define LTQ_EBU_ID_MODNUM (0xffffff << 8) -#define LTQ_EBU_ID_MODNUM_GET(val) ((((val) & LTQ_EBU_ID_MODNUM) >> 8) & 0xffffff) -/* Revision Number (7:0) */ -#define LTQ_EBU_ID_REVNUM (0xff) -#define LTQ_EBU_ID_REVNUM_GET(val) ((((val) & LTQ_EBU_ID_REVNUM) >> 0) & 0xff) - -/******************************************************************************* - * External Bus Unit Control Register - ******************************************************************************/ - -/* Driver Turn-Around Control, Chip Select Triggered (22:20) */ -#define LTQ_EBU_CON_DTACS (0x7 << 20) -#define LTQ_EBU_CON_DTACS_VAL(val) (((val) & 0x7) << 20) -#define LTQ_EBU_CON_DTACS_GET(val) ((((val) & LTQ_EBU_CON_DTACS) >> 20) & 0x7) -#define LTQ_EBU_CON_DTACS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTACS) | (((val) & 0x7) << 20)) -/* Driver Turn-Around Control, Read-write Triggered (18:16) */ -#define LTQ_EBU_CON_DTARW (0x7 << 16) -#define LTQ_EBU_CON_DTARW_VAL(val) (((val) & 0x7) << 16) -#define LTQ_EBU_CON_DTARW_GET(val) ((((val) & LTQ_EBU_CON_DTARW) >> 16) & 0x7) -#define LTQ_EBU_CON_DTARW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTARW) | (((val) & 0x7) << 16)) -/* Time-Out Control (15:8) */ -#define LTQ_EBU_CON_TOUTC (0xff << 8) -#define LTQ_EBU_CON_TOUTC_VAL(val) (((val) & 0xff) << 8) -#define LTQ_EBU_CON_TOUTC_GET(val) ((((val) & LTQ_EBU_CON_TOUTC) >> 8) & 0xff) -#define LTQ_EBU_CON_TOUTC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_TOUTC) | (((val) & 0xff) << 8)) -/* Arbitration Mode (7:6) */ -#define LTQ_EBU_CON_ARBMODE (0x3 << 6) -#define LTQ_EBU_CON_ARBMODE_VAL(val) (((val) & 0x3) << 6) -#define LTQ_EBU_CON_ARBMODE_GET(val) ((((val) & LTQ_EBU_CON_ARBMODE) >> 6) & 0x3) -#define LTQ_EBU_CON_ARBMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBMODE) | (((val) & 0x3) << 6)) -/* Arbitration Synchronization (5) */ -#define LTQ_EBU_CON_ARBSYNC (0x1 << 5) -#define LTQ_EBU_CON_ARBSYNC_VAL(val) (((val) & 0x1) << 5) -#define LTQ_EBU_CON_ARBSYNC_GET(val) ((((val) & LTQ_EBU_CON_ARBSYNC) >> 5) & 0x1) -#define LTQ_EBU_CON_ARBSYNC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBSYNC) | (((val) & 0x1) << 5)) - -/******************************************************************************* - * Address Select Registers - ******************************************************************************/ - -/* Memory Region Base Address (31:12) */ -#define LTQ_EBU_ADDR_SEL_0_BASE (0xfffff << 12) -#define LTQ_EBU_ADDR_SEL_0_BASE_VAL(val) (((val) & 0xfffff) << 12) -#define LTQ_EBU_ADDR_SEL_0_BASE_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_BASE) >> 12) & 0xfffff) -#define LTQ_EBU_ADDR_SEL_0_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_BASE) | (((val) & 0xfffff) << 12)) -/* Memory Region Address Mask (7:4) */ -#define LTQ_EBU_ADDR_SEL_0_MASK (0xf << 4) -#define LTQ_EBU_ADDR_SEL_0_MASK_VAL(val) (((val) & 0xf) << 4) -#define LTQ_EBU_ADDR_SEL_0_MASK_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MASK) >> 4) & 0xf) -#define LTQ_EBU_ADDR_SEL_0_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MASK) | (((val) & 0xf) << 4)) -/* Memory Region Mirror Enable Control (1) */ -#define LTQ_EBU_ADDR_SEL_0_MRME (0x1 << 1) -#define LTQ_EBU_ADDR_SEL_0_MRME_VAL(val) (((val) & 0x1) << 1) -#define LTQ_EBU_ADDR_SEL_0_MRME_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MRME) >> 1) & 0x1) -#define LTQ_EBU_ADDR_SEL_0_MRME_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MRME) | (((val) & 0x1) << 1)) -/* Memory Region Enable Control (0) */ -#define LTQ_EBU_ADDR_SEL_0_REGEN (0x1) -#define LTQ_EBU_ADDR_SEL_0_REGEN_VAL(val) (((val) & 0x1) << 0) -#define LTQ_EBU_ADDR_SEL_0_REGEN_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_REGEN) >> 0) & 0x1) -#define LTQ_EBU_ADDR_SEL_0_REGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_REGEN) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Bus Configuration Registers - ******************************************************************************/ - -/* Memory Region Write Protection (31) */ -#define LTQ_EBU_CON_0_WRDIS (0x1 << 31) -#define LTQ_EBU_CON_0_WRDIS_VAL(val) (((val) & 0x1) << 31) -#define LTQ_EBU_CON_0_WRDIS_GET(val) ((((val) & LTQ_EBU_CON_0_WRDIS) >> 31) & 0x1) -#define LTQ_EBU_CON_0_WRDIS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WRDIS) | (((val) & 0x1) << 31)) -/* Address Swapping (30) */ -#define LTQ_EBU_CON_0_ADSWP (0x1 << 30) -#define LTQ_EBU_CON_0_ADSWP_VAL(val) (((val) & 0x1) << 30) -#define LTQ_EBU_CON_0_ADSWP_GET(val) ((((val) & LTQ_EBU_CON_0_ADSWP) >> 30) & 0x1) -#define LTQ_EBU_CON_0_ADSWP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ADSWP) | (((val) & 0x1) << 30)) -/* Address Generation Control (26:24) */ -#define LTQ_EBU_CON_0_AGEN (0x7 << 24) -#define LTQ_EBU_CON_0_AGEN_VAL(val) (((val) & 0x7) << 24) -#define LTQ_EBU_CON_0_AGEN_GET(val) ((((val) & LTQ_EBU_CON_0_AGEN) >> 24) & 0x7) -#define LTQ_EBU_CON_0_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_AGEN) | (((val) & 0x7) << 24)) -/* Extended Address Setup Control (22) */ -#define LTQ_EBU_CON_0_SETUP (0x1 << 22) -#define LTQ_EBU_CON_0_SETUP_VAL(val) (((val) & 0x1) << 22) -#define LTQ_EBU_CON_0_SETUP_GET(val) ((((val) & LTQ_EBU_CON_0_SETUP) >> 22) & 0x1) -#define LTQ_EBU_CON_0_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_SETUP) | (((val) & 0x1) << 22)) -/* Variable Wait-State Insertion Control (21:20) */ -#define LTQ_EBU_CON_0_WAIT (0x3 << 20) -#define LTQ_EBU_CON_0_WAIT_VAL(val) (((val) & 0x3) << 20) -#define LTQ_EBU_CON_0_WAIT_GET(val) ((((val) & LTQ_EBU_CON_0_WAIT) >> 20) & 0x3) -#define LTQ_EBU_CON_0_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAIT) | (((val) & 0x3) << 20)) -/* Active WAIT Level Control (19) */ -#define LTQ_EBU_CON_0_WINV (0x1 << 19) -#define LTQ_EBU_CON_0_WINV_VAL(val) (((val) & 0x1) << 19) -#define LTQ_EBU_CON_0_WINV_GET(val) ((((val) & LTQ_EBU_CON_0_WINV) >> 19) & 0x1) -#define LTQ_EBU_CON_0_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WINV) | (((val) & 0x1) << 19)) -/* External Device Data Width Control (17:16) */ -#define LTQ_EBU_CON_0_PW (0x3 << 16) -#define LTQ_EBU_CON_0_PW_VAL(val) (((val) & 0x3) << 16) -#define LTQ_EBU_CON_0_PW_GET(val) ((((val) & LTQ_EBU_CON_0_PW) >> 16) & 0x3) -#define LTQ_EBU_CON_0_PW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_PW) | (((val) & 0x3) << 16)) -/* Address Latch Enable ALE Duration Control (15:14) */ -#define LTQ_EBU_CON_0_ALEC (0x3 << 14) -#define LTQ_EBU_CON_0_ALEC_VAL(val) (((val) & 0x3) << 14) -#define LTQ_EBU_CON_0_ALEC_GET(val) ((((val) & LTQ_EBU_CON_0_ALEC) >> 14) & 0x3) -#define LTQ_EBU_CON_0_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ALEC) | (((val) & 0x3) << 14)) -/* Byte Control Signal Timing Mode Control (13:12) */ -#define LTQ_EBU_CON_0_BCGEN (0x3 << 12) -#define LTQ_EBU_CON_0_BCGEN_VAL(val) (((val) & 0x3) << 12) -#define LTQ_EBU_CON_0_BCGEN_GET(val) ((((val) & LTQ_EBU_CON_0_BCGEN) >> 12) & 0x3) -#define LTQ_EBU_CON_0_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_BCGEN) | (((val) & 0x3) << 12)) -/* Write Access Wait-State Control (10:8) */ -#define LTQ_EBU_CON_0_WAITWRC (0x7 << 8) -#define LTQ_EBU_CON_0_WAITWRC_VAL(val) (((val) & 0x7) << 8) -#define LTQ_EBU_CON_0_WAITWRC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITWRC) >> 8) & 0x7) -#define LTQ_EBU_CON_0_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITWRC) | (((val) & 0x7) << 8)) -/* Read Access Wait-State Control (7:6) */ -#define LTQ_EBU_CON_0_WAITRDC (0x3 << 6) -#define LTQ_EBU_CON_0_WAITRDC_VAL(val) (((val) & 0x3) << 6) -#define LTQ_EBU_CON_0_WAITRDC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITRDC) >> 6) & 0x3) -#define LTQ_EBU_CON_0_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITRDC) | (((val) & 0x3) << 6)) -/* Hold/Pause Cycle Control (5:4) */ -#define LTQ_EBU_CON_0_HOLDC (0x3 << 4) -#define LTQ_EBU_CON_0_HOLDC_VAL(val) (((val) & 0x3) << 4) -#define LTQ_EBU_CON_0_HOLDC_GET(val) ((((val) & LTQ_EBU_CON_0_HOLDC) >> 4) & 0x3) -#define LTQ_EBU_CON_0_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_HOLDC) | (((val) & 0x3) << 4)) -/* Recovery Cycle Control (3:2) */ -#define LTQ_EBU_CON_0_RECOVC (0x3 << 2) -#define LTQ_EBU_CON_0_RECOVC_VAL(val) (((val) & 0x3) << 2) -#define LTQ_EBU_CON_0_RECOVC_GET(val) ((((val) & LTQ_EBU_CON_0_RECOVC) >> 2) & 0x3) -#define LTQ_EBU_CON_0_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_RECOVC) | (((val) & 0x3) << 2)) -/* Wait Cycle Multiplier Control (1:0) */ -#define LTQ_EBU_CON_0_CMULT (0x3) -#define LTQ_EBU_CON_0_CMULT_VAL(val) (((val) & 0x3) << 0) -#define LTQ_EBU_CON_0_CMULT_GET(val) ((((val) & LTQ_EBU_CON_0_CMULT) >> 0) & 0x3) -#define LTQ_EBU_CON_0_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_CMULT) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * External Bus Unit Emulator Bus Configuration Register - ******************************************************************************/ - -/* Write Protection (31) */ -#define LTQ_EBU_EMU_BC_WRITE (0x1 << 31) -#define LTQ_EBU_EMU_BC_WRITE_VAL(val) (((val) & 0x1) << 31) -#define LTQ_EBU_EMU_BC_WRITE_GET(val) ((((val) & LTQ_EBU_EMU_BC_WRITE) >> 31) & 0x1) -#define LTQ_EBU_EMU_BC_WRITE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WRITE) | (((val) & 0x1) << 31)) -/* Address Generation Control (26:24) */ -#define LTQ_EBU_EMU_BC_AGEN (0x7 << 24) -#define LTQ_EBU_EMU_BC_AGEN_VAL(val) (((val) & 0x7) << 24) -#define LTQ_EBU_EMU_BC_AGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_AGEN) >> 24) & 0x7) -#define LTQ_EBU_EMU_BC_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_AGEN) | (((val) & 0x7) << 24)) -/* Extended Address Setup Control (22) */ -#define LTQ_EBU_EMU_BC_SETUP (0x1 << 22) -#define LTQ_EBU_EMU_BC_SETUP_VAL(val) (((val) & 0x1) << 22) -#define LTQ_EBU_EMU_BC_SETUP_GET(val) ((((val) & LTQ_EBU_EMU_BC_SETUP) >> 22) & 0x1) -#define LTQ_EBU_EMU_BC_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_SETUP) | (((val) & 0x1) << 22)) -/* Variable Waitstate Insertion Control (21:20) */ -#define LTQ_EBU_EMU_BC_WAIT (0x3 << 20) -#define LTQ_EBU_EMU_BC_WAIT_VAL(val) (((val) & 0x3) << 20) -#define LTQ_EBU_EMU_BC_WAIT_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAIT) >> 20) & 0x3) -#define LTQ_EBU_EMU_BC_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAIT) | (((val) & 0x3) << 20)) -/* Active WAIT Level Control (19) */ -#define LTQ_EBU_EMU_BC_WINV (0x1 << 19) -#define LTQ_EBU_EMU_BC_WINV_VAL(val) (((val) & 0x1) << 19) -#define LTQ_EBU_EMU_BC_WINV_GET(val) ((((val) & LTQ_EBU_EMU_BC_WINV) >> 19) & 0x1) -#define LTQ_EBU_EMU_BC_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WINV) | (((val) & 0x1) << 19)) -/* External Device Data Width Control (17:16) */ -#define LTQ_EBU_EMU_BC_PORTW (0x3 << 16) -#define LTQ_EBU_EMU_BC_PORTW_VAL(val) (((val) & 0x3) << 16) -#define LTQ_EBU_EMU_BC_PORTW_GET(val) ((((val) & LTQ_EBU_EMU_BC_PORTW) >> 16) & 0x3) -#define LTQ_EBU_EMU_BC_PORTW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_PORTW) | (((val) & 0x3) << 16)) -/* Address Latch Enable Function (15:14) */ -#define LTQ_EBU_EMU_BC_ALEC (0x3 << 14) -#define LTQ_EBU_EMU_BC_ALEC_VAL(val) (((val) & 0x3) << 14) -#define LTQ_EBU_EMU_BC_ALEC_GET(val) ((((val) & LTQ_EBU_EMU_BC_ALEC) >> 14) & 0x3) -#define LTQ_EBU_EMU_BC_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_ALEC) | (((val) & 0x3) << 14)) -/* Byte Control Signal Timing Mode (13:12) */ -#define LTQ_EBU_EMU_BC_BCGEN (0x3 << 12) -#define LTQ_EBU_EMU_BC_BCGEN_VAL(val) (((val) & 0x3) << 12) -#define LTQ_EBU_EMU_BC_BCGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_BCGEN) >> 12) & 0x3) -#define LTQ_EBU_EMU_BC_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_BCGEN) | (((val) & 0x3) << 12)) -/* Write Access Waitstate Control (10:8) */ -#define LTQ_EBU_EMU_BC_WAITWRC (0x7 << 8) -#define LTQ_EBU_EMU_BC_WAITWRC_VAL(val) (((val) & 0x7) << 8) -#define LTQ_EBU_EMU_BC_WAITWRC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITWRC) >> 8) & 0x7) -#define LTQ_EBU_EMU_BC_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITWRC) | (((val) & 0x7) << 8)) -/* Read Access Waitstate Control (7:6) */ -#define LTQ_EBU_EMU_BC_WAITRDC (0x3 << 6) -#define LTQ_EBU_EMU_BC_WAITRDC_VAL(val) (((val) & 0x3) << 6) -#define LTQ_EBU_EMU_BC_WAITRDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITRDC) >> 6) & 0x3) -#define LTQ_EBU_EMU_BC_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITRDC) | (((val) & 0x3) << 6)) -/* Hold/Pause Cycle Control (5:4) */ -#define LTQ_EBU_EMU_BC_HOLDC (0x3 << 4) -#define LTQ_EBU_EMU_BC_HOLDC_VAL(val) (((val) & 0x3) << 4) -#define LTQ_EBU_EMU_BC_HOLDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_HOLDC) >> 4) & 0x3) -#define LTQ_EBU_EMU_BC_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_HOLDC) | (((val) & 0x3) << 4)) -/* Recovery Cycles Control (3:2) */ -#define LTQ_EBU_EMU_BC_RECOVC (0x3 << 2) -#define LTQ_EBU_EMU_BC_RECOVC_VAL(val) (((val) & 0x3) << 2) -#define LTQ_EBU_EMU_BC_RECOVC_GET(val) ((((val) & LTQ_EBU_EMU_BC_RECOVC) >> 2) & 0x3) -#define LTQ_EBU_EMU_BC_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_RECOVC) | (((val) & 0x3) << 2)) -/* Cycle Multiplier Control (1:0) */ -#define LTQ_EBU_EMU_BC_CMULT (0x3) -#define LTQ_EBU_EMU_BC_CMULT_VAL(val) (((val) & 0x3) << 0) -#define LTQ_EBU_EMU_BC_CMULT_GET(val) ((((val) & LTQ_EBU_EMU_BC_CMULT) >> 0) & 0x3) -#define LTQ_EBU_EMU_BC_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_CMULT) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * PC-Card Control Register - ******************************************************************************/ - -/* External Interrupt Input IREQ (3:1) */ -#define LTQ_EBU_PCC_CON_IREQ (0x7 << 1) -#define LTQ_EBU_PCC_CON_IREQ_VAL(val) (((val) & 0x7) << 1) -#define LTQ_EBU_PCC_CON_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_CON_IREQ) >> 1) & 0x7) -#define LTQ_EBU_PCC_CON_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_IREQ) | (((val) & 0x7) << 1)) -/* PC Card ON (0) */ -#define LTQ_EBU_PCC_CON_ON (0x1) -#define LTQ_EBU_PCC_CON_ON_VAL(val) (((val) & 0x1) << 0) -#define LTQ_EBU_PCC_CON_ON_GET(val) ((((val) & LTQ_EBU_PCC_CON_ON) >> 0) & 0x1) -#define LTQ_EBU_PCC_CON_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_ON) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * PCC Status Register - ******************************************************************************/ - -/* Interrupt Request (6) */ -#define LTQ_EBU_PCC_STAT_IRQ (0x1 << 6) -#define LTQ_EBU_PCC_STAT_IRQ_GET(val) ((((val) & LTQ_EBU_PCC_STAT_IRQ) >> 6) & 0x1) -/* PC-Card Overcurrent (5) */ -#define LTQ_EBU_PCC_STAT_OC (0x1 << 5) -#define LTQ_EBU_PCC_STAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_STAT_OC) >> 5) & 0x1) -/* PC-Card Socket Power On (4) */ -#define LTQ_EBU_PCC_STAT_SPON (0x1 << 4) -#define LTQ_EBU_PCC_STAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_STAT_SPON) >> 4) & 0x1) -/* Card Detect Status (1:0) */ -#define LTQ_EBU_PCC_STAT_CD (0x3) -#define LTQ_EBU_PCC_STAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_STAT_CD) >> 0) & 0x3) - -/******************************************************************************* - * PCC Interrupt Status Register - ******************************************************************************/ - -/* Interrupt Request Active Interrupt (4) */ -#define LTQ_EBU_PCC_ISTAT_IREQ (0x1 << 4) -#define LTQ_EBU_PCC_ISTAT_IREQ_VAL(val) (((val) & 0x1) << 4) -#define LTQ_EBU_PCC_ISTAT_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_IREQ) >> 4) & 0x1) -#define LTQ_EBU_PCC_ISTAT_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_IREQ) | (((val) & 0x1) << 4)) -/* Over Current Status Change Interrupt (3) */ -#define LTQ_EBU_PCC_ISTAT_OC (0x1 << 3) -#define LTQ_EBU_PCC_ISTAT_OC_VAL(val) (((val) & 0x1) << 3) -#define LTQ_EBU_PCC_ISTAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_OC) >> 3) & 0x1) -#define LTQ_EBU_PCC_ISTAT_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_OC) | (((val) & 0x1) << 3)) -/* Socket Power on Status Change Interrupt (2) */ -#define LTQ_EBU_PCC_ISTAT_SPON (0x1 << 2) -#define LTQ_EBU_PCC_ISTAT_SPON_VAL(val) (((val) & 0x1) << 2) -#define LTQ_EBU_PCC_ISTAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_SPON) >> 2) & 0x1) -#define LTQ_EBU_PCC_ISTAT_SPON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_SPON) | (((val) & 0x1) << 2)) -/* Voltage Sense Status Change Interrupt (1) */ -#define LTQ_EBU_PCC_ISTAT_VS (0x1 << 1) -#define LTQ_EBU_PCC_ISTAT_VS_VAL(val) (((val) & 0x1) << 1) -#define LTQ_EBU_PCC_ISTAT_VS_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_VS) >> 1) & 0x1) -#define LTQ_EBU_PCC_ISTAT_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_VS) | (((val) & 0x1) << 1)) -/* Card Detect Status Change Interrupt (0) */ -#define LTQ_EBU_PCC_ISTAT_CD (0x1) -#define LTQ_EBU_PCC_ISTAT_CD_VAL(val) (((val) & 0x1) << 0) -#define LTQ_EBU_PCC_ISTAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_CD) >> 0) & 0x1) -#define LTQ_EBU_PCC_ISTAT_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_CD) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * PCC Interrupt Enable Register - ******************************************************************************/ - -/* Enable of Interrupt Request IR (4) */ -#define LTQ_EBU_PCC_IEN_IR (0x1 << 4) -#define LTQ_EBU_PCC_IEN_IR_VAL(val) (((val) & 0x1) << 4) -#define LTQ_EBU_PCC_IEN_IR_GET(val) ((((val) & LTQ_EBU_PCC_IEN_IR) >> 4) & 0x1) -#define LTQ_EBU_PCC_IEN_IR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_IR) | (((val) & 0x1) << 4)) -/* Enable of Interrupt Request OC event (3) */ -#define LTQ_EBU_PCC_IEN_OC (0x1 << 3) -#define LTQ_EBU_PCC_IEN_OC_VAL(val) (((val) & 0x1) << 3) -#define LTQ_EBU_PCC_IEN_OC_GET(val) ((((val) & LTQ_EBU_PCC_IEN_OC) >> 3) & 0x1) -#define LTQ_EBU_PCC_IEN_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_OC) | (((val) & 0x1) << 3)) -/* Enable of Interrupt Request Socket Power On (2) */ -#define LTQ_EBU_PCC_IEN_PWRON (0x1 << 2) -#define LTQ_EBU_PCC_IEN_PWRON_VAL(val) (((val) & 0x1) << 2) -#define LTQ_EBU_PCC_IEN_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_IEN_PWRON) >> 2) & 0x1) -#define LTQ_EBU_PCC_IEN_PWRON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_PWRON) | (((val) & 0x1) << 2)) -/* Enable of Interrupt Request Voltage Sense (1) */ -#define LTQ_EBU_PCC_IEN_VS (0x1 << 1) -#define LTQ_EBU_PCC_IEN_VS_VAL(val) (((val) & 0x1) << 1) -#define LTQ_EBU_PCC_IEN_VS_GET(val) ((((val) & LTQ_EBU_PCC_IEN_VS) >> 1) & 0x1) -#define LTQ_EBU_PCC_IEN_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_VS) | (((val) & 0x1) << 1)) -/* Enable of Interrupt Request Card Detect (0) */ -#define LTQ_EBU_PCC_IEN_CD (0x1) -#define LTQ_EBU_PCC_IEN_CD_VAL(val) (((val) & 0x1) << 0) -#define LTQ_EBU_PCC_IEN_CD_GET(val) ((((val) & LTQ_EBU_PCC_IEN_CD) >> 0) & 0x1) -#define LTQ_EBU_PCC_IEN_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_CD) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * PCC Interrupt Output Status Register - ******************************************************************************/ - -/* Status of Interrupt Request IR (4) */ -#define LTQ_EBU_PCC_INT_OUT_IR (0x1 << 4) -#define LTQ_EBU_PCC_INT_OUT_IR_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_IR) >> 4) & 0x1) -/* Status of Interrupt Request OC (3) */ -#define LTQ_EBU_PCC_INT_OUT_OC (0x1 << 3) -#define LTQ_EBU_PCC_INT_OUT_OC_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_OC) >> 3) & 0x1) -/* Status of Interrupt Request Socket Power On (2) */ -#define LTQ_EBU_PCC_INT_OUT_PWRON (0x1 << 2) -#define LTQ_EBU_PCC_INT_OUT_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_PWRON) >> 2) & 0x1) -/* Status of Interrupt Request Voltage Sense (1) */ -#define LTQ_EBU_PCC_INT_OUT_VS (0x1 << 1) -#define LTQ_EBU_PCC_INT_OUT_VS_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_VS) >> 1) & 0x1) -/* Status of Interrupt Request Card Detect (0) */ -#define LTQ_EBU_PCC_INT_OUT_CD (0x1) -#define LTQ_EBU_PCC_INT_OUT_CD_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_CD) >> 0) & 0x1) - -/******************************************************************************* - * PCC Interrupt Request Set Register - ******************************************************************************/ - -/* Set Interrupt Request IR (4) */ -#define LTQ_EBU_PCC_IRS_IR (0x1 << 4) -#define LTQ_EBU_PCC_IRS_IR_VAL(val) (((val) & 0x1) << 4) -#define LTQ_EBU_PCC_IRS_IR_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_IR) | (val) & 1) << 4) -/* Set Interrupt Request OC (3) */ -#define LTQ_EBU_PCC_IRS_OC (0x1 << 3) -#define LTQ_EBU_PCC_IRS_OC_VAL(val) (((val) & 0x1) << 3) -#define LTQ_EBU_PCC_IRS_OC_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_OC) | (val) & 1) << 3) -/* Set Interrupt Request Socket Power On (2) */ -#define LTQ_EBU_PCC_IRS_PWRON (0x1 << 2) -#define LTQ_EBU_PCC_IRS_PWRON_VAL(val) (((val) & 0x1) << 2) -#define LTQ_EBU_PCC_IRS_PWRON_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_PWRON) | (val) & 1) << 2) -/* Set Interrupt Request Voltage Sense (1) */ -#define LTQ_EBU_PCC_IRS_VS (0x1 << 1) -#define LTQ_EBU_PCC_IRS_VS_VAL(val) (((val) & 0x1) << 1) -#define LTQ_EBU_PCC_IRS_VS_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_VS) | (val) & 1) << 1) -/* Set Interrupt Request Card Detect (0) */ -#define LTQ_EBU_PCC_IRS_CD (0x1) -#define LTQ_EBU_PCC_IRS_CD_VAL(val) (((val) & 0x1) << 0) -#define LTQ_EBU_PCC_IRS_CD_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_CD) | (val) & 1) << 0) - -/******************************************************************************* - * NAND Flash Control Register - ******************************************************************************/ - -/* ECC Enabling (31) */ -#define LTQ_EBU_NAND_CON_ECC_ON (0x1 << 31) -#define LTQ_EBU_NAND_CON_ECC_ON_VAL(val) (((val) & 0x1) << 31) -#define LTQ_EBU_NAND_CON_ECC_ON_GET(val) ((((val) & LTQ_EBU_NAND_CON_ECC_ON) >> 31) & 0x1) -#define LTQ_EBU_NAND_CON_ECC_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ECC_ON) | (((val) & 0x1) << 31)) -/* Latch enable (23:18) */ -#define LTQ_EBU_NAND_CON_LAT_EN (0x3f << 18) -#define LTQ_EBU_NAND_CON_LAT_EN_VAL(val) (((val) & 0x3f) << 18) -#define LTQ_EBU_NAND_CON_LAT_EN_GET(val) ((((val) & LTQ_EBU_NAND_CON_LAT_EN) >> 18) & 0x3f) -#define LTQ_EBU_NAND_CON_LAT_EN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_LAT_EN) | (((val) & 0x3f) << 18)) -/* Output ChipSelect# Selection (11:10) */ -#define LTQ_EBU_NAND_CON_OUT_CS_S (0x3 << 10) -#define LTQ_EBU_NAND_CON_OUT_CS_S_VAL(val) (((val) & 0x3) << 10) -#define LTQ_EBU_NAND_CON_OUT_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_OUT_CS_S) >> 10) & 0x3) -#define LTQ_EBU_NAND_CON_OUT_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_OUT_CS_S) | (((val) & 0x3) << 10)) -/* Input ChipSelect# Selection (9:8) */ -#define LTQ_EBU_NAND_CON_IN_CS_S (0x3 << 8) -#define LTQ_EBU_NAND_CON_IN_CS_S_VAL(val) (((val) & 0x3) << 8) -#define LTQ_EBU_NAND_CON_IN_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_IN_CS_S) >> 8) & 0x3) -#define LTQ_EBU_NAND_CON_IN_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_IN_CS_S) | (((val) & 0x3) << 8)) -/* Set PRE (7) */ -#define LTQ_EBU_NAND_CON_PRE_P (0x1 << 7) -#define LTQ_EBU_NAND_CON_PRE_P_VAL(val) (((val) & 0x1) << 7) -#define LTQ_EBU_NAND_CON_PRE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_PRE_P) >> 7) & 0x1) -#define LTQ_EBU_NAND_CON_PRE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_PRE_P) | (((val) & 0x1) << 7)) -/* Set WP Active Polarity (6) */ -#define LTQ_EBU_NAND_CON_WP_P (0x1 << 6) -#define LTQ_EBU_NAND_CON_WP_P_VAL(val) (((val) & 0x1) << 6) -#define LTQ_EBU_NAND_CON_WP_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_WP_P) >> 6) & 0x1) -#define LTQ_EBU_NAND_CON_WP_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_WP_P) | (((val) & 0x1) << 6)) -/* Set SE Active Polarity (5) */ -#define LTQ_EBU_NAND_CON_SE_P (0x1 << 5) -#define LTQ_EBU_NAND_CON_SE_P_VAL(val) (((val) & 0x1) << 5) -#define LTQ_EBU_NAND_CON_SE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_SE_P) >> 5) & 0x1) -#define LTQ_EBU_NAND_CON_SE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_SE_P) | (((val) & 0x1) << 5)) -/* Set CS Active Polarity (4) */ -#define LTQ_EBU_NAND_CON_CS_P (0x1 << 4) -#define LTQ_EBU_NAND_CON_CS_P_VAL(val) (((val) & 0x1) << 4) -#define LTQ_EBU_NAND_CON_CS_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CS_P) >> 4) & 0x1) -#define LTQ_EBU_NAND_CON_CS_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CS_P) | (((val) & 0x1) << 4)) -/* Set CLE Active Polarity (3) */ -#define LTQ_EBU_NAND_CON_CLE_P (0x1 << 3) -#define LTQ_EBU_NAND_CON_CLE_P_VAL(val) (((val) & 0x1) << 3) -#define LTQ_EBU_NAND_CON_CLE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CLE_P) >> 3) & 0x1) -#define LTQ_EBU_NAND_CON_CLE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CLE_P) | (((val) & 0x1) << 3)) -/* Set ALE Active Polarity (2) */ -#define LTQ_EBU_NAND_CON_ALE_P (0x1 << 2) -#define LTQ_EBU_NAND_CON_ALE_P_VAL(val) (((val) & 0x1) << 2) -#define LTQ_EBU_NAND_CON_ALE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_ALE_P) >> 2) & 0x1) -#define LTQ_EBU_NAND_CON_ALE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ALE_P) | (((val) & 0x1) << 2)) -/* NAND CS Mux with EBU CS Enable (1) */ -#define LTQ_EBU_NAND_CON_CSMUX_E (0x1 << 1) -#define LTQ_EBU_NAND_CON_CSMUX_E_VAL(val) (((val) & 0x1) << 1) -#define LTQ_EBU_NAND_CON_CSMUX_E_GET(val) ((((val) & LTQ_EBU_NAND_CON_CSMUX_E) >> 1) & 0x1) -#define LTQ_EBU_NAND_CON_CSMUX_E_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CSMUX_E) | (((val) & 0x1) << 1)) -/* NAND FLASH Mode Support (0) */ -#define LTQ_EBU_NAND_CON_NANDMODE (0x1) -#define LTQ_EBU_NAND_CON_NANDMODE_VAL(val) (((val) & 0x1) << 0) -#define LTQ_EBU_NAND_CON_NANDMODE_GET(val) ((((val) & LTQ_EBU_NAND_CON_NANDMODE) >> 0) & 0x1) -#define LTQ_EBU_NAND_CON_NANDMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_NANDMODE) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * NAND Flash State Register - ******************************************************************************/ - -/* Reserved (31:3) */ -#define LTQ_EBU_NAND_WAIT_RES (0x1fffffff << 3) -#define LTQ_EBU_NAND_WAIT_RES_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RES) >> 3) & 0x1fffffff) -/* NAND Write Complete (3) */ -#define LTQ_EBU_NAND_WAIT_WR_C (0x1 << 3) -#define LTQ_EBU_NAND_WAIT_WR_C_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_WR_C) >> 3) & 0x1) -/* Record the RD Edge (rising ) (2) */ -#define LTQ_EBU_NAND_WAIT_RD_EDGE (0x1 << 2) -#define LTQ_EBU_NAND_WAIT_RD_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RD_EDGE) >> 2) & 0x1) -/* Record the BY# Edge (falling) (1) */ -#define LTQ_EBU_NAND_WAIT_BY_EDGE (0x1 << 1) -#define LTQ_EBU_NAND_WAIT_BY_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_BY_EDGE) >> 1) & 0x1) -/* Rd/BY# value (0) */ -#define LTQ_EBU_NAND_WAIT_RDBY_VALUE (0x1) -#define LTQ_EBU_NAND_WAIT_RDBY_VALUE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RDBY_VALUE) >> 0) & 0x1) - -/******************************************************************************* - * NAND ECC Result Register 0 - ******************************************************************************/ - -/* Reserved (31:24) */ -#define LTQ_EBU_NAND_ECC0_RES (0xff << 24) -#define LTQ_EBU_NAND_ECC0_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_RES) >> 24) & 0xff) -/* ECC value (23:16) */ -#define LTQ_EBU_NAND_ECC0_ECC_B2 (0xff << 16) -#define LTQ_EBU_NAND_ECC0_ECC_B2_VAL(val) (((val) & 0xff) << 16) -#define LTQ_EBU_NAND_ECC0_ECC_B2_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B2) >> 16) & 0xff) -#define LTQ_EBU_NAND_ECC0_ECC_B2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B2) | (((val) & 0xff) << 16)) -/* ECC value (15:8) */ -#define LTQ_EBU_NAND_ECC0_ECC_B1 (0xff << 8) -#define LTQ_EBU_NAND_ECC0_ECC_B1_VAL(val) (((val) & 0xff) << 8) -#define LTQ_EBU_NAND_ECC0_ECC_B1_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B1) >> 8) & 0xff) -#define LTQ_EBU_NAND_ECC0_ECC_B1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B1) | (((val) & 0xff) << 8)) -/* ECC value (7:0) */ -#define LTQ_EBU_NAND_ECC0_ECC_B0 (0xff) -#define LTQ_EBU_NAND_ECC0_ECC_B0_VAL(val) (((val) & 0xff) << 0) -#define LTQ_EBU_NAND_ECC0_ECC_B0_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B0) >> 0) & 0xff) -#define LTQ_EBU_NAND_ECC0_ECC_B0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B0) | (((val) & 0xff) << 0)) - -/******************************************************************************* - * NAND ECC Address Counter Register - ******************************************************************************/ - -/* Reserved (31:9) */ -#define LTQ_EBU_NAND_ECC_AC_RES (0x7fffff << 9) -#define LTQ_EBU_NAND_ECC_AC_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_RES) >> 9) & 0x7fffff) -/* ECC address counter (8:0) */ -#define LTQ_EBU_NAND_ECC_AC_ECC_AC (0x1ff) -#define LTQ_EBU_NAND_ECC_AC_ECC_AC_VAL(val) (((val) & 0x1ff) << 0) -#define LTQ_EBU_NAND_ECC_AC_ECC_AC_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_ECC_AC) >> 0) & 0x1ff) -#define LTQ_EBU_NAND_ECC_AC_ECC_AC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC_AC_ECC_AC) | (((val) & 0x1ff) << 0)) - -/******************************************************************************* - * Internal Address Emulation Register - ******************************************************************************/ - -/* Memory Region Base Address (31:12) */ -#define LTQ_EBU_EMU_ADDR_BASE (0xfffff << 12) -#define LTQ_EBU_EMU_ADDR_BASE_VAL(val) (((val) & 0xfffff) << 12) -#define LTQ_EBU_EMU_ADDR_BASE_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_BASE) >> 12) & 0xfffff) -#define LTQ_EBU_EMU_ADDR_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_BASE) | (((val) & 0xfffff) << 12)) -/* Memory Region Address Mask (7:4) */ -#define LTQ_EBU_EMU_ADDR_MASK (0xf << 4) -#define LTQ_EBU_EMU_ADDR_MASK_VAL(val) (((val) & 0xf) << 4) -#define LTQ_EBU_EMU_ADDR_MASK_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MASK) >> 4) & 0xf) -#define LTQ_EBU_EMU_ADDR_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MASK) | (((val) & 0xf) << 4)) -/* Memory Region Mirror Segment B Control (1) */ -#define LTQ_EBU_EMU_ADDR_MRMB (0x1 << 1) -#define LTQ_EBU_EMU_ADDR_MRMB_VAL(val) (((val) & 0x1) << 1) -#define LTQ_EBU_EMU_ADDR_MRMB_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MRMB) >> 1) & 0x1) -#define LTQ_EBU_EMU_ADDR_MRMB_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MRMB) | (((val) & 0x1) << 1)) -/* Memory Region Enable Control (0) */ -#define LTQ_EBU_EMU_ADDR_MREC (0x1) -#define LTQ_EBU_EMU_ADDR_MREC_VAL(val) (((val) & 0x1) << 0) -#define LTQ_EBU_EMU_ADDR_MREC_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MREC) >> 0) & 0x1) -#define LTQ_EBU_EMU_ADDR_MREC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MREC) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * nternal Emulator Configuration Register - ******************************************************************************/ - -/* Overlay Memory Control Region 3 (3) */ -#define LTQ_EBU_EMU_CON_OVL3 (0x1 << 3) -#define LTQ_EBU_EMU_CON_OVL3_VAL(val) (((val) & 0x1) << 3) -#define LTQ_EBU_EMU_CON_OVL3_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL3) >> 3) & 0x1) -#define LTQ_EBU_EMU_CON_OVL3_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL3) | (((val) & 0x1) << 3)) -/* Overlay Memory Control Region 2 (2) */ -#define LTQ_EBU_EMU_CON_OVL2 (0x1 << 2) -#define LTQ_EBU_EMU_CON_OVL2_VAL(val) (((val) & 0x1) << 2) -#define LTQ_EBU_EMU_CON_OVL2_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL2) >> 2) & 0x1) -#define LTQ_EBU_EMU_CON_OVL2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL2) | (((val) & 0x1) << 2)) -/* Overlay Memory Control Region 1 (1) */ -#define LTQ_EBU_EMU_CON_OVL1 (0x1 << 1) -#define LTQ_EBU_EMU_CON_OVL1_VAL(val) (((val) & 0x1) << 1) -#define LTQ_EBU_EMU_CON_OVL1_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL1) >> 1) & 0x1) -#define LTQ_EBU_EMU_CON_OVL1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL1) | (((val) & 0x1) << 1)) -/* Overlay Memory Control Region 0 (0) */ -#define LTQ_EBU_EMU_CON_OVL0 (0x1) -#define LTQ_EBU_EMU_CON_OVL0_VAL(val) (((val) & 0x1) << 0) -#define LTQ_EBU_EMU_CON_OVL0_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL0) >> 0) & 0x1) -#define LTQ_EBU_EMU_CON_OVL0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL0) | (((val) & 0x1) << 0)) - -#endif /* __LTQ_EBU_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h deleted file mode 100644 index da84900f5e..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h +++ /dev/null @@ -1,2098 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __ES_REG_H -#define __ES_REG_H - -#define es_r32(reg) ltq_r32(&es->reg) -#define es_w32(val, reg) ltq_w32(val, &es->reg) -#define es_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &es->reg) - -/** ES register structure */ -struct svip_reg_es { - volatile unsigned long ps; /* 0x0000 */ - volatile unsigned long p0_ctl; /* 0x0004 */ - volatile unsigned long p1_ctl; /* 0x0008 */ - volatile unsigned long p2_ctl; /* 0x000C */ - volatile unsigned long p0_vlan; /* 0x0010 */ - volatile unsigned long p1_vlan; /* 0x0014 */ - volatile unsigned long p2_vlan; /* 0x0018 */ - volatile unsigned long reserved1[1]; /* 0x001C */ - volatile unsigned long p0_inctl; /* 0x0020 */ - volatile unsigned long p1_inctl; /* 0x0024 */ - volatile unsigned long p2_inctl; /* 0x0028 */ - volatile unsigned long reserved2[1]; /* 0x002C */ - volatile unsigned long p0_ecs_q32; /* 0x0030 */ - volatile unsigned long p0_ecs_q10; /* 0x0034 */ - volatile unsigned long p0_ecw_q32; /* 0x0038 */ - volatile unsigned long p0_ecw_q10; /* 0x003C */ - volatile unsigned long p1_ecs_q32; /* 0x0040 */ - volatile unsigned long p1_ecs_q10; /* 0x0044 */ - volatile unsigned long p1_ecw_q32; /* 0x0048 */ - volatile unsigned long p1_ecw_q10; /* 0x004C */ - volatile unsigned long p2_ecs_q32; /* 0x0050 */ - volatile unsigned long p2_ecs_q10; /* 0x0054 */ - volatile unsigned long p2_ecw_q32; /* 0x0058 */ - volatile unsigned long p2_ecw_q10; /* 0x005C */ - volatile unsigned long int_ena; /* 0x0060 */ - volatile unsigned long int_st; /* 0x0064 */ - volatile unsigned long sw_gctl0; /* 0x0068 */ - volatile unsigned long sw_gctl1; /* 0x006C */ - volatile unsigned long arp; /* 0x0070 */ - volatile unsigned long strm_ctl; /* 0x0074 */ - volatile unsigned long rgmii_ctl; /* 0x0078 */ - volatile unsigned long prt_1p; /* 0x007C */ - volatile unsigned long gbkt_szbs; /* 0x0080 */ - volatile unsigned long gbkt_szebs; /* 0x0084 */ - volatile unsigned long bf_th; /* 0x0088 */ - volatile unsigned long pmac_hd_ctl; /* 0x008C */ - volatile unsigned long pmac_sa1; /* 0x0090 */ - volatile unsigned long pmac_sa2; /* 0x0094 */ - volatile unsigned long pmac_da1; /* 0x0098 */ - volatile unsigned long pmac_da2; /* 0x009C */ - volatile unsigned long pmac_vlan; /* 0x00A0 */ - volatile unsigned long pmac_tx_ipg; /* 0x00A4 */ - volatile unsigned long pmac_rx_ipg; /* 0x00A8 */ - volatile unsigned long adr_tb_ctl0; /* 0x00AC */ - volatile unsigned long adr_tb_ctl1; /* 0x00B0 */ - volatile unsigned long adr_tb_ctl2; /* 0x00B4 */ - volatile unsigned long adr_tb_st0; /* 0x00B8 */ - volatile unsigned long adr_tb_st1; /* 0x00BC */ - volatile unsigned long adr_tb_st2; /* 0x00C0 */ - volatile unsigned long rmon_ctl; /* 0x00C4 */ - volatile unsigned long rmon_st; /* 0x00C8 */ - volatile unsigned long mdio_ctl; /* 0x00CC */ - volatile unsigned long mdio_data; /* 0x00D0 */ - volatile unsigned long tp_flt_act; /* 0x00D4 */ - volatile unsigned long prtcl_flt_act; /* 0x00D8 */ - volatile unsigned long reserved4[9]; /* 0xdc */ - volatile unsigned long vlan_flt0; /* 0x0100 */ - volatile unsigned long vlan_flt1; /* 0x0104 */ - volatile unsigned long vlan_flt2; /* 0x0108 */ - volatile unsigned long vlan_flt3; /* 0x010C */ - volatile unsigned long vlan_flt4; /* 0x0110 */ - volatile unsigned long vlan_flt5; /* 0x0114 */ - volatile unsigned long vlan_flt6; /* 0x0118 */ - volatile unsigned long vlan_flt7; /* 0x011C */ - volatile unsigned long vlan_flt8; /* 0x0120 */ - volatile unsigned long vlan_flt9; /* 0x0124 */ - volatile unsigned long vlan_flt10; /* 0x0128 */ - volatile unsigned long vlan_flt11; /* 0x012C */ - volatile unsigned long vlan_flt12; /* 0x0130 */ - volatile unsigned long vlan_flt13; /* 0x0134 */ - volatile unsigned long vlan_flt14; /* 0x0138 */ - volatile unsigned long vlan_flt15; /* 0x013C */ - volatile unsigned long tp_flt10; /* 0x0140 */ - volatile unsigned long tp_flt32; /* 0x0144 */ - volatile unsigned long tp_flt54; /* 0x0148 */ - volatile unsigned long tp_flt76; /* 0x014C */ - volatile unsigned long dfsrv_map0; /* 0x0150 */ - volatile unsigned long dfsrv_map1; /* 0x0154 */ - volatile unsigned long dfsrv_map2; /* 0x0158 */ - volatile unsigned long dfsrv_map3; /* 0x015C */ - volatile unsigned long tcp_pf0; /* 0x0160 */ - volatile unsigned long tcp_pf1; /* 0x0164 */ - volatile unsigned long tcp_pf2; /* 0x0168 */ - volatile unsigned long tcp_pf3; /* 0x016C */ - volatile unsigned long tcp_pf4; /* 0x0170 */ - volatile unsigned long tcp_pf5; /* 0x0174 */ - volatile unsigned long tcp_pf6; /* 0x0178 */ - volatile unsigned long tcp_pf7; /* 0x017C */ - volatile unsigned long ra_03_00; /* 0x0180 */ - volatile unsigned long ra_07_04; /* 0x0184 */ - volatile unsigned long ra_0b_08; /* 0x0188 */ - volatile unsigned long ra_0f_0c; /* 0x018C */ - volatile unsigned long ra_13_10; /* 0x0190 */ - volatile unsigned long ra_17_14; /* 0x0194 */ - volatile unsigned long ra_1b_18; /* 0x0198 */ - volatile unsigned long ra_1f_1c; /* 0x019C */ - volatile unsigned long ra_23_20; /* 0x01A0 */ - volatile unsigned long ra_27_24; /* 0x01A4 */ - volatile unsigned long ra_2b_28; /* 0x01A8 */ - volatile unsigned long ra_2f_2c; /* 0x01AC */ - volatile unsigned long prtcl_f0; /* 0x01B0 */ - volatile unsigned long prtcl_f1; /* 0x01B4 */ -}; - -/******************************************************************************* - * ES - ******************************************************************************/ -#define LTQ_ES_PS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0000)) -#define LTQ_ES_P0_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0004)) -#define LTQ_ES_P1_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0008)) -#define LTQ_ES_P2_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x000C)) -#define LTQ_ES_P0_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) -#define LTQ_ES_P1_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0014)) -#define LTQ_ES_P2_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) -#define LTQ_ES_P0_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0020)) -#define LTQ_ES_P1_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0024)) -#define LTQ_ES_P2_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0028)) -#define LTQ_ES_P0_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) -#define LTQ_ES_P0_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) -#define LTQ_ES_P0_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) -#define LTQ_ES_P0_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) -#define LTQ_ES_P1_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) -#define LTQ_ES_P1_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) -#define LTQ_ES_P1_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) -#define LTQ_ES_P1_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) -#define LTQ_ES_P2_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) -#define LTQ_ES_P2_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) -#define LTQ_ES_P2_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) -#define LTQ_ES_P2_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) -#define LTQ_ES_INT_ENA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0060)) -#define LTQ_ES_INT_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0064)) -#define LTQ_ES_SW_GCTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0068)) -#define LTQ_ES_SW_GCTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x006C)) -#define LTQ_ES_ARP_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0070)) -#define LTQ_ES_STRM_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0074)) -#define LTQ_ES_RGMII_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0078)) -#define LTQ_ES_PRT_1P_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x007C)) -#define LTQ_ES_GBKT_SZBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0080)) -#define LTQ_ES_GBKT_SZEBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0084)) -#define LTQ_ES_BF_TH_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0088)) -#define LTQ_ES_PMAC_HD_CTL ((volatile unsigned int*)(LTQ_ES_BASE + 0x008C)) -#define LTQ_ES_PMAC_SA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0090)) -#define LTQ_ES_PMAC_SA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0094)) -#define LTQ_ES_PMAC_DA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0098)) -#define LTQ_ES_PMAC_DA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x009C)) -#define LTQ_ES_PMAC_VLAN ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A0)) -#define LTQ_ES_PMAC_TX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A4)) -#define LTQ_ES_PMAC_RX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A8)) -#define LTQ_ES_ADR_TB_CTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00AC)) -#define LTQ_ES_ADR_TB_CTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B0)) -#define LTQ_ES_ADR_TB_CTL2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B4)) -#define LTQ_ES_ADR_TB_ST0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B8)) -#define LTQ_ES_ADR_TB_ST1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00BC)) -#define LTQ_ES_ADR_TB_ST2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C0)) -#define LTQ_ES_RMON_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C4)) -#define LTQ_ES_RMON_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C8)) -#define LTQ_ES_MDIO_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00CC)) -#define LTQ_ES_MDIO_DATA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D0)) -#define LTQ_ES_TP_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D4)) -#define LTQ_ES_PRTCL_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D8)) -#define LTQ_ES_VLAN_FLT0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0100)) -#define LTQ_ES_VLAN_FLT1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0104)) -#define LTQ_ES_VLAN_FLT2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0108)) -#define LTQ_ES_VLAN_FLT3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x010C)) -#define LTQ_ES_VLAN_FLT4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0110)) -#define LTQ_ES_VLAN_FLT5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0114)) -#define LTQ_ES_VLAN_FLT6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0118)) -#define LTQ_ES_VLAN_FLT7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x011C)) -#define LTQ_ES_VLAN_FLT8_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0120)) -#define LTQ_ES_VLAN_FLT9_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0124)) -#define LTQ_ES_VLAN_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0128)) -#define LTQ_ES_VLAN_FLT11_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x012C)) -#define LTQ_ES_VLAN_FLT12_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0130)) -#define LTQ_ES_VLAN_FLT13_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0134)) -#define LTQ_ES_VLAN_FLT14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0138)) -#define LTQ_ES_VLAN_FLT15_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x013C)) -#define LTQ_ES_TP_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0140)) -#define LTQ_ES_TP_FLT32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0144)) -#define LTQ_ES_TP_FLT54_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0148)) -#define LTQ_ES_TP_FLT76_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x014C)) -#define LTQ_ES_DFSRV_MAP0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0150)) -#define LTQ_ES_DFSRV_MAP1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0154)) -#define LTQ_ES_DFSRV_MAP2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0158)) -#define LTQ_ES_DFSRV_MAP3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x015C)) -#define LTQ_ES_TCP_PF0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0160)) -#define LTQ_ES_TCP_PF1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0164)) -#define LTQ_ES_TCP_PF2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0168)) -#define LTQ_ES_TCP_PF3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x016C)) -#define LTQ_ES_TCP_PF4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0170)) -#define LTQ_ES_TCP_PF5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0174)) -#define LTQ_ES_TCP_PF6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0178)) -#define LTQ_ES_TCP_PF7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x017C)) -#define LTQ_ES_RA_03_00_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0180)) -#define LTQ_ES_RA_07_04_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0184)) -#define LTQ_ES_RA_0B_08_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0188)) -#define LTQ_ES_RA_0F_0C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x018C)) -#define LTQ_ES_RA_13_10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0190)) -#define LTQ_ES_RA_17_14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0194)) -#define LTQ_ES_RA_1B_18_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0198)) -#define LTQ_ES_RA_1F_1C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x019C)) -#define LTQ_ES_RA_23_20_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A0)) -#define LTQ_ES_RA_27_24_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A4)) -#define LTQ_ES_RA_2B_28_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A8)) -#define LTQ_ES_RA_2F_2C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01AC)) -#define LTQ_ES_PRTCL_F0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B0)) -#define LTQ_ES_PRTCL_F1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B4)) - -/******************************************************************************* - * Port Status Register - ******************************************************************************/ - -/* Port 1 Flow Control Status (12) */ -#define LTQ_ES_PS_REG_P1FCS (0x1 << 12) -#define LTQ_ES_PS_REG_P1FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P1FCS) >> 12) & 0x1) -/* Port 1 Duplex Status (11) */ -#define LTQ_ES_PS_REG_P1DS (0x1 << 11) -#define LTQ_ES_PS_REG_P1DS_GET(val) ((((val) & LTQ_ES_PS_REG_P1DS) >> 11) & 0x1) -/* Port 1 Speed High Status (10) */ -#define LTQ_ES_PS_REG_P1SHS (0x1 << 10) -#define LTQ_ES_PS_REG_P1SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SHS) >> 10) & 0x1) -/* Port 1 Speed Status (9) */ -#define LTQ_ES_PS_REG_P1SS (0x1 << 9) -#define LTQ_ES_PS_REG_P1SS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SS) >> 9) & 0x1) -/* Port 1 Link Status (8) */ -#define LTQ_ES_PS_REG_P1LS (0x1 << 8) -#define LTQ_ES_PS_REG_P1LS_GET(val) ((((val) & LTQ_ES_PS_REG_P1LS) >> 8) & 0x1) -/* Port 0 Flow Control Status (4) */ -#define LTQ_ES_PS_REG_P0FCS (0x1 << 4) -#define LTQ_ES_PS_REG_P0FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P0FCS) >> 4) & 0x1) -/* Port 0 Duplex Status (3) */ -#define LTQ_ES_PS_REG_P0DS (0x1 << 3) -#define LTQ_ES_PS_REG_P0DS_GET(val) ((((val) & LTQ_ES_PS_REG_P0DS) >> 3) & 0x1) -/* Port 0 Speed High Status (2) */ -#define LTQ_ES_PS_REG_P0SHS (0x1 << 2) -#define LTQ_ES_PS_REG_P0SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SHS) >> 2) & 0x1) -/* Port 0 Speed Status (1) */ -#define LTQ_ES_PS_REG_P0SS (0x1 << 1) -#define LTQ_ES_PS_REG_P0SS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SS) >> 1) & 0x1) -/* Port 0 Link Status (0) */ -#define LTQ_ES_PS_REG_P0LS (0x1) -#define LTQ_ES_PS_REG_P0LS_GET(val) ((((val) & LTQ_ES_PS_REG_P0LS) >> 0) & 0x1) - -/******************************************************************************* - * P0 Control Register - ******************************************************************************/ - -/* STP/RSTP port state (31:30) */ -#define LTQ_ES_P0_CTL_REG_SPS (0x3 << 30) -#define LTQ_ES_P0_CTL_REG_SPS_VAL(val) (((val) & 0x3) << 30) -#define LTQ_ES_P0_CTL_REG_SPS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPS) >> 30) & 0x3) -#define LTQ_ES_P0_CTL_REG_SPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPS) | (((val) & 0x3) << 30)) -/* TCP/UDP PRIEN (29) */ -#define LTQ_ES_P0_CTL_REG_TCPE (0x1 << 29) -#define LTQ_ES_P0_CTL_REG_TCPE_VAL(val) (((val) & 0x1) << 29) -#define LTQ_ES_P0_CTL_REG_TCPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TCPE) >> 29) & 0x1) -#define LTQ_ES_P0_CTL_REG_TCPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TCPE) | (((val) & 0x1) << 29)) -/* IP over TCP/UDP (28) */ -#define LTQ_ES_P0_CTL_REG_IPOVTU (0x1 << 28) -#define LTQ_ES_P0_CTL_REG_IPOVTU_VAL(val) (((val) & 0x1) << 28) -#define LTQ_ES_P0_CTL_REG_IPOVTU_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPOVTU) >> 28) & 0x1) -#define LTQ_ES_P0_CTL_REG_IPOVTU_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPOVTU) | (((val) & 0x1) << 28)) -/* VLAN Priority Enable (27) */ -#define LTQ_ES_P0_CTL_REG_VPE (0x1 << 27) -#define LTQ_ES_P0_CTL_REG_VPE_VAL(val) (((val) & 0x1) << 27) -#define LTQ_ES_P0_CTL_REG_VPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_VPE) >> 27) & 0x1) -#define LTQ_ES_P0_CTL_REG_VPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_VPE) | (((val) & 0x1) << 27)) -/* Service Priority Enable (26) */ -#define LTQ_ES_P0_CTL_REG_SPE (0x1 << 26) -#define LTQ_ES_P0_CTL_REG_SPE_VAL(val) (((val) & 0x1) << 26) -#define LTQ_ES_P0_CTL_REG_SPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPE) >> 26) & 0x1) -#define LTQ_ES_P0_CTL_REG_SPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPE) | (((val) & 0x1) << 26)) -/* IP over VLAN PRI (25) */ -#define LTQ_ES_P0_CTL_REG_IPVLAN (0x1 << 25) -#define LTQ_ES_P0_CTL_REG_IPVLAN_VAL(val) (((val) & 0x1) << 25) -#define LTQ_ES_P0_CTL_REG_IPVLAN_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPVLAN) >> 25) & 0x1) -#define LTQ_ES_P0_CTL_REG_IPVLAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPVLAN) | (((val) & 0x1) << 25)) -/* Ether Type Priority Enable (24) */ -#define LTQ_ES_P0_CTL_REG_TPE (0x1 << 24) -#define LTQ_ES_P0_CTL_REG_TPE_VAL(val) (((val) & 0x1) << 24) -#define LTQ_ES_P0_CTL_REG_TPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TPE) >> 24) & 0x1) -#define LTQ_ES_P0_CTL_REG_TPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TPE) | (((val) & 0x1) << 24)) -/* Force Link Up (18) */ -#define LTQ_ES_P0_CTL_REG_FLP (0x1 << 18) -#define LTQ_ES_P0_CTL_REG_FLP_VAL(val) (((val) & 0x1) << 18) -#define LTQ_ES_P0_CTL_REG_FLP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLP) >> 18) & 0x1) -#define LTQ_ES_P0_CTL_REG_FLP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLP) | (((val) & 0x1) << 18)) -/* Force Link Down (17) */ -#define LTQ_ES_P0_CTL_REG_FLD (0x1 << 17) -#define LTQ_ES_P0_CTL_REG_FLD_VAL(val) (((val) & 0x1) << 17) -#define LTQ_ES_P0_CTL_REG_FLD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLD) >> 17) & 0x1) -#define LTQ_ES_P0_CTL_REG_FLD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLD) | (((val) & 0x1) << 17)) -/* Ratio Mode for WFQ (16) */ -#define LTQ_ES_P0_CTL_REG_RMWFQ (0x1 << 16) -#define LTQ_ES_P0_CTL_REG_RMWFQ_VAL(val) (((val) & 0x1) << 16) -#define LTQ_ES_P0_CTL_REG_RMWFQ_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_RMWFQ) >> 16) & 0x1) -#define LTQ_ES_P0_CTL_REG_RMWFQ_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_RMWFQ) | (((val) & 0x1) << 16)) -/* Aging Disable (15) */ -#define LTQ_ES_P0_CTL_REG_AD (0x1 << 15) -#define LTQ_ES_P0_CTL_REG_AD_VAL(val) (((val) & 0x1) << 15) -#define LTQ_ES_P0_CTL_REG_AD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_AD) >> 15) & 0x1) -#define LTQ_ES_P0_CTL_REG_AD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_AD) | (((val) & 0x1) << 15)) -/* Learning Disable (14) */ -#define LTQ_ES_P0_CTL_REG_LD (0x1 << 14) -#define LTQ_ES_P0_CTL_REG_LD_VAL(val) (((val) & 0x1) << 14) -#define LTQ_ES_P0_CTL_REG_LD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_LD) >> 14) & 0x1) -#define LTQ_ES_P0_CTL_REG_LD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_LD) | (((val) & 0x1) << 14)) -/* Maximum Number of Addresses (12:8) */ -#define LTQ_ES_P0_CTL_REG_MNA024 (0x1f << 8) -#define LTQ_ES_P0_CTL_REG_MNA024_VAL(val) (((val) & 0x1f) << 8) -#define LTQ_ES_P0_CTL_REG_MNA024_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_MNA024) >> 8) & 0x1f) -#define LTQ_ES_P0_CTL_REG_MNA024_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_MNA024) | (((val) & 0x1f) << 8)) -/* PPPOE Port Only (7) */ -#define LTQ_ES_P0_CTL_REG_PPPOEP (0x1 << 7) -#define LTQ_ES_P0_CTL_REG_PPPOEP_VAL(val) (((val) & 0x1) << 7) -#define LTQ_ES_P0_CTL_REG_PPPOEP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PPPOEP) >> 7) & 0x1) -#define LTQ_ES_P0_CTL_REG_PPPOEP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PPPOEP) | (((val) & 0x1) << 7)) -/* PPPOE Manage (6) */ -#define LTQ_ES_P0_CTL_REG_PM (0x1 << 6) -#define LTQ_ES_P0_CTL_REG_PM_VAL(val) (((val) & 0x1) << 6) -#define LTQ_ES_P0_CTL_REG_PM_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PM) >> 6) & 0x1) -#define LTQ_ES_P0_CTL_REG_PM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PM) | (((val) & 0x1) << 6)) -/* Port Mirror Option (5:4) */ -#define LTQ_ES_P0_CTL_REG_IPMO (0x3 << 4) -#define LTQ_ES_P0_CTL_REG_IPMO_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_P0_CTL_REG_IPMO_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPMO) >> 4) & 0x3) -#define LTQ_ES_P0_CTL_REG_IPMO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPMO) | (((val) & 0x3) << 4)) -/* 802.1x Port Authorized state (3:2) */ -#define LTQ_ES_P0_CTL_REG_PAS (0x3 << 2) -#define LTQ_ES_P0_CTL_REG_PAS_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_P0_CTL_REG_PAS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PAS) >> 2) & 0x3) -#define LTQ_ES_P0_CTL_REG_PAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PAS) | (((val) & 0x3) << 2)) -/* Drop Scheme for voilation 802.1x (1) */ -#define LTQ_ES_P0_CTL_REG_DSV8021X (0x1 << 1) -#define LTQ_ES_P0_CTL_REG_DSV8021X_VAL(val) (((val) & 0x1) << 1) -#define LTQ_ES_P0_CTL_REG_DSV8021X_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_DSV8021X) >> 1) & 0x1) -#define LTQ_ES_P0_CTL_REG_DSV8021X_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_DSV8021X) | (((val) & 0x1) << 1)) -/* ByPass Mode for Output (0) */ -#define LTQ_ES_P0_CTL_REG_BYPASS (0x1) -#define LTQ_ES_P0_CTL_REG_BYPASS_VAL(val) (((val) & 0x1) << 0) -#define LTQ_ES_P0_CTL_REG_BYPASS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_BYPASS) >> 0) & 0x1) -#define LTQ_ES_P0_CTL_REG_BYPASS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_BYPASS) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 0 VLAN Control Register - ******************************************************************************/ - -/* Default FID (31:30) */ -#define LTQ_ES_P0_VLAN_REG_DFID (0x3 << 30) -#define LTQ_ES_P0_VLAN_REG_DFID_VAL(val) (((val) & 0x3) << 30) -#define LTQ_ES_P0_VLAN_REG_DFID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DFID) >> 30) & 0x3) -#define LTQ_ES_P0_VLAN_REG_DFID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DFID) | (((val) & 0x3) << 30)) -/* Tagged Base VLAN Enable (29) */ -#define LTQ_ES_P0_VLAN_REG_TBVE (0x1 << 29) -#define LTQ_ES_P0_VLAN_REG_TBVE_VAL(val) (((val) & 0x1) << 29) -#define LTQ_ES_P0_VLAN_REG_TBVE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_TBVE) >> 29) & 0x1) -#define LTQ_ES_P0_VLAN_REG_TBVE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_TBVE) | (((val) & 0x1) << 29)) -/* Input Force No TAG Enable (28) */ -#define LTQ_ES_P0_VLAN_REG_IFNTE (0x1 << 28) -#define LTQ_ES_P0_VLAN_REG_IFNTE_VAL(val) (((val) & 0x1) << 28) -#define LTQ_ES_P0_VLAN_REG_IFNTE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_IFNTE) >> 28) & 0x1) -#define LTQ_ES_P0_VLAN_REG_IFNTE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_IFNTE) | (((val) & 0x1) << 28)) -/* VID Check with the VID table (27) */ -#define LTQ_ES_P0_VLAN_REG_VC (0x1 << 27) -#define LTQ_ES_P0_VLAN_REG_VC_VAL(val) (((val) & 0x1) << 27) -#define LTQ_ES_P0_VLAN_REG_VC_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VC) >> 27) & 0x1) -#define LTQ_ES_P0_VLAN_REG_VC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VC) | (((val) & 0x1) << 27)) -/* VLAN Security Disable (26) */ -#define LTQ_ES_P0_VLAN_REG_VSD (0x1 << 26) -#define LTQ_ES_P0_VLAN_REG_VSD_VAL(val) (((val) & 0x1) << 26) -#define LTQ_ES_P0_VLAN_REG_VSD_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VSD) >> 26) & 0x1) -#define LTQ_ES_P0_VLAN_REG_VSD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VSD) | (((val) & 0x1) << 26)) -/* Admit Only VLAN_Tagged Packet (25) */ -#define LTQ_ES_P0_VLAN_REG_AOVTP (0x1 << 25) -#define LTQ_ES_P0_VLAN_REG_AOVTP_VAL(val) (((val) & 0x1) << 25) -#define LTQ_ES_P0_VLAN_REG_AOVTP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_AOVTP) >> 25) & 0x1) -#define LTQ_ES_P0_VLAN_REG_AOVTP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_AOVTP) | (((val) & 0x1) << 25)) -/* VLAN Member Check Enable (24) */ -#define LTQ_ES_P0_VLAN_REG_VMCE (0x1 << 24) -#define LTQ_ES_P0_VLAN_REG_VMCE_VAL(val) (((val) & 0x1) << 24) -#define LTQ_ES_P0_VLAN_REG_VMCE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VMCE) >> 24) & 0x1) -#define LTQ_ES_P0_VLAN_REG_VMCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VMCE) | (((val) & 0x1) << 24)) -/* Reserved (23:19) */ -#define LTQ_ES_P0_VLAN_REG_RES (0x1f << 19) -#define LTQ_ES_P0_VLAN_REG_RES_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_RES) >> 19) & 0x1f) -/* Default VLAN Port Map (18:16) */ -#define LTQ_ES_P0_VLAN_REG_DVPM (0x7 << 16) -#define LTQ_ES_P0_VLAN_REG_DVPM_VAL(val) (((val) & 0x7) << 16) -#define LTQ_ES_P0_VLAN_REG_DVPM_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DVPM) >> 16) & 0x7) -#define LTQ_ES_P0_VLAN_REG_DVPM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DVPM) | (((val) & 0x7) << 16)) -/* Port Priority (15:14) */ -#define LTQ_ES_P0_VLAN_REG_PP (0x3 << 14) -#define LTQ_ES_P0_VLAN_REG_PP_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_P0_VLAN_REG_PP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PP) >> 14) & 0x3) -#define LTQ_ES_P0_VLAN_REG_PP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PP) | (((val) & 0x3) << 14)) -/* Port Priority Enable (13) */ -#define LTQ_ES_P0_VLAN_REG_PPE (0x1 << 13) -#define LTQ_ES_P0_VLAN_REG_PPE_VAL(val) (((val) & 0x1) << 13) -#define LTQ_ES_P0_VLAN_REG_PPE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PPE) >> 13) & 0x1) -#define LTQ_ES_P0_VLAN_REG_PPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PPE) | (((val) & 0x1) << 13)) -/* Portbase VLAN tag member for Port 0 (12) */ -#define LTQ_ES_P0_VLAN_REG_PVTAGMP (0x1 << 12) -#define LTQ_ES_P0_VLAN_REG_PVTAGMP_VAL(val) (((val) & 0x1) << 12) -#define LTQ_ES_P0_VLAN_REG_PVTAGMP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVTAGMP) >> 12) & 0x1) -#define LTQ_ES_P0_VLAN_REG_PVTAGMP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVTAGMP) | (((val) & 0x1) << 12)) -/* PVID (11:0) */ -#define LTQ_ES_P0_VLAN_REG_PVID (0xfff) -#define LTQ_ES_P0_VLAN_REG_PVID_VAL(val) (((val) & 0xfff) << 0) -#define LTQ_ES_P0_VLAN_REG_PVID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVID) >> 0) & 0xfff) -#define LTQ_ES_P0_VLAN_REG_PVID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVID) | (((val) & 0xfff) << 0)) - -/******************************************************************************* - * Port 0 Ingress Control Register - ******************************************************************************/ - -/* Reserved (31:13) */ -#define LTQ_ES_P0_INCTL_REG_RES (0x7ffff << 13) -#define LTQ_ES_P0_INCTL_REG_RES_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_RES) >> 13) & 0x7ffff) -/* Port 0 Ingress/Egress Timer Tick T selection (12:11) */ -#define LTQ_ES_P0_INCTL_REG_P0ITT (0x3 << 11) -#define LTQ_ES_P0_INCTL_REG_P0ITT_VAL(val) (((val) & 0x3) << 11) -#define LTQ_ES_P0_INCTL_REG_P0ITT_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITT) >> 11) & 0x3) -#define LTQ_ES_P0_INCTL_REG_P0ITT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITT) | (((val) & 0x3) << 11)) -/* Port 0 Igress Token R (10:0) */ -#define LTQ_ES_P0_INCTL_REG_P0ITR (0x7ff) -#define LTQ_ES_P0_INCTL_REG_P0ITR_VAL(val) (((val) & 0x7ff) << 0) -#define LTQ_ES_P0_INCTL_REG_P0ITR_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITR) >> 0) & 0x7ff) -#define LTQ_ES_P0_INCTL_REG_P0ITR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITR) | (((val) & 0x7ff) << 0)) - -/******************************************************************************* - * Port 0 Egress Control for Strict Q32 Register - ******************************************************************************/ - -/* Port 0 Egress Token R for Strict Priority Q3 (26:16) */ -#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR (0x7ff << 16) -#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_VAL(val) (((val) & 0x7ff) << 16) -#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) >> 16) & 0x7ff) -#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) | (((val) & 0x7ff) << 16)) -/* Port 0 Egress Token R for Strict Priority Q2 (10:0) */ -#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR (0x7ff) -#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_VAL(val) (((val) & 0x7ff) << 0) -#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) >> 0) & 0x7ff) -#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) | (((val) & 0x7ff) << 0)) - -/******************************************************************************* - * Port 0 Egress Control for Strict Q10 Register - ******************************************************************************/ - -/* Reserved (31:27) */ -#define LTQ_ES_P0_ECS_Q10_REG_RES (0x1f << 27) -#define LTQ_ES_P0_ECS_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_RES) >> 27) & 0x1f) -/* Port 0 Egress Token R for Strict Priority Q1 (26:16) */ -#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR (0x7ff << 16) -#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_VAL(val) (((val) & 0x7ff) << 16) -#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) >> 16) & 0x7ff) -#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) | (((val) & 0x7ff) << 16)) -/* Port 0 Egress Token R for Strict Priority Q0 (10:0) */ -#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR (0x7ff) -#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_VAL(val) (((val) & 0x7ff) << 0) -#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) >> 0) & 0x7ff) -#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) | (((val) & 0x7ff) << 0)) - -/******************************************************************************* - * Port 0 Egress Control for WFQ Q32 Register - ******************************************************************************/ - -/* Reserved (31:27) */ -#define LTQ_ES_P0_ECW_Q32_REG_RES (0x1f << 27) -#define LTQ_ES_P0_ECW_Q32_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_RES) >> 27) & 0x1f) -/* Port 0 Egress Token R for WFQ Q3 (26:16) */ -#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR (0x7ff << 16) -#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_VAL(val) (((val) & 0x7ff) << 16) -#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) >> 16) & 0x7ff) -#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) | (((val) & 0x7ff) << 16)) -/* Port 0 Egress Token R for WFQ Q2 (10:0) */ -#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR (0x7ff) -#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_VAL(val) (((val) & 0x7ff) << 0) -#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) >> 0) & 0x7ff) -#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) | (((val) & 0x7ff) << 0)) - -/******************************************************************************* - * Port 0 Egress Control for WFQ Q10 Register - ******************************************************************************/ - -/* Reserved (31:27) */ -#define LTQ_ES_P0_ECW_Q10_REG_RES (0x1f << 27) -#define LTQ_ES_P0_ECW_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_RES) >> 27) & 0x1f) -/* Port 0 Egress Token R for WFQ Q1 (26:16) */ -#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR (0x7ff << 16) -#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_VAL(val) (((val) & 0x7ff) << 16) -#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) >> 16) & 0x7ff) -#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) | (((val) & 0x7ff) << 16)) -/* Port 0 Egress Token R for WFQ Q0 (10:0) */ -#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR (0x7ff) -#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_VAL(val) (((val) & 0x7ff) << 0) -#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) >> 0) & 0x7ff) -#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) | (((val) & 0x7ff) << 0)) - -/******************************************************************************* - * Interrupt Enable Register - ******************************************************************************/ - -/* Reserved (31:8) */ -#define LTQ_ES_INT_ENA_REG_RES (0xffffff << 8) -#define LTQ_ES_INT_ENA_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_RES) >> 8) & 0xffffff) -/* Data Buffer is Full Interrupt Enable (7) */ -#define LTQ_ES_INT_ENA_REG_DBFIE (0x1 << 7) -#define LTQ_ES_INT_ENA_REG_DBFIE_VAL(val) (((val) & 0x1) << 7) -#define LTQ_ES_INT_ENA_REG_DBFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBFIE) >> 7) & 0x1) -#define LTQ_ES_INT_ENA_REG_DBFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBFIE) | (((val) & 0x1) << 7)) -/* Data Buffer is nearly Full Interrupt Enable (6) */ -#define LTQ_ES_INT_ENA_REG_DBNFIE (0x1 << 6) -#define LTQ_ES_INT_ENA_REG_DBNFIE_VAL(val) (((val) & 0x1) << 6) -#define LTQ_ES_INT_ENA_REG_DBNFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBNFIE) >> 6) & 0x1) -#define LTQ_ES_INT_ENA_REG_DBNFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBNFIE) | (((val) & 0x1) << 6)) -/* Learning Table Full Interrupt Enable (5) */ -#define LTQ_ES_INT_ENA_REG_LTFIE (0x1 << 5) -#define LTQ_ES_INT_ENA_REG_LTFIE_VAL(val) (((val) & 0x1) << 5) -#define LTQ_ES_INT_ENA_REG_LTFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTFIE) >> 5) & 0x1) -#define LTQ_ES_INT_ENA_REG_LTFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTFIE) | (((val) & 0x1) << 5)) -/* Leaning Table Access Done Interrupt Enable (4) */ -#define LTQ_ES_INT_ENA_REG_LTADIE (0x1 << 4) -#define LTQ_ES_INT_ENA_REG_LTADIE_VAL(val) (((val) & 0x1) << 4) -#define LTQ_ES_INT_ENA_REG_LTADIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTADIE) >> 4) & 0x1) -#define LTQ_ES_INT_ENA_REG_LTADIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTADIE) | (((val) & 0x1) << 4)) -/* Port Security Violation Interrupt Enable (3:1) */ -#define LTQ_ES_INT_ENA_REG_PSVIE (0x7 << 1) -#define LTQ_ES_INT_ENA_REG_PSVIE_VAL(val) (((val) & 0x7) << 1) -#define LTQ_ES_INT_ENA_REG_PSVIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSVIE) >> 1) & 0x7) -#define LTQ_ES_INT_ENA_REG_PSVIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSVIE) | (((val) & 0x7) << 1)) -/* Port Status Change Interrupt Enable (0) */ -#define LTQ_ES_INT_ENA_REG_PSCIE (0x1) -#define LTQ_ES_INT_ENA_REG_PSCIE_VAL(val) (((val) & 0x1) << 0) -#define LTQ_ES_INT_ENA_REG_PSCIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSCIE) >> 0) & 0x1) -#define LTQ_ES_INT_ENA_REG_PSCIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSCIE) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Interrupt Status Register - ******************************************************************************/ - -/* Reserved (31:8) */ -#define LTQ_ES_INT_ST_REG_RES (0xffffff << 8) -#define LTQ_ES_INT_ST_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ST_REG_RES) >> 8) & 0xffffff) -/* Data Buffer is Full (7) */ -#define LTQ_ES_INT_ST_REG_DBF (0x1 << 7) -#define LTQ_ES_INT_ST_REG_DBF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBF) >> 7) & 0x1) -/* Data Buffer is nearly Full (6) */ -#define LTQ_ES_INT_ST_REG_DBNF (0x1 << 6) -#define LTQ_ES_INT_ST_REG_DBNF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBNF) >> 6) & 0x1) -/* Learning Table Full (5) */ -#define LTQ_ES_INT_ST_REG_LTF (0x1 << 5) -#define LTQ_ES_INT_ST_REG_LTF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTF) >> 5) & 0x1) -/* Leaning Table Access Done (4) */ -#define LTQ_ES_INT_ST_REG_LTAD (0x1 << 4) -#define LTQ_ES_INT_ST_REG_LTAD_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTAD) >> 4) & 0x1) -/* Port Security Violation (3:1) */ -#define LTQ_ES_INT_ST_REG_PSV (0x7 << 1) -#define LTQ_ES_INT_ST_REG_PSV_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSV) >> 1) & 0x7) -/* Port Status Change (0) */ -#define LTQ_ES_INT_ST_REG_PSC (0x1) -#define LTQ_ES_INT_ST_REG_PSC_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSC) >> 0) & 0x1) - -/******************************************************************************* - * Switch Global Control Register 0 - ******************************************************************************/ - -/* Switch Enable (31) */ -#define LTQ_ES_SW_GCTL0_REG_SE (0x1 << 31) -#define LTQ_ES_SW_GCTL0_REG_SE_VAL(val) (((val) & 0x1) << 31) -#define LTQ_ES_SW_GCTL0_REG_SE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SE) >> 31) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_SE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SE) | (((val) & 0x1) << 31)) -/* CRC Check Disable (30) */ -#define LTQ_ES_SW_GCTL0_REG_ICRCCD (0x1 << 30) -#define LTQ_ES_SW_GCTL0_REG_ICRCCD_VAL(val) (((val) & 0x1) << 30) -#define LTQ_ES_SW_GCTL0_REG_ICRCCD_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ICRCCD) >> 30) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_ICRCCD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ICRCCD) | (((val) & 0x1) << 30)) -/* Replace VID0 (28) */ -#define LTQ_ES_SW_GCTL0_REG_RVID0 (0x1 << 28) -#define LTQ_ES_SW_GCTL0_REG_RVID0_VAL(val) (((val) & 0x1) << 28) -#define LTQ_ES_SW_GCTL0_REG_RVID0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID0) >> 28) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_RVID0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID0) | (((val) & 0x1) << 28)) -/* Replace VID1 (27) */ -#define LTQ_ES_SW_GCTL0_REG_RVID1 (0x1 << 27) -#define LTQ_ES_SW_GCTL0_REG_RVID1_VAL(val) (((val) & 0x1) << 27) -#define LTQ_ES_SW_GCTL0_REG_RVID1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID1) >> 27) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_RVID1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID1) | (((val) & 0x1) << 27)) -/* Replace VIDFFF (26) */ -#define LTQ_ES_SW_GCTL0_REG_RVIDFFF (0x1 << 26) -#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_VAL(val) (((val) & 0x1) << 26) -#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVIDFFF) >> 26) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVIDFFF) | (((val) & 0x1) << 26)) -/* Priority Change Rule (25) */ -#define LTQ_ES_SW_GCTL0_REG_PCR (0x1 << 25) -#define LTQ_ES_SW_GCTL0_REG_PCR_VAL(val) (((val) & 0x1) << 25) -#define LTQ_ES_SW_GCTL0_REG_PCR_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCR) >> 25) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_PCR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCR) | (((val) & 0x1) << 25)) -/* Priority Change Enable (24) */ -#define LTQ_ES_SW_GCTL0_REG_PCE (0x1 << 24) -#define LTQ_ES_SW_GCTL0_REG_PCE_VAL(val) (((val) & 0x1) << 24) -#define LTQ_ES_SW_GCTL0_REG_PCE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCE) >> 24) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_PCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCE) | (((val) & 0x1) << 24)) -/* Transmit Short IPG Enable (23) */ -#define LTQ_ES_SW_GCTL0_REG_TSIPGE (0x1 << 23) -#define LTQ_ES_SW_GCTL0_REG_TSIPGE_VAL(val) (((val) & 0x1) << 23) -#define LTQ_ES_SW_GCTL0_REG_TSIPGE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_TSIPGE) >> 23) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_TSIPGE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_TSIPGE) | (((val) & 0x1) << 23)) -/* PHY Base Address (22) */ -#define LTQ_ES_SW_GCTL0_REG_PHYBA (0x1 << 22) -#define LTQ_ES_SW_GCTL0_REG_PHYBA_VAL(val) (((val) & 0x1) << 22) -#define LTQ_ES_SW_GCTL0_REG_PHYBA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PHYBA) >> 22) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_PHYBA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PHYBA) | (((val) & 0x1) << 22)) -/* Drop Packet When Excessive Collision Happen (21) */ -#define LTQ_ES_SW_GCTL0_REG_DPWECH (0x1 << 21) -#define LTQ_ES_SW_GCTL0_REG_DPWECH_VAL(val) (((val) & 0x1) << 21) -#define LTQ_ES_SW_GCTL0_REG_DPWECH_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DPWECH) >> 21) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_DPWECH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DPWECH) | (((val) & 0x1) << 21)) -/* Aging Timer Select (20:18) */ -#define LTQ_ES_SW_GCTL0_REG_ATS (0x7 << 18) -#define LTQ_ES_SW_GCTL0_REG_ATS_VAL(val) (((val) & 0x7) << 18) -#define LTQ_ES_SW_GCTL0_REG_ATS_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ATS) >> 18) & 0x7) -#define LTQ_ES_SW_GCTL0_REG_ATS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ATS) | (((val) & 0x7) << 18)) -/* Mirror CRC Also (17) */ -#define LTQ_ES_SW_GCTL0_REG_MCA (0x1 << 17) -#define LTQ_ES_SW_GCTL0_REG_MCA_VAL(val) (((val) & 0x1) << 17) -#define LTQ_ES_SW_GCTL0_REG_MCA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MCA) >> 17) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_MCA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MCA) | (((val) & 0x1) << 17)) -/* Mirror RXER Also (16) */ -#define LTQ_ES_SW_GCTL0_REG_MRA (0x1 << 16) -#define LTQ_ES_SW_GCTL0_REG_MRA_VAL(val) (((val) & 0x1) << 16) -#define LTQ_ES_SW_GCTL0_REG_MRA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MRA) >> 16) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_MRA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MRA) | (((val) & 0x1) << 16)) -/* Mirror PAUSE Also (15) */ -#define LTQ_ES_SW_GCTL0_REG_MPA (0x1 << 15) -#define LTQ_ES_SW_GCTL0_REG_MPA_VAL(val) (((val) & 0x1) << 15) -#define LTQ_ES_SW_GCTL0_REG_MPA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPA) >> 15) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_MPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPA) | (((val) & 0x1) << 15)) -/* Mirror Long Also (14) */ -#define LTQ_ES_SW_GCTL0_REG_MLA (0x1 << 14) -#define LTQ_ES_SW_GCTL0_REG_MLA_VAL(val) (((val) & 0x1) << 14) -#define LTQ_ES_SW_GCTL0_REG_MLA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MLA) >> 14) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_MLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MLA) | (((val) & 0x1) << 14)) -/* Mirror Short Also (13) */ -#define LTQ_ES_SW_GCTL0_REG_MSA (0x1 << 13) -#define LTQ_ES_SW_GCTL0_REG_MSA_VAL(val) (((val) & 0x1) << 13) -#define LTQ_ES_SW_GCTL0_REG_MSA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MSA) >> 13) & 0x1) -#define LTQ_ES_SW_GCTL0_REG_MSA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MSA) | (((val) & 0x1) << 13)) -/* Sniffer port number (12:11) */ -#define LTQ_ES_SW_GCTL0_REG_SNIFFPN (0x3 << 11) -#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(val) (((val) & 0x3) << 11) -#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SNIFFPN) >> 11) & 0x3) -#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SNIFFPN) | (((val) & 0x3) << 11)) -/* Max Packet Length (MAXPKTLEN) (9:8) */ -#define LTQ_ES_SW_GCTL0_REG_MPL (0x3 << 8) -#define LTQ_ES_SW_GCTL0_REG_MPL_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_SW_GCTL0_REG_MPL_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPL) >> 8) & 0x3) -#define LTQ_ES_SW_GCTL0_REG_MPL_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPL) | (((val) & 0x3) << 8)) -/* Discard Mode (Drop scheme for Packets Classified as Q3) (7:6) */ -#define LTQ_ES_SW_GCTL0_REG_DMQ3 (0x3 << 6) -#define LTQ_ES_SW_GCTL0_REG_DMQ3_VAL(val) (((val) & 0x3) << 6) -#define LTQ_ES_SW_GCTL0_REG_DMQ3_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ3) >> 6) & 0x3) -#define LTQ_ES_SW_GCTL0_REG_DMQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ3) | (((val) & 0x3) << 6)) -/* Discard Mode (Drop scheme for Packets Classified as Q2) (5:4) */ -#define LTQ_ES_SW_GCTL0_REG_DMQ2 (0x3 << 4) -#define LTQ_ES_SW_GCTL0_REG_DMQ2_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_SW_GCTL0_REG_DMQ2_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ2) >> 4) & 0x3) -#define LTQ_ES_SW_GCTL0_REG_DMQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ2) | (((val) & 0x3) << 4)) -/* Discard Mode (Drop scheme for Packets Classified as Q1) (3:2) */ -#define LTQ_ES_SW_GCTL0_REG_DMQ1 (0x3 << 2) -#define LTQ_ES_SW_GCTL0_REG_DMQ1_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_SW_GCTL0_REG_DMQ1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ1) >> 2) & 0x3) -#define LTQ_ES_SW_GCTL0_REG_DMQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ1) | (((val) & 0x3) << 2)) -/* Discard Mode (Drop scheme for Packets Classified as Q0) (1:0) */ -#define LTQ_ES_SW_GCTL0_REG_DMQ0 (0x3) -#define LTQ_ES_SW_GCTL0_REG_DMQ0_VAL(val) (((val) & 0x3) << 0) -#define LTQ_ES_SW_GCTL0_REG_DMQ0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ0) >> 0) & 0x3) -#define LTQ_ES_SW_GCTL0_REG_DMQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ0) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * Switch Global Control Register 1 - ******************************************************************************/ - -/* BIST Done (27) */ -#define LTQ_ES_SW_GCTL1_REG_BISTDN (0x1 << 27) -#define LTQ_ES_SW_GCTL1_REG_BISTDN_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BISTDN) >> 27) & 0x1) -/* Enable drop scheme of TX and RX (26) */ -#define LTQ_ES_SW_GCTL1_REG_EDSTX (0x1 << 26) -#define LTQ_ES_SW_GCTL1_REG_EDSTX_VAL(val) (((val) & 0x1) << 26) -#define LTQ_ES_SW_GCTL1_REG_EDSTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_EDSTX) >> 26) & 0x1) -#define LTQ_ES_SW_GCTL1_REG_EDSTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_EDSTX) | (((val) & 0x1) << 26)) -/* Congestion threshold for TX queue (25:24) */ -#define LTQ_ES_SW_GCTL1_REG_CTTX (0x3 << 24) -#define LTQ_ES_SW_GCTL1_REG_CTTX_VAL(val) (((val) & 0x3) << 24) -#define LTQ_ES_SW_GCTL1_REG_CTTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_CTTX) >> 24) & 0x3) -#define LTQ_ES_SW_GCTL1_REG_CTTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_CTTX) | (((val) & 0x3) << 24)) -/* Input Jam Threshold (23:21) */ -#define LTQ_ES_SW_GCTL1_REG_IJT (0x7 << 21) -#define LTQ_ES_SW_GCTL1_REG_IJT_VAL(val) (((val) & 0x7) << 21) -#define LTQ_ES_SW_GCTL1_REG_IJT_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_IJT) >> 21) & 0x7) -#define LTQ_ES_SW_GCTL1_REG_IJT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_IJT) | (((val) & 0x7) << 21)) -/* Do not Identify VLAN after SNAP (20) */ -#define LTQ_ES_SW_GCTL1_REG_DIVS (0x1 << 20) -#define LTQ_ES_SW_GCTL1_REG_DIVS_VAL(val) (((val) & 0x1) << 20) -#define LTQ_ES_SW_GCTL1_REG_DIVS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIVS) >> 20) & 0x1) -#define LTQ_ES_SW_GCTL1_REG_DIVS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIVS) | (((val) & 0x1) << 20)) -/* Do not Identify IPV6 in PPPOE (19) */ -#define LTQ_ES_SW_GCTL1_REG_DII6P (0x1 << 19) -#define LTQ_ES_SW_GCTL1_REG_DII6P_VAL(val) (((val) & 0x1) << 19) -#define LTQ_ES_SW_GCTL1_REG_DII6P_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DII6P) >> 19) & 0x1) -#define LTQ_ES_SW_GCTL1_REG_DII6P_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DII6P) | (((val) & 0x1) << 19)) -/* Do not Identify IP in PPPOE after SNAP (18) */ -#define LTQ_ES_SW_GCTL1_REG_DIIPS (0x1 << 18) -#define LTQ_ES_SW_GCTL1_REG_DIIPS_VAL(val) (((val) & 0x1) << 18) -#define LTQ_ES_SW_GCTL1_REG_DIIPS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIPS) >> 18) & 0x1) -#define LTQ_ES_SW_GCTL1_REG_DIIPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIPS) | (((val) & 0x1) << 18)) -/* Do not Identify Ether-Type = 0x0800, IP VER = 6 as IPV6 packets (17) */ -#define LTQ_ES_SW_GCTL1_REG_DIE (0x1 << 17) -#define LTQ_ES_SW_GCTL1_REG_DIE_VAL(val) (((val) & 0x1) << 17) -#define LTQ_ES_SW_GCTL1_REG_DIE_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIE) >> 17) & 0x1) -#define LTQ_ES_SW_GCTL1_REG_DIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIE) | (((val) & 0x1) << 17)) -/* Do not Identify IP in PPPOE (16) */ -#define LTQ_ES_SW_GCTL1_REG_DIIP (0x1 << 16) -#define LTQ_ES_SW_GCTL1_REG_DIIP_VAL(val) (((val) & 0x1) << 16) -#define LTQ_ES_SW_GCTL1_REG_DIIP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIP) >> 16) & 0x1) -#define LTQ_ES_SW_GCTL1_REG_DIIP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIP) | (((val) & 0x1) << 16)) -/* Do not Identify SNAP (15) */ -#define LTQ_ES_SW_GCTL1_REG_DIS (0x1 << 15) -#define LTQ_ES_SW_GCTL1_REG_DIS_VAL(val) (((val) & 0x1) << 15) -#define LTQ_ES_SW_GCTL1_REG_DIS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIS) >> 15) & 0x1) -#define LTQ_ES_SW_GCTL1_REG_DIS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIS) | (((val) & 0x1) << 15)) -/* Unicast Portmap (14:12) */ -#define LTQ_ES_SW_GCTL1_REG_UP (0x7 << 12) -#define LTQ_ES_SW_GCTL1_REG_UP_VAL(val) (((val) & 0x7) << 12) -#define LTQ_ES_SW_GCTL1_REG_UP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_UP) >> 12) & 0x7) -#define LTQ_ES_SW_GCTL1_REG_UP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_UP) | (((val) & 0x7) << 12)) -/* Broadcast Portmap (10:8) */ -#define LTQ_ES_SW_GCTL1_REG_BP (0x7 << 8) -#define LTQ_ES_SW_GCTL1_REG_BP_VAL(val) (((val) & 0x7) << 8) -#define LTQ_ES_SW_GCTL1_REG_BP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BP) >> 8) & 0x7) -#define LTQ_ES_SW_GCTL1_REG_BP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_BP) | (((val) & 0x7) << 8)) -/* Multicast Portmap (6:4) */ -#define LTQ_ES_SW_GCTL1_REG_MP (0x7 << 4) -#define LTQ_ES_SW_GCTL1_REG_MP_VAL(val) (((val) & 0x7) << 4) -#define LTQ_ES_SW_GCTL1_REG_MP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_MP) >> 4) & 0x7) -#define LTQ_ES_SW_GCTL1_REG_MP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_MP) | (((val) & 0x7) << 4)) -/* Reserve Portmap (2:0) */ -#define LTQ_ES_SW_GCTL1_REG_RP (0x7) -#define LTQ_ES_SW_GCTL1_REG_RP_VAL(val) (((val) & 0x7) << 0) -#define LTQ_ES_SW_GCTL1_REG_RP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_RP) >> 0) & 0x7) -#define LTQ_ES_SW_GCTL1_REG_RP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_RP) | (((val) & 0x7) << 0)) - -/******************************************************************************* - * ARP/RARP Register - ******************************************************************************/ - -/* MAC Control Action (15:14) */ -#define LTQ_ES_ARP_REG_MACA (0x3 << 14) -#define LTQ_ES_ARP_REG_MACA_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_ARP_REG_MACA_GET(val) ((((val) & LTQ_ES_ARP_REG_MACA) >> 14) & 0x3) -#define LTQ_ES_ARP_REG_MACA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_MACA) | (((val) & 0x3) << 14)) -/* Unicast packet Treated as Cross_VLAN packet (13) */ -#define LTQ_ES_ARP_REG_UPT (0x1 << 13) -#define LTQ_ES_ARP_REG_UPT_VAL(val) (((val) & 0x1) << 13) -#define LTQ_ES_ARP_REG_UPT_GET(val) ((((val) & LTQ_ES_ARP_REG_UPT) >> 13) & 0x1) -#define LTQ_ES_ARP_REG_UPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_UPT) | (((val) & 0x1) << 13)) -/* RARP Packet Treated as Cross_VLAN Packet (12) */ -#define LTQ_ES_ARP_REG_RPT (0x1 << 12) -#define LTQ_ES_ARP_REG_RPT_VAL(val) (((val) & 0x1) << 12) -#define LTQ_ES_ARP_REG_RPT_GET(val) ((((val) & LTQ_ES_ARP_REG_RPT) >> 12) & 0x1) -#define LTQ_ES_ARP_REG_RPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RPT) | (((val) & 0x1) << 12)) -/* RARP/ARP Packet Action (11:10) */ -#define LTQ_ES_ARP_REG_RAPA (0x3 << 10) -#define LTQ_ES_ARP_REG_RAPA_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_ARP_REG_RAPA_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPA) >> 10) & 0x3) -#define LTQ_ES_ARP_REG_RAPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPA) | (((val) & 0x3) << 10)) -/* RARP/ARP Packet Priority Enable (9) */ -#define LTQ_ES_ARP_REG_RAPPE (0x1 << 9) -#define LTQ_ES_ARP_REG_RAPPE_VAL(val) (((val) & 0x1) << 9) -#define LTQ_ES_ARP_REG_RAPPE_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPPE) >> 9) & 0x1) -#define LTQ_ES_ARP_REG_RAPPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPPE) | (((val) & 0x1) << 9)) -/* RARP/ARP Packet Priority (8:7) */ -#define LTQ_ES_ARP_REG_RAPP (0x3 << 7) -#define LTQ_ES_ARP_REG_RAPP_VAL(val) (((val) & 0x3) << 7) -#define LTQ_ES_ARP_REG_RAPP_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPP) >> 7) & 0x3) -#define LTQ_ES_ARP_REG_RAPP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPP) | (((val) & 0x3) << 7)) -/* RARP/ARP Packet Output Tag Handle (6:5) */ -#define LTQ_ES_ARP_REG_RAPOTH (0x3 << 5) -#define LTQ_ES_ARP_REG_RAPOTH_VAL(val) (((val) & 0x3) << 5) -#define LTQ_ES_ARP_REG_RAPOTH_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPOTH) >> 5) & 0x3) -#define LTQ_ES_ARP_REG_RAPOTH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPOTH) | (((val) & 0x3) << 5)) -/* ARP Packet Treated as Cross _ VLAN Packet (4) */ -#define LTQ_ES_ARP_REG_APT (0x1 << 4) -#define LTQ_ES_ARP_REG_APT_VAL(val) (((val) & 0x1) << 4) -#define LTQ_ES_ARP_REG_APT_GET(val) ((((val) & LTQ_ES_ARP_REG_APT) >> 4) & 0x1) -#define LTQ_ES_ARP_REG_APT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_APT) | (((val) & 0x1) << 4)) -/* RARP/ARP Packet Treated as Management Packet (3) */ -#define LTQ_ES_ARP_REG_RAPTM (0x1 << 3) -#define LTQ_ES_ARP_REG_RAPTM_VAL(val) (((val) & 0x1) << 3) -#define LTQ_ES_ARP_REG_RAPTM_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPTM) >> 3) & 0x1) -#define LTQ_ES_ARP_REG_RAPTM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPTM) | (((val) & 0x1) << 3)) -/* RARP/ARP Packet Treated as Span Packet (2) */ -#define LTQ_ES_ARP_REG_TAPTS (0x1 << 2) -#define LTQ_ES_ARP_REG_TAPTS_VAL(val) (((val) & 0x1) << 2) -#define LTQ_ES_ARP_REG_TAPTS_GET(val) ((((val) & LTQ_ES_ARP_REG_TAPTS) >> 2) & 0x1) -#define LTQ_ES_ARP_REG_TAPTS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAPTS) | (((val) & 0x1) << 2)) -/* Trap ARP Packet (1) */ -#define LTQ_ES_ARP_REG_TAP (0x1 << 1) -#define LTQ_ES_ARP_REG_TAP_VAL(val) (((val) & 0x1) << 1) -#define LTQ_ES_ARP_REG_TAP_GET(val) ((((val) & LTQ_ES_ARP_REG_TAP) >> 1) & 0x1) -#define LTQ_ES_ARP_REG_TAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAP) | (((val) & 0x1) << 1)) -/* Trap RARP Packet (0) */ -#define LTQ_ES_ARP_REG_TRP (0x1) -#define LTQ_ES_ARP_REG_TRP_VAL(val) (((val) & 0x1) << 0) -#define LTQ_ES_ARP_REG_TRP_GET(val) ((((val) & LTQ_ES_ARP_REG_TRP) >> 0) & 0x1) -#define LTQ_ES_ARP_REG_TRP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TRP) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Storm control Register - ******************************************************************************/ - -/* Reserved (31:29) */ -#define LTQ_ES_STRM_CTL_REG_RES (0x7 << 29) -#define LTQ_ES_STRM_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_RES) >> 29) & 0x7) -/* 10M Threshold (28:16) */ -#define LTQ_ES_STRM_CTL_REG_STORM_10_TH (0x1fff << 16) -#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_VAL(val) (((val) & 0x1fff) << 16) -#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_10_TH) >> 16) & 0x1fff) -#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_10_TH) | (((val) & 0x1fff) << 16)) -/* Storm Enable for Broadcast Packets (15) */ -#define LTQ_ES_STRM_CTL_REG_STORM_B (0x1 << 15) -#define LTQ_ES_STRM_CTL_REG_STORM_B_VAL(val) (((val) & 0x1) << 15) -#define LTQ_ES_STRM_CTL_REG_STORM_B_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_B) >> 15) & 0x1) -#define LTQ_ES_STRM_CTL_REG_STORM_B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_B) | (((val) & 0x1) << 15)) -/* Storm Enable for Multicast Packets (14) */ -#define LTQ_ES_STRM_CTL_REG_STORM_M (0x1 << 14) -#define LTQ_ES_STRM_CTL_REG_STORM_M_VAL(val) (((val) & 0x1) << 14) -#define LTQ_ES_STRM_CTL_REG_STORM_M_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_M) >> 14) & 0x1) -#define LTQ_ES_STRM_CTL_REG_STORM_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_M) | (((val) & 0x1) << 14)) -/* Storm Enable for Un-learned Unicast Packets (13) */ -#define LTQ_ES_STRM_CTL_REG_STORM_U (0x1 << 13) -#define LTQ_ES_STRM_CTL_REG_STORM_U_VAL(val) (((val) & 0x1) << 13) -#define LTQ_ES_STRM_CTL_REG_STORM_U_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_U) >> 13) & 0x1) -#define LTQ_ES_STRM_CTL_REG_STORM_U_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_U) | (((val) & 0x1) << 13)) -/* 100M Threshold (12:0) */ -#define LTQ_ES_STRM_CTL_REG_STORM_100_TH (0x1fff) -#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_VAL(val) (((val) & 0x1fff) << 0) -#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_100_TH) >> 0) & 0x1fff) -#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_100_TH) | (((val) & 0x1fff) << 0)) - -/******************************************************************************* - * RGMII/GMII Port Control Register - ******************************************************************************/ - -/* Management Clock Select (31:24) */ -#define LTQ_ES_RGMII_CTL_REG_MCS (0xff << 24) -#define LTQ_ES_RGMII_CTL_REG_MCS_VAL(val) (((val) & 0xff) << 24) -#define LTQ_ES_RGMII_CTL_REG_MCS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_MCS) >> 24) & 0xff) -#define LTQ_ES_RGMII_CTL_REG_MCS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_MCS) | (((val) & 0xff) << 24)) -/* Interface Selection (19:18) */ -#define LTQ_ES_RGMII_CTL_REG_IS (0x3 << 18) -#define LTQ_ES_RGMII_CTL_REG_IS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_IS) >> 18) & 0x3) -/* Port 1 RGMII Rx Clock Delay (17:16) */ -#define LTQ_ES_RGMII_CTL_REG_P1RDLY (0x3 << 16) -#define LTQ_ES_RGMII_CTL_REG_P1RDLY_VAL(val) (((val) & 0x3) << 16) -#define LTQ_ES_RGMII_CTL_REG_P1RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1RDLY) >> 16) & 0x3) -#define LTQ_ES_RGMII_CTL_REG_P1RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1RDLY) | (((val) & 0x3) << 16)) -/* Port 1 RGMII Tx Clock Delay (15:14) */ -#define LTQ_ES_RGMII_CTL_REG_P1TDLY (0x3 << 14) -#define LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_RGMII_CTL_REG_P1TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1TDLY) >> 14) & 0x3) -#define LTQ_ES_RGMII_CTL_REG_P1TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1TDLY) | (((val) & 0x3) << 14)) -/* Port 1 Speed (13:12) */ -#define LTQ_ES_RGMII_CTL_REG_P1SPD (0x3 << 12) -#define LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(val) (((val) & 0x3) << 12) -#define LTQ_ES_RGMII_CTL_REG_P1SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1SPD) >> 12) & 0x3) -#define LTQ_ES_RGMII_CTL_REG_P1SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1SPD) | (((val) & 0x3) << 12)) -/* Port 1 Duplex mode (11) */ -#define LTQ_ES_RGMII_CTL_REG_P1DUP (0x1 << 11) -#define LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(val) (((val) & 0x1) << 11) -#define LTQ_ES_RGMII_CTL_REG_P1DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1DUP) >> 11) & 0x1) -#define LTQ_ES_RGMII_CTL_REG_P1DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1DUP) | (((val) & 0x1) << 11)) -/* Port 1 Flow Control Enable (10) */ -#define LTQ_ES_RGMII_CTL_REG_P1FCE (0x1 << 10) -#define LTQ_ES_RGMII_CTL_REG_P1FCE_VAL(val) (((val) & 0x1) << 10) -#define LTQ_ES_RGMII_CTL_REG_P1FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1FCE) >> 10) & 0x1) -#define LTQ_ES_RGMII_CTL_REG_P1FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1FCE) | (((val) & 0x1) << 10)) -/* Port 0 RGMII Rx Clock Delay (7:6) */ -#define LTQ_ES_RGMII_CTL_REG_P0RDLY (0x3 << 6) -#define LTQ_ES_RGMII_CTL_REG_P0RDLY_VAL(val) (((val) & 0x3) << 6) -#define LTQ_ES_RGMII_CTL_REG_P0RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0RDLY) >> 6) & 0x3) -#define LTQ_ES_RGMII_CTL_REG_P0RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0RDLY) | (((val) & 0x3) << 6)) -/* Port 0 RGMII Tx Clock Delay (5:4) */ -#define LTQ_ES_RGMII_CTL_REG_P0TDLY (0x3 << 4) -#define LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_RGMII_CTL_REG_P0TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0TDLY) >> 4) & 0x3) -#define LTQ_ES_RGMII_CTL_REG_P0TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0TDLY) | (((val) & 0x3) << 4)) -/* Port 0 Speed (3:2) */ -#define LTQ_ES_RGMII_CTL_REG_P0SPD (0x3 << 2) -#define LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_RGMII_CTL_REG_P0SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0SPD) >> 2) & 0x3) -#define LTQ_ES_RGMII_CTL_REG_P0SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0SPD) | (((val) & 0x3) << 2)) -/* Port 0 Duplex mode (1) */ -#define LTQ_ES_RGMII_CTL_REG_P0DUP (0x1 << 1) -#define LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(val) (((val) & 0x1) << 1) -#define LTQ_ES_RGMII_CTL_REG_P0DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0DUP) >> 1) & 0x1) -#define LTQ_ES_RGMII_CTL_REG_P0DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0DUP) | (((val) & 0x1) << 1)) -/* Port 0 Flow Control Enable (0) */ -#define LTQ_ES_RGMII_CTL_REG_P0FCE (0x1) -#define LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(val) (((val) & 0x1) << 0) -#define LTQ_ES_RGMII_CTL_REG_P0FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0FCE) >> 0) & 0x1) -#define LTQ_ES_RGMII_CTL_REG_P0FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0FCE) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * 802.1p Priority Map Register - ******************************************************************************/ - -/* Priority Queue 7 (15:14) */ -#define LTQ_ES_PRT_1P_REG_1PPQ7 (0x3 << 14) -#define LTQ_ES_PRT_1P_REG_1PPQ7_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_PRT_1P_REG_1PPQ7_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ7) >> 14) & 0x3) -#define LTQ_ES_PRT_1P_REG_1PPQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ7) | (((val) & 0x3) << 14)) -/* Priority Queue 6 (13:12) */ -#define LTQ_ES_PRT_1P_REG_1PPQ6 (0x3 << 12) -#define LTQ_ES_PRT_1P_REG_1PPQ6_VAL(val) (((val) & 0x3) << 12) -#define LTQ_ES_PRT_1P_REG_1PPQ6_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ6) >> 12) & 0x3) -#define LTQ_ES_PRT_1P_REG_1PPQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ6) | (((val) & 0x3) << 12)) -/* Priority Queue 5 (11:10) */ -#define LTQ_ES_PRT_1P_REG_1PPQ5 (0x3 << 10) -#define LTQ_ES_PRT_1P_REG_1PPQ5_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_PRT_1P_REG_1PPQ5_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ5) >> 10) & 0x3) -#define LTQ_ES_PRT_1P_REG_1PPQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ5) | (((val) & 0x3) << 10)) -/* Priority Queue 4 (9:8) */ -#define LTQ_ES_PRT_1P_REG_1PPQ4 (0x3 << 8) -#define LTQ_ES_PRT_1P_REG_1PPQ4_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_PRT_1P_REG_1PPQ4_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ4) >> 8) & 0x3) -#define LTQ_ES_PRT_1P_REG_1PPQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ4) | (((val) & 0x3) << 8)) -/* Priority Queue 3 (7:6) */ -#define LTQ_ES_PRT_1P_REG_1PPQ3 (0x3 << 6) -#define LTQ_ES_PRT_1P_REG_1PPQ3_VAL(val) (((val) & 0x3) << 6) -#define LTQ_ES_PRT_1P_REG_1PPQ3_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ3) >> 6) & 0x3) -#define LTQ_ES_PRT_1P_REG_1PPQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ3) | (((val) & 0x3) << 6)) -/* Priority Queue 2 (5:4) */ -#define LTQ_ES_PRT_1P_REG_1PPQ2 (0x3 << 4) -#define LTQ_ES_PRT_1P_REG_1PPQ2_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_PRT_1P_REG_1PPQ2_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ2) >> 4) & 0x3) -#define LTQ_ES_PRT_1P_REG_1PPQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ2) | (((val) & 0x3) << 4)) -/* Priority Queue 1 (3:2) */ -#define LTQ_ES_PRT_1P_REG_1PPQ1 (0x3 << 2) -#define LTQ_ES_PRT_1P_REG_1PPQ1_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_PRT_1P_REG_1PPQ1_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ1) >> 2) & 0x3) -#define LTQ_ES_PRT_1P_REG_1PPQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ1) | (((val) & 0x3) << 2)) -/* Priority Queue 0 (1:0) */ -#define LTQ_ES_PRT_1P_REG_1PPQ0 (0x3) -#define LTQ_ES_PRT_1P_REG_1PPQ0_VAL(val) (((val) & 0x3) << 0) -#define LTQ_ES_PRT_1P_REG_1PPQ0_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ0) >> 0) & 0x3) -#define LTQ_ES_PRT_1P_REG_1PPQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ0) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * Global Bucket Size Base counter - ******************************************************************************/ - -/* Reserved (31:18) */ -#define LTQ_ES_GBKT_SZBS_REG_REV (0x3fff << 18) -#define LTQ_ES_GBKT_SZBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_REV) >> 18) & 0x3fff) -/* Base[17:0] (17:0) */ -#define LTQ_ES_GBKT_SZBS_REG_BASE17_0 (0x3ffff) -#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_VAL(val) (((val) & 0x3ffff) << 0) -#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_BASE17_0) >> 0) & 0x3ffff) -#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZBS_REG_BASE17_0) | (((val) & 0x3ffff) << 0)) - -/******************************************************************************* - * Global Bucket Size Extend Base Counter - ******************************************************************************/ - -/* Reserved (31:18) */ -#define LTQ_ES_GBKT_SZEBS_REG_REV (0x3fff << 18) -#define LTQ_ES_GBKT_SZEBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_REV) >> 18) & 0x3fff) -/* Extend Base[17:0] (17:0) */ -#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0 (0x3ffff) -#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_VAL(val) (((val) & 0x3ffff) << 0) -#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) >> 0) & 0x3ffff) -#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) | (((val) & 0x3ffff) << 0)) - -/******************************************************************************* - * Buffer Threshold Register - ******************************************************************************/ - -/* Port Unfull Offset 3 (31:30) */ -#define LTQ_ES_BF_TH_REG_PUO3 (0x3 << 30) -#define LTQ_ES_BF_TH_REG_PUO3_VAL(val) (((val) & 0x3) << 30) -#define LTQ_ES_BF_TH_REG_PUO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO3) >> 30) & 0x3) -#define LTQ_ES_BF_TH_REG_PUO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO3) | (((val) & 0x3) << 30)) -/* Port Unfull Offset 2 (29:28) */ -#define LTQ_ES_BF_TH_REG_PUO2 (0x3 << 28) -#define LTQ_ES_BF_TH_REG_PUO2_VAL(val) (((val) & 0x3) << 28) -#define LTQ_ES_BF_TH_REG_PUO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO2) >> 28) & 0x3) -#define LTQ_ES_BF_TH_REG_PUO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO2) | (((val) & 0x3) << 28)) -/* Port Unfull Offset 1 (27:26) */ -#define LTQ_ES_BF_TH_REG_PUO1 (0x3 << 26) -#define LTQ_ES_BF_TH_REG_PUO1_VAL(val) (((val) & 0x3) << 26) -#define LTQ_ES_BF_TH_REG_PUO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO1) >> 26) & 0x3) -#define LTQ_ES_BF_TH_REG_PUO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO1) | (((val) & 0x3) << 26)) -/* Port Unfull Offset 0 (25:24) */ -#define LTQ_ES_BF_TH_REG_PUO0 (0x3 << 24) -#define LTQ_ES_BF_TH_REG_PUO0_VAL(val) (((val) & 0x3) << 24) -#define LTQ_ES_BF_TH_REG_PUO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO0) >> 24) & 0x3) -#define LTQ_ES_BF_TH_REG_PUO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO0) | (((val) & 0x3) << 24)) -/* Port Full Offset 3 (23:22) */ -#define LTQ_ES_BF_TH_REG_PFO3 (0x3 << 22) -#define LTQ_ES_BF_TH_REG_PFO3_VAL(val) (((val) & 0x3) << 22) -#define LTQ_ES_BF_TH_REG_PFO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO3) >> 22) & 0x3) -#define LTQ_ES_BF_TH_REG_PFO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO3) | (((val) & 0x3) << 22)) -/* Port Full Offset 2 (21:20) */ -#define LTQ_ES_BF_TH_REG_PFO2 (0x3 << 20) -#define LTQ_ES_BF_TH_REG_PFO2_VAL(val) (((val) & 0x3) << 20) -#define LTQ_ES_BF_TH_REG_PFO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO2) >> 20) & 0x3) -#define LTQ_ES_BF_TH_REG_PFO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO2) | (((val) & 0x3) << 20)) -/* Port Full Offset 1 (19:18) */ -#define LTQ_ES_BF_TH_REG_PFO1 (0x3 << 18) -#define LTQ_ES_BF_TH_REG_PFO1_VAL(val) (((val) & 0x3) << 18) -#define LTQ_ES_BF_TH_REG_PFO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO1) >> 18) & 0x3) -#define LTQ_ES_BF_TH_REG_PFO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO1) | (((val) & 0x3) << 18)) -/* Port Full Offset 0 (17:16) */ -#define LTQ_ES_BF_TH_REG_PFO0 (0x3 << 16) -#define LTQ_ES_BF_TH_REG_PFO0_VAL(val) (((val) & 0x3) << 16) -#define LTQ_ES_BF_TH_REG_PFO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO0) >> 16) & 0x3) -#define LTQ_ES_BF_TH_REG_PFO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO0) | (((val) & 0x3) << 16)) -/* Reserved (15:14) */ -#define LTQ_ES_BF_TH_REG_RES (0x3 << 14) -#define LTQ_ES_BF_TH_REG_RES_GET(val) ((((val) & LTQ_ES_BF_TH_REG_RES) >> 14) & 0x3) -/* Total Low Add (13) */ -#define LTQ_ES_BF_TH_REG_TLA (0x1 << 13) -#define LTQ_ES_BF_TH_REG_TLA_VAL(val) (((val) & 0x1) << 13) -#define LTQ_ES_BF_TH_REG_TLA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLA) >> 13) & 0x1) -#define LTQ_ES_BF_TH_REG_TLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLA) | (((val) & 0x1) << 13)) -/* Total High Add (12) */ -#define LTQ_ES_BF_TH_REG_THA (0x1 << 12) -#define LTQ_ES_BF_TH_REG_THA_VAL(val) (((val) & 0x1) << 12) -#define LTQ_ES_BF_TH_REG_THA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THA) >> 12) & 0x1) -#define LTQ_ES_BF_TH_REG_THA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THA) | (((val) & 0x1) << 12)) -/* Total Low Offset (11:10) */ -#define LTQ_ES_BF_TH_REG_TLO (0x3 << 10) -#define LTQ_ES_BF_TH_REG_TLO_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_BF_TH_REG_TLO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLO) >> 10) & 0x3) -#define LTQ_ES_BF_TH_REG_TLO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLO) | (((val) & 0x3) << 10)) -/* Total High Offset (9:8) */ -#define LTQ_ES_BF_TH_REG_THO (0x3 << 8) -#define LTQ_ES_BF_TH_REG_THO_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_BF_TH_REG_THO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THO) >> 8) & 0x3) -#define LTQ_ES_BF_TH_REG_THO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THO) | (((val) & 0x3) << 8)) -/* Port Unfull Add (7:4) */ -#define LTQ_ES_BF_TH_REG_PUA (0xf << 4) -#define LTQ_ES_BF_TH_REG_PUA_VAL(val) (((val) & 0xf) << 4) -#define LTQ_ES_BF_TH_REG_PUA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUA) >> 4) & 0xf) -#define LTQ_ES_BF_TH_REG_PUA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUA) | (((val) & 0xf) << 4)) -/* Port Full Add (3:0) */ -#define LTQ_ES_BF_TH_REG_PFA (0xf) -#define LTQ_ES_BF_TH_REG_PFA_VAL(val) (((val) & 0xf) << 0) -#define LTQ_ES_BF_TH_REG_PFA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFA) >> 0) & 0xf) -#define LTQ_ES_BF_TH_REG_PFA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFA) | (((val) & 0xf) << 0)) - -/******************************************************************************* - * PMAC Header Control Register - ******************************************************************************/ - -/* Reserved (31:22) */ -#define LTQ_ES_PMAC_HD_CTL_RES (0x3ff << 22) -#define LTQ_ES_PMAC_HD_CTL_RES_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RES) >> 22) & 0x3ff) -/* Remove Layer-2 Header from Packets Going from PMAC to DMA (21) */ -#define LTQ_ES_PMAC_HD_CTL_RL2 (0x1 << 21) -#define LTQ_ES_PMAC_HD_CTL_RL2_VAL(val) (((val) & 0x1) << 21) -#define LTQ_ES_PMAC_HD_CTL_RL2_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RL2) >> 21) & 0x1) -#define LTQ_ES_PMAC_HD_CTL_RL2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RL2) | (((val) & 0x1) << 21)) -/* Remove CRC from Packets Going from PMAC to DMA (20) */ -#define LTQ_ES_PMAC_HD_CTL_RC (0x1 << 20) -#define LTQ_ES_PMAC_HD_CTL_RC_VAL(val) (((val) & 0x1) << 20) -#define LTQ_ES_PMAC_HD_CTL_RC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RC) >> 20) & 0x1) -#define LTQ_ES_PMAC_HD_CTL_RC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RC) | (((val) & 0x1) << 20)) -/* Status Header for Packets from PMAC to DMA (19) */ -#define LTQ_ES_PMAC_HD_CTL_AS (0x1 << 19) -#define LTQ_ES_PMAC_HD_CTL_AS_VAL(val) (((val) & 0x1) << 19) -#define LTQ_ES_PMAC_HD_CTL_AS_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AS) >> 19) & 0x1) -#define LTQ_ES_PMAC_HD_CTL_AS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AS) | (((val) & 0x1) << 19)) -/* Add CRC for packets from DMA to PMAC (18) */ -#define LTQ_ES_PMAC_HD_CTL_AC (0x1 << 18) -#define LTQ_ES_PMAC_HD_CTL_AC_VAL(val) (((val) & 0x1) << 18) -#define LTQ_ES_PMAC_HD_CTL_AC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AC) >> 18) & 0x1) -#define LTQ_ES_PMAC_HD_CTL_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AC) | (((val) & 0x1) << 18)) -/* Contains the length/type value to the added to packets from DMA to PMAC (17:2) */ -#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN (0xffff << 2) -#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_VAL(val) (((val) & 0xffff) << 2) -#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TYPE_LEN) >> 2) & 0xffff) -#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TYPE_LEN) | (((val) & 0xffff) << 2)) -/* Add TAG to Packets from DMA to PMAC (1) */ -#define LTQ_ES_PMAC_HD_CTL_TAG (0x1 << 1) -#define LTQ_ES_PMAC_HD_CTL_TAG_VAL(val) (((val) & 0x1) << 1) -#define LTQ_ES_PMAC_HD_CTL_TAG_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TAG) >> 1) & 0x1) -#define LTQ_ES_PMAC_HD_CTL_TAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TAG) | (((val) & 0x1) << 1)) -/* ADD Header to Packets from DMA to PMAC (0) */ -#define LTQ_ES_PMAC_HD_CTL_ADD (0x1) -#define LTQ_ES_PMAC_HD_CTL_ADD_VAL(val) (((val) & 0x1) << 0) -#define LTQ_ES_PMAC_HD_CTL_ADD_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_ADD) >> 0) & 0x1) -#define LTQ_ES_PMAC_HD_CTL_ADD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_ADD) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * PMAC Source Address Register 1 - ******************************************************************************/ - -/* Source Address to be inserted as a part of the Ethernet header. (15:0) */ -#define LTQ_ES_PMAC_SA1_SA_47_32 (0xffff) -#define LTQ_ES_PMAC_SA1_SA_47_32_VAL(val) (((val) & 0xffff) << 0) -#define LTQ_ES_PMAC_SA1_SA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_SA1_SA_47_32) >> 0) & 0xffff) -#define LTQ_ES_PMAC_SA1_SA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA1_SA_47_32) | (((val) & 0xffff) << 0)) - -/******************************************************************************* - * PMAC Source Address Register 2 - ******************************************************************************/ - -/* Source Address (31:0) */ -#define LTQ_ES_PMAC_SA2_SA_31_0 (0xFFFFFFFFL) -#define LTQ_ES_PMAC_SA2_SA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) -#define LTQ_ES_PMAC_SA2_SA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_SA2_SA_31_0) >> 0) & 0xFFFFFFFFL) -#define LTQ_ES_PMAC_SA2_SA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA2_SA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) - -/******************************************************************************* - * PMAC Destination Address Register 1 - ******************************************************************************/ - -/* Destination Address (15:0) */ -#define LTQ_ES_PMAC_DA1_DA_47_32 (0xffff) -#define LTQ_ES_PMAC_DA1_DA_47_32_VAL(val) (((val) & 0xffff) << 0) -#define LTQ_ES_PMAC_DA1_DA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_DA1_DA_47_32) >> 0) & 0xffff) -#define LTQ_ES_PMAC_DA1_DA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA1_DA_47_32) | (((val) & 0xffff) << 0)) - -/******************************************************************************* - * PMAC Destination Address Register 2 - ******************************************************************************/ - -/* Destination Address to be inserted as a part of the Ethernet header. (31:0) */ -#define LTQ_ES_PMAC_DA2_DA_31_0 (0xFFFFFFFFL) -#define LTQ_ES_PMAC_DA2_DA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) -#define LTQ_ES_PMAC_DA2_DA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_DA2_DA_31_0) >> 0) & 0xFFFFFFFFL) -#define LTQ_ES_PMAC_DA2_DA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA2_DA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) - -/******************************************************************************* - * PMAC VLAN Register - ******************************************************************************/ - -/* Priority to be inserted as a part of VLAN tag (15:13) */ -#define LTQ_ES_PMAC_VLAN_PRI (0x7 << 13) -#define LTQ_ES_PMAC_VLAN_PRI_VAL(val) (((val) & 0x7) << 13) -#define LTQ_ES_PMAC_VLAN_PRI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_PRI) >> 13) & 0x7) -#define LTQ_ES_PMAC_VLAN_PRI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_PRI) | (((val) & 0x7) << 13)) -/* CFI bit to be inserted as a part of VLAN tag (12) */ -#define LTQ_ES_PMAC_VLAN_CFI (0x1 << 12) -#define LTQ_ES_PMAC_VLAN_CFI_VAL(val) (((val) & 0x1) << 12) -#define LTQ_ES_PMAC_VLAN_CFI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_CFI) >> 12) & 0x1) -#define LTQ_ES_PMAC_VLAN_CFI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_CFI) | (((val) & 0x1) << 12)) -/* VLAN ID to be inserted as a part of VLAN tag (11:0) */ -#define LTQ_ES_PMAC_VLAN_VLAN_ID (0xfff) -#define LTQ_ES_PMAC_VLAN_VLAN_ID_VAL(val) (((val) & 0xfff) << 0) -#define LTQ_ES_PMAC_VLAN_VLAN_ID_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_VLAN_ID) >> 0) & 0xfff) -#define LTQ_ES_PMAC_VLAN_VLAN_ID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_VLAN ID) | (((val) & 0xfff) << 0)) - -/******************************************************************************* - * PMAC TX IPG Counter Register - ******************************************************************************/ - -/* IPG Counter (7:0) */ -#define LTQ_ES_PMAC_TX_IPG_IPG_CNT (0xff) -#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) -#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_TX_IPG_IPG_CNT) >> 0) & 0xff) -#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_TX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) - -/******************************************************************************* - * PMAC RX IPG Counter Register - ******************************************************************************/ - -/* IPG Counter (7:0) */ -#define LTQ_ES_PMAC_RX_IPG_IPG_CNT (0xff) -#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) -#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_RX_IPG_IPG_CNT) >> 0) & 0xff) -#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_RX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) - -/******************************************************************************* - * Address Table Control 0 Register - ******************************************************************************/ - -/* Address [31:0] (31:0) */ -#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0 (0xFFFFFFFFL) -#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) -#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) >> 0) & 0xFFFFFFFFL) -#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) | (((val) & 0xFFFFFFFFL) << 0)) - -/******************************************************************************* - * Address Table Control 1 Register - ******************************************************************************/ - -/* Port Map (22:20) */ -#define LTQ_ES_ADR_TB_CTL1_REG_PMAP (0x7 << 20) -#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(val) (((val) & 0x7) << 20) -#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_PMAP) >> 20) & 0x7) -#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_PMAP) | (((val) & 0x7) << 20)) -/* FID group (17:16) */ -#define LTQ_ES_ADR_TB_CTL1_REG_FID (0x3 << 16) -#define LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(val) (((val) & 0x3) << 16) -#define LTQ_ES_ADR_TB_CTL1_REG_FID_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_FID) >> 16) & 0x3) -#define LTQ_ES_ADR_TB_CTL1_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_FID) | (((val) & 0x3) << 16)) -/* Address [47:32] (15:0) */ -#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32 (0xffff) -#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_VAL(val) (((val) & 0xffff) << 0) -#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) >> 0) & 0xffff) -#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) | (((val) & 0xffff) << 0)) - -/******************************************************************************* - * Address Table Control 2 Register - ******************************************************************************/ - -/* Command (22:20) */ -#define LTQ_ES_ADR_TB_CTL2_REG_CMD (0x7 << 20) -#define LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(val) (((val) & 0x7) << 20) -#define LTQ_ES_ADR_TB_CTL2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_CMD) >> 20) & 0x7) -#define LTQ_ES_ADR_TB_CTL2_REG_CMD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_CMD) | (((val) & 0x7) << 20)) -/* Access Control (19:16) */ -#define LTQ_ES_ADR_TB_CTL2_REG_AC (0xf << 16) -#define LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(val) (((val) & 0xf) << 16) -#define LTQ_ES_ADR_TB_CTL2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_AC) >> 16) & 0xf) -#define LTQ_ES_ADR_TB_CTL2_REG_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_AC) | (((val) & 0xf) << 16)) -/* Info Type: Static address (12) */ -#define LTQ_ES_ADR_TB_CTL2_REG_INFOT (0x1 << 12) -#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_VAL(val) (((val) & 0x1) << 12) -#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_INFOT) >> 12) & 0x1) -#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_INFOT) | (((val) & 0x1) << 12)) -/* Info_Ctrl/Age Timer (10:0) */ -#define LTQ_ES_ADR_TB_CTL2_REG_ITAT (0x7ff) -#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_VAL(val) (((val) & 0x7ff) << 0) -#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_ITAT) >> 0) & 0x7ff) -#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_ITAT) | (((val) & 0x7ff) << 0)) - -/******************************************************************************* - * Address Table Status 0 Register - ******************************************************************************/ - -/* Address [31:0] (31:0) */ -#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0 (0xFFFFFFFFL) -#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0) >> 0) & 0xFFFFFFFFL) - -/******************************************************************************* - * Address Table Status 1 Register - ******************************************************************************/ - -/* Port Map (22:20) */ -#define LTQ_ES_ADR_TB_ST1_REG_PMAPS (0x7 << 20) -#define LTQ_ES_ADR_TB_ST1_REG_PMAPS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_PMAPS) >> 20) & 0x7) -/* FID group (17:16) */ -#define LTQ_ES_ADR_TB_ST1_REG_FIDS (0x3 << 16) -#define LTQ_ES_ADR_TB_ST1_REG_FIDS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_FIDS) >> 16) & 0x3) -/* Address [47:32] (15:0) */ -#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32 (0xffff) -#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32) >> 0) & 0xffff) - -/******************************************************************************* - * Address Table Status 2 Register - ******************************************************************************/ - -/* Busy (31) */ -#define LTQ_ES_ADR_TB_ST2_REG_BUSY (0x1 << 31) -#define LTQ_ES_ADR_TB_ST2_REG_BUSY_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BUSY) >> 31) & 0x1) -/* Result (30:28) */ -#define LTQ_ES_ADR_TB_ST2_REG_RSLT (0x7 << 28) -#define LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_RSLT) >> 28) & 0x7) -/* Command (22:20) */ -#define LTQ_ES_ADR_TB_ST2_REG_CMD (0x7 << 20) -#define LTQ_ES_ADR_TB_ST2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_CMD) >> 20) & 0x7) -/* Access Control (19:16) */ -#define LTQ_ES_ADR_TB_ST2_REG_AC (0xf << 16) -#define LTQ_ES_ADR_TB_ST2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_AC) >> 16) & 0xf) -/* Bad Status (14) */ -#define LTQ_ES_ADR_TB_ST2_REG_BAD (0x1 << 14) -#define LTQ_ES_ADR_TB_ST2_REG_BAD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BAD) >> 14) & 0x1) -/* Occupy (13) */ -#define LTQ_ES_ADR_TB_ST2_REG_OCP (0x1 << 13) -#define LTQ_ES_ADR_TB_ST2_REG_OCP_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_OCP) >> 13) & 0x1) -/* Info Type: Static address (12) */ -#define LTQ_ES_ADR_TB_ST2_REG_INFOTS (0x1 << 12) -#define LTQ_ES_ADR_TB_ST2_REG_INFOTS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_INFOTS) >> 12) & 0x1) -/* Info_Ctrl/Age Timer Status (10:0) */ -#define LTQ_ES_ADR_TB_ST2_REG_ITATS (0x7ff) -#define LTQ_ES_ADR_TB_ST2_REG_ITATS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_ITATS) >> 0) & 0x7ff) - -/******************************************************************************* - * RMON Counter Control Register - ******************************************************************************/ - -/* Reserved (31:12) */ -#define LTQ_ES_RMON_CTL_REG_RES (0xfffff << 12) -#define LTQ_ES_RMON_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_RES) >> 12) & 0xfffff) -/* Busy/Access Start (11) */ -#define LTQ_ES_RMON_CTL_REG_BAS (0x1 << 11) -#define LTQ_ES_RMON_CTL_REG_BAS_VAL(val) (((val) & 0x1) << 11) -#define LTQ_ES_RMON_CTL_REG_BAS_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_BAS) >> 11) & 0x1) -#define LTQ_ES_RMON_CTL_REG_BAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_BAS) | (((val) & 0x1) << 11)) -/* Command for access counter (10:9) */ -#define LTQ_ES_RMON_CTL_REG_CAC (0x3 << 9) -#define LTQ_ES_RMON_CTL_REG_CAC_VAL(val) (((val) & 0x3) << 9) -#define LTQ_ES_RMON_CTL_REG_CAC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_CAC) >> 9) & 0x3) -#define LTQ_ES_RMON_CTL_REG_CAC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_CAC) | (((val) & 0x3) << 9)) -/* Port (8:6) */ -#define LTQ_ES_RMON_CTL_REG_PORTC (0x7 << 6) -#define LTQ_ES_RMON_CTL_REG_PORTC_VAL(val) (((val) & 0x7) << 6) -#define LTQ_ES_RMON_CTL_REG_PORTC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_PORTC) >> 6) & 0x7) -#define LTQ_ES_RMON_CTL_REG_PORTC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_PORTC) | (((val) & 0x7) << 6)) -/* Counter Offset (5:0) */ -#define LTQ_ES_RMON_CTL_REG_OFFSET (0x3f) -#define LTQ_ES_RMON_CTL_REG_OFFSET_VAL(val) (((val) & 0x3f) << 0) -#define LTQ_ES_RMON_CTL_REG_OFFSET_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_OFFSET) >> 0) & 0x3f) -#define LTQ_ES_RMON_CTL_REG_OFFSET_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_OFFSET) | (((val) & 0x3f) << 0)) - -/******************************************************************************* - * RMON Counter Status Register - ******************************************************************************/ - -/* Counter [31:0] or Counter[63:32] for byte count (31:0) */ -#define LTQ_ES_RMON_ST_REG_COUNTER (0xFFFFFFFFL) -#define LTQ_ES_RMON_ST_REG_COUNTER_GET(val) ((((val) & LTQ_ES_RMON_ST_REG_COUNTER) >> 0) & 0xFFFFFFFFL) - -/******************************************************************************* - * MDIO Indirect Access Control - ******************************************************************************/ - -/* The Write Data to the MDIO register (31:16) */ -#define LTQ_ES_MDIO_CTL_REG_WD (0xffff << 16) -#define LTQ_ES_MDIO_CTL_REG_WD_VAL(val) (((val) & 0xffff) << 16) -#define LTQ_ES_MDIO_CTL_REG_WD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_WD) >> 16) & 0xffff) -#define LTQ_ES_MDIO_CTL_REG_WD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_WD) | (((val) & 0xffff) << 16)) -/* Busy state (15) */ -#define LTQ_ES_MDIO_CTL_REG_MBUSY (0x1 << 15) -#define LTQ_ES_MDIO_CTL_REG_MBUSY_VAL(val) (((val) & 0x1) << 15) -#define LTQ_ES_MDIO_CTL_REG_MBUSY_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_MBUSY) >> 15) & 0x1) -#define LTQ_ES_MDIO_CTL_REG_MBUSY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_MBUSY) | (((val) & 0x1) << 15)) -/* Reserved (14:12) */ -#define LTQ_ES_MDIO_CTL_REG_RES (0x7 << 12) -#define LTQ_ES_MDIO_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_RES) >> 12) & 0x7) -/* Operation Code (11:10) */ -#define LTQ_ES_MDIO_CTL_REG_OP (0x3 << 10) -#define LTQ_ES_MDIO_CTL_REG_OP_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_MDIO_CTL_REG_OP_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_OP) >> 10) & 0x3) -#define LTQ_ES_MDIO_CTL_REG_OP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_OP) | (((val) & 0x3) << 10)) -/* PHY Address (9:5) */ -#define LTQ_ES_MDIO_CTL_REG_PHYAD (0x1f << 5) -#define LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(val) (((val) & 0x1f) << 5) -#define LTQ_ES_MDIO_CTL_REG_PHYAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_PHYAD) >> 5) & 0x1f) -#define LTQ_ES_MDIO_CTL_REG_PHYAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_PHYAD) | (((val) & 0x1f) << 5)) -/* Register Address (4:0) */ -#define LTQ_ES_MDIO_CTL_REG_REGAD (0x1f) -#define LTQ_ES_MDIO_CTL_REG_REGAD_VAL(val) (((val) & 0x1f) << 0) -#define LTQ_ES_MDIO_CTL_REG_REGAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_REGAD) >> 0) & 0x1f) -#define LTQ_ES_MDIO_CTL_REG_REGAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_REGAD) | (((val) & 0x1f) << 0)) - -/******************************************************************************* - * MDIO Indirect Read Data - ******************************************************************************/ - -/* Reserved (31:16) */ -#define LTQ_ES_MDIO_DATA_REG_RES (0xffff << 16) -#define LTQ_ES_MDIO_DATA_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RES) >> 16) & 0xffff) -/* The Read Data (15:0) */ -#define LTQ_ES_MDIO_DATA_REG_RD (0xffff) -#define LTQ_ES_MDIO_DATA_REG_RD_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RD) >> 0) & 0xffff) - -/******************************************************************************* - * Type Filter Action - ******************************************************************************/ - -/* Destination Queue for Type Filter 7 (31:30) */ -#define LTQ_ES_TP_FLT_ACT_REG_QATF7 (0x3 << 30) -#define LTQ_ES_TP_FLT_ACT_REG_QATF7_VAL(val) (((val) & 0x3) << 30) -#define LTQ_ES_TP_FLT_ACT_REG_QATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF7) >> 30) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_QATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF7) | (((val) & 0x3) << 30)) -/* Destination Queue for Type Filter 6 (29:28) */ -#define LTQ_ES_TP_FLT_ACT_REG_QATF6 (0x3 << 28) -#define LTQ_ES_TP_FLT_ACT_REG_QATF6_VAL(val) (((val) & 0x3) << 28) -#define LTQ_ES_TP_FLT_ACT_REG_QATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF6) >> 28) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_QATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF6) | (((val) & 0x3) << 28)) -/* Destination Queue for Type Filter 5 (27:26) */ -#define LTQ_ES_TP_FLT_ACT_REG_QTF5 (0x3 << 26) -#define LTQ_ES_TP_FLT_ACT_REG_QTF5_VAL(val) (((val) & 0x3) << 26) -#define LTQ_ES_TP_FLT_ACT_REG_QTF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF5) >> 26) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_QTF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF5) | (((val) & 0x3) << 26)) -/* Destination Queue for Type Filter 4 (25:24) */ -#define LTQ_ES_TP_FLT_ACT_REG_QTF4 (0x3 << 24) -#define LTQ_ES_TP_FLT_ACT_REG_QTF4_VAL(val) (((val) & 0x3) << 24) -#define LTQ_ES_TP_FLT_ACT_REG_QTF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF4) >> 24) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_QTF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF4) | (((val) & 0x3) << 24)) -/* Destination Queue for Type Filter 3 (23:22) */ -#define LTQ_ES_TP_FLT_ACT_REG_QTF3 (0x3 << 22) -#define LTQ_ES_TP_FLT_ACT_REG_QTF3_VAL(val) (((val) & 0x3) << 22) -#define LTQ_ES_TP_FLT_ACT_REG_QTF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF3) >> 22) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_QTF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF3) | (((val) & 0x3) << 22)) -/* Destination Queue for Type Filter 2 (21:20) */ -#define LTQ_ES_TP_FLT_ACT_REG_QTF2 (0x3 << 20) -#define LTQ_ES_TP_FLT_ACT_REG_QTF2_VAL(val) (((val) & 0x3) << 20) -#define LTQ_ES_TP_FLT_ACT_REG_QTF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF2) >> 20) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_QTF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF2) | (((val) & 0x3) << 20)) -/* Destination Queue for Type Filter 1 (19:18) */ -#define LTQ_ES_TP_FLT_ACT_REG_QTF1 (0x3 << 18) -#define LTQ_ES_TP_FLT_ACT_REG_QTF1_VAL(val) (((val) & 0x3) << 18) -#define LTQ_ES_TP_FLT_ACT_REG_QTF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF1) >> 18) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_QTF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF1) | (((val) & 0x3) << 18)) -/* Destination Queue for Type Filter 0 (17:16) */ -#define LTQ_ES_TP_FLT_ACT_REG_QTF0 (0x3 << 16) -#define LTQ_ES_TP_FLT_ACT_REG_QTF0_VAL(val) (((val) & 0x3) << 16) -#define LTQ_ES_TP_FLT_ACT_REG_QTF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF0) >> 16) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_QTF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF0) | (((val) & 0x3) << 16)) -/* Action for Type Filter 7 (15:14) */ -#define LTQ_ES_TP_FLT_ACT_REG_ATF7 (0x3 << 14) -#define LTQ_ES_TP_FLT_ACT_REG_ATF7_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_TP_FLT_ACT_REG_ATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF7) >> 14) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_ATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF7) | (((val) & 0x3) << 14)) -/* Action for Type Filter 6 (13:12) */ -#define LTQ_ES_TP_FLT_ACT_REG_ATF6 (0x3 << 12) -#define LTQ_ES_TP_FLT_ACT_REG_ATF6_VAL(val) (((val) & 0x3) << 12) -#define LTQ_ES_TP_FLT_ACT_REG_ATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF6) >> 12) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_ATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF6) | (((val) & 0x3) << 12)) -/* Action for Type Filter 5 (11:10) */ -#define LTQ_ES_TP_FLT_ACT_REG_ATF5 (0x3 << 10) -#define LTQ_ES_TP_FLT_ACT_REG_ATF5_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_TP_FLT_ACT_REG_ATF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF5) >> 10) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_ATF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF5) | (((val) & 0x3) << 10)) -/* Action for Type Filter 4 (9:8) */ -#define LTQ_ES_TP_FLT_ACT_REG_ATF4 (0x3 << 8) -#define LTQ_ES_TP_FLT_ACT_REG_ATF4_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_TP_FLT_ACT_REG_ATF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF4) >> 8) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_ATF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF4) | (((val) & 0x3) << 8)) -/* Action for Type Filter 3 (7:6) */ -#define LTQ_ES_TP_FLT_ACT_REG_ATF3 (0x3 << 6) -#define LTQ_ES_TP_FLT_ACT_REG_ATF3_VAL(val) (((val) & 0x3) << 6) -#define LTQ_ES_TP_FLT_ACT_REG_ATF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF3) >> 6) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_ATF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF3) | (((val) & 0x3) << 6)) -/* Action for Type Filter 2 (5:4) */ -#define LTQ_ES_TP_FLT_ACT_REG_ATF2 (0x3 << 4) -#define LTQ_ES_TP_FLT_ACT_REG_ATF2_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_TP_FLT_ACT_REG_ATF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF2) >> 4) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_ATF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF2) | (((val) & 0x3) << 4)) -/* Action for Type Filter 1 (3:2) */ -#define LTQ_ES_TP_FLT_ACT_REG_ATF1 (0x3 << 2) -#define LTQ_ES_TP_FLT_ACT_REG_ATF1_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_TP_FLT_ACT_REG_ATF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF1) >> 2) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_ATF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF1) | (((val) & 0x3) << 2)) -/* Action for Type Filter 0 (1:0) */ -#define LTQ_ES_TP_FLT_ACT_REG_ATF0 (0x3) -#define LTQ_ES_TP_FLT_ACT_REG_ATF0_VAL(val) (((val) & 0x3) << 0) -#define LTQ_ES_TP_FLT_ACT_REG_ATF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF0) >> 0) & 0x3) -#define LTQ_ES_TP_FLT_ACT_REG_ATF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF0) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * Protocol Filter Action - ******************************************************************************/ - -/* Action for Protocol Filter 7 (15:14) */ -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7 (0x3 << 14) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF7) >> 14) & 0x3) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF7) | (((val) & 0x3) << 14)) -/* Action for Protocol Filter 6 (13:12) */ -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6 (0x3 << 12) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_VAL(val) (((val) & 0x3) << 12) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF6) >> 12) & 0x3) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF6) | (((val) & 0x3) << 12)) -/* Action for Protocol Filter 5 (11:10) */ -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5 (0x3 << 10) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF5) >> 10) & 0x3) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF5) | (((val) & 0x3) << 10)) -/* Action for Protocol Filter 4 (9:8) */ -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4 (0x3 << 8) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF4) >> 8) & 0x3) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF4) | (((val) & 0x3) << 8)) -/* Action for Protocol Filter 3 (7:6) */ -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3 (0x3 << 6) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_VAL(val) (((val) & 0x3) << 6) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF3) >> 6) & 0x3) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF3) | (((val) & 0x3) << 6)) -/* Action for Protocol Filter 2 (5:4) */ -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2 (0x3 << 4) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF2) >> 4) & 0x3) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF2) | (((val) & 0x3) << 4)) -/* Action for Protocol Filter 1 (3:2) */ -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1 (0x3 << 2) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF1) >> 2) & 0x3) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF1) | (((val) & 0x3) << 2)) -/* Action for Protocol Filter 0 (1:0) */ -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0 (0x3) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_VAL(val) (((val) & 0x3) << 0) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF0) >> 0) & 0x3) -#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF0) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * VLAN Filter 0 - ******************************************************************************/ - -/* Res (31:24) */ -#define LTQ_ES_VLAN_FLT0_REG_RES (0xff << 24) -#define LTQ_ES_VLAN_FLT0_REG_RES_VAL(val) (((val) & 0xff) << 24) -#define LTQ_ES_VLAN_FLT0_REG_RES_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_RES) >> 24) & 0xff) -#define LTQ_ES_VLAN_FLT0_REG_RES_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_RES) | (((val) & 0xff) << 24)) -/* FID (23:22) */ -#define LTQ_ES_VLAN_FLT0_REG_FID (0x3 << 22) -#define LTQ_ES_VLAN_FLT0_REG_FID_VAL(val) (((val) & 0x3) << 22) -#define LTQ_ES_VLAN_FLT0_REG_FID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_FID) >> 22) & 0x3) -#define LTQ_ES_VLAN_FLT0_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_FID) | (((val) & 0x3) << 22)) -/* Tagged Member (21:19) */ -#define LTQ_ES_VLAN_FLT0_REG_TM (0x7 << 19) -#define LTQ_ES_VLAN_FLT0_REG_TM_VAL(val) (((val) & 0x7) << 19) -#define LTQ_ES_VLAN_FLT0_REG_TM_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_TM) >> 19) & 0x7) -#define LTQ_ES_VLAN_FLT0_REG_TM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_TM) | (((val) & 0x7) << 19)) -/* Member (18:16) */ -#define LTQ_ES_VLAN_FLT0_REG_M (0x7 << 16) -#define LTQ_ES_VLAN_FLT0_REG_M_VAL(val) (((val) & 0x7) << 16) -#define LTQ_ES_VLAN_FLT0_REG_M_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_M) >> 16) & 0x7) -#define LTQ_ES_VLAN_FLT0_REG_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_M) | (((val) & 0x7) << 16)) -/* VLAN_Valid (15) */ -#define LTQ_ES_VLAN_FLT0_REG_VV (0x1 << 15) -#define LTQ_ES_VLAN_FLT0_REG_VV_VAL(val) (((val) & 0x1) << 15) -#define LTQ_ES_VLAN_FLT0_REG_VV_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VV) >> 15) & 0x1) -#define LTQ_ES_VLAN_FLT0_REG_VV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VV) | (((val) & 0x1) << 15)) -/* VLAN PRI (14:12) */ -#define LTQ_ES_VLAN_FLT0_REG_VP (0x7 << 12) -#define LTQ_ES_VLAN_FLT0_REG_VP_VAL(val) (((val) & 0x7) << 12) -#define LTQ_ES_VLAN_FLT0_REG_VP_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VP) >> 12) & 0x7) -#define LTQ_ES_VLAN_FLT0_REG_VP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VP) | (((val) & 0x7) << 12)) -/* VID (11:0) */ -#define LTQ_ES_VLAN_FLT0_REG_VID (0xfff) -#define LTQ_ES_VLAN_FLT0_REG_VID_VAL(val) (((val) & 0xfff) << 0) -#define LTQ_ES_VLAN_FLT0_REG_VID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VID) >> 0) & 0xfff) -#define LTQ_ES_VLAN_FLT0_REG_VID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VID) | (((val) & 0xfff) << 0)) - -/******************************************************************************* - * Type Filter 10 - ******************************************************************************/ - -/* Value 1 Compared with Ether-Type (31:16) */ -#define LTQ_ES_TP_FLT10_REG_VCET1 (0xffff << 16) -#define LTQ_ES_TP_FLT10_REG_VCET1_VAL(val) (((val) & 0xffff) << 16) -#define LTQ_ES_TP_FLT10_REG_VCET1_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET1) >> 16) & 0xffff) -#define LTQ_ES_TP_FLT10_REG_VCET1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET1) | (((val) & 0xffff) << 16)) -/* Value 0 Compared with Ether-Type (15:0) */ -#define LTQ_ES_TP_FLT10_REG_VCET0 (0xffff) -#define LTQ_ES_TP_FLT10_REG_VCET0_VAL(val) (((val) & 0xffff) << 0) -#define LTQ_ES_TP_FLT10_REG_VCET0_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET0) >> 0) & 0xffff) -#define LTQ_ES_TP_FLT10_REG_VCET0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET0) | (((val) & 0xffff) << 0)) - -/******************************************************************************* - * DiffServMapping 0 - ******************************************************************************/ - -/* Priority Queue F (31:30) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQF (0x3 << 30) -#define LTQ_ES_DFSRV_MAP0_REG_PQF_VAL(val) (((val) & 0x3) << 30) -#define LTQ_ES_DFSRV_MAP0_REG_PQF_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQF) >> 30) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQF) | (((val) & 0x3) << 30)) -/* Priority Queue E (29:28) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQE (0x3 << 28) -#define LTQ_ES_DFSRV_MAP0_REG_PQE_VAL(val) (((val) & 0x3) << 28) -#define LTQ_ES_DFSRV_MAP0_REG_PQE_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQE) >> 28) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQE) | (((val) & 0x3) << 28)) -/* Priority Queue D (27:26) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQD (0x3 << 26) -#define LTQ_ES_DFSRV_MAP0_REG_PQD_VAL(val) (((val) & 0x3) << 26) -#define LTQ_ES_DFSRV_MAP0_REG_PQD_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQD) >> 26) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQD) | (((val) & 0x3) << 26)) -/* Priority Queue C (25:24) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQC (0x3 << 24) -#define LTQ_ES_DFSRV_MAP0_REG_PQC_VAL(val) (((val) & 0x3) << 24) -#define LTQ_ES_DFSRV_MAP0_REG_PQC_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQC) >> 24) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQC) | (((val) & 0x3) << 24)) -/* Priority Queue B (23:22) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQB (0x3 << 22) -#define LTQ_ES_DFSRV_MAP0_REG_PQB_VAL(val) (((val) & 0x3) << 22) -#define LTQ_ES_DFSRV_MAP0_REG_PQB_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQB) >> 22) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQB_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQB) | (((val) & 0x3) << 22)) -/* Priority Queue A (21:20) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQA (0x3 << 20) -#define LTQ_ES_DFSRV_MAP0_REG_PQA_VAL(val) (((val) & 0x3) << 20) -#define LTQ_ES_DFSRV_MAP0_REG_PQA_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQA) >> 20) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQA) | (((val) & 0x3) << 20)) -/* Priority Queue 9 (19:18) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ9 (0x3 << 18) -#define LTQ_ES_DFSRV_MAP0_REG_PQ9_VAL(val) (((val) & 0x3) << 18) -#define LTQ_ES_DFSRV_MAP0_REG_PQ9_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ9) >> 18) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ9_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ9) | (((val) & 0x3) << 18)) -/* Priority Queue 8 (17:16) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ8 (0x3 << 16) -#define LTQ_ES_DFSRV_MAP0_REG_PQ8_VAL(val) (((val) & 0x3) << 16) -#define LTQ_ES_DFSRV_MAP0_REG_PQ8_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ8) >> 16) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ8_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ8) | (((val) & 0x3) << 16)) -/* Priority Queue 7 (15:14) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ7 (0x3 << 14) -#define LTQ_ES_DFSRV_MAP0_REG_PQ7_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_DFSRV_MAP0_REG_PQ7_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ7) >> 14) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ7) | (((val) & 0x3) << 14)) -/* Priority Queue 6 (13:12) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ6 (0x3 << 12) -#define LTQ_ES_DFSRV_MAP0_REG_PQ6_VAL(val) (((val) & 0x3) << 12) -#define LTQ_ES_DFSRV_MAP0_REG_PQ6_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ6) >> 12) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ6) | (((val) & 0x3) << 12)) -/* Priority Queue 5 (11:10) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ5 (0x3 << 10) -#define LTQ_ES_DFSRV_MAP0_REG_PQ5_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_DFSRV_MAP0_REG_PQ5_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ5) >> 10) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ5) | (((val) & 0x3) << 10)) -/* Priority Queue 4 (9:8) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ4 (0x3 << 8) -#define LTQ_ES_DFSRV_MAP0_REG_PQ4_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_DFSRV_MAP0_REG_PQ4_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ4) >> 8) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ4) | (((val) & 0x3) << 8)) -/* Priority Queue 3 (7:6) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ3 (0x3 << 6) -#define LTQ_ES_DFSRV_MAP0_REG_PQ3_VAL(val) (((val) & 0x3) << 6) -#define LTQ_ES_DFSRV_MAP0_REG_PQ3_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ3) >> 6) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ3) | (((val) & 0x3) << 6)) -/* Priority Queue 2 (5:4) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ2 (0x3 << 4) -#define LTQ_ES_DFSRV_MAP0_REG_PQ2_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_DFSRV_MAP0_REG_PQ2_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ2) >> 4) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ2) | (((val) & 0x3) << 4)) -/* Priority Queue 1 (3:2) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ1 (0x3 << 2) -#define LTQ_ES_DFSRV_MAP0_REG_PQ1_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_DFSRV_MAP0_REG_PQ1_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ1) >> 2) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ1) | (((val) & 0x3) << 2)) -/* Priority Queue 0 (1:0) */ -#define LTQ_ES_DFSRV_MAP0_REG_PQ0 (0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ0_VAL(val) (((val) & 0x3) << 0) -#define LTQ_ES_DFSRV_MAP0_REG_PQ0_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ0) >> 0) & 0x3) -#define LTQ_ES_DFSRV_MAP0_REG_PQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ0) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * DiffServMapping 1 - ******************************************************************************/ - -/* Priority Queue 1F (31:30) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ1F (0x3 << 30) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_VAL(val) (((val) & 0x3) << 30) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1F) >> 30) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1F) | (((val) & 0x3) << 30)) -/* Priority Queue 1E (29:28) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ1E (0x3 << 28) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_VAL(val) (((val) & 0x3) << 28) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1E) >> 28) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1E) | (((val) & 0x3) << 28)) -/* Priority Queue 1D (27:26) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ1D (0x3 << 26) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_VAL(val) (((val) & 0x3) << 26) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1D) >> 26) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1D) | (((val) & 0x3) << 26)) -/* Priority Queue 1C (25:24) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ1C (0x3 << 24) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_VAL(val) (((val) & 0x3) << 24) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1C) >> 24) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1C) | (((val) & 0x3) << 24)) -/* Priority Queue 1B (23:22) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ1B (0x3 << 22) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_VAL(val) (((val) & 0x3) << 22) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1B) >> 22) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1B) | (((val) & 0x3) << 22)) -/* Priority Queue 1A (21:20) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ1A (0x3 << 20) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_VAL(val) (((val) & 0x3) << 20) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1A) >> 20) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1A) | (((val) & 0x3) << 20)) -/* Priority Queue 19 (19:18) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ19 (0x3 << 18) -#define LTQ_ES_DFSRV_MAP1_REG_PQ19_VAL(val) (((val) & 0x3) << 18) -#define LTQ_ES_DFSRV_MAP1_REG_PQ19_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ19) >> 18) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ19_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ19) | (((val) & 0x3) << 18)) -/* Priority Queue 18 (17:16) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ18 (0x3 << 16) -#define LTQ_ES_DFSRV_MAP1_REG_PQ18_VAL(val) (((val) & 0x3) << 16) -#define LTQ_ES_DFSRV_MAP1_REG_PQ18_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ18) >> 16) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ18_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ18) | (((val) & 0x3) << 16)) -/* Priority Queue 17 (15:14) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ17 (0x3 << 14) -#define LTQ_ES_DFSRV_MAP1_REG_PQ17_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_DFSRV_MAP1_REG_PQ17_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ17) >> 14) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ17_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ17) | (((val) & 0x3) << 14)) -/* Priority Queue 16 (13:12) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ16 (0x3 << 12) -#define LTQ_ES_DFSRV_MAP1_REG_PQ16_VAL(val) (((val) & 0x3) << 12) -#define LTQ_ES_DFSRV_MAP1_REG_PQ16_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ16) >> 12) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ16_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ16) | (((val) & 0x3) << 12)) -/* Priority Queue 15 (11:10) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ15 (0x3 << 10) -#define LTQ_ES_DFSRV_MAP1_REG_PQ15_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_DFSRV_MAP1_REG_PQ15_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ15) >> 10) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ15_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ15) | (((val) & 0x3) << 10)) -/* Priority Queue 14 (9:8) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ14 (0x3 << 8) -#define LTQ_ES_DFSRV_MAP1_REG_PQ14_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_DFSRV_MAP1_REG_PQ14_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ14) >> 8) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ14_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ14) | (((val) & 0x3) << 8)) -/* Priority Queue 13 (7:6) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ13 (0x3 << 6) -#define LTQ_ES_DFSRV_MAP1_REG_PQ13_VAL(val) (((val) & 0x3) << 6) -#define LTQ_ES_DFSRV_MAP1_REG_PQ13_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ13) >> 6) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ13_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ13) | (((val) & 0x3) << 6)) -/* Priority Queue 12 (5:4) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ12 (0x3 << 4) -#define LTQ_ES_DFSRV_MAP1_REG_PQ12_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_DFSRV_MAP1_REG_PQ12_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ12) >> 4) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ12_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ12) | (((val) & 0x3) << 4)) -/* Priority Queue 11 (3:2) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ11 (0x3 << 2) -#define LTQ_ES_DFSRV_MAP1_REG_PQ11_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_DFSRV_MAP1_REG_PQ11_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ11) >> 2) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ11_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ11) | (((val) & 0x3) << 2)) -/* Priority Queue 10 (1:0) */ -#define LTQ_ES_DFSRV_MAP1_REG_PQ10 (0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ10_VAL(val) (((val) & 0x3) << 0) -#define LTQ_ES_DFSRV_MAP1_REG_PQ10_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ10) >> 0) & 0x3) -#define LTQ_ES_DFSRV_MAP1_REG_PQ10_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ10) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * DiffServMapping 2 - ******************************************************************************/ - -/* Priority Queue 2F (31:30) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ2F (0x3 << 30) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_VAL(val) (((val) & 0x3) << 30) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2F) >> 30) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2F) | (((val) & 0x3) << 30)) -/* Priority Queue 2E (29:28) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ2E (0x3 << 28) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_VAL(val) (((val) & 0x3) << 28) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2E) >> 28) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2E) | (((val) & 0x3) << 28)) -/* Priority Queue 2D (27:26) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ2D (0x3 << 26) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_VAL(val) (((val) & 0x3) << 26) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2D) >> 26) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2D) | (((val) & 0x3) << 26)) -/* Priority Queue 2C (25:24) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ2C (0x3 << 24) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_VAL(val) (((val) & 0x3) << 24) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2C) >> 24) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2C) | (((val) & 0x3) << 24)) -/* Priority Queue 2B (23:22) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ2B (0x3 << 22) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_VAL(val) (((val) & 0x3) << 22) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2B) >> 22) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2B) | (((val) & 0x3) << 22)) -/* Priority Queue 2A (21:20) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ2A (0x3 << 20) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_VAL(val) (((val) & 0x3) << 20) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2A) >> 20) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2A) | (((val) & 0x3) << 20)) -/* Priority Queue 29 (19:18) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ29 (0x3 << 18) -#define LTQ_ES_DFSRV_MAP2_REG_PQ29_VAL(val) (((val) & 0x3) << 18) -#define LTQ_ES_DFSRV_MAP2_REG_PQ29_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ29) >> 18) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ29_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ29) | (((val) & 0x3) << 18)) -/* Priority Queue 28 (17:16) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ28 (0x3 << 16) -#define LTQ_ES_DFSRV_MAP2_REG_PQ28_VAL(val) (((val) & 0x3) << 16) -#define LTQ_ES_DFSRV_MAP2_REG_PQ28_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ28) >> 16) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ28_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ28) | (((val) & 0x3) << 16)) -/* Priority Queue 27 (15:14) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ27 (0x3 << 14) -#define LTQ_ES_DFSRV_MAP2_REG_PQ27_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_DFSRV_MAP2_REG_PQ27_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ27) >> 14) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ27_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ27) | (((val) & 0x3) << 14)) -/* Priority Queue 26 (13:12) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ26 (0x3 << 12) -#define LTQ_ES_DFSRV_MAP2_REG_PQ26_VAL(val) (((val) & 0x3) << 12) -#define LTQ_ES_DFSRV_MAP2_REG_PQ26_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ26) >> 12) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ26_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ26) | (((val) & 0x3) << 12)) -/* Priority Queue 25 (11:10) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ25 (0x3 << 10) -#define LTQ_ES_DFSRV_MAP2_REG_PQ25_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_DFSRV_MAP2_REG_PQ25_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ25) >> 10) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ25_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ25) | (((val) & 0x3) << 10)) -/* Priority Queue 24 (9:8) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ24 (0x3 << 8) -#define LTQ_ES_DFSRV_MAP2_REG_PQ24_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_DFSRV_MAP2_REG_PQ24_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ24) >> 8) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ24_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ24) | (((val) & 0x3) << 8)) -/* Priority Queue 23 (7:6) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ23 (0x3 << 6) -#define LTQ_ES_DFSRV_MAP2_REG_PQ23_VAL(val) (((val) & 0x3) << 6) -#define LTQ_ES_DFSRV_MAP2_REG_PQ23_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ23) >> 6) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ23_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ23) | (((val) & 0x3) << 6)) -/* Priority Queue 22 (5:4) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ22 (0x3 << 4) -#define LTQ_ES_DFSRV_MAP2_REG_PQ22_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_DFSRV_MAP2_REG_PQ22_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ22) >> 4) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ22_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ22) | (((val) & 0x3) << 4)) -/* Priority Queue 21 (3:2) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ21 (0x3 << 2) -#define LTQ_ES_DFSRV_MAP2_REG_PQ21_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_DFSRV_MAP2_REG_PQ21_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ21) >> 2) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ21_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ21) | (((val) & 0x3) << 2)) -/* Priority Queue 20 (1:0) */ -#define LTQ_ES_DFSRV_MAP2_REG_PQ20 (0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ20_VAL(val) (((val) & 0x3) << 0) -#define LTQ_ES_DFSRV_MAP2_REG_PQ20_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ20) >> 0) & 0x3) -#define LTQ_ES_DFSRV_MAP2_REG_PQ20_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ20) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * DiffServMapping 3 - ******************************************************************************/ - -/* Priority Queue 3F (31:30) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ3F (0x3 << 30) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_VAL(val) (((val) & 0x3) << 30) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3F) >> 30) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3F) | (((val) & 0x3) << 30)) -/* Priority Queue 3E (29:28) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ3E (0x3 << 28) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_VAL(val) (((val) & 0x3) << 28) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3E) >> 28) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3E) | (((val) & 0x3) << 28)) -/* Priority Queue 3D (27:26) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ3D (0x3 << 26) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_VAL(val) (((val) & 0x3) << 26) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3D) >> 26) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3D) | (((val) & 0x3) << 26)) -/* Priority Queue 3C (25:24) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ3C (0x3 << 24) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_VAL(val) (((val) & 0x3) << 24) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3C) >> 24) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3C) | (((val) & 0x3) << 24)) -/* Priority Queue 3B (23:22) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ3B (0x3 << 22) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_VAL(val) (((val) & 0x3) << 22) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3B) >> 22) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3B) | (((val) & 0x3) << 22)) -/* Priority Queue 3A (21:20) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ3A (0x3 << 20) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_VAL(val) (((val) & 0x3) << 20) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3A) >> 20) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3A) | (((val) & 0x3) << 20)) -/* Priority Queue 39 (19:18) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ39 (0x3 << 18) -#define LTQ_ES_DFSRV_MAP3_REG_PQ39_VAL(val) (((val) & 0x3) << 18) -#define LTQ_ES_DFSRV_MAP3_REG_PQ39_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ39) >> 18) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ39_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ39) | (((val) & 0x3) << 18)) -/* Priority Queue 38 (17:16) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ38 (0x3 << 16) -#define LTQ_ES_DFSRV_MAP3_REG_PQ38_VAL(val) (((val) & 0x3) << 16) -#define LTQ_ES_DFSRV_MAP3_REG_PQ38_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ38) >> 16) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ38_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ38) | (((val) & 0x3) << 16)) -/* Priority Queue 37 (15:14) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ37 (0x3 << 14) -#define LTQ_ES_DFSRV_MAP3_REG_PQ37_VAL(val) (((val) & 0x3) << 14) -#define LTQ_ES_DFSRV_MAP3_REG_PQ37_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ37) >> 14) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ37_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ37) | (((val) & 0x3) << 14)) -/* Priority Queue 36 (13:12) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ36 (0x3 << 12) -#define LTQ_ES_DFSRV_MAP3_REG_PQ36_VAL(val) (((val) & 0x3) << 12) -#define LTQ_ES_DFSRV_MAP3_REG_PQ36_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ36) >> 12) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ36_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ36) | (((val) & 0x3) << 12)) -/* Priority Queue 35 (11:10) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ35 (0x3 << 10) -#define LTQ_ES_DFSRV_MAP3_REG_PQ35_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_DFSRV_MAP3_REG_PQ35_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ35) >> 10) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ35_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ35) | (((val) & 0x3) << 10)) -/* Priority Queue 34 (9:8) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ34 (0x3 << 8) -#define LTQ_ES_DFSRV_MAP3_REG_PQ34_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_DFSRV_MAP3_REG_PQ34_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ34) >> 8) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ34_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ34) | (((val) & 0x3) << 8)) -/* Priority Queue 33 (7:6) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ33 (0x3 << 6) -#define LTQ_ES_DFSRV_MAP3_REG_PQ33_VAL(val) (((val) & 0x3) << 6) -#define LTQ_ES_DFSRV_MAP3_REG_PQ33_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ33) >> 6) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ33_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ33) | (((val) & 0x3) << 6)) -/* Priority Queue 32 (5:4) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ32 (0x3 << 4) -#define LTQ_ES_DFSRV_MAP3_REG_PQ32_VAL(val) (((val) & 0x3) << 4) -#define LTQ_ES_DFSRV_MAP3_REG_PQ32_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ32) >> 4) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ32) | (((val) & 0x3) << 4)) -/* Priority Queue 31 (3:2) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ31 (0x3 << 2) -#define LTQ_ES_DFSRV_MAP3_REG_PQ31_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_DFSRV_MAP3_REG_PQ31_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ31) >> 2) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ31_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ31) | (((val) & 0x3) << 2)) -/* Priority Queue 30 (1:0) */ -#define LTQ_ES_DFSRV_MAP3_REG_PQ30 (0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ30_VAL(val) (((val) & 0x3) << 0) -#define LTQ_ES_DFSRV_MAP3_REG_PQ30_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ30) >> 0) & 0x3) -#define LTQ_ES_DFSRV_MAP3_REG_PQ30_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ30) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * TCP/UDP Port Filter 0 - ******************************************************************************/ - -/* Reserved (31:30) */ -#define LTQ_ES_TCP_PF0_REG_RES (0x3 << 30) -#define LTQ_ES_TCP_PF0_REG_RES_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_RES) >> 30) & 0x3) -/* Action for TCP/UDP Port Filter 0 (29:28) */ -#define LTQ_ES_TCP_PF0_REG_ATUF0 (0x3 << 28) -#define LTQ_ES_TCP_PF0_REG_ATUF0_VAL(val) (((val) & 0x3) << 28) -#define LTQ_ES_TCP_PF0_REG_ATUF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_ATUF0) >> 28) & 0x3) -#define LTQ_ES_TCP_PF0_REG_ATUF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_ATUF0) | (((val) & 0x3) << 28)) -/* TCP/UDP PRI for TCP/UDP Port Filter 0 (27:26) */ -#define LTQ_ES_TCP_PF0_REG_TUPF0 (0x3 << 26) -#define LTQ_ES_TCP_PF0_REG_TUPF0_VAL(val) (((val) & 0x3) << 26) -#define LTQ_ES_TCP_PF0_REG_TUPF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_TUPF0) >> 26) & 0x3) -#define LTQ_ES_TCP_PF0_REG_TUPF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_TUPF0) | (((val) & 0x3) << 26)) -/* Compare TCP/UDP Source Port or Destination Port (25:24) */ -#define LTQ_ES_TCP_PF0_REG_COMP0 (0x3 << 24) -#define LTQ_ES_TCP_PF0_REG_COMP0_VAL(val) (((val) & 0x3) << 24) -#define LTQ_ES_TCP_PF0_REG_COMP0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_COMP0) >> 24) & 0x3) -#define LTQ_ES_TCP_PF0_REG_COMP0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_COMP0) | (((val) & 0x3) << 24)) -/* Port Range in TCP/UDP (23:16) */ -#define LTQ_ES_TCP_PF0_REG_PRANGE0 (0xff << 16) -#define LTQ_ES_TCP_PF0_REG_PRANGE0_VAL(val) (((val) & 0xff) << 16) -#define LTQ_ES_TCP_PF0_REG_PRANGE0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_PRANGE0) >> 16) & 0xff) -#define LTQ_ES_TCP_PF0_REG_PRANGE0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_PRANGE0) | (((val) & 0xff) << 16)) -/* Base Port number 0 (15:0) */ -#define LTQ_ES_TCP_PF0_REG_BASEPT0 (0xffff) -#define LTQ_ES_TCP_PF0_REG_BASEPT0_VAL(val) (((val) & 0xffff) << 0) -#define LTQ_ES_TCP_PF0_REG_BASEPT0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_BASEPT0) >> 0) & 0xffff) -#define LTQ_ES_TCP_PF0_REG_BASEPT0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_BASEPT0) | (((val) & 0xffff) << 0)) - -/******************************************************************************* - * Reserved DA(0180C2000003~0180C2000000) control register - ******************************************************************************/ - -/* Valid bit for 0180C2000003 (31) */ -#define LTQ_ES_RA_03_00_REG_RA03_VALID (0x1 << 31) -#define LTQ_ES_RA_03_00_REG_RA03_VALID_VAL(val) (((val) & 0x1) << 31) -#define LTQ_ES_RA_03_00_REG_RA03_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_VALID) >> 31) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA03_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_VALID) | (((val) & 0x1) << 31)) -/* Span bit for 0180C2000003 (30) */ -#define LTQ_ES_RA_03_00_REG_RA03_SPAN (0x1 << 30) -#define LTQ_ES_RA_03_00_REG_RA03_SPAN_VAL(val) (((val) & 0x1) << 30) -#define LTQ_ES_RA_03_00_REG_RA03_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_SPAN) >> 30) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA03_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_SPAN) | (((val) & 0x1) << 30)) -/* Management bit for 0180C2000003 (29) */ -#define LTQ_ES_RA_03_00_REG_RA03_MG (0x1 << 29) -#define LTQ_ES_RA_03_00_REG_RA03_MG_VAL(val) (((val) & 0x1) << 29) -#define LTQ_ES_RA_03_00_REG_RA03_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_MG) >> 29) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA03_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_MG) | (((val) & 0x1) << 29)) -/* Cross_VLAN bit for 0180C2000003 (28) */ -#define LTQ_ES_RA_03_00_REG_RA03_CV (0x1 << 28) -#define LTQ_ES_RA_03_00_REG_RA03_CV_VAL(val) (((val) & 0x1) << 28) -#define LTQ_ES_RA_03_00_REG_RA03_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_CV) >> 28) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA03_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_CV) | (((val) & 0x1) << 28)) -/* TXTAG bit for 0180C2000003 (27:26) */ -#define LTQ_ES_RA_03_00_REG_RA03_TXTAG (0x3 << 26) -#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_VAL(val) (((val) & 0x3) << 26) -#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_TXTAG) >> 26) & 0x3) -#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_TXTAG) | (((val) & 0x3) << 26)) -/* Action bit for 0180C2000003 (25:24) */ -#define LTQ_ES_RA_03_00_REG_RA03_ACT (0x3 << 24) -#define LTQ_ES_RA_03_00_REG_RA03_ACT_VAL(val) (((val) & 0x3) << 24) -#define LTQ_ES_RA_03_00_REG_RA03_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_ACT) >> 24) & 0x3) -#define LTQ_ES_RA_03_00_REG_RA03_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_ACT) | (((val) & 0x3) << 24)) -/* Valid bit for 0180C2000002 (23) */ -#define LTQ_ES_RA_03_00_REG_RA02_VALID (0x1 << 23) -#define LTQ_ES_RA_03_00_REG_RA02_VALID_VAL(val) (((val) & 0x1) << 23) -#define LTQ_ES_RA_03_00_REG_RA02_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_VALID) >> 23) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA02_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_VALID) | (((val) & 0x1) << 23)) -/* Span bit for 0180C2000002 (22) */ -#define LTQ_ES_RA_03_00_REG_RA02_SPAN (0x1 << 22) -#define LTQ_ES_RA_03_00_REG_RA02_SPAN_VAL(val) (((val) & 0x1) << 22) -#define LTQ_ES_RA_03_00_REG_RA02_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_SPAN) >> 22) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA02_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_SPAN) | (((val) & 0x1) << 22)) -/* Management bit for 0180C2000002 (21) */ -#define LTQ_ES_RA_03_00_REG_RA02_MG (0x1 << 21) -#define LTQ_ES_RA_03_00_REG_RA02_MG_VAL(val) (((val) & 0x1) << 21) -#define LTQ_ES_RA_03_00_REG_RA02_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_MG) >> 21) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA02_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_MG) | (((val) & 0x1) << 21)) -/* Cross_VLAN bit for 0180C2000002 (20) */ -#define LTQ_ES_RA_03_00_REG_RA02_CV (0x1 << 20) -#define LTQ_ES_RA_03_00_REG_RA02_CV_VAL(val) (((val) & 0x1) << 20) -#define LTQ_ES_RA_03_00_REG_RA02_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_CV) >> 20) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA02_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_CV) | (((val) & 0x1) << 20)) -/* TXTAG bit for 0180C2000002 (19:18) */ -#define LTQ_ES_RA_03_00_REG_RA02_TXTAG (0x3 << 18) -#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_VAL(val) (((val) & 0x3) << 18) -#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_TXTAG) >> 18) & 0x3) -#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_TXTAG) | (((val) & 0x3) << 18)) -/* Action bit for 0180C2000002 (17:16) */ -#define LTQ_ES_RA_03_00_REG_RA02_ACT (0x3 << 16) -#define LTQ_ES_RA_03_00_REG_RA02_ACT_VAL(val) (((val) & 0x3) << 16) -#define LTQ_ES_RA_03_00_REG_RA02_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_ACT) >> 16) & 0x3) -#define LTQ_ES_RA_03_00_REG_RA02_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_ACT) | (((val) & 0x3) << 16)) -/* Valid bit for 0180C2000001 (15) */ -#define LTQ_ES_RA_03_00_REG_RA01_VALID (0x1 << 15) -#define LTQ_ES_RA_03_00_REG_RA01_VALID_VAL(val) (((val) & 0x1) << 15) -#define LTQ_ES_RA_03_00_REG_RA01_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_VALID) >> 15) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA01_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_VALID) | (((val) & 0x1) << 15)) -/* Span bit for 0180C2000001 (14) */ -#define LTQ_ES_RA_03_00_REG_RA01_SPAN (0x1 << 14) -#define LTQ_ES_RA_03_00_REG_RA01_SPAN_VAL(val) (((val) & 0x1) << 14) -#define LTQ_ES_RA_03_00_REG_RA01_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_SPAN) >> 14) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA01_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_SPAN) | (((val) & 0x1) << 14)) -/* Management bit for 0180C2000001 (13) */ -#define LTQ_ES_RA_03_00_REG_RA01_MG (0x1 << 13) -#define LTQ_ES_RA_03_00_REG_RA01_MG_VAL(val) (((val) & 0x1) << 13) -#define LTQ_ES_RA_03_00_REG_RA01_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_MG) >> 13) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA01_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_MG) | (((val) & 0x1) << 13)) -/* Cross_VLAN bit for 0180C2000001 (12) */ -#define LTQ_ES_RA_03_00_REG_RA01_CV (0x1 << 12) -#define LTQ_ES_RA_03_00_REG_RA01_CV_VAL(val) (((val) & 0x1) << 12) -#define LTQ_ES_RA_03_00_REG_RA01_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_CV) >> 12) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA01_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_CV) | (((val) & 0x1) << 12)) -/* TXTAG bit for 0180C2000001 (11:10) */ -#define LTQ_ES_RA_03_00_REG_RA01_TXTAG (0x3 << 10) -#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_VAL(val) (((val) & 0x3) << 10) -#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_TXTAG) >> 10) & 0x3) -#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_TXTAG) | (((val) & 0x3) << 10)) -/* Action bit for 0180C2000001 (9:8) */ -#define LTQ_ES_RA_03_00_REG_RA01_ACT (0x3 << 8) -#define LTQ_ES_RA_03_00_REG_RA01_ACT_VAL(val) (((val) & 0x3) << 8) -#define LTQ_ES_RA_03_00_REG_RA01_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_ACT) >> 8) & 0x3) -#define LTQ_ES_RA_03_00_REG_RA01_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_ACT) | (((val) & 0x3) << 8)) -/* Valid bit for 0180C2000000 (7) */ -#define LTQ_ES_RA_03_00_REG_RA00_VALID (0x1 << 7) -#define LTQ_ES_RA_03_00_REG_RA00_VALID_VAL(val) (((val) & 0x1) << 7) -#define LTQ_ES_RA_03_00_REG_RA00_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_VALID) >> 7) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA00_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_VALID) | (((val) & 0x1) << 7)) -/* Span bit for 0180C2000000 (6) */ -#define LTQ_ES_RA_03_00_REG_RA00_SPAN (0x1 << 6) -#define LTQ_ES_RA_03_00_REG_RA00_SPAN_VAL(val) (((val) & 0x1) << 6) -#define LTQ_ES_RA_03_00_REG_RA00_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_SPAN) >> 6) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA00_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_SPAN) | (((val) & 0x1) << 6)) -/* Management bit for 0180C2000000 (5) */ -#define LTQ_ES_RA_03_00_REG_RA00_MG (0x1 << 5) -#define LTQ_ES_RA_03_00_REG_RA00_MG_VAL(val) (((val) & 0x1) << 5) -#define LTQ_ES_RA_03_00_REG_RA00_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_MG) >> 5) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA00_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_MG) | (((val) & 0x1) << 5)) -/* Cross_VLAN bit for 0180C2000000 (4) */ -#define LTQ_ES_RA_03_00_REG_RA00_CV (0x1 << 4) -#define LTQ_ES_RA_03_00_REG_RA00_CV_VAL(val) (((val) & 0x1) << 4) -#define LTQ_ES_RA_03_00_REG_RA00_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_CV) >> 4) & 0x1) -#define LTQ_ES_RA_03_00_REG_RA00_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_CV) | (((val) & 0x1) << 4)) -/* TXTAG bit for 0180C2000000 (3:2) */ -#define LTQ_ES_RA_03_00_REG_RA00_TXTAG (0x3 << 2) -#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_VAL(val) (((val) & 0x3) << 2) -#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_TXTAG) >> 2) & 0x3) -#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_TXTAG) | (((val) & 0x3) << 2)) -/* Action bit for 0180C2000000 (1:0) */ -#define LTQ_ES_RA_03_00_REG_RA00_ACT (0x3) -#define LTQ_ES_RA_03_00_REG_RA00_ACT_VAL(val) (((val) & 0x3) << 0) -#define LTQ_ES_RA_03_00_REG_RA00_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_ACT) >> 0) & 0x3) -#define LTQ_ES_RA_03_00_REG_RA00_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_ACT) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * Protocol Filter 0 - ******************************************************************************/ - -/* Value Compared with Protocol in IP Header (31:24) */ -#define LTQ_ES_PRTCL_F0_REG_PFR3 (0xff << 24) -#define LTQ_ES_PRTCL_F0_REG_PFR3_VAL(val) (((val) & 0xff) << 24) -#define LTQ_ES_PRTCL_F0_REG_PFR3_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR3) >> 24) & 0xff) -#define LTQ_ES_PRTCL_F0_REG_PFR3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR3) | (((val) & 0xff) << 24)) -/* Value Compared with Protocol in IP Header (23:16) */ -#define LTQ_ES_PRTCL_F0_REG_PFR2 (0xff << 16) -#define LTQ_ES_PRTCL_F0_REG_PFR2_VAL(val) (((val) & 0xff) << 16) -#define LTQ_ES_PRTCL_F0_REG_PFR2_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR2) >> 16) & 0xff) -#define LTQ_ES_PRTCL_F0_REG_PFR2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR2) | (((val) & 0xff) << 16)) -/* Value Compared with Protocol in IP Header (15:8) */ -#define LTQ_ES_PRTCL_F0_REG_PFR1 (0xff << 8) -#define LTQ_ES_PRTCL_F0_REG_PFR1_VAL(val) (((val) & 0xff) << 8) -#define LTQ_ES_PRTCL_F0_REG_PFR1_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR1) >> 8) & 0xff) -#define LTQ_ES_PRTCL_F0_REG_PFR1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR1) | (((val) & 0xff) << 8)) -/* Value Compared with Protocol in IP Header (7:0) */ -#define LTQ_ES_PRTCL_F0_REG_PFR0 (0xff) -#define LTQ_ES_PRTCL_F0_REG_PFR0_VAL(val) (((val) & 0xff) << 0) -#define LTQ_ES_PRTCL_F0_REG_PFR0_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR0) >> 0) & 0xff) -#define LTQ_ES_PRTCL_F0_REG_PFR0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR0) | (((val) & 0xff) << 0)) - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h deleted file mode 100644 index 06dc173544..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/mips/include/asm/mach-lantiq/svip/irq.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2010 Lantiq - * - */ - -#ifndef __IRQ_H -#define __IRQ_H - -#include <svip_irq.h> - -#define NR_IRQS 264 - -#include_next <irq.h> - -/* Functions for EXINT handling */ -extern int ifx_enable_external_int(u32 exint, u32 mode); -extern int ifx_disable_external_int(u32 exint); -extern int ifx_external_int_level(u32 exint); - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h deleted file mode 100644 index 697d672f36..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#ifndef _LTQ_SVIP_H__ -#define _LTQ_SVIP_H__ - -#ifdef CONFIG_SOC_SVIP - -#include <lantiq.h> - -/* Chip IDs */ -#define SOC_ID_SVIP 0x169 - -/* SoC Types */ -#define SOC_TYPE_SVIP 0x01 - -/* ASC0/1 - serial port */ -#define LTQ_ASC0_BASE_ADDR 0x14100100 -#define LTQ_ASC1_BASE_ADDR 0x14100200 -#define LTQ_ASC_SIZE 0x100 -#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) - -#define LTQ_ASC_TIR(x) (INT_NUM_IM0_IRL0 + (x * 8)) -#define LTQ_ASC_RIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 2) -#define LTQ_ASC_EIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 3) - -/* ICU - interrupt control unit */ -#define LTQ_ICU_BASE_ADDR 0x14106000 -#define LTQ_ICU_BASE_ADDR1 0x14106028 -#define LTQ_ICU_BASE_ADDR2 0x1E016000 -#define LTQ_ICU_BASE_ADDR3 0x1E016028 -#define LTQ_ICU_BASE_ADDR4 0x14106050 -#define LTQ_ICU_BASE_ADDR5 0x14106078 -#define LTQ_ICU_SIZE 0x100 - -/* WDT */ -#define LTQ_WDT_BASE_ADDR 0x1F8803F0 -#define LTQ_WDT_SIZE 0x10 - -/* Status */ -#define LTQ_STATUS_BASE_ADDR (KSEG1 + 0x1E000500) -#define LTQ_STATUS_CHIPID ((u32 *)(LTQ_STATUS_BASE_ADDR + 0x000C)) - -#define LTQ_EIU_BASE_ADDR 0 - -#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) -#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) - -extern __iomem void *ltq_ebu_membase; - -extern void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, - bool altsel0, bool altsel1); -extern int ltq_port_get_dir(unsigned int port, unsigned int pin); -extern int ltq_port_get_puden(unsigned int port, unsigned int pin); -extern int ltq_port_get_altsel0(unsigned int port, unsigned int pin); -extern int ltq_port_get_altsel1(unsigned int port, unsigned int pin); - -#define ltq_is_ar9() 0 -#define ltq_is_vr9() 0 -#define ltq_is_falcon() 0 - -#define BS_FLASH 0 -#define LTQ_RST_CAUSE_WDTRST 0x2 - -#endif /* CONFIG_SOC_SVIP */ -#endif /* _LTQ_SVIP_H__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h deleted file mode 100644 index 79966b7be7..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h +++ /dev/null @@ -1,242 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __MPS_REG_H -#define __MPS_REG_H - -#define mbs_r32(reg) ltq_r32(&mbs->reg) -#define mbs_w32(val, reg) ltq_w32(val, &mbs->reg) -#define mbs_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &mbs->reg) - -/** MBS register structure */ -struct svip_reg_mbs { - unsigned long reserved0[4]; - unsigned long mbsr0; /* 0x0010 */ - unsigned long mbsr1; /* 0x0014 */ - unsigned long mbsr2; /* 0x0018 */ - unsigned long mbsr3; /* 0x001c */ - unsigned long mbsr4; /* 0x0020 */ - unsigned long mbsr5; /* 0x0024 */ - unsigned long mbsr6; /* 0x0028 */ - unsigned long mbsr7; /* 0x002c */ - unsigned long mbsr8; /* 0x0030 */ - unsigned long mbsr9; /* 0x0034 */ - unsigned long mbsr10; /* 0x0038 */ - unsigned long mbsr11; /* 0x003c */ - unsigned long mbsr12; /* 0x0040 */ - unsigned long mbsr13; /* 0x0044 */ - unsigned long mbsr14; /* 0x0048 */ - unsigned long mbsr15; /* 0x004c */ - unsigned long mbsr16; /* 0x0050 */ - unsigned long mbsr17; /* 0x0054 */ - unsigned long mbsr18; /* 0x0058 */ - unsigned long mbsr19; /* 0x005c */ - unsigned long mbsr20; /* 0x0060 */ - unsigned long mbsr21; /* 0x0064 */ - unsigned long mbsr22; /* 0x0068 */ - unsigned long mbsr23; /* 0x006c */ - unsigned long mbsr24; /* 0x0070 */ - unsigned long mbsr25; /* 0x0074 */ - unsigned long mbsr26; /* 0x0078 */ - unsigned long mbsr27; /* 0x007c */ - unsigned long mbsr28; /* 0x0080 */ -}; - -/** MPS register structure */ -struct svip_reg_mps { - volatile unsigned long mps_swirn0set; /* 0x0000 */ - volatile unsigned long mps_swirn0en; /* 0x0004 */ - volatile unsigned long mps_swirn0cr; /* 0x0008 */ - volatile unsigned long mps_swirn0icr; /* 0x000C */ - volatile unsigned long mps_swirn1set; /* 0x0010 */ - volatile unsigned long mps_swirn1en; /* 0x0014 */ - volatile unsigned long mps_swirn1cr; /* 0x0018 */ - volatile unsigned long mps_swirn1icr; /* 0x001C */ - volatile unsigned long mps_swirn2set; /* 0x0020 */ - volatile unsigned long mps_swirn2en; /* 0x0024 */ - volatile unsigned long mps_swirn2cr; /* 0x0028 */ - volatile unsigned long mps_swirn2icr; /* 0x002C */ - volatile unsigned long mps_swirn3set; /* 0x0030 */ - volatile unsigned long mps_swirn3en; /* 0x0034 */ - volatile unsigned long mps_swirn3cr; /* 0x0038 */ - volatile unsigned long mps_swirn3icr; /* 0x003C */ - volatile unsigned long mps_swirn4set; /* 0x0040 */ - volatile unsigned long mps_swirn4en; /* 0x0044 */ - volatile unsigned long mps_swirn4cr; /* 0x0048 */ - volatile unsigned long mps_swirn4icr; /* 0x004C */ - volatile unsigned long mps_swirn5set; /* 0x0050 */ - volatile unsigned long mps_swirn5en; /* 0x0054 */ - volatile unsigned long mps_swirn5cr; /* 0x0058 */ - volatile unsigned long mps_swirn5icr; /* 0x005C */ - volatile unsigned long mps_swirn6set; /* 0x0060 */ - volatile unsigned long mps_swirn6en; /* 0x0064 */ - volatile unsigned long mps_swirn6cr; /* 0x0068 */ - volatile unsigned long mps_swirn6icr; /* 0x006C */ - volatile unsigned long mps_swirn7set; /* 0x0070 */ - volatile unsigned long mps_swirn7en; /* 0x0074 */ - volatile unsigned long mps_swirn7cr; /* 0x0078 */ - volatile unsigned long mps_swirn7icr; /* 0x007C */ - volatile unsigned long mps_swirn8set; /* 0x0080 */ - volatile unsigned long mps_swirn8en; /* 0x0084 */ - volatile unsigned long mps_swirn8cr; /* 0x0088 */ - volatile unsigned long mps_swirn8icr; /* 0x008C */ -}; - -/* Software Interrupt */ -#define IFX_MPS_SWIRN0SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0000)) -#define IFX_MPS_SWIRN0EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0004)) -#define IFX_MPS_SWIRN0CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0008)) -#define IFX_MPS_SWIRN0ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x000C)) -#define IFX_MPS_SWIRN1SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0010)) -#define IFX_MPS_SWIRN1EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0014)) -#define IFX_MPS_SWIRN1CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0018)) -#define IFX_MPS_SWIRN1ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x001C)) -#define IFX_MPS_SWIRN2SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0020)) -#define IFX_MPS_SWIRN2EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0024)) -#define IFX_MPS_SWIRN2CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0028)) -#define IFX_MPS_SWIRN2ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x002C)) -#define IFX_MPS_SWIRN3SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0030)) -#define IFX_MPS_SWIRN3EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0034)) -#define IFX_MPS_SWIRN3CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0038)) -#define IFX_MPS_SWIRN3ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x003C)) -#define IFX_MPS_SWIRN4SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0040)) -#define IFX_MPS_SWIRN4EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0044)) -#define IFX_MPS_SWIRN4CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0048)) -#define IFX_MPS_SWIRN4ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x004C)) -#define IFX_MPS_SWIRN5SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0050)) -#define IFX_MPS_SWIRN5EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0054)) -#define IFX_MPS_SWIRN5CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0058)) -#define IFX_MPS_SWIRN5ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x005C)) -#define IFX_MPS_SWIRN6SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0060)) -#define IFX_MPS_SWIRN6EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0064)) -#define IFX_MPS_SWIRN6CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0068)) -#define IFX_MPS_SWIRN6ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x006C)) -#define IFX_MPS_SWIRN7SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0070)) -#define IFX_MPS_SWIRN7EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0074)) -#define IFX_MPS_SWIRN7CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0078)) -#define IFX_MPS_SWIRN7ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x007C)) -#define IFX_MPS_SWIRN8SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0080)) -#define IFX_MPS_SWIRN8EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0084)) -#define IFX_MPS_SWIRN8ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x008C)) -#define IFX_MPS_SWIRN8CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0088)) - -/******************************************************************************* - * MPS_SWIRNSET Register - ******************************************************************************/ - -/* Software Interrupt Request IR5 (5) */ -#define IFX_MPS_SWIRNSET_IR5 (0x1 << 5) -#define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5) -#define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5) -/* Software Interrupt Request IR4 (4) */ -#define IFX_MPS_SWIRNSET_IR4 (0x1 << 4) -#define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4) -#define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val) & 1) << 4) -/* Software Interrupt Request IR3 (3) */ -#define IFX_MPS_SWIRNSET_IR3 (0x1 << 3) -#define IFX_MPS_SWIRNSET_IR3_VAL(val) (((val) & 0x1) << 3) -#define IFX_MPS_SWIRNSET_IR3_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR3) | (val) & 1) << 3) -/* Software Interrupt Request IR2 (2) */ -#define IFX_MPS_SWIRNSET_IR2 (0x1 << 2) -#define IFX_MPS_SWIRNSET_IR2_VAL(val) (((val) & 0x1) << 2) -#define IFX_MPS_SWIRNSET_IR2_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR2) | (val) & 1) << 2) -/* Software Interrupt Request IR1 (1) */ -#define IFX_MPS_SWIRNSET_IR1 (0x1 << 1) -#define IFX_MPS_SWIRNSET_IR1_VAL(val) (((val) & 0x1) << 1) -#define IFX_MPS_SWIRNSET_IR1_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR1) | (val) & 1) << 1) -/* Software Interrupt Request IR0 (0) */ -#define IFX_MPS_SWIRNSET_IR0 (0x1) -#define IFX_MPS_SWIRNSET_IR0_VAL(val) (((val) & 0x1) << 0) -#define IFX_MPS_SWIRNSET_IR0_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR0) | (val) & 1) << 0) - -/******************************************************************************* - * MPS_SWIRNEN Register - ******************************************************************************/ - -/* Software Interrupt Request IR5 (5) */ -#define IFX_MPS_SWIRNEN_IR5 (0x1 << 5) -#define IFX_MPS_SWIRNEN_IR5_VAL(val) (((val) & 0x1) << 5) -#define IFX_MPS_SWIRNEN_IR5_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR5) >> 5) & 0x1) -#define IFX_MPS_SWIRNEN_IR5_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR5) | (((val) & 0x1) << 5)) -/* Software Interrupt Request IR4 (4) */ -#define IFX_MPS_SWIRNEN_IR4 (0x1 << 4) -#define IFX_MPS_SWIRNEN_IR4_VAL(val) (((val) & 0x1) << 4) -#define IFX_MPS_SWIRNEN_IR4_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR4) >> 4) & 0x1) -#define IFX_MPS_SWIRNEN_IR4_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR4) | (((val) & 0x1) << 4)) -/* Software Interrupt Request IR3 (3) */ -#define IFX_MPS_SWIRNEN_IR3 (0x1 << 3) -#define IFX_MPS_SWIRNEN_IR3_VAL(val) (((val) & 0x1) << 3) -#define IFX_MPS_SWIRNEN_IR3_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR3) >> 3) & 0x1) -#define IFX_MPS_SWIRNEN_IR3_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR3) | (((val) & 0x1) << 3)) -/* Software Interrupt Request IR2 (2) */ -#define IFX_MPS_SWIRNEN_IR2 (0x1 << 2) -#define IFX_MPS_SWIRNEN_IR2_VAL(val) (((val) & 0x1) << 2) -#define IFX_MPS_SWIRNEN_IR2_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR2) >> 2) & 0x1) -#define IFX_MPS_SWIRNEN_IR2_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR2) | (((val) & 0x1) << 2)) -/* Software Interrupt Request IR1 (1) */ -#define IFX_MPS_SWIRNEN_IR1 (0x1 << 1) -#define IFX_MPS_SWIRNEN_IR1_VAL(val) (((val) & 0x1) << 1) -#define IFX_MPS_SWIRNEN_IR1_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR1) >> 1) & 0x1) -#define IFX_MPS_SWIRNEN_IR1_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR1) | (((val) & 0x1) << 1)) -/* Software Interrupt Request IR0 (0) */ -#define IFX_MPS_SWIRNEN_IR0 (0x1) -#define IFX_MPS_SWIRNEN_IR0_VAL(val) (((val) & 0x1) << 0) -#define IFX_MPS_SWIRNEN_IR0_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR0) >> 0) & 0x1) -#define IFX_MPS_SWIRNEN_IR0_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * MPS_SWIRNICR Register - ******************************************************************************/ - -/* Software Interrupt Request IR5 (5) */ -#define IFX_MPS_SWIRNICR_IR5 (0x1 << 5) -#define IFX_MPS_SWIRNICR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR5) >> 5) & 0x1) -/* Software Interrupt Request IR4 (4) */ -#define IFX_MPS_SWIRNICR_IR4 (0x1 << 4) -#define IFX_MPS_SWIRNICR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR4) >> 4) & 0x1) -/* Software Interrupt Request IR3 (3) */ -#define IFX_MPS_SWIRNICR_IR3 (0x1 << 3) -#define IFX_MPS_SWIRNICR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR3) >> 3) & 0x1) -/* Software Interrupt Request IR2 (2) */ -#define IFX_MPS_SWIRNICR_IR2 (0x1 << 2) -#define IFX_MPS_SWIRNICR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR2) >> 2) & 0x1) -/* Software Interrupt Request IR1 (1) */ -#define IFX_MPS_SWIRNICR_IR1 (0x1 << 1) -#define IFX_MPS_SWIRNICR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR1) >> 1) & 0x1) -/* Software Interrupt Request IR0 (0) */ -#define IFX_MPS_SWIRNICR_IR0 (0x1) -#define IFX_MPS_SWIRNICR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR0) >> 0) & 0x1) - -/******************************************************************************* - * MPS_SWIRNCR Register - ******************************************************************************/ - -/* Software Interrupt Request IR5 (5) */ -#define IFX_MPS_SWIRNCR_IR5 (0x1 << 5) -#define IFX_MPS_SWIRNCR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR5) >> 5) & 0x1) -/* Software Interrupt Request IR4 (4) */ -#define IFX_MPS_SWIRNCR_IR4 (0x1 << 4) -#define IFX_MPS_SWIRNCR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR4) >> 4) & 0x1) -/* Software Interrupt Request IR3 (3) */ -#define IFX_MPS_SWIRNCR_IR3 (0x1 << 3) -#define IFX_MPS_SWIRNCR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR3) >> 3) & 0x1) -/* Software Interrupt Request IR2 (2) */ -#define IFX_MPS_SWIRNCR_IR2 (0x1 << 2) -#define IFX_MPS_SWIRNCR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR2) >> 2) & 0x1) -/* Software Interrupt Request IR1 (1) */ -#define IFX_MPS_SWIRNCR_IR1 (0x1 << 1) -#define IFX_MPS_SWIRNCR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR1) >> 1) & 0x1) -/* Software Interrupt Request IR0 (0) */ -#define IFX_MPS_SWIRNCR_IR0 (0x1) -#define IFX_MPS_SWIRNCR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR0) >> 0) & 0x1) - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h deleted file mode 100644 index 57d04917fc..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h +++ /dev/null @@ -1,3262 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __PORT_REG_H -#define __PORT_REG_H - -#define port_r32(reg) __raw_readl(®) -#define port_w32(val, reg) __raw_writel(val, ®) - -/** PORT register structure */ -struct svip_reg_port { - volatile u32 out; /* 0x0000 */ - volatile u32 in; /* 0x0004 */ - volatile u32 dir; /* 0x0008 */ - volatile u32 altsel0; /* 0x000C */ - volatile u32 altsel1; /* 0x0010 */ - volatile u32 puen; /* 0x0014 */ - volatile u32 exintcr0; /* 0x0018 */ - volatile u32 exintcr1; /* 0x001C */ - volatile u32 irncr; /* 0x0020 */ - volatile u32 irnicr; /* 0x0024 */ - volatile u32 irnen; /* 0x0028 */ - volatile u32 irncfg; /* 0x002C */ - volatile u32 irnenset; /* 0x0030 */ - volatile u32 irnenclr; /* 0x0034 */ -}; - -/******************************************************************************* - * Port 0 Data Output Register - ******************************************************************************/ - -/* Port 0 Pin # Output Value (19) */ -#define PORT_P0_OUT_P19 (0x1 << 19) -#define PORT_P0_OUT_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_OUT_P19_GET(val) ((((val) & PORT_P0_OUT_P19) >> 19) & 0x1) -#define PORT_P0_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P19) | (((val) & 0x1) << 19)) -/* Port 0 Pin # Output Value (18) */ -#define PORT_P0_OUT_P18 (0x1 << 18) -#define PORT_P0_OUT_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P0_OUT_P18_GET(val) ((((val) & PORT_P0_OUT_P18) >> 18) & 0x1) -#define PORT_P0_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P18) | (((val) & 0x1) << 18)) -/* Port 0 Pin # Output Value (17) */ -#define PORT_P0_OUT_P17 (0x1 << 17) -#define PORT_P0_OUT_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_OUT_P17_GET(val) ((((val) & PORT_P0_OUT_P17) >> 17) & 0x1) -#define PORT_P0_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P17) | (((val) & 0x1) << 17)) -/* Port 0 Pin # Output Value (16) */ -#define PORT_P0_OUT_P16 (0x1 << 16) -#define PORT_P0_OUT_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_OUT_P16_GET(val) ((((val) & PORT_P0_OUT_P16) >> 16) & 0x1) -#define PORT_P0_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P16) | (((val) & 0x1) << 16)) -/* Port 0 Pin # Output Value (15) */ -#define PORT_P0_OUT_P15 (0x1 << 15) -#define PORT_P0_OUT_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_OUT_P15_GET(val) ((((val) & PORT_P0_OUT_P15) >> 15) & 0x1) -#define PORT_P0_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P15) | (((val) & 0x1) << 15)) -/* Port 0 Pin # Output Value (14) */ -#define PORT_P0_OUT_P14 (0x1 << 14) -#define PORT_P0_OUT_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_OUT_P14_GET(val) ((((val) & PORT_P0_OUT_P14) >> 14) & 0x1) -#define PORT_P0_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P14) | (((val) & 0x1) << 14)) -/* Port 0 Pin # Output Value (13) */ -#define PORT_P0_OUT_P13 (0x1 << 13) -#define PORT_P0_OUT_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_OUT_P13_GET(val) ((((val) & PORT_P0_OUT_P13) >> 13) & 0x1) -#define PORT_P0_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P13) | (((val) & 0x1) << 13)) -/* Port 0 Pin # Output Value (12) */ -#define PORT_P0_OUT_P12 (0x1 << 12) -#define PORT_P0_OUT_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_OUT_P12_GET(val) ((((val) & PORT_P0_OUT_P12) >> 12) & 0x1) -#define PORT_P0_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P12) | (((val) & 0x1) << 12)) -/* Port 0 Pin # Output Value (11) */ -#define PORT_P0_OUT_P11 (0x1 << 11) -#define PORT_P0_OUT_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_OUT_P11_GET(val) ((((val) & PORT_P0_OUT_P11) >> 11) & 0x1) -#define PORT_P0_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P11) | (((val) & 0x1) << 11)) -/* Port 0 Pin # Output Value (10) */ -#define PORT_P0_OUT_P10 (0x1 << 10) -#define PORT_P0_OUT_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_OUT_P10_GET(val) ((((val) & PORT_P0_OUT_P10) >> 10) & 0x1) -#define PORT_P0_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P10) | (((val) & 0x1) << 10)) -/* Port 0 Pin # Output Value (9) */ -#define PORT_P0_OUT_P9 (0x1 << 9) -#define PORT_P0_OUT_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_OUT_P9_GET(val) ((((val) & PORT_P0_OUT_P9) >> 9) & 0x1) -#define PORT_P0_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P9) | (((val) & 0x1) << 9)) -/* Port 0 Pin # Output Value (8) */ -#define PORT_P0_OUT_P8 (0x1 << 8) -#define PORT_P0_OUT_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_OUT_P8_GET(val) ((((val) & PORT_P0_OUT_P8) >> 8) & 0x1) -#define PORT_P0_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P8) | (((val) & 0x1) << 8)) -/* Port 0 Pin # Output Value (7) */ -#define PORT_P0_OUT_P7 (0x1 << 7) -#define PORT_P0_OUT_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_OUT_P7_GET(val) ((((val) & PORT_P0_OUT_P7) >> 7) & 0x1) -#define PORT_P0_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P7) | (((val) & 0x1) << 7)) -/* Port 0 Pin # Output Value (6) */ -#define PORT_P0_OUT_P6 (0x1 << 6) -#define PORT_P0_OUT_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P0_OUT_P6_GET(val) ((((val) & PORT_P0_OUT_P6) >> 6) & 0x1) -#define PORT_P0_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P6) | (((val) & 0x1) << 6)) -/* Port 0 Pin # Output Value (5) */ -#define PORT_P0_OUT_P5 (0x1 << 5) -#define PORT_P0_OUT_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P0_OUT_P5_GET(val) ((((val) & PORT_P0_OUT_P5) >> 5) & 0x1) -#define PORT_P0_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P5) | (((val) & 0x1) << 5)) -/* Port 0 Pin # Output Value (4) */ -#define PORT_P0_OUT_P4 (0x1 << 4) -#define PORT_P0_OUT_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P0_OUT_P4_GET(val) ((((val) & PORT_P0_OUT_P4) >> 4) & 0x1) -#define PORT_P0_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P4) | (((val) & 0x1) << 4)) -/* Port 0 Pin # Output Value (3) */ -#define PORT_P0_OUT_P3 (0x1 << 3) -#define PORT_P0_OUT_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P0_OUT_P3_GET(val) ((((val) & PORT_P0_OUT_P3) >> 3) & 0x1) -#define PORT_P0_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P3) | (((val) & 0x1) << 3)) -/* Port 0 Pin # Output Value (2) */ -#define PORT_P0_OUT_P2 (0x1 << 2) -#define PORT_P0_OUT_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P0_OUT_P2_GET(val) ((((val) & PORT_P0_OUT_P2) >> 2) & 0x1) -#define PORT_P0_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P2) | (((val) & 0x1) << 2)) -/* Port 0 Pin # Output Value (1) */ -#define PORT_P0_OUT_P1 (0x1 << 1) -#define PORT_P0_OUT_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P0_OUT_P1_GET(val) ((((val) & PORT_P0_OUT_P1) >> 1) & 0x1) -#define PORT_P0_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P1) | (((val) & 0x1) << 1)) -/* Port 0 Pin # Output Value (0) */ -#define PORT_P0_OUT_P0 (0x1) -#define PORT_P0_OUT_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P0_OUT_P0_GET(val) ((((val) & PORT_P0_OUT_P0) >> 0) & 0x1) -#define PORT_P0_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 0 Data Input Register - ******************************************************************************/ - -/* Port 0 Pin # Latched Input Value (19) */ -#define PORT_P0_IN_P19 (0x1 << 19) -#define PORT_P0_IN_P19_GET(val) ((((val) & PORT_P0_IN_P19) >> 19) & 0x1) -/* Port 0 Pin # Latched Input Value (18) */ -#define PORT_P0_IN_P18 (0x1 << 18) -#define PORT_P0_IN_P18_GET(val) ((((val) & PORT_P0_IN_P18) >> 18) & 0x1) -/* Port 0 Pin # Latched Input Value (17) */ -#define PORT_P0_IN_P17 (0x1 << 17) -#define PORT_P0_IN_P17_GET(val) ((((val) & PORT_P0_IN_P17) >> 17) & 0x1) -/* Port 0 Pin # Latched Input Value (16) */ -#define PORT_P0_IN_P16 (0x1 << 16) -#define PORT_P0_IN_P16_GET(val) ((((val) & PORT_P0_IN_P16) >> 16) & 0x1) -/* Port 0 Pin # Latched Input Value (15) */ -#define PORT_P0_IN_P15 (0x1 << 15) -#define PORT_P0_IN_P15_GET(val) ((((val) & PORT_P0_IN_P15) >> 15) & 0x1) -/* Port 0 Pin # Latched Input Value (14) */ -#define PORT_P0_IN_P14 (0x1 << 14) -#define PORT_P0_IN_P14_GET(val) ((((val) & PORT_P0_IN_P14) >> 14) & 0x1) -/* Port 0 Pin # Latched Input Value (13) */ -#define PORT_P0_IN_P13 (0x1 << 13) -#define PORT_P0_IN_P13_GET(val) ((((val) & PORT_P0_IN_P13) >> 13) & 0x1) -/* Port 0 Pin # Latched Input Value (12) */ -#define PORT_P0_IN_P12 (0x1 << 12) -#define PORT_P0_IN_P12_GET(val) ((((val) & PORT_P0_IN_P12) >> 12) & 0x1) -/* Port 0 Pin # Latched Input Value (11) */ -#define PORT_P0_IN_P11 (0x1 << 11) -#define PORT_P0_IN_P11_GET(val) ((((val) & PORT_P0_IN_P11) >> 11) & 0x1) -/* Port 0 Pin # Latched Input Value (10) */ -#define PORT_P0_IN_P10 (0x1 << 10) -#define PORT_P0_IN_P10_GET(val) ((((val) & PORT_P0_IN_P10) >> 10) & 0x1) -/* Port 0 Pin # Latched Input Value (9) */ -#define PORT_P0_IN_P9 (0x1 << 9) -#define PORT_P0_IN_P9_GET(val) ((((val) & PORT_P0_IN_P9) >> 9) & 0x1) -/* Port 0 Pin # Latched Input Value (8) */ -#define PORT_P0_IN_P8 (0x1 << 8) -#define PORT_P0_IN_P8_GET(val) ((((val) & PORT_P0_IN_P8) >> 8) & 0x1) -/* Port 0 Pin # Latched Input Value (7) */ -#define PORT_P0_IN_P7 (0x1 << 7) -#define PORT_P0_IN_P7_GET(val) ((((val) & PORT_P0_IN_P7) >> 7) & 0x1) -/* Port 0 Pin # Latched Input Value (6) */ -#define PORT_P0_IN_P6 (0x1 << 6) -#define PORT_P0_IN_P6_GET(val) ((((val) & PORT_P0_IN_P6) >> 6) & 0x1) -/* Port 0 Pin # Latched Input Value (5) */ -#define PORT_P0_IN_P5 (0x1 << 5) -#define PORT_P0_IN_P5_GET(val) ((((val) & PORT_P0_IN_P5) >> 5) & 0x1) -/* Port 0 Pin # Latched Input Value (4) */ -#define PORT_P0_IN_P4 (0x1 << 4) -#define PORT_P0_IN_P4_GET(val) ((((val) & PORT_P0_IN_P4) >> 4) & 0x1) -/* Port 0 Pin # Latched Input Value (3) */ -#define PORT_P0_IN_P3 (0x1 << 3) -#define PORT_P0_IN_P3_GET(val) ((((val) & PORT_P0_IN_P3) >> 3) & 0x1) -/* Port 0 Pin # Latched Input Value (2) */ -#define PORT_P0_IN_P2 (0x1 << 2) -#define PORT_P0_IN_P2_GET(val) ((((val) & PORT_P0_IN_P2) >> 2) & 0x1) -/* Port 0 Pin # Latched Input Value (1) */ -#define PORT_P0_IN_P1 (0x1 << 1) -#define PORT_P0_IN_P1_GET(val) ((((val) & PORT_P0_IN_P1) >> 1) & 0x1) -/* Port 0 Pin # Latched Input Value (0) */ -#define PORT_P0_IN_P0 (0x1) -#define PORT_P0_IN_P0_GET(val) ((((val) & PORT_P0_IN_P0) >> 0) & 0x1) - -/******************************************************************************* - * Port 0 Direction Register - ******************************************************************************/ - -/* Port 0 Pin #Direction Control (19) */ -#define PORT_P0_DIR_P19 (0x1 << 19) -#define PORT_P0_DIR_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_DIR_P19_GET(val) ((((val) & PORT_P0_DIR_P19) >> 19) & 0x1) -#define PORT_P0_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P19) | (((val) & 0x1) << 19)) -/* Port 0 Pin #Direction Control (18) */ -#define PORT_P0_DIR_P18 (0x1 << 18) -#define PORT_P0_DIR_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P0_DIR_P18_GET(val) ((((val) & PORT_P0_DIR_P18) >> 18) & 0x1) -#define PORT_P0_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P18) | (((val) & 0x1) << 18)) -/* Port 0 Pin #Direction Control (17) */ -#define PORT_P0_DIR_P17 (0x1 << 17) -#define PORT_P0_DIR_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_DIR_P17_GET(val) ((((val) & PORT_P0_DIR_P17) >> 17) & 0x1) -#define PORT_P0_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P17) | (((val) & 0x1) << 17)) -/* Port 0 Pin #Direction Control (16) */ -#define PORT_P0_DIR_P16 (0x1 << 16) -#define PORT_P0_DIR_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_DIR_P16_GET(val) ((((val) & PORT_P0_DIR_P16) >> 16) & 0x1) -#define PORT_P0_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P16) | (((val) & 0x1) << 16)) -/* Port 0 Pin #Direction Control (15) */ -#define PORT_P0_DIR_P15 (0x1 << 15) -#define PORT_P0_DIR_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_DIR_P15_GET(val) ((((val) & PORT_P0_DIR_P15) >> 15) & 0x1) -#define PORT_P0_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P15) | (((val) & 0x1) << 15)) -/* Port 0 Pin #Direction Control (14) */ -#define PORT_P0_DIR_P14 (0x1 << 14) -#define PORT_P0_DIR_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_DIR_P14_GET(val) ((((val) & PORT_P0_DIR_P14) >> 14) & 0x1) -#define PORT_P0_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P14) | (((val) & 0x1) << 14)) -/* Port 0 Pin #Direction Control (13) */ -#define PORT_P0_DIR_P13 (0x1 << 13) -#define PORT_P0_DIR_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_DIR_P13_GET(val) ((((val) & PORT_P0_DIR_P13) >> 13) & 0x1) -#define PORT_P0_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P13) | (((val) & 0x1) << 13)) -/* Port 0 Pin #Direction Control (12) */ -#define PORT_P0_DIR_P12 (0x1 << 12) -#define PORT_P0_DIR_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_DIR_P12_GET(val) ((((val) & PORT_P0_DIR_P12) >> 12) & 0x1) -#define PORT_P0_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P12) | (((val) & 0x1) << 12)) -/* Port 0 Pin #Direction Control (11) */ -#define PORT_P0_DIR_P11 (0x1 << 11) -#define PORT_P0_DIR_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_DIR_P11_GET(val) ((((val) & PORT_P0_DIR_P11) >> 11) & 0x1) -#define PORT_P0_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P11) | (((val) & 0x1) << 11)) -/* Port 0 Pin #Direction Control (10) */ -#define PORT_P0_DIR_P10 (0x1 << 10) -#define PORT_P0_DIR_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_DIR_P10_GET(val) ((((val) & PORT_P0_DIR_P10) >> 10) & 0x1) -#define PORT_P0_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P10) | (((val) & 0x1) << 10)) -/* Port 0 Pin #Direction Control (9) */ -#define PORT_P0_DIR_P9 (0x1 << 9) -#define PORT_P0_DIR_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_DIR_P9_GET(val) ((((val) & PORT_P0_DIR_P9) >> 9) & 0x1) -#define PORT_P0_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P9) | (((val) & 0x1) << 9)) -/* Port 0 Pin #Direction Control (8) */ -#define PORT_P0_DIR_P8 (0x1 << 8) -#define PORT_P0_DIR_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_DIR_P8_GET(val) ((((val) & PORT_P0_DIR_P8) >> 8) & 0x1) -#define PORT_P0_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P8) | (((val) & 0x1) << 8)) -/* Port 0 Pin #Direction Control (7) */ -#define PORT_P0_DIR_P7 (0x1 << 7) -#define PORT_P0_DIR_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_DIR_P7_GET(val) ((((val) & PORT_P0_DIR_P7) >> 7) & 0x1) -#define PORT_P0_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P7) | (((val) & 0x1) << 7)) -/* Port 0 Pin #Direction Control (6) */ -#define PORT_P0_DIR_P6 (0x1 << 6) -#define PORT_P0_DIR_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P0_DIR_P6_GET(val) ((((val) & PORT_P0_DIR_P6) >> 6) & 0x1) -#define PORT_P0_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P6) | (((val) & 0x1) << 6)) -/* Port 0 Pin #Direction Control (5) */ -#define PORT_P0_DIR_P5 (0x1 << 5) -#define PORT_P0_DIR_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P0_DIR_P5_GET(val) ((((val) & PORT_P0_DIR_P5) >> 5) & 0x1) -#define PORT_P0_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P5) | (((val) & 0x1) << 5)) -/* Port 0 Pin #Direction Control (4) */ -#define PORT_P0_DIR_P4 (0x1 << 4) -#define PORT_P0_DIR_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P0_DIR_P4_GET(val) ((((val) & PORT_P0_DIR_P4) >> 4) & 0x1) -#define PORT_P0_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P4) | (((val) & 0x1) << 4)) -/* Port 0 Pin #Direction Control (3) */ -#define PORT_P0_DIR_P3 (0x1 << 3) -#define PORT_P0_DIR_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P0_DIR_P3_GET(val) ((((val) & PORT_P0_DIR_P3) >> 3) & 0x1) -#define PORT_P0_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P3) | (((val) & 0x1) << 3)) -/* Port 0 Pin #Direction Control (2) */ -#define PORT_P0_DIR_P2 (0x1 << 2) -#define PORT_P0_DIR_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P0_DIR_P2_GET(val) ((((val) & PORT_P0_DIR_P2) >> 2) & 0x1) -#define PORT_P0_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P2) | (((val) & 0x1) << 2)) -/* Port 0 Pin #Direction Control (1) */ -#define PORT_P0_DIR_P1 (0x1 << 1) -#define PORT_P0_DIR_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P0_DIR_P1_GET(val) ((((val) & PORT_P0_DIR_P1) >> 1) & 0x1) -#define PORT_P0_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P1) | (((val) & 0x1) << 1)) -/* Port 0 Pin #Direction Control (0) */ -#define PORT_P0_DIR_P0 (0x1) -#define PORT_P0_DIR_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P0_DIR_P0_GET(val) ((((val) & PORT_P0_DIR_P0) >> 0) & 0x1) -#define PORT_P0_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 0 Alternate Function Select Register 0 - ******************************************************************************/ - -/* Alternate Function at Port 0 Bit # (19) */ -#define PORT_P0_ALTSEL0_P19 (0x1 << 19) -#define PORT_P0_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_ALTSEL0_P19_GET(val) ((((val) & PORT_P0_ALTSEL0_P19) >> 19) & 0x1) -#define PORT_P0_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P19) | (((val) & 0x1) << 19)) -/* Alternate Function at Port 0 Bit # (18) */ -#define PORT_P0_ALTSEL0_P18 (0x1 << 18) -#define PORT_P0_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P0_ALTSEL0_P18_GET(val) ((((val) & PORT_P0_ALTSEL0_P18) >> 18) & 0x1) -#define PORT_P0_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P18) | (((val) & 0x1) << 18)) -/* Alternate Function at Port 0 Bit # (17) */ -#define PORT_P0_ALTSEL0_P17 (0x1 << 17) -#define PORT_P0_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_ALTSEL0_P17_GET(val) ((((val) & PORT_P0_ALTSEL0_P17) >> 17) & 0x1) -#define PORT_P0_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P17) | (((val) & 0x1) << 17)) -/* Alternate Function at Port 0 Bit # (16) */ -#define PORT_P0_ALTSEL0_P16 (0x1 << 16) -#define PORT_P0_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_ALTSEL0_P16_GET(val) ((((val) & PORT_P0_ALTSEL0_P16) >> 16) & 0x1) -#define PORT_P0_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P16) | (((val) & 0x1) << 16)) -/* Alternate Function at Port 0 Bit # (15) */ -#define PORT_P0_ALTSEL0_P15 (0x1 << 15) -#define PORT_P0_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_ALTSEL0_P15_GET(val) ((((val) & PORT_P0_ALTSEL0_P15) >> 15) & 0x1) -#define PORT_P0_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P15) | (((val) & 0x1) << 15)) -/* Alternate Function at Port 0 Bit # (14) */ -#define PORT_P0_ALTSEL0_P14 (0x1 << 14) -#define PORT_P0_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_ALTSEL0_P14_GET(val) ((((val) & PORT_P0_ALTSEL0_P14) >> 14) & 0x1) -#define PORT_P0_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P14) | (((val) & 0x1) << 14)) -/* Alternate Function at Port 0 Bit # (13) */ -#define PORT_P0_ALTSEL0_P13 (0x1 << 13) -#define PORT_P0_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_ALTSEL0_P13_GET(val) ((((val) & PORT_P0_ALTSEL0_P13) >> 13) & 0x1) -#define PORT_P0_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P13) | (((val) & 0x1) << 13)) -/* Alternate Function at Port 0 Bit # (12) */ -#define PORT_P0_ALTSEL0_P12 (0x1 << 12) -#define PORT_P0_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_ALTSEL0_P12_GET(val) ((((val) & PORT_P0_ALTSEL0_P12) >> 12) & 0x1) -#define PORT_P0_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P12) | (((val) & 0x1) << 12)) -/* Alternate Function at Port 0 Bit # (11) */ -#define PORT_P0_ALTSEL0_P11 (0x1 << 11) -#define PORT_P0_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_ALTSEL0_P11_GET(val) ((((val) & PORT_P0_ALTSEL0_P11) >> 11) & 0x1) -#define PORT_P0_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P11) | (((val) & 0x1) << 11)) -/* Alternate Function at Port 0 Bit # (10) */ -#define PORT_P0_ALTSEL0_P10 (0x1 << 10) -#define PORT_P0_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_ALTSEL0_P10_GET(val) ((((val) & PORT_P0_ALTSEL0_P10) >> 10) & 0x1) -#define PORT_P0_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P10) | (((val) & 0x1) << 10)) -/* Alternate Function at Port 0 Bit # (9) */ -#define PORT_P0_ALTSEL0_P9 (0x1 << 9) -#define PORT_P0_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_ALTSEL0_P9_GET(val) ((((val) & PORT_P0_ALTSEL0_P9) >> 9) & 0x1) -#define PORT_P0_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P9) | (((val) & 0x1) << 9)) -/* Alternate Function at Port 0 Bit # (8) */ -#define PORT_P0_ALTSEL0_P8 (0x1 << 8) -#define PORT_P0_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_ALTSEL0_P8_GET(val) ((((val) & PORT_P0_ALTSEL0_P8) >> 8) & 0x1) -#define PORT_P0_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P8) | (((val) & 0x1) << 8)) -/* Alternate Function at Port 0 Bit # (7) */ -#define PORT_P0_ALTSEL0_P7 (0x1 << 7) -#define PORT_P0_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_ALTSEL0_P7_GET(val) ((((val) & PORT_P0_ALTSEL0_P7) >> 7) & 0x1) -#define PORT_P0_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P7) | (((val) & 0x1) << 7)) -/* Alternate Function at Port 0 Bit # (6) */ -#define PORT_P0_ALTSEL0_P6 (0x1 << 6) -#define PORT_P0_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P0_ALTSEL0_P6_GET(val) ((((val) & PORT_P0_ALTSEL0_P6) >> 6) & 0x1) -#define PORT_P0_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P6) | (((val) & 0x1) << 6)) -/* Alternate Function at Port 0 Bit # (5) */ -#define PORT_P0_ALTSEL0_P5 (0x1 << 5) -#define PORT_P0_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P0_ALTSEL0_P5_GET(val) ((((val) & PORT_P0_ALTSEL0_P5) >> 5) & 0x1) -#define PORT_P0_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P5) | (((val) & 0x1) << 5)) -/* Alternate Function at Port 0 Bit # (4) */ -#define PORT_P0_ALTSEL0_P4 (0x1 << 4) -#define PORT_P0_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P0_ALTSEL0_P4_GET(val) ((((val) & PORT_P0_ALTSEL0_P4) >> 4) & 0x1) -#define PORT_P0_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P4) | (((val) & 0x1) << 4)) -/* Alternate Function at Port 0 Bit # (3) */ -#define PORT_P0_ALTSEL0_P3 (0x1 << 3) -#define PORT_P0_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P0_ALTSEL0_P3_GET(val) ((((val) & PORT_P0_ALTSEL0_P3) >> 3) & 0x1) -#define PORT_P0_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P3) | (((val) & 0x1) << 3)) -/* Alternate Function at Port 0 Bit # (2) */ -#define PORT_P0_ALTSEL0_P2 (0x1 << 2) -#define PORT_P0_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P0_ALTSEL0_P2_GET(val) ((((val) & PORT_P0_ALTSEL0_P2) >> 2) & 0x1) -#define PORT_P0_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P2) | (((val) & 0x1) << 2)) -/* Alternate Function at Port 0 Bit # (1) */ -#define PORT_P0_ALTSEL0_P1 (0x1 << 1) -#define PORT_P0_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P0_ALTSEL0_P1_GET(val) ((((val) & PORT_P0_ALTSEL0_P1) >> 1) & 0x1) -#define PORT_P0_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P1) | (((val) & 0x1) << 1)) -/* Alternate Function at Port 0 Bit # (0) */ -#define PORT_P0_ALTSEL0_P0 (0x1) -#define PORT_P0_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P0_ALTSEL0_P0_GET(val) ((((val) & PORT_P0_ALTSEL0_P0) >> 0) & 0x1) -#define PORT_P0_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 0 Alternate Function Select Register 1 - ******************************************************************************/ - -/* Alternate Function at Port 0 Bit # (13) */ -#define PORT_P0_ALTSEL1_P13 (0x1 << 13) -#define PORT_P0_ALTSEL1_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_ALTSEL1_P13_GET(val) ((((val) & PORT_P0_ALTSEL1_P13) >> 13) & 0x1) -#define PORT_P0_ALTSEL1_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P13) | (((val) & 0x1) << 13)) -/* Alternate Function at Port 0 Bit # (12) */ -#define PORT_P0_ALTSEL1_P12 (0x1 << 12) -#define PORT_P0_ALTSEL1_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_ALTSEL1_P12_GET(val) ((((val) & PORT_P0_ALTSEL1_P12) >> 12) & 0x1) -#define PORT_P0_ALTSEL1_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P12) | (((val) & 0x1) << 12)) -/* Alternate Function at Port 0 Bit # (11) */ -#define PORT_P0_ALTSEL1_P11 (0x1 << 11) -#define PORT_P0_ALTSEL1_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_ALTSEL1_P11_GET(val) ((((val) & PORT_P0_ALTSEL1_P11) >> 11) & 0x1) -#define PORT_P0_ALTSEL1_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P11) | (((val) & 0x1) << 11)) -/* Alternate Function at Port 0 Bit # (10) */ -#define PORT_P0_ALTSEL1_P10 (0x1 << 10) -#define PORT_P0_ALTSEL1_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_ALTSEL1_P10_GET(val) ((((val) & PORT_P0_ALTSEL1_P10) >> 10) & 0x1) -#define PORT_P0_ALTSEL1_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P10) | (((val) & 0x1) << 10)) -/* Alternate Function at Port 0 Bit # (9) */ -#define PORT_P0_ALTSEL1_P9 (0x1 << 9) -#define PORT_P0_ALTSEL1_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_ALTSEL1_P9_GET(val) ((((val) & PORT_P0_ALTSEL1_P9) >> 9) & 0x1) -#define PORT_P0_ALTSEL1_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P9) | (((val) & 0x1) << 9)) -/* Alternate Function at Port 0 Bit # (8) */ -#define PORT_P0_ALTSEL1_P8 (0x1 << 8) -#define PORT_P0_ALTSEL1_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_ALTSEL1_P8_GET(val) ((((val) & PORT_P0_ALTSEL1_P8) >> 8) & 0x1) -#define PORT_P0_ALTSEL1_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P8) | (((val) & 0x1) << 8)) -/* Alternate Function at Port 0 Bit # (7) */ -#define PORT_P0_ALTSEL1_P7 (0x1 << 7) -#define PORT_P0_ALTSEL1_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_ALTSEL1_P7_GET(val) ((((val) & PORT_P0_ALTSEL1_P7) >> 7) & 0x1) -#define PORT_P0_ALTSEL1_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P7) | (((val) & 0x1) << 7)) -/* Alternate Function at Port 0 Bit # (6) */ -#define PORT_P0_ALTSEL1_P6 (0x1 << 6) -#define PORT_P0_ALTSEL1_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P0_ALTSEL1_P6_GET(val) ((((val) & PORT_P0_ALTSEL1_P6) >> 6) & 0x1) -#define PORT_P0_ALTSEL1_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P6) | (((val) & 0x1) << 6)) -/* Alternate Function at Port 0 Bit # (3) */ -#define PORT_P0_ALTSEL1_P3 (0x1 << 3) -#define PORT_P0_ALTSEL1_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P0_ALTSEL1_P3_GET(val) ((((val) & PORT_P0_ALTSEL1_P3) >> 3) & 0x1) -#define PORT_P0_ALTSEL1_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P3) | (((val) & 0x1) << 3)) - -/******************************************************************************* - * Port 0 Pull Up Enable Register - ******************************************************************************/ - -/* Pull Up Device Enable at Port 0 Bit # (19) */ -#define PORT_P0_PUEN_P19 (0x1 << 19) -#define PORT_P0_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_PUEN_P19_GET(val) ((((val) & PORT_P0_PUEN_P19) >> 19) & 0x1) -#define PORT_P0_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P19) | (((val) & 0x1) << 19)) -/* Pull Up Device Enable at Port 0 Bit # (18) */ -#define PORT_P0_PUEN_P18 (0x1 << 18) -#define PORT_P0_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P0_PUEN_P18_GET(val) ((((val) & PORT_P0_PUEN_P18) >> 18) & 0x1) -#define PORT_P0_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P18) | (((val) & 0x1) << 18)) -/* Pull Up Device Enable at Port 0 Bit # (17) */ -#define PORT_P0_PUEN_P17 (0x1 << 17) -#define PORT_P0_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_PUEN_P17_GET(val) ((((val) & PORT_P0_PUEN_P17) >> 17) & 0x1) -#define PORT_P0_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P17) | (((val) & 0x1) << 17)) -/* Pull Up Device Enable at Port 0 Bit # (16) */ -#define PORT_P0_PUEN_P16 (0x1 << 16) -#define PORT_P0_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_PUEN_P16_GET(val) ((((val) & PORT_P0_PUEN_P16) >> 16) & 0x1) -#define PORT_P0_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P16) | (((val) & 0x1) << 16)) -/* Pull Up Device Enable at Port 0 Bit # (15) */ -#define PORT_P0_PUEN_P15 (0x1 << 15) -#define PORT_P0_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_PUEN_P15_GET(val) ((((val) & PORT_P0_PUEN_P15) >> 15) & 0x1) -#define PORT_P0_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P15) | (((val) & 0x1) << 15)) -/* Pull Up Device Enable at Port 0 Bit # (14) */ -#define PORT_P0_PUEN_P14 (0x1 << 14) -#define PORT_P0_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_PUEN_P14_GET(val) ((((val) & PORT_P0_PUEN_P14) >> 14) & 0x1) -#define PORT_P0_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P14) | (((val) & 0x1) << 14)) -/* Pull Up Device Enable at Port 0 Bit # (13) */ -#define PORT_P0_PUEN_P13 (0x1 << 13) -#define PORT_P0_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_PUEN_P13_GET(val) ((((val) & PORT_P0_PUEN_P13) >> 13) & 0x1) -#define PORT_P0_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P13) | (((val) & 0x1) << 13)) -/* Pull Up Device Enable at Port 0 Bit # (12) */ -#define PORT_P0_PUEN_P12 (0x1 << 12) -#define PORT_P0_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_PUEN_P12_GET(val) ((((val) & PORT_P0_PUEN_P12) >> 12) & 0x1) -#define PORT_P0_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P12) | (((val) & 0x1) << 12)) -/* Pull Up Device Enable at Port 0 Bit # (11) */ -#define PORT_P0_PUEN_P11 (0x1 << 11) -#define PORT_P0_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_PUEN_P11_GET(val) ((((val) & PORT_P0_PUEN_P11) >> 11) & 0x1) -#define PORT_P0_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P11) | (((val) & 0x1) << 11)) -/* Pull Up Device Enable at Port 0 Bit # (10) */ -#define PORT_P0_PUEN_P10 (0x1 << 10) -#define PORT_P0_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_PUEN_P10_GET(val) ((((val) & PORT_P0_PUEN_P10) >> 10) & 0x1) -#define PORT_P0_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P10) | (((val) & 0x1) << 10)) -/* Pull Up Device Enable at Port 0 Bit # (9) */ -#define PORT_P0_PUEN_P9 (0x1 << 9) -#define PORT_P0_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_PUEN_P9_GET(val) ((((val) & PORT_P0_PUEN_P9) >> 9) & 0x1) -#define PORT_P0_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P9) | (((val) & 0x1) << 9)) -/* Pull Up Device Enable at Port 0 Bit # (8) */ -#define PORT_P0_PUEN_P8 (0x1 << 8) -#define PORT_P0_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_PUEN_P8_GET(val) ((((val) & PORT_P0_PUEN_P8) >> 8) & 0x1) -#define PORT_P0_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P8) | (((val) & 0x1) << 8)) -/* Pull Up Device Enable at Port 0 Bit # (7) */ -#define PORT_P0_PUEN_P7 (0x1 << 7) -#define PORT_P0_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_PUEN_P7_GET(val) ((((val) & PORT_P0_PUEN_P7) >> 7) & 0x1) -#define PORT_P0_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P7) | (((val) & 0x1) << 7)) -/* Pull Up Device Enable at Port 0 Bit # (6) */ -#define PORT_P0_PUEN_P6 (0x1 << 6) -#define PORT_P0_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P0_PUEN_P6_GET(val) ((((val) & PORT_P0_PUEN_P6) >> 6) & 0x1) -#define PORT_P0_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P6) | (((val) & 0x1) << 6)) -/* Pull Up Device Enable at Port 0 Bit # (5) */ -#define PORT_P0_PUEN_P5 (0x1 << 5) -#define PORT_P0_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P0_PUEN_P5_GET(val) ((((val) & PORT_P0_PUEN_P5) >> 5) & 0x1) -#define PORT_P0_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P5) | (((val) & 0x1) << 5)) -/* Pull Up Device Enable at Port 0 Bit # (4) */ -#define PORT_P0_PUEN_P4 (0x1 << 4) -#define PORT_P0_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P0_PUEN_P4_GET(val) ((((val) & PORT_P0_PUEN_P4) >> 4) & 0x1) -#define PORT_P0_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P4) | (((val) & 0x1) << 4)) -/* Pull Up Device Enable at Port 0 Bit # (3) */ -#define PORT_P0_PUEN_P3 (0x1 << 3) -#define PORT_P0_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P0_PUEN_P3_GET(val) ((((val) & PORT_P0_PUEN_P3) >> 3) & 0x1) -#define PORT_P0_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P3) | (((val) & 0x1) << 3)) -/* Pull Up Device Enable at Port 0 Bit # (2) */ -#define PORT_P0_PUEN_P2 (0x1 << 2) -#define PORT_P0_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P0_PUEN_P2_GET(val) ((((val) & PORT_P0_PUEN_P2) >> 2) & 0x1) -#define PORT_P0_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P2) | (((val) & 0x1) << 2)) -/* Pull Up Device Enable at Port 0 Bit # (1) */ -#define PORT_P0_PUEN_P1 (0x1 << 1) -#define PORT_P0_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P0_PUEN_P1_GET(val) ((((val) & PORT_P0_PUEN_P1) >> 1) & 0x1) -#define PORT_P0_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P1) | (((val) & 0x1) << 1)) -/* Pull Up Device Enable at Port 0 Bit # (0) */ -#define PORT_P0_PUEN_P0 (0x1) -#define PORT_P0_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P0_PUEN_P0_GET(val) ((((val) & PORT_P0_PUEN_P0) >> 0) & 0x1) -#define PORT_P0_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * External Interrupt Control Register 0 - ******************************************************************************/ - -/* Type of Level or Edge Detection of EXINT16 (19) */ -#define PORT_P0_EXINTCR0_EXINT16 (0x1 << 19) -#define PORT_P0_EXINTCR0_EXINT16_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_EXINTCR0_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT16) >> 19) & 0x1) -#define PORT_P0_EXINTCR0_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT16) | (((val) & 0x1) << 19)) -/* Type of Level or Edge Detection of EXINT10 (17) */ -#define PORT_P0_EXINTCR0_EXINT10 (0x1 << 17) -#define PORT_P0_EXINTCR0_EXINT10_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_EXINTCR0_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT10) >> 17) & 0x1) -#define PORT_P0_EXINTCR0_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT10) | (((val) & 0x1) << 17)) -/* Type of Level or Edge Detection of EXINT9 (16) */ -#define PORT_P0_EXINTCR0_EXINT9 (0x1 << 16) -#define PORT_P0_EXINTCR0_EXINT9_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_EXINTCR0_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT9) >> 16) & 0x1) -#define PORT_P0_EXINTCR0_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT9) | (((val) & 0x1) << 16)) -/* Type of Level or Edge Detection of EXINT8 (15) */ -#define PORT_P0_EXINTCR0_EXINT8 (0x1 << 15) -#define PORT_P0_EXINTCR0_EXINT8_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_EXINTCR0_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT8) >> 15) & 0x1) -#define PORT_P0_EXINTCR0_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT8) | (((val) & 0x1) << 15)) -/* Type of Level or Edge Detection of EXINT7 (14) */ -#define PORT_P0_EXINTCR0_EXINT7 (0x1 << 14) -#define PORT_P0_EXINTCR0_EXINT7_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_EXINTCR0_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT7) >> 14) & 0x1) -#define PORT_P0_EXINTCR0_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT7) | (((val) & 0x1) << 14)) -/* Type of Level or Edge Detection of EXINT6 (13) */ -#define PORT_P0_EXINTCR0_EXINT6 (0x1 << 13) -#define PORT_P0_EXINTCR0_EXINT6_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_EXINTCR0_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT6) >> 13) & 0x1) -#define PORT_P0_EXINTCR0_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT6) | (((val) & 0x1) << 13)) -/* Type of Level or Edge Detection of EXINT5 (12) */ -#define PORT_P0_EXINTCR0_EXINT5 (0x1 << 12) -#define PORT_P0_EXINTCR0_EXINT5_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_EXINTCR0_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT5) >> 12) & 0x1) -#define PORT_P0_EXINTCR0_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT5) | (((val) & 0x1) << 12)) -/* Type of Level or Edge Detection of EXINT4 (11) */ -#define PORT_P0_EXINTCR0_EXINT4 (0x1 << 11) -#define PORT_P0_EXINTCR0_EXINT4_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_EXINTCR0_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT4) >> 11) & 0x1) -#define PORT_P0_EXINTCR0_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT4) | (((val) & 0x1) << 11)) -/* Type of Level or Edge Detection of EXINT3 (10) */ -#define PORT_P0_EXINTCR0_EXINT3 (0x1 << 10) -#define PORT_P0_EXINTCR0_EXINT3_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_EXINTCR0_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT3) >> 10) & 0x1) -#define PORT_P0_EXINTCR0_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT3) | (((val) & 0x1) << 10)) -/* Type of Level or Edge Detection of EXINT2 (9) */ -#define PORT_P0_EXINTCR0_EXINT2 (0x1 << 9) -#define PORT_P0_EXINTCR0_EXINT2_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_EXINTCR0_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT2) >> 9) & 0x1) -#define PORT_P0_EXINTCR0_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT2) | (((val) & 0x1) << 9)) -/* Type of Level or Edge Detection of EXINT1 (8) */ -#define PORT_P0_EXINTCR0_EXINT1 (0x1 << 8) -#define PORT_P0_EXINTCR0_EXINT1_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_EXINTCR0_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT1) >> 8) & 0x1) -#define PORT_P0_EXINTCR0_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT1) | (((val) & 0x1) << 8)) -/* Type of Level or Edge Detection of EXINT0 (7) */ -#define PORT_P0_EXINTCR0_EXINT0 (0x1 << 7) -#define PORT_P0_EXINTCR0_EXINT0_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_EXINTCR0_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT0) >> 7) & 0x1) -#define PORT_P0_EXINTCR0_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT0) | (((val) & 0x1) << 7)) - -/******************************************************************************* - * External Interrupt Control Register 1 - ******************************************************************************/ - -/* Type of Level or Edge Detection of EXINT16 (19) */ -#define PORT_P0_EXINTCR1_EXINT16 (0x1 << 19) -#define PORT_P0_EXINTCR1_EXINT16_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_EXINTCR1_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT16) >> 19) & 0x1) -#define PORT_P0_EXINTCR1_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT16) | (((val) & 0x1) << 19)) -/* Type of Level or Edge Detection of EXINT10 (17) */ -#define PORT_P0_EXINTCR1_EXINT10 (0x1 << 17) -#define PORT_P0_EXINTCR1_EXINT10_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_EXINTCR1_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT10) >> 17) & 0x1) -#define PORT_P0_EXINTCR1_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT10) | (((val) & 0x1) << 17)) -/* Type of Level or Edge Detection of EXINT9 (16) */ -#define PORT_P0_EXINTCR1_EXINT9 (0x1 << 16) -#define PORT_P0_EXINTCR1_EXINT9_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_EXINTCR1_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT9) >> 16) & 0x1) -#define PORT_P0_EXINTCR1_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT9) | (((val) & 0x1) << 16)) -/* Type of Level or Edge Detection of EXINT8 (15) */ -#define PORT_P0_EXINTCR1_EXINT8 (0x1 << 15) -#define PORT_P0_EXINTCR1_EXINT8_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_EXINTCR1_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT8) >> 15) & 0x1) -#define PORT_P0_EXINTCR1_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT8) | (((val) & 0x1) << 15)) -/* Type of Level or Edge Detection of EXINT7 (14) */ -#define PORT_P0_EXINTCR1_EXINT7 (0x1 << 14) -#define PORT_P0_EXINTCR1_EXINT7_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_EXINTCR1_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT7) >> 14) & 0x1) -#define PORT_P0_EXINTCR1_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT7) | (((val) & 0x1) << 14)) -/* Type of Level or Edge Detection of EXINT6 (13) */ -#define PORT_P0_EXINTCR1_EXINT6 (0x1 << 13) -#define PORT_P0_EXINTCR1_EXINT6_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_EXINTCR1_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT6) >> 13) & 0x1) -#define PORT_P0_EXINTCR1_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT6) | (((val) & 0x1) << 13)) -/* Type of Level or Edge Detection of EXINT5 (12) */ -#define PORT_P0_EXINTCR1_EXINT5 (0x1 << 12) -#define PORT_P0_EXINTCR1_EXINT5_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_EXINTCR1_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT5) >> 12) & 0x1) -#define PORT_P0_EXINTCR1_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT5) | (((val) & 0x1) << 12)) -/* Type of Level or Edge Detection of EXINT4 (11) */ -#define PORT_P0_EXINTCR1_EXINT4 (0x1 << 11) -#define PORT_P0_EXINTCR1_EXINT4_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_EXINTCR1_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT4) >> 11) & 0x1) -#define PORT_P0_EXINTCR1_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT4) | (((val) & 0x1) << 11)) -/* Type of Level or Edge Detection of EXINT3 (10) */ -#define PORT_P0_EXINTCR1_EXINT3 (0x1 << 10) -#define PORT_P0_EXINTCR1_EXINT3_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_EXINTCR1_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT3) >> 10) & 0x1) -#define PORT_P0_EXINTCR1_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT3) | (((val) & 0x1) << 10)) -/* Type of Level or Edge Detection of EXINT2 (9) */ -#define PORT_P0_EXINTCR1_EXINT2 (0x1 << 9) -#define PORT_P0_EXINTCR1_EXINT2_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_EXINTCR1_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT2) >> 9) & 0x1) -#define PORT_P0_EXINTCR1_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT2) | (((val) & 0x1) << 9)) -/* Type of Level or Edge Detection of EXINT1 (8) */ -#define PORT_P0_EXINTCR1_EXINT1 (0x1 << 8) -#define PORT_P0_EXINTCR1_EXINT1_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_EXINTCR1_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT1) >> 8) & 0x1) -#define PORT_P0_EXINTCR1_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT1) | (((val) & 0x1) << 8)) -/* Type of Level or Edge Detection of EXINT0 (7) */ -#define PORT_P0_EXINTCR1_EXINT0 (0x1 << 7) -#define PORT_P0_EXINTCR1_EXINT0_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_EXINTCR1_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT0) >> 7) & 0x1) -#define PORT_P0_EXINTCR1_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT0) | (((val) & 0x1) << 7)) - -/******************************************************************************* - * P0_IRNEN Register - ******************************************************************************/ - -/* EXINT16 Interrupt Request Enable (19) */ -#define PORT_P0_IRNEN_EXINT16 (0x1 << 19) -#define PORT_P0_IRNEN_EXINT16_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_IRNEN_EXINT16_GET(val) ((((val) & PORT_P0_IRNEN_EXINT16) >> 19) & 0x1) -#define PORT_P0_IRNEN_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT16) | (((val) & 0x1) << 19)) -/* EXINT10 Interrupt Request Enable (17) */ -#define PORT_P0_IRNEN_EXINT10 (0x1 << 17) -#define PORT_P0_IRNEN_EXINT10_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_IRNEN_EXINT10_GET(val) ((((val) & PORT_P0_IRNEN_EXINT10) >> 17) & 0x1) -#define PORT_P0_IRNEN_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT10) | (((val) & 0x1) << 17)) -/* EXINT9 Interrupt Request Enable (16) */ -#define PORT_P0_IRNEN_EXINT9 (0x1 << 16) -#define PORT_P0_IRNEN_EXINT9_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_IRNEN_EXINT9_GET(val) ((((val) & PORT_P0_IRNEN_EXINT9) >> 16) & 0x1) -#define PORT_P0_IRNEN_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT9) | (((val) & 0x1) << 16)) -/* EXINT8 Interrupt Request Enable (15) */ -#define PORT_P0_IRNEN_EXINT8 (0x1 << 15) -#define PORT_P0_IRNEN_EXINT8_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_IRNEN_EXINT8_GET(val) ((((val) & PORT_P0_IRNEN_EXINT8) >> 15) & 0x1) -#define PORT_P0_IRNEN_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT8) | (((val) & 0x1) << 15)) -/* EXINT7 Interrupt Request Enable (14) */ -#define PORT_P0_IRNEN_EXINT7 (0x1 << 14) -#define PORT_P0_IRNEN_EXINT7_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_IRNEN_EXINT7_GET(val) ((((val) & PORT_P0_IRNEN_EXINT7) >> 14) & 0x1) -#define PORT_P0_IRNEN_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT7) | (((val) & 0x1) << 14)) -/* EXINT6 Interrupt Request Enable (13) */ -#define PORT_P0_IRNEN_EXINT6 (0x1 << 13) -#define PORT_P0_IRNEN_EXINT6_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_IRNEN_EXINT6_GET(val) ((((val) & PORT_P0_IRNEN_EXINT6) >> 13) & 0x1) -#define PORT_P0_IRNEN_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT6) | (((val) & 0x1) << 13)) -/* EXINT5 Interrupt Request Enable (12) */ -#define PORT_P0_IRNEN_EXINT5 (0x1 << 12) -#define PORT_P0_IRNEN_EXINT5_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_IRNEN_EXINT5_GET(val) ((((val) & PORT_P0_IRNEN_EXINT5) >> 12) & 0x1) -#define PORT_P0_IRNEN_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT5) | (((val) & 0x1) << 12)) -/* EXINT4 Interrupt Request Enable (11) */ -#define PORT_P0_IRNEN_EXINT4 (0x1 << 11) -#define PORT_P0_IRNEN_EXINT4_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_IRNEN_EXINT4_GET(val) ((((val) & PORT_P0_IRNEN_EXINT4) >> 11) & 0x1) -#define PORT_P0_IRNEN_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT4) | (((val) & 0x1) << 11)) -/* EXINT3 Interrupt Request Enable (10) */ -#define PORT_P0_IRNEN_EXINT3 (0x1 << 10) -#define PORT_P0_IRNEN_EXINT3_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_IRNEN_EXINT3_GET(val) ((((val) & PORT_P0_IRNEN_EXINT3) >> 10) & 0x1) -#define PORT_P0_IRNEN_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT3) | (((val) & 0x1) << 10)) -/* EXINT2 Interrupt Request Enable (9) */ -#define PORT_P0_IRNEN_EXINT2 (0x1 << 9) -#define PORT_P0_IRNEN_EXINT2_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_IRNEN_EXINT2_GET(val) ((((val) & PORT_P0_IRNEN_EXINT2) >> 9) & 0x1) -#define PORT_P0_IRNEN_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT2) | (((val) & 0x1) << 9)) -/* EXINT1 Interrupt Request Enable (8) */ -#define PORT_P0_IRNEN_EXINT1 (0x1 << 8) -#define PORT_P0_IRNEN_EXINT1_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_IRNEN_EXINT1_GET(val) ((((val) & PORT_P0_IRNEN_EXINT1) >> 8) & 0x1) -#define PORT_P0_IRNEN_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT1) | (((val) & 0x1) << 8)) -/* EXINT0 Interrupt Request Enable (7) */ -#define PORT_P0_IRNEN_EXINT0 (0x1 << 7) -#define PORT_P0_IRNEN_EXINT0_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_IRNEN_EXINT0_GET(val) ((((val) & PORT_P0_IRNEN_EXINT0) >> 7) & 0x1) -#define PORT_P0_IRNEN_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT0) | (((val) & 0x1) << 7)) - -/******************************************************************************* - * P0_IRNICR Register - ******************************************************************************/ - -/* EXINT16 Interrupt Request (19) */ -#define PORT_P0_IRNICR_EXINT16 (0x1 << 19) -#define PORT_P0_IRNICR_EXINT16_GET(val) ((((val) & PORT_P0_IRNICR_EXINT16) >> 19) & 0x1) -/* EXINT10 Interrupt Request (17) */ -#define PORT_P0_IRNICR_EXINT10 (0x1 << 17) -#define PORT_P0_IRNICR_EXINT10_GET(val) ((((val) & PORT_P0_IRNICR_EXINT10) >> 17) & 0x1) -/* EXINT9 Interrupt Request (16) */ -#define PORT_P0_IRNICR_EXINT9 (0x1 << 16) -#define PORT_P0_IRNICR_EXINT9_GET(val) ((((val) & PORT_P0_IRNICR_EXINT9) >> 16) & 0x1) -/* EXINT8 Interrupt Request (15) */ -#define PORT_P0_IRNICR_EXINT8 (0x1 << 15) -#define PORT_P0_IRNICR_EXINT8_GET(val) ((((val) & PORT_P0_IRNICR_EXINT8) >> 15) & 0x1) -/* EXINT7 Interrupt Request (14) */ -#define PORT_P0_IRNICR_EXINT7 (0x1 << 14) -#define PORT_P0_IRNICR_EXINT7_GET(val) ((((val) & PORT_P0_IRNICR_EXINT7) >> 14) & 0x1) -/* EXINT6 Interrupt Request (13) */ -#define PORT_P0_IRNICR_EXINT6 (0x1 << 13) -#define PORT_P0_IRNICR_EXINT6_GET(val) ((((val) & PORT_P0_IRNICR_EXINT6) >> 13) & 0x1) -/* EXINT5 Interrupt Request (12) */ -#define PORT_P0_IRNICR_EXINT5 (0x1 << 12) -#define PORT_P0_IRNICR_EXINT5_GET(val) ((((val) & PORT_P0_IRNICR_EXINT5) >> 12) & 0x1) -/* EXINT4 Interrupt Request (11) */ -#define PORT_P0_IRNICR_EXINT4 (0x1 << 11) -#define PORT_P0_IRNICR_EXINT4_GET(val) ((((val) & PORT_P0_IRNICR_EXINT4) >> 11) & 0x1) -/* EXINT3 Interrupt Request (10) */ -#define PORT_P0_IRNICR_EXINT3 (0x1 << 10) -#define PORT_P0_IRNICR_EXINT3_GET(val) ((((val) & PORT_P0_IRNICR_EXINT3) >> 10) & 0x1) -/* EXINT2 Interrupt Request (9) */ -#define PORT_P0_IRNICR_EXINT2 (0x1 << 9) -#define PORT_P0_IRNICR_EXINT2_GET(val) ((((val) & PORT_P0_IRNICR_EXINT2) >> 9) & 0x1) -/* EXINT1 Interrupt Request (8) */ -#define PORT_P0_IRNICR_EXINT1 (0x1 << 8) -#define PORT_P0_IRNICR_EXINT1_GET(val) ((((val) & PORT_P0_IRNICR_EXINT1) >> 8) & 0x1) -/* EXINT0 Interrupt Request (7) */ -#define PORT_P0_IRNICR_EXINT0 (0x1 << 7) -#define PORT_P0_IRNICR_EXINT0_GET(val) ((((val) & PORT_P0_IRNICR_EXINT0) >> 7) & 0x1) - -/******************************************************************************* - * P0_IRNCR Register - ******************************************************************************/ - -/* EXINT16 Interrupt Request (19) */ -#define PORT_P0_IRNCR_EXINT16 (0x1 << 19) -#define PORT_P0_IRNCR_EXINT16_GET(val) ((((val) & PORT_P0_IRNCR_EXINT16) >> 19) & 0x1) -/* EXINT10 Interrupt Request (17) */ -#define PORT_P0_IRNCR_EXINT10 (0x1 << 17) -#define PORT_P0_IRNCR_EXINT10_GET(val) ((((val) & PORT_P0_IRNCR_EXINT10) >> 17) & 0x1) -/* EXINT9 Interrupt Request (16) */ -#define PORT_P0_IRNCR_EXINT9 (0x1 << 16) -#define PORT_P0_IRNCR_EXINT9_GET(val) ((((val) & PORT_P0_IRNCR_EXINT9) >> 16) & 0x1) -/* EXINT8 Interrupt Request (15) */ -#define PORT_P0_IRNCR_EXINT8 (0x1 << 15) -#define PORT_P0_IRNCR_EXINT8_GET(val) ((((val) & PORT_P0_IRNCR_EXINT8) >> 15) & 0x1) -/* EXINT7 Interrupt Request (14) */ -#define PORT_P0_IRNCR_EXINT7 (0x1 << 14) -#define PORT_P0_IRNCR_EXINT7_GET(val) ((((val) & PORT_P0_IRNCR_EXINT7) >> 14) & 0x1) -/* EXINT6 Interrupt Request (13) */ -#define PORT_P0_IRNCR_EXINT6 (0x1 << 13) -#define PORT_P0_IRNCR_EXINT6_GET(val) ((((val) & PORT_P0_IRNCR_EXINT6) >> 13) & 0x1) -/* EXINT5 Interrupt Request (12) */ -#define PORT_P0_IRNCR_EXINT5 (0x1 << 12) -#define PORT_P0_IRNCR_EXINT5_GET(val) ((((val) & PORT_P0_IRNCR_EXINT5) >> 12) & 0x1) -/* EXINT4 Interrupt Request (11) */ -#define PORT_P0_IRNCR_EXINT4 (0x1 << 11) -#define PORT_P0_IRNCR_EXINT4_GET(val) ((((val) & PORT_P0_IRNCR_EXINT4) >> 11) & 0x1) -/* EXINT3 Interrupt Request (10) */ -#define PORT_P0_IRNCR_EXINT3 (0x1 << 10) -#define PORT_P0_IRNCR_EXINT3_GET(val) ((((val) & PORT_P0_IRNCR_EXINT3) >> 10) & 0x1) -/* EXINT2 Interrupt Request (9) */ -#define PORT_P0_IRNCR_EXINT2 (0x1 << 9) -#define PORT_P0_IRNCR_EXINT2_GET(val) ((((val) & PORT_P0_IRNCR_EXINT2) >> 9) & 0x1) -/* EXINT1 Interrupt Request (8) */ -#define PORT_P0_IRNCR_EXINT1 (0x1 << 8) -#define PORT_P0_IRNCR_EXINT1_GET(val) ((((val) & PORT_P0_IRNCR_EXINT1) >> 8) & 0x1) -/* EXINT0 Interrupt Request (7) */ -#define PORT_P0_IRNCR_EXINT0 (0x1 << 7) -#define PORT_P0_IRNCR_EXINT0_GET(val) ((((val) & PORT_P0_IRNCR_EXINT0) >> 7) & 0x1) - -/******************************************************************************* - * P0 External Event Detection Configuration Register - ******************************************************************************/ - -/* EXINT16 configured for Edge or Level Detection (19) */ -#define PORT_P0_IRNCFG_EXINT16 (0x1 << 19) -#define PORT_P0_IRNCFG_EXINT16_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_IRNCFG_EXINT16_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT16) >> 19) & 0x1) -#define PORT_P0_IRNCFG_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT16) | (((val) & 0x1) << 19)) -/* EXINT10 configured for Edge or Level Detection (17) */ -#define PORT_P0_IRNCFG_EXINT10 (0x1 << 17) -#define PORT_P0_IRNCFG_EXINT10_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_IRNCFG_EXINT10_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT10) >> 17) & 0x1) -#define PORT_P0_IRNCFG_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT10) | (((val) & 0x1) << 17)) -/* EXINT9 configured for Edge or Level Detection (16) */ -#define PORT_P0_IRNCFG_EXINT9 (0x1 << 16) -#define PORT_P0_IRNCFG_EXINT9_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_IRNCFG_EXINT9_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT9) >> 16) & 0x1) -#define PORT_P0_IRNCFG_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT9) | (((val) & 0x1) << 16)) -/* EXINT8 configured for Edge or Level Detection (15) */ -#define PORT_P0_IRNCFG_EXINT8 (0x1 << 15) -#define PORT_P0_IRNCFG_EXINT8_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_IRNCFG_EXINT8_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT8) >> 15) & 0x1) -#define PORT_P0_IRNCFG_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT8) | (((val) & 0x1) << 15)) -/* EXINT7 configured for Edge or Level Detection (14) */ -#define PORT_P0_IRNCFG_EXINT7 (0x1 << 14) -#define PORT_P0_IRNCFG_EXINT7_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_IRNCFG_EXINT7_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT7) >> 14) & 0x1) -#define PORT_P0_IRNCFG_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT7) | (((val) & 0x1) << 14)) -/* EXINT6 configured for Edge or Level Detection (13) */ -#define PORT_P0_IRNCFG_EXINT6 (0x1 << 13) -#define PORT_P0_IRNCFG_EXINT6_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_IRNCFG_EXINT6_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT6) >> 13) & 0x1) -#define PORT_P0_IRNCFG_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT6) | (((val) & 0x1) << 13)) -/* EXINT5 configured for Edge or Level Detection (12) */ -#define PORT_P0_IRNCFG_EXINT5 (0x1 << 12) -#define PORT_P0_IRNCFG_EXINT5_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_IRNCFG_EXINT5_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT5) >> 12) & 0x1) -#define PORT_P0_IRNCFG_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT5) | (((val) & 0x1) << 12)) -/* EXINT4 configured for Edge or Level Detection (11) */ -#define PORT_P0_IRNCFG_EXINT4 (0x1 << 11) -#define PORT_P0_IRNCFG_EXINT4_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_IRNCFG_EXINT4_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT4) >> 11) & 0x1) -#define PORT_P0_IRNCFG_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT4) | (((val) & 0x1) << 11)) -/* EXINT3 configured for Edge or Level Detection (10) */ -#define PORT_P0_IRNCFG_EXINT3 (0x1 << 10) -#define PORT_P0_IRNCFG_EXINT3_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_IRNCFG_EXINT3_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT3) >> 10) & 0x1) -#define PORT_P0_IRNCFG_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT3) | (((val) & 0x1) << 10)) -/* EXINT2 configured for Edge or Level Detection (9) */ -#define PORT_P0_IRNCFG_EXINT2 (0x1 << 9) -#define PORT_P0_IRNCFG_EXINT2_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_IRNCFG_EXINT2_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT2) >> 9) & 0x1) -#define PORT_P0_IRNCFG_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT2) | (((val) & 0x1) << 9)) -/* EXINT1 configured for Edge or Level Detection (8) */ -#define PORT_P0_IRNCFG_EXINT1 (0x1 << 8) -#define PORT_P0_IRNCFG_EXINT1_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_IRNCFG_EXINT1_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT1) >> 8) & 0x1) -#define PORT_P0_IRNCFG_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT1) | (((val) & 0x1) << 8)) -/* EXINT0 configured for Edge or Level Detection (7) */ -#define PORT_P0_IRNCFG_EXINT0 (0x1 << 7) -#define PORT_P0_IRNCFG_EXINT0_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_IRNCFG_EXINT0_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT0) >> 7) & 0x1) -#define PORT_P0_IRNCFG_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT0) | (((val) & 0x1) << 7)) - -/******************************************************************************* - * P0_IRNENSET Register - ******************************************************************************/ - -/* Set Interrupt Node Enable Flag EXINT16 (19) */ -#define PORT_P0_IRNENSET_EXINT16 (0x1 << 19) -#define PORT_P0_IRNENSET_EXINT16_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_IRNENSET_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT16) | (val) & 1) << 19) -/* Set Interrupt Node Enable Flag EXINT10 (17) */ -#define PORT_P0_IRNENSET_EXINT10 (0x1 << 17) -#define PORT_P0_IRNENSET_EXINT10_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_IRNENSET_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT10) | (val) & 1) << 17) -/* Set Interrupt Node Enable Flag EXINT9 (16) */ -#define PORT_P0_IRNENSET_EXINT9 (0x1 << 16) -#define PORT_P0_IRNENSET_EXINT9_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_IRNENSET_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT9) | (val) & 1) << 16) -/* Set Interrupt Node Enable Flag EXINT8 (15) */ -#define PORT_P0_IRNENSET_EXINT8 (0x1 << 15) -#define PORT_P0_IRNENSET_EXINT8_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_IRNENSET_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT8) | (val) & 1) << 15) -/* Set Interrupt Node Enable Flag EXINT7 (14) */ -#define PORT_P0_IRNENSET_EXINT7 (0x1 << 14) -#define PORT_P0_IRNENSET_EXINT7_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_IRNENSET_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT7) | (val) & 1) << 14) -/* Set Interrupt Node Enable Flag EXINT6 (13) */ -#define PORT_P0_IRNENSET_EXINT6 (0x1 << 13) -#define PORT_P0_IRNENSET_EXINT6_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_IRNENSET_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT6) | (val) & 1) << 13) -/* Set Interrupt Node Enable Flag EXINT5 (12) */ -#define PORT_P0_IRNENSET_EXINT5 (0x1 << 12) -#define PORT_P0_IRNENSET_EXINT5_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_IRNENSET_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT5) | (val) & 1) << 12) -/* Set Interrupt Node Enable Flag EXINT4 (11) */ -#define PORT_P0_IRNENSET_EXINT4 (0x1 << 11) -#define PORT_P0_IRNENSET_EXINT4_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_IRNENSET_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT4) | (val) & 1) << 11) -/* Set Interrupt Node Enable Flag EXINT3 (10) */ -#define PORT_P0_IRNENSET_EXINT3 (0x1 << 10) -#define PORT_P0_IRNENSET_EXINT3_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_IRNENSET_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT3) | (val) & 1) << 10) -/* Set Interrupt Node Enable Flag EXINT2 (9) */ -#define PORT_P0_IRNENSET_EXINT2 (0x1 << 9) -#define PORT_P0_IRNENSET_EXINT2_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_IRNENSET_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT2) | (val) & 1) << 9) -/* Set Interrupt Node Enable Flag EXINT1 (8) */ -#define PORT_P0_IRNENSET_EXINT1 (0x1 << 8) -#define PORT_P0_IRNENSET_EXINT1_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_IRNENSET_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT1) | (val) & 1) << 8) -/* Set Interrupt Node Enable Flag EXINT0 (7) */ -#define PORT_P0_IRNENSET_EXINT0 (0x1 << 7) -#define PORT_P0_IRNENSET_EXINT0_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_IRNENSET_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT0) | (val) & 1) << 7) - -/******************************************************************************* - * P0_IRNENCLR Register - ******************************************************************************/ - -/* Clear Interrupt Node Enable Flag EXINT16 (19) */ -#define PORT_P0_IRNENCLR_EXINT16 (0x1 << 19) -#define PORT_P0_IRNENCLR_EXINT16_VAL(val) (((val) & 0x1) << 19) -#define PORT_P0_IRNENCLR_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT16) | (val) & 1) << 19) -/* Clear Interrupt Node Enable Flag EXINT10 (17) */ -#define PORT_P0_IRNENCLR_EXINT10 (0x1 << 17) -#define PORT_P0_IRNENCLR_EXINT10_VAL(val) (((val) & 0x1) << 17) -#define PORT_P0_IRNENCLR_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT10) | (val) & 1) << 17) -/* Clear Interrupt Node Enable Flag EXINT9 (16) */ -#define PORT_P0_IRNENCLR_EXINT9 (0x1 << 16) -#define PORT_P0_IRNENCLR_EXINT9_VAL(val) (((val) & 0x1) << 16) -#define PORT_P0_IRNENCLR_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT9) | (val) & 1) << 16) -/* Clear Interrupt Node Enable Flag EXINT8 (15) */ -#define PORT_P0_IRNENCLR_EXINT8 (0x1 << 15) -#define PORT_P0_IRNENCLR_EXINT8_VAL(val) (((val) & 0x1) << 15) -#define PORT_P0_IRNENCLR_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT8) | (val) & 1) << 15) -/* Clear Interrupt Node Enable Flag EXINT7 (14) */ -#define PORT_P0_IRNENCLR_EXINT7 (0x1 << 14) -#define PORT_P0_IRNENCLR_EXINT7_VAL(val) (((val) & 0x1) << 14) -#define PORT_P0_IRNENCLR_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT7) | (val) & 1) << 14) -/* Clear Interrupt Node Enable Flag EXINT6 (13) */ -#define PORT_P0_IRNENCLR_EXINT6 (0x1 << 13) -#define PORT_P0_IRNENCLR_EXINT6_VAL(val) (((val) & 0x1) << 13) -#define PORT_P0_IRNENCLR_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT6) | (val) & 1) << 13) -/* Clear Interrupt Node Enable Flag EXINT5 (12) */ -#define PORT_P0_IRNENCLR_EXINT5 (0x1 << 12) -#define PORT_P0_IRNENCLR_EXINT5_VAL(val) (((val) & 0x1) << 12) -#define PORT_P0_IRNENCLR_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT5) | (val) & 1) << 12) -/* Clear Interrupt Node Enable Flag EXINT4 (11) */ -#define PORT_P0_IRNENCLR_EXINT4 (0x1 << 11) -#define PORT_P0_IRNENCLR_EXINT4_VAL(val) (((val) & 0x1) << 11) -#define PORT_P0_IRNENCLR_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT4) | (val) & 1) << 11) -/* Clear Interrupt Node Enable Flag EXINT3 (10) */ -#define PORT_P0_IRNENCLR_EXINT3 (0x1 << 10) -#define PORT_P0_IRNENCLR_EXINT3_VAL(val) (((val) & 0x1) << 10) -#define PORT_P0_IRNENCLR_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT3) | (val) & 1) << 10) -/* Clear Interrupt Node Enable Flag EXINT2 (9) */ -#define PORT_P0_IRNENCLR_EXINT2 (0x1 << 9) -#define PORT_P0_IRNENCLR_EXINT2_VAL(val) (((val) & 0x1) << 9) -#define PORT_P0_IRNENCLR_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT2) | (val) & 1) << 9) -/* Clear Interrupt Node Enable Flag EXINT1 (8) */ -#define PORT_P0_IRNENCLR_EXINT1 (0x1 << 8) -#define PORT_P0_IRNENCLR_EXINT1_VAL(val) (((val) & 0x1) << 8) -#define PORT_P0_IRNENCLR_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT1) | (val) & 1) << 8) -/* Clear Interrupt Node Enable Flag EXINT0 (7) */ -#define PORT_P0_IRNENCLR_EXINT0 (0x1 << 7) -#define PORT_P0_IRNENCLR_EXINT0_VAL(val) (((val) & 0x1) << 7) -#define PORT_P0_IRNENCLR_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT0) | (val) & 1) << 7) - -/******************************************************************************* - * Port 1 Data Output Register - ******************************************************************************/ - -/* Port 1 Pin # Output Value (19) */ -#define PORT_P1_OUT_P19 (0x1 << 19) -#define PORT_P1_OUT_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_OUT_P19_GET(val) ((((val) & PORT_P1_OUT_P19) >> 19) & 0x1) -#define PORT_P1_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P19) | (((val) & 0x1) << 19)) -/* Port 1 Pin # Output Value (18) */ -#define PORT_P1_OUT_P18 (0x1 << 18) -#define PORT_P1_OUT_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_OUT_P18_GET(val) ((((val) & PORT_P1_OUT_P18) >> 18) & 0x1) -#define PORT_P1_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P18) | (((val) & 0x1) << 18)) -/* Port 1 Pin # Output Value (17) */ -#define PORT_P1_OUT_P17 (0x1 << 17) -#define PORT_P1_OUT_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_OUT_P17_GET(val) ((((val) & PORT_P1_OUT_P17) >> 17) & 0x1) -#define PORT_P1_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P17) | (((val) & 0x1) << 17)) -/* Port 1 Pin # Output Value (16) */ -#define PORT_P1_OUT_P16 (0x1 << 16) -#define PORT_P1_OUT_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_OUT_P16_GET(val) ((((val) & PORT_P1_OUT_P16) >> 16) & 0x1) -#define PORT_P1_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P16) | (((val) & 0x1) << 16)) -/* Port 1 Pin # Output Value (15) */ -#define PORT_P1_OUT_P15 (0x1 << 15) -#define PORT_P1_OUT_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_OUT_P15_GET(val) ((((val) & PORT_P1_OUT_P15) >> 15) & 0x1) -#define PORT_P1_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P15) | (((val) & 0x1) << 15)) -/* Port 1 Pin # Output Value (14) */ -#define PORT_P1_OUT_P14 (0x1 << 14) -#define PORT_P1_OUT_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P1_OUT_P14_GET(val) ((((val) & PORT_P1_OUT_P14) >> 14) & 0x1) -#define PORT_P1_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P14) | (((val) & 0x1) << 14)) -/* Port 1 Pin # Output Value (13) */ -#define PORT_P1_OUT_P13 (0x1 << 13) -#define PORT_P1_OUT_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P1_OUT_P13_GET(val) ((((val) & PORT_P1_OUT_P13) >> 13) & 0x1) -#define PORT_P1_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P13) | (((val) & 0x1) << 13)) -/* Port 1 Pin # Output Value (12) */ -#define PORT_P1_OUT_P12 (0x1 << 12) -#define PORT_P1_OUT_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P1_OUT_P12_GET(val) ((((val) & PORT_P1_OUT_P12) >> 12) & 0x1) -#define PORT_P1_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P12) | (((val) & 0x1) << 12)) -/* Port 1 Pin # Output Value (11) */ -#define PORT_P1_OUT_P11 (0x1 << 11) -#define PORT_P1_OUT_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P1_OUT_P11_GET(val) ((((val) & PORT_P1_OUT_P11) >> 11) & 0x1) -#define PORT_P1_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P11) | (((val) & 0x1) << 11)) -/* Port 1 Pin # Output Value (10) */ -#define PORT_P1_OUT_P10 (0x1 << 10) -#define PORT_P1_OUT_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P1_OUT_P10_GET(val) ((((val) & PORT_P1_OUT_P10) >> 10) & 0x1) -#define PORT_P1_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P10) | (((val) & 0x1) << 10)) -/* Port 1 Pin # Output Value (9) */ -#define PORT_P1_OUT_P9 (0x1 << 9) -#define PORT_P1_OUT_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P1_OUT_P9_GET(val) ((((val) & PORT_P1_OUT_P9) >> 9) & 0x1) -#define PORT_P1_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P9) | (((val) & 0x1) << 9)) -/* Port 1 Pin # Output Value (8) */ -#define PORT_P1_OUT_P8 (0x1 << 8) -#define PORT_P1_OUT_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P1_OUT_P8_GET(val) ((((val) & PORT_P1_OUT_P8) >> 8) & 0x1) -#define PORT_P1_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P8) | (((val) & 0x1) << 8)) -/* Port 1 Pin # Output Value (7) */ -#define PORT_P1_OUT_P7 (0x1 << 7) -#define PORT_P1_OUT_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P1_OUT_P7_GET(val) ((((val) & PORT_P1_OUT_P7) >> 7) & 0x1) -#define PORT_P1_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P7) | (((val) & 0x1) << 7)) -/* Port 1 Pin # Output Value (6) */ -#define PORT_P1_OUT_P6 (0x1 << 6) -#define PORT_P1_OUT_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P1_OUT_P6_GET(val) ((((val) & PORT_P1_OUT_P6) >> 6) & 0x1) -#define PORT_P1_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P6) | (((val) & 0x1) << 6)) -/* Port 1 Pin # Output Value (5) */ -#define PORT_P1_OUT_P5 (0x1 << 5) -#define PORT_P1_OUT_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P1_OUT_P5_GET(val) ((((val) & PORT_P1_OUT_P5) >> 5) & 0x1) -#define PORT_P1_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P5) | (((val) & 0x1) << 5)) -/* Port 1 Pin # Output Value (4) */ -#define PORT_P1_OUT_P4 (0x1 << 4) -#define PORT_P1_OUT_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P1_OUT_P4_GET(val) ((((val) & PORT_P1_OUT_P4) >> 4) & 0x1) -#define PORT_P1_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P4) | (((val) & 0x1) << 4)) -/* Port 1 Pin # Output Value (3) */ -#define PORT_P1_OUT_P3 (0x1 << 3) -#define PORT_P1_OUT_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P1_OUT_P3_GET(val) ((((val) & PORT_P1_OUT_P3) >> 3) & 0x1) -#define PORT_P1_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P3) | (((val) & 0x1) << 3)) -/* Port 1 Pin # Output Value (2) */ -#define PORT_P1_OUT_P2 (0x1 << 2) -#define PORT_P1_OUT_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P1_OUT_P2_GET(val) ((((val) & PORT_P1_OUT_P2) >> 2) & 0x1) -#define PORT_P1_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P2) | (((val) & 0x1) << 2)) -/* Port 1 Pin # Output Value (1) */ -#define PORT_P1_OUT_P1 (0x1 << 1) -#define PORT_P1_OUT_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P1_OUT_P1_GET(val) ((((val) & PORT_P1_OUT_P1) >> 1) & 0x1) -#define PORT_P1_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P1) | (((val) & 0x1) << 1)) -/* Port 1 Pin # Output Value (0) */ -#define PORT_P1_OUT_P0 (0x1) -#define PORT_P1_OUT_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P1_OUT_P0_GET(val) ((((val) & PORT_P1_OUT_P0) >> 0) & 0x1) -#define PORT_P1_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 1 Data Input Register - ******************************************************************************/ - -/* Port 1 Pin # Latched Input Value (19) */ -#define PORT_P1_IN_P19 (0x1 << 19) -#define PORT_P1_IN_P19_GET(val) ((((val) & PORT_P1_IN_P19) >> 19) & 0x1) -/* Port 1 Pin # Latched Input Value (18) */ -#define PORT_P1_IN_P18 (0x1 << 18) -#define PORT_P1_IN_P18_GET(val) ((((val) & PORT_P1_IN_P18) >> 18) & 0x1) -/* Port 1 Pin # Latched Input Value (17) */ -#define PORT_P1_IN_P17 (0x1 << 17) -#define PORT_P1_IN_P17_GET(val) ((((val) & PORT_P1_IN_P17) >> 17) & 0x1) -/* Port 1 Pin # Latched Input Value (16) */ -#define PORT_P1_IN_P16 (0x1 << 16) -#define PORT_P1_IN_P16_GET(val) ((((val) & PORT_P1_IN_P16) >> 16) & 0x1) -/* Port 1 Pin # Latched Input Value (15) */ -#define PORT_P1_IN_P15 (0x1 << 15) -#define PORT_P1_IN_P15_GET(val) ((((val) & PORT_P1_IN_P15) >> 15) & 0x1) -/* Port 1 Pin # Latched Input Value (14) */ -#define PORT_P1_IN_P14 (0x1 << 14) -#define PORT_P1_IN_P14_GET(val) ((((val) & PORT_P1_IN_P14) >> 14) & 0x1) -/* Port 1 Pin # Latched Input Value (13) */ -#define PORT_P1_IN_P13 (0x1 << 13) -#define PORT_P1_IN_P13_GET(val) ((((val) & PORT_P1_IN_P13) >> 13) & 0x1) -/* Port 1 Pin # Latched Input Value (12) */ -#define PORT_P1_IN_P12 (0x1 << 12) -#define PORT_P1_IN_P12_GET(val) ((((val) & PORT_P1_IN_P12) >> 12) & 0x1) -/* Port 1 Pin # Latched Input Value (11) */ -#define PORT_P1_IN_P11 (0x1 << 11) -#define PORT_P1_IN_P11_GET(val) ((((val) & PORT_P1_IN_P11) >> 11) & 0x1) -/* Port 1 Pin # Latched Input Value (10) */ -#define PORT_P1_IN_P10 (0x1 << 10) -#define PORT_P1_IN_P10_GET(val) ((((val) & PORT_P1_IN_P10) >> 10) & 0x1) -/* Port 1 Pin # Latched Input Value (9) */ -#define PORT_P1_IN_P9 (0x1 << 9) -#define PORT_P1_IN_P9_GET(val) ((((val) & PORT_P1_IN_P9) >> 9) & 0x1) -/* Port 1 Pin # Latched Input Value (8) */ -#define PORT_P1_IN_P8 (0x1 << 8) -#define PORT_P1_IN_P8_GET(val) ((((val) & PORT_P1_IN_P8) >> 8) & 0x1) -/* Port 1 Pin # Latched Input Value (7) */ -#define PORT_P1_IN_P7 (0x1 << 7) -#define PORT_P1_IN_P7_GET(val) ((((val) & PORT_P1_IN_P7) >> 7) & 0x1) -/* Port 1 Pin # Latched Input Value (6) */ -#define PORT_P1_IN_P6 (0x1 << 6) -#define PORT_P1_IN_P6_GET(val) ((((val) & PORT_P1_IN_P6) >> 6) & 0x1) -/* Port 1 Pin # Latched Input Value (5) */ -#define PORT_P1_IN_P5 (0x1 << 5) -#define PORT_P1_IN_P5_GET(val) ((((val) & PORT_P1_IN_P5) >> 5) & 0x1) -/* Port 1 Pin # Latched Input Value (4) */ -#define PORT_P1_IN_P4 (0x1 << 4) -#define PORT_P1_IN_P4_GET(val) ((((val) & PORT_P1_IN_P4) >> 4) & 0x1) -/* Port 1 Pin # Latched Input Value (3) */ -#define PORT_P1_IN_P3 (0x1 << 3) -#define PORT_P1_IN_P3_GET(val) ((((val) & PORT_P1_IN_P3) >> 3) & 0x1) -/* Port 1 Pin # Latched Input Value (2) */ -#define PORT_P1_IN_P2 (0x1 << 2) -#define PORT_P1_IN_P2_GET(val) ((((val) & PORT_P1_IN_P2) >> 2) & 0x1) -/* Port 1 Pin # Latched Input Value (1) */ -#define PORT_P1_IN_P1 (0x1 << 1) -#define PORT_P1_IN_P1_GET(val) ((((val) & PORT_P1_IN_P1) >> 1) & 0x1) -/* Port 1 Pin # Latched Input Value (0) */ -#define PORT_P1_IN_P0 (0x1) -#define PORT_P1_IN_P0_GET(val) ((((val) & PORT_P1_IN_P0) >> 0) & 0x1) - -/******************************************************************************* - * Port 1 Direction Register - ******************************************************************************/ - -/* Port 1 Pin #Direction Control (19) */ -#define PORT_P1_DIR_P19 (0x1 << 19) -#define PORT_P1_DIR_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_DIR_P19_GET(val) ((((val) & PORT_P1_DIR_P19) >> 19) & 0x1) -#define PORT_P1_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P19) | (((val) & 0x1) << 19)) -/* Port 1 Pin #Direction Control (18) */ -#define PORT_P1_DIR_P18 (0x1 << 18) -#define PORT_P1_DIR_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_DIR_P18_GET(val) ((((val) & PORT_P1_DIR_P18) >> 18) & 0x1) -#define PORT_P1_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P18) | (((val) & 0x1) << 18)) -/* Port 1 Pin #Direction Control (17) */ -#define PORT_P1_DIR_P17 (0x1 << 17) -#define PORT_P1_DIR_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_DIR_P17_GET(val) ((((val) & PORT_P1_DIR_P17) >> 17) & 0x1) -#define PORT_P1_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P17) | (((val) & 0x1) << 17)) -/* Port 1 Pin #Direction Control (16) */ -#define PORT_P1_DIR_P16 (0x1 << 16) -#define PORT_P1_DIR_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_DIR_P16_GET(val) ((((val) & PORT_P1_DIR_P16) >> 16) & 0x1) -#define PORT_P1_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P16) | (((val) & 0x1) << 16)) -/* Port 1 Pin #Direction Control (15) */ -#define PORT_P1_DIR_P15 (0x1 << 15) -#define PORT_P1_DIR_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_DIR_P15_GET(val) ((((val) & PORT_P1_DIR_P15) >> 15) & 0x1) -#define PORT_P1_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P15) | (((val) & 0x1) << 15)) -/* Port 1 Pin #Direction Control (14) */ -#define PORT_P1_DIR_P14 (0x1 << 14) -#define PORT_P1_DIR_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P1_DIR_P14_GET(val) ((((val) & PORT_P1_DIR_P14) >> 14) & 0x1) -#define PORT_P1_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P14) | (((val) & 0x1) << 14)) -/* Port 1 Pin #Direction Control (13) */ -#define PORT_P1_DIR_P13 (0x1 << 13) -#define PORT_P1_DIR_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P1_DIR_P13_GET(val) ((((val) & PORT_P1_DIR_P13) >> 13) & 0x1) -#define PORT_P1_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P13) | (((val) & 0x1) << 13)) -/* Port 1 Pin #Direction Control (12) */ -#define PORT_P1_DIR_P12 (0x1 << 12) -#define PORT_P1_DIR_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P1_DIR_P12_GET(val) ((((val) & PORT_P1_DIR_P12) >> 12) & 0x1) -#define PORT_P1_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P12) | (((val) & 0x1) << 12)) -/* Port 1 Pin #Direction Control (11) */ -#define PORT_P1_DIR_P11 (0x1 << 11) -#define PORT_P1_DIR_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P1_DIR_P11_GET(val) ((((val) & PORT_P1_DIR_P11) >> 11) & 0x1) -#define PORT_P1_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P11) | (((val) & 0x1) << 11)) -/* Port 1 Pin #Direction Control (10) */ -#define PORT_P1_DIR_P10 (0x1 << 10) -#define PORT_P1_DIR_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P1_DIR_P10_GET(val) ((((val) & PORT_P1_DIR_P10) >> 10) & 0x1) -#define PORT_P1_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P10) | (((val) & 0x1) << 10)) -/* Port 1 Pin #Direction Control (9) */ -#define PORT_P1_DIR_P9 (0x1 << 9) -#define PORT_P1_DIR_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P1_DIR_P9_GET(val) ((((val) & PORT_P1_DIR_P9) >> 9) & 0x1) -#define PORT_P1_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P9) | (((val) & 0x1) << 9)) -/* Port 1 Pin #Direction Control (8) */ -#define PORT_P1_DIR_P8 (0x1 << 8) -#define PORT_P1_DIR_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P1_DIR_P8_GET(val) ((((val) & PORT_P1_DIR_P8) >> 8) & 0x1) -#define PORT_P1_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P8) | (((val) & 0x1) << 8)) -/* Port 1 Pin #Direction Control (7) */ -#define PORT_P1_DIR_P7 (0x1 << 7) -#define PORT_P1_DIR_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P1_DIR_P7_GET(val) ((((val) & PORT_P1_DIR_P7) >> 7) & 0x1) -#define PORT_P1_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P7) | (((val) & 0x1) << 7)) -/* Port 1 Pin #Direction Control (6) */ -#define PORT_P1_DIR_P6 (0x1 << 6) -#define PORT_P1_DIR_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P1_DIR_P6_GET(val) ((((val) & PORT_P1_DIR_P6) >> 6) & 0x1) -#define PORT_P1_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P6) | (((val) & 0x1) << 6)) -/* Port 1 Pin #Direction Control (5) */ -#define PORT_P1_DIR_P5 (0x1 << 5) -#define PORT_P1_DIR_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P1_DIR_P5_GET(val) ((((val) & PORT_P1_DIR_P5) >> 5) & 0x1) -#define PORT_P1_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P5) | (((val) & 0x1) << 5)) -/* Port 1 Pin #Direction Control (4) */ -#define PORT_P1_DIR_P4 (0x1 << 4) -#define PORT_P1_DIR_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P1_DIR_P4_GET(val) ((((val) & PORT_P1_DIR_P4) >> 4) & 0x1) -#define PORT_P1_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P4) | (((val) & 0x1) << 4)) -/* Port 1 Pin #Direction Control (3) */ -#define PORT_P1_DIR_P3 (0x1 << 3) -#define PORT_P1_DIR_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P1_DIR_P3_GET(val) ((((val) & PORT_P1_DIR_P3) >> 3) & 0x1) -#define PORT_P1_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P3) | (((val) & 0x1) << 3)) -/* Port 1 Pin #Direction Control (2) */ -#define PORT_P1_DIR_P2 (0x1 << 2) -#define PORT_P1_DIR_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P1_DIR_P2_GET(val) ((((val) & PORT_P1_DIR_P2) >> 2) & 0x1) -#define PORT_P1_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P2) | (((val) & 0x1) << 2)) -/* Port 1 Pin #Direction Control (1) */ -#define PORT_P1_DIR_P1 (0x1 << 1) -#define PORT_P1_DIR_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P1_DIR_P1_GET(val) ((((val) & PORT_P1_DIR_P1) >> 1) & 0x1) -#define PORT_P1_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P1) | (((val) & 0x1) << 1)) -/* Port 1 Pin #Direction Control (0) */ -#define PORT_P1_DIR_P0 (0x1) -#define PORT_P1_DIR_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P1_DIR_P0_GET(val) ((((val) & PORT_P1_DIR_P0) >> 0) & 0x1) -#define PORT_P1_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 1 Alternate Function Select Register 0 - ******************************************************************************/ - -/* Alternate Function at Port 1 Bit # (19) */ -#define PORT_P1_ALTSEL0_P19 (0x1 << 19) -#define PORT_P1_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_ALTSEL0_P19_GET(val) ((((val) & PORT_P1_ALTSEL0_P19) >> 19) & 0x1) -#define PORT_P1_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P19) | (((val) & 0x1) << 19)) -/* Alternate Function at Port 1 Bit # (18) */ -#define PORT_P1_ALTSEL0_P18 (0x1 << 18) -#define PORT_P1_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_ALTSEL0_P18_GET(val) ((((val) & PORT_P1_ALTSEL0_P18) >> 18) & 0x1) -#define PORT_P1_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P18) | (((val) & 0x1) << 18)) -/* Alternate Function at Port 1 Bit # (17) */ -#define PORT_P1_ALTSEL0_P17 (0x1 << 17) -#define PORT_P1_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_ALTSEL0_P17_GET(val) ((((val) & PORT_P1_ALTSEL0_P17) >> 17) & 0x1) -#define PORT_P1_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P17) | (((val) & 0x1) << 17)) -/* Alternate Function at Port 1 Bit # (16) */ -#define PORT_P1_ALTSEL0_P16 (0x1 << 16) -#define PORT_P1_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_ALTSEL0_P16_GET(val) ((((val) & PORT_P1_ALTSEL0_P16) >> 16) & 0x1) -#define PORT_P1_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P16) | (((val) & 0x1) << 16)) -/* Alternate Function at Port 1 Bit # (15) */ -#define PORT_P1_ALTSEL0_P15 (0x1 << 15) -#define PORT_P1_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_ALTSEL0_P15_GET(val) ((((val) & PORT_P1_ALTSEL0_P15) >> 15) & 0x1) -#define PORT_P1_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P15) | (((val) & 0x1) << 15)) -/* Alternate Function at Port 1 Bit # (14) */ -#define PORT_P1_ALTSEL0_P14 (0x1 << 14) -#define PORT_P1_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P1_ALTSEL0_P14_GET(val) ((((val) & PORT_P1_ALTSEL0_P14) >> 14) & 0x1) -#define PORT_P1_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P14) | (((val) & 0x1) << 14)) -/* Alternate Function at Port 1 Bit # (13) */ -#define PORT_P1_ALTSEL0_P13 (0x1 << 13) -#define PORT_P1_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P1_ALTSEL0_P13_GET(val) ((((val) & PORT_P1_ALTSEL0_P13) >> 13) & 0x1) -#define PORT_P1_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P13) | (((val) & 0x1) << 13)) -/* Alternate Function at Port 1 Bit # (12) */ -#define PORT_P1_ALTSEL0_P12 (0x1 << 12) -#define PORT_P1_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P1_ALTSEL0_P12_GET(val) ((((val) & PORT_P1_ALTSEL0_P12) >> 12) & 0x1) -#define PORT_P1_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P12) | (((val) & 0x1) << 12)) -/* Alternate Function at Port 1 Bit # (11) */ -#define PORT_P1_ALTSEL0_P11 (0x1 << 11) -#define PORT_P1_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P1_ALTSEL0_P11_GET(val) ((((val) & PORT_P1_ALTSEL0_P11) >> 11) & 0x1) -#define PORT_P1_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P11) | (((val) & 0x1) << 11)) -/* Alternate Function at Port 1 Bit # (10) */ -#define PORT_P1_ALTSEL0_P10 (0x1 << 10) -#define PORT_P1_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P1_ALTSEL0_P10_GET(val) ((((val) & PORT_P1_ALTSEL0_P10) >> 10) & 0x1) -#define PORT_P1_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P10) | (((val) & 0x1) << 10)) -/* Alternate Function at Port 1 Bit # (9) */ -#define PORT_P1_ALTSEL0_P9 (0x1 << 9) -#define PORT_P1_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P1_ALTSEL0_P9_GET(val) ((((val) & PORT_P1_ALTSEL0_P9) >> 9) & 0x1) -#define PORT_P1_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P9) | (((val) & 0x1) << 9)) -/* Alternate Function at Port 1 Bit # (8) */ -#define PORT_P1_ALTSEL0_P8 (0x1 << 8) -#define PORT_P1_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P1_ALTSEL0_P8_GET(val) ((((val) & PORT_P1_ALTSEL0_P8) >> 8) & 0x1) -#define PORT_P1_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P8) | (((val) & 0x1) << 8)) -/* Alternate Function at Port 1 Bit # (7) */ -#define PORT_P1_ALTSEL0_P7 (0x1 << 7) -#define PORT_P1_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P1_ALTSEL0_P7_GET(val) ((((val) & PORT_P1_ALTSEL0_P7) >> 7) & 0x1) -#define PORT_P1_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P7) | (((val) & 0x1) << 7)) -/* Alternate Function at Port 1 Bit # (6) */ -#define PORT_P1_ALTSEL0_P6 (0x1 << 6) -#define PORT_P1_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P1_ALTSEL0_P6_GET(val) ((((val) & PORT_P1_ALTSEL0_P6) >> 6) & 0x1) -#define PORT_P1_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P6) | (((val) & 0x1) << 6)) -/* Alternate Function at Port 1 Bit # (5) */ -#define PORT_P1_ALTSEL0_P5 (0x1 << 5) -#define PORT_P1_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P1_ALTSEL0_P5_GET(val) ((((val) & PORT_P1_ALTSEL0_P5) >> 5) & 0x1) -#define PORT_P1_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P5) | (((val) & 0x1) << 5)) -/* Alternate Function at Port 1 Bit # (4) */ -#define PORT_P1_ALTSEL0_P4 (0x1 << 4) -#define PORT_P1_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P1_ALTSEL0_P4_GET(val) ((((val) & PORT_P1_ALTSEL0_P4) >> 4) & 0x1) -#define PORT_P1_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P4) | (((val) & 0x1) << 4)) -/* Alternate Function at Port 1 Bit # (3) */ -#define PORT_P1_ALTSEL0_P3 (0x1 << 3) -#define PORT_P1_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P1_ALTSEL0_P3_GET(val) ((((val) & PORT_P1_ALTSEL0_P3) >> 3) & 0x1) -#define PORT_P1_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P3) | (((val) & 0x1) << 3)) -/* Alternate Function at Port 1 Bit # (2) */ -#define PORT_P1_ALTSEL0_P2 (0x1 << 2) -#define PORT_P1_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P1_ALTSEL0_P2_GET(val) ((((val) & PORT_P1_ALTSEL0_P2) >> 2) & 0x1) -#define PORT_P1_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P2) | (((val) & 0x1) << 2)) -/* Alternate Function at Port 1 Bit # (1) */ -#define PORT_P1_ALTSEL0_P1 (0x1 << 1) -#define PORT_P1_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P1_ALTSEL0_P1_GET(val) ((((val) & PORT_P1_ALTSEL0_P1) >> 1) & 0x1) -#define PORT_P1_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P1) | (((val) & 0x1) << 1)) -/* Alternate Function at Port 1 Bit # (0) */ -#define PORT_P1_ALTSEL0_P0 (0x1) -#define PORT_P1_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P1_ALTSEL0_P0_GET(val) ((((val) & PORT_P1_ALTSEL0_P0) >> 0) & 0x1) -#define PORT_P1_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 1 Pull Up Device Enable Register - ******************************************************************************/ - -/* Pull Up Device Enable at Port 1 Bit # (19) */ -#define PORT_P1_PUEN_P19 (0x1 << 19) -#define PORT_P1_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_PUEN_P19_GET(val) ((((val) & PORT_P1_PUEN_P19) >> 19) & 0x1) -#define PORT_P1_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P19) | (((val) & 0x1) << 19)) -/* Pull Up Device Enable at Port 1 Bit # (18) */ -#define PORT_P1_PUEN_P18 (0x1 << 18) -#define PORT_P1_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_PUEN_P18_GET(val) ((((val) & PORT_P1_PUEN_P18) >> 18) & 0x1) -#define PORT_P1_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P18) | (((val) & 0x1) << 18)) -/* Pull Up Device Enable at Port 1 Bit # (17) */ -#define PORT_P1_PUEN_P17 (0x1 << 17) -#define PORT_P1_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_PUEN_P17_GET(val) ((((val) & PORT_P1_PUEN_P17) >> 17) & 0x1) -#define PORT_P1_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P17) | (((val) & 0x1) << 17)) -/* Pull Up Device Enable at Port 1 Bit # (16) */ -#define PORT_P1_PUEN_P16 (0x1 << 16) -#define PORT_P1_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_PUEN_P16_GET(val) ((((val) & PORT_P1_PUEN_P16) >> 16) & 0x1) -#define PORT_P1_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P16) | (((val) & 0x1) << 16)) -/* Pull Up Device Enable at Port 1 Bit # (15) */ -#define PORT_P1_PUEN_P15 (0x1 << 15) -#define PORT_P1_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_PUEN_P15_GET(val) ((((val) & PORT_P1_PUEN_P15) >> 15) & 0x1) -#define PORT_P1_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P15) | (((val) & 0x1) << 15)) -/* Pull Up Device Enable at Port 1 Bit # (14) */ -#define PORT_P1_PUEN_P14 (0x1 << 14) -#define PORT_P1_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P1_PUEN_P14_GET(val) ((((val) & PORT_P1_PUEN_P14) >> 14) & 0x1) -#define PORT_P1_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P14) | (((val) & 0x1) << 14)) -/* Pull Up Device Enable at Port 1 Bit # (13) */ -#define PORT_P1_PUEN_P13 (0x1 << 13) -#define PORT_P1_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P1_PUEN_P13_GET(val) ((((val) & PORT_P1_PUEN_P13) >> 13) & 0x1) -#define PORT_P1_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P13) | (((val) & 0x1) << 13)) -/* Pull Up Device Enable at Port 1 Bit # (12) */ -#define PORT_P1_PUEN_P12 (0x1 << 12) -#define PORT_P1_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P1_PUEN_P12_GET(val) ((((val) & PORT_P1_PUEN_P12) >> 12) & 0x1) -#define PORT_P1_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P12) | (((val) & 0x1) << 12)) -/* Pull Up Device Enable at Port 1 Bit # (11) */ -#define PORT_P1_PUEN_P11 (0x1 << 11) -#define PORT_P1_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P1_PUEN_P11_GET(val) ((((val) & PORT_P1_PUEN_P11) >> 11) & 0x1) -#define PORT_P1_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P11) | (((val) & 0x1) << 11)) -/* Pull Up Device Enable at Port 1 Bit # (10) */ -#define PORT_P1_PUEN_P10 (0x1 << 10) -#define PORT_P1_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P1_PUEN_P10_GET(val) ((((val) & PORT_P1_PUEN_P10) >> 10) & 0x1) -#define PORT_P1_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P10) | (((val) & 0x1) << 10)) -/* Pull Up Device Enable at Port 1 Bit # (9) */ -#define PORT_P1_PUEN_P9 (0x1 << 9) -#define PORT_P1_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P1_PUEN_P9_GET(val) ((((val) & PORT_P1_PUEN_P9) >> 9) & 0x1) -#define PORT_P1_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P9) | (((val) & 0x1) << 9)) -/* Pull Up Device Enable at Port 1 Bit # (8) */ -#define PORT_P1_PUEN_P8 (0x1 << 8) -#define PORT_P1_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P1_PUEN_P8_GET(val) ((((val) & PORT_P1_PUEN_P8) >> 8) & 0x1) -#define PORT_P1_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P8) | (((val) & 0x1) << 8)) -/* Pull Up Device Enable at Port 1 Bit # (7) */ -#define PORT_P1_PUEN_P7 (0x1 << 7) -#define PORT_P1_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P1_PUEN_P7_GET(val) ((((val) & PORT_P1_PUEN_P7) >> 7) & 0x1) -#define PORT_P1_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P7) | (((val) & 0x1) << 7)) -/* Pull Up Device Enable at Port 1 Bit # (6) */ -#define PORT_P1_PUEN_P6 (0x1 << 6) -#define PORT_P1_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P1_PUEN_P6_GET(val) ((((val) & PORT_P1_PUEN_P6) >> 6) & 0x1) -#define PORT_P1_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P6) | (((val) & 0x1) << 6)) -/* Pull Up Device Enable at Port 1 Bit # (5) */ -#define PORT_P1_PUEN_P5 (0x1 << 5) -#define PORT_P1_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P1_PUEN_P5_GET(val) ((((val) & PORT_P1_PUEN_P5) >> 5) & 0x1) -#define PORT_P1_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P5) | (((val) & 0x1) << 5)) -/* Pull Up Device Enable at Port 1 Bit # (4) */ -#define PORT_P1_PUEN_P4 (0x1 << 4) -#define PORT_P1_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P1_PUEN_P4_GET(val) ((((val) & PORT_P1_PUEN_P4) >> 4) & 0x1) -#define PORT_P1_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P4) | (((val) & 0x1) << 4)) -/* Pull Up Device Enable at Port 1 Bit # (3) */ -#define PORT_P1_PUEN_P3 (0x1 << 3) -#define PORT_P1_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P1_PUEN_P3_GET(val) ((((val) & PORT_P1_PUEN_P3) >> 3) & 0x1) -#define PORT_P1_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P3) | (((val) & 0x1) << 3)) -/* Pull Up Device Enable at Port 1 Bit # (2) */ -#define PORT_P1_PUEN_P2 (0x1 << 2) -#define PORT_P1_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P1_PUEN_P2_GET(val) ((((val) & PORT_P1_PUEN_P2) >> 2) & 0x1) -#define PORT_P1_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P2) | (((val) & 0x1) << 2)) -/* Pull Up Device Enable at Port 1 Bit # (1) */ -#define PORT_P1_PUEN_P1 (0x1 << 1) -#define PORT_P1_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P1_PUEN_P1_GET(val) ((((val) & PORT_P1_PUEN_P1) >> 1) & 0x1) -#define PORT_P1_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P1) | (((val) & 0x1) << 1)) -/* Pull Up Device Enable at Port 1 Bit # (0) */ -#define PORT_P1_PUEN_P0 (0x1) -#define PORT_P1_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P1_PUEN_P0_GET(val) ((((val) & PORT_P1_PUEN_P0) >> 0) & 0x1) -#define PORT_P1_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * External Interrupt Control Register 0 - ******************************************************************************/ - -/* Type of Level or Edge Detection of EXINT15 (19) */ -#define PORT_P1_EXINTCR0_EXINT15 (0x1 << 19) -#define PORT_P1_EXINTCR0_EXINT15_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_EXINTCR0_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT15) >> 19) & 0x1) -#define PORT_P1_EXINTCR0_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT15) | (((val) & 0x1) << 19)) -/* Type of Level or Edge Detection of EXINT11 (18) */ -#define PORT_P1_EXINTCR0_EXINT11 (0x1 << 18) -#define PORT_P1_EXINTCR0_EXINT11_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_EXINTCR0_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT11) >> 18) & 0x1) -#define PORT_P1_EXINTCR0_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT11) | (((val) & 0x1) << 18)) -/* Type of Level or Edge Detection of EXINT12 (17) */ -#define PORT_P1_EXINTCR0_EXINT12 (0x1 << 17) -#define PORT_P1_EXINTCR0_EXINT12_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_EXINTCR0_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT12) >> 17) & 0x1) -#define PORT_P1_EXINTCR0_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT12) | (((val) & 0x1) << 17)) -/* Type of Level or Edge Detection of EXINT13 (16) */ -#define PORT_P1_EXINTCR0_EXINT13 (0x1 << 16) -#define PORT_P1_EXINTCR0_EXINT13_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_EXINTCR0_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT13) >> 16) & 0x1) -#define PORT_P1_EXINTCR0_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT13) | (((val) & 0x1) << 16)) -/* Type of Level or Edge Detection of EXINT14 (15) */ -#define PORT_P1_EXINTCR0_EXINT14 (0x1 << 15) -#define PORT_P1_EXINTCR0_EXINT14_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_EXINTCR0_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT14) >> 15) & 0x1) -#define PORT_P1_EXINTCR0_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT14) | (((val) & 0x1) << 15)) - -/******************************************************************************* - * External Interrupt Control Register 1 - ******************************************************************************/ - -/* Type of Level or Edge Detection of EXINT15 (19) */ -#define PORT_P1_EXINTCR1_EXINT15 (0x1 << 19) -#define PORT_P1_EXINTCR1_EXINT15_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_EXINTCR1_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT15) >> 19) & 0x1) -#define PORT_P1_EXINTCR1_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT15) | (((val) & 0x1) << 19)) -/* Type of Level or Edge Detection of EXINT11 (18) */ -#define PORT_P1_EXINTCR1_EXINT11 (0x1 << 18) -#define PORT_P1_EXINTCR1_EXINT11_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_EXINTCR1_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT11) >> 18) & 0x1) -#define PORT_P1_EXINTCR1_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT11) | (((val) & 0x1) << 18)) -/* Type of Level or Edge Detection of EXINT12 (17) */ -#define PORT_P1_EXINTCR1_EXINT12 (0x1 << 17) -#define PORT_P1_EXINTCR1_EXINT12_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_EXINTCR1_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT12) >> 17) & 0x1) -#define PORT_P1_EXINTCR1_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT12) | (((val) & 0x1) << 17)) -/* Type of Level or Edge Detection of EXINT13 (16) */ -#define PORT_P1_EXINTCR1_EXINT13 (0x1 << 16) -#define PORT_P1_EXINTCR1_EXINT13_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_EXINTCR1_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT13) >> 16) & 0x1) -#define PORT_P1_EXINTCR1_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT13) | (((val) & 0x1) << 16)) -/* Type of Level or Edge Detection of EXINT14 (15) */ -#define PORT_P1_EXINTCR1_EXINT14 (0x1 << 15) -#define PORT_P1_EXINTCR1_EXINT14_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_EXINTCR1_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT14) >> 15) & 0x1) -#define PORT_P1_EXINTCR1_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT14) | (((val) & 0x1) << 15)) - -/******************************************************************************* - * P1_IRNEN Register - ******************************************************************************/ - -/* EXINT15 Interrupt Request Enable (19) */ -#define PORT_P1_IRNEN_EXINT15 (0x1 << 19) -#define PORT_P1_IRNEN_EXINT15_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_IRNEN_EXINT15_GET(val) ((((val) & PORT_P1_IRNEN_EXINT15) >> 19) & 0x1) -#define PORT_P1_IRNEN_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT15) | (((val) & 0x1) << 19)) -/* EXINT11 Interrupt Request Enable (18) */ -#define PORT_P1_IRNEN_EXINT11 (0x1 << 18) -#define PORT_P1_IRNEN_EXINT11_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_IRNEN_EXINT11_GET(val) ((((val) & PORT_P1_IRNEN_EXINT11) >> 18) & 0x1) -#define PORT_P1_IRNEN_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT11) | (((val) & 0x1) << 18)) -/* EXINT12 Interrupt Request Enable (17) */ -#define PORT_P1_IRNEN_EXINT12 (0x1 << 17) -#define PORT_P1_IRNEN_EXINT12_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_IRNEN_EXINT12_GET(val) ((((val) & PORT_P1_IRNEN_EXINT12) >> 17) & 0x1) -#define PORT_P1_IRNEN_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT12) | (((val) & 0x1) << 17)) -/* EXINT13 Interrupt Request Enable (16) */ -#define PORT_P1_IRNEN_EXINT13 (0x1 << 16) -#define PORT_P1_IRNEN_EXINT13_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_IRNEN_EXINT13_GET(val) ((((val) & PORT_P1_IRNEN_EXINT13) >> 16) & 0x1) -#define PORT_P1_IRNEN_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT13) | (((val) & 0x1) << 16)) -/* EXINT14 Interrupt Request Enable (15) */ -#define PORT_P1_IRNEN_EXINT14 (0x1 << 15) -#define PORT_P1_IRNEN_EXINT14_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_IRNEN_EXINT14_GET(val) ((((val) & PORT_P1_IRNEN_EXINT14) >> 15) & 0x1) -#define PORT_P1_IRNEN_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT14) | (((val) & 0x1) << 15)) - -/******************************************************************************* - * P1_IRNICR Register - ******************************************************************************/ - -/* EXINT15 Interrupt Request (19) */ -#define PORT_P1_IRNICR_EXINT15 (0x1 << 19) -#define PORT_P1_IRNICR_EXINT15_GET(val) ((((val) & PORT_P1_IRNICR_EXINT15) >> 19) & 0x1) -/* EXINT11 Interrupt Request (18) */ -#define PORT_P1_IRNICR_EXINT11 (0x1 << 18) -#define PORT_P1_IRNICR_EXINT11_GET(val) ((((val) & PORT_P1_IRNICR_EXINT11) >> 18) & 0x1) -/* EXINT12 Interrupt Request (17) */ -#define PORT_P1_IRNICR_EXINT12 (0x1 << 17) -#define PORT_P1_IRNICR_EXINT12_GET(val) ((((val) & PORT_P1_IRNICR_EXINT12) >> 17) & 0x1) -/* EXINT13 Interrupt Request (16) */ -#define PORT_P1_IRNICR_EXINT13 (0x1 << 16) -#define PORT_P1_IRNICR_EXINT13_GET(val) ((((val) & PORT_P1_IRNICR_EXINT13) >> 16) & 0x1) -/* EXINT14 Interrupt Request (15) */ -#define PORT_P1_IRNICR_EXINT14 (0x1 << 15) -#define PORT_P1_IRNICR_EXINT14_GET(val) ((((val) & PORT_P1_IRNICR_EXINT14) >> 15) & 0x1) - -/******************************************************************************* - * P1_IRNCR Register - ******************************************************************************/ - -/* EXINT15 Interrupt Request (19) */ -#define PORT_P1_IRNCR_EXINT15 (0x1 << 19) -#define PORT_P1_IRNCR_EXINT15_GET(val) ((((val) & PORT_P1_IRNCR_EXINT15) >> 19) & 0x1) -/* EXINT11 Interrupt Request (18) */ -#define PORT_P1_IRNCR_EXINT11 (0x1 << 18) -#define PORT_P1_IRNCR_EXINT11_GET(val) ((((val) & PORT_P1_IRNCR_EXINT11) >> 18) & 0x1) -/* EXINT12 Interrupt Request (17) */ -#define PORT_P1_IRNCR_EXINT12 (0x1 << 17) -#define PORT_P1_IRNCR_EXINT12_GET(val) ((((val) & PORT_P1_IRNCR_EXINT12) >> 17) & 0x1) -/* EXINT13 Interrupt Request (16) */ -#define PORT_P1_IRNCR_EXINT13 (0x1 << 16) -#define PORT_P1_IRNCR_EXINT13_GET(val) ((((val) & PORT_P1_IRNCR_EXINT13) >> 16) & 0x1) -/* EXINT14 Interrupt Request (15) */ -#define PORT_P1_IRNCR_EXINT14 (0x1 << 15) -#define PORT_P1_IRNCR_EXINT14_GET(val) ((((val) & PORT_P1_IRNCR_EXINT14) >> 15) & 0x1) - -/******************************************************************************* - * P1 External Event Detection Configuration Register - ******************************************************************************/ - -/* EXINT15 configured for Edge or Level Detection (19) */ -#define PORT_P1_IRNCFG_EXINT15 (0x1 << 19) -#define PORT_P1_IRNCFG_EXINT15_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_IRNCFG_EXINT15_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT15) >> 19) & 0x1) -#define PORT_P1_IRNCFG_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT15) | (((val) & 0x1) << 19)) -/* EXINT11 configured for Edge or Level Detection (18) */ -#define PORT_P1_IRNCFG_EXINT11 (0x1 << 18) -#define PORT_P1_IRNCFG_EXINT11_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_IRNCFG_EXINT11_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT11) >> 18) & 0x1) -#define PORT_P1_IRNCFG_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT11) | (((val) & 0x1) << 18)) -/* EXINT12 configured for Edge or Level Detection (17) */ -#define PORT_P1_IRNCFG_EXINT12 (0x1 << 17) -#define PORT_P1_IRNCFG_EXINT12_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_IRNCFG_EXINT12_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT12) >> 17) & 0x1) -#define PORT_P1_IRNCFG_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT12) | (((val) & 0x1) << 17)) -/* EXINT13 configured for Edge or Level Detection (16) */ -#define PORT_P1_IRNCFG_EXINT13 (0x1 << 16) -#define PORT_P1_IRNCFG_EXINT13_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_IRNCFG_EXINT13_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT13) >> 16) & 0x1) -#define PORT_P1_IRNCFG_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT13) | (((val) & 0x1) << 16)) -/* EXINT14 configured for Edge or Level Detection (15) */ -#define PORT_P1_IRNCFG_EXINT14 (0x1 << 15) -#define PORT_P1_IRNCFG_EXINT14_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_IRNCFG_EXINT14_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT14) >> 15) & 0x1) -#define PORT_P1_IRNCFG_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT14) | (((val) & 0x1) << 15)) - -/******************************************************************************* - * P1_IRNENSET Register - ******************************************************************************/ - -/* Set Interrupt Node Enable Flag EXINT15 (19) */ -#define PORT_P1_IRNENSET_EXINT15 (0x1 << 19) -#define PORT_P1_IRNENSET_EXINT15_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_IRNENSET_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT15) | (val) & 1) << 19) -/* Set Interrupt Node Enable Flag EXINT11 (18) */ -#define PORT_P1_IRNENSET_EXINT11 (0x1 << 18) -#define PORT_P1_IRNENSET_EXINT11_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_IRNENSET_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT11) | (val) & 1) << 18) -/* Set Interrupt Node Enable Flag EXINT12 (17) */ -#define PORT_P1_IRNENSET_EXINT12 (0x1 << 17) -#define PORT_P1_IRNENSET_EXINT12_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_IRNENSET_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT12) | (val) & 1) << 17) -/* Set Interrupt Node Enable Flag EXINT13 (16) */ -#define PORT_P1_IRNENSET_EXINT13 (0x1 << 16) -#define PORT_P1_IRNENSET_EXINT13_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_IRNENSET_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT13) | (val) & 1) << 16) -/* Set Interrupt Node Enable Flag EXINT14 (15) */ -#define PORT_P1_IRNENSET_EXINT14 (0x1 << 15) -#define PORT_P1_IRNENSET_EXINT14_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_IRNENSET_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT14) | (val) & 1) << 15) - -/******************************************************************************* - * P1_IRNENCLR Register - ******************************************************************************/ - -/* Clear Interrupt Node Enable Flag EXINT15 (19) */ -#define PORT_P1_IRNENCLR_EXINT15 (0x1 << 19) -#define PORT_P1_IRNENCLR_EXINT15_VAL(val) (((val) & 0x1) << 19) -#define PORT_P1_IRNENCLR_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT15) | (val) & 1) << 19) -/* Clear Interrupt Node Enable Flag EXINT11 (18) */ -#define PORT_P1_IRNENCLR_EXINT11 (0x1 << 18) -#define PORT_P1_IRNENCLR_EXINT11_VAL(val) (((val) & 0x1) << 18) -#define PORT_P1_IRNENCLR_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT11) | (val) & 1) << 18) -/* Clear Interrupt Node Enable Flag EXINT12 (17) */ -#define PORT_P1_IRNENCLR_EXINT12 (0x1 << 17) -#define PORT_P1_IRNENCLR_EXINT12_VAL(val) (((val) & 0x1) << 17) -#define PORT_P1_IRNENCLR_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT12) | (val) & 1) << 17) -/* Clear Interrupt Node Enable Flag EXINT13 (16) */ -#define PORT_P1_IRNENCLR_EXINT13 (0x1 << 16) -#define PORT_P1_IRNENCLR_EXINT13_VAL(val) (((val) & 0x1) << 16) -#define PORT_P1_IRNENCLR_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT13) | (val) & 1) << 16) -/* Clear Interrupt Node Enable Flag EXINT14 (15) */ -#define PORT_P1_IRNENCLR_EXINT14 (0x1 << 15) -#define PORT_P1_IRNENCLR_EXINT14_VAL(val) (((val) & 0x1) << 15) -#define PORT_P1_IRNENCLR_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT14) | (val) & 1) << 15) - -/******************************************************************************* - * Port 2 Data Output Register - ******************************************************************************/ - -/* Port 2 Pin # Output Value (19) */ -#define PORT_P2_OUT_P19 (0x1 << 19) -#define PORT_P2_OUT_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P2_OUT_P19_GET(val) ((((val) & PORT_P2_OUT_P19) >> 19) & 0x1) -#define PORT_P2_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P19) | (((val) & 0x1) << 19)) -/* Port 2 Pin # Output Value (18) */ -#define PORT_P2_OUT_P18 (0x1 << 18) -#define PORT_P2_OUT_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P2_OUT_P18_GET(val) ((((val) & PORT_P2_OUT_P18) >> 18) & 0x1) -#define PORT_P2_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P18) | (((val) & 0x1) << 18)) -/* Port 2 Pin # Output Value (17) */ -#define PORT_P2_OUT_P17 (0x1 << 17) -#define PORT_P2_OUT_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P2_OUT_P17_GET(val) ((((val) & PORT_P2_OUT_P17) >> 17) & 0x1) -#define PORT_P2_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P17) | (((val) & 0x1) << 17)) -/* Port 2 Pin # Output Value (16) */ -#define PORT_P2_OUT_P16 (0x1 << 16) -#define PORT_P2_OUT_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P2_OUT_P16_GET(val) ((((val) & PORT_P2_OUT_P16) >> 16) & 0x1) -#define PORT_P2_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P16) | (((val) & 0x1) << 16)) -/* Port 2 Pin # Output Value (15) */ -#define PORT_P2_OUT_P15 (0x1 << 15) -#define PORT_P2_OUT_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P2_OUT_P15_GET(val) ((((val) & PORT_P2_OUT_P15) >> 15) & 0x1) -#define PORT_P2_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P15) | (((val) & 0x1) << 15)) -/* Port 2 Pin # Output Value (14) */ -#define PORT_P2_OUT_P14 (0x1 << 14) -#define PORT_P2_OUT_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P2_OUT_P14_GET(val) ((((val) & PORT_P2_OUT_P14) >> 14) & 0x1) -#define PORT_P2_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P14) | (((val) & 0x1) << 14)) -/* Port 2 Pin # Output Value (13) */ -#define PORT_P2_OUT_P13 (0x1 << 13) -#define PORT_P2_OUT_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P2_OUT_P13_GET(val) ((((val) & PORT_P2_OUT_P13) >> 13) & 0x1) -#define PORT_P2_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P13) | (((val) & 0x1) << 13)) -/* Port 2 Pin # Output Value (12) */ -#define PORT_P2_OUT_P12 (0x1 << 12) -#define PORT_P2_OUT_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P2_OUT_P12_GET(val) ((((val) & PORT_P2_OUT_P12) >> 12) & 0x1) -#define PORT_P2_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P12) | (((val) & 0x1) << 12)) -/* Port 2 Pin # Output Value (11) */ -#define PORT_P2_OUT_P11 (0x1 << 11) -#define PORT_P2_OUT_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P2_OUT_P11_GET(val) ((((val) & PORT_P2_OUT_P11) >> 11) & 0x1) -#define PORT_P2_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P11) | (((val) & 0x1) << 11)) -/* Port 2 Pin # Output Value (10) */ -#define PORT_P2_OUT_P10 (0x1 << 10) -#define PORT_P2_OUT_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P2_OUT_P10_GET(val) ((((val) & PORT_P2_OUT_P10) >> 10) & 0x1) -#define PORT_P2_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P10) | (((val) & 0x1) << 10)) -/* Port 2 Pin # Output Value (9) */ -#define PORT_P2_OUT_P9 (0x1 << 9) -#define PORT_P2_OUT_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P2_OUT_P9_GET(val) ((((val) & PORT_P2_OUT_P9) >> 9) & 0x1) -#define PORT_P2_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P9) | (((val) & 0x1) << 9)) -/* Port 2 Pin # Output Value (8) */ -#define PORT_P2_OUT_P8 (0x1 << 8) -#define PORT_P2_OUT_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P2_OUT_P8_GET(val) ((((val) & PORT_P2_OUT_P8) >> 8) & 0x1) -#define PORT_P2_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P8) | (((val) & 0x1) << 8)) -/* Port 2 Pin # Output Value (7) */ -#define PORT_P2_OUT_P7 (0x1 << 7) -#define PORT_P2_OUT_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P2_OUT_P7_GET(val) ((((val) & PORT_P2_OUT_P7) >> 7) & 0x1) -#define PORT_P2_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P7) | (((val) & 0x1) << 7)) -/* Port 2 Pin # Output Value (6) */ -#define PORT_P2_OUT_P6 (0x1 << 6) -#define PORT_P2_OUT_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P2_OUT_P6_GET(val) ((((val) & PORT_P2_OUT_P6) >> 6) & 0x1) -#define PORT_P2_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P6) | (((val) & 0x1) << 6)) -/* Port 2 Pin # Output Value (5) */ -#define PORT_P2_OUT_P5 (0x1 << 5) -#define PORT_P2_OUT_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P2_OUT_P5_GET(val) ((((val) & PORT_P2_OUT_P5) >> 5) & 0x1) -#define PORT_P2_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P5) | (((val) & 0x1) << 5)) -/* Port 2 Pin # Output Value (4) */ -#define PORT_P2_OUT_P4 (0x1 << 4) -#define PORT_P2_OUT_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P2_OUT_P4_GET(val) ((((val) & PORT_P2_OUT_P4) >> 4) & 0x1) -#define PORT_P2_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P4) | (((val) & 0x1) << 4)) -/* Port 2 Pin # Output Value (3) */ -#define PORT_P2_OUT_P3 (0x1 << 3) -#define PORT_P2_OUT_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P2_OUT_P3_GET(val) ((((val) & PORT_P2_OUT_P3) >> 3) & 0x1) -#define PORT_P2_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P3) | (((val) & 0x1) << 3)) -/* Port 2 Pin # Output Value (2) */ -#define PORT_P2_OUT_P2 (0x1 << 2) -#define PORT_P2_OUT_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P2_OUT_P2_GET(val) ((((val) & PORT_P2_OUT_P2) >> 2) & 0x1) -#define PORT_P2_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P2) | (((val) & 0x1) << 2)) -/* Port 2 Pin # Output Value (1) */ -#define PORT_P2_OUT_P1 (0x1 << 1) -#define PORT_P2_OUT_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P2_OUT_P1_GET(val) ((((val) & PORT_P2_OUT_P1) >> 1) & 0x1) -#define PORT_P2_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P1) | (((val) & 0x1) << 1)) -/* Port 2 Pin # Output Value (0) */ -#define PORT_P2_OUT_P0 (0x1) -#define PORT_P2_OUT_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P2_OUT_P0_GET(val) ((((val) & PORT_P2_OUT_P0) >> 0) & 0x1) -#define PORT_P2_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 2 Data Input Register - ******************************************************************************/ - -/* Port 2 Pin # Latched Input Value (19) */ -#define PORT_P2_IN_P19 (0x1 << 19) -#define PORT_P2_IN_P19_GET(val) ((((val) & PORT_P2_IN_P19) >> 19) & 0x1) -/* Port 2 Pin # Latched Input Value (18) */ -#define PORT_P2_IN_P18 (0x1 << 18) -#define PORT_P2_IN_P18_GET(val) ((((val) & PORT_P2_IN_P18) >> 18) & 0x1) -/* Port 2 Pin # Latched Input Value (17) */ -#define PORT_P2_IN_P17 (0x1 << 17) -#define PORT_P2_IN_P17_GET(val) ((((val) & PORT_P2_IN_P17) >> 17) & 0x1) -/* Port 2 Pin # Latched Input Value (16) */ -#define PORT_P2_IN_P16 (0x1 << 16) -#define PORT_P2_IN_P16_GET(val) ((((val) & PORT_P2_IN_P16) >> 16) & 0x1) -/* Port 2 Pin # Latched Input Value (15) */ -#define PORT_P2_IN_P15 (0x1 << 15) -#define PORT_P2_IN_P15_GET(val) ((((val) & PORT_P2_IN_P15) >> 15) & 0x1) -/* Port 2 Pin # Latched Input Value (14) */ -#define PORT_P2_IN_P14 (0x1 << 14) -#define PORT_P2_IN_P14_GET(val) ((((val) & PORT_P2_IN_P14) >> 14) & 0x1) -/* Port 2 Pin # Latched Input Value (13) */ -#define PORT_P2_IN_P13 (0x1 << 13) -#define PORT_P2_IN_P13_GET(val) ((((val) & PORT_P2_IN_P13) >> 13) & 0x1) -/* Port 2 Pin # Latched Input Value (12) */ -#define PORT_P2_IN_P12 (0x1 << 12) -#define PORT_P2_IN_P12_GET(val) ((((val) & PORT_P2_IN_P12) >> 12) & 0x1) -/* Port 2 Pin # Latched Input Value (11) */ -#define PORT_P2_IN_P11 (0x1 << 11) -#define PORT_P2_IN_P11_GET(val) ((((val) & PORT_P2_IN_P11) >> 11) & 0x1) -/* Port 2 Pin # Latched Input Value (10) */ -#define PORT_P2_IN_P10 (0x1 << 10) -#define PORT_P2_IN_P10_GET(val) ((((val) & PORT_P2_IN_P10) >> 10) & 0x1) -/* Port 2 Pin # Latched Input Value (9) */ -#define PORT_P2_IN_P9 (0x1 << 9) -#define PORT_P2_IN_P9_GET(val) ((((val) & PORT_P2_IN_P9) >> 9) & 0x1) -/* Port 2 Pin # Latched Input Value (8) */ -#define PORT_P2_IN_P8 (0x1 << 8) -#define PORT_P2_IN_P8_GET(val) ((((val) & PORT_P2_IN_P8) >> 8) & 0x1) -/* Port 2 Pin # Latched Input Value (7) */ -#define PORT_P2_IN_P7 (0x1 << 7) -#define PORT_P2_IN_P7_GET(val) ((((val) & PORT_P2_IN_P7) >> 7) & 0x1) -/* Port 2 Pin # Latched Input Value (6) */ -#define PORT_P2_IN_P6 (0x1 << 6) -#define PORT_P2_IN_P6_GET(val) ((((val) & PORT_P2_IN_P6) >> 6) & 0x1) -/* Port 2 Pin # Latched Input Value (5) */ -#define PORT_P2_IN_P5 (0x1 << 5) -#define PORT_P2_IN_P5_GET(val) ((((val) & PORT_P2_IN_P5) >> 5) & 0x1) -/* Port 2 Pin # Latched Input Value (4) */ -#define PORT_P2_IN_P4 (0x1 << 4) -#define PORT_P2_IN_P4_GET(val) ((((val) & PORT_P2_IN_P4) >> 4) & 0x1) -/* Port 2 Pin # Latched Input Value (3) */ -#define PORT_P2_IN_P3 (0x1 << 3) -#define PORT_P2_IN_P3_GET(val) ((((val) & PORT_P2_IN_P3) >> 3) & 0x1) -/* Port 2 Pin # Latched Input Value (2) */ -#define PORT_P2_IN_P2 (0x1 << 2) -#define PORT_P2_IN_P2_GET(val) ((((val) & PORT_P2_IN_P2) >> 2) & 0x1) -/* Port 2 Pin # Latched Input Value (1) */ -#define PORT_P2_IN_P1 (0x1 << 1) -#define PORT_P2_IN_P1_GET(val) ((((val) & PORT_P2_IN_P1) >> 1) & 0x1) -/* Port 2 Pin # Latched Input Value (0) */ -#define PORT_P2_IN_P0 (0x1) -#define PORT_P2_IN_P0_GET(val) ((((val) & PORT_P2_IN_P0) >> 0) & 0x1) - -/******************************************************************************* - * Port 2 Direction Register - ******************************************************************************/ - -/* Port 2 Pin #Direction Control (19) */ -#define PORT_P2_DIR_P19 (0x1 << 19) -#define PORT_P2_DIR_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P2_DIR_P19_GET(val) ((((val) & PORT_P2_DIR_P19) >> 19) & 0x1) -#define PORT_P2_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P19) | (((val) & 0x1) << 19)) -/* Port 2 Pin #Direction Control (18) */ -#define PORT_P2_DIR_P18 (0x1 << 18) -#define PORT_P2_DIR_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P2_DIR_P18_GET(val) ((((val) & PORT_P2_DIR_P18) >> 18) & 0x1) -#define PORT_P2_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P18) | (((val) & 0x1) << 18)) -/* Port 2 Pin #Direction Control (17) */ -#define PORT_P2_DIR_P17 (0x1 << 17) -#define PORT_P2_DIR_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P2_DIR_P17_GET(val) ((((val) & PORT_P2_DIR_P17) >> 17) & 0x1) -#define PORT_P2_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P17) | (((val) & 0x1) << 17)) -/* Port 2 Pin #Direction Control (16) */ -#define PORT_P2_DIR_P16 (0x1 << 16) -#define PORT_P2_DIR_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P2_DIR_P16_GET(val) ((((val) & PORT_P2_DIR_P16) >> 16) & 0x1) -#define PORT_P2_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P16) | (((val) & 0x1) << 16)) -/* Port 2 Pin #Direction Control (15) */ -#define PORT_P2_DIR_P15 (0x1 << 15) -#define PORT_P2_DIR_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P2_DIR_P15_GET(val) ((((val) & PORT_P2_DIR_P15) >> 15) & 0x1) -#define PORT_P2_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P15) | (((val) & 0x1) << 15)) -/* Port 2 Pin #Direction Control (14) */ -#define PORT_P2_DIR_P14 (0x1 << 14) -#define PORT_P2_DIR_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P2_DIR_P14_GET(val) ((((val) & PORT_P2_DIR_P14) >> 14) & 0x1) -#define PORT_P2_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P14) | (((val) & 0x1) << 14)) -/* Port 2 Pin #Direction Control (13) */ -#define PORT_P2_DIR_P13 (0x1 << 13) -#define PORT_P2_DIR_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P2_DIR_P13_GET(val) ((((val) & PORT_P2_DIR_P13) >> 13) & 0x1) -#define PORT_P2_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P13) | (((val) & 0x1) << 13)) -/* Port 2 Pin #Direction Control (12) */ -#define PORT_P2_DIR_P12 (0x1 << 12) -#define PORT_P2_DIR_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P2_DIR_P12_GET(val) ((((val) & PORT_P2_DIR_P12) >> 12) & 0x1) -#define PORT_P2_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P12) | (((val) & 0x1) << 12)) -/* Port 2 Pin #Direction Control (11) */ -#define PORT_P2_DIR_P11 (0x1 << 11) -#define PORT_P2_DIR_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P2_DIR_P11_GET(val) ((((val) & PORT_P2_DIR_P11) >> 11) & 0x1) -#define PORT_P2_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P11) | (((val) & 0x1) << 11)) -/* Port 2 Pin #Direction Control (10) */ -#define PORT_P2_DIR_P10 (0x1 << 10) -#define PORT_P2_DIR_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P2_DIR_P10_GET(val) ((((val) & PORT_P2_DIR_P10) >> 10) & 0x1) -#define PORT_P2_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P10) | (((val) & 0x1) << 10)) -/* Port 2 Pin #Direction Control (9) */ -#define PORT_P2_DIR_P9 (0x1 << 9) -#define PORT_P2_DIR_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P2_DIR_P9_GET(val) ((((val) & PORT_P2_DIR_P9) >> 9) & 0x1) -#define PORT_P2_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P9) | (((val) & 0x1) << 9)) -/* Port 2 Pin #Direction Control (8) */ -#define PORT_P2_DIR_P8 (0x1 << 8) -#define PORT_P2_DIR_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P2_DIR_P8_GET(val) ((((val) & PORT_P2_DIR_P8) >> 8) & 0x1) -#define PORT_P2_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P8) | (((val) & 0x1) << 8)) -/* Port 2 Pin #Direction Control (7) */ -#define PORT_P2_DIR_P7 (0x1 << 7) -#define PORT_P2_DIR_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P2_DIR_P7_GET(val) ((((val) & PORT_P2_DIR_P7) >> 7) & 0x1) -#define PORT_P2_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P7) | (((val) & 0x1) << 7)) -/* Port 2 Pin #Direction Control (6) */ -#define PORT_P2_DIR_P6 (0x1 << 6) -#define PORT_P2_DIR_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P2_DIR_P6_GET(val) ((((val) & PORT_P2_DIR_P6) >> 6) & 0x1) -#define PORT_P2_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P6) | (((val) & 0x1) << 6)) -/* Port 2 Pin #Direction Control (5) */ -#define PORT_P2_DIR_P5 (0x1 << 5) -#define PORT_P2_DIR_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P2_DIR_P5_GET(val) ((((val) & PORT_P2_DIR_P5) >> 5) & 0x1) -#define PORT_P2_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P5) | (((val) & 0x1) << 5)) -/* Port 2 Pin #Direction Control (4) */ -#define PORT_P2_DIR_P4 (0x1 << 4) -#define PORT_P2_DIR_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P2_DIR_P4_GET(val) ((((val) & PORT_P2_DIR_P4) >> 4) & 0x1) -#define PORT_P2_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P4) | (((val) & 0x1) << 4)) -/* Port 2 Pin #Direction Control (3) */ -#define PORT_P2_DIR_P3 (0x1 << 3) -#define PORT_P2_DIR_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P2_DIR_P3_GET(val) ((((val) & PORT_P2_DIR_P3) >> 3) & 0x1) -#define PORT_P2_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P3) | (((val) & 0x1) << 3)) -/* Port 2 Pin #Direction Control (2) */ -#define PORT_P2_DIR_P2 (0x1 << 2) -#define PORT_P2_DIR_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P2_DIR_P2_GET(val) ((((val) & PORT_P2_DIR_P2) >> 2) & 0x1) -#define PORT_P2_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P2) | (((val) & 0x1) << 2)) -/* Port 2 Pin #Direction Control (1) */ -#define PORT_P2_DIR_P1 (0x1 << 1) -#define PORT_P2_DIR_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P2_DIR_P1_GET(val) ((((val) & PORT_P2_DIR_P1) >> 1) & 0x1) -#define PORT_P2_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P1) | (((val) & 0x1) << 1)) -/* Port 2 Pin #Direction Control (0) */ -#define PORT_P2_DIR_P0 (0x1) -#define PORT_P2_DIR_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P2_DIR_P0_GET(val) ((((val) & PORT_P2_DIR_P0) >> 0) & 0x1) -#define PORT_P2_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 2 Alternate Function Select Register 0 - ******************************************************************************/ - -/* Alternate Function at Port 2 Bit # (19) */ -#define PORT_P2_ALTSEL0_P19 (0x1 << 19) -#define PORT_P2_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P2_ALTSEL0_P19_GET(val) ((((val) & PORT_P2_ALTSEL0_P19) >> 19) & 0x1) -#define PORT_P2_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P19) | (((val) & 0x1) << 19)) -/* Alternate Function at Port 2 Bit # (18) */ -#define PORT_P2_ALTSEL0_P18 (0x1 << 18) -#define PORT_P2_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P2_ALTSEL0_P18_GET(val) ((((val) & PORT_P2_ALTSEL0_P18) >> 18) & 0x1) -#define PORT_P2_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P18) | (((val) & 0x1) << 18)) -/* Alternate Function at Port 2 Bit # (17) */ -#define PORT_P2_ALTSEL0_P17 (0x1 << 17) -#define PORT_P2_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P2_ALTSEL0_P17_GET(val) ((((val) & PORT_P2_ALTSEL0_P17) >> 17) & 0x1) -#define PORT_P2_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P17) | (((val) & 0x1) << 17)) -/* Alternate Function at Port 2 Bit # (16) */ -#define PORT_P2_ALTSEL0_P16 (0x1 << 16) -#define PORT_P2_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P2_ALTSEL0_P16_GET(val) ((((val) & PORT_P2_ALTSEL0_P16) >> 16) & 0x1) -#define PORT_P2_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P16) | (((val) & 0x1) << 16)) -/* Alternate Function at Port 2 Bit # (15) */ -#define PORT_P2_ALTSEL0_P15 (0x1 << 15) -#define PORT_P2_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P2_ALTSEL0_P15_GET(val) ((((val) & PORT_P2_ALTSEL0_P15) >> 15) & 0x1) -#define PORT_P2_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P15) | (((val) & 0x1) << 15)) -/* Alternate Function at Port 2 Bit # (14) */ -#define PORT_P2_ALTSEL0_P14 (0x1 << 14) -#define PORT_P2_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P2_ALTSEL0_P14_GET(val) ((((val) & PORT_P2_ALTSEL0_P14) >> 14) & 0x1) -#define PORT_P2_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P14) | (((val) & 0x1) << 14)) -/* Alternate Function at Port 2 Bit # (13) */ -#define PORT_P2_ALTSEL0_P13 (0x1 << 13) -#define PORT_P2_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P2_ALTSEL0_P13_GET(val) ((((val) & PORT_P2_ALTSEL0_P13) >> 13) & 0x1) -#define PORT_P2_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P13) | (((val) & 0x1) << 13)) -/* Alternate Function at Port 2 Bit # (12) */ -#define PORT_P2_ALTSEL0_P12 (0x1 << 12) -#define PORT_P2_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P2_ALTSEL0_P12_GET(val) ((((val) & PORT_P2_ALTSEL0_P12) >> 12) & 0x1) -#define PORT_P2_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P12) | (((val) & 0x1) << 12)) -/* Alternate Function at Port 2 Bit # (11) */ -#define PORT_P2_ALTSEL0_P11 (0x1 << 11) -#define PORT_P2_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P2_ALTSEL0_P11_GET(val) ((((val) & PORT_P2_ALTSEL0_P11) >> 11) & 0x1) -#define PORT_P2_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P11) | (((val) & 0x1) << 11)) -/* Alternate Function at Port 2 Bit # (10) */ -#define PORT_P2_ALTSEL0_P10 (0x1 << 10) -#define PORT_P2_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P2_ALTSEL0_P10_GET(val) ((((val) & PORT_P2_ALTSEL0_P10) >> 10) & 0x1) -#define PORT_P2_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P10) | (((val) & 0x1) << 10)) -/* Alternate Function at Port 2 Bit # (9) */ -#define PORT_P2_ALTSEL0_P9 (0x1 << 9) -#define PORT_P2_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P2_ALTSEL0_P9_GET(val) ((((val) & PORT_P2_ALTSEL0_P9) >> 9) & 0x1) -#define PORT_P2_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P9) | (((val) & 0x1) << 9)) -/* Alternate Function at Port 2 Bit # (8) */ -#define PORT_P2_ALTSEL0_P8 (0x1 << 8) -#define PORT_P2_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P2_ALTSEL0_P8_GET(val) ((((val) & PORT_P2_ALTSEL0_P8) >> 8) & 0x1) -#define PORT_P2_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P8) | (((val) & 0x1) << 8)) -/* Alternate Function at Port 2 Bit # (7) */ -#define PORT_P2_ALTSEL0_P7 (0x1 << 7) -#define PORT_P2_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P2_ALTSEL0_P7_GET(val) ((((val) & PORT_P2_ALTSEL0_P7) >> 7) & 0x1) -#define PORT_P2_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P7) | (((val) & 0x1) << 7)) -/* Alternate Function at Port 2 Bit # (6) */ -#define PORT_P2_ALTSEL0_P6 (0x1 << 6) -#define PORT_P2_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P2_ALTSEL0_P6_GET(val) ((((val) & PORT_P2_ALTSEL0_P6) >> 6) & 0x1) -#define PORT_P2_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P6) | (((val) & 0x1) << 6)) -/* Alternate Function at Port 2 Bit # (5) */ -#define PORT_P2_ALTSEL0_P5 (0x1 << 5) -#define PORT_P2_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P2_ALTSEL0_P5_GET(val) ((((val) & PORT_P2_ALTSEL0_P5) >> 5) & 0x1) -#define PORT_P2_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P5) | (((val) & 0x1) << 5)) -/* Alternate Function at Port 2 Bit # (4) */ -#define PORT_P2_ALTSEL0_P4 (0x1 << 4) -#define PORT_P2_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P2_ALTSEL0_P4_GET(val) ((((val) & PORT_P2_ALTSEL0_P4) >> 4) & 0x1) -#define PORT_P2_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P4) | (((val) & 0x1) << 4)) -/* Alternate Function at Port 2 Bit # (3) */ -#define PORT_P2_ALTSEL0_P3 (0x1 << 3) -#define PORT_P2_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P2_ALTSEL0_P3_GET(val) ((((val) & PORT_P2_ALTSEL0_P3) >> 3) & 0x1) -#define PORT_P2_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P3) | (((val) & 0x1) << 3)) -/* Alternate Function at Port 2 Bit # (2) */ -#define PORT_P2_ALTSEL0_P2 (0x1 << 2) -#define PORT_P2_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P2_ALTSEL0_P2_GET(val) ((((val) & PORT_P2_ALTSEL0_P2) >> 2) & 0x1) -#define PORT_P2_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P2) | (((val) & 0x1) << 2)) -/* Alternate Function at Port 2 Bit # (1) */ -#define PORT_P2_ALTSEL0_P1 (0x1 << 1) -#define PORT_P2_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P2_ALTSEL0_P1_GET(val) ((((val) & PORT_P2_ALTSEL0_P1) >> 1) & 0x1) -#define PORT_P2_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P1) | (((val) & 0x1) << 1)) -/* Alternate Function at Port 2 Bit # (0) */ -#define PORT_P2_ALTSEL0_P0 (0x1) -#define PORT_P2_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P2_ALTSEL0_P0_GET(val) ((((val) & PORT_P2_ALTSEL0_P0) >> 0) & 0x1) -#define PORT_P2_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 2 Pull Up Device Enable Register - ******************************************************************************/ - -/* Pull Up Device Enable at Port 2 Bit # (19) */ -#define PORT_P2_PUEN_P19 (0x1 << 19) -#define PORT_P2_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P2_PUEN_P19_GET(val) ((((val) & PORT_P2_PUEN_P19) >> 19) & 0x1) -#define PORT_P2_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P19) | (((val) & 0x1) << 19)) -/* Pull Up Device Enable at Port 2 Bit # (18) */ -#define PORT_P2_PUEN_P18 (0x1 << 18) -#define PORT_P2_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P2_PUEN_P18_GET(val) ((((val) & PORT_P2_PUEN_P18) >> 18) & 0x1) -#define PORT_P2_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P18) | (((val) & 0x1) << 18)) -/* Pull Up Device Enable at Port 2 Bit # (17) */ -#define PORT_P2_PUEN_P17 (0x1 << 17) -#define PORT_P2_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P2_PUEN_P17_GET(val) ((((val) & PORT_P2_PUEN_P17) >> 17) & 0x1) -#define PORT_P2_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P17) | (((val) & 0x1) << 17)) -/* Pull Up Device Enable at Port 2 Bit # (16) */ -#define PORT_P2_PUEN_P16 (0x1 << 16) -#define PORT_P2_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P2_PUEN_P16_GET(val) ((((val) & PORT_P2_PUEN_P16) >> 16) & 0x1) -#define PORT_P2_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P16) | (((val) & 0x1) << 16)) -/* Pull Up Device Enable at Port 2 Bit # (15) */ -#define PORT_P2_PUEN_P15 (0x1 << 15) -#define PORT_P2_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P2_PUEN_P15_GET(val) ((((val) & PORT_P2_PUEN_P15) >> 15) & 0x1) -#define PORT_P2_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P15) | (((val) & 0x1) << 15)) -/* Pull Up Device Enable at Port 2 Bit # (14) */ -#define PORT_P2_PUEN_P14 (0x1 << 14) -#define PORT_P2_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P2_PUEN_P14_GET(val) ((((val) & PORT_P2_PUEN_P14) >> 14) & 0x1) -#define PORT_P2_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P14) | (((val) & 0x1) << 14)) -/* Pull Up Device Enable at Port 2 Bit # (13) */ -#define PORT_P2_PUEN_P13 (0x1 << 13) -#define PORT_P2_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P2_PUEN_P13_GET(val) ((((val) & PORT_P2_PUEN_P13) >> 13) & 0x1) -#define PORT_P2_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P13) | (((val) & 0x1) << 13)) -/* Pull Up Device Enable at Port 2 Bit # (12) */ -#define PORT_P2_PUEN_P12 (0x1 << 12) -#define PORT_P2_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P2_PUEN_P12_GET(val) ((((val) & PORT_P2_PUEN_P12) >> 12) & 0x1) -#define PORT_P2_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P12) | (((val) & 0x1) << 12)) -/* Pull Up Device Enable at Port 2 Bit # (11) */ -#define PORT_P2_PUEN_P11 (0x1 << 11) -#define PORT_P2_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P2_PUEN_P11_GET(val) ((((val) & PORT_P2_PUEN_P11) >> 11) & 0x1) -#define PORT_P2_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P11) | (((val) & 0x1) << 11)) -/* Pull Up Device Enable at Port 2 Bit # (10) */ -#define PORT_P2_PUEN_P10 (0x1 << 10) -#define PORT_P2_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P2_PUEN_P10_GET(val) ((((val) & PORT_P2_PUEN_P10) >> 10) & 0x1) -#define PORT_P2_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P10) | (((val) & 0x1) << 10)) -/* Pull Up Device Enable at Port 2 Bit # (9) */ -#define PORT_P2_PUEN_P9 (0x1 << 9) -#define PORT_P2_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P2_PUEN_P9_GET(val) ((((val) & PORT_P2_PUEN_P9) >> 9) & 0x1) -#define PORT_P2_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P9) | (((val) & 0x1) << 9)) -/* Pull Up Device Enable at Port 2 Bit # (8) */ -#define PORT_P2_PUEN_P8 (0x1 << 8) -#define PORT_P2_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P2_PUEN_P8_GET(val) ((((val) & PORT_P2_PUEN_P8) >> 8) & 0x1) -#define PORT_P2_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P8) | (((val) & 0x1) << 8)) -/* Pull Up Device Enable at Port 2 Bit # (7) */ -#define PORT_P2_PUEN_P7 (0x1 << 7) -#define PORT_P2_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P2_PUEN_P7_GET(val) ((((val) & PORT_P2_PUEN_P7) >> 7) & 0x1) -#define PORT_P2_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P7) | (((val) & 0x1) << 7)) -/* Pull Up Device Enable at Port 2 Bit # (6) */ -#define PORT_P2_PUEN_P6 (0x1 << 6) -#define PORT_P2_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P2_PUEN_P6_GET(val) ((((val) & PORT_P2_PUEN_P6) >> 6) & 0x1) -#define PORT_P2_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P6) | (((val) & 0x1) << 6)) -/* Pull Up Device Enable at Port 2 Bit # (5) */ -#define PORT_P2_PUEN_P5 (0x1 << 5) -#define PORT_P2_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P2_PUEN_P5_GET(val) ((((val) & PORT_P2_PUEN_P5) >> 5) & 0x1) -#define PORT_P2_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P5) | (((val) & 0x1) << 5)) -/* Pull Up Device Enable at Port 2 Bit # (4) */ -#define PORT_P2_PUEN_P4 (0x1 << 4) -#define PORT_P2_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P2_PUEN_P4_GET(val) ((((val) & PORT_P2_PUEN_P4) >> 4) & 0x1) -#define PORT_P2_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P4) | (((val) & 0x1) << 4)) -/* Pull Up Device Enable at Port 2 Bit # (3) */ -#define PORT_P2_PUEN_P3 (0x1 << 3) -#define PORT_P2_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P2_PUEN_P3_GET(val) ((((val) & PORT_P2_PUEN_P3) >> 3) & 0x1) -#define PORT_P2_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P3) | (((val) & 0x1) << 3)) -/* Pull Up Device Enable at Port 2 Bit # (2) */ -#define PORT_P2_PUEN_P2 (0x1 << 2) -#define PORT_P2_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P2_PUEN_P2_GET(val) ((((val) & PORT_P2_PUEN_P2) >> 2) & 0x1) -#define PORT_P2_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P2) | (((val) & 0x1) << 2)) -/* Pull Up Device Enable at Port 2 Bit # (1) */ -#define PORT_P2_PUEN_P1 (0x1 << 1) -#define PORT_P2_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P2_PUEN_P1_GET(val) ((((val) & PORT_P2_PUEN_P1) >> 1) & 0x1) -#define PORT_P2_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P1) | (((val) & 0x1) << 1)) -/* Pull Up Device Enable at Port 2 Bit # (0) */ -#define PORT_P2_PUEN_P0 (0x1) -#define PORT_P2_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P2_PUEN_P0_GET(val) ((((val) & PORT_P2_PUEN_P0) >> 0) & 0x1) -#define PORT_P2_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 3 Data Output Register - ******************************************************************************/ - -/* Port 3 Pin # Output Value (19) */ -#define PORT_P3_OUT_P19 (0x1 << 19) -#define PORT_P3_OUT_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P3_OUT_P19_GET(val) ((((val) & PORT_P3_OUT_P19) >> 19) & 0x1) -#define PORT_P3_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P19) | (((val) & 0x1) << 19)) -/* Port 3 Pin # Output Value (18) */ -#define PORT_P3_OUT_P18 (0x1 << 18) -#define PORT_P3_OUT_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P3_OUT_P18_GET(val) ((((val) & PORT_P3_OUT_P18) >> 18) & 0x1) -#define PORT_P3_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P18) | (((val) & 0x1) << 18)) -/* Port 3 Pin # Output Value (17) */ -#define PORT_P3_OUT_P17 (0x1 << 17) -#define PORT_P3_OUT_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P3_OUT_P17_GET(val) ((((val) & PORT_P3_OUT_P17) >> 17) & 0x1) -#define PORT_P3_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P17) | (((val) & 0x1) << 17)) -/* Port 3 Pin # Output Value (16) */ -#define PORT_P3_OUT_P16 (0x1 << 16) -#define PORT_P3_OUT_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P3_OUT_P16_GET(val) ((((val) & PORT_P3_OUT_P16) >> 16) & 0x1) -#define PORT_P3_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P16) | (((val) & 0x1) << 16)) -/* Port 3 Pin # Output Value (15) */ -#define PORT_P3_OUT_P15 (0x1 << 15) -#define PORT_P3_OUT_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P3_OUT_P15_GET(val) ((((val) & PORT_P3_OUT_P15) >> 15) & 0x1) -#define PORT_P3_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P15) | (((val) & 0x1) << 15)) -/* Port 3 Pin # Output Value (14) */ -#define PORT_P3_OUT_P14 (0x1 << 14) -#define PORT_P3_OUT_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P3_OUT_P14_GET(val) ((((val) & PORT_P3_OUT_P14) >> 14) & 0x1) -#define PORT_P3_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P14) | (((val) & 0x1) << 14)) -/* Port 3 Pin # Output Value (13) */ -#define PORT_P3_OUT_P13 (0x1 << 13) -#define PORT_P3_OUT_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P3_OUT_P13_GET(val) ((((val) & PORT_P3_OUT_P13) >> 13) & 0x1) -#define PORT_P3_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P13) | (((val) & 0x1) << 13)) -/* Port 3 Pin # Output Value (12) */ -#define PORT_P3_OUT_P12 (0x1 << 12) -#define PORT_P3_OUT_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P3_OUT_P12_GET(val) ((((val) & PORT_P3_OUT_P12) >> 12) & 0x1) -#define PORT_P3_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P12) | (((val) & 0x1) << 12)) -/* Port 3 Pin # Output Value (11) */ -#define PORT_P3_OUT_P11 (0x1 << 11) -#define PORT_P3_OUT_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P3_OUT_P11_GET(val) ((((val) & PORT_P3_OUT_P11) >> 11) & 0x1) -#define PORT_P3_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P11) | (((val) & 0x1) << 11)) -/* Port 3 Pin # Output Value (10) */ -#define PORT_P3_OUT_P10 (0x1 << 10) -#define PORT_P3_OUT_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P3_OUT_P10_GET(val) ((((val) & PORT_P3_OUT_P10) >> 10) & 0x1) -#define PORT_P3_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P10) | (((val) & 0x1) << 10)) -/* Port 3 Pin # Output Value (9) */ -#define PORT_P3_OUT_P9 (0x1 << 9) -#define PORT_P3_OUT_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P3_OUT_P9_GET(val) ((((val) & PORT_P3_OUT_P9) >> 9) & 0x1) -#define PORT_P3_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P9) | (((val) & 0x1) << 9)) -/* Port 3 Pin # Output Value (8) */ -#define PORT_P3_OUT_P8 (0x1 << 8) -#define PORT_P3_OUT_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P3_OUT_P8_GET(val) ((((val) & PORT_P3_OUT_P8) >> 8) & 0x1) -#define PORT_P3_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P8) | (((val) & 0x1) << 8)) -/* Port 3 Pin # Output Value (7) */ -#define PORT_P3_OUT_P7 (0x1 << 7) -#define PORT_P3_OUT_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P3_OUT_P7_GET(val) ((((val) & PORT_P3_OUT_P7) >> 7) & 0x1) -#define PORT_P3_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P7) | (((val) & 0x1) << 7)) -/* Port 3 Pin # Output Value (6) */ -#define PORT_P3_OUT_P6 (0x1 << 6) -#define PORT_P3_OUT_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P3_OUT_P6_GET(val) ((((val) & PORT_P3_OUT_P6) >> 6) & 0x1) -#define PORT_P3_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P6) | (((val) & 0x1) << 6)) -/* Port 3 Pin # Output Value (5) */ -#define PORT_P3_OUT_P5 (0x1 << 5) -#define PORT_P3_OUT_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P3_OUT_P5_GET(val) ((((val) & PORT_P3_OUT_P5) >> 5) & 0x1) -#define PORT_P3_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P5) | (((val) & 0x1) << 5)) -/* Port 3 Pin # Output Value (4) */ -#define PORT_P3_OUT_P4 (0x1 << 4) -#define PORT_P3_OUT_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P3_OUT_P4_GET(val) ((((val) & PORT_P3_OUT_P4) >> 4) & 0x1) -#define PORT_P3_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P4) | (((val) & 0x1) << 4)) -/* Port 3 Pin # Output Value (3) */ -#define PORT_P3_OUT_P3 (0x1 << 3) -#define PORT_P3_OUT_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P3_OUT_P3_GET(val) ((((val) & PORT_P3_OUT_P3) >> 3) & 0x1) -#define PORT_P3_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P3) | (((val) & 0x1) << 3)) -/* Port 3 Pin # Output Value (2) */ -#define PORT_P3_OUT_P2 (0x1 << 2) -#define PORT_P3_OUT_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P3_OUT_P2_GET(val) ((((val) & PORT_P3_OUT_P2) >> 2) & 0x1) -#define PORT_P3_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P2) | (((val) & 0x1) << 2)) -/* Port 3 Pin # Output Value (1) */ -#define PORT_P3_OUT_P1 (0x1 << 1) -#define PORT_P3_OUT_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P3_OUT_P1_GET(val) ((((val) & PORT_P3_OUT_P1) >> 1) & 0x1) -#define PORT_P3_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P1) | (((val) & 0x1) << 1)) -/* Port 3 Pin # Output Value (0) */ -#define PORT_P3_OUT_P0 (0x1) -#define PORT_P3_OUT_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P3_OUT_P0_GET(val) ((((val) & PORT_P3_OUT_P0) >> 0) & 0x1) -#define PORT_P3_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 3 Data Input Register - ******************************************************************************/ - -/* Port 3 Pin # Latched Input Value (19) */ -#define PORT_P3_IN_P19 (0x1 << 19) -#define PORT_P3_IN_P19_GET(val) ((((val) & PORT_P3_IN_P19) >> 19) & 0x1) -/* Port 3 Pin # Latched Input Value (18) */ -#define PORT_P3_IN_P18 (0x1 << 18) -#define PORT_P3_IN_P18_GET(val) ((((val) & PORT_P3_IN_P18) >> 18) & 0x1) -/* Port 3 Pin # Latched Input Value (17) */ -#define PORT_P3_IN_P17 (0x1 << 17) -#define PORT_P3_IN_P17_GET(val) ((((val) & PORT_P3_IN_P17) >> 17) & 0x1) -/* Port 3 Pin # Latched Input Value (16) */ -#define PORT_P3_IN_P16 (0x1 << 16) -#define PORT_P3_IN_P16_GET(val) ((((val) & PORT_P3_IN_P16) >> 16) & 0x1) -/* Port 3 Pin # Latched Input Value (15) */ -#define PORT_P3_IN_P15 (0x1 << 15) -#define PORT_P3_IN_P15_GET(val) ((((val) & PORT_P3_IN_P15) >> 15) & 0x1) -/* Port 3 Pin # Latched Input Value (14) */ -#define PORT_P3_IN_P14 (0x1 << 14) -#define PORT_P3_IN_P14_GET(val) ((((val) & PORT_P3_IN_P14) >> 14) & 0x1) -/* Port 3 Pin # Latched Input Value (13) */ -#define PORT_P3_IN_P13 (0x1 << 13) -#define PORT_P3_IN_P13_GET(val) ((((val) & PORT_P3_IN_P13) >> 13) & 0x1) -/* Port 3 Pin # Latched Input Value (12) */ -#define PORT_P3_IN_P12 (0x1 << 12) -#define PORT_P3_IN_P12_GET(val) ((((val) & PORT_P3_IN_P12) >> 12) & 0x1) -/* Port 3 Pin # Latched Input Value (11) */ -#define PORT_P3_IN_P11 (0x1 << 11) -#define PORT_P3_IN_P11_GET(val) ((((val) & PORT_P3_IN_P11) >> 11) & 0x1) -/* Port 3 Pin # Latched Input Value (10) */ -#define PORT_P3_IN_P10 (0x1 << 10) -#define PORT_P3_IN_P10_GET(val) ((((val) & PORT_P3_IN_P10) >> 10) & 0x1) -/* Port 3 Pin # Latched Input Value (9) */ -#define PORT_P3_IN_P9 (0x1 << 9) -#define PORT_P3_IN_P9_GET(val) ((((val) & PORT_P3_IN_P9) >> 9) & 0x1) -/* Port 3 Pin # Latched Input Value (8) */ -#define PORT_P3_IN_P8 (0x1 << 8) -#define PORT_P3_IN_P8_GET(val) ((((val) & PORT_P3_IN_P8) >> 8) & 0x1) -/* Port 3 Pin # Latched Input Value (7) */ -#define PORT_P3_IN_P7 (0x1 << 7) -#define PORT_P3_IN_P7_GET(val) ((((val) & PORT_P3_IN_P7) >> 7) & 0x1) -/* Port 3 Pin # Latched Input Value (6) */ -#define PORT_P3_IN_P6 (0x1 << 6) -#define PORT_P3_IN_P6_GET(val) ((((val) & PORT_P3_IN_P6) >> 6) & 0x1) -/* Port 3 Pin # Latched Input Value (5) */ -#define PORT_P3_IN_P5 (0x1 << 5) -#define PORT_P3_IN_P5_GET(val) ((((val) & PORT_P3_IN_P5) >> 5) & 0x1) -/* Port 3 Pin # Latched Input Value (4) */ -#define PORT_P3_IN_P4 (0x1 << 4) -#define PORT_P3_IN_P4_GET(val) ((((val) & PORT_P3_IN_P4) >> 4) & 0x1) -/* Port 3 Pin # Latched Input Value (3) */ -#define PORT_P3_IN_P3 (0x1 << 3) -#define PORT_P3_IN_P3_GET(val) ((((val) & PORT_P3_IN_P3) >> 3) & 0x1) -/* Port 3 Pin # Latched Input Value (2) */ -#define PORT_P3_IN_P2 (0x1 << 2) -#define PORT_P3_IN_P2_GET(val) ((((val) & PORT_P3_IN_P2) >> 2) & 0x1) -/* Port 3 Pin # Latched Input Value (1) */ -#define PORT_P3_IN_P1 (0x1 << 1) -#define PORT_P3_IN_P1_GET(val) ((((val) & PORT_P3_IN_P1) >> 1) & 0x1) -/* Port 3 Pin # Latched Input Value (0) */ -#define PORT_P3_IN_P0 (0x1) -#define PORT_P3_IN_P0_GET(val) ((((val) & PORT_P3_IN_P0) >> 0) & 0x1) - -/******************************************************************************* - * Port 3 Direction Register - ******************************************************************************/ - -/* Port 3 Pin #Direction Control (19) */ -#define PORT_P3_DIR_P19 (0x1 << 19) -#define PORT_P3_DIR_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P3_DIR_P19_GET(val) ((((val) & PORT_P3_DIR_P19) >> 19) & 0x1) -#define PORT_P3_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P19) | (((val) & 0x1) << 19)) -/* Port 3 Pin #Direction Control (18) */ -#define PORT_P3_DIR_P18 (0x1 << 18) -#define PORT_P3_DIR_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P3_DIR_P18_GET(val) ((((val) & PORT_P3_DIR_P18) >> 18) & 0x1) -#define PORT_P3_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P18) | (((val) & 0x1) << 18)) -/* Port 3 Pin #Direction Control (17) */ -#define PORT_P3_DIR_P17 (0x1 << 17) -#define PORT_P3_DIR_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P3_DIR_P17_GET(val) ((((val) & PORT_P3_DIR_P17) >> 17) & 0x1) -#define PORT_P3_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P17) | (((val) & 0x1) << 17)) -/* Port 3 Pin #Direction Control (16) */ -#define PORT_P3_DIR_P16 (0x1 << 16) -#define PORT_P3_DIR_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P3_DIR_P16_GET(val) ((((val) & PORT_P3_DIR_P16) >> 16) & 0x1) -#define PORT_P3_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P16) | (((val) & 0x1) << 16)) -/* Port 3 Pin #Direction Control (15) */ -#define PORT_P3_DIR_P15 (0x1 << 15) -#define PORT_P3_DIR_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P3_DIR_P15_GET(val) ((((val) & PORT_P3_DIR_P15) >> 15) & 0x1) -#define PORT_P3_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P15) | (((val) & 0x1) << 15)) -/* Port 3 Pin #Direction Control (14) */ -#define PORT_P3_DIR_P14 (0x1 << 14) -#define PORT_P3_DIR_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P3_DIR_P14_GET(val) ((((val) & PORT_P3_DIR_P14) >> 14) & 0x1) -#define PORT_P3_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P14) | (((val) & 0x1) << 14)) -/* Port 3 Pin #Direction Control (13) */ -#define PORT_P3_DIR_P13 (0x1 << 13) -#define PORT_P3_DIR_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P3_DIR_P13_GET(val) ((((val) & PORT_P3_DIR_P13) >> 13) & 0x1) -#define PORT_P3_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P13) | (((val) & 0x1) << 13)) -/* Port 3 Pin #Direction Control (12) */ -#define PORT_P3_DIR_P12 (0x1 << 12) -#define PORT_P3_DIR_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P3_DIR_P12_GET(val) ((((val) & PORT_P3_DIR_P12) >> 12) & 0x1) -#define PORT_P3_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P12) | (((val) & 0x1) << 12)) -/* Port 3 Pin #Direction Control (11) */ -#define PORT_P3_DIR_P11 (0x1 << 11) -#define PORT_P3_DIR_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P3_DIR_P11_GET(val) ((((val) & PORT_P3_DIR_P11) >> 11) & 0x1) -#define PORT_P3_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P11) | (((val) & 0x1) << 11)) -/* Port 3 Pin #Direction Control (10) */ -#define PORT_P3_DIR_P10 (0x1 << 10) -#define PORT_P3_DIR_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P3_DIR_P10_GET(val) ((((val) & PORT_P3_DIR_P10) >> 10) & 0x1) -#define PORT_P3_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P10) | (((val) & 0x1) << 10)) -/* Port 3 Pin #Direction Control (9) */ -#define PORT_P3_DIR_P9 (0x1 << 9) -#define PORT_P3_DIR_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P3_DIR_P9_GET(val) ((((val) & PORT_P3_DIR_P9) >> 9) & 0x1) -#define PORT_P3_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P9) | (((val) & 0x1) << 9)) -/* Port 3 Pin #Direction Control (8) */ -#define PORT_P3_DIR_P8 (0x1 << 8) -#define PORT_P3_DIR_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P3_DIR_P8_GET(val) ((((val) & PORT_P3_DIR_P8) >> 8) & 0x1) -#define PORT_P3_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P8) | (((val) & 0x1) << 8)) -/* Port 3 Pin #Direction Control (7) */ -#define PORT_P3_DIR_P7 (0x1 << 7) -#define PORT_P3_DIR_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P3_DIR_P7_GET(val) ((((val) & PORT_P3_DIR_P7) >> 7) & 0x1) -#define PORT_P3_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P7) | (((val) & 0x1) << 7)) -/* Port 3 Pin #Direction Control (6) */ -#define PORT_P3_DIR_P6 (0x1 << 6) -#define PORT_P3_DIR_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P3_DIR_P6_GET(val) ((((val) & PORT_P3_DIR_P6) >> 6) & 0x1) -#define PORT_P3_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P6) | (((val) & 0x1) << 6)) -/* Port 3 Pin #Direction Control (5) */ -#define PORT_P3_DIR_P5 (0x1 << 5) -#define PORT_P3_DIR_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P3_DIR_P5_GET(val) ((((val) & PORT_P3_DIR_P5) >> 5) & 0x1) -#define PORT_P3_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P5) | (((val) & 0x1) << 5)) -/* Port 3 Pin #Direction Control (4) */ -#define PORT_P3_DIR_P4 (0x1 << 4) -#define PORT_P3_DIR_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P3_DIR_P4_GET(val) ((((val) & PORT_P3_DIR_P4) >> 4) & 0x1) -#define PORT_P3_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P4) | (((val) & 0x1) << 4)) -/* Port 3 Pin #Direction Control (3) */ -#define PORT_P3_DIR_P3 (0x1 << 3) -#define PORT_P3_DIR_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P3_DIR_P3_GET(val) ((((val) & PORT_P3_DIR_P3) >> 3) & 0x1) -#define PORT_P3_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P3) | (((val) & 0x1) << 3)) -/* Port 3 Pin #Direction Control (2) */ -#define PORT_P3_DIR_P2 (0x1 << 2) -#define PORT_P3_DIR_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P3_DIR_P2_GET(val) ((((val) & PORT_P3_DIR_P2) >> 2) & 0x1) -#define PORT_P3_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P2) | (((val) & 0x1) << 2)) -/* Port 3 Pin #Direction Control (1) */ -#define PORT_P3_DIR_P1 (0x1 << 1) -#define PORT_P3_DIR_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P3_DIR_P1_GET(val) ((((val) & PORT_P3_DIR_P1) >> 1) & 0x1) -#define PORT_P3_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P1) | (((val) & 0x1) << 1)) -/* Port 3 Pin #Direction Control (0) */ -#define PORT_P3_DIR_P0 (0x1) -#define PORT_P3_DIR_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P3_DIR_P0_GET(val) ((((val) & PORT_P3_DIR_P0) >> 0) & 0x1) -#define PORT_P3_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 3 Alternate Function Select Register 0 - ******************************************************************************/ - -/* Alternate Function at Port 3 Bit # (19) */ -#define PORT_P3_ALTSEL0_P19 (0x1 << 19) -#define PORT_P3_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P3_ALTSEL0_P19_GET(val) ((((val) & PORT_P3_ALTSEL0_P19) >> 19) & 0x1) -#define PORT_P3_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P19) | (((val) & 0x1) << 19)) -/* Alternate Function at Port 3 Bit # (18) */ -#define PORT_P3_ALTSEL0_P18 (0x1 << 18) -#define PORT_P3_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P3_ALTSEL0_P18_GET(val) ((((val) & PORT_P3_ALTSEL0_P18) >> 18) & 0x1) -#define PORT_P3_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P18) | (((val) & 0x1) << 18)) -/* Alternate Function at Port 3 Bit # (17) */ -#define PORT_P3_ALTSEL0_P17 (0x1 << 17) -#define PORT_P3_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P3_ALTSEL0_P17_GET(val) ((((val) & PORT_P3_ALTSEL0_P17) >> 17) & 0x1) -#define PORT_P3_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P17) | (((val) & 0x1) << 17)) -/* Alternate Function at Port 3 Bit # (16) */ -#define PORT_P3_ALTSEL0_P16 (0x1 << 16) -#define PORT_P3_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P3_ALTSEL0_P16_GET(val) ((((val) & PORT_P3_ALTSEL0_P16) >> 16) & 0x1) -#define PORT_P3_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P16) | (((val) & 0x1) << 16)) -/* Alternate Function at Port 3 Bit # (15) */ -#define PORT_P3_ALTSEL0_P15 (0x1 << 15) -#define PORT_P3_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P3_ALTSEL0_P15_GET(val) ((((val) & PORT_P3_ALTSEL0_P15) >> 15) & 0x1) -#define PORT_P3_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P15) | (((val) & 0x1) << 15)) -/* Alternate Function at Port 3 Bit # (14) */ -#define PORT_P3_ALTSEL0_P14 (0x1 << 14) -#define PORT_P3_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P3_ALTSEL0_P14_GET(val) ((((val) & PORT_P3_ALTSEL0_P14) >> 14) & 0x1) -#define PORT_P3_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P14) | (((val) & 0x1) << 14)) -/* Alternate Function at Port 3 Bit # (13) */ -#define PORT_P3_ALTSEL0_P13 (0x1 << 13) -#define PORT_P3_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P3_ALTSEL0_P13_GET(val) ((((val) & PORT_P3_ALTSEL0_P13) >> 13) & 0x1) -#define PORT_P3_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P13) | (((val) & 0x1) << 13)) -/* Alternate Function at Port 3 Bit # (12) */ -#define PORT_P3_ALTSEL0_P12 (0x1 << 12) -#define PORT_P3_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P3_ALTSEL0_P12_GET(val) ((((val) & PORT_P3_ALTSEL0_P12) >> 12) & 0x1) -#define PORT_P3_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P12) | (((val) & 0x1) << 12)) -/* Alternate Function at Port 3 Bit # (11) */ -#define PORT_P3_ALTSEL0_P11 (0x1 << 11) -#define PORT_P3_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P3_ALTSEL0_P11_GET(val) ((((val) & PORT_P3_ALTSEL0_P11) >> 11) & 0x1) -#define PORT_P3_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P11) | (((val) & 0x1) << 11)) -/* Alternate Function at Port 3 Bit # (10) */ -#define PORT_P3_ALTSEL0_P10 (0x1 << 10) -#define PORT_P3_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P3_ALTSEL0_P10_GET(val) ((((val) & PORT_P3_ALTSEL0_P10) >> 10) & 0x1) -#define PORT_P3_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P10) | (((val) & 0x1) << 10)) -/* Alternate Function at Port 3 Bit # (9) */ -#define PORT_P3_ALTSEL0_P9 (0x1 << 9) -#define PORT_P3_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P3_ALTSEL0_P9_GET(val) ((((val) & PORT_P3_ALTSEL0_P9) >> 9) & 0x1) -#define PORT_P3_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P9) | (((val) & 0x1) << 9)) -/* Alternate Function at Port 3 Bit # (8) */ -#define PORT_P3_ALTSEL0_P8 (0x1 << 8) -#define PORT_P3_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P3_ALTSEL0_P8_GET(val) ((((val) & PORT_P3_ALTSEL0_P8) >> 8) & 0x1) -#define PORT_P3_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P8) | (((val) & 0x1) << 8)) -/* Alternate Function at Port 3 Bit # (7) */ -#define PORT_P3_ALTSEL0_P7 (0x1 << 7) -#define PORT_P3_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P3_ALTSEL0_P7_GET(val) ((((val) & PORT_P3_ALTSEL0_P7) >> 7) & 0x1) -#define PORT_P3_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P7) | (((val) & 0x1) << 7)) -/* Alternate Function at Port 3 Bit # (6) */ -#define PORT_P3_ALTSEL0_P6 (0x1 << 6) -#define PORT_P3_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P3_ALTSEL0_P6_GET(val) ((((val) & PORT_P3_ALTSEL0_P6) >> 6) & 0x1) -#define PORT_P3_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P6) | (((val) & 0x1) << 6)) -/* Alternate Function at Port 3 Bit # (5) */ -#define PORT_P3_ALTSEL0_P5 (0x1 << 5) -#define PORT_P3_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P3_ALTSEL0_P5_GET(val) ((((val) & PORT_P3_ALTSEL0_P5) >> 5) & 0x1) -#define PORT_P3_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P5) | (((val) & 0x1) << 5)) -/* Alternate Function at Port 3 Bit # (4) */ -#define PORT_P3_ALTSEL0_P4 (0x1 << 4) -#define PORT_P3_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P3_ALTSEL0_P4_GET(val) ((((val) & PORT_P3_ALTSEL0_P4) >> 4) & 0x1) -#define PORT_P3_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P4) | (((val) & 0x1) << 4)) -/* Alternate Function at Port 3 Bit # (3) */ -#define PORT_P3_ALTSEL0_P3 (0x1 << 3) -#define PORT_P3_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P3_ALTSEL0_P3_GET(val) ((((val) & PORT_P3_ALTSEL0_P3) >> 3) & 0x1) -#define PORT_P3_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P3) | (((val) & 0x1) << 3)) -/* Alternate Function at Port 3 Bit # (2) */ -#define PORT_P3_ALTSEL0_P2 (0x1 << 2) -#define PORT_P3_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P3_ALTSEL0_P2_GET(val) ((((val) & PORT_P3_ALTSEL0_P2) >> 2) & 0x1) -#define PORT_P3_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P2) | (((val) & 0x1) << 2)) -/* Alternate Function at Port 3 Bit # (1) */ -#define PORT_P3_ALTSEL0_P1 (0x1 << 1) -#define PORT_P3_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P3_ALTSEL0_P1_GET(val) ((((val) & PORT_P3_ALTSEL0_P1) >> 1) & 0x1) -#define PORT_P3_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P1) | (((val) & 0x1) << 1)) -/* Alternate Function at Port 3 Bit # (0) */ -#define PORT_P3_ALTSEL0_P0 (0x1) -#define PORT_P3_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P3_ALTSEL0_P0_GET(val) ((((val) & PORT_P3_ALTSEL0_P0) >> 0) & 0x1) -#define PORT_P3_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 3 Pull Up Device Enable Register - ******************************************************************************/ - -/* Pull Up Device Enable at Port 3 Bit # (19) */ -#define PORT_P3_PUEN_P19 (0x1 << 19) -#define PORT_P3_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P3_PUEN_P19_GET(val) ((((val) & PORT_P3_PUEN_P19) >> 19) & 0x1) -#define PORT_P3_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P19) | (((val) & 0x1) << 19)) -/* Pull Up Device Enable at Port 3 Bit # (18) */ -#define PORT_P3_PUEN_P18 (0x1 << 18) -#define PORT_P3_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P3_PUEN_P18_GET(val) ((((val) & PORT_P3_PUEN_P18) >> 18) & 0x1) -#define PORT_P3_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P18) | (((val) & 0x1) << 18)) -/* Pull Up Device Enable at Port 3 Bit # (17) */ -#define PORT_P3_PUEN_P17 (0x1 << 17) -#define PORT_P3_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P3_PUEN_P17_GET(val) ((((val) & PORT_P3_PUEN_P17) >> 17) & 0x1) -#define PORT_P3_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P17) | (((val) & 0x1) << 17)) -/* Pull Up Device Enable at Port 3 Bit # (16) */ -#define PORT_P3_PUEN_P16 (0x1 << 16) -#define PORT_P3_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P3_PUEN_P16_GET(val) ((((val) & PORT_P3_PUEN_P16) >> 16) & 0x1) -#define PORT_P3_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P16) | (((val) & 0x1) << 16)) -/* Pull Up Device Enable at Port 3 Bit # (15) */ -#define PORT_P3_PUEN_P15 (0x1 << 15) -#define PORT_P3_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P3_PUEN_P15_GET(val) ((((val) & PORT_P3_PUEN_P15) >> 15) & 0x1) -#define PORT_P3_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P15) | (((val) & 0x1) << 15)) -/* Pull Up Device Enable at Port 3 Bit # (14) */ -#define PORT_P3_PUEN_P14 (0x1 << 14) -#define PORT_P3_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P3_PUEN_P14_GET(val) ((((val) & PORT_P3_PUEN_P14) >> 14) & 0x1) -#define PORT_P3_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P14) | (((val) & 0x1) << 14)) -/* Pull Up Device Enable at Port 3 Bit # (13) */ -#define PORT_P3_PUEN_P13 (0x1 << 13) -#define PORT_P3_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P3_PUEN_P13_GET(val) ((((val) & PORT_P3_PUEN_P13) >> 13) & 0x1) -#define PORT_P3_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P13) | (((val) & 0x1) << 13)) -/* Pull Up Device Enable at Port 3 Bit # (12) */ -#define PORT_P3_PUEN_P12 (0x1 << 12) -#define PORT_P3_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P3_PUEN_P12_GET(val) ((((val) & PORT_P3_PUEN_P12) >> 12) & 0x1) -#define PORT_P3_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P12) | (((val) & 0x1) << 12)) -/* Pull Up Device Enable at Port 3 Bit # (11) */ -#define PORT_P3_PUEN_P11 (0x1 << 11) -#define PORT_P3_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P3_PUEN_P11_GET(val) ((((val) & PORT_P3_PUEN_P11) >> 11) & 0x1) -#define PORT_P3_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P11) | (((val) & 0x1) << 11)) -/* Pull Up Device Enable at Port 3 Bit # (10) */ -#define PORT_P3_PUEN_P10 (0x1 << 10) -#define PORT_P3_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P3_PUEN_P10_GET(val) ((((val) & PORT_P3_PUEN_P10) >> 10) & 0x1) -#define PORT_P3_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P10) | (((val) & 0x1) << 10)) -/* Pull Up Device Enable at Port 3 Bit # (9) */ -#define PORT_P3_PUEN_P9 (0x1 << 9) -#define PORT_P3_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P3_PUEN_P9_GET(val) ((((val) & PORT_P3_PUEN_P9) >> 9) & 0x1) -#define PORT_P3_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P9) | (((val) & 0x1) << 9)) -/* Pull Up Device Enable at Port 3 Bit # (8) */ -#define PORT_P3_PUEN_P8 (0x1 << 8) -#define PORT_P3_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P3_PUEN_P8_GET(val) ((((val) & PORT_P3_PUEN_P8) >> 8) & 0x1) -#define PORT_P3_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P8) | (((val) & 0x1) << 8)) -/* Pull Up Device Enable at Port 3 Bit # (7) */ -#define PORT_P3_PUEN_P7 (0x1 << 7) -#define PORT_P3_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P3_PUEN_P7_GET(val) ((((val) & PORT_P3_PUEN_P7) >> 7) & 0x1) -#define PORT_P3_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P7) | (((val) & 0x1) << 7)) -/* Pull Up Device Enable at Port 3 Bit # (6) */ -#define PORT_P3_PUEN_P6 (0x1 << 6) -#define PORT_P3_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P3_PUEN_P6_GET(val) ((((val) & PORT_P3_PUEN_P6) >> 6) & 0x1) -#define PORT_P3_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P6) | (((val) & 0x1) << 6)) -/* Pull Up Device Enable at Port 3 Bit # (5) */ -#define PORT_P3_PUEN_P5 (0x1 << 5) -#define PORT_P3_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P3_PUEN_P5_GET(val) ((((val) & PORT_P3_PUEN_P5) >> 5) & 0x1) -#define PORT_P3_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P5) | (((val) & 0x1) << 5)) -/* Pull Up Device Enable at Port 3 Bit # (4) */ -#define PORT_P3_PUEN_P4 (0x1 << 4) -#define PORT_P3_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P3_PUEN_P4_GET(val) ((((val) & PORT_P3_PUEN_P4) >> 4) & 0x1) -#define PORT_P3_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P4) | (((val) & 0x1) << 4)) -/* Pull Up Device Enable at Port 3 Bit # (3) */ -#define PORT_P3_PUEN_P3 (0x1 << 3) -#define PORT_P3_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P3_PUEN_P3_GET(val) ((((val) & PORT_P3_PUEN_P3) >> 3) & 0x1) -#define PORT_P3_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P3) | (((val) & 0x1) << 3)) -/* Pull Up Device Enable at Port 3 Bit # (2) */ -#define PORT_P3_PUEN_P2 (0x1 << 2) -#define PORT_P3_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P3_PUEN_P2_GET(val) ((((val) & PORT_P3_PUEN_P2) >> 2) & 0x1) -#define PORT_P3_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P2) | (((val) & 0x1) << 2)) -/* Pull Up Device Enable at Port 3 Bit # (1) */ -#define PORT_P3_PUEN_P1 (0x1 << 1) -#define PORT_P3_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P3_PUEN_P1_GET(val) ((((val) & PORT_P3_PUEN_P1) >> 1) & 0x1) -#define PORT_P3_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P1) | (((val) & 0x1) << 1)) -/* Pull Up Device Enable at Port 3 Bit # (0) */ -#define PORT_P3_PUEN_P0 (0x1) -#define PORT_P3_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P3_PUEN_P0_GET(val) ((((val) & PORT_P3_PUEN_P0) >> 0) & 0x1) -#define PORT_P3_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 4 Data Output Register - ******************************************************************************/ - -/* Port 4 Pin # Output Value (23) */ -#define PORT_P4_OUT_P23 (0x1 << 23) -#define PORT_P4_OUT_P23_VAL(val) (((val) & 0x1) << 23) -#define PORT_P4_OUT_P23_GET(val) ((((val) & PORT_P4_OUT_P23) >> 23) & 0x1) -#define PORT_P4_OUT_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P23) | (((val) & 0x1) << 23)) -/* Port 4 Pin # Output Value (22) */ -#define PORT_P4_OUT_P22 (0x1 << 22) -#define PORT_P4_OUT_P22_VAL(val) (((val) & 0x1) << 22) -#define PORT_P4_OUT_P22_GET(val) ((((val) & PORT_P4_OUT_P22) >> 22) & 0x1) -#define PORT_P4_OUT_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P22) | (((val) & 0x1) << 22)) -/* Port 4 Pin # Output Value (21) */ -#define PORT_P4_OUT_P21 (0x1 << 21) -#define PORT_P4_OUT_P21_VAL(val) (((val) & 0x1) << 21) -#define PORT_P4_OUT_P21_GET(val) ((((val) & PORT_P4_OUT_P21) >> 21) & 0x1) -#define PORT_P4_OUT_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P21) | (((val) & 0x1) << 21)) -/* Port 4 Pin # Output Value (20) */ -#define PORT_P4_OUT_P20 (0x1 << 20) -#define PORT_P4_OUT_P20_VAL(val) (((val) & 0x1) << 20) -#define PORT_P4_OUT_P20_GET(val) ((((val) & PORT_P4_OUT_P20) >> 20) & 0x1) -#define PORT_P4_OUT_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P20) | (((val) & 0x1) << 20)) -/* Port 4 Pin # Output Value (19) */ -#define PORT_P4_OUT_P19 (0x1 << 19) -#define PORT_P4_OUT_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P4_OUT_P19_GET(val) ((((val) & PORT_P4_OUT_P19) >> 19) & 0x1) -#define PORT_P4_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P19) | (((val) & 0x1) << 19)) -/* Port 4 Pin # Output Value (18) */ -#define PORT_P4_OUT_P18 (0x1 << 18) -#define PORT_P4_OUT_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P4_OUT_P18_GET(val) ((((val) & PORT_P4_OUT_P18) >> 18) & 0x1) -#define PORT_P4_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P18) | (((val) & 0x1) << 18)) -/* Port 4 Pin # Output Value (17) */ -#define PORT_P4_OUT_P17 (0x1 << 17) -#define PORT_P4_OUT_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P4_OUT_P17_GET(val) ((((val) & PORT_P4_OUT_P17) >> 17) & 0x1) -#define PORT_P4_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P17) | (((val) & 0x1) << 17)) -/* Port 4 Pin # Output Value (16) */ -#define PORT_P4_OUT_P16 (0x1 << 16) -#define PORT_P4_OUT_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P4_OUT_P16_GET(val) ((((val) & PORT_P4_OUT_P16) >> 16) & 0x1) -#define PORT_P4_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P16) | (((val) & 0x1) << 16)) -/* Port 4 Pin # Output Value (15) */ -#define PORT_P4_OUT_P15 (0x1 << 15) -#define PORT_P4_OUT_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P4_OUT_P15_GET(val) ((((val) & PORT_P4_OUT_P15) >> 15) & 0x1) -#define PORT_P4_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P15) | (((val) & 0x1) << 15)) -/* Port 4 Pin # Output Value (14) */ -#define PORT_P4_OUT_P14 (0x1 << 14) -#define PORT_P4_OUT_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P4_OUT_P14_GET(val) ((((val) & PORT_P4_OUT_P14) >> 14) & 0x1) -#define PORT_P4_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P14) | (((val) & 0x1) << 14)) -/* Port 4 Pin # Output Value (13) */ -#define PORT_P4_OUT_P13 (0x1 << 13) -#define PORT_P4_OUT_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P4_OUT_P13_GET(val) ((((val) & PORT_P4_OUT_P13) >> 13) & 0x1) -#define PORT_P4_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P13) | (((val) & 0x1) << 13)) -/* Port 4 Pin # Output Value (12) */ -#define PORT_P4_OUT_P12 (0x1 << 12) -#define PORT_P4_OUT_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P4_OUT_P12_GET(val) ((((val) & PORT_P4_OUT_P12) >> 12) & 0x1) -#define PORT_P4_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P12) | (((val) & 0x1) << 12)) -/* Port 4 Pin # Output Value (11) */ -#define PORT_P4_OUT_P11 (0x1 << 11) -#define PORT_P4_OUT_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P4_OUT_P11_GET(val) ((((val) & PORT_P4_OUT_P11) >> 11) & 0x1) -#define PORT_P4_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P11) | (((val) & 0x1) << 11)) -/* Port 4 Pin # Output Value (10) */ -#define PORT_P4_OUT_P10 (0x1 << 10) -#define PORT_P4_OUT_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P4_OUT_P10_GET(val) ((((val) & PORT_P4_OUT_P10) >> 10) & 0x1) -#define PORT_P4_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P10) | (((val) & 0x1) << 10)) -/* Port 4 Pin # Output Value (9) */ -#define PORT_P4_OUT_P9 (0x1 << 9) -#define PORT_P4_OUT_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P4_OUT_P9_GET(val) ((((val) & PORT_P4_OUT_P9) >> 9) & 0x1) -#define PORT_P4_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P9) | (((val) & 0x1) << 9)) -/* Port 4 Pin # Output Value (8) */ -#define PORT_P4_OUT_P8 (0x1 << 8) -#define PORT_P4_OUT_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P4_OUT_P8_GET(val) ((((val) & PORT_P4_OUT_P8) >> 8) & 0x1) -#define PORT_P4_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P8) | (((val) & 0x1) << 8)) -/* Port 4 Pin # Output Value (7) */ -#define PORT_P4_OUT_P7 (0x1 << 7) -#define PORT_P4_OUT_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P4_OUT_P7_GET(val) ((((val) & PORT_P4_OUT_P7) >> 7) & 0x1) -#define PORT_P4_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P7) | (((val) & 0x1) << 7)) -/* Port 4 Pin # Output Value (6) */ -#define PORT_P4_OUT_P6 (0x1 << 6) -#define PORT_P4_OUT_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P4_OUT_P6_GET(val) ((((val) & PORT_P4_OUT_P6) >> 6) & 0x1) -#define PORT_P4_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P6) | (((val) & 0x1) << 6)) -/* Port 4 Pin # Output Value (5) */ -#define PORT_P4_OUT_P5 (0x1 << 5) -#define PORT_P4_OUT_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P4_OUT_P5_GET(val) ((((val) & PORT_P4_OUT_P5) >> 5) & 0x1) -#define PORT_P4_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P5) | (((val) & 0x1) << 5)) -/* Port 4 Pin # Output Value (4) */ -#define PORT_P4_OUT_P4 (0x1 << 4) -#define PORT_P4_OUT_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P4_OUT_P4_GET(val) ((((val) & PORT_P4_OUT_P4) >> 4) & 0x1) -#define PORT_P4_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P4) | (((val) & 0x1) << 4)) -/* Port 4 Pin # Output Value (3) */ -#define PORT_P4_OUT_P3 (0x1 << 3) -#define PORT_P4_OUT_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P4_OUT_P3_GET(val) ((((val) & PORT_P4_OUT_P3) >> 3) & 0x1) -#define PORT_P4_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P3) | (((val) & 0x1) << 3)) -/* Port 4 Pin # Output Value (2) */ -#define PORT_P4_OUT_P2 (0x1 << 2) -#define PORT_P4_OUT_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P4_OUT_P2_GET(val) ((((val) & PORT_P4_OUT_P2) >> 2) & 0x1) -#define PORT_P4_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P2) | (((val) & 0x1) << 2)) -/* Port 4 Pin # Output Value (1) */ -#define PORT_P4_OUT_P1 (0x1 << 1) -#define PORT_P4_OUT_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P4_OUT_P1_GET(val) ((((val) & PORT_P4_OUT_P1) >> 1) & 0x1) -#define PORT_P4_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P1) | (((val) & 0x1) << 1)) -/* Port 4 Pin # Output Value (0) */ -#define PORT_P4_OUT_P0 (0x1) -#define PORT_P4_OUT_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P4_OUT_P0_GET(val) ((((val) & PORT_P4_OUT_P0) >> 0) & 0x1) -#define PORT_P4_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 4 Data Input Register - ******************************************************************************/ - -/* Port 4 Pin # Latched Input Value (23) */ -#define PORT_P4_IN_P23 (0x1 << 23) -#define PORT_P4_IN_P23_GET(val) ((((val) & PORT_P4_IN_P23) >> 23) & 0x1) -/* Port 4 Pin # Latched Input Value (22) */ -#define PORT_P4_IN_P22 (0x1 << 22) -#define PORT_P4_IN_P22_GET(val) ((((val) & PORT_P4_IN_P22) >> 22) & 0x1) -/* Port 4 Pin # Latched Input Value (21) */ -#define PORT_P4_IN_P21 (0x1 << 21) -#define PORT_P4_IN_P21_GET(val) ((((val) & PORT_P4_IN_P21) >> 21) & 0x1) -/* Port 4 Pin # Latched Input Value (20) */ -#define PORT_P4_IN_P20 (0x1 << 20) -#define PORT_P4_IN_P20_GET(val) ((((val) & PORT_P4_IN_P20) >> 20) & 0x1) -/* Port 4 Pin # Latched Input Value (19) */ -#define PORT_P4_IN_P19 (0x1 << 19) -#define PORT_P4_IN_P19_GET(val) ((((val) & PORT_P4_IN_P19) >> 19) & 0x1) -/* Port 4 Pin # Latched Input Value (18) */ -#define PORT_P4_IN_P18 (0x1 << 18) -#define PORT_P4_IN_P18_GET(val) ((((val) & PORT_P4_IN_P18) >> 18) & 0x1) -/* Port 4 Pin # Latched Input Value (17) */ -#define PORT_P4_IN_P17 (0x1 << 17) -#define PORT_P4_IN_P17_GET(val) ((((val) & PORT_P4_IN_P17) >> 17) & 0x1) -/* Port 4 Pin # Latched Input Value (16) */ -#define PORT_P4_IN_P16 (0x1 << 16) -#define PORT_P4_IN_P16_GET(val) ((((val) & PORT_P4_IN_P16) >> 16) & 0x1) -/* Port 4 Pin # Latched Input Value (15) */ -#define PORT_P4_IN_P15 (0x1 << 15) -#define PORT_P4_IN_P15_GET(val) ((((val) & PORT_P4_IN_P15) >> 15) & 0x1) -/* Port 4 Pin # Latched Input Value (14) */ -#define PORT_P4_IN_P14 (0x1 << 14) -#define PORT_P4_IN_P14_GET(val) ((((val) & PORT_P4_IN_P14) >> 14) & 0x1) -/* Port 4 Pin # Latched Input Value (13) */ -#define PORT_P4_IN_P13 (0x1 << 13) -#define PORT_P4_IN_P13_GET(val) ((((val) & PORT_P4_IN_P13) >> 13) & 0x1) -/* Port 4 Pin # Latched Input Value (12) */ -#define PORT_P4_IN_P12 (0x1 << 12) -#define PORT_P4_IN_P12_GET(val) ((((val) & PORT_P4_IN_P12) >> 12) & 0x1) -/* Port 4 Pin # Latched Input Value (11) */ -#define PORT_P4_IN_P11 (0x1 << 11) -#define PORT_P4_IN_P11_GET(val) ((((val) & PORT_P4_IN_P11) >> 11) & 0x1) -/* Port 4 Pin # Latched Input Value (10) */ -#define PORT_P4_IN_P10 (0x1 << 10) -#define PORT_P4_IN_P10_GET(val) ((((val) & PORT_P4_IN_P10) >> 10) & 0x1) -/* Port 4 Pin # Latched Input Value (9) */ -#define PORT_P4_IN_P9 (0x1 << 9) -#define PORT_P4_IN_P9_GET(val) ((((val) & PORT_P4_IN_P9) >> 9) & 0x1) -/* Port 4 Pin # Latched Input Value (8) */ -#define PORT_P4_IN_P8 (0x1 << 8) -#define PORT_P4_IN_P8_GET(val) ((((val) & PORT_P4_IN_P8) >> 8) & 0x1) -/* Port 4 Pin # Latched Input Value (7) */ -#define PORT_P4_IN_P7 (0x1 << 7) -#define PORT_P4_IN_P7_GET(val) ((((val) & PORT_P4_IN_P7) >> 7) & 0x1) -/* Port 4 Pin # Latched Input Value (6) */ -#define PORT_P4_IN_P6 (0x1 << 6) -#define PORT_P4_IN_P6_GET(val) ((((val) & PORT_P4_IN_P6) >> 6) & 0x1) -/* Port 4 Pin # Latched Input Value (5) */ -#define PORT_P4_IN_P5 (0x1 << 5) -#define PORT_P4_IN_P5_GET(val) ((((val) & PORT_P4_IN_P5) >> 5) & 0x1) -/* Port 4 Pin # Latched Input Value (4) */ -#define PORT_P4_IN_P4 (0x1 << 4) -#define PORT_P4_IN_P4_GET(val) ((((val) & PORT_P4_IN_P4) >> 4) & 0x1) -/* Port 4 Pin # Latched Input Value (3) */ -#define PORT_P4_IN_P3 (0x1 << 3) -#define PORT_P4_IN_P3_GET(val) ((((val) & PORT_P4_IN_P3) >> 3) & 0x1) -/* Port 4 Pin # Latched Input Value (2) */ -#define PORT_P4_IN_P2 (0x1 << 2) -#define PORT_P4_IN_P2_GET(val) ((((val) & PORT_P4_IN_P2) >> 2) & 0x1) -/* Port 4 Pin # Latched Input Value (1) */ -#define PORT_P4_IN_P1 (0x1 << 1) -#define PORT_P4_IN_P1_GET(val) ((((val) & PORT_P4_IN_P1) >> 1) & 0x1) -/* Port 4 Pin # Latched Input Value (0) */ -#define PORT_P4_IN_P0 (0x1) -#define PORT_P4_IN_P0_GET(val) ((((val) & PORT_P4_IN_P0) >> 0) & 0x1) - -/******************************************************************************* - * Port 4 Direction Register - ******************************************************************************/ - -/* Port 4 Pin #Direction Control (23) */ -#define PORT_P4_DIR_P23 (0x1 << 23) -#define PORT_P4_DIR_P23_VAL(val) (((val) & 0x1) << 23) -#define PORT_P4_DIR_P23_GET(val) ((((val) & PORT_P4_DIR_P23) >> 23) & 0x1) -#define PORT_P4_DIR_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P23) | (((val) & 0x1) << 23)) -/* Port 4 Pin #Direction Control (22) */ -#define PORT_P4_DIR_P22 (0x1 << 22) -#define PORT_P4_DIR_P22_VAL(val) (((val) & 0x1) << 22) -#define PORT_P4_DIR_P22_GET(val) ((((val) & PORT_P4_DIR_P22) >> 22) & 0x1) -#define PORT_P4_DIR_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P22) | (((val) & 0x1) << 22)) -/* Port 4 Pin #Direction Control (21) */ -#define PORT_P4_DIR_P21 (0x1 << 21) -#define PORT_P4_DIR_P21_VAL(val) (((val) & 0x1) << 21) -#define PORT_P4_DIR_P21_GET(val) ((((val) & PORT_P4_DIR_P21) >> 21) & 0x1) -#define PORT_P4_DIR_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P21) | (((val) & 0x1) << 21)) -/* Port 4 Pin #Direction Control (20) */ -#define PORT_P4_DIR_P20 (0x1 << 20) -#define PORT_P4_DIR_P20_VAL(val) (((val) & 0x1) << 20) -#define PORT_P4_DIR_P20_GET(val) ((((val) & PORT_P4_DIR_P20) >> 20) & 0x1) -#define PORT_P4_DIR_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P20) | (((val) & 0x1) << 20)) -/* Port 4 Pin #Direction Control (19) */ -#define PORT_P4_DIR_P19 (0x1 << 19) -#define PORT_P4_DIR_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P4_DIR_P19_GET(val) ((((val) & PORT_P4_DIR_P19) >> 19) & 0x1) -#define PORT_P4_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P19) | (((val) & 0x1) << 19)) -/* Port 4 Pin #Direction Control (18) */ -#define PORT_P4_DIR_P18 (0x1 << 18) -#define PORT_P4_DIR_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P4_DIR_P18_GET(val) ((((val) & PORT_P4_DIR_P18) >> 18) & 0x1) -#define PORT_P4_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P18) | (((val) & 0x1) << 18)) -/* Port 4 Pin #Direction Control (17) */ -#define PORT_P4_DIR_P17 (0x1 << 17) -#define PORT_P4_DIR_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P4_DIR_P17_GET(val) ((((val) & PORT_P4_DIR_P17) >> 17) & 0x1) -#define PORT_P4_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P17) | (((val) & 0x1) << 17)) -/* Port 4 Pin #Direction Control (16) */ -#define PORT_P4_DIR_P16 (0x1 << 16) -#define PORT_P4_DIR_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P4_DIR_P16_GET(val) ((((val) & PORT_P4_DIR_P16) >> 16) & 0x1) -#define PORT_P4_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P16) | (((val) & 0x1) << 16)) -/* Port 4 Pin #Direction Control (15) */ -#define PORT_P4_DIR_P15 (0x1 << 15) -#define PORT_P4_DIR_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P4_DIR_P15_GET(val) ((((val) & PORT_P4_DIR_P15) >> 15) & 0x1) -#define PORT_P4_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P15) | (((val) & 0x1) << 15)) -/* Port 4 Pin #Direction Control (14) */ -#define PORT_P4_DIR_P14 (0x1 << 14) -#define PORT_P4_DIR_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P4_DIR_P14_GET(val) ((((val) & PORT_P4_DIR_P14) >> 14) & 0x1) -#define PORT_P4_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P14) | (((val) & 0x1) << 14)) -/* Port 4 Pin #Direction Control (13) */ -#define PORT_P4_DIR_P13 (0x1 << 13) -#define PORT_P4_DIR_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P4_DIR_P13_GET(val) ((((val) & PORT_P4_DIR_P13) >> 13) & 0x1) -#define PORT_P4_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P13) | (((val) & 0x1) << 13)) -/* Port 4 Pin #Direction Control (12) */ -#define PORT_P4_DIR_P12 (0x1 << 12) -#define PORT_P4_DIR_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P4_DIR_P12_GET(val) ((((val) & PORT_P4_DIR_P12) >> 12) & 0x1) -#define PORT_P4_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P12) | (((val) & 0x1) << 12)) -/* Port 4 Pin #Direction Control (11) */ -#define PORT_P4_DIR_P11 (0x1 << 11) -#define PORT_P4_DIR_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P4_DIR_P11_GET(val) ((((val) & PORT_P4_DIR_P11) >> 11) & 0x1) -#define PORT_P4_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P11) | (((val) & 0x1) << 11)) -/* Port 4 Pin #Direction Control (10) */ -#define PORT_P4_DIR_P10 (0x1 << 10) -#define PORT_P4_DIR_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P4_DIR_P10_GET(val) ((((val) & PORT_P4_DIR_P10) >> 10) & 0x1) -#define PORT_P4_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P10) | (((val) & 0x1) << 10)) -/* Port 4 Pin #Direction Control (9) */ -#define PORT_P4_DIR_P9 (0x1 << 9) -#define PORT_P4_DIR_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P4_DIR_P9_GET(val) ((((val) & PORT_P4_DIR_P9) >> 9) & 0x1) -#define PORT_P4_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P9) | (((val) & 0x1) << 9)) -/* Port 4 Pin #Direction Control (8) */ -#define PORT_P4_DIR_P8 (0x1 << 8) -#define PORT_P4_DIR_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P4_DIR_P8_GET(val) ((((val) & PORT_P4_DIR_P8) >> 8) & 0x1) -#define PORT_P4_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P8) | (((val) & 0x1) << 8)) -/* Port 4 Pin #Direction Control (7) */ -#define PORT_P4_DIR_P7 (0x1 << 7) -#define PORT_P4_DIR_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P4_DIR_P7_GET(val) ((((val) & PORT_P4_DIR_P7) >> 7) & 0x1) -#define PORT_P4_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P7) | (((val) & 0x1) << 7)) -/* Port 4 Pin #Direction Control (6) */ -#define PORT_P4_DIR_P6 (0x1 << 6) -#define PORT_P4_DIR_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P4_DIR_P6_GET(val) ((((val) & PORT_P4_DIR_P6) >> 6) & 0x1) -#define PORT_P4_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P6) | (((val) & 0x1) << 6)) -/* Port 4 Pin #Direction Control (5) */ -#define PORT_P4_DIR_P5 (0x1 << 5) -#define PORT_P4_DIR_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P4_DIR_P5_GET(val) ((((val) & PORT_P4_DIR_P5) >> 5) & 0x1) -#define PORT_P4_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P5) | (((val) & 0x1) << 5)) -/* Port 4 Pin #Direction Control (4) */ -#define PORT_P4_DIR_P4 (0x1 << 4) -#define PORT_P4_DIR_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P4_DIR_P4_GET(val) ((((val) & PORT_P4_DIR_P4) >> 4) & 0x1) -#define PORT_P4_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P4) | (((val) & 0x1) << 4)) -/* Port 4 Pin #Direction Control (3) */ -#define PORT_P4_DIR_P3 (0x1 << 3) -#define PORT_P4_DIR_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P4_DIR_P3_GET(val) ((((val) & PORT_P4_DIR_P3) >> 3) & 0x1) -#define PORT_P4_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P3) | (((val) & 0x1) << 3)) -/* Port 4 Pin #Direction Control (2) */ -#define PORT_P4_DIR_P2 (0x1 << 2) -#define PORT_P4_DIR_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P4_DIR_P2_GET(val) ((((val) & PORT_P4_DIR_P2) >> 2) & 0x1) -#define PORT_P4_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P2) | (((val) & 0x1) << 2)) -/* Port 4 Pin #Direction Control (1) */ -#define PORT_P4_DIR_P1 (0x1 << 1) -#define PORT_P4_DIR_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P4_DIR_P1_GET(val) ((((val) & PORT_P4_DIR_P1) >> 1) & 0x1) -#define PORT_P4_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P1) | (((val) & 0x1) << 1)) -/* Port 4 Pin #Direction Control (0) */ -#define PORT_P4_DIR_P0 (0x1) -#define PORT_P4_DIR_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P4_DIR_P0_GET(val) ((((val) & PORT_P4_DIR_P0) >> 0) & 0x1) -#define PORT_P4_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 4 Alternate Function Select Register 0 - ******************************************************************************/ - -/* Alternate Function at Port 4 Bit # (23) */ -#define PORT_P4_ALTSEL0_P23 (0x1 << 23) -#define PORT_P4_ALTSEL0_P23_VAL(val) (((val) & 0x1) << 23) -#define PORT_P4_ALTSEL0_P23_GET(val) ((((val) & PORT_P4_ALTSEL0_P23) >> 23) & 0x1) -#define PORT_P4_ALTSEL0_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P23) | (((val) & 0x1) << 23)) -/* Alternate Function at Port 4 Bit # (22) */ -#define PORT_P4_ALTSEL0_P22 (0x1 << 22) -#define PORT_P4_ALTSEL0_P22_VAL(val) (((val) & 0x1) << 22) -#define PORT_P4_ALTSEL0_P22_GET(val) ((((val) & PORT_P4_ALTSEL0_P22) >> 22) & 0x1) -#define PORT_P4_ALTSEL0_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P22) | (((val) & 0x1) << 22)) -/* Alternate Function at Port 4 Bit # (21) */ -#define PORT_P4_ALTSEL0_P21 (0x1 << 21) -#define PORT_P4_ALTSEL0_P21_VAL(val) (((val) & 0x1) << 21) -#define PORT_P4_ALTSEL0_P21_GET(val) ((((val) & PORT_P4_ALTSEL0_P21) >> 21) & 0x1) -#define PORT_P4_ALTSEL0_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P21) | (((val) & 0x1) << 21)) -/* Alternate Function at Port 4 Bit # (20) */ -#define PORT_P4_ALTSEL0_P20 (0x1 << 20) -#define PORT_P4_ALTSEL0_P20_VAL(val) (((val) & 0x1) << 20) -#define PORT_P4_ALTSEL0_P20_GET(val) ((((val) & PORT_P4_ALTSEL0_P20) >> 20) & 0x1) -#define PORT_P4_ALTSEL0_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P20) | (((val) & 0x1) << 20)) -/* Alternate Function at Port 4 Bit # (19) */ -#define PORT_P4_ALTSEL0_P19 (0x1 << 19) -#define PORT_P4_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P4_ALTSEL0_P19_GET(val) ((((val) & PORT_P4_ALTSEL0_P19) >> 19) & 0x1) -#define PORT_P4_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P19) | (((val) & 0x1) << 19)) -/* Alternate Function at Port 4 Bit # (18) */ -#define PORT_P4_ALTSEL0_P18 (0x1 << 18) -#define PORT_P4_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P4_ALTSEL0_P18_GET(val) ((((val) & PORT_P4_ALTSEL0_P18) >> 18) & 0x1) -#define PORT_P4_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P18) | (((val) & 0x1) << 18)) -/* Alternate Function at Port 4 Bit # (17) */ -#define PORT_P4_ALTSEL0_P17 (0x1 << 17) -#define PORT_P4_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P4_ALTSEL0_P17_GET(val) ((((val) & PORT_P4_ALTSEL0_P17) >> 17) & 0x1) -#define PORT_P4_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P17) | (((val) & 0x1) << 17)) -/* Alternate Function at Port 4 Bit # (16) */ -#define PORT_P4_ALTSEL0_P16 (0x1 << 16) -#define PORT_P4_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P4_ALTSEL0_P16_GET(val) ((((val) & PORT_P4_ALTSEL0_P16) >> 16) & 0x1) -#define PORT_P4_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P16) | (((val) & 0x1) << 16)) -/* Alternate Function at Port 4 Bit # (15) */ -#define PORT_P4_ALTSEL0_P15 (0x1 << 15) -#define PORT_P4_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P4_ALTSEL0_P15_GET(val) ((((val) & PORT_P4_ALTSEL0_P15) >> 15) & 0x1) -#define PORT_P4_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P15) | (((val) & 0x1) << 15)) -/* Alternate Function at Port 4 Bit # (14) */ -#define PORT_P4_ALTSEL0_P14 (0x1 << 14) -#define PORT_P4_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P4_ALTSEL0_P14_GET(val) ((((val) & PORT_P4_ALTSEL0_P14) >> 14) & 0x1) -#define PORT_P4_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P14) | (((val) & 0x1) << 14)) -/* Alternate Function at Port 4 Bit # (13) */ -#define PORT_P4_ALTSEL0_P13 (0x1 << 13) -#define PORT_P4_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P4_ALTSEL0_P13_GET(val) ((((val) & PORT_P4_ALTSEL0_P13) >> 13) & 0x1) -#define PORT_P4_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P13) | (((val) & 0x1) << 13)) -/* Alternate Function at Port 4 Bit # (12) */ -#define PORT_P4_ALTSEL0_P12 (0x1 << 12) -#define PORT_P4_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P4_ALTSEL0_P12_GET(val) ((((val) & PORT_P4_ALTSEL0_P12) >> 12) & 0x1) -#define PORT_P4_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P12) | (((val) & 0x1) << 12)) -/* Alternate Function at Port 4 Bit # (11) */ -#define PORT_P4_ALTSEL0_P11 (0x1 << 11) -#define PORT_P4_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P4_ALTSEL0_P11_GET(val) ((((val) & PORT_P4_ALTSEL0_P11) >> 11) & 0x1) -#define PORT_P4_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P11) | (((val) & 0x1) << 11)) -/* Alternate Function at Port 4 Bit # (10) */ -#define PORT_P4_ALTSEL0_P10 (0x1 << 10) -#define PORT_P4_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P4_ALTSEL0_P10_GET(val) ((((val) & PORT_P4_ALTSEL0_P10) >> 10) & 0x1) -#define PORT_P4_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P10) | (((val) & 0x1) << 10)) -/* Alternate Function at Port 4 Bit # (9) */ -#define PORT_P4_ALTSEL0_P9 (0x1 << 9) -#define PORT_P4_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P4_ALTSEL0_P9_GET(val) ((((val) & PORT_P4_ALTSEL0_P9) >> 9) & 0x1) -#define PORT_P4_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P9) | (((val) & 0x1) << 9)) -/* Alternate Function at Port 4 Bit # (8) */ -#define PORT_P4_ALTSEL0_P8 (0x1 << 8) -#define PORT_P4_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P4_ALTSEL0_P8_GET(val) ((((val) & PORT_P4_ALTSEL0_P8) >> 8) & 0x1) -#define PORT_P4_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P8) | (((val) & 0x1) << 8)) -/* Alternate Function at Port 4 Bit # (7) */ -#define PORT_P4_ALTSEL0_P7 (0x1 << 7) -#define PORT_P4_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P4_ALTSEL0_P7_GET(val) ((((val) & PORT_P4_ALTSEL0_P7) >> 7) & 0x1) -#define PORT_P4_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P7) | (((val) & 0x1) << 7)) -/* Alternate Function at Port 4 Bit # (6) */ -#define PORT_P4_ALTSEL0_P6 (0x1 << 6) -#define PORT_P4_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P4_ALTSEL0_P6_GET(val) ((((val) & PORT_P4_ALTSEL0_P6) >> 6) & 0x1) -#define PORT_P4_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P6) | (((val) & 0x1) << 6)) -/* Alternate Function at Port 4 Bit # (5) */ -#define PORT_P4_ALTSEL0_P5 (0x1 << 5) -#define PORT_P4_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P4_ALTSEL0_P5_GET(val) ((((val) & PORT_P4_ALTSEL0_P5) >> 5) & 0x1) -#define PORT_P4_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P5) | (((val) & 0x1) << 5)) -/* Alternate Function at Port 4 Bit # (4) */ -#define PORT_P4_ALTSEL0_P4 (0x1 << 4) -#define PORT_P4_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P4_ALTSEL0_P4_GET(val) ((((val) & PORT_P4_ALTSEL0_P4) >> 4) & 0x1) -#define PORT_P4_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P4) | (((val) & 0x1) << 4)) -/* Alternate Function at Port 4 Bit # (3) */ -#define PORT_P4_ALTSEL0_P3 (0x1 << 3) -#define PORT_P4_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P4_ALTSEL0_P3_GET(val) ((((val) & PORT_P4_ALTSEL0_P3) >> 3) & 0x1) -#define PORT_P4_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P3) | (((val) & 0x1) << 3)) -/* Alternate Function at Port 4 Bit # (2) */ -#define PORT_P4_ALTSEL0_P2 (0x1 << 2) -#define PORT_P4_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P4_ALTSEL0_P2_GET(val) ((((val) & PORT_P4_ALTSEL0_P2) >> 2) & 0x1) -#define PORT_P4_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P2) | (((val) & 0x1) << 2)) -/* Alternate Function at Port 4 Bit # (1) */ -#define PORT_P4_ALTSEL0_P1 (0x1 << 1) -#define PORT_P4_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P4_ALTSEL0_P1_GET(val) ((((val) & PORT_P4_ALTSEL0_P1) >> 1) & 0x1) -#define PORT_P4_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P1) | (((val) & 0x1) << 1)) -/* Alternate Function at Port 4 Bit # (0) */ -#define PORT_P4_ALTSEL0_P0 (0x1) -#define PORT_P4_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P4_ALTSEL0_P0_GET(val) ((((val) & PORT_P4_ALTSEL0_P0) >> 0) & 0x1) -#define PORT_P4_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * Port 4 Pull Up Device Enable Register - ******************************************************************************/ - -/* Pull Up Device Enable at Port 4 Bit # (23) */ -#define PORT_P4_PUEN_P23 (0x1 << 23) -#define PORT_P4_PUEN_P23_VAL(val) (((val) & 0x1) << 23) -#define PORT_P4_PUEN_P23_GET(val) ((((val) & PORT_P4_PUEN_P23) >> 23) & 0x1) -#define PORT_P4_PUEN_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P23) | (((val) & 0x1) << 23)) -/* Pull Up Device Enable at Port 4 Bit # (22) */ -#define PORT_P4_PUEN_P22 (0x1 << 22) -#define PORT_P4_PUEN_P22_VAL(val) (((val) & 0x1) << 22) -#define PORT_P4_PUEN_P22_GET(val) ((((val) & PORT_P4_PUEN_P22) >> 22) & 0x1) -#define PORT_P4_PUEN_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P22) | (((val) & 0x1) << 22)) -/* Pull Up Device Enable at Port 4 Bit # (21) */ -#define PORT_P4_PUEN_P21 (0x1 << 21) -#define PORT_P4_PUEN_P21_VAL(val) (((val) & 0x1) << 21) -#define PORT_P4_PUEN_P21_GET(val) ((((val) & PORT_P4_PUEN_P21) >> 21) & 0x1) -#define PORT_P4_PUEN_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P21) | (((val) & 0x1) << 21)) -/* Pull Up Device Enable at Port 4 Bit # (20) */ -#define PORT_P4_PUEN_P20 (0x1 << 20) -#define PORT_P4_PUEN_P20_VAL(val) (((val) & 0x1) << 20) -#define PORT_P4_PUEN_P20_GET(val) ((((val) & PORT_P4_PUEN_P20) >> 20) & 0x1) -#define PORT_P4_PUEN_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P20) | (((val) & 0x1) << 20)) -/* Pull Up Device Enable at Port 4 Bit # (19) */ -#define PORT_P4_PUEN_P19 (0x1 << 19) -#define PORT_P4_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -#define PORT_P4_PUEN_P19_GET(val) ((((val) & PORT_P4_PUEN_P19) >> 19) & 0x1) -#define PORT_P4_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P19) | (((val) & 0x1) << 19)) -/* Pull Up Device Enable at Port 4 Bit # (18) */ -#define PORT_P4_PUEN_P18 (0x1 << 18) -#define PORT_P4_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -#define PORT_P4_PUEN_P18_GET(val) ((((val) & PORT_P4_PUEN_P18) >> 18) & 0x1) -#define PORT_P4_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P18) | (((val) & 0x1) << 18)) -/* Pull Up Device Enable at Port 4 Bit # (17) */ -#define PORT_P4_PUEN_P17 (0x1 << 17) -#define PORT_P4_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -#define PORT_P4_PUEN_P17_GET(val) ((((val) & PORT_P4_PUEN_P17) >> 17) & 0x1) -#define PORT_P4_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P17) | (((val) & 0x1) << 17)) -/* Pull Up Device Enable at Port 4 Bit # (16) */ -#define PORT_P4_PUEN_P16 (0x1 << 16) -#define PORT_P4_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -#define PORT_P4_PUEN_P16_GET(val) ((((val) & PORT_P4_PUEN_P16) >> 16) & 0x1) -#define PORT_P4_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P16) | (((val) & 0x1) << 16)) -/* Pull Up Device Enable at Port 4 Bit # (15) */ -#define PORT_P4_PUEN_P15 (0x1 << 15) -#define PORT_P4_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -#define PORT_P4_PUEN_P15_GET(val) ((((val) & PORT_P4_PUEN_P15) >> 15) & 0x1) -#define PORT_P4_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P15) | (((val) & 0x1) << 15)) -/* Pull Up Device Enable at Port 4 Bit # (14) */ -#define PORT_P4_PUEN_P14 (0x1 << 14) -#define PORT_P4_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -#define PORT_P4_PUEN_P14_GET(val) ((((val) & PORT_P4_PUEN_P14) >> 14) & 0x1) -#define PORT_P4_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P14) | (((val) & 0x1) << 14)) -/* Pull Up Device Enable at Port 4 Bit # (13) */ -#define PORT_P4_PUEN_P13 (0x1 << 13) -#define PORT_P4_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -#define PORT_P4_PUEN_P13_GET(val) ((((val) & PORT_P4_PUEN_P13) >> 13) & 0x1) -#define PORT_P4_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P13) | (((val) & 0x1) << 13)) -/* Pull Up Device Enable at Port 4 Bit # (12) */ -#define PORT_P4_PUEN_P12 (0x1 << 12) -#define PORT_P4_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -#define PORT_P4_PUEN_P12_GET(val) ((((val) & PORT_P4_PUEN_P12) >> 12) & 0x1) -#define PORT_P4_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P12) | (((val) & 0x1) << 12)) -/* Pull Up Device Enable at Port 4 Bit # (11) */ -#define PORT_P4_PUEN_P11 (0x1 << 11) -#define PORT_P4_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -#define PORT_P4_PUEN_P11_GET(val) ((((val) & PORT_P4_PUEN_P11) >> 11) & 0x1) -#define PORT_P4_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P11) | (((val) & 0x1) << 11)) -/* Pull Up Device Enable at Port 4 Bit # (10) */ -#define PORT_P4_PUEN_P10 (0x1 << 10) -#define PORT_P4_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -#define PORT_P4_PUEN_P10_GET(val) ((((val) & PORT_P4_PUEN_P10) >> 10) & 0x1) -#define PORT_P4_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P10) | (((val) & 0x1) << 10)) -/* Pull Up Device Enable at Port 4 Bit # (9) */ -#define PORT_P4_PUEN_P9 (0x1 << 9) -#define PORT_P4_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -#define PORT_P4_PUEN_P9_GET(val) ((((val) & PORT_P4_PUEN_P9) >> 9) & 0x1) -#define PORT_P4_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P9) | (((val) & 0x1) << 9)) -/* Pull Up Device Enable at Port 4 Bit # (8) */ -#define PORT_P4_PUEN_P8 (0x1 << 8) -#define PORT_P4_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -#define PORT_P4_PUEN_P8_GET(val) ((((val) & PORT_P4_PUEN_P8) >> 8) & 0x1) -#define PORT_P4_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P8) | (((val) & 0x1) << 8)) -/* Pull Up Device Enable at Port 4 Bit # (7) */ -#define PORT_P4_PUEN_P7 (0x1 << 7) -#define PORT_P4_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -#define PORT_P4_PUEN_P7_GET(val) ((((val) & PORT_P4_PUEN_P7) >> 7) & 0x1) -#define PORT_P4_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P7) | (((val) & 0x1) << 7)) -/* Pull Up Device Enable at Port 4 Bit # (6) */ -#define PORT_P4_PUEN_P6 (0x1 << 6) -#define PORT_P4_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -#define PORT_P4_PUEN_P6_GET(val) ((((val) & PORT_P4_PUEN_P6) >> 6) & 0x1) -#define PORT_P4_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P6) | (((val) & 0x1) << 6)) -/* Pull Up Device Enable at Port 4 Bit # (5) */ -#define PORT_P4_PUEN_P5 (0x1 << 5) -#define PORT_P4_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -#define PORT_P4_PUEN_P5_GET(val) ((((val) & PORT_P4_PUEN_P5) >> 5) & 0x1) -#define PORT_P4_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P5) | (((val) & 0x1) << 5)) -/* Pull Up Device Enable at Port 4 Bit # (4) */ -#define PORT_P4_PUEN_P4 (0x1 << 4) -#define PORT_P4_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -#define PORT_P4_PUEN_P4_GET(val) ((((val) & PORT_P4_PUEN_P4) >> 4) & 0x1) -#define PORT_P4_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P4) | (((val) & 0x1) << 4)) -/* Pull Up Device Enable at Port 4 Bit # (3) */ -#define PORT_P4_PUEN_P3 (0x1 << 3) -#define PORT_P4_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -#define PORT_P4_PUEN_P3_GET(val) ((((val) & PORT_P4_PUEN_P3) >> 3) & 0x1) -#define PORT_P4_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P3) | (((val) & 0x1) << 3)) -/* Pull Up Device Enable at Port 4 Bit # (2) */ -#define PORT_P4_PUEN_P2 (0x1 << 2) -#define PORT_P4_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -#define PORT_P4_PUEN_P2_GET(val) ((((val) & PORT_P4_PUEN_P2) >> 2) & 0x1) -#define PORT_P4_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P2) | (((val) & 0x1) << 2)) -/* Pull Up Device Enable at Port 4 Bit # (1) */ -#define PORT_P4_PUEN_P1 (0x1 << 1) -#define PORT_P4_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -#define PORT_P4_PUEN_P1_GET(val) ((((val) & PORT_P4_PUEN_P1) >> 1) & 0x1) -#define PORT_P4_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P1) | (((val) & 0x1) << 1)) -/* Pull Up Device Enable at Port 4 Bit # (0) */ -#define PORT_P4_PUEN_P0 (0x1) -#define PORT_P4_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -#define PORT_P4_PUEN_P0_GET(val) ((((val) & PORT_P4_PUEN_P0) >> 0) & 0x1) -#define PORT_P4_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P0) | (((val) & 0x1) << 0)) - -#endif /* __PORT_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h deleted file mode 100644 index 4ea2f5a685..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h +++ /dev/null @@ -1,624 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __SSC_REG_H -#define __SSC_REG_H - -/** SSC register structure */ -struct svip_reg_ssc { - volatile unsigned long clc; /* 0x00 */ - volatile unsigned long pisel; /* 0x04 */ - volatile unsigned long id; /* 0x08 */ - volatile unsigned long reserved0; /* 0x0c */ - volatile unsigned long mcon; /* 0x10 */ - volatile unsigned long state; /* 0x14 */ - volatile unsigned long whbstate; /* 0x18 */ - volatile unsigned long reserved1; /* 0x1c */ - volatile unsigned long tb; /* 0x20 */ - volatile unsigned long rb; /* 0x24 */ - volatile unsigned long reserved2[2]; /* 0x28 */ - volatile unsigned long rxfcon; /* 0x30 */ - volatile unsigned long txfcon; /* 0x34 */ - volatile unsigned long fstat; /* 0x38 */ - volatile unsigned long reserved3; /* 0x3c */ - volatile unsigned long br; /* 0x40 */ - volatile unsigned long brstat; /* 0x44 */ - volatile unsigned long reserved4[6]; /* 0x48 */ - volatile unsigned long sfcon; /* 0x60 */ - volatile unsigned long sfstat; /* 0x64 */ - volatile unsigned long reserved5[2]; /* 0x68 */ - volatile unsigned long gpocon; /* 0x70 */ - volatile unsigned long gpostat; /* 0x74 */ - volatile unsigned long whbgpostat; /* 0x78 */ - volatile unsigned long reserved6; /* 0x7c */ - volatile unsigned long rxreq; /* 0x80 */ - volatile unsigned long rxcnt; /* 0x84 */ - volatile unsigned long reserved7[25]; /* 0x88 */ - volatile unsigned long dma_con; /* 0xEC */ - volatile unsigned long reserved8; /* 0xf0 */ - volatile unsigned long irnen; /* 0xF4 */ - volatile unsigned long irncr; /* 0xF8 */ - volatile unsigned long irnicr; /* 0xFC */ -}; - -/******************************************************************************* - * CLC Register - ******************************************************************************/ - -/* Clock Divider for Sleep Mode (23:16) */ -#define SSC_CLC_SMC (0xff << 16) -#define SSC_CLC_SMC_VAL(val) (((val) & 0xff) << 16) -#define SSC_CLC_SMC_GET(val) ((((val) & SSC_CLC_SMC) >> 16) & 0xff) -#define SSC_CLC_SMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SMC) | (((val) & 0xff) << 16)) -/* Clock Divider for Normal Run Mode (15:8) */ -#define SSC_CLC_RMC (0xff << 8) -#define SSC_CLC_RMC_VAL(val) (((val) & 0xff) << 8) -#define SSC_CLC_RMC_GET(val) ((((val) & SSC_CLC_RMC) >> 8) & 0xff) -#define SSC_CLC_RMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_RMC) | (((val) & 0xff) << 8)) -/* Fast Shut-Off Enable Bit (5) */ -#define SSC_CLC_FSOE (0x1 << 5) -#define SSC_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) -#define SSC_CLC_FSOE_GET(val) ((((val) & SSC_CLC_FSOE) >> 5) & 0x1) -#define SSC_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~SSC_CLC_FSOE) | (((val) & 0x1) << 5)) -/* Suspend Bit Write Enable for OCDS (4) */ -#define SSC_CLC_SBWE (0x1 << 4) -#define SSC_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) -#define SSC_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~SSC_CLC_SBWE) | (val) & 1) << 4) -/* External Request Disable (3) */ -#define SSC_CLC_EDIS (0x1 << 3) -#define SSC_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) -#define SSC_CLC_EDIS_GET(val) ((((val) & SSC_CLC_EDIS) >> 3) & 0x1) -#define SSC_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~SSC_CLC_EDIS) | (((val) & 0x1) << 3)) -/* Suspend Enable Bit for OCDS (2) */ -#define SSC_CLC_SPEN (0x1 << 2) -#define SSC_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) -#define SSC_CLC_SPEN_GET(val) ((((val) & SSC_CLC_SPEN) >> 2) & 0x1) -#define SSC_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SPEN) | (((val) & 0x1) << 2)) -/* Disable Status Bit (1) */ -#define SSC_CLC_DISS (0x1 << 1) -#define SSC_CLC_DISS_GET(val) ((((val) & SSC_CLC_DISS) >> 1) & 0x1) -/* Disable Request Bit (0) */ -#define SSC_CLC_DISR (0x1) -#define SSC_CLC_DISR_VAL(val) (((val) & 0x1) << 0) -#define SSC_CLC_DISR_GET(val) ((((val) & SSC_CLC_DISR) >> 0) & 0x1) -#define SSC_CLC_DISR_SET(reg,val) (reg) = ((reg & ~SSC_CLC_DISR) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * ID Register - ******************************************************************************/ - -/* Transmit FIFO Size (29:24) */ -#define SSC_ID_TXFS (0x3f << 24) -#define SSC_ID_TXFS_GET(val) ((((val) & SSC_ID_TXFS) >> 24) & 0x3f) -/* Receive FIFO Size (21:16) */ -#define SSC_ID_RXFS (0x3f << 16) -#define SSC_ID_RXFS_GET(val) ((((val) & SSC_ID_RXFS) >> 16) & 0x3f) -/* Module ID (15:8) */ -#define SSC_ID_ID (0xff << 8) -#define SSC_ID_ID_GET(val) ((((val) & SSC_ID_ID) >> 8) & 0xff) -/* Configuration (5) */ -#define SSC_ID_CFG (0x1 << 5) -#define SSC_ID_CFG_GET(val) ((((val) & SSC_ID_CFG) >> 5) & 0x1) -/* Revision (4:0) */ -#define SSC_ID_REV (0x1f) -#define SSC_ID_REV_GET(val) ((((val) & SSC_ID_REV) >> 0) & 0x1f) - -/******************************************************************************* - * MCON Register - ******************************************************************************/ - -/* Echo Mode (24) */ -#define SSC_MCON_EM (0x1 << 24) -#define SSC_MCON_EM_VAL(val) (((val) & 0x1) << 24) -#define SSC_MCON_EM_GET(val) ((((val) & SSC_MCON_EM) >> 24) & 0x1) -#define SSC_MCON_EM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_EM) | (((val) & 0x1) << 24)) -/* Idle Bit Value (23) */ -#define SSC_MCON_IDLE (0x1 << 23) -#define SSC_MCON_IDLE_VAL(val) (((val) & 0x1) << 23) -#define SSC_MCON_IDLE_GET(val) ((((val) & SSC_MCON_IDLE) >> 23) & 0x1) -#define SSC_MCON_IDLE_SET(reg,val) (reg) = ((reg & ~SSC_MCON_IDLE) | (((val) & 0x1) << 23)) -/* Enable Byte Valid Control (22) */ -#define SSC_MCON_ENBV (0x1 << 22) -#define SSC_MCON_ENBV_VAL(val) (((val) & 0x1) << 22) -#define SSC_MCON_ENBV_GET(val) ((((val) & SSC_MCON_ENBV) >> 22) & 0x1) -#define SSC_MCON_ENBV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_ENBV) | (((val) & 0x1) << 22)) -/* Data Width Selection (20:16) */ -#define SSC_MCON_BM (0x1f << 16) -#define SSC_MCON_BM_VAL(val) (((val) & 0x1f) << 16) -#define SSC_MCON_BM_GET(val) ((((val) & SSC_MCON_BM) >> 16) & 0x1f) -#define SSC_MCON_BM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_BM) | (((val) & 0x1f) << 16)) -/* Receive Underflow Error Enable (12) */ -#define SSC_MCON_RUEN (0x1 << 12) -#define SSC_MCON_RUEN_VAL(val) (((val) & 0x1) << 12) -#define SSC_MCON_RUEN_GET(val) ((((val) & SSC_MCON_RUEN) >> 12) & 0x1) -#define SSC_MCON_RUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RUEN) | (((val) & 0x1) << 12)) -/* Transmit Underflow Error Enable (11) */ -#define SSC_MCON_TUEN (0x1 << 11) -#define SSC_MCON_TUEN_VAL(val) (((val) & 0x1) << 11) -#define SSC_MCON_TUEN_GET(val) ((((val) & SSC_MCON_TUEN) >> 11) & 0x1) -#define SSC_MCON_TUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TUEN) | (((val) & 0x1) << 11)) -/* Abort Error Enable (10) */ -#define SSC_MCON_AEN (0x1 << 10) -#define SSC_MCON_AEN_VAL(val) (((val) & 0x1) << 10) -#define SSC_MCON_AEN_GET(val) ((((val) & SSC_MCON_AEN) >> 10) & 0x1) -#define SSC_MCON_AEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_AEN) | (((val) & 0x1) << 10)) -/* Receive Overflow Error Enable (9) */ -#define SSC_MCON_REN (0x1 << 9) -#define SSC_MCON_REN_VAL(val) (((val) & 0x1) << 9) -#define SSC_MCON_REN_GET(val) ((((val) & SSC_MCON_REN) >> 9) & 0x1) -#define SSC_MCON_REN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_REN) | (((val) & 0x1) << 9)) -/* Transmit Overflow Error Enable (8) */ -#define SSC_MCON_TEN (0x1 << 8) -#define SSC_MCON_TEN_VAL(val) (((val) & 0x1) << 8) -#define SSC_MCON_TEN_GET(val) ((((val) & SSC_MCON_TEN) >> 8) & 0x1) -#define SSC_MCON_TEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TEN) | (((val) & 0x1) << 8)) -/* Loop Back Control (7) */ -#define SSC_MCON_LB (0x1 << 7) -#define SSC_MCON_LB_VAL(val) (((val) & 0x1) << 7) -#define SSC_MCON_LB_GET(val) ((((val) & SSC_MCON_LB) >> 7) & 0x1) -#define SSC_MCON_LB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_LB) | (((val) & 0x1) << 7)) -/* Clock Polarity Control (6) */ -#define SSC_MCON_PO (0x1 << 6) -#define SSC_MCON_PO_VAL(val) (((val) & 0x1) << 6) -#define SSC_MCON_PO_GET(val) ((((val) & SSC_MCON_PO) >> 6) & 0x1) -#define SSC_MCON_PO_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PO) | (((val) & 0x1) << 6)) -/* Clock Phase Control (5) */ -#define SSC_MCON_PH (0x1 << 5) -#define SSC_MCON_PH_VAL(val) (((val) & 0x1) << 5) -#define SSC_MCON_PH_GET(val) ((((val) & SSC_MCON_PH) >> 5) & 0x1) -#define SSC_MCON_PH_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PH) | (((val) & 0x1) << 5)) -/* Heading Control (4) */ -#define SSC_MCON_HB (0x1 << 4) -#define SSC_MCON_HB_VAL(val) (((val) & 0x1) << 4) -#define SSC_MCON_HB_GET(val) ((((val) & SSC_MCON_HB) >> 4) & 0x1) -#define SSC_MCON_HB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_HB) | (((val) & 0x1) << 4)) -/* Chip Select Enable (3) */ -#define SSC_MCON_CSBEN (0x1 << 3) -#define SSC_MCON_CSBEN_VAL(val) (((val) & 0x1) << 3) -#define SSC_MCON_CSBEN_GET(val) ((((val) & SSC_MCON_CSBEN) >> 3) & 0x1) -#define SSC_MCON_CSBEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBEN) | (((val) & 0x1) << 3)) -/* Chip Select Invert (2) */ -#define SSC_MCON_CSBINV (0x1 << 2) -#define SSC_MCON_CSBINV_VAL(val) (((val) & 0x1) << 2) -#define SSC_MCON_CSBINV_GET(val) ((((val) & SSC_MCON_CSBINV) >> 2) & 0x1) -#define SSC_MCON_CSBINV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBINV) | (((val) & 0x1) << 2)) -/* Receive Off (1) */ -#define SSC_MCON_RXOFF (0x1 << 1) -#define SSC_MCON_RXOFF_VAL(val) (((val) & 0x1) << 1) -#define SSC_MCON_RXOFF_GET(val) ((((val) & SSC_MCON_RXOFF) >> 1) & 0x1) -#define SSC_MCON_RXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RXOFF) | (((val) & 0x1) << 1)) -/* Transmit Off (0) */ -#define SSC_MCON_TXOFF (0x1) -#define SSC_MCON_TXOFF_VAL(val) (((val) & 0x1) << 0) -#define SSC_MCON_TXOFF_GET(val) ((((val) & SSC_MCON_TXOFF) >> 0) & 0x1) -#define SSC_MCON_TXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TXOFF) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * STATE Register - ******************************************************************************/ - -/* Receive End-of-Message (31) */ -#define SSC_STATE_RXEOM (0x1 << 31) -#define SSC_STATE_RXEOM_GET(val) ((((val) & SSC_STATE_RXEOM) >> 31) & 0x1) -/* Receive Byte Valid (30:28) */ -#define SSC_STATE_RXBV (0x7 << 28) -#define SSC_STATE_RXBV_GET(val) ((((val) & SSC_STATE_RXBV) >> 28) & 0x7) -/* Transmit End-of-Message (27) */ -#define SSC_STATE_TXEOM (0x1 << 27) -#define SSC_STATE_TXEOM_GET(val) ((((val) & SSC_STATE_TXEOM) >> 27) & 0x1) -/* Transmit Byte Valid (26:24) */ -#define SSC_STATE_TXBV (0x7 << 24) -#define SSC_STATE_TXBV_GET(val) ((((val) & SSC_STATE_TXBV) >> 24) & 0x7) -/* Bit Count Field (20:16) */ -#define SSC_STATE_BC (0x1f << 16) -#define SSC_STATE_BC_GET(val) ((((val) & SSC_STATE_BC) >> 16) & 0x1f) -/* Busy Flag (13) */ -#define SSC_STATE_BSY (0x1 << 13) -#define SSC_STATE_BSY_GET(val) ((((val) & SSC_STATE_BSY) >> 13) & 0x1) -/* Receive Underflow Error Flag (12) */ -#define SSC_STATE_RUE (0x1 << 12) -#define SSC_STATE_RUE_GET(val) ((((val) & SSC_STATE_RUE) >> 12) & 0x1) -/* Transmit Underflow Error Flag (11) */ -#define SSC_STATE_TUE (0x1 << 11) -#define SSC_STATE_TUE_GET(val) ((((val) & SSC_STATE_TUE) >> 11) & 0x1) -/* Abort Error Flag (10) */ -#define SSC_STATE_AE (0x1 << 10) -#define SSC_STATE_AE_GET(val) ((((val) & SSC_STATE_AE) >> 10) & 0x1) -/* Receive Error Flag (9) */ -#define SSC_STATE_RE (0x1 << 9) -#define SSC_STATE_RE_GET(val) ((((val) & SSC_STATE_RE) >> 9) & 0x1) -/* Transmit Error Flag (8) */ -#define SSC_STATE_TE (0x1 << 8) -#define SSC_STATE_TE_GET(val) ((((val) & SSC_STATE_TE) >> 8) & 0x1) -/* Mode Error Flag (7) */ -#define SSC_STATE_ME (0x1 << 7) -#define SSC_STATE_ME_GET(val) ((((val) & SSC_STATE_ME) >> 7) & 0x1) -/* Slave Selected (2) */ -#define SSC_STATE_SSEL (0x1 << 2) -#define SSC_STATE_SSEL_GET(val) ((((val) & SSC_STATE_SSEL) >> 2) & 0x1) -/* Master Select Bit (1) */ -#define SSC_STATE_MS (0x1 << 1) -#define SSC_STATE_MS_GET(val) ((((val) & SSC_STATE_MS) >> 1) & 0x1) -/* Enable Bit (0) */ -#define SSC_STATE_EN (0x1) -#define SSC_STATE_EN_GET(val) ((((val) & SSC_STATE_EN) >> 0) & 0x1) - -/******************************************************************************* - * WHBSTATE Register - ******************************************************************************/ - -/* Set Transmit Underflow Error Flag Bit (15) */ -#define SSC_WHBSTATE_SETTUE (0x1 << 15) -#define SSC_WHBSTATE_SETTUE_VAL(val) (((val) & 0x1) << 15) -#define SSC_WHBSTATE_SETTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTUE) | (val) & 1) << 15) -/* Set Abort Error Flag Bit (14) */ -#define SSC_WHBSTATE_SETAE (0x1 << 14) -#define SSC_WHBSTATE_SETAE_VAL(val) (((val) & 0x1) << 14) -#define SSC_WHBSTATE_SETAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETAE) | (val) & 1) << 14) -/* Set Receive Error Flag Bit (13) */ -#define SSC_WHBSTATE_SETRE (0x1 << 13) -#define SSC_WHBSTATE_SETRE_VAL(val) (((val) & 0x1) << 13) -#define SSC_WHBSTATE_SETRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRE) | (val) & 1) << 13) -/* Set Transmit Error Flag Bit (12) */ -#define SSC_WHBSTATE_SETTE (0x1 << 12) -#define SSC_WHBSTATE_SETTE_VAL(val) (((val) & 0x1) << 12) -#define SSC_WHBSTATE_SETTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTE) | (val) & 1) << 12) -/* Clear Transmit Underflow Error Flag Bit (11) */ -#define SSC_WHBSTATE_CLRTUE (0x1 << 11) -#define SSC_WHBSTATE_CLRTUE_VAL(val) (((val) & 0x1) << 11) -#define SSC_WHBSTATE_CLRTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTUE) | (val) & 1) << 11) -/* Clear Abort Error Flag Bit (10) */ -#define SSC_WHBSTATE_CLRAE (0x1 << 10) -#define SSC_WHBSTATE_CLRAE_VAL(val) (((val) & 0x1) << 10) -#define SSC_WHBSTATE_CLRAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRAE) | (val) & 1) << 10) -/* Clear Receive Error Flag Bit (9) */ -#define SSC_WHBSTATE_CLRRE (0x1 << 9) -#define SSC_WHBSTATE_CLRRE_VAL(val) (((val) & 0x1) << 9) -#define SSC_WHBSTATE_CLRRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRE) | (val) & 1) << 9) -/* Clear Transmit Error Flag Bit (8) */ -#define SSC_WHBSTATE_CLRTE (0x1 << 8) -#define SSC_WHBSTATE_CLRTE_VAL(val) (((val) & 0x1) << 8) -#define SSC_WHBSTATE_CLRTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTE) | (val) & 1) << 8) -/* Set Mode Error Flag Bit (7) */ -#define SSC_WHBSTATE_SETME (0x1 << 7) -#define SSC_WHBSTATE_SETME_VAL(val) (((val) & 0x1) << 7) -#define SSC_WHBSTATE_SETME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETME) | (val) & 1) << 7) -/* Clear Mode Error Flag Bit (6) */ -#define SSC_WHBSTATE_CLRME (0x1 << 6) -#define SSC_WHBSTATE_CLRME_VAL(val) (((val) & 0x1) << 6) -#define SSC_WHBSTATE_CLRME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRME) | (val) & 1) << 6) -/* Set Receive Underflow Error Bit (5) */ -#define SSC_WHBSTATE_SETRUE (0x1 << 5) -#define SSC_WHBSTATE_SETRUE_VAL(val) (((val) & 0x1) << 5) -#define SSC_WHBSTATE_SETRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRUE) | (val) & 1) << 5) -/* Clear Receive Underflow Error Bit (4) */ -#define SSC_WHBSTATE_CLRRUE (0x1 << 4) -#define SSC_WHBSTATE_CLRRUE_VAL(val) (((val) & 0x1) << 4) -#define SSC_WHBSTATE_CLRRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRUE) | (val) & 1) << 4) -/* Set Master Select Bit (3) */ -#define SSC_WHBSTATE_SETMS (0x1 << 3) -#define SSC_WHBSTATE_SETMS_VAL(val) (((val) & 0x1) << 3) -#define SSC_WHBSTATE_SETMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETMS) | (val) & 1) << 3) -/* Clear Master Select Bit (2) */ -#define SSC_WHBSTATE_CLRMS (0x1 << 2) -#define SSC_WHBSTATE_CLRMS_VAL(val) (((val) & 0x1) << 2) -#define SSC_WHBSTATE_CLRMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRMS) | (val) & 1) << 2) -/* Set Enable Bit (1) */ -#define SSC_WHBSTATE_SETEN (0x1 << 1) -#define SSC_WHBSTATE_SETEN_VAL(val) (((val) & 0x1) << 1) -#define SSC_WHBSTATE_SETEN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETEN) | (val) & 1) << 1) -/* Clear Enable Bit (0) */ -#define SSC_WHBSTATE_CLREN (0x1) -#define SSC_WHBSTATE_CLREN_VAL(val) (((val) & 0x1) << 0) -#define SSC_WHBSTATE_CLREN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLREN) | (val) & 1) << 0) - -/******************************************************************************* - * TB Register - ******************************************************************************/ - -/* Transmit Data Register Value (31:0) */ -#define SSC_TB_TB_VAL (0xFFFFFFFFL) -#define SSC_TB_TB_VAL_VAL(val) (((val) & 0xFFFFFFFFL) << 0) -#define SSC_TB_TB_VAL_GET(val) ((((val) & SSC_TB_TB_VAL) >> 0) & 0xFFFFFFFFL) -#define SSC_TB_TB_VAL_SET(reg,val) (reg) = ((reg & ~SSC_TB_TB_VAL) | (((val) & 0xFFFFFFFFL) << 0)) - -/******************************************************************************* - * RB Register - ******************************************************************************/ - -/* Receive Data Register Value (31:0) */ -#define SSC_RB_RB_VAL (0xFFFFFFFFL) -#define SSC_RB_RB_VAL_GET(val) ((((val) & SSC_RB_RB_VAL) >> 0) & 0xFFFFFFFFL) - -/******************************************************************************* - * FSTAT Register - ******************************************************************************/ - -/* Transmit FIFO Filling Level (13:8) */ -#define SSC_FSTAT_TXFFL (0x3f << 8) -#define SSC_FSTAT_TXFFL_GET(val) ((((val) & SSC_FSTAT_TXFFL) >> 8) & 0x3f) -/* Receive FIFO Filling Level (5:0) */ -#define SSC_FSTAT_RXFFL (0x3f) -#define SSC_FSTAT_RXFFL_GET(val) ((((val) & SSC_FSTAT_RXFFL) >> 0) & 0x3f) - -/******************************************************************************* - * PISEL Register - ******************************************************************************/ - -/* Slave Mode Clock Input Select (2) */ -#define SSC_PISEL_CIS (0x1 << 2) -#define SSC_PISEL_CIS_VAL(val) (((val) & 0x1) << 2) -#define SSC_PISEL_CIS_GET(val) ((((val) & SSC_PISEL_CIS) >> 2) & 0x1) -#define SSC_PISEL_CIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_CIS) | (((val) & 0x1) << 2)) -/* Slave Mode Receiver Input Select (1) */ -#define SSC_PISEL_SIS (0x1 << 1) -#define SSC_PISEL_SIS_VAL(val) (((val) & 0x1) << 1) -#define SSC_PISEL_SIS_GET(val) ((((val) & SSC_PISEL_SIS) >> 1) & 0x1) -#define SSC_PISEL_SIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_SIS) | (((val) & 0x1) << 1)) -/* Master Mode Receiver Input Select (0) */ -#define SSC_PISEL_MIS (0x1) -#define SSC_PISEL_MIS_VAL(val) (((val) & 0x1) << 0) -#define SSC_PISEL_MIS_GET(val) ((((val) & SSC_PISEL_MIS) >> 0) & 0x1) -#define SSC_PISEL_MIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_MIS) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * RXFCON Register - ******************************************************************************/ - -/* Receive FIFO Interrupt Trigger Level (13:8) */ -#define SSC_RXFCON_RXFITL (0x3f << 8) -#define SSC_RXFCON_RXFITL_VAL(val) (((val) & 0x3f) << 8) -#define SSC_RXFCON_RXFITL_GET(val) ((((val) & SSC_RXFCON_RXFITL) >> 8) & 0x3f) -#define SSC_RXFCON_RXFITL_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFITL) | (((val) & 0x3f) << 8)) -/* Receive FIFO Flush (1) */ -#define SSC_RXFCON_RXFLU (0x1 << 1) -#define SSC_RXFCON_RXFLU_VAL(val) (((val) & 0x1) << 1) -#define SSC_RXFCON_RXFLU_SET(reg,val) (reg) = (((reg & ~SSC_RXFCON_RXFLU) | (val) & 1) << 1) -/* Receive FIFO Enable (0) */ -#define SSC_RXFCON_RXFEN (0x1) -#define SSC_RXFCON_RXFEN_VAL(val) (((val) & 0x1) << 0) -#define SSC_RXFCON_RXFEN_GET(val) ((((val) & SSC_RXFCON_RXFEN) >> 0) & 0x1) -#define SSC_RXFCON_RXFEN_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFEN) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * TXFCON Register - ******************************************************************************/ - -/* Transmit FIFO Interrupt Trigger Level (13:8) */ -#define SSC_TXFCON_TXFITL (0x3f << 8) -#define SSC_TXFCON_TXFITL_VAL(val) (((val) & 0x3f) << 8) -#define SSC_TXFCON_TXFITL_GET(val) ((((val) & SSC_TXFCON_TXFITL) >> 8) & 0x3f) -#define SSC_TXFCON_TXFITL_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFITL) | (((val) & 0x3f) << 8)) -/* Transmit FIFO Flush (1) */ -#define SSC_TXFCON_TXFLU (0x1 << 1) -#define SSC_TXFCON_TXFLU_VAL(val) (((val) & 0x1) << 1) -#define SSC_TXFCON_TXFLU_SET(reg,val) (reg) = (((reg & ~SSC_TXFCON_TXFLU) | (val) & 1) << 1) -/* Transmit FIFO Enable (0) */ -#define SSC_TXFCON_TXFEN (0x1) -#define SSC_TXFCON_TXFEN_VAL(val) (((val) & 0x1) << 0) -#define SSC_TXFCON_TXFEN_GET(val) ((((val) & SSC_TXFCON_TXFEN) >> 0) & 0x1) -#define SSC_TXFCON_TXFEN_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFEN) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * BR Register - ******************************************************************************/ - -/* Baudrate Timer Reload Register Value (15:0) */ -#define SSC_BR_BR_VAL (0xffff) -#define SSC_BR_BR_VAL_VAL(val) (((val) & 0xffff) << 0) -#define SSC_BR_BR_VAL_GET(val) ((((val) & SSC_BR_BR_VAL) >> 0) & 0xffff) -#define SSC_BR_BR_VAL_SET(reg,val) (reg) = ((reg & ~SSC_BR_BR_VAL) | (((val) & 0xffff) << 0)) - -/******************************************************************************* - * BRSTAT Register - ******************************************************************************/ - -/* Baudrate Timer Register Value (15:0) */ -#define SSC_BRSTAT_BT_VAL (0xffff) -#define SSC_BRSTAT_BT_VAL_GET(val) ((((val) & SSC_BRSTAT_BT_VAL) >> 0) & 0xffff) - -/******************************************************************************* - * SFCON Register - ******************************************************************************/ - -/* Pause Length (31:22) */ -#define SSC_SFCON_PLEN (0x3ff << 22) -#define SSC_SFCON_PLEN_VAL(val) (((val) & 0x3ff) << 22) -#define SSC_SFCON_PLEN_GET(val) ((((val) & SSC_SFCON_PLEN) >> 22) & 0x3ff) -#define SSC_SFCON_PLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_PLEN) | (((val) & 0x3ff) << 22)) -/* Stop After Pause (20) */ -#define SSC_SFCON_STOP (0x1 << 20) -#define SSC_SFCON_STOP_VAL(val) (((val) & 0x1) << 20) -#define SSC_SFCON_STOP_GET(val) ((((val) & SSC_SFCON_STOP) >> 20) & 0x1) -#define SSC_SFCON_STOP_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_STOP) | (((val) & 0x1) << 20)) -/* Idle Clock Configuration (19:18) */ -#define SSC_SFCON_ICLK (0x3 << 18) -#define SSC_SFCON_ICLK_VAL(val) (((val) & 0x3) << 18) -#define SSC_SFCON_ICLK_GET(val) ((((val) & SSC_SFCON_ICLK) >> 18) & 0x3) -#define SSC_SFCON_ICLK_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_ICLK) | (((val) & 0x3) << 18)) -/* Idle Data Configuration (17:16) */ -#define SSC_SFCON_IDAT (0x3 << 16) -#define SSC_SFCON_IDAT_VAL(val) (((val) & 0x3) << 16) -#define SSC_SFCON_IDAT_GET(val) ((((val) & SSC_SFCON_IDAT) >> 16) & 0x3) -#define SSC_SFCON_IDAT_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IDAT) | (((val) & 0x3) << 16)) -/* Data Length (15:4) */ -#define SSC_SFCON_DLEN (0xfff << 4) -#define SSC_SFCON_DLEN_VAL(val) (((val) & 0xfff) << 4) -#define SSC_SFCON_DLEN_GET(val) ((((val) & SSC_SFCON_DLEN) >> 4) & 0xfff) -#define SSC_SFCON_DLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_DLEN) | (((val) & 0xfff) << 4)) -/* Enable Interrupt After Pause (3) */ -#define SSC_SFCON_IAEN (0x1 << 3) -#define SSC_SFCON_IAEN_VAL(val) (((val) & 0x1) << 3) -#define SSC_SFCON_IAEN_GET(val) ((((val) & SSC_SFCON_IAEN) >> 3) & 0x1) -#define SSC_SFCON_IAEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IAEN) | (((val) & 0x1) << 3)) -/* Enable Interrupt Before Pause (2) */ -#define SSC_SFCON_IBEN (0x1 << 2) -#define SSC_SFCON_IBEN_VAL(val) (((val) & 0x1) << 2) -#define SSC_SFCON_IBEN_GET(val) ((((val) & SSC_SFCON_IBEN) >> 2) & 0x1) -#define SSC_SFCON_IBEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IBEN) | (((val) & 0x1) << 2)) -/* Serial Frame Enable (0) */ -#define SSC_SFCON_SFEN (0x1) -#define SSC_SFCON_SFEN_VAL(val) (((val) & 0x1) << 0) -#define SSC_SFCON_SFEN_GET(val) ((((val) & SSC_SFCON_SFEN) >> 0) & 0x1) -#define SSC_SFCON_SFEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_SFEN) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * SFSTAT Register - ******************************************************************************/ - -/* Pause Count (31:22) */ -#define SSC_SFSTAT_PCNT (0x3ff << 22) -#define SSC_SFSTAT_PCNT_GET(val) ((((val) & SSC_SFSTAT_PCNT) >> 22) & 0x3ff) -/* Data Bit Count (15:4) */ -#define SSC_SFSTAT_DCNT (0xfff << 4) -#define SSC_SFSTAT_DCNT_GET(val) ((((val) & SSC_SFSTAT_DCNT) >> 4) & 0xfff) -/* Pause Busy (1) */ -#define SSC_SFSTAT_PBSY (0x1 << 1) -#define SSC_SFSTAT_PBSY_GET(val) ((((val) & SSC_SFSTAT_PBSY) >> 1) & 0x1) -/* Data Busy (0) */ -#define SSC_SFSTAT_DBSY (0x1) -#define SSC_SFSTAT_DBSY_GET(val) ((((val) & SSC_SFSTAT_DBSY) >> 0) & 0x1) - -/******************************************************************************* - * GPOCON Register - ******************************************************************************/ - -/* Output OUTn Is Chip Select (15:8) */ -#define SSC_GPOCON_ISCSBN (0xff << 8) -#define SSC_GPOCON_ISCSBN_VAL(val) (((val) & 0xff) << 8) -#define SSC_GPOCON_ISCSBN_GET(val) ((((val) & SSC_GPOCON_ISCSBN) >> 8) & 0xff) -#define SSC_GPOCON_ISCSBN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_ISCSBN) | (((val) & 0xff) << 8)) -/* Invert Output OUTn (7:0) */ -#define SSC_GPOCON_INVOUTN (0xff) -#define SSC_GPOCON_INVOUTN_VAL(val) (((val) & 0xff) << 0) -#define SSC_GPOCON_INVOUTN_GET(val) ((((val) & SSC_GPOCON_INVOUTN) >> 0) & 0xff) -#define SSC_GPOCON_INVOUTN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_INVOUTN) | (((val) & 0xff) << 0)) - -/******************************************************************************* - * GPOSTAT Register - ******************************************************************************/ - -/* Output Register Bit n (7:0) */ -#define SSC_GPOSTAT_OUTN (0xff) -#define SSC_GPOSTAT_OUTN_GET(val) ((((val) & SSC_GPOSTAT_OUTN) >> 0) & 0xff) - -/******************************************************************************* - * WHBGPOSTAT - ******************************************************************************/ - -/* Set Output Register Bit n (15:8) */ -#define SSC_WHBGPOSTAT_SETOUTN (0xff << 8) -#define SSC_WHBGPOSTAT_SETOUTN_VAL(val) (((val) & 0xff) << 8) -#define SSC_WHBGPOSTAT_SETOUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_SETOUTN) | (val) & 1) << 8) -/* Clear Output Register Bit n (7:0) */ -#define SSC_WHBGPOSTAT_CLROUTN (0xff) -#define SSC_WHBGPOSTAT_CLROUTN_VAL(val) (((val) & 0xff) << 0) -#define SSC_WHBGPOSTAT_CLROUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_CLROUTN) | (val) & 1) << 0) - -/******************************************************************************* - * RXREQ Register - ******************************************************************************/ - -/* Receive Count Value (15:0) */ -#define SSC_RXREQ_RXCNT (0xffff) -#define SSC_RXREQ_RXCNT_VAL(val) (((val) & 0xffff) << 0) -#define SSC_RXREQ_RXCNT_GET(val) ((((val) & SSC_RXREQ_RXCNT) >> 0) & 0xffff) -#define SSC_RXREQ_RXCNT_SET(reg,val) (reg) = ((reg & ~SSC_RXREQ_RXCNT) | (((val) & 0xffff) << 0)) - -/******************************************************************************* - * RXCNT Register - ******************************************************************************/ - -/* Receive To Do Value (15:0) */ -#define SSC_RXCNT_TODO (0xffff) -#define SSC_RXCNT_TODO_GET(val) ((((val) & SSC_RXCNT_TODO) >> 0) & 0xffff) - -/******************************************************************************* - * DMA_CON Register - ******************************************************************************/ - -/* Receive Class (3:2) */ -#define SSC_DMA_CON_RXCLS (0x3 << 2) -#define SSC_DMA_CON_RXCLS_VAL(val) (((val) & 0x3) << 2) -#define SSC_DMA_CON_RXCLS_GET(val) ((((val) & SSC_DMA_CON_RXCLS) >> 2) & 0x3) -#define SSC_DMA_CON_RXCLS_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXCLS) | (((val) & 0x3) << 2)) -/* Transmit Path On (1) */ -#define SSC_DMA_CON_TXON (0x1 << 1) -#define SSC_DMA_CON_TXON_VAL(val) (((val) & 0x1) << 1) -#define SSC_DMA_CON_TXON_GET(val) ((((val) & SSC_DMA_CON_TXON) >> 1) & 0x1) -#define SSC_DMA_CON_TXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_TXON) | (((val) & 0x1) << 1)) -/* Receive Path On (0) */ -#define SSC_DMA_CON_RXON (0x1) -#define SSC_DMA_CON_RXON_VAL(val) (((val) & 0x1) << 0) -#define SSC_DMA_CON_RXON_GET(val) ((((val) & SSC_DMA_CON_RXON) >> 0) & 0x1) -#define SSC_DMA_CON_RXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXON) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * IRNEN Register - ******************************************************************************/ - -/* Frame End Interrupt Request Enable (3) */ -#define SSC_IRNEN_F (0x1 << 3) -#define SSC_IRNEN_F_VAL(val) (((val) & 0x1) << 3) -#define SSC_IRNEN_F_GET(val) ((((val) & SSC_IRNEN_F) >> 3) & 0x1) -#define SSC_IRNEN_F_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_F) | (((val) & 0x1) << 3)) -/* Error Interrupt Request Enable (2) */ -#define SSC_IRNEN_E (0x1 << 2) -#define SSC_IRNEN_E_VAL(val) (((val) & 0x1) << 2) -#define SSC_IRNEN_E_GET(val) ((((val) & SSC_IRNEN_E) >> 2) & 0x1) -#define SSC_IRNEN_E_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_E) | (((val) & 0x1) << 2)) -/* Receive Interrupt Request Enable (1) */ -#define SSC_IRNEN_R (0x1 << 1) -#define SSC_IRNEN_R_VAL(val) (((val) & 0x1) << 1) -#define SSC_IRNEN_R_GET(val) ((((val) & SSC_IRNEN_R) >> 1) & 0x1) -#define SSC_IRNEN_R_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_R) | (((val) & 0x1) << 1)) -/* Transmit Interrupt Request Enable (0) */ -#define SSC_IRNEN_T (0x1) -#define SSC_IRNEN_T_VAL(val) (((val) & 0x1) << 0) -#define SSC_IRNEN_T_GET(val) ((((val) & SSC_IRNEN_T) >> 0) & 0x1) -#define SSC_IRNEN_T_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_T) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * IRNICR Register - ******************************************************************************/ - -/* Frame End Interrupt Request (3) */ -#define SSC_IRNICR_F (0x1 << 3) -#define SSC_IRNICR_F_GET(val) ((((val) & SSC_IRNICR_F) >> 3) & 0x1) -/* Error Interrupt Request (2) */ -#define SSC_IRNICR_E (0x1 << 2) -#define SSC_IRNICR_E_GET(val) ((((val) & SSC_IRNICR_E) >> 2) & 0x1) -/* Receive Interrupt Request (1) */ -#define SSC_IRNICR_R (0x1 << 1) -#define SSC_IRNICR_R_GET(val) ((((val) & SSC_IRNICR_R) >> 1) & 0x1) -/* Transmit Interrupt Request (0) */ -#define SSC_IRNICR_T (0x1) -#define SSC_IRNICR_T_GET(val) ((((val) & SSC_IRNICR_T) >> 0) & 0x1) - -/******************************************************************************* - * IRNCR Register - ******************************************************************************/ - -/* Frame End Interrupt Request (3) */ -#define SSC_IRNCR_F (0x1 << 3) -#define SSC_IRNCR_F_GET(val) ((((val) & SSC_IRNCR_F) >> 3) & 0x1) -/* Error Interrupt Request (2) */ -#define SSC_IRNCR_E (0x1 << 2) -#define SSC_IRNCR_E_GET(val) ((((val) & SSC_IRNCR_E) >> 2) & 0x1) -/* Receive Interrupt Request (1) */ -#define SSC_IRNCR_R (0x1 << 1) -#define SSC_IRNCR_R_GET(val) ((((val) & SSC_IRNCR_R) >> 1) & 0x1) -/* Transmit Interrupt Request (0) */ -#define SSC_IRNCR_T (0x1) -#define SSC_IRNCR_T_GET(val) ((((val) & SSC_IRNCR_T) >> 0) & 0x1) - -#endif /* __SSC_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h deleted file mode 100644 index 100230fa7c..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h +++ /dev/null @@ -1,130 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __STATUS_REG_H -#define __STATUS_REG_H - -#define status_r32(reg) ltq_r32(&status->reg) -#define status_w32(val, reg) ltq_w32(val, &status->reg) -#define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg) - -/** STATUS register structure */ -struct svip_reg_status { - unsigned long fuse_deu; /* 0x0000 */ - unsigned long fuse_cpu; /* 0x0004 */ - unsigned long fuse_pll; /* 0x0008 */ - unsigned long chipid; /* 0x000C */ - unsigned long config; /* 0x0010 */ - unsigned long chip_loc; /* 0x0014 */ - unsigned long fuse_spare; /* 0x0018 */ -}; - -/******************************************************************************* - * Fuse for DEU Settings - ******************************************************************************/ - -/* Fuse for Enabling the TRNG (6) */ -#define STATUS_FUSE_DEU_TRNG (0x1 << 6) -#define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1) -/* Fuse for Enabling the DES Submodule (5) */ -#define STATUS_FUSE_DEU_DES (0x1 << 5) -#define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1) -/* Fuse for Enabling the 3DES Submodule (4) */ -#define STATUS_FUSE_DEU_3DES (0x1 << 4) -#define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1) -/* Fuse for Enabling the AES Submodule (3) */ -#define STATUS_FUSE_DEU_AES (0x1 << 3) -#define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1) -/* Fuse for Enabling the HASH Submodule (2) */ -#define STATUS_FUSE_DEU_HASH (0x1 << 2) -#define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1) -/* Fuse for Enabling the ARC4 Submodule (1) */ -#define STATUS_FUSE_DEU_ARC4 (0x1 << 1) -#define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1) -/* Fuse for Enabling the DEU Module (0) */ -#define STATUS_FUSE_DEU_DEU (0x1) -#define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1) - -/******************************************************************************* - * Fuse for CPU Settings - ******************************************************************************/ - -/* Fuse for Enabling CPU5 (5) */ -#define STATUS_FUSE_CPU_CPU5 (0x1 << 5) -#define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1) -/* Fuse for Enabling the CPU4 (4) */ -#define STATUS_FUSE_CPU_CPU4 (0x1 << 4) -#define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1) -/* Fuse for Enabling the CPU3 (3) */ -#define STATUS_FUSE_CPU_CPU3 (0x1 << 3) -#define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1) -/* Fuse for Enabling the CPU2 (2) */ -#define STATUS_FUSE_CPU_CPU2 (0x1 << 2) -#define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1) -/* Fuse for Enabling the CPU1 (1) */ -#define STATUS_FUSE_CPU_CPU1 (0x1 << 1) -#define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1) -/* Fuse for Enabling the CPU0 (0) */ -#define STATUS_FUSE_CPU_CPU0 (0x1) -#define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1) - -/******************************************************************************* - * Fuse for PLL Settings - ******************************************************************************/ - -/* Fuse for Enabling PLL (7:0) */ -#define STATUS_FUSE_PLL_PLL (0xff) -#define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff) - -/******************************************************************************* - * Chip Identification Register - ******************************************************************************/ - -/* Chip Version Number (31:28) */ -#define STATUS_CHIPID_VERSION (0xf << 28) -#define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf) -/* Part Number (27:12) */ -#define STATUS_CHIPID_PART_NUMBER (0xffff << 12) -#define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff) -/* Manufacturer ID (11:1) */ -#define STATUS_CHIPID_MANID (0x7ff << 1) -#define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff) - -/******************************************************************************* - * Chip Configuration Register - ******************************************************************************/ - -/* Number of Analog Channels (8:5) */ -#define STATUS_CONFIG_ANA_CHAN (0xf << 5) -#define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf) -/* Clock Mode (4) */ -#define STATUS_CONFIG_CLK_MODE (0x1 << 1) -#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1) -/* Subversion Number (3:0) */ -#define STATUS_CONFIG_SUB_VERS (0xF) -#define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF) - -/******************************************************************************* - * Chip Location Register - ******************************************************************************/ - -/* Chip Lot ID (31:16) */ -#define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16) -#define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff) -/* Chip X Coordinate (15:8) */ -#define STATUS_CHIP_LOC_CHIP_X (0xff << 8) -#define STATUS_CHIP_LOC_CHIP_X_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_X) >> 8) & 0xff) -/* Chip Y Coordinate (7:0) */ -#define STATUS_CHIP_LOC_CHIP_Y (0xff) -#define STATUS_CHIP_LOC_CHIP_Y_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_Y) >> 0) & 0xff) - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h deleted file mode 100644 index 5c34bb6902..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h +++ /dev/null @@ -1,245 +0,0 @@ -/************************************************************************ - * - * Copyright (c) 2007 - * Infineon Technologies AG - * St. Martin Strasse 53; 81669 Muenchen; Germany - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - ************************************************************************/ - -#ifndef __SVIP_DMA_H -#define __SVIP_DMA_H - -#define LTQ_DMA_CH_ON 1 -#define LTQ_DMA_CH_OFF 0 -#define LTQ_DMA_CH_DEFAULT_WEIGHT 100; - -#define DMA_OWN 1 -#define CPU_OWN 0 -#define DMA_MAJOR 250 - -/* Descriptors */ -#define DMA_DESC_OWN_CPU 0x0 -#define DMA_DESC_OWN_DMA 0x80000000 -#define DMA_DESC_CPT_SET 0x40000000 -#define DMA_DESC_SOP_SET 0x20000000 -#define DMA_DESC_EOP_SET 0x10000000 - -struct rx_desc { - union { - struct { -#ifdef CONFIG_CPU_LITTLE_ENDIAN - volatile u32 data_length:16; - volatile u32 reserve2:7; - volatile u32 byte_offset:2; - volatile u32 reserve1:3; - volatile u32 eop:1; - volatile u32 sop:1; - volatile u32 c:1; - volatile u32 own:1; -#else - volatile u32 own:1; - volatile u32 c:1; - volatile u32 sop:1; - volatile u32 eop:1; - volatile u32 reserve1:3; - volatile u32 byte_offset:2; - volatile u32 reserve2:7; - volatile u32 data_length:16; -#endif - } field; - - volatile u32 word; - } status; - - volatile u32 data_pointer; -}; - -struct tx_desc { - union { - struct { -#ifdef CONFIG_CPU_LITTLE_ENDIAN - volatile u32 data_length:16; - volatile u32 reserved:7; - volatile u32 byte_offset:5; - volatile u32 eop:1; - volatile u32 sop:1; - volatile u32 c:1; - volatile u32 own:1; -#else - volatile u32 own:1; - volatile u32 c:1; - volatile u32 sop:1; - volatile u32 eop:1; - volatile u32 byte_offset:5; - volatile u32 reserved:7; - volatile u32 data_length:16; -#endif - } field; - - volatile u32 word; - } status; - - volatile u32 data_pointer; -}; - -/* DMA pseudo interrupts notified to switch driver */ -#define RCV_INT 0x01 -#define TX_BUF_FULL_INT 0x02 -#define TRANSMIT_CPT_INT 0x04 -#define CHANNEL_CLOSED 0x10 - -/* Parameters for switch DMA device */ -#define DEFAULT_SW_CHANNEL_WEIGHT 3 -#define DEFAULT_SW_PORT_WEIGHT 7 - -#define DEFAULT_SW_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ -#define DEFAULT_SW_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ - -#define DEFAULT_SW_TX_CHANNEL_NUM 4 -#define DEFAULT_SW_RX_CHANNEL_NUM 4 - -#define DEFAULT_SW_TX_CHANNEL_DESCR_NUM 20 -#define DEFAULT_SW_RX_CHANNEL_DESCR_NUM 20 - -/* Parameters for SSC DMA device */ -#define DEFAULT_SSC_CHANNEL_WEIGHT 3 -#define DEFAULT_SSC_PORT_WEIGHT 7 - -#define DEFAULT_SSC_TX_CHANNEL_CLASS 3 -#define DEFAULT_SSC_RX_CHANNEL_CLASS 0 - -#define DEFAULT_SSC_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ -#define DEFAULT_SSC_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ - -#define DEFAULT_SSC0_TX_CHANNEL_NUM 1 -#define DEFAULT_SSC0_RX_CHANNEL_NUM 1 -#define DEFAULT_SSC1_TX_CHANNEL_NUM 1 -#define DEFAULT_SSC1_RX_CHANNEL_NUM 1 - -#define DEFAULT_SSC_TX_CHANNEL_DESCR_NUM 10 -#define DEFAULT_SSC_RX_CHANNEL_DESCR_NUM 10 - -/* Parameters for memory DMA device */ -#define DEFAULT_MEM_CHANNEL_WEIGHT 3 -#define DEFAULT_MEM_PORT_WEIGHT 7 - -#define DEFAULT_MEM_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ -#define DEFAULT_MEM_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ - -#define DEFAULT_MEM_TX_CHANNEL_NUM 1 -#define DEFAULT_MEM_RX_CHANNEL_NUM 1 - -#define DEFAULT_MEM_TX_CHANNEL_DESCR_NUM 2 -#define DEFAULT_MEM_RX_CHANNEL_DESCR_NUM 2 - -/* Parameters for DEU DMA device */ -#define DEFAULT_DEU_CHANNEL_WEIGHT 1 -#define DEFAULT_DEU_PORT_WEIGHT 1 - -#define DEFAULT_DEU_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ -#define DEFAULT_DEU_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ - -#define DEFAULT_DEU_TX_CHANNEL_DESCR_NUM 20 -#define DEFAULT_DEU_RX_CHANNEL_DESCR_NUM 20 - -#define DMA_DESCR_NUM 30 /* number of descriptors per channel */ - -enum dma_dir_t { - DIR_RX = 0, - DIR_TX = 1, -}; - -struct dma_device_info; - -struct dma_channel_info { - /*Pointer to the peripheral device who is using this channel*/ - /*const*/ struct dma_device_info *dma_dev; - /*direction*/ - const enum dma_dir_t dir; /*RX or TX*/ - /*class for this channel for QoS*/ - int pri; - /*irq number*/ - const int irq; - /*relative channel number*/ - const int rel_chan_no; - /*absolute channel number*/ - int abs_chan_no; - - /*specify byte_offset*/ - int byte_offset; - int tx_weight; - - /*descriptor parameter*/ - int desc_base; - int desc_len; - int curr_desc; - int prev_desc;/*only used if it is a tx channel*/ - - /*weight setting for WFQ algorithm*/ - int weight; - int default_weight; - - int packet_size; - - /*status of this channel*/ - int control; /*on or off*/ - int xfer_cnt; - int dur; /*descriptor underrun*/ - - /**optional information for the upper layer devices*/ - void *opt[DMA_DESCR_NUM]; - - /*channel operations*/ - int (*open)(struct dma_channel_info *ch); - int (*close)(struct dma_channel_info *ch); - int (*reset)(struct dma_channel_info *ch); - void (*enable_irq)(struct dma_channel_info *ch); - void (*disable_irq)(struct dma_channel_info *ch); -}; - - -struct dma_device_info { - /*device name of this peripheral*/ - const char device_name[16]; - const int max_rx_chan_num; - const int max_tx_chan_num; - int drop_enable; - - int reserved; - - int tx_burst_len; - int rx_burst_len; - int tx_weight; - - int current_tx_chan; - int current_rx_chan; - int num_tx_chan; - int num_rx_chan; - int tx_endianness_mode; - int rx_endianness_mode; - struct dma_channel_info *tx_chan[4]; - struct dma_channel_info *rx_chan[4]; - - /*functions, optional*/ - u8 *(*buffer_alloc)(int len,int *offset, void **opt); - void (*buffer_free)(u8 *dataptr, void *opt); - int (*intr_handler)(struct dma_device_info *dma_dev, int status); - - /* used by peripheral driver only */ - void *priv; -}; - -struct dma_device_info *dma_device_reserve(char *dev_name); -int dma_device_release(struct dma_device_info *dma_dev); -int dma_device_register(struct dma_device_info *dma_dev); -int dma_device_unregister(struct dma_device_info *dma_dev); -int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt); -int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, - int len, void *opt); - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h deleted file mode 100644 index bca8df9fd5..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2010 Lantiq - */ -#ifndef __SVIP_IRQ_H -#define __SVIP_IRQ_H - -#define IM_NUM 6 - -#define INT_NUM_IRQ0 8 -#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) -#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) -#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) -#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) -#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) -#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) -#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) - -#define INT_NUM_IM5_IRL0 (INT_NUM_IRQ0 + 160) -#define MIPS_CPU_TIMER_IRQ (INT_NUM_IM5_IRL0 + 2) - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h deleted file mode 100644 index 8ca3285f2c..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h +++ /dev/null @@ -1,467 +0,0 @@ -/************************************************************************ - * - * Copyright (c) 2007 - * Infineon Technologies AG - * St. Martin Strasse 53; 81669 Muenchen; Germany - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - ************************************************************************/ - -#ifndef __SVIP_MUX_H -#define __SVIP_MUX_H - -#define LTQ_MUX_P0_PINS 20 -#define LTQ_MUX_P1_PINS 20 -#define LTQ_MUX_P2_PINS 19 -#define LTQ_MUX_P3_PINS 20 -#define LTQ_MUX_P4_PINS 24 - -struct ltq_mux_pin { - int dirin; - int puen; - int altsel0; - int altsel1; -}; - -struct ltq_mux_settings { - const struct ltq_mux_pin *mux_p0; - const struct ltq_mux_pin *mux_p1; - const struct ltq_mux_pin *mux_p2; - const struct ltq_mux_pin *mux_p3; - const struct ltq_mux_pin *mux_p4; -}; - -#define LTQ_MUX_P0_19_EXINT16 { 1, 0, 1, 0 } -#define LTQ_MUX_P0_19 { 0, 0, 1, 0 } - -#define LTQ_MUX_P0_18_EJ_BRKIN { 1, 0, 0, 0 } -#define LTQ_MUX_P0_18 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_18_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P0_17_EXINT10 { 1, 0, 0, 0 } -#define LTQ_MUX_P0_17 { 0, 0, 0, 0 } -#define LTQ_MUX_P0_17_ASC1_RXD { 1, 0, 1, 0 } - -#define LTQ_MUX_P0_16_EXINT9 { 1, 0, 0, 0 } -#define LTQ_MUX_P0_16 { 0, 0, 0, 0 } -#define LTQ_MUX_P0_16_ASC1_TXD { 0, 0, 1, 0 } - -#define LTQ_MUX_P0_15_EXINT8 { 1, 0, 0, 0 } -#define LTQ_MUX_P0_15 { 0, 0, 0, 0 } -#define LTQ_MUX_P0_15_ASC0_RXD { 1, 0, 1, 0 } - -#define LTQ_MUX_P0_14_EXINT7 { 1, 0, 0, 0 } -#define LTQ_MUX_P0_14 { 0, 0, 0, 0 } -#define LTQ_MUX_P0_14_ASC0_TXD { 1, 0, 1, 0 } - -#define LTQ_MUX_P0_13_SSC0_CS7 { 0, 1, 0, 0 } -#define LTQ_MUX_P0_13_EXINT6 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_13 { 1, 0, 1, 0 } -#define LTQ_MUX_P0_13_SSC1_CS7 { 0, 0, 0, 1 } -#define LTQ_MUX_P0_13_SSC1_INT { 0, 0, 1, 1 } - -#define LTQ_MUX_P0_12_SSC0_CS6 { 0, 1, 0, 0 } -#define LTQ_MUX_P0_12_EXINT5 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_12 { 1, 0, 1, 0 } -#define LTQ_MUX_P0_12_SSC1_CS6 { 0, 0, 0, 1 } - -#define LTQ_MUX_P0_11_SSC0_CS5 { 0, 1, 0, 0 } -#define LTQ_MUX_P0_11_EXINT4 { 1, 0, 1, 0 } -#define LTQ_MUX_P0_11 { 1, 0, 0, 0 } -#define LTQ_MUX_P0_11_SSC1_CS5 { 0, 0, 0, 1 } - -#define LTQ_MUX_P0_10_SSC0_CS4 { 0, 1, 0, 0 } -#define LTQ_MUX_P0_10_EXINT3 { 1, 0, 1, 0 } -#define LTQ_MUX_P0_10 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_10_SSC1_CS4 { 0, 0, 0, 1 } - -#define LTQ_MUX_P0_9_SSC0_CS3 { 0, 1, 0, 0 } -#define LTQ_MUX_P0_9_EXINT2 { 1, 0, 1, 0 } -#define LTQ_MUX_P0_9 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_9_SSC1_CS3 { 0, 0, 0, 1 } - -#define LTQ_MUX_P0_8_SSC0_CS2 { 0, 1, 0, 0 } -#define LTQ_MUX_P0_8_EXINT1 { 1, 0, 1, 0 } -#define LTQ_MUX_P0_8 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_8_SSC1_CS2 { 0, 0, 0, 1 } - -#define LTQ_MUX_P0_7_SSC0_CS1 { 0, 1, 0, 0 } -#define LTQ_MUX_P0_7_EXINT0 { 1, 0, 1, 0 } -#define LTQ_MUX_P0_7 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_7_SSC1_CS1 { 0, 0, 0, 1 } -#define LTQ_MUX_P0_7_SSC1_CS0 { 1, 0, 0, 1 } -#define LTQ_MUX_P0_7_SSC2_CS0 { 1, 0, 1, 1 } - -#define LTQ_MUX_P0_6_SSC0_CS0 { 0, 1, 0, 0 } -#define LTQ_MUX_P0_6 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_6_IN { 1, 0, 1, 0 } -#define LTQ_MUX_P0_6_SSC1_CS0 { 0, 0, 0, 1 } - -#define LTQ_MUX_P0_5_SSC1_SCLK { 0, 0, 0, 0 } -#define LTQ_MUX_P0_5 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_5_IN { 1, 0, 1, 0 } -#define LTQ_MUX_P0_5_SSC2_CLK { 1, 0, 0, 1 } - -#define LTQ_MUX_P0_4_SSC1_MRST { 1, 0, 0, 0 } -#define LTQ_MUX_P0_4 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_4_IN { 1, 0, 1, 0 } -#define LTQ_MUX_P0_4_SSC2_MRST { 0, 0, 0, 1 } - -#define LTQ_MUX_P0_3_SSC1_MTSR { 0, 0, 0, 0 } -#define LTQ_MUX_P0_3 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_3_IN { 1, 0, 1, 0 } -#define LTQ_MUX_P0_3_SSC2_MTSR { 0, 0, 0, 1 } - -#define LTQ_MUX_P0_2_SSC0_SCLK { 0, 0, 0, 0 } -#define LTQ_MUX_P0_2 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_2_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P0_1_SSC0_MRST { 1, 0, 0, 0 } -#define LTQ_MUX_P0_1 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_1_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P0_0_SSC0_MTSR { 0, 0, 0, 0 } -#define LTQ_MUX_P0_0 { 0, 0, 1, 0 } -#define LTQ_MUX_P0_0_IN { 1, 0, 1, 0 } - - -#define LTQ_MUX_P1_19_PCM3_TC1 { 0, 0, 0, 0 } -#define LTQ_MUX_P1_19_EXINT15 { 1, 0, 1, 0 } -#define LTQ_MUX_P1_19 { 0, 0, 1, 0 } - -#define LTQ_MUX_P1_18_PCM3_FSC { 0, 0, 0, 0 } -#define LTQ_MUX_P1_18_EXINT11 { 1, 0, 1, 0 } -#define LTQ_MUX_P1_18 { 0, 0, 1, 0 } - -#define LTQ_MUX_P1_17_PCM3_PCL { 0, 0, 0, 0 } -#define LTQ_MUX_P1_17_EXINT12 { 1, 0, 1, 0 } -#define LTQ_MUX_P1_17 { 0, 0, 1, 0 } - -#define LTQ_MUX_P1_16_PCM3_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P1_16_EXINT13 { 1, 0, 1, 0 } -#define LTQ_MUX_P1_16 { 0, 0, 1, 0 } - -#define LTQ_MUX_P1_15_PCM3_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P1_15_EXINT14 { 1, 0, 1, 0 } -#define LTQ_MUX_P1_15 { 0, 0, 1, 0 } - -#define LTQ_MUX_P1_14_PCM2_TC1 { 0, 0, 0, 0 } -#define LTQ_MUX_P1_14 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_14_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_13_PCM2_FSC { 0, 0, 0, 0 } -#define LTQ_MUX_P1_13 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_13_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_12_PCM2_PCL { 0, 0, 0, 0 } -#define LTQ_MUX_P1_12 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_12_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_11_PCM2_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P1_11 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_11_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_10_PCM2_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P1_10 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_10_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_9_PCM1_TC1 { 0, 0, 0, 0 } -#define LTQ_MUX_P1_9 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_9_IN { 0, 0, 1, 0 } - -#define LTQ_MUX_P1_8_PCM1_FSC { 0, 0, 0, 0 } -#define LTQ_MUX_P1_8 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_8_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_7_PCM1_PCL { 0, 0, 0, 0 } -#define LTQ_MUX_P1_7 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_7_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_6_PCM1_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P1_6 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_6_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_5_PCM1_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P1_5 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_5_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_4_PCM0_TC1 { 0, 0, 0, 0 } -#define LTQ_MUX_P1_4 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_4_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_3_PCM0_FSC { 0, 0, 0, 0 } -#define LTQ_MUX_P1_3 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_3_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_2_PCM0_PCL { 0, 0, 0, 0 } -#define LTQ_MUX_P1_2 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_2_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_1_PCM0_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P1_1 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_1_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P1_0_PCM0_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P1_0 { 0, 0, 1, 0 } -#define LTQ_MUX_P1_0_IN { 1, 0, 1, 0 } - - -#define LTQ_MUX_P2_18_EBU_BC1 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_18 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_18_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_17_EBU_BC0 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_17 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_17_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_16_EBU_RDBY { 1, 0, 0, 0 } -#define LTQ_MUX_P2_16 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_16_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_15_EBU_WAIT { 1, 0, 0, 0 } -#define LTQ_MUX_P2_15 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_15_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_14_EBU_ALE { 0, 0, 0, 0 } -#define LTQ_MUX_P2_14 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_14_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_13_EBU_WR { 0, 0, 0, 0 } -#define LTQ_MUX_P2_13 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_13_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_12_EBU_RD { 0, 0, 0, 0 } -#define LTQ_MUX_P2_12 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_12_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_11_EBU_A11 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_11 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_11_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_10_EBU_A10 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_10 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_10_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_9_EBU_A9 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_9 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_9_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_8_EBU_A8 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_8 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_8_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_7_EBU_A7 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_7 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_7_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_6_EBU_A6 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_6 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_6_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_5_EBU_A5 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_5 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_5_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_4_EBU_A4 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_4 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_4_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_3_EBU_A3 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_3 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_3_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_2_EBU_A2 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_2 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_2_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_1_EBU_A1 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_1 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_1_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P2_0_EBU_A0 { 0, 0, 0, 0 } -#define LTQ_MUX_P2_0 { 0, 0, 1, 0 } -#define LTQ_MUX_P2_0_IN { 1, 0, 1, 0 } - - -#define LTQ_MUX_P3_19_EBU_CS3 { 0, 0, 0, 0 } -#define LTQ_MUX_P3_19 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_19_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_18_EBU_CS2 { 0, 0, 0, 0 } -#define LTQ_MUX_P3_18 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_18_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_17_EBU_CS1 { 0, 0, 0, 0 } -#define LTQ_MUX_P3_17 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_17_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_16_EBU_CS0 { 0, 0, 0, 0 } -#define LTQ_MUX_P3_16 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_16_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_15_EBU_AD15 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_15 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_15_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_14_EBU_AD14 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_14 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_14_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_13_EBU_AD13 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_13 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_13_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_12_EBU_AD12 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_12 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_12_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_11_EBU_AD11 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_11 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_11_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_10_EBU_AD10 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_10 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_10_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_9_EBU_AD9 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_9 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_9_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_8_EBU_AD8 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_8 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_8_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_7_EBU_AD7 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_7 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_7_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_6_EBU_AD6 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_6 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_6_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_5_EBU_AD5 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_5 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_5_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_4_EBU_AD4 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_4 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_4_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_3_EBU_AD3 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_3 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_3_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_2_EBU_AD2 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_2 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_2_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_1_EBU_AD1 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_1 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_1_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P3_0_EBU_AD0 { 1, 0, 0, 0 } -#define LTQ_MUX_P3_0 { 0, 0, 1, 0 } -#define LTQ_MUX_P3_0_IN { 1, 0, 1, 0 } - - -#define LTQ_MUX_P4_23_SSLIC7_CLK { 0, 0, 0, 0 } -#define LTQ_MUX_P4_23 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_23_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_22_SSLIC7_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_22 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_22_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_21_SSLIC7_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_21 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_21_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_20_SSLIC6_CLK { 0, 0, 0, 0 } -#define LTQ_MUX_P4_20 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_20_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_19_SSLIC6_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_19 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_19_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_18_SSLIC6_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_18 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_18_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_17_SSLIC5_CLK { 0, 0, 0, 0 } -#define LTQ_MUX_P4_17 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_17_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_16_SSLIC5_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_16 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_16_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_15_SSLIC5_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_15 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_15_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_14_SSLIC4_CLK { 0, 0, 0, 0 } -#define LTQ_MUX_P4_14 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_14_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_13_SSLIC4_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_13 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_13_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_12_SSLIC4_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_12 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_12_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_11_SSLIC3_CLK { 0, 0, 0, 0 } -#define LTQ_MUX_P4_11 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_11_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_10_SSLIC3_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_10 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_10_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_9_SSLIC3_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_9 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_9_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_8_SSLIC2_CLK { 0, 0, 0, 0 } -#define LTQ_MUX_P4_8 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_8_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_7_SSLIC2_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_7 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_7_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_6_SSLIC2_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_6 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_6_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_5_SSLIC1_CLK { 0, 0, 0, 0 } -#define LTQ_MUX_P4_5 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_5_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_4_SSLIC1_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_4 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_4_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_3_SSLIC1_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_3 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_3_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_2_SSLIC0_CLK { 0, 0, 0, 0 } -#define LTQ_MUX_P4_2 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_2_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_1_SSLIC0_RX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_1 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_1_IN { 1, 0, 1, 0 } - -#define LTQ_MUX_P4_0_SSLIC0_TX { 0, 0, 0, 0 } -#define LTQ_MUX_P4_0 { 0, 0, 1, 0 } -#define LTQ_MUX_P4_0_IN { 1, 0, 1, 0 } - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h deleted file mode 100644 index 7329711858..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h +++ /dev/null @@ -1,23 +0,0 @@ -/************************************************************************ - * - * Copyright (c) 2007 - * Infineon Technologies AG - * St. Martin Strasse 53; 81669 Muenchen; Germany - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - ************************************************************************/ - -#ifndef __SVIP_PMS_H -#define __SVIP_PMS_H - -void svip_sys1_clk_enable(u32 mask); -int svip_sys1_clk_is_enabled(u32 mask); - -void svip_sys2_clk_enable(u32 mask); -int svip_sys2_clk_is_enabled(u32 mask); - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h deleted file mode 100644 index 7428cccc87..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h +++ /dev/null @@ -1,165 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __SYS0_REG_H -#define __SYS0_REG_H - -#define sys0_r32(reg) ltq_r32(&sys0->reg) -#define sys0_w32(val, reg) ltq_w32(val, &sys0->reg) -#define sys0_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys0->reg) - -/** SYS0 register structure */ -struct svip_reg_sys0 { - unsigned long sr; /* 0x0000 */ - unsigned long bcr; /* 0x0004 */ - unsigned long pll1cr; /* 0x0008 */ - unsigned long pll2cr; /* 0x000c */ - unsigned long tscr; /* 0x0010 */ - unsigned long phyclkr; /* 0x0014 */ -}; - -/******************************************************************************* - * SYS0 Status Register - ******************************************************************************/ - -/* Endian select pin (31) */ -#define SYS0_SR_ESEL (0x1 << 31) -#define SYS0_SR_ESEL_GET(val) ((((val) & SYS0_SR_ESEL) >> 31) & 0x1) -/* Boot mode pins (27:24) */ -#define SYS0_SR_BMODE (0xf << 24) -#define SYS0_SR_BMODE_GET(val) ((((val) & SYS0_SR_BMODE) >> 24) & 0xf) -/* PLL2 Lock (18) */ -#define SYS0_SR_PLL2LOCK (0x1 << 18) -#define SYS0_SR_PLL2LOCK_GET(val) ((((val) & SYS0_SR_PLL2LOCK) >> 18) & 0x1) -/* PLL1 Lock (17) */ -#define SYS0_SR_PLL1LOCK (0x1 << 17) -#define SYS0_SR_PLL1LOCK_GET(val) ((((val) & SYS0_SR_PLL1LOCK) >> 17) & 0x1) -/* Discrete Timing Oscillator Lock (16) */ -#define SYS0_SR_DTOLOCK (0x1 << 16) -#define SYS0_SR_DTOLOCK_GET(val) ((((val) & SYS0_SR_DTOLOCK) >> 16) & 0x1) -/* Hardware Reset Indication (1) */ -#define SYS0_SR_HRSTIN (0x1 << 1) -#define SYS0_SR_HRSTIN_VAL(val) (((val) & 0x1) << 1) -#define SYS0_SR_HRSTIN_GET(val) ((((val) & SYS0_SR_HRSTIN) >> 1) & 0x1) -#define SYS0_SR_HRSTIN_SET(reg,val) (reg) = ((reg & ~SYS0_SR_HRSTIN) | (((val) & 0x1) << 1)) -/* Power-on Reset Indication (0) */ -#define SYS0_SR_POR (0x1 << 0) -#define SYS0_SR_POR_VAL(val) (((val) & 0x1) << 0) -#define SYS0_SR_POR_GET(val) ((((val) & SYS0_SR_POR) >> 0) & 0x1) -#define SYS0_SR_POR_SET(reg,val) (reg) = ((reg & ~SYS0_SR_POR) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * SYS0 Boot Control Register - ******************************************************************************/ - -/* Configuration of Boot Source for CPU5 (25) */ -#define SYS0_BCR_BMODECPU5 (0x1 << 25) -#define SYS0_BCR_BMODECPU5_VAL(val) (((val) & 0x1) << 25) -#define SYS0_BCR_BMODECPU5_GET(val) ((((val) & SYS0_BCR_BMODECPU5) >> 25) & 0x1) -#define SYS0_BCR_BMODECPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU5) | (((val) & 0x1) << 25)) -/* Configuration of Boot Source for CPU4 (24) */ -#define SYS0_BCR_BMODECPU4 (0x1 << 24) -#define SYS0_BCR_BMODECPU4_VAL(val) (((val) & 0x1) << 24) -#define SYS0_BCR_BMODECPU4_GET(val) ((((val) & SYS0_BCR_BMODECPU4) >> 24) & 0x1) -#define SYS0_BCR_BMODECPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU4) | (((val) & 0x1) << 24)) -/* Configuration of Boot Source for CPU3 (23) */ -#define SYS0_BCR_BMODECPU3 (0x1 << 23) -#define SYS0_BCR_BMODECPU3_VAL(val) (((val) & 0x1) << 23) -#define SYS0_BCR_BMODECPU3_GET(val) ((((val) & SYS0_BCR_BMODECPU3) >> 23) & 0x1) -#define SYS0_BCR_BMODECPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU3) | (((val) & 0x1) << 23)) -/* Configuration of Boot Source for CPU2 (22) */ -#define SYS0_BCR_BMODECPU2 (0x1 << 22) -#define SYS0_BCR_BMODECPU2_VAL(val) (((val) & 0x1) << 22) -#define SYS0_BCR_BMODECPU2_GET(val) ((((val) & SYS0_BCR_BMODECPU2) >> 22) & 0x1) -#define SYS0_BCR_BMODECPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU2) | (((val) & 0x1) << 22)) -/* Configuration of Boot Source for CPU1 (21) */ -#define SYS0_BCR_BMODECPU1 (0x1 << 21) -#define SYS0_BCR_BMODECPU1_VAL(val) (((val) & 0x1) << 21) -#define SYS0_BCR_BMODECPU1_GET(val) ((((val) & SYS0_BCR_BMODECPU1) >> 21) & 0x1) -#define SYS0_BCR_BMODECPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU1) | (((val) & 0x1) << 21)) -/* Configuration of Boot Source for CPU0 (20:16) */ -#define SYS0_BCR_BMODECPU0 (0x1f << 16) -#define SYS0_BCR_BMODECPU0_VAL(val) (((val) & 0x1f) << 16) -#define SYS0_BCR_BMODECPU0_GET(val) ((((val) & SYS0_BCR_BMODECPU0) >> 16) & 0x1f) -#define SYS0_BCR_BMODECPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU0) | (((val) & 0x1f) << 16)) -/* Configuration of Endianess for CPU5 (5) */ -#define SYS0_BCR_ESELCPU5 (0x1 << 5) -#define SYS0_BCR_ESELCPU5_VAL(val) (((val) & 0x1) << 5) -#define SYS0_BCR_ESELCPU5_GET(val) ((((val) & SYS0_BCR_ESELCPU5) >> 5) & 0x1) -#define SYS0_BCR_ESELCPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU5) | (((val) & 0x1) << 5)) -/* Configuration of Endianess for CPU4 (4) */ -#define SYS0_BCR_ESELCPU4 (0x1 << 4) -#define SYS0_BCR_ESELCPU4_VAL(val) (((val) & 0x1) << 4) -#define SYS0_BCR_ESELCPU4_GET(val) ((((val) & SYS0_BCR_ESELCPU4) >> 4) & 0x1) -#define SYS0_BCR_ESELCPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU4) | (((val) & 0x1) << 4)) -/* Configuration of Endianess for CPU3 (3) */ -#define SYS0_BCR_ESELCPU3 (0x1 << 3) -#define SYS0_BCR_ESELCPU3_VAL(val) (((val) & 0x1) << 3) -#define SYS0_BCR_ESELCPU3_GET(val) ((((val) & SYS0_BCR_ESELCPU3) >> 3) & 0x1) -#define SYS0_BCR_ESELCPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU3) | (((val) & 0x1) << 3)) -/* Configuration of Endianess for CPU2 (2) */ -#define SYS0_BCR_ESELCPU2 (0x1 << 2) -#define SYS0_BCR_ESELCPU2_VAL(val) (((val) & 0x1) << 2) -#define SYS0_BCR_ESELCPU2_GET(val) ((((val) & SYS0_BCR_ESELCPU2) >> 2) & 0x1) -#define SYS0_BCR_ESELCPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU2) | (((val) & 0x1) << 2)) -/* Configuration of Endianess for CPU1 (1) */ -#define SYS0_BCR_ESELCPU1 (0x1 << 1) -#define SYS0_BCR_ESELCPU1_VAL(val) (((val) & 0x1) << 1) -#define SYS0_BCR_ESELCPU1_GET(val) ((((val) & SYS0_BCR_ESELCPU1) >> 1) & 0x1) -#define SYS0_BCR_ESELCPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU1) | (((val) & 0x1) << 1)) -/* Configuration of Endianess for CPU0 (0) */ -#define SYS0_BCR_ESELCPU0 (0x1) -#define SYS0_BCR_ESELCPU0_VAL(val) (((val) & 0x1) << 0) -#define SYS0_BCR_ESELCPU0_GET(val) ((((val) & SYS0_BCR_ESELCPU0) >> 0) & 0x1) -#define SYS0_BCR_ESELCPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU0) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * PLL1 Control Register - ******************************************************************************/ - -/* PLL1 Bypass Enable (31) */ -#define SYS0_PLL1CR_OSCBYP (0x1 << 31) -#define SYS0_PLL1CR_OSCBYP_VAL(val) (((val) & 0x1) << 31) -#define SYS0_PLL1CR_OSCBYP_GET(val) ((((val) & SYS0_PLL1CR_OSCBYP) >> 31) & 0x1) -#define SYS0_PLL1CR_OSCBYP_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_OSCBYP) | (((val) & 0x1) << 31)) -/* PLL1 Divider Value (1:0) */ -#define SYS0_PLL1CR_PLLDIV (0x3) -#define SYS0_PLL1CR_PLLDIV_VAL(val) (((val) & 0x3) << 0) -#define SYS0_PLL1CR_PLLDIV_GET(val) ((((val) & SYS0_PLL1CR_PLLDIV) >> 0) & 0x3) -#define SYS0_PLL1CR_PLLDIV_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_PLLDIV) | (((val) & 0x3) << 0)) - -/******************************************************************************* - * PLL2 Control Register - ******************************************************************************/ - -/* PLL2 clear deepsleep (31) */ -#define SYS0_PLL2CR_CLRDS (0x1 << 31) -#define SYS0_PLL2CR_CLRDS_VAL(val) (((val) & 0x1) << 31) -#define SYS0_PLL2CR_CLRDS_GET(val) ((((val) & SYS0_PLL2CR_CLRDS) >> 31) & 0x1) -#define SYS0_PLL2CR_CLRDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_CLRDS) | (((val) & 0x1) << 31)) -/* PLL2 set deepsleep (30) */ -#define SYS0_PLL2CR_SETDS (0x1 << 30) -#define SYS0_PLL2CR_SETDS_VAL(val) (((val) & 0x1) << 30) -#define SYS0_PLL2CR_SETDS_GET(val) ((((val) & SYS0_PLL2CR_SETDS) >> 30) & 0x1) -#define SYS0_PLL2CR_SETDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_SETDS) | (((val) & 0x1) << 30)) -/* PLL2 Fractional division enable (16) */ -#define SYS0_PLL2CR_FRACTEN (0x1 << 16) -#define SYS0_PLL2CR_FRACTEN_VAL(val) (((val) & 0x1) << 16) -#define SYS0_PLL2CR_FRACTEN_GET(val) ((((val) & SYS0_PLL2CR_FRACTEN) >> 16) & 0x1) -#define SYS0_PLL2CR_FRACTEN_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_FRACTEN) | (((val) & 0x1) << 16)) -/* PLL2 Fractional division value (9:0) */ -#define SYS0_FRACTVAL (0x3f) -#define SYS0_FRACTVAL_VAL(val) (((val) & 0x3f) << 0) -#define SYS0_FRACTVAL_GET(val) ((((val) & SYS0_FRACTVAL) >> 0) & 0x3f) -#define SYS0_FRACTVAL_SET(reg,val) (reg) = ((reg & ~SYS0_FRACTVAL) | (((val) & 0x3f) << 0)) - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h deleted file mode 100644 index e0c2e84b1a..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h +++ /dev/null @@ -1,370 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __SYS1_REG_H -#define __SYS1_REG_H - -#define sys1_r32(reg) ltq_r32(&sys1->reg) -#define sys1_w32(val, reg) ltq_w32(val, &sys1->reg) -#define sys1_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys1->reg) - -/** SYS1 register structure */ -struct svip_reg_sys1 { - unsigned long clksr; /* 0x0000 */ - unsigned long clkenr; /* 0x0004 */ - unsigned long clkclr; /* 0x0008 */ - unsigned long reserved0[1]; - unsigned long l2ccr; /* 0x0010 */ - unsigned long fpicr; /* 0x0014 */ - unsigned long wdtcr; /* 0x0018 */ - unsigned long reserved1[1]; - unsigned long cpucr[6]; /* 0x0020 */ - unsigned long reserved2[2]; - unsigned long rsr; /* 0x0040 */ - unsigned long rreqr; /* 0x0044 */ - unsigned long rrlsr; /* 0x0048 */ - unsigned long rbtr; /* 0x004c */ - unsigned long irncr; /* 0x0050 */ - unsigned long irnicr; /* 0x0054 */ - unsigned long irnen; /* 0x0058 */ - unsigned long reserved3[1]; - unsigned long cpursr[6]; /* 0x0060 */ - unsigned long reserved4[2]; - unsigned long cpusrssr[6]; /* 0x0080 */ - unsigned long reserved5[2]; - unsigned long cpuwrssr[6]; /* 0x00a0 */ -}; - -/******************************************************************************* - * SYS1 Clock Status Register - ******************************************************************************/ -/* (r) Clock Enable for L2C */ -#define SYS1_CLKSR_L2C (0x1 << 31) -/* (r) Clock Enable for DDR2 */ -#define SYS1_CLKSR_DDR2 (0x1 << 30) -/* (r) Clock Enable for SMI2 */ -#define SYS1_CLKSR_SMI2 (0x1 << 29) -/* (r) Clock Enable for SMI1 */ -#define SYS1_CLKSR_SMI1 (0x1 << 28) -/* (r) Clock Enable for SMI0 */ -#define SYS1_CLKSR_SMI0 (0x1 << 27) -/* (r) Clock Enable for FMI0 */ -#define SYS1_CLKSR_FMI0 (0x1 << 26) -/* (r) Clock Enable for PORT0 */ -#define SYS1_CLKSR_PORT0 (0x1 << 0) -/* (r) Clock Enable for PCM3 */ -#define SYS1_CLKSR_PCM3 (0x1 << 19) -/* (r) Clock Enable for PCM2 */ -#define SYS1_CLKSR_PCM2 (0x1 << 18) -/* (r) Clock Enable for PCM1 */ -#define SYS1_CLKSR_PCM1 (0x1 << 17) -/* (r) Clock Enable for PCM0 */ -#define SYS1_CLKSR_PCM0 (0x1 << 16) -/* (r) Clock Enable for ASC1 */ -#define SYS1_CLKSR_ASC1 (0x1 << 15) -/* (r) Clock Enable for ASC0 */ -#define SYS1_CLKSR_ASC0 (0x1 << 14) -/* (r) Clock Enable for SSC2 */ -#define SYS1_CLKSR_SSC2 (0x1 << 13) -/* (r) Clock Enable for SSC1 */ -#define SYS1_CLKSR_SSC1 (0x1 << 12) -/* (r) Clock Enable for SSC0 */ -#define SYS1_CLKSR_SSC0 (0x1 << 11) -/* (r) Clock Enable for GPTC */ -#define SYS1_CLKSR_GPTC (0x1 << 10) -/* (r) Clock Enable for DMA */ -#define SYS1_CLKSR_DMA (0x1 << 9) -/* (r) Clock Enable for FSCT */ -#define SYS1_CLKSR_FSCT (0x1 << 8) -/* (r) Clock Enable for ETHSW */ -#define SYS1_CLKSR_ETHSW (0x1 << 7) -/* (r) Clock Enable for EBU */ -#define SYS1_CLKSR_EBU (0x1 << 6) -/* (r) Clock Enable for TRNG */ -#define SYS1_CLKSR_TRNG (0x1 << 5) -/* (r) Clock Enable for DEU */ -#define SYS1_CLKSR_DEU (0x1 << 4) -/* (r) Clock Enable for PORT3 */ -#define SYS1_CLKSR_PORT3 (0x1 << 3) -/* (r) Clock Enable for PORT2 */ -#define SYS1_CLKSR_PORT2 (0x1 << 2) -/* (r) Clock Enable for PORT1 */ -#define SYS1_CLKSR_PORT1 (0x1 << 1) - -/******************************************************************************* - * SYS1 Clock Enable Register - ******************************************************************************/ -/* (w) Clock Enable Request for L2C */ -#define SYS1_CLKENR_L2C (0x1 << 31) -/* (w) Clock Enable Request for DDR2 */ -#define SYS1_CLKENR_DDR2 (0x1 << 30) -/* (w) Clock Enable Request for SMI2 */ -#define SYS1_CLKENR_SMI2 (0x1 << 29) -/* (w) Clock Enable Request for SMI1 */ -#define SYS1_CLKENR_SMI1 (0x1 << 28) -/* (w) Clock Enable Request for SMI0 */ -#define SYS1_CLKENR_SMI0 (0x1 << 27) -/* (w) Clock Enable Request for FMI0 */ -#define SYS1_CLKENR_FMI0 (0x1 << 26) -/* (w) Clock Enable Request for PORT0 */ -#define SYS1_CLKENR_PORT0 (0x1 << 0) -/* (w) Clock Enable Request for PCM3 */ -#define SYS1_CLKENR_PCM3 (0x1 << 19) -/* (w) Clock Enable Request for PCM2 */ -#define SYS1_CLKENR_PCM2 (0x1 << 18) -/* (w) Clock Enable Request for PCM1 */ -#define SYS1_CLKENR_PCM1 (0x1 << 17) -/* (w) Clock Enable Request for PCM0 */ -#define SYS1_CLKENR_PCM0 (0x1 << 16) -/* (w) Clock Enable Request for ASC1 */ -#define SYS1_CLKENR_ASC1 (0x1 << 15) -/* (w) Clock Enable Request for ASC0 */ -#define SYS1_CLKENR_ASC0 (0x1 << 14) -/* (w) Clock Enable Request for SSC2 */ -#define SYS1_CLKENR_SSC2 (0x1 << 13) -/* (w) Clock Enable Request for SSC1 */ -#define SYS1_CLKENR_SSC1 (0x1 << 12) -/* (w) Clock Enable Request for SSC0 */ -#define SYS1_CLKENR_SSC0 (0x1 << 11) -/* (w) Clock Enable Request for GPTC */ -#define SYS1_CLKENR_GPTC (0x1 << 10) -/* (w) Clock Enable Request for DMA */ -#define SYS1_CLKENR_DMA (0x1 << 9) -/* (w) Clock Enable Request for FSCT */ -#define SYS1_CLKENR_FSCT (0x1 << 8) -/* (w) Clock Enable Request for ETHSW */ -#define SYS1_CLKENR_ETHSW (0x1 << 7) -/* (w) Clock Enable Request for EBU */ -#define SYS1_CLKENR_EBU (0x1 << 6) -/* (w) Clock Enable Request for TRNG */ -#define SYS1_CLKENR_TRNG (0x1 << 5) -/* (w) Clock Enable Request for DEU */ -#define SYS1_CLKENR_DEU (0x1 << 4) -/* (w) Clock Enable Request for PORT3 */ -#define SYS1_CLKENR_PORT3 (0x1 << 3) -/* (w) Clock Enable Request for PORT2 */ -#define SYS1_CLKENR_PORT2 (0x1 << 2) -/* (w) Clock Enable Request for PORT1 */ -#define SYS1_CLKENR_PORT1 (0x1 << 1) - -/******************************************************************************* - * SYS1 Clock Clear Register - ******************************************************************************/ -/* (w) Clock Disable Request for L2C */ -#define SYS1_CLKCLR_L2C (0x1 << 31) -/* (w) Clock Disable Request for DDR2 */ -#define SYS1_CLKCLR_DDR2 (0x1 << 30) -/* (w) Clock Disable Request for SMI2 */ -#define SYS1_CLKCLR_SMI2 (0x1 << 29) -/* (w) Clock Disable Request for SMI1 */ -#define SYS1_CLKCLR_SMI1 (0x1 << 28) -/* (w) Clock Disable Request for SMI0 */ -#define SYS1_CLKCLR_SMI0 (0x1 << 27) -/* (w) Clock Disable Request for FMI0 */ -#define SYS1_CLKCLR_FMI0 (0x1 << 26) -/* (w) Clock Disable Request for PORT0 */ -#define SYS1_CLKCLR_PORT0 (0x1 << 0) -/* (w) Clock Disable Request for PCM3 */ -#define SYS1_CLKCLR_PCM3 (0x1 << 19) -/* (w) Clock Disable Request for PCM2 */ -#define SYS1_CLKCLR_PCM2 (0x1 << 18) -/* (w) Clock Disable Request for PCM1 */ -#define SYS1_CLKCLR_PCM1 (0x1 << 17) -/* (w) Clock Disable Request for PCM0 */ -#define SYS1_CLKCLR_PCM0 (0x1 << 16) -/* (w) Clock Disable Request for ASC1 */ -#define SYS1_CLKCLR_ASC1 (0x1 << 15) -/* (w) Clock Disable Request for ASC0 */ -#define SYS1_CLKCLR_ASC0 (0x1 << 14) -/* (w) Clock Disable Request for SSC2 */ -#define SYS1_CLKCLR_SSC2 (0x1 << 13) -/* (w) Clock Disable Request for SSC1 */ -#define SYS1_CLKCLR_SSC1 (0x1 << 12) -/* (w) Clock Disable Request for SSC0 */ -#define SYS1_CLKCLR_SSC0 (0x1 << 11) -/* (w) Clock Disable Request for GPTC */ -#define SYS1_CLKCLR_GPTC (0x1 << 10) -/* (w) Clock Disable Request for DMA */ -#define SYS1_CLKCLR_DMA (0x1 << 9) -/* (w) Clock Disable Request for FSCT */ -#define SYS1_CLKCLR_FSCT (0x1 << 8) -/* (w) Clock Disable Request for ETHSW */ -#define SYS1_CLKCLR_ETHSW (0x1 << 7) -/* (w) Clock Disable Request for EBU */ -#define SYS1_CLKCLR_EBU (0x1 << 6) -/* (w) Clock Disable Request for TRNG */ -#define SYS1_CLKCLR_TRNG (0x1 << 5) -/* (w) Clock Disable Request for DEU */ -#define SYS1_CLKCLR_DEU (0x1 << 4) -/* (w) Clock Disable Request for PORT3 */ -#define SYS1_CLKCLR_PORT3 (0x1 << 3) -/* (w) Clock Disable Request for PORT2 */ -#define SYS1_CLKCLR_PORT2 (0x1 << 2) -/* (w) Clock Disable Request for PORT1 */ -#define SYS1_CLKCLR_PORT1 (0x1 << 1) - -/******************************************************************************* - * SYS1 FPI Control Register - ******************************************************************************/ - -/* FPI Bus Clock divider (0) */ -#define SYS1_FPICR_FPIDIV (0x1) -#define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0) -#define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1) -#define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * SYS1 Clock Control Register for CPUn - ******************************************************************************/ - -/* Enable bit for clock of CPUn (1) */ -#define SYS1_CPUCR_CPUCLKEN (0x1 << 1) -#define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val) & 0x1) << 1) -#define SYS1_CPUCR_CPUCLKEN_GET(val) ((((val) & SYS1_CPUCR_CPUCLKEN) >> 1) & 0x1) -#define SYS1_CPUCR_CPUCLKEN_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUCLKEN) | (((val) & 0x1) << 1)) -/* Divider factor for clock of CPUn (0) */ -#define SYS1_CPUCR_CPUDIV (0x1) -#define SYS1_CPUCR_CPUDIV_VAL(val) (((val) & 0x1) << 0) -#define SYS1_CPUCR_CPUDIV_GET(val) ((((val) & SYS1_CPUCR_CPUDIV) >> 0) & 0x1) -#define SYS1_CPUCR_CPUDIV_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUDIV) | (((val) & 0x1) << 0)) - -/******************************************************************************* - * SYS1 Reset Request Register - ******************************************************************************/ - -/* HRSTOUT Reset Request (18) */ -#define SYS1_RREQ_HRSTOUT (0x1 << 18) -#define SYS1_RREQ_HRSTOUT_VAL(val) (((val) & 0x1) << 18) -#define SYS1_RREQ_HRSTOUT_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_HRSTOUT) | (((val) & 1) << 18)) - /* FBS0 Reset Request (17) */ -#define SYS1_RREQ_FBS0 (0x1 << 17) -#define SYS1_RREQ_FBS0_VAL(val) (((val) & 0x1) << 17) -#define SYS1_RREQ_FBS0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_FBS0) | (((val) & 1) << 17)) - /* SUBSYS Reset Request (16) */ -#define SYS1_RREQ_SUBSYS (0x1 << 16) -#define SYS1_RREQ_SUBSYS_VAL(val) (((val) & 0x1) << 16) -#define SYS1_RREQ_SUBSYS_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_SUBSYS) | (((val) & 1) << 16)) - /* Watchdog5 Reset Request (13) */ -#define SYS1_RREQ_WDT5 (0x1 << 13) -#define SYS1_RREQ_WDT5_VAL(val) (((val) & 0x1) << 13) -#define SYS1_RREQ_WDT5_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT5) | (((val) & 1) << 13)) - /* Watchdog4 Reset Request (12) */ -#define SYS1_RREQ_WDT4 (0x1 << 12) -#define SYS1_RREQ_WDT4_VAL(val) (((val) & 0x1) << 12) -#define SYS1_RREQ_WDT4_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT4) | (((val) & 1) << 12)) - /* Watchdog3 Reset Request (11) */ -#define SYS1_RREQ_WDT3 (0x1 << 11) -#define SYS1_RREQ_WDT3_VAL(val) (((val) & 0x1) << 11) -#define SYS1_RREQ_WDT3_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT3) | (((val) & 1) << 11)) - /* Watchdog2 Reset Request (10) */ -#define SYS1_RREQ_WDT2 (0x1 << 10) -#define SYS1_RREQ_WDT2_VAL(val) (((val) & 0x1) << 10) -#define SYS1_RREQ_WDT2_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT2) | (((val) & 1) << 10)) - /* Watchdog1 Reset Request (9) */ -#define SYS1_RREQ_WDT1 (0x1 << 9) -#define SYS1_RREQ_WDT1_VAL(val) (((val) & 0x1) << 9) -#define SYS1_RREQ_WDT1_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT1) | (((val) & 1) << 9)) - /* Watchdog0 Reset Request (8) */ -#define SYS1_RREQ_WDT0 (0x1 << 8) -#define SYS1_RREQ_WDT0_VAL(val) (((val) & 0x1) << 8) -#define SYS1_RREQ_WDT0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT0) | (((val) & 1) << 8)) - /* CPU5 Reset Request (5) */ -#define SYS1_RREQ_CPU5 (0x1 << 5) -#define SYS1_RREQ_CPU5_VAL(val) (((val) & 0x1) << 5) -#define SYS1_RREQ_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU5) | (((val) & 1) << 5)) - /* CPU4 Reset Request (4) */ -#define SYS1_RREQ_CPU4 (0x1 << 4) -#define SYS1_RREQ_CPU4_VAL(val) (((val) & 0x1) << 4) -#define SYS1_RREQ_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU4) | (((val) & 1) << 4)) - /* CPU3 Reset Request (3) */ -#define SYS1_RREQ_CPU3 (0x1 << 3) -#define SYS1_RREQ_CPU3_VAL(val) (((val) & 0x1) << 3) -#define SYS1_RREQ_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU3) | (((val) & 1) << 3)) - /* CPU2 Reset Request (2) */ -#define SYS1_RREQ_CPU2 (0x1 << 2) -#define SYS1_RREQ_CPU2_VAL(val) (((val) & 0x1) << 2) -#define SYS1_RREQ_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU2) | (((val) & 1) << 2)) - /* CPU1 Reset Request (1) */ -#define SYS1_RREQ_CPU1 (0x1 << 1) -#define SYS1_RREQ_CPU1_VAL(val) (((val) & 0x1) << 1) -#define SYS1_RREQ_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU1) | (((val) & 1) << 1)) -/* CPU0 Reset Request (0) */ -#define SYS1_RREQ_CPU0 (0x1) -#define SYS1_RREQ_CPU0_VAL(val) (((val) & 0x1) << 0) -#define SYS1_RREQ_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU0) | (((val) & 1) << 0)) - -/******************************************************************************* - * SYS1 Reset Release Register - ******************************************************************************/ - -/* HRSTOUT Reset Release (18) */ -#define SYS1_RRLSR_HRSTOUT (0x1 << 18) -#define SYS1_RRLSR_HRSTOUT_VAL(val) (((val) & 0x1) << 18) -#define SYS1_RRLSR_HRSTOUT_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_HRSTOUT) | (((val) & 1) << 18)) -/* FBS0 Reset Release (17) */ -#define SYS1_RRLSR_FBS0 (0x1 << 17) -#define SYS1_RRLSR_FBS0_VAL(val) (((val) & 0x1) << 17) -#define SYS1_RRLSR_FBS0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_FBS0) | (((val) & 1) << 17)) -/* SUBSYS Reset Release (16) */ -#define SYS1_RRLSR_SUBSYS (0x1 << 16) -#define SYS1_RRLSR_SUBSYS_VAL(val) (((val) & 0x1) << 16) -#define SYS1_RRLSR_SUBSYS_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_SUBSYS) | (((val) & 1) << 16)) -/* Watchdog5 Reset Release (13) */ -#define SYS1_RRLSR_WDT5 (0x1 << 13) -#define SYS1_RRLSR_WDT5_VAL(val) (((val) & 0x1) << 13) -#define SYS1_RRLSR_WDT5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT5) | (((val) & 1) << 13)) -/* Watchdog4 Reset Release (12) */ -#define SYS1_RRLSR_WDT4 (0x1 << 12) -#define SYS1_RRLSR_WDT4_VAL(val) (((val) & 0x1) << 12) -#define SYS1_RRLSR_WDT4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT4) | (((val) & 1) << 12)) -/* Watchdog3 Reset Release (11) */ -#define SYS1_RRLSR_WDT3 (0x1 << 11) -#define SYS1_RRLSR_WDT3_VAL(val) (((val) & 0x1) << 11) -#define SYS1_RRLSR_WDT3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT3) | (((val) & 1) << 11)) -/* Watchdog2 Reset Release (10) */ -#define SYS1_RRLSR_WDT2 (0x1 << 10) -#define SYS1_RRLSR_WDT2_VAL(val) (((val) & 0x1) << 10) -#define SYS1_RRLSR_WDT2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT2) | (((val) & 1) << 10)) -/* Watchdog1 Reset Release (9) */ -#define SYS1_RRLSR_WDT1 (0x1 << 9) -#define SYS1_RRLSR_WDT1_VAL(val) (((val) & 0x1) << 9) -#define SYS1_RRLSR_WDT1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT1) | (((val) & 1) << 9)) -/* Watchdog0 Reset Release (8) */ -#define SYS1_RRLSR_WDT0 (0x1 << 8) -#define SYS1_RRLSR_WDT0_VAL(val) (((val) & 0x1) << 8) -#define SYS1_RRLSR_WDT0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT0) | (((val) & 1) << 8)) -/* CPU5 Reset Release (5) */ -#define SYS1_RRLSR_CPU5 (0x1 << 5) -#define SYS1_RRLSR_CPU5_VAL(val) (((val) & 0x1) << 5) -#define SYS1_RRLSR_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU5) | (((val) & 1) << 5)) -/* CPU4 Reset Release (4) */ -#define SYS1_RRLSR_CPU4 (0x1 << 4) -#define SYS1_RRLSR_CPU4_VAL(val) (((val) & 0x1) << 4) -#define SYS1_RRLSR_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU4) | (((val) & 1) << 4)) -/* CPU3 Reset Release (3) */ -#define SYS1_RRLSR_CPU3 (0x1 << 3) -#define SYS1_RRLSR_CPU3_VAL(val) (((val) & 0x1) << 3) -#define SYS1_RRLSR_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU3) | (((val) & 1) << 3)) -/* CPU2 Reset Release (2) */ -#define SYS1_RRLSR_CPU2 (0x1 << 2) -#define SYS1_RRLSR_CPU2_VAL(val) (((val) & 0x1) << 2) -#define SYS1_RRLSR_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU2) | (((val) & 1) << 2)) -/* CPU1 Reset Release (1) */ -#define SYS1_RRLSR_CPU1 (0x1 << 1) -#define SYS1_RRLSR_CPU1_VAL(val) (((val) & 0x1) << 1) -#define SYS1_RRLSR_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU1) | (((val) & 1) << 1)) -/* CPU0 Reset Release (0) */ -#define SYS1_RRLSR_CPU0 (0x1) -#define SYS1_RRLSR_CPU0_VAL(val) (((val) & 0x1) << 0) -#define SYS1_RRLSR_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU0) | (((val) & 1) << 0)) - -#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h deleted file mode 100644 index ff9f04b4d7..0000000000 --- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h +++ /dev/null @@ -1,494 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - - ******************************************************************************/ - -#ifndef __SYS2_REG_H -#define __SYS2_REG_H - -#define sys2_r32(reg) ltq_r32(&sys2->reg) -#define sys2_w32(val, reg) ltq_w32(val, &sys2->reg) -#define sys2_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys2->reg) - -/** SYS2 register structure */ -struct svip_reg_sys2 { - volatile unsigned long clksr; /* 0x0000 */ - volatile unsigned long clkenr; /* 0x0004 */ - volatile unsigned long clkclr; /* 0x0008 */ - volatile unsigned long reserved0[1]; - volatile unsigned long rsr; /* 0x0010 */ - volatile unsigned long rreqr; /* 0x0014 */ - volatile unsigned long rrlsr; /* 0x0018 */ -}; - -/******************************************************************************* - * SYS2 Clock Status Register - ******************************************************************************/ - -/* Clock Enable for PORT4 */ -#define SYS2_CLKSR_PORT4 (0x1 << 27) -#define SYS2_CLKSR_PORT4_VAL(val) (((val) & 0x1) << 27) -#define SYS2_CLKSR_PORT4_GET(val) (((val) & SYS2_CLKSR_PORT4) >> 27) -/* Clock Enable for HWSYNC */ -#define SYS2_CLKSR_HWSYNC (0x1 << 26) -#define SYS2_CLKSR_HWSYNC_VAL(val) (((val) & -#define SYS2_CLKSR_HWSYNC_GET(val) (((val) & SYS2_CLKSR_HWSYNC) >> 26) - /* Clock Enable for MBS */ -#define SYS2_CLKSR_MBS (0x1 << 25) -#define SYS2_CLKSR_MBS_VAL(val) (((val) & 0x1) << 25) -#define SYS2_CLKSR_MBS_GET(val) (((val) & SYS2_CLKSR_MBS) >> 25) - /* Clock Enable for SWINT */ -#define SYS2_CLKSR_SWINT (0x1 << 24) -#define SYS2_CLKSR_SWINT_VAL(val) (((val) & 0x1) << 24) -#define SYS2_CLKSR_SWINT_GET(val) (((val) & SYS2_CLKSR_SWINT) >> 24) - /* Clock Enable for HWACC3 */ -#define SYS2_CLKSR_HWACC3 (0x1 << 19) -#define SYS2_CLKSR_HWACC3_VAL(val) (((val) & -#define SYS2_CLKSR_HWACC3_GET(val) (((val) & SYS2_CLKSR_HWACC3) >> 19) - /* Clock Enable for HWACC2 */ -#define SYS2_CLKSR_HWACC2 (0x1 << 18) -#define SYS2_CLKSR_HWACC2_VAL(val) (((val) & -#define SYS2_CLKSR_HWACC2_GET(val) (((val) & SYS2_CLKSR_HWACC2) >> 18) - /* Clock Enable for HWACC1 */ -#define SYS2_CLKSR_HWACC1 (0x1 << 17) -#define SYS2_CLKSR_HWACC1_VAL(val) (((val) & -#define SYS2_CLKSR_HWACC1_GET(val) (((val) & SYS2_CLKSR_HWACC1) >> 17) - /* Clock Enable for HWACC0 */ -#define SYS2_CLKSR_HWACC0 (0x1 << 16) -#define SYS2_CLKSR_HWACC0_VAL(val) (((val) & -#define SYS2_CLKSR_HWACC0_GET(val) (((val) & SYS2_CLKSR_HWACC0) >> 16) - /* Clock Enable for SIF7 */ -#define SYS2_CLKSR_SIF7 (0x1 << 15) -#define SYS2_CLKSR_SIF7_VAL(val) (((val) & 0x1) << 15) -#define SYS2_CLKSR_SIF7_GET(val) (((val) & SYS2_CLKSR_SIF7) >> 15) - /* Clock Enable for SIF6 */ -#define SYS2_CLKSR_SIF6 (0x1 << 14) -#define SYS2_CLKSR_SIF6_VAL(val) (((val) & 0x1) << 14) -#define SYS2_CLKSR_SIF6_GET(val) (((val) & SYS2_CLKSR_SIF6) >> 14) - /* Clock Enable for SIF5 */ -#define SYS2_CLKSR_SIF5 (0x1 << 13) -#define SYS2_CLKSR_SIF5_VAL(val) (((val) & 0x1) << 13) -#define SYS2_CLKSR_SIF5_GET(val) (((val) & SYS2_CLKSR_SIF5) >> 13) - /* Clock Enable for SIF4 */ -#define SYS2_CLKSR_SIF4 (0x1 << 12) -#define SYS2_CLKSR_SIF4_VAL(val) (((val) & 0x1) << 12) -#define SYS2_CLKSR_SIF4_GET(val) (((val) & SYS2_CLKSR_SIF4) >> 12) - /* Clock Enable for SIF3 */ -#define SYS2_CLKSR_SIF3 (0x1 << 11) -#define SYS2_CLKSR_SIF3_VAL(val) (((val) & 0x1) << 11) -#define SYS2_CLKSR_SIF3_GET(val) (((val) & SYS2_CLKSR_SIF3) >> 11) -/* Clock Enable for SIF2 */ -#define SYS2_CLKSR_SIF2 (0x1 << 10) -#define SYS2_CLKSR_SIF2_VAL(val) (((val) & 0x1) << 10) -#define SYS2_CLKSR_SIF2_GET(val) (((val) & SYS2_CLKSR_SIF2) >> 10) -/* Clock Enable for SIF1 */ -#define SYS2_CLKSR_SIF1 (0x1 << 9) -#define SYS2_CLKSR_SIF1_VAL(val) (((val) & 0x1) << 9) -#define SYS2_CLKSR_SIF1_GET(val) (((val) & SYS2_CLKSR_SIF1) >> 9) -/* Clock Enable for SIF0 */ -#define SYS2_CLKSR_SIF0 (0x1 << 8) -#define SYS2_CLKSR_SIF0_VAL(val) (((val) & 0x1) << 8) -#define SYS2_CLKSR_SIF0_GET(val) (((val) & SYS2_CLKSR_SIF0) >> 8) -/* Clock Enable for DFEV7 */ -#define SYS2_CLKSR_DFEV7 (0x1 << 7) -#define SYS2_CLKSR_DFEV7_VAL(val) (((val) & 0x1) << 7) -#define SYS2_CLKSR_DFEV7_GET(val) (((val) & SYS2_CLKSR_DFEV7) >> 7) -/* Clock Enable for DFEV6 */ -#define SYS2_CLKSR_DFEV6 (0x1 << 6) -#define SYS2_CLKSR_DFEV6_VAL(val) (((val) & 0x1) << 6) -#define SYS2_CLKSR_DFEV6_GET(val) (((val) & SYS2_CLKSR_DFEV6) >> 6) -/* Clock Enable for DFEV5 */ -#define SYS2_CLKSR_DFEV5 (0x1 << 5) -#define SYS2_CLKSR_DFEV5_VAL(val) (((val) & 0x1) << 5) -#define SYS2_CLKSR_DFEV5_GET(val) (((val) & SYS2_CLKSR_DFEV5) >> 5) -/* Clock Enable for DFEV4 */ -#define SYS2_CLKSR_DFEV4 (0x1 << 4) -#define SYS2_CLKSR_DFEV4_VAL(val) (((val) & 0x1) << 4) -#define SYS2_CLKSR_DFEV4_GET(val) (((val) & SYS2_CLKSR_DFEV4) >> 4) -/* Clock Enable for DFEV3 */ -#define SYS2_CLKSR_DFEV3 (0x1 << 3) -#define SYS2_CLKSR_DFEV3_VAL(val) (((val) & 0x1) << 3) -#define SYS2_CLKSR_DFEV3_GET(val) (((val) & SYS2_CLKSR_DFEV3) >> 3) -/* Clock Enable for DFEV2 */ -#define SYS2_CLKSR_DFEV2 (0x1 << 2) -#define SYS2_CLKSR_DFEV2_VAL(val) (((val) & 0x1) << 2) -#define SYS2_CLKSR_DFEV2_GET(val) (((val) & SYS2_CLKSR_DFEV2) >> 2) -/* Clock Enable for DFEV1 */ -#define SYS2_CLKSR_DFEV1 (0x1 << 1) -#define SYS2_CLKSR_DFEV1_VAL(val) (((val) & 0x1) << 1) -#define SYS2_CLKSR_DFEV1_GET(val) (((val) & SYS2_CLKSR_DFEV1) >> 1) -/* Clock Enable for DFEV0 */ -#define SYS2_CLKSR_DFEV0 (0x1) -#define SYS2_CLKSR_DFEV0_VAL(val) (((val) & 0x1)) -#define SYS2_CLKSR_DFEV0_GET(val) ((val) & SYS2_CLKSR_DFEV0) - -/******************************************************************************* - * SYS2 Clock Enable Register - ******************************************************************************/ - -/* Clock Enable Request for PORT4 */ -#define SYS2_CLKENR_PORT4 (0x1 << 27) -#define SYS2_CLKENR_PORT4_VAL(val) (((val) & 0x1) << 27) -#define SYS2_CLKENR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_PORT4) | ((val & 0x1) << 27)) -/* Clock Enable Request for HWSYNC */ -#define SYS2_CLKENR_HWSYNC (0x1 << 26) -#define SYS2_CLKENR_HWSYNC_VAL(val) (((val) & 0x1) << 26) -#define SYS2_CLKENR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWSYNC) | ((val & 0x1) << 26)) -/* Clock Enable Request for MBS */ -#define SYS2_CLKENR_MBS (0x1 << 25) -#define SYS2_CLKENR_MBS_VAL(val) (((val) & 0x1) << 25) -#define SYS2_CLKENR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_MBS) | ((val & 0x1) << 25)) -/* Clock Enable Request for SWINT */ -#define SYS2_CLKENR_SWINT (0x1 << 24) -#define SYS2_CLKENR_SWINT_VAL(val) (((val) & 0x1) << 24) -#define SYS2_CLKENR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SWINT) | ((val & 0x1) << 24)) -/* Clock Enable Request for HWACC3 */ -#define SYS2_CLKENR_HWACC3 (0x1 << 19) -#define SYS2_CLKENR_HWACC3_VAL(val) (((val) & 0x1) << 19) -#define SYS2_CLKENR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC3) | ((val & 0x1) << 19)) -/* Clock Enable Request for HWACC2 */ -#define SYS2_CLKENR_HWACC2 (0x1 << 18) -#define SYS2_CLKENR_HWACC2_VAL(val) (((val) & 0x1) << 18) -#define SYS2_CLKENR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC2) | ((val & 0x1) << 18)) -/* Clock Enable Request for HWACC1 */ -#define SYS2_CLKENR_HWACC1 (0x1 << 17) -#define SYS2_CLKENR_HWACC1_VAL(val) (((val) & 0x1) << 17) -#define SYS2_CLKENR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC1) | ((val & 0x1) << 17)) -/* Clock Enable Request for HWACC0 */ -#define SYS2_CLKENR_HWACC0 (0x1 << 16) -#define SYS2_CLKENR_HWACC0_VAL(val) (((val) & 0x1) << 16) -#define SYS2_CLKENR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC0) | ((val & 0x1) << 16)) -/* Clock Enable Request for SIF7 */ -#define SYS2_CLKENR_SIF7 (0x1 << 15) -#define SYS2_CLKENR_SIF7_VAL(val) (((val) & 0x1) << 15) -#define SYS2_CLKENR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF7) | ((val & 0x1) << 15)) -/* Clock Enable Request for SIF6 */ -#define SYS2_CLKENR_SIF6 (0x1 << 14) -#define SYS2_CLKENR_SIF6_VAL(val) (((val) & 0x1) << 14) -#define SYS2_CLKENR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF6) | ((val & 0x1) << 14)) -/* Clock Enable Request for SIF5 */ -#define SYS2_CLKENR_SIF5 (0x1 << 13) -#define SYS2_CLKENR_SIF5_VAL(val) (((val) & 0x1) << 13) -#define SYS2_CLKENR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF5) | ((val & 0x1) << 13)) -/* Clock Enable Request for SIF4 */ -#define SYS2_CLKENR_SIF4 (0x1 << 12) -#define SYS2_CLKENR_SIF4_VAL(val) (((val) & 0x1) << 12) -#define SYS2_CLKENR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF4) | ((val & 0x1) << 12)) -/* Clock Enable Request for SIF3 */ -#define SYS2_CLKENR_SIF3 (0x1 << 11) -#define SYS2_CLKENR_SIF3_VAL(val) (((val) & 0x1) << 11) -#define SYS2_CLKENR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF3) | ((val & 0x1) << 11)) -/* Clock Enable Request for SIF2 */ -#define SYS2_CLKENR_SIF2 (0x1 << 10) -#define SYS2_CLKENR_SIF2_VAL(val) (((val) & 0x1) << 10) -#define SYS2_CLKENR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF2) | ((val & 0x1) << 10)) -/* Clock Enable Request for SIF1 */ -#define SYS2_CLKENR_SIF1 (0x1 << 9) -#define SYS2_CLKENR_SIF1_VAL(val) (((val) & 0x1) << 9) -#define SYS2_CLKENR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF1) | ((val & 0x1) << 9)) -/* Clock Enable Request for SIF0 */ -#define SYS2_CLKENR_SIF0 (0x1 << 8) -#define SYS2_CLKENR_SIF0_VAL(val) (((val) & 0x1) << 8) -#define SYS2_CLKENR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF0) | ((val & 0x1) << 8)) -/* Clock Enable Request for DFEV7 */ -#define SYS2_CLKENR_DFEV7 (0x1 << 7) -#define SYS2_CLKENR_DFEV7_VAL(val) (((val) & 0x1) << 7) -#define SYS2_CLKENR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV7) | ((val & 0x1) << 7)) -/* Clock Enable Request for DFEV6 */ -#define SYS2_CLKENR_DFEV6 (0x1 << 6) -#define SYS2_CLKENR_DFEV6_VAL(val) (((val) & 0x1) << 6) -#define SYS2_CLKENR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV6) | ((val & 0x1) << 6)) -/* Clock Enable Request for DFEV5 */ -#define SYS2_CLKENR_DFEV5 (0x1 << 5) -#define SYS2_CLKENR_DFEV5_VAL(val) (((val) & 0x1) << 5) -#define SYS2_CLKENR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV5) | ((val & 0x1) << 5)) -/* Clock Enable Request for DFEV4 */ -#define SYS2_CLKENR_DFEV4 (0x1 << 4) -#define SYS2_CLKENR_DFEV4_VAL(val) (((val) & 0x1) << 4) -#define SYS2_CLKENR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV4) | ((val & 0x1) << 4)) -/* Clock Enable Request for DFEV3 */ -#define SYS2_CLKENR_DFEV3 (0x1 << 3) -#define SYS2_CLKENR_DFEV3_VAL(val) (((val) & 0x1) << 3) -#define SYS2_CLKENR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV3) | ((val & 0x1) << 3)) -/* Clock Enable Request for DFEV2 */ -#define SYS2_CLKENR_DFEV2 (0x1 << 2) -#define SYS2_CLKENR_DFEV2_VAL(val) (((val) & 0x1) << 2) -#define SYS2_CLKENR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV2) | ((val & 0x1) << 2)) -/* Clock Enable Request for DFEV1 */ -#define SYS2_CLKENR_DFEV1 (0x1 << 1) -#define SYS2_CLKENR_DFEV1_VAL(val) (((val) & 0x1) << 1) -#define SYS2_CLKENR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV1) | ((val & 0x1) << 1)) -/* Clock Enable Request for DFEV0 */ -#define SYS2_CLKENR_DFEV0 (0x1) -#define SYS2_CLKENR_DFEV0_VAL(val) (((val) & 0x1)) -#define SYS2_CLKENR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV0) | ((val & 0x1))) - -/******************************************************************************* - * SYS2 Clock Clear Register - ******************************************************************************/ - -/* Clock Disable Request for PORT4 */ -#define SYS2_CLKCLR_PORT4 (0x1 << 27) -#define SYS2_CLKCLR_PORT4_VAL(val) (((val) & 0x1) << 27) -#define SYS2_CLKCLR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_PORT4) | ((val & 0x1) << 27)) -/* Clock Disable Request for HWSYNC */ -#define SYS2_CLKCLR_HWSYNC (0x1 << 26) -#define SYS2_CLKCLR_HWSYNC_VAL(val) (((val) & 0x1) << 26) -#define SYS2_CLKCLR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWSYNC) | ((val & 0x1) << 26)) -/* Clock Disable Request for MBS */ -#define SYS2_CLKCLR_MBS (0x1 << 25) -#define SYS2_CLKCLR_MBS_VAL(val) (((val) & 0x1) << 25) -#define SYS2_CLKCLR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_MBS) | ((val & 0x1) << 25)) -/* Clock Disable Request for SWINT */ -#define SYS2_CLKCLR_SWINT (0x1 << 24) -#define SYS2_CLKCLR_SWINT_VAL(val) (((val) & 0x1) << 24) -#define SYS2_CLKCLR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SWINT) | ((val & 0x1) << 24)) -/* Clock Disable Request for HWACC3 */ -#define SYS2_CLKCLR_HWACC3 (0x1 << 19) -#define SYS2_CLKCLR_HWACC3_VAL(val) (((val) & 0x1) << 19) -#define SYS2_CLKCLR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC3) | ((val & 0x1) << 19)) -/* Clock Disable Request for HWACC2 */ -#define SYS2_CLKCLR_HWACC2 (0x1 << 18) -#define SYS2_CLKCLR_HWACC2_VAL(val) (((val) & 0x1) << 18) -#define SYS2_CLKCLR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC2) | ((val & 0x1) << 18)) -/* Clock Disable Request for HWACC1 */ -#define SYS2_CLKCLR_HWACC1 (0x1 << 17) -#define SYS2_CLKCLR_HWACC1_VAL(val) (((val) & 0x1) << 17) -#define SYS2_CLKCLR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC1) | ((val & 0x1) << 17)) -/* Clock Disable Request for HWACC0 */ -#define SYS2_CLKCLR_HWACC0 (0x1 << 16) -#define SYS2_CLKCLR_HWACC0_VAL(val) (((val) & 0x1) << 16) -#define SYS2_CLKCLR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC0) | ((val & 0x1) << 16)) -/* Clock Disable Request for SIF7 */ -#define SYS2_CLKCLR_SIF7 (0x1 << 15) -#define SYS2_CLKCLR_SIF7_VAL(val) (((val) & 0x1) << 15) -#define SYS2_CLKCLR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF7) | ((val & 0x1) << 15)) -/* Clock Disable Request for SIF6 */ -#define SYS2_CLKCLR_SIF6 (0x1 << 14) -#define SYS2_CLKCLR_SIF6_VAL(val) (((val) & 0x1) << 14) -#define SYS2_CLKCLR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF6) | ((val & 0x1) << 14)) -/* Clock Disable Request for SIF5 */ -#define SYS2_CLKCLR_SIF5 (0x1 << 13) -#define SYS2_CLKCLR_SIF5_VAL(val) (((val) & 0x1) << 13) -#define SYS2_CLKCLR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF5) | ((val & 0x1) << 13)) -/* Clock Disable Request for SIF4 */ -#define SYS2_CLKCLR_SIF4 (0x1 << 12) -#define SYS2_CLKCLR_SIF4_VAL(val) (((val) & 0x1) << 12) -#define SYS2_CLKCLR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF4) | ((val & 0x1) << 12)) -/* Clock Disable Request for SIF3 */ -#define SYS2_CLKCLR_SIF3 (0x1 << 11) -#define SYS2_CLKCLR_SIF3_VAL(val) (((val) & 0x1) << 11) -#define SYS2_CLKCLR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF3) | ((val & 0x1) << 11)) -/* Clock Disable Request for SIF2 */ -#define SYS2_CLKCLR_SIF2 (0x1 << 10) -#define SYS2_CLKCLR_SIF2_VAL(val) (((val) & 0x1) << 10) -#define SYS2_CLKCLR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF2) | ((val & 0x1) << 10)) -/* Clock Disable Request for SIF1 */ -#define SYS2_CLKCLR_SIF1 (0x1 << 9) -#define SYS2_CLKCLR_SIF1_VAL(val) (((val) & 0x1) << 9) -#define SYS2_CLKCLR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF1) | ((val & 0x1) << 9)) -/* Clock Disable Request for SIF0 */ -#define SYS2_CLKCLR_SIF0 (0x1 << 8) -#define SYS2_CLKCLR_SIF0_VAL(val) (((val) & 0x1) << 8) -#define SYS2_CLKCLR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF0) | ((val & 0x1) << 8)) -/* Clock Disable Request for DFEV7 */ -#define SYS2_CLKCLR_DFEV7 (0x1 << 7) -#define SYS2_CLKCLR_DFEV7_VAL(val) (((val) & 0x1) << 7) -#define SYS2_CLKCLR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV7) | ((val & 0x1) << 7)) -/* Clock Disable Request for DFEV6 */ -#define SYS2_CLKCLR_DFEV6 (0x1 << 6) -#define SYS2_CLKCLR_DFEV6_VAL(val) (((val) & 0x1) << 6) -#define SYS2_CLKCLR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV6) | ((val & 0x1) << 6)) -/* Clock Disable Request for DFEV5 */ -#define SYS2_CLKCLR_DFEV5 (0x1 << 5) -#define SYS2_CLKCLR_DFEV5_VAL(val) (((val) & 0x1) << 5) -#define SYS2_CLKCLR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV5) | ((val & 0x1) << 5)) -/* Clock Disable Request for DFEV4 */ -#define SYS2_CLKCLR_DFEV4 (0x1 << 4) -#define SYS2_CLKCLR_DFEV4_VAL(val) (((val) & 0x1) << 4) -#define SYS2_CLKCLR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV4) | ((val & 0x1) << 4)) -/* Clock Disable Request for DFEV3 */ -#define SYS2_CLKCLR_DFEV3 (0x1 << 3) -#define SYS2_CLKCLR_DFEV3_VAL(val) (((val) & 0x1) << 3) -#define SYS2_CLKCLR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV3) | ((val & 0x1) << 3)) -/* Clock Disable Request for DFEV2 */ -#define SYS2_CLKCLR_DFEV2 (0x1 << 2) -#define SYS2_CLKCLR_DFEV2_VAL(val) (((val) & 0x1) << 2) -#define SYS2_CLKCLR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV2) | ((val & 0x1) << 2)) -/* Clock Disable Request for DFEV1 */ -#define SYS2_CLKCLR_DFEV1 (0x1 << 1) -#define SYS2_CLKCLR_DFEV1_VAL(val) (((val) & 0x1) << 1) -#define SYS2_CLKCLR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV1) | ((val & 0x1) << 1)) -/* Clock Disable Request for DFEV0 */ -#define SYS2_CLKCLR_DFEV0 (0x1) -#define SYS2_CLKCLR_DFEV0_VAL(val) (((val) & 0x1)) -#define SYS2_CLKCLR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV0) | ((val & 0x1))) - -/******************************************************************************* - * SYS2 Reset Status Register - ******************************************************************************/ - -/* HWACC3 Reset */ -#define SYS2_RSR_HWACC3 (0x1 << 11) -#define SYS2_RSR_HWACC3_VAL(val) (((val) & 0x1) << 11) -#define SYS2_RSR_HWACC3_GET(val) (((val) & SYS2_RSR_HWACC3) >> 11) -/* HWACC2 Reset */ -#define SYS2_RSR_HWACC2 (0x1 << 10) -#define SYS2_RSR_HWACC2_VAL(val) (((val) & 0x1) << 10) -#define SYS2_RSR_HWACC2_GET(val) (((val) & SYS2_RSR_HWACC2) >> 10) -/* HWACC1 Reset */ -#define SYS2_RSR_HWACC1 (0x1 << 9) -#define SYS2_RSR_HWACC1_VAL(val) (((val) & 0x1) << 9) -#define SYS2_RSR_HWACC1_GET(val) (((val) & SYS2_RSR_HWACC1) >> 9) -/* HWACC0 Reset */ -#define SYS2_RSR_HWACC0 (0x1 << 8) -#define SYS2_RSR_HWACC0_VAL(val) (((val) & 0x1) << 8) -#define SYS2_RSR_HWACC0_GET(val) (((val) & SYS2_RSR_HWACC0) >> 8) -/* DFEV7 Reset */ -#define SYS2_RSR_DFEV7 (0x1 << 7) -#define SYS2_RSR_DFEV7_VAL(val) (((val) & 0x1) << 7) -#define SYS2_RSR_DFEV7_GET(val) (((val) & SYS2_RSR_DFEV7) >> 7) -/* DFEV6 Reset */ -#define SYS2_RSR_DFEV6 (0x1 << 6) -#define SYS2_RSR_DFEV6_VAL(val) (((val) & 0x1) << 6) -#define SYS2_RSR_DFEV6_GET(val) (((val) & SYS2_RSR_DFEV6) >> 6) -/* DFEV5 Reset */ -#define SYS2_RSR_DFEV5 (0x1 << 5) -#define SYS2_RSR_DFEV5_VAL(val) (((val) & 0x1) << 5) -#define SYS2_RSR_DFEV5_GET(val) (((val) & SYS2_RSR_DFEV5) >> 5) -/* DFEV4 Reset */ -#define SYS2_RSR_DFEV4 (0x1 << 4) -#define SYS2_RSR_DFEV4_VAL(val) (((val) & 0x1) << 4) -#define SYS2_RSR_DFEV4_GET(val) (((val) & SYS2_RSR_DFEV4) >> 4) -/* DFEV3 Reset */ -#define SYS2_RSR_DFEV3 (0x1 << 3) -#define SYS2_RSR_DFEV3_VAL(val) (((val) & 0x1) << 3) -#define SYS2_RSR_DFEV3_GET(val) (((val) & SYS2_RSR_DFEV3) >> 3) -/* DFEV2 Reset */ -#define SYS2_RSR_DFEV2 (0x1 << 2) -#define SYS2_RSR_DFEV2_VAL(val) (((val) & 0x1) << 2) -#define SYS2_RSR_DFEV2_GET(val) (((val) & SYS2_RSR_DFEV2) >> 2) -/* DFEV1 Reset */ -#define SYS2_RSR_DFEV1 (0x1 << 1) -#define SYS2_RSR_DFEV1_VAL(val) (((val) & 0x1) << 1) -#define SYS2_RSR_DFEV1_GET(val) (((val) & SYS2_RSR_DFEV1) >> 1) -/* DFEV0 Reset */ -#define SYS2_RSR_DFEV0 (0x1) -#define SYS2_RSR_DFEV0_VAL(val) (((val) & 0x1)) -#define SYS2_RSR_DFEV0_GET(val) ((val) & SYS2_RSR_DFEV0) - -/****************************************************************************** - * SYS2 Reset Request Register - ******************************************************************************/ - -/* HWACC3 Reset Request */ -#define SYS2_RREQR_HWACC3 (0x1 << 11) -#define SYS2_RREQR_HWACC3_VAL(val) (((val) & 0x1) << 11) -#define SYS2_RREQR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC3) | ((val & 0x1) << 11)) -/* HWACC2 Reset Request */ -#define SYS2_RREQR_HWACC2 (0x1 << 10) -#define SYS2_RREQR_HWACC2_VAL(val) (((val) & 0x1) << 10) -#define SYS2_RREQR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC2) | ((val & 0x1) << 10)) -/* HWACC1 Reset Request */ -#define SYS2_RREQR_HWACC1 (0x1 << 9) -#define SYS2_RREQR_HWACC1_VAL(val) (((val) & 0x1) << 9) -#define SYS2_RREQR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC1) | ((val & 0x1) << 9)) -/* HWACC0 Reset Request */ -#define SYS2_RREQR_HWACC0 (0x1 << 8) -#define SYS2_RREQR_HWACC0_VAL(val) (((val) & 0x1) << 8) -#define SYS2_RREQR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC0) | ((val & 0x1) << 8)) -/* DFEV7 Reset Request */ -#define SYS2_RREQR_DFEV7 (0x1 << 7) -#define SYS2_RREQR_DFEV7_VAL(val) (((val) & 0x1) << 7) -#define SYS2_RREQR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV7) | ((val & 0x1) << 7)) -/* DFEV6 Reset Request */ -#define SYS2_RREQR_DFEV6 (0x1 << 6) -#define SYS2_RREQR_DFEV6_VAL(val) (((val) & 0x1) << 6) -#define SYS2_RREQR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV6) | ((val & 0x1) << 6)) -/* DFEV5 Reset Request */ -#define SYS2_RREQR_DFEV5 (0x1 << 5) -#define SYS2_RREQR_DFEV5_VAL(val) (((val) & 0x1) << 5) -#define SYS2_RREQR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV5) | ((val & 0x1) << 5)) -/* DFEV4 Reset Request */ -#define SYS2_RREQR_DFEV4 (0x1 << 4) -#define SYS2_RREQR_DFEV4_VAL(val) (((val) & 0x1) << 4) -#define SYS2_RREQR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV4) | ((val & 0x1) << 4)) -/* DFEV3 Reset Request */ -#define SYS2_RREQR_DFEV3 (0x1 << 3) -#define SYS2_RREQR_DFEV3_VAL(val) (((val) & 0x1) << 3) -#define SYS2_RREQR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV3) | ((val & 0x1) << 3)) -/* DFEV2 Reset Request */ -#define SYS2_RREQR_DFEV2 (0x1 << 2) -#define SYS2_RREQR_DFEV2_VAL(val) (((val) & 0x1) << 2) -#define SYS2_RREQR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV2) | ((val & 0x1) << 2)) -/* DFEV1 Reset Request */ -#define SYS2_RREQR_DFEV1 (0x1 << 1) -#define SYS2_RREQR_DFEV1_VAL(val) (((val) & 0x1) << 1) -#define SYS2_RREQR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV1) | ((val & 0x1) << 1)) -/* DFEV0 Reset Request */ -#define SYS2_RREQR_DFEV0 (0x1) -#define SYS2_RREQR_DFEV0_VAL(val) (((val) & 0x1)) -#define SYS2_RREQR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV0) | ((val & 0x1))) - -/******************************************************************************* - * SYS2 Reset Release Register - ******************************************************************************/ - -/* HWACC3 Reset Release */ -#define SYS2_RRLSR_HWACC3 (0x1 << 11) -#define SYS2_RRLSR_HWACC3_VAL(val) (((val) & 0x1) << 11) -#define SYS2_RRLSR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC3) | ((val & 0x1) << 11)) -/* HWACC2 Reset Release */ -#define SYS2_RRLSR_HWACC2 (0x1 << 10) -#define SYS2_RRLSR_HWACC2_VAL(val) (((val) & 0x1) << 10) -#define SYS2_RRLSR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC2) | ((val & 0x1) << 10)) -/* HWACC1 Reset Release */ -#define SYS2_RRLSR_HWACC1 (0x1 << 9) -#define SYS2_RRLSR_HWACC1_VAL(val) (((val) & 0x1) << 9) -#define SYS2_RRLSR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC1) | ((val & 0x1) << 9)) -/* HWACC0 Reset Release */ -#define SYS2_RRLSR_HWACC0 (0x1 << 8) -#define SYS2_RRLSR_HWACC0_VAL(val) (((val) & 0x1) << 8) -#define SYS2_RRLSR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC0) | ((val & 0x1) << 8)) -/* DFEV7 Reset Release */ -#define SYS2_RRLSR_DFEV7 (0x1 << 7) -#define SYS2_RRLSR_DFEV7_VAL(val) (((val) & 0x1) << 7) -#define SYS2_RRLSR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV7) | ((val & 0x1) << 7)) -/* DFEV6 Reset Release */ -#define SYS2_RRLSR_DFEV6 (0x1 << 6) -#define SYS2_RRLSR_DFEV6_VAL(val) (((val) & 0x1) << 6) -#define SYS2_RRLSR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV6) | ((val & 0x1) << 6)) -/* DFEV5 Reset Release */ -#define SYS2_RRLSR_DFEV5 (0x1 << 5) -#define SYS2_RRLSR_DFEV5_VAL(val) (((val) & 0x1) << 5) -#define SYS2_RRLSR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV5) | ((val & 0x1) << 5)) -/* DFEV4 Reset Release */ -#define SYS2_RRLSR_DFEV4 (0x1 << 4) -#define SYS2_RRLSR_DFEV4_VAL(val) (((val) & 0x1) << 4) -#define SYS2_RRLSR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV4) | ((val & 0x1) << 4)) -/* DFEV3 Reset Release */ -#define SYS2_RRLSR_DFEV3 (0x1 << 3) -#define SYS2_RRLSR_DFEV3_VAL(val) (((val) & 0x1) << 3) -#define SYS2_RRLSR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV3) | ((val & 0x1) << 3)) -/* DFEV2 Reset Release */ -#define SYS2_RRLSR_DFEV2 (0x1 << 2) -#define SYS2_RRLSR_DFEV2_VAL(val) (((val) & 0x1) << 2) -#define SYS2_RRLSR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV2) | ((val & 0x1) << 2)) -/* DFEV1 Reset Release */ -#define SYS2_RRLSR_DFEV1 (0x1 << 1) -#define SYS2_RRLSR_DFEV1_VAL(val) (((val) & 0x1) << 1) -#define SYS2_RRLSR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV1) | ((val & 0x1) << 1)) -/* DFEV0 Reset Release */ -#define SYS2_RRLSR_DFEV0 (0x1) -#define SYS2_RRLSR_DFEV0_VAL(val) (((val) & 0x1)) -#define SYS2_RRLSR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV0) | ((val & 0x1))) - -#endif /* __SYS2_H */ - diff --git a/target/linux/lantiq/files/arch/mips/lantiq/dev-gpio-buttons.c b/target/linux/lantiq/files/arch/mips/lantiq/dev-gpio-buttons.c deleted file mode 100644 index ad25cac797..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/dev-gpio-buttons.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Lantiq GPIO button support - * - * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/platform_device.h> - -#include <dev-gpio-buttons.h> - -void __init ltq_register_gpio_keys_polled(int id, - unsigned poll_interval, - unsigned nbuttons, - struct gpio_keys_button *buttons) -{ - struct platform_device *pdev; - struct gpio_keys_platform_data pdata; - struct gpio_keys_button *p; - int err; - - p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); - if (!p) - return; - - memcpy(p, buttons, nbuttons * sizeof(*p)); - - pdev = platform_device_alloc("gpio-keys-polled", id); - if (!pdev) - goto err_free_buttons; - - memset(&pdata, 0, sizeof(pdata)); - pdata.poll_interval = poll_interval; - pdata.nbuttons = nbuttons; - pdata.buttons = p; - - err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); - if (err) - goto err_put_pdev; - - err = platform_device_add(pdev); - if (err) - goto err_put_pdev; - - return; - -err_put_pdev: - platform_device_put(pdev); - -err_free_buttons: - kfree(p); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/dev-gpio-leds.c b/target/linux/lantiq/files/arch/mips/lantiq/dev-gpio-leds.c deleted file mode 100644 index 89dc79de61..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/dev-gpio-leds.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Lantiq GPIO LED device support - * - * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * Parts of this file are based on Atheros' 2.6.15 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/platform_device.h> - -#include <dev-gpio-leds.h> - -void __init ltq_add_device_gpio_leds(int id, unsigned num_leds, - struct gpio_led *leds) -{ - struct platform_device *pdev; - struct gpio_led_platform_data pdata; - struct gpio_led *p; - int err; - - p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); - if (!p) - return; - - memcpy(p, leds, num_leds * sizeof(*p)); - - pdev = platform_device_alloc("leds-gpio", id); - if (!pdev) - goto err_free_leds; - - memset(&pdata, 0, sizeof(pdata)); - pdata.num_leds = num_leds; - pdata.leds = p; - - err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); - if (err) - goto err_put_pdev; - - err = platform_device_add(pdev); - if (err) - goto err_put_pdev; - - return; - -err_put_pdev: - platform_device_put(pdev); - -err_free_leds: - kfree(p); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/Kconfig b/target/linux/lantiq/files/arch/mips/lantiq/falcon/Kconfig deleted file mode 100644 index 03e999d92e..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -if SOC_FALCON - -menu "MIPS Machine" - -config LANTIQ_MACH_EASY98000 - bool "Easy98000" - default y - -endmenu - -endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/Makefile b/target/linux/lantiq/files/arch/mips/lantiq/falcon/Makefile deleted file mode 100644 index 3634154fb9..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-y := prom.o reset.o sysctrl.o devices.o gpio.o -obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/addon-easy98000.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/addon-easy98000.c deleted file mode 100644 index 317ee4001b..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/addon-easy98000.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * EASY98000 CPLD Addon driver - * - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/version.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/errno.h> -#include <linux/slab.h> -#include <linux/proc_fs.h> -#include <linux/seq_file.h> - -struct easy98000_reg_cpld { - u16 cmdreg1; /* 0x1 */ - u16 cmdreg0; /* 0x0 */ - u16 idreg0; /* 0x3 */ - u16 resreg; /* 0x2 */ - u16 intreg; /* 0x5 */ - u16 idreg1; /* 0x4 */ - u16 ledreg; /* 0x7 */ - u16 pcmconconfig; /* 0x6 */ - u16 res0; /* 0x9 */ - u16 ethledreg; /* 0x8 */ - u16 res1[4]; /* 0xa-0xd */ - u16 cpld1v; /* 0xf */ - u16 cpld2v; /* 0xe */ -}; -static struct easy98000_reg_cpld * const cpld = - (struct easy98000_reg_cpld *)(KSEG1 | 0x17c00000); -#define cpld_r8(reg) (__raw_readw(&cpld->reg) & 0xFF) -#define cpld_w8(val, reg) __raw_writew((val) & 0xFF, &cpld->reg) - -int easy98000_addon_has_dm9000(void) -{ - if ((cpld_r8(idreg0) & 0xF) == 1) - return 1; - return 0; -} - -#if defined(CONFIG_PROC_FS) -typedef void (*cpld_dump) (struct seq_file *s); -struct proc_entry { - char *name; - void *callback; -}; - -static int cpld_proc_show ( struct seq_file *s, void *p ) -{ - cpld_dump dump = s->private; - - if ( dump != NULL ) - dump(s); - - return 0; -} - -static int cpld_proc_open ( struct inode *inode, struct file *file ) -{ - return single_open ( file, cpld_proc_show, PDE(inode)->data ); -} - -static void cpld_versions_get ( struct seq_file *s ) -{ - seq_printf(s, "CPLD1: V%d\n", cpld_r8(cpld1v)); - seq_printf(s, "CPLD2: V%d\n", cpld_r8(cpld2v)); -} - -static void cpld_ebu_module_get ( struct seq_file *s ) -{ - u8 addon_id; - - addon_id = cpld_r8(idreg0) & 0xF; - switch (addon_id) { - case 0xF: /* nothing connected */ - break; - case 1: - seq_printf(s, "Ethernet Controller module (dm9000)\n"); - break; - default: - seq_printf(s, "Unknown EBU module (EBU_ID=0x%02X)\n", addon_id); - break; - } -} - -static void cpld_xmii_module_get ( struct seq_file *s ) -{ - u8 addon_id; - char *mod = NULL; - - addon_id = cpld_r8(idreg1) & 0xF; - switch (addon_id) { - case 0xF: - mod = "no module"; - break; - case 0x1: - mod = "RGMII module"; - break; - case 0x4: - mod = "GMII MAC Mode (XWAY TANTOS-3G)"; - break; - case 0x6: - mod = "TMII MAC Mode (XWAY TANTOS-3G)"; - break; - case 0x8: - mod = "GMII PHY module"; - break; - case 0x9: - mod = "MII PHY module"; - break; - case 0xA: - mod = "RMII PHY module"; - break; - default: - break; - } - if (mod) - seq_printf(s, "%s\n", mod); - else - seq_printf(s, "unknown xMII module (xMII_ID=0x%02X)\n", addon_id); -} - -static struct proc_entry proc_entries[] = { - {"versions", cpld_versions_get}, - {"ebu", cpld_ebu_module_get}, - {"xmii", cpld_xmii_module_get}, -}; - -static struct file_operations ops = { - .owner = THIS_MODULE, - .open = cpld_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static void cpld_proc_entry_create(struct proc_dir_entry *parent_node, - struct proc_entry *proc_entry) -{ - proc_create_data ( proc_entry->name, (S_IFREG | S_IRUGO), parent_node, - &ops, proc_entry->callback); -} - -static int cpld_proc_install(void) -{ - struct proc_dir_entry *driver_proc_node; - - driver_proc_node = proc_mkdir("cpld", NULL); - if (driver_proc_node != NULL) { - int i; - for (i = 0; i < ARRAY_SIZE(proc_entries); i++) - cpld_proc_entry_create(driver_proc_node, - &proc_entries[i]); - } else { - printk("cannot create proc entry"); - return -1; - } - return 0; -} -#else -static inline int cpld_proc_install(void) {} -#endif - -static int easy98000_addon_probe(struct platform_device *pdev) -{ - return cpld_proc_install(); -} - -static int easy98000_addon_remove(struct platform_device *pdev) -{ -#if defined(CONFIG_PROC_FS) - char buf[64]; - int i; - - for (i = 0; i < sizeof(proc_entries) / sizeof(proc_entries[0]); i++) { - sprintf(buf, "cpld/%s", proc_entries[i].name); - remove_proc_entry(buf, 0); - } - remove_proc_entry("cpld", 0); -#endif - return 0; -} - -static struct platform_driver easy98000_addon_driver = { - .probe = easy98000_addon_probe, - .remove = __devexit_p(easy98000_addon_remove), - .driver = { - .name = "easy98000_addon", - .owner = THIS_MODULE, - }, -}; - -int __init easy98000_addon_init(void) -{ - return platform_driver_register(&easy98000_addon_driver); -} - -void __exit easy98000_addon_exit(void) -{ - platform_driver_unregister(&easy98000_addon_driver); -} - -module_init(easy98000_addon_init); -module_exit(easy98000_addon_exit); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c deleted file mode 100644 index 94622cfda8..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * EASY98000 CPLD LED driver - * - * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - */ - -#include <linux/kernel.h> -#include <linux/version.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/module.h> -#include <linux/errno.h> -#include <linux/leds.h> -#include <linux/slab.h> - -#include "dev-leds-easy98000-cpld.h" - -const char *led_name[8] = { - "ge0_act", - "ge0_link", - "ge1_act", - "ge1_link", - "fe2_act", - "fe2_link", - "fe3_act", - "fe3_link" -}; - -#define cpld_base7 ((u16 *)(KSEG1 | 0x17c0000c)) -#define cpld_base8 ((u16 *)(KSEG1 | 0x17c00012)) - -#define ltq_r16(reg) __raw_readw(reg) -#define ltq_w16(val, reg) __raw_writew(val, reg) - -struct cpld_led_dev { - struct led_classdev cdev; - u8 mask; - u16 *base; -}; - -struct cpld_led_drvdata { - struct cpld_led_dev *led_devs; - int num_leds; -}; - -void led_set(u8 mask, u16 *base) -{ - ltq_w16(ltq_r16(base) | mask, base); -} - -void led_clear(u8 mask, u16 *base) -{ - ltq_w16(ltq_r16(base) & (~mask), base); -} - -void led_blink_clear(u8 mask, u16 *base) -{ - led_clear(mask, base); -} - -static void led_brightness(struct led_classdev *led_cdev, - enum led_brightness value) -{ - struct cpld_led_dev *led_dev = - container_of(led_cdev, struct cpld_led_dev, cdev); - - if (value) - led_set(led_dev->mask, led_dev->base); - else - led_clear(led_dev->mask, led_dev->base); -} - -static int led_probe(struct platform_device *pdev) -{ - int i; - char name[32]; - struct cpld_led_drvdata *drvdata; - int ret = 0; - - drvdata = kzalloc(sizeof(struct cpld_led_drvdata) + - sizeof(struct cpld_led_dev) * MAX_LED, - GFP_KERNEL); - if (!drvdata) - return -ENOMEM; - - drvdata->led_devs = (struct cpld_led_dev *) &drvdata[1]; - - for (i = 0; i < MAX_LED; i++) { - struct cpld_led_dev *led_dev = &drvdata->led_devs[i]; - led_dev->cdev.brightness_set = led_brightness; - led_dev->cdev.default_trigger = NULL; - led_dev->mask = 1 << (i % 8); - if(i < 8) { - sprintf(name, "easy98000-cpld:%s", led_name[i]); - led_dev->base = cpld_base8; - } else { - sprintf(name, "easy98000-cpld:red:%d", i-8); - led_dev->base = cpld_base7; - } - led_dev->cdev.name = name; - ret = led_classdev_register(&pdev->dev, &led_dev->cdev); - if (ret) - goto err; - } - platform_set_drvdata(pdev, drvdata); - return 0; - -err: - printk("led_probe: 3\n"); - for (i = i - 1; i >= 0; i--) - led_classdev_unregister(&drvdata->led_devs[i].cdev); - - kfree(drvdata); - return ret; -} - -static int led_remove(struct platform_device *pdev) -{ - int i; - struct cpld_led_drvdata *drvdata = platform_get_drvdata(pdev); - for (i = 0; i < MAX_LED; i++) - led_classdev_unregister(&drvdata->led_devs[i].cdev); - kfree(drvdata); - return 0; -} - -static struct platform_driver led_driver = { - .probe = led_probe, - .remove = __devexit_p(led_remove), - .driver = { - .name = LED_NAME, - .owner = THIS_MODULE, - }, -}; - -int __init easy98000_cpld_led_init(void) -{ - pr_info(LED_DESC ", Version " LED_VERSION - " (c) Copyright 2011, Lantiq Deutschland GmbH\n"); - return platform_driver_register(&led_driver); -} - -void __exit easy98000_cpld_led_exit(void) -{ - platform_driver_unregister(&led_driver); -} - -module_init(easy98000_cpld_led_init); -module_exit(easy98000_cpld_led_exit); - -MODULE_DESCRIPTION(LED_NAME); -MODULE_DESCRIPTION(LED_DESC); -MODULE_AUTHOR("Ralph Hempel <ralph.hempel@lantiq.com>"); -MODULE_LICENSE("GPL v2"); - diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h b/target/linux/lantiq/files/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h deleted file mode 100644 index 3160189fe9..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * EASY98000 CPLD LED driver - * - * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - */ -#ifndef _INCLUDE_EASY98000_CPLD_LED_H_ -#define _INCLUDE_EASY98000_CPLD_LED_H_ - -#define LED_NAME "easy98000_cpld_led" -#define LED_DESC "EASY98000 LED driver" -#define LED_VERSION "1.0.0" - -#define MAX_LED 16 - -#endif /* _INCLUDE_EASY98000_CPLD_LED_H_ */ diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.c deleted file mode 100644 index e684ed470f..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - */ - -#include <linux/platform_device.h> -#include <linux/mtd/nand.h> -#include <linux/gpio.h> - -#include <lantiq_soc.h> - -#include "devices.h" - -/* nand flash */ -/* address lines used for NAND control signals */ -#define NAND_ADDR_ALE 0x10000 -#define NAND_ADDR_CLE 0x20000 -/* Ready/Busy Status */ -#define MODCON_STS 0x0002 -/* Ready/Busy Status Edge */ -#define MODCON_STSEDGE 0x0004 - -static const char *part_probes[] = { "cmdlinepart", NULL }; - -static int -falcon_nand_ready(struct mtd_info *mtd) -{ - u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON); - - return (((modcon & (MODCON_STS | MODCON_STSEDGE)) == - (MODCON_STS | MODCON_STSEDGE))); -} - -static void -falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE); - - if (ctrl & NAND_CLE) - nandaddr |= NAND_ADDR_CLE; - if (ctrl & NAND_ALE) - nandaddr |= NAND_ADDR_ALE; - - this->IO_ADDR_W = (void __iomem *) nandaddr; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static struct platform_nand_data falcon_flash_nand_data = { - .chip = { - .nr_chips = 1, - .chip_delay = 25, - .part_probe_types = part_probes, - }, - .ctrl = { - .cmd_ctrl = falcon_hwcontrol, - .dev_ready = falcon_nand_ready, - } -}; - -static struct resource ltq_nand_res = - MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX); - -static struct platform_device ltq_flash_nand = { - .name = "gen_nand", - .id = -1, - .num_resources = 1, - .resource = <q_nand_res, - .dev = { - .platform_data = &falcon_flash_nand_data, - }, -}; - -void __init -falcon_register_nand(void) -{ - platform_device_register(<q_flash_nand); -} - -/* gpio */ -#define DECLARE_GPIO_RES(port) \ -static struct resource falcon_gpio ## port ## _res[] = { \ - MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \ - LTQ_GPIO ## port ## _SIZE), \ - MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \ - LTQ_PADCTRL ## port ## _SIZE), \ - IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \ -} -DECLARE_GPIO_RES(0); -DECLARE_GPIO_RES(1); -DECLARE_GPIO_RES(2); -DECLARE_GPIO_RES(3); -DECLARE_GPIO_RES(4); - -void __init -falcon_register_gpio(void) -{ - platform_device_register_simple("falcon_gpio", 0, - falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res)); - platform_device_register_simple("falcon_gpio", 1, - falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res)); - platform_device_register_simple("falcon_gpio", 2, - falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res)); -} - -void __init -falcon_register_gpio_extra(void) -{ - platform_device_register_simple("falcon_gpio", 3, - falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res)); - platform_device_register_simple("falcon_gpio", 4, - falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); -} - -/* spi flash */ -static struct platform_device ltq_spi = { - .name = "falcon_spi", - .num_resources = 0, -}; - -void __init -falcon_register_spi_flash(struct spi_board_info *data) -{ - spi_register_board_info(data, 1); - platform_device_register(<q_spi); -} - -/* i2c */ -static struct resource falcon_i2c_resources[] = { - MEM_RES("i2c", GPON_I2C_BASE, GPON_I2C_SIZE), - IRQ_RES(i2c_lb, FALCON_IRQ_I2C_LBREQ), - IRQ_RES(i2c_b, FALCON_IRQ_I2C_BREQ), - IRQ_RES(i2c_err, FALCON_IRQ_I2C_I2C_ERR), - IRQ_RES(i2c_p, FALCON_IRQ_I2C_I2C_P), -}; - -void __init -falcon_register_i2c(void) -{ - platform_device_register_simple("i2c-falcon", 0, - falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources)); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.h b/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.h deleted file mode 100644 index d81edbe74e..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - */ - -#ifndef _FALCON_DEVICES_H__ -#define _FALCON_DEVICES_H__ - -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> - -#include "../devices.h" - -extern void falcon_register_nand(void); -extern void falcon_register_gpio(void); -extern void falcon_register_gpio_extra(void); -extern void falcon_register_spi_flash(struct spi_board_info *data); -extern void falcon_register_i2c(void); - -#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/gpio.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/gpio.c deleted file mode 100644 index 4147d61c7d..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/gpio.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - */ - -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/slab.h> -#include <linux/export.h> -#include <linux/err.h> -#include <linux/platform_device.h> - -#include <lantiq_soc.h> - -/* Multiplexer Control Register */ -#define LTQ_PADC_MUX(x) (x * 0x4) -/* Pad Control Availability Register */ -#define LTQ_PADC_AVAIL 0x000000F0 - -/* Data Output Register */ -#define LTQ_GPIO_OUT 0x00000000 -/* Data Input Register */ -#define LTQ_GPIO_IN 0x00000004 -/* Direction Register */ -#define LTQ_GPIO_DIR 0x00000008 -/* External Interrupt Control Register 0 */ -#define LTQ_GPIO_EXINTCR0 0x00000018 -/* External Interrupt Control Register 1 */ -#define LTQ_GPIO_EXINTCR1 0x0000001C -/* IRN Capture Register */ -#define LTQ_GPIO_IRNCR 0x00000020 -/* IRN Interrupt Configuration Register */ -#define LTQ_GPIO_IRNCFG 0x0000002C -/* IRN Interrupt Enable Set Register */ -#define LTQ_GPIO_IRNRNSET 0x00000030 -/* IRN Interrupt Enable Clear Register */ -#define LTQ_GPIO_IRNENCLR 0x00000034 -/* Output Set Register */ -#define LTQ_GPIO_OUTSET 0x00000040 -/* Output Cler Register */ -#define LTQ_GPIO_OUTCLR 0x00000044 -/* Direction Clear Register */ -#define LTQ_GPIO_DIRSET 0x00000048 -/* Direction Set Register */ -#define LTQ_GPIO_DIRCLR 0x0000004C - -/* turn a gpio_chip into a falcon_gpio_port */ -#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip) -/* turn a irq_data into a falcon_gpio_port */ -#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq)) - -#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg) -#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg) -#define ltq_pad_w32_mask(c, clear, set, reg) \ - ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg) - -#define ltq_port_r32(p, reg) ltq_r32(p->port + reg) -#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg) -#define ltq_port_w32_mask(p, clear, set, reg) \ - ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg) - -#define MAX_PORTS 5 -#define PINS_PER_PORT 32 - -struct falcon_gpio_port { - struct gpio_chip gpio_chip; - void __iomem *pad; - void __iomem *port; - unsigned int irq_base; - unsigned int chained_irq; - struct clk *clk; -}; - -static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS]; - -int gpio_to_irq(unsigned int gpio) -{ - return __gpio_to_irq(gpio); -} -EXPORT_SYMBOL(gpio_to_irq); - -int ltq_gpio_mux_set(unsigned int pin, unsigned int mux) -{ - int port = pin / 100; - int offset = pin % 100; - struct falcon_gpio_port *gpio_port; - - if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS)) - return -EINVAL; - - gpio_port = <q_gpio_port[port]; - ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset)); - - return 0; -} -EXPORT_SYMBOL(ltq_gpio_mux_set); - -int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, - unsigned int dir, const char *name) -{ - int port = pin / 100; - int offset = pin % 100; - - if (offset >= PINS_PER_PORT || port >= MAX_PORTS) - return -EINVAL; - - if (devm_gpio_request(dev, pin, name)) { - pr_err("failed to setup lantiq gpio: %s\n", name); - return -EBUSY; - } - - if (dir) - gpio_direction_output(pin, 1); - else - gpio_direction_input(pin); - - return ltq_gpio_mux_set(pin, mux); -} -EXPORT_SYMBOL(ltq_gpio_request); - -static int -falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) -{ - ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR); - - return 0; -} - -static void -falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) -{ - if (value) - ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET); - else - ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR); -} - -static int -falcon_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - falcon_gpio_set(chip, offset, value); - ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET); - - return 0; -} - -static int -falcon_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1) - return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1; - else - return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1; -} - -static int -falcon_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { - if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) - return -EBUSY; - /* switch on gpio function */ - ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset)); - return 0; - } - - return -ENODEV; -} - -static void -falcon_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { - if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) - return; - /* switch off gpio function */ - ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset)); - } -} - -static int -falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - return ctop(chip)->irq_base + offset; -} - -static void -falcon_gpio_disable_irq(struct irq_data *d) -{ - unsigned int offset = d->irq - itop(d)->irq_base; - - ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); -} - -static void -falcon_gpio_enable_irq(struct irq_data *d) -{ - unsigned int offset = d->irq - itop(d)->irq_base; - - if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1) - /* switch on gpio function */ - ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset)); - - ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET); -} - -static void -falcon_gpio_ack_irq(struct irq_data *d) -{ - unsigned int offset = d->irq - itop(d)->irq_base; - - ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); -} - -static void -falcon_gpio_mask_and_ack_irq(struct irq_data *d) -{ - unsigned int offset = d->irq - itop(d)->irq_base; - - ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); - ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); -} - -static struct irq_chip falcon_gpio_irq_chip; -static int -falcon_gpio_irq_type(struct irq_data *d, unsigned int type) -{ - unsigned int offset = d->irq - itop(d)->irq_base; - unsigned int mask = 1 << offset; - - if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE) - return 0; - - if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) { - /* level triggered */ - ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG); - irq_set_chip_and_handler_name(d->irq, - &falcon_gpio_irq_chip, handle_level_irq, "mux"); - } else { - /* edge triggered */ - ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG); - irq_set_chip_and_handler_name(d->irq, - &falcon_gpio_irq_chip, handle_simple_irq, "mux"); - } - - if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { - ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); - ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1); - } else { - if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0) - /* positive logic: rising edge, high level */ - ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); - else - /* negative logic: falling edge, low level */ - ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0); - ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1); - } - - return gpio_direction_input(itop(d)->gpio_chip.base + offset); -} - -static void -falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc); - unsigned long irncr; - int offset; - - /* acknowledge interrupt */ - irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR); - ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR); - - desc->irq_data.chip->irq_ack(&desc->irq_data); - - for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio) - generic_handle_irq(gpio_port->irq_base + offset); -} - -static struct irq_chip falcon_gpio_irq_chip = { - .name = "gpio_irq_mux", - .irq_mask = falcon_gpio_disable_irq, - .irq_unmask = falcon_gpio_enable_irq, - .irq_ack = falcon_gpio_ack_irq, - .irq_mask_ack = falcon_gpio_mask_and_ack_irq, - .irq_set_type = falcon_gpio_irq_type, -}; - -static struct irqaction gpio_cascade = { - .handler = no_action, - .flags = IRQF_DISABLED, - .name = "gpio_cascade", -}; - -static int -falcon_gpio_probe(struct platform_device *pdev) -{ - struct falcon_gpio_port *gpio_port; - int ret, i; - struct resource *gpiores, *padres; - int irq; - - if (pdev->id >= MAX_PORTS) - return -ENODEV; - - gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0); - padres = platform_get_resource(pdev, IORESOURCE_MEM, 1); - irq = platform_get_irq(pdev, 0); - if (!gpiores || !padres) - return -ENODEV; - - gpio_port = <q_gpio_port[pdev->id]; - gpio_port->gpio_chip.label = "falcon-gpio"; - gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input; - gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output; - gpio_port->gpio_chip.get = falcon_gpio_get; - gpio_port->gpio_chip.set = falcon_gpio_set; - gpio_port->gpio_chip.request = falcon_gpio_request; - gpio_port->gpio_chip.free = falcon_gpio_free; - gpio_port->gpio_chip.base = 100 * pdev->id; - gpio_port->gpio_chip.ngpio = 32; - gpio_port->gpio_chip.dev = &pdev->dev; - - gpio_port->port = ltq_remap_resource(gpiores); - gpio_port->pad = ltq_remap_resource(padres); - - if (!gpio_port->port || !gpio_port->pad) { - dev_err(&pdev->dev, "Could not map io ranges\n"); - ret = -ENOMEM; - goto err; - } - - gpio_port->clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(gpio_port->clk)) { - dev_err(&pdev->dev, "Could not get clock\n"); - ret = PTR_ERR(gpio_port->clk);; - goto err; - } - clk_enable(gpio_port->clk); - - if (irq > 0) { - /* irq_chip support */ - gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq; - gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id); - - for (i = 0; i < 32; i++) { - irq_set_chip_and_handler_name(gpio_port->irq_base + i, - &falcon_gpio_irq_chip, handle_simple_irq, - "mux"); - irq_set_chip_data(gpio_port->irq_base + i, gpio_port); - /* set to negative logic (falling edge, low level) */ - ltq_port_w32_mask(gpio_port, 0, 1 << i, - LTQ_GPIO_EXINTCR0); - } - - gpio_port->chained_irq = irq; - setup_irq(irq, &gpio_cascade); - irq_set_handler_data(irq, gpio_port); - irq_set_chained_handler(irq, falcon_gpio_irq_handler); - } - - ret = gpiochip_add(&gpio_port->gpio_chip); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", - pdev->id, ret); - goto err; - } - platform_set_drvdata(pdev, gpio_port); - return ret; - -err: - dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret); - if (gpiores) - release_resource(gpiores); - if (padres) - release_resource(padres); - - if (gpio_port->port) - iounmap(gpio_port->port); - if (gpio_port->pad) - iounmap(gpio_port->pad); - return ret; -} - -static struct platform_driver falcon_gpio_driver = { - .probe = falcon_gpio_probe, - .driver = { - .name = "falcon_gpio", - .owner = THIS_MODULE, - }, -}; - -int __init -falcon_gpio_init(void) -{ - int ret; - - pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n"); - ret = platform_driver_register(&falcon_gpio_driver); - if (ret) - pr_err("falcon_gpio: Error registering platform driver!"); - return ret; -} - -postcore_initcall(falcon_gpio_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-95C3AM1.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-95C3AM1.c deleted file mode 100644 index 42a3344ae9..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-95C3AM1.c +++ /dev/null @@ -1,94 +0,0 @@ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c-gpio.h> - -#include <dev-gpio-leds.h> - -#include "../machtypes.h" -#include "devices.h" - -#define BOARD_95C3AM1_GPIO_LED_0 10 -#define BOARD_95C3AM1_GPIO_LED_1 11 -#define BOARD_95C3AM1_GPIO_LED_2 12 -#define BOARD_95C3AM1_GPIO_LED_3 13 - -static struct mtd_partition board_95C3AM1_partitions[] = -{ - { - .name = "uboot", - .offset = 0x0, - .size = 0x40000, - }, - { - .name = "uboot_env", - .offset = 0x40000, - .size = 0x40000, /* 2 sectors for redundant env. */ - }, - { - .name = "linux", - .offset = 0x80000, - .size = 0xF80000, /* map only 16 MiB */ - }, -}; - -static struct flash_platform_data board_95C3AM1_flash_platform_data = { - .name = "sflash", - .parts = board_95C3AM1_partitions, - .nr_parts = ARRAY_SIZE(board_95C3AM1_partitions) -}; - -static struct spi_board_info board_95C3AM1_flash_data __initdata = { - .modalias = "m25p80", - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 10 * 1000 * 1000, - .mode = SPI_MODE_3, - .platform_data = &board_95C3AM1_flash_platform_data -}; - -static struct gpio_led board_95C3AM1_gpio_leds[] __initdata = { - { - .name = "power", - .gpio = BOARD_95C3AM1_GPIO_LED_0, - .active_low = 0, - }, { - .name = "optical", - .gpio = BOARD_95C3AM1_GPIO_LED_1, - .active_low = 0, - }, { - .name = "lan", - .gpio = BOARD_95C3AM1_GPIO_LED_2, - .active_low = 0, - }, { - .name = "update", - .gpio = BOARD_95C3AM1_GPIO_LED_3, - .active_low = 0, - } -}; - -static struct i2c_gpio_platform_data board_95C3AM1_i2c_gpio_data = { - .sda_pin = 107, - .scl_pin = 108, -}; - -static struct platform_device board_95C3AM1_i2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev = { - .platform_data = &board_95C3AM1_i2c_gpio_data, - } -}; - -static void __init board_95C3AM1_init(void) -{ - falcon_register_i2c(); - falcon_register_spi_flash(&board_95C3AM1_flash_data); - platform_device_register(&board_95C3AM1_i2c_gpio_device); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(board_95C3AM1_gpio_leds), - board_95C3AM1_gpio_leds); -} - -MIPS_MACHINE(LANTIQ_MACH_95C3AM1, - "95C3AM1", - "95C3AM1 Board", - board_95C3AM1_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98000.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98000.c deleted file mode 100644 index fc5720d4ea..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98000.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - */ - -#include <linux/platform_device.h> -#include <linux/mtd/partitions.h> -#include <linux/spi/spi.h> -#include <linux/spi/spi_gpio.h> -#include <linux/spi/eeprom.h> - -#include "../machtypes.h" - -#include "devices.h" - -static struct mtd_partition easy98000_nor_partitions[] = { - { - .name = "uboot", - .offset = 0x0, - .size = 0x40000, - }, - { - .name = "uboot_env", - .offset = 0x40000, - .size = 0x40000, /* 2 sectors for redundant env. */ - }, - { - .name = "linux", - .offset = 0x80000, - .size = 0xF80000, /* map only 16 MiB */ - }, -}; - -struct physmap_flash_data easy98000_nor_flash_data = { - .nr_parts = ARRAY_SIZE(easy98000_nor_partitions), - .parts = easy98000_nor_partitions, -}; - -static struct flash_platform_data easy98000_spi_flash_platform_data = { - .name = "sflash", - .parts = easy98000_nor_partitions, - .nr_parts = ARRAY_SIZE(easy98000_nor_partitions) -}; - -static struct spi_board_info easy98000_spi_flash_data __initdata = { - .modalias = "m25p80", - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 10 * 1000 * 1000, - .mode = SPI_MODE_3, - .platform_data = &easy98000_spi_flash_platform_data -}; - -/* setup gpio based spi bus/device for access to the eeprom on the board */ -#define SPI_GPIO_MRST 102 -#define SPI_GPIO_MTSR 103 -#define SPI_GPIO_CLK 104 -#define SPI_GPIO_CS0 105 -#define SPI_GPIO_CS1 106 -#define SPI_GPIO_BUS_NUM 1 - -static struct spi_gpio_platform_data easy98000_spi_gpio_data = { - .sck = SPI_GPIO_CLK, - .mosi = SPI_GPIO_MTSR, - .miso = SPI_GPIO_MRST, - .num_chipselect = 2, -}; - -static struct platform_device easy98000_spi_gpio_device = { - .name = "spi_gpio", - .id = SPI_GPIO_BUS_NUM, - .dev.platform_data = &easy98000_spi_gpio_data, -}; - -static struct spi_eeprom at25160n = { - .byte_len = 16 * 1024 / 8, - .name = "at25160n", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static struct spi_board_info easy98000_spi_gpio_devices __initdata = { - .modalias = "at25", - .bus_num = SPI_GPIO_BUS_NUM, - .max_speed_hz = 1000 * 1000, - .mode = SPI_MODE_3, - .chip_select = 1, - .controller_data = (void *) SPI_GPIO_CS1, - .platform_data = &at25160n, -}; - -static void __init -easy98000_init_common(void) -{ - spi_register_board_info(&easy98000_spi_gpio_devices, 1); - platform_device_register(&easy98000_spi_gpio_device); - falcon_register_i2c(); -} - -static void __init -easy98000_init(void) -{ - easy98000_init_common(); - ltq_register_nor(&easy98000_nor_flash_data); -} - -static void __init -easy98000sf_init(void) -{ - easy98000_init_common(); - falcon_register_spi_flash(&easy98000_spi_flash_data); -} - -static void __init -easy98000nand_init(void) -{ - easy98000_init_common(); - falcon_register_nand(); -} - -MIPS_MACHINE(LANTIQ_MACH_EASY98000, - "EASY98000", - "EASY98000 Eval Board", - easy98000_init); - -MIPS_MACHINE(LANTIQ_MACH_EASY98000SF, - "EASY98000SF", - "EASY98000 Eval Board (Serial Flash)", - easy98000sf_init); - -MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND, - "EASY98000NAND", - "EASY98000 Eval Board (NAND Flash)", - easy98000nand_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98020.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98020.c deleted file mode 100644 index 4cdfc199db..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98020.c +++ /dev/null @@ -1,118 +0,0 @@ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/gpio_buttons.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/input.h> -#include <linux/interrupt.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> - -#include <dev-gpio-leds.h> - -#include "../machtypes.h" -#include "devices.h" - -#define EASY98020_GPIO_LED_0 9 -#define EASY98020_GPIO_LED_1 10 -#define EASY98020_GPIO_LED_2 11 -#define EASY98020_GPIO_LED_3 12 -#define EASY98020_GPIO_LED_GE0_ACT 110 -#define EASY98020_GPIO_LED_GE0_LINK 109 -#define EASY98020_GPIO_LED_GE1_ACT 106 -#define EASY98020_GPIO_LED_GE1_LINK 105 - -static struct mtd_partition easy98020_spi_partitions[] = -{ - { - .name = "uboot", - .offset = 0x0, - .size = 0x40000, - }, - { - .name = "uboot_env", - .offset = 0x40000, - .size = 0x40000, /* 2 sectors for redundant env. */ - }, - { - .name = "linux", - .offset = 0x80000, - .size = 0xF80000, /* map only 16 MiB */ - }, -}; - -static struct flash_platform_data easy98020_spi_flash_platform_data = { - .name = "sflash", - .parts = easy98020_spi_partitions, - .nr_parts = ARRAY_SIZE(easy98020_spi_partitions) -}; - -static struct spi_board_info easy98020_spi_flash_data __initdata = { - .modalias = "m25p80", - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 10 * 1000 * 1000, - .mode = SPI_MODE_3, - .platform_data = &easy98020_spi_flash_platform_data -}; - -static struct gpio_led easy98020_gpio_leds[] __initdata = { - { - .name = "easy98020:green:0", - .gpio = EASY98020_GPIO_LED_0, - .active_low = 0, - }, { - .name = "easy98020:green:1", - .gpio = EASY98020_GPIO_LED_1, - .active_low = 0, - }, { - .name = "easy98020:green:2", - .gpio = EASY98020_GPIO_LED_2, - .active_low = 0, - }, { - .name = "easy98020:green:3", - .gpio = EASY98020_GPIO_LED_3, - .active_low = 0, - }, { - .name = "easy98020:ge0_act", - .gpio = EASY98020_GPIO_LED_GE0_ACT, - .active_low = 0, - }, { - .name = "easy98020:ge0_link", - .gpio = EASY98020_GPIO_LED_GE0_LINK, - .active_low = 0, - }, { - .name = "easy98020:ge1_act", - .gpio = EASY98020_GPIO_LED_GE1_ACT, - .active_low = 0, - }, { - .name = "easy98020:ge1_link", - .gpio = EASY98020_GPIO_LED_GE1_LINK, - .active_low = 0, - } -}; - -static void __init easy98020_init(void) -{ - falcon_register_i2c(); - falcon_register_spi_flash(&easy98020_spi_flash_data); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(easy98020_gpio_leds), - easy98020_gpio_leds); -} - -MIPS_MACHINE(LANTIQ_MACH_EASY98020, - "EASY98020", - "EASY98020 Eval Board", - easy98020_init); - -MIPS_MACHINE(LANTIQ_MACH_EASY98020_1LAN, - "EASY98020_1LAN", - "EASY98020 Eval Board (1 LAN port)", - easy98020_init); - -MIPS_MACHINE(LANTIQ_MACH_EASY98020_2LAN, - "EASY98020_2LAN", - "EASY98020 Eval Board (2 LAN ports)", - easy98020_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/prom.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/prom.c deleted file mode 100644 index 2a4eea1782..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/prom.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - */ - -#include <lantiq_soc.h> - -#include "devices.h" - -#include "../prom.h" - -#define SOC_FALCON "Falcon" -#define SOC_FALCON_D "Falcon-D" -#define SOC_FALCON_V "Falcon-V" -#define SOC_FALCON_M "Falcon-M" - -#define PART_SHIFT 12 -#define PART_MASK 0x0FFFF000 -#define REV_SHIFT 28 -#define REV_MASK 0xF0000000 -#define SREV_SHIFT 22 -#define SREV_MASK 0x03C00000 -#define TYPE_SHIFT 26 -#define TYPE_MASK 0x3C000000 - -/* this parameter allows us enable/disable asc1 via commandline */ -static int register_asc1; -static int __init -ltq_parse_asc1(char *p) -{ - register_asc1 = 1; - return 0; -} -__setup("use_asc1", ltq_parse_asc1); - -void __init -ltq_soc_setup(void) -{ - ltq_register_asc(0); - ltq_register_wdt(); - falcon_register_gpio(); - if (register_asc1) - ltq_register_asc(1); -} - -void __init -ltq_soc_detect(struct ltq_soc_info *i) -{ - u32 type; - i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; - i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; - i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT); - sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), - i->rev & 0x7, (i->srev & 0x3) + 1); - - switch (i->partnum) { - case SOC_ID_FALCON: - type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT; - switch (type) { - case 0: - i->name = SOC_FALCON_D; - break; - case 1: - i->name = SOC_FALCON_V; - break; - case 2: - i->name = SOC_FALCON_M; - break; - default: - i->name = SOC_FALCON; - break; - } - i->type = SOC_TYPE_FALCON; - break; - - default: - unreachable(); - break; - } -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/reset.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/reset.c deleted file mode 100644 index cbcadc5c48..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/reset.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/pm.h> -#include <asm/reboot.h> -#include <linux/export.h> - -#include <lantiq_soc.h> - -/* CPU0 Reset Source Register */ -#define LTQ_SYS1_CPU0RS 0x0040 -/* reset cause mask */ -#define LTQ_CPU0RS_MASK 0x0003 - -int -ltq_reset_cause(void) -{ - return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK; -} -EXPORT_SYMBOL_GPL(ltq_reset_cause); - -#define BOOT_REG_BASE (KSEG1 | 0x1F200000) -#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20) -#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24) -#define BOOT_PW1 0x4C545100 -#define BOOT_PW2 0x0051544C - -#define WDT_REG_BASE (KSEG1 | 0x1F8803F0) -#define WDT_PW1 0x00BE0000 -#define WDT_PW2 0x00DC0000 - -static void -ltq_machine_restart(char *command) -{ - pr_notice("System restart\n"); - local_irq_disable(); - - /* reboot magic */ - ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ - ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ - ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ - - /* watchdog magic */ - ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); - ltq_w32(WDT_PW2 | - (0x3 << 26) | /* PWL */ - (0x2 << 24) | /* CLKDIV */ - (0x1 << 31) | /* enable */ - (1), /* reload */ - (void *)WDT_REG_BASE); - unreachable(); -} - -static void -ltq_machine_halt(void) -{ - pr_notice("System halted.\n"); - local_irq_disable(); - unreachable(); -} - -static void -ltq_machine_power_off(void) -{ - pr_notice("Please turn off the power now.\n"); - local_irq_disable(); - unreachable(); -} - -static int __init -mips_reboot_setup(void) -{ - _machine_restart = ltq_machine_restart; - _machine_halt = ltq_machine_halt; - pm_power_off = ltq_machine_power_off; - return 0; -} - -arch_initcall(mips_reboot_setup); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/sysctrl.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/sysctrl.c deleted file mode 100644 index f27d694826..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/falcon/sysctrl.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - */ - -#include <linux/ioport.h> -#include <linux/export.h> -#include <linux/clkdev.h> -#include <asm/delay.h> - -#include <lantiq_soc.h> - -#include "devices.h" -#include "../clk.h" - -/* infrastructure control register */ -#define SYS1_INFRAC 0x00bc -/* Configuration fuses for drivers and pll */ -#define STATUS_CONFIG 0x0040 - -/* GPE frequency selection */ -#define GPPC_OFFSET 24 -#define GPEFREQ_MASK 0x00000C0 -#define GPEFREQ_OFFSET 10 -/* Clock status register */ -#define LTQ_SYSCTL_CLKS 0x0000 -/* Clock enable register */ -#define LTQ_SYSCTL_CLKEN 0x0004 -/* Clock clear register */ -#define LTQ_SYSCTL_CLKCLR 0x0008 -/* Activation Status Register */ -#define LTQ_SYSCTL_ACTS 0x0020 -/* Activation Register */ -#define LTQ_SYSCTL_ACT 0x0024 -/* Deactivation Register */ -#define LTQ_SYSCTL_DEACT 0x0028 -/* reboot Register */ -#define LTQ_SYSCTL_RBT 0x002c -/* CPU0 Clock Control Register */ -#define LTQ_SYS1_CPU0CC 0x0040 -/* clock divider bit */ -#define LTQ_CPU0CC_CPUDIV 0x0001 - -static struct resource ltq_sysctl_res[] = { - MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), - MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE), - MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE), -}; - -static struct resource ltq_status_res = - MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE); -static struct resource ltq_ebu_res = - MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); - -static void __iomem *ltq_sysctl[3]; -static void __iomem *ltq_status_membase; -void __iomem *ltq_sys1_membase; -void __iomem *ltq_ebu_membase; - -#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y)) -#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x)) -#define ltq_reg_w32_mask(m, clear, set, reg) \ - ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg) - -#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y)) -#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) - -static inline void -ltq_sysctl_wait(struct clk *clk, - unsigned int test, unsigned int reg) -{ - int err = 1000000; - - do {} while (--err && ((ltq_reg_r32(clk->module, reg) - & clk->bits) != test)); - if (!err) - pr_err("module de/activation failed %d %08X %08X %08X\n", - clk->module, clk->bits, test, - ltq_reg_r32(clk->module, reg) & clk->bits); -} - -static int -ltq_sysctl_activate(struct clk *clk) -{ - ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); - ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT); - ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); - return 0; -} - -static void -ltq_sysctl_deactivate(struct clk *clk) -{ - ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); - ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT); - ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS); -} - -static int -ltq_sysctl_clken(struct clk *clk) -{ - ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); - ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS); - return 0; -} - -static void -ltq_sysctl_clkdis(struct clk *clk) -{ - ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); - ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS); -} - -static void -ltq_sysctl_reboot(struct clk *clk) -{ - unsigned int act; - unsigned int bits; - - act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT); - bits = ~act & clk->bits; - if (bits != 0) { - ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN); - ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT); - ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS); - } - ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT); - ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); -} - -/* enable the ONU core */ -static void -ltq_gpe_enable(void) -{ - unsigned int freq; - unsigned int status; - - /* if if the clock is already enabled */ - status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC); - if (status & (1 << (GPPC_OFFSET + 1))) - return; - - if (ltq_status_r32(STATUS_CONFIG) == 0) - freq = 1; /* use 625MHz on unfused chip */ - else - freq = (ltq_status_r32(STATUS_CONFIG) & - GPEFREQ_MASK) >> - GPEFREQ_OFFSET; - - /* apply new frequency */ - ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), - freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); - udelay(1); - - /* enable new frequency */ - ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); - udelay(1); -} - -static inline void -clkdev_add_sys(const char *dev, unsigned int module, - unsigned int bits) -{ - struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); - - clk->cl.dev_id = dev; - clk->cl.con_id = NULL; - clk->cl.clk = clk; - clk->module = module; - clk->bits = bits; - clk->activate = ltq_sysctl_activate; - clk->deactivate = ltq_sysctl_deactivate; - clk->enable = ltq_sysctl_clken; - clk->disable = ltq_sysctl_clkdis; - clk->reboot = ltq_sysctl_reboot; - clkdev_add(&clk->cl); -} - -void __init -ltq_soc_init(void) -{ - int i; - - for (i = 0; i < 3; i++) - ltq_sysctl[i] = ltq_remap_resource(<q_sysctl_res[i]); - - ltq_sys1_membase = ltq_sysctl[0]; - ltq_status_membase = ltq_remap_resource(<q_status_res); - ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); - - ltq_gpe_enable(); - - /* get our 3 static rates for cpu, fpi and io clocks */ - if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) - clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M); - else - clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M); - - /* add our clock domains */ - clkdev_add_sys("falcon_gpio.0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0); - clkdev_add_sys("falcon_gpio.1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); - clkdev_add_sys("falcon_gpio.2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2); - clkdev_add_sys("falcon_gpio.3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3); - clkdev_add_sys("falcon_gpio.4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4); - clkdev_add_sys("ltq_asc.1", SYSCTL_SYS1, ACTS_ASC1_ACT); - clkdev_add_sys("i2c-falcon.0", SYSCTL_SYS1, ACTS_I2C_ACT); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/Kconfig b/target/linux/lantiq/files/arch/mips/lantiq/svip/Kconfig deleted file mode 100644 index f351a189a7..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if SOC_SVIP - -menu "Mips Machine" - -config LANTIQ_MACH_EASY33016 - bool "Easy33016" - default y - -config LANTIQ_MACH_EASY336 - select SYS_SUPPORTS_LITTLE_ENDIAN - bool "Easy336" - default y - -endmenu - -endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/Makefile b/target/linux/lantiq/files/arch/mips/lantiq/svip/Makefile deleted file mode 100644 index 405d652191..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y := devices.o prom.o reset.o clk-svip.o gpio.o dma.o switchip_setup.o pms.o mux.o -obj-$(CONFIG_LANTIQ_MACH_EASY33016) += mach-easy33016.o -obj-$(CONFIG_LANTIQ_MACH_EASY336) += mach-easy336.o diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/clk-svip.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/clk-svip.c deleted file mode 100644 index 4a14df509f..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/clk-svip.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/io.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/time.h> - -#include <asm/irq.h> -#include <asm/div64.h> - -#include <lantiq_soc.h> -#include <base_reg.h> -#include <sys0_reg.h> -#include <sys1_reg.h> -#include <status_reg.h> - -static struct svip_reg_status *const status = -(struct svip_reg_status *)LTQ_STATUS_BASE; -static struct svip_reg_sys0 *const sys0 = (struct svip_reg_sys0 *)LTQ_SYS0_BASE; -static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; - -unsigned int ltq_svip_io_region_clock(void) -{ - return 200000000; /* 200 MHz */ -} -EXPORT_SYMBOL(ltq_svip_io_region_clock); - -unsigned int ltq_svip_cpu_hz(void) -{ - /* Magic BootROM speed location... */ - if ((*(u32 *)0x9fc07ff0) == 1) - return *(u32 *)0x9fc07ff4; - - if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { - /* xT16 */ - return 393216000; - } else { - switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { - case 3: - return 475000000; - case 2: - return 450000000; - case 1: - return 425000000; - default: - return 400000000; - } - } -} -EXPORT_SYMBOL(ltq_svip_cpu_hz); - -unsigned int ltq_svip_fpi_hz(void) -{ - u32 fbs0_div[2] = {4, 8}; - u32 div; - - div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); - return ltq_svip_cpu_hz()/fbs0_div[div]; -} -EXPORT_SYMBOL(ltq_svip_fpi_hz); - -unsigned int ltq_get_ppl_hz(void) -{ - /* Magic BootROM speed location... */ - if ((*(u32 *)0x9fc07ff0) == 1) - return *(u32 *)0x9fc07ff4; - - if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { - /* xT16 */ - return 393216000; - } else { - switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { - case 3: - return 475000000; - case 2: - return 450000000; - case 1: - return 425000000; - default: - return 400000000; - } - } -} - -unsigned int ltq_get_fbs0_hz(void) -{ - u32 fbs0_div[2] = {4, 8}; - u32 div; - - div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); - return ltq_get_ppl_hz()/fbs0_div[div]; -} -EXPORT_SYMBOL(ltq_get_fbs0_hz); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.c deleted file mode 100644 index 735b9419f7..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.c +++ /dev/null @@ -1,380 +0,0 @@ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/string.h> -#include <linux/mtd/physmap.h> -#include <linux/kernel.h> -#include <linux/reboot.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/etherdevice.h> -#include <linux/reboot.h> -#include <linux/time.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/spi/spi.h> -#include <linux/mtd/nand.h> - -#include <asm/bootinfo.h> -#include <asm/irq.h> - -#include <lantiq.h> - -#include <base_reg.h> -#include <sys1_reg.h> -#include <sys2_reg.h> -#include <ebu_reg.h> - -#include "devices.h" - -#include <lantiq_soc.h> -#include <svip_mux.h> -#include <svip_pms.h> - -/* ASC */ -void __init svip_register_asc(int port) -{ - switch (port) { - case 0: - ltq_register_asc(0); - svip_sys1_clk_enable(SYS1_CLKENR_ASC0); - break; - case 1: - ltq_register_asc(1); - svip_sys1_clk_enable(SYS1_CLKENR_ASC1); - break; - default: - break; - }; -} - -/* Ethernet */ -static unsigned char svip_ethaddr[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; - -static struct platform_device ltq_mii = { - .name = "ifxmips_mii0", - .dev = { - .platform_data = svip_ethaddr, - }, -}; - -static int __init svip_set_ethaddr(char *str) -{ - sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", - &svip_ethaddr[0], &svip_ethaddr[1], &svip_ethaddr[2], - &svip_ethaddr[3], &svip_ethaddr[4], &svip_ethaddr[5]); - return 0; -} -__setup("ethaddr=", svip_set_ethaddr); - -void __init svip_register_eth(void) -{ - if (!is_valid_ether_addr(svip_ethaddr)) - random_ether_addr(svip_ethaddr); - - platform_device_register(<q_mii); - svip_sys1_clk_enable(SYS1_CLKENR_ETHSW); -} - -/* Virtual Ethernet */ -static struct platform_device ltq_ve = { - .name = "ifxmips_svip_ve", -}; - -void __init svip_register_virtual_eth(void) -{ - platform_device_register(<q_ve); -} - -/* SPI */ -static void __init ltq_register_ssc(int bus_num, unsigned long base, int irq_rx, - int irq_tx, int irq_err, int irq_frm) -{ - struct resource res[] = { - { - .name = "regs", - .start = base, - .end = base + 0x20 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "rx", - .start = irq_rx, - .flags = IORESOURCE_IRQ, - }, { - .name = "tx", - .start = irq_tx, - .flags = IORESOURCE_IRQ, - }, { - .name = "err", - .start = irq_err, - .flags = IORESOURCE_IRQ, - }, { - .name = "frm", - .start = irq_frm, - .flags = IORESOURCE_IRQ, - }, - }; - - platform_device_register_simple("ifx_ssc", bus_num, res, - ARRAY_SIZE(res)); -} - -static struct spi_board_info bdinfo[] __initdata = { - { - .modalias = "xt16", - .mode = SPI_MODE_3, - .irq = INT_NUM_IM5_IRL0 + 28, - .max_speed_hz = 1000000, - .bus_num = 0, - .chip_select = 1, - }, - { - .modalias = "xt16", - .mode = SPI_MODE_3, - .irq = INT_NUM_IM5_IRL0 + 19, - .max_speed_hz = 1000000, - .bus_num = 0, - .chip_select = 2, - }, - { - .modalias = "loop", - .mode = SPI_MODE_0 | SPI_LOOP, - .irq = -1, - .max_speed_hz = 10000000, - .bus_num = 0, - .chip_select = 3, - }, -}; - -void __init svip_register_spi(void) -{ - - ltq_register_ssc(0, LTQ_SSC0_BASE, INT_NUM_IM1_IRL0 + 6, - INT_NUM_IM1_IRL0 + 7, INT_NUM_IM1_IRL0 + 8, - INT_NUM_IM1_IRL0 + 9); - - ltq_register_ssc(1, LTQ_SSC1_BASE, INT_NUM_IM1_IRL0 + 10, - INT_NUM_IM1_IRL0 + 11, INT_NUM_IM1_IRL0 + 12, - INT_NUM_IM1_IRL0 + 13); - - spi_register_board_info(bdinfo, ARRAY_SIZE(bdinfo)); - - svip_sys1_clk_enable(SYS1_CLKENR_SSC0 | SYS1_CLKENR_SSC1); -} - -void __init svip_register_spi_flash(struct spi_board_info *bdinfo) -{ - spi_register_board_info(bdinfo, 1); -} - -/* GPIO */ -static struct platform_device ltq_gpio = { - .name = "ifxmips_gpio", -}; - -void __init svip_register_gpio(void) -{ - platform_device_register(<q_gpio); -} - -/* MUX */ -static struct ltq_mux_settings ltq_mux_settings; - -static struct platform_device ltq_mux = { - .name = "ltq_mux", - .dev = { - .platform_data = <q_mux_settings, - } -}; - -void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], - const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], - const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], - const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], - const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]) -{ - ltq_mux_settings.mux_p0 = mux_p0; - ltq_mux_settings.mux_p1 = mux_p1; - ltq_mux_settings.mux_p2 = mux_p2; - ltq_mux_settings.mux_p3 = mux_p3; - ltq_mux_settings.mux_p4 = mux_p4; - - if (mux_p0) - svip_sys1_clk_enable(SYS1_CLKENR_PORT0); - - if (mux_p1) - svip_sys1_clk_enable(SYS1_CLKENR_PORT1); - - if (mux_p2) - svip_sys1_clk_enable(SYS1_CLKENR_PORT2); - - if (mux_p3) - svip_sys1_clk_enable(SYS1_CLKENR_PORT3); - - if (mux_p4) - svip_sys2_clk_enable(SYS2_CLKENR_PORT4); - - platform_device_register(<q_mux); -} - -/* NAND */ -#define NAND_ADDR_REGION_BASE (LTQ_EBU_SEG1_BASE) -#define NAND_CLE_BIT (1 << 3) -#define NAND_ALE_BIT (1 << 2) - -static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; - -static int svip_nand_probe(struct platform_device *pdev) -{ - ebu_w32(LTQ_EBU_ADDR_SEL_0_BASE_VAL(CPHYSADDR(NAND_ADDR_REGION_BASE) - >> 12) - | LTQ_EBU_ADDR_SEL_0_MASK_VAL(15) - | LTQ_EBU_ADDR_SEL_0_MRME_VAL(0) - | LTQ_EBU_ADDR_SEL_0_REGEN_VAL(1), - addr_sel_0); - - ebu_w32(LTQ_EBU_CON_0_WRDIS_VAL(0) - | LTQ_EBU_CON_0_ADSWP_VAL(1) - | LTQ_EBU_CON_0_AGEN_VAL(0x00) - | LTQ_EBU_CON_0_SETUP_VAL(1) - | LTQ_EBU_CON_0_WAIT_VAL(0x00) - | LTQ_EBU_CON_0_WINV_VAL(0) - | LTQ_EBU_CON_0_PW_VAL(0x00) - | LTQ_EBU_CON_0_ALEC_VAL(0) - | LTQ_EBU_CON_0_BCGEN_VAL(0x01) - | LTQ_EBU_CON_0_WAITWRC_VAL(1) - | LTQ_EBU_CON_0_WAITRDC_VAL(1) - | LTQ_EBU_CON_0_HOLDC_VAL(1) - | LTQ_EBU_CON_0_RECOVC_VAL(0) - | LTQ_EBU_CON_0_CMULT_VAL(0x01), - con_0); - - /* - * ECC disabled - * CLE, ALE and CS are pulse, all other signal are latches based - * CLE and ALE are active high, PRE, WP, SE and CS/CE are active low - * OUT_CS_S is disabled - * NAND mode is disabled - */ - ebu_w32(LTQ_EBU_NAND_CON_ECC_ON_VAL(0) - | LTQ_EBU_NAND_CON_LAT_EN_VAL(0x38) - | LTQ_EBU_NAND_CON_OUT_CS_S_VAL(0) - | LTQ_EBU_NAND_CON_IN_CS_S_VAL(0) - | LTQ_EBU_NAND_CON_PRE_P_VAL(1) - | LTQ_EBU_NAND_CON_WP_P_VAL(1) - | LTQ_EBU_NAND_CON_SE_P_VAL(1) - | LTQ_EBU_NAND_CON_CS_P_VAL(1) - | LTQ_EBU_NAND_CON_CLE_P_VAL(0) - | LTQ_EBU_NAND_CON_ALE_P_VAL(0) - | LTQ_EBU_NAND_CON_CSMUX_E_VAL(0) - | LTQ_EBU_NAND_CON_NANDMODE_VAL(0), - nand_con); - - return 0; -} - -static void svip_nand_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - unsigned long adr; - /* Coming here means to change either the enable state or - * the address for controlling ALE or CLE */ - - /* NAND_NCE: Select the chip by setting nCE to low. - * This is done in CON register */ - if (ctrl & NAND_NCE) - ebu_w32_mask(0, LTQ_EBU_NAND_CON_NANDMODE_VAL(1), - nand_con); - else - ebu_w32_mask(LTQ_EBU_NAND_CON_NANDMODE_VAL(1), - 0, nand_con); - - /* The addressing of CLE or ALE is done via different addresses. - We are now changing the address depending on the given action - SVIPs NAND_CLE_BIT = (1 << 3), NAND_CLE = 0x02 - NAND_ALE_BIT = (1 << 2) = NAND_ALE (0x04) */ - adr = (unsigned long)this->IO_ADDR_W; - adr &= ~(NAND_CLE_BIT | NAND_ALE_BIT); - adr |= (ctrl & NAND_CLE) << 2 | (ctrl & NAND_ALE); - this->IO_ADDR_W = (void __iomem *)adr; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int svip_nand_ready(struct mtd_info *mtd) -{ - return (ebu_r32(nand_wait) & 0x01) == 0x01; -} - -static inline void svip_nand_wait(void) -{ - static const int nops = 150; - int i; - - for (i = 0; i < nops; i++) - asm("nop"); -} - -static void svip_nand_write_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) { - writeb(buf[i], this->IO_ADDR_W); - svip_nand_wait(); - } -} - -static void svip_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) { - buf[i] = readb(this->IO_ADDR_R); - svip_nand_wait(); - } -} - -static const char *part_probes[] = { "cmdlinepart", NULL }; - -static struct platform_nand_data svip_flash_nand_data = { - .chip = { - .nr_chips = 1, - .part_probe_types = part_probes, - }, - .ctrl = { - .probe = svip_nand_probe, - .cmd_ctrl = svip_nand_hwcontrol, - .dev_ready = svip_nand_ready, - .write_buf = svip_nand_write_buf, - .read_buf = svip_nand_read_buf, - } -}; - -static struct resource svip_nand_resources[] = { - MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX), -}; - -static struct platform_device svip_flash_nand = { - .name = "gen_nand", - .id = -1, - .num_resources = ARRAY_SIZE(svip_nand_resources), - .resource = svip_nand_resources, - .dev = { - .platform_data = &svip_flash_nand_data, - }, -}; - -void __init svip_register_nand(void) -{ - platform_device_register(&svip_flash_nand); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.h b/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.h deleted file mode 100644 index a064e67ec1..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _SVIP_DEVICES_H__ -#define _SVIP_DEVICES_H__ - -#include <linux/mtd/physmap.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#include <svip_mux.h> -#include "../devices.h" - -extern void __init svip_register_asc(int port); -extern void __init svip_register_eth(void); -extern void __init svip_register_virtual_eth(void); -extern void __init svip_register_spi(void); -extern void __init svip_register_spi_flash(struct spi_board_info *bdinfo); -extern void __init svip_register_gpio(void); -extern void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], - const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], - const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], - const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], - const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]); -extern void __init svip_register_nand(void); - -#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/dma.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/dma.c deleted file mode 100644 index 7464be1bd5..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/dma.c +++ /dev/null @@ -1,1206 +0,0 @@ -/* - ** Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com> - ** - ** This program is free software; you can redistribute it and/or modify - ** it under the terms of the GNU General Public License as published by - ** the Free Software Foundation; either version 2 of the License, or - ** (at your option) any later version. - ** - ** This program is distributed in the hope that it will be useful, - ** but WITHOUT ANY WARRANTY; without even the implied warranty of - ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - ** GNU General Public License for more details. - ** - ** You should have received a copy of the GNU General Public License - ** along with this program; if not, write to the Free Software - ** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -/* - * Description: - * Driver for SVIP DMA - * Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com] - * Created: 26-September-2005 - */ - -#include <linux/module.h> -#include <linux/init.h> -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/string.h> -#include <linux/timer.h> -#include <linux/fs.h> -#include <linux/errno.h> -#include <linux/proc_fs.h> -#include <linux/stat.h> -#include <linux/mm.h> -#include <linux/tty.h> -#include <linux/selection.h> -#include <linux/kmod.h> -#include <linux/vmalloc.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/uaccess.h> -#include <linux/io.h> -#include <linux/semaphore.h> - -#include <base_reg.h> -#include <mps_reg.h> -#include <dma_reg.h> -#include <svip_dma.h> -#include <lantiq_soc.h> -#include <irq.h> -#include <sys1_reg.h> - -static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; -static struct svip_reg_dma *const dma = (struct svip_reg_dma *)LTQ_DMA_BASE; -static struct svip_reg_mbs *const mbs = (struct svip_reg_mbs *)LTQ_MBS_BASE; - -#define DRV_NAME "ltq_dma" -extern void ltq_mask_and_ack_irq(struct irq_data *data); -extern void ltq_enable_irq(struct irq_data *data); - -static inline void mask_and_ack_irq(unsigned int irq_nr) -{ - static int i = 0; - struct irq_data data; - data.irq = irq_nr; - if ((i < 2) && (irq_nr == 137)) { - printk("eth delay hack\n"); - i++; - } - ltq_mask_and_ack_irq(&data); -} - -static inline void svip_enable_irq(unsigned int irq_nr) -{ - struct irq_data data; - data.irq = irq_nr; - ltq_enable_irq(&data); -} - -#define DMA_EMSG(fmt, args...) \ - printk(KERN_ERR "%s: " fmt, __func__, ## args) - -static inline void mbs_grab(void) -{ - while (mbs_r32(mbsr0) != 0); -} - -static inline void mbs_release(void) -{ - mbs_w32(0, mbsr0); - asm("sync"); -} - -/* max ports connecting to dma */ -#define LTQ_MAX_DMA_DEVICE_NUM ARRAY_SIZE(dma_devices) -/* max dma channels */ -#define LTQ_MAX_DMA_CHANNEL_NUM ARRAY_SIZE(dma_chan) - -/* bytes per descriptor */ -#define DMA_DESCR_SIZE 8 - -#define DMA_DESCR_CH_SIZE (DMA_DESCR_NUM * DMA_DESCR_SIZE) -#define DMA_DESCR_TOTAL_SIZE (LTQ_MAX_DMA_CHANNEL_NUM * DMA_DESCR_CH_SIZE) -#define DMA_DESCR_MEM_PAGES ((DMA_DESCR_TOTAL_SIZE / PAGE_SIZE) + \ - (((DMA_DESCR_TOTAL_SIZE % PAGE_SIZE) > 0))) - -/* budget for interrupt handling */ -#define DMA_INT_BUDGET 100 -/* set the correct counter value here! */ -#define DMA_POLL_COUNTER 32 - -struct proc_dir_entry *g_dma_dir; - -/* device_name | max_rx_chan_num | max_tx_chan_num | drop_enable */ -struct dma_device_info dma_devices[] = { - { "SW", 4, 4, 0 }, - { "DEU", 1, 1, 0 }, - { "SSC0", 1, 1, 0 }, - { "SSC1", 1, 1, 0 }, - { "MCTRL", 1, 1, 0 }, - { "PCM0", 1, 1, 0 }, - { "PCM1", 1, 1, 0 }, - { "PCM2", 1, 1, 0 }, - { "PCM3", 1, 1, 0 } -}; - -/* *dma_dev | dir | pri | irq | rel_chan_no */ -struct dma_channel_info dma_chan[] = { - { &dma_devices[0], DIR_RX, 0, INT_NUM_IM4_IRL0 + 0, 0 }, - { &dma_devices[0], DIR_TX, 0, INT_NUM_IM4_IRL0 + 1, 0 }, - { &dma_devices[0], DIR_RX, 1, INT_NUM_IM4_IRL0 + 2, 1 }, - { &dma_devices[0], DIR_TX, 1, INT_NUM_IM4_IRL0 + 3, 1 }, - { &dma_devices[0], DIR_RX, 2, INT_NUM_IM4_IRL0 + 4, 2 }, - { &dma_devices[0], DIR_TX, 2, INT_NUM_IM4_IRL0 + 5, 2 }, - { &dma_devices[0], DIR_RX, 3, INT_NUM_IM4_IRL0 + 6, 3 }, - { &dma_devices[0], DIR_TX, 3, INT_NUM_IM4_IRL0 + 7, 3 }, - { &dma_devices[1], DIR_RX, 0, INT_NUM_IM4_IRL0 + 8, 0 }, - { &dma_devices[1], DIR_TX, 0, INT_NUM_IM4_IRL0 + 9, 0 }, - { &dma_devices[2], DIR_RX, 0, INT_NUM_IM4_IRL0 + 10, 0 }, - { &dma_devices[2], DIR_TX, 0, INT_NUM_IM4_IRL0 + 11, 0 }, - { &dma_devices[3], DIR_RX, 0, INT_NUM_IM4_IRL0 + 12, 0 }, - { &dma_devices[3], DIR_TX, 0, INT_NUM_IM4_IRL0 + 13, 0 }, - { &dma_devices[4], DIR_RX, 0, INT_NUM_IM4_IRL0 + 14, 0 }, - { &dma_devices[4], DIR_TX, 0, INT_NUM_IM4_IRL0 + 15, 0 }, - { &dma_devices[5], DIR_RX, 0, INT_NUM_IM4_IRL0 + 16, 0 }, - { &dma_devices[5], DIR_TX, 0, INT_NUM_IM4_IRL0 + 17, 0 }, - { &dma_devices[6], DIR_RX, 1, INT_NUM_IM3_IRL0 + 18, 0 }, - { &dma_devices[6], DIR_TX, 1, INT_NUM_IM3_IRL0 + 19, 0 }, - { &dma_devices[7], DIR_RX, 2, INT_NUM_IM4_IRL0 + 20, 0 }, - { &dma_devices[7], DIR_TX, 2, INT_NUM_IM4_IRL0 + 21, 0 }, - { &dma_devices[8], DIR_RX, 3, INT_NUM_IM4_IRL0 + 22, 0 }, - { &dma_devices[8], DIR_TX, 3, INT_NUM_IM4_IRL0 + 23, 0 } -}; - -u64 *g_desc_list[DMA_DESCR_MEM_PAGES]; - -volatile u32 g_dma_int_status = 0; - -/* 0 - not in process, 1 - in process */ -volatile int g_dma_in_process; - -int ltq_dma_init(void); -void do_dma_tasklet(unsigned long); -DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0); -irqreturn_t dma_interrupt(int irq, void *dev_id); - -u8 *common_buffer_alloc(int len, int *byte_offset, void **opt) -{ - u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL); - *byte_offset = 0; - return buffer; -} - -void common_buffer_free(u8 *dataptr, void *opt) -{ - kfree(dataptr); -} - -void enable_ch_irq(struct dma_channel_info *ch) -{ - int chan_no = (int)(ch - dma_chan); - unsigned long flag; - u32 val; - - if (ch->dir == DIR_RX) - val = DMA_CIE_DESCPT | DMA_CIE_DUR; - else - val = DMA_CIE_DESCPT; - - local_irq_save(flag); - mbs_grab(); - dma_w32(chan_no, cs); - dma_w32(val, cie); - dma_w32_mask(0, 1 << chan_no, irnen); - mbs_release(); - local_irq_restore(flag); - - svip_enable_irq(ch->irq); -} - -void disable_ch_irq(struct dma_channel_info *ch) -{ - unsigned long flag; - int chan_no = (int)(ch - dma_chan); - - local_irq_save(flag); - g_dma_int_status &= ~(1 << chan_no); - mbs_grab(); - dma_w32(chan_no, cs); - dma_w32(0, cie); - mbs_release(); - dma_w32_mask(1 << chan_no, 0, irnen); - local_irq_restore(flag); - - mask_and_ack_irq(ch->irq); -} - -int open_chan(struct dma_channel_info *ch) -{ - unsigned long flag; - int j; - int chan_no = (int)(ch - dma_chan); - u8 *buffer; - int byte_offset; - struct rx_desc *rx_desc_p; - struct tx_desc *tx_desc_p; - - if (ch->control == LTQ_DMA_CH_ON) - return -1; - - if (ch->dir == DIR_RX) { - for (j = 0; j < ch->desc_len; j++) { - rx_desc_p = (struct rx_desc *)ch->desc_base+j; - buffer = ch->dma_dev->buffer_alloc(ch->packet_size, - &byte_offset, - (void *)&ch->opt[j]); - if (!buffer) - return -ENOBUFS; - - rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buffer); - rx_desc_p->status.word = 0; - rx_desc_p->status.field.byte_offset = byte_offset; - rx_desc_p->status.field.data_length = ch->packet_size; - rx_desc_p->status.field.own = DMA_OWN; - } - } else { - for (j = 0; j < ch->desc_len; j++) { - tx_desc_p = (struct tx_desc *)ch->desc_base + j; - tx_desc_p->data_pointer = 0; - tx_desc_p->status.word = 0; - } - } - ch->xfer_cnt = 0; - - local_irq_save(flag); - mbs_grab(); - dma_w32(chan_no, cs); - dma_w32(ch->desc_len, cdlen); - dma_w32(0x7e, cis); - dma_w32(DMA_CCTRL_TXWGT_VAL(ch->tx_weight) - | DMA_CCTRL_CLASS_VAL(ch->pri) - | (ch->dir == DIR_RX ? DMA_CCTRL_ON_OFF : 0), cctrl); - mbs_release(); - ch->control = LTQ_DMA_CH_ON; - local_irq_restore(flag); - - if (request_irq(ch->irq, dma_interrupt, - IRQF_DISABLED, "dma-core", (void *)ch) != 0) { - printk(KERN_ERR "error, cannot get dma_irq!\n"); - return -EFAULT; - } - - enable_ch_irq(ch); - return 0; -} - -int close_chan(struct dma_channel_info *ch) -{ - unsigned long flag; - int j; - int chan_no = (int)(ch - dma_chan); - struct rx_desc *desc_p; - - if (ch->control == LTQ_DMA_CH_OFF) - return -1; - - local_irq_save(flag); - mbs_grab(); - dma_w32(chan_no, cs); - dma_w32_mask(DMA_CCTRL_ON_OFF, 0, cctrl); - mbs_release(); - disable_ch_irq(ch); - free_irq(ch->irq, (void *)ch); - ch->control = LTQ_DMA_CH_OFF; - local_irq_restore(flag); - - /* free descriptors in use */ - for (j = 0; j < ch->desc_len; j++) { - desc_p = (struct rx_desc *)ch->desc_base+j; - if ((desc_p->status.field.own == CPU_OWN && - desc_p->status.field.c) || - (desc_p->status.field.own == DMA_OWN)) { - if (desc_p->data_pointer) { - ch->dma_dev->buffer_free((u8 *)__va(desc_p->data_pointer), - (void *)ch->opt[j]); - desc_p->data_pointer = (u32)NULL; - } - } - } - - return 0; -} - -int reset_chan(struct dma_channel_info *ch) -{ - unsigned long flag; - int val; - int chan_no = (int)(ch - dma_chan); - - close_chan(ch); - - local_irq_save(flag); - mbs_grab(); - dma_w32(chan_no, cs); - dma_w32_mask(0, DMA_CCTRL_RST, cctrl); - mbs_release(); - local_irq_restore(flag); - - do { - local_irq_save(flag); - mbs_grab(); - dma_w32(chan_no, cs); - val = dma_r32(cctrl); - mbs_release(); - local_irq_restore(flag); - } while (val & DMA_CCTRL_RST); - - return 0; -} - -static inline void rx_chan_intr_handler(int chan_no) -{ - struct dma_device_info *dma_dev = (struct dma_device_info *) - dma_chan[chan_no].dma_dev; - struct dma_channel_info *ch = &dma_chan[chan_no]; - struct rx_desc *rx_desc_p; - unsigned long flag; - u32 val; - - local_irq_save(flag); - mbs_grab(); - dma_w32(chan_no, cs); - val = dma_r32(cis); - dma_w32(DMA_CIS_DESCPT, cis); - mbs_release(); - - /* handle command complete interrupt */ - rx_desc_p = (struct rx_desc *)ch->desc_base + ch->curr_desc; - if ((rx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == - DMA_DESC_CPT_SET) { - local_irq_restore(flag); - /* Every thing is correct, then we inform the upper layer */ - dma_dev->current_rx_chan = ch->rel_chan_no; - if (dma_dev->intr_handler) - dma_dev->intr_handler(dma_dev, RCV_INT); - ch->weight--; - } else { - g_dma_int_status &= ~(1 << chan_no); - local_irq_restore(flag); - svip_enable_irq(dma_chan[chan_no].irq); - } -} - -static inline void tx_chan_intr_handler(int chan_no) -{ - struct dma_device_info *dma_dev = (struct dma_device_info *) - dma_chan[chan_no].dma_dev; - struct dma_channel_info *ch = &dma_chan[chan_no]; - struct tx_desc *tx_desc_p; - unsigned long flag; - - local_irq_save(flag); - mbs_grab(); - dma_w32(chan_no, cs); - dma_w32(DMA_CIS_DESCPT, cis); - mbs_release(); - - tx_desc_p = (struct tx_desc *)ch->desc_base+ch->prev_desc; - if ((tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == - DMA_DESC_CPT_SET) { - local_irq_restore(flag); - - dma_dev->buffer_free((u8 *)__va(tx_desc_p->data_pointer), - ch->opt[ch->prev_desc]); - memset(tx_desc_p, 0, sizeof(struct tx_desc)); - dma_dev->current_tx_chan = ch->rel_chan_no; - if (dma_dev->intr_handler) - dma_dev->intr_handler(dma_dev, TRANSMIT_CPT_INT); - ch->weight--; - - ch->prev_desc = (ch->prev_desc + 1) % (ch->desc_len); - } else { - g_dma_int_status &= ~(1 << chan_no); - local_irq_restore(flag); - svip_enable_irq(dma_chan[chan_no].irq); - } -} - -void do_dma_tasklet(unsigned long unused) -{ - int i; - int chan_no = 0; - int budget = DMA_INT_BUDGET; - int weight = 0; - unsigned long flag; - - while (g_dma_int_status) { - if (budget-- < 0) { - tasklet_schedule(&dma_tasklet); - return; - } - chan_no = -1; - weight = 0; - /* WFQ algorithm to select the channel */ - for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { - if (g_dma_int_status & (1 << i) && - dma_chan[i].weight > 0) { - if (dma_chan[i].weight > weight) { - chan_no = i; - weight = dma_chan[chan_no].weight; - } - } - } - if (chan_no >= 0) { - if (dma_chan[chan_no].dir == DIR_RX) - rx_chan_intr_handler(chan_no); - else - tx_chan_intr_handler(chan_no); - } else { - /* reset all the channels */ - for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) - dma_chan[i].weight = dma_chan[i].default_weight; - } - } - - local_irq_save(flag); - g_dma_in_process = 0; - if (g_dma_int_status) { - g_dma_in_process = 1; - tasklet_schedule(&dma_tasklet); - } - local_irq_restore(flag); -} - -irqreturn_t dma_interrupt(int irq, void *dev_id) -{ - struct dma_channel_info *ch; - int chan_no = 0; - - ch = (struct dma_channel_info *)dev_id; - chan_no = (int)(ch - dma_chan); - - if ((unsigned)chan_no >= LTQ_MAX_DMA_CHANNEL_NUM) { - printk(KERN_ERR "error: dma_interrupt irq=%d chan_no=%d\n", - irq, chan_no); - } - - g_dma_int_status |= 1 << chan_no; - dma_w32(1 << chan_no, irncr); - mask_and_ack_irq(irq); - - if (!g_dma_in_process) { - g_dma_in_process = 1; - tasklet_schedule(&dma_tasklet); - } - - return IRQ_RETVAL(1); -} - -struct dma_device_info *dma_device_reserve(char *dev_name) -{ - int i; - - ltq_dma_init(); - for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { - if (strcmp(dev_name, dma_devices[i].device_name) == 0) { - if (dma_devices[i].reserved) - return NULL; - dma_devices[i].reserved = 1; - break; - } - } - - if (i == LTQ_MAX_DMA_DEVICE_NUM) - return NULL; - - return &dma_devices[i]; -} -EXPORT_SYMBOL(dma_device_reserve); - -int dma_device_release(struct dma_device_info *dma_dev) -{ - dma_dev->reserved = 0; - - return 0; -} -EXPORT_SYMBOL(dma_device_release); - -int dma_device_register(struct dma_device_info *dma_dev) -{ - int port_no = (int)(dma_dev - dma_devices); - int txbl, rxbl; - unsigned long flag; - - switch (dma_dev->tx_burst_len) { - case 8: - txbl = 3; - break; - case 4: - txbl = 2; - break; - default: - txbl = 1; - break; - } - - switch (dma_dev->rx_burst_len) { - case 8: - rxbl = 3; - break; - case 4: - rxbl = 2; - break; - default: - rxbl = 1; - } - - local_irq_save(flag); - mbs_grab(); - dma_w32(port_no, ps); - dma_w32(DMA_PCTRL_TXWGT_VAL(dma_dev->tx_weight) - | DMA_PCTRL_TXENDI_VAL(dma_dev->tx_endianness_mode) - | DMA_PCTRL_RXENDI_VAL(dma_dev->rx_endianness_mode) - | DMA_PCTRL_PDEN_VAL(dma_dev->drop_enable) - | DMA_PCTRL_TXBL_VAL(txbl) - | DMA_PCTRL_RXBL_VAL(rxbl), pctrl); - mbs_release(); - local_irq_restore(flag); - - return 0; -} -EXPORT_SYMBOL(dma_device_register); - -int dma_device_unregister(struct dma_device_info *dma_dev) -{ - int i; - int port_no = (int)(dma_dev - dma_devices); - unsigned long flag; - - /* flush memcopy module; has no effect for other ports */ - local_irq_save(flag); - mbs_grab(); - dma_w32(port_no, ps); - dma_w32_mask(0, DMA_PCTRL_GPC, pctrl); - mbs_release(); - local_irq_restore(flag); - - for (i = 0; i < dma_dev->max_tx_chan_num; i++) - reset_chan(dma_dev->tx_chan[i]); - - for (i = 0; i < dma_dev->max_rx_chan_num; i++) - reset_chan(dma_dev->rx_chan[i]); - - return 0; -} -EXPORT_SYMBOL(dma_device_unregister); - -/** - * Read Packet from DMA Rx channel. - * The function gets the data from the current rx descriptor assigned - * to the passed DMA device and passes it back to the caller. - * The function is called in the context of DMA interrupt. - * In detail the following actions are done: - * - get current receive descriptor - * - allocate memory via allocation callback function - * - pass data from descriptor to allocated memory - * - update channel weight - * - release descriptor - * - update current descriptor position - * - * \param *dma_dev - pointer to DMA device structure - * \param **dataptr - pointer to received data - * \param **opt - * \return packet length - length of received data - * \ingroup Internal - */ -int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt) -{ - u8 *buf; - int len; - int byte_offset = 0; - void *p = NULL; - - struct dma_channel_info *ch = - dma_dev->rx_chan[dma_dev->current_rx_chan]; - - struct rx_desc *rx_desc_p; - - /* get the rx data first */ - rx_desc_p = (struct rx_desc *)ch->desc_base+ch->curr_desc; - buf = (u8 *)__va(rx_desc_p->data_pointer); - *(u32 *)dataptr = (u32)buf; - len = rx_desc_p->status.field.data_length; -#ifndef CONFIG_MIPS_UNCACHED - dma_cache_inv((unsigned long)buf, len); -#endif - if (opt) - *(int *)opt = (int)ch->opt[ch->curr_desc]; - - /* replace with a new allocated buffer */ - buf = dma_dev->buffer_alloc(ch->packet_size, &byte_offset, &p); - if (buf) { - ch->opt[ch->curr_desc] = p; - - wmb(); - rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buf); - rx_desc_p->status.word = (DMA_OWN << 31) \ - |(byte_offset << 23) \ - | ch->packet_size; - - wmb(); - } else { - *(u32 *)dataptr = 0; - if (opt) - *(int *)opt = 0; - } - - ch->xfer_cnt++; - /* increase the curr_desc pointer */ - ch->curr_desc++; - if (ch->curr_desc == ch->desc_len) - ch->curr_desc = 0; - /* return the length of the received packet */ - return len; -} -EXPORT_SYMBOL(dma_device_read); - -/** - * Write Packet through DMA Tx channel to peripheral. - * - * \param *dma_dev - pointer to DMA device structure - * \param *dataptr - pointer to data to be sent - * \param len - amount of data bytes to be sent - * \param *opt - * \return len - length of transmitted data - * \ingroup Internal - */ -int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, - void *opt) -{ - unsigned long flag; - u32 byte_offset; - struct dma_channel_info *ch; - int chan_no; - struct tx_desc *tx_desc_p; - local_irq_save(flag); - - ch = dma_dev->tx_chan[dma_dev->current_tx_chan]; - chan_no = (int)(ch - dma_chan); - - if (ch->control == LTQ_DMA_CH_OFF) { - local_irq_restore(flag); - printk(KERN_ERR "%s: dma channel %d not enabled!\n", - __func__, chan_no); - return 0; - } - - tx_desc_p = (struct tx_desc *)ch->desc_base+ch->curr_desc; - /* Check whether this descriptor is available */ - if (tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) { - /* if not , the tell the upper layer device */ - dma_dev->intr_handler(dma_dev, TX_BUF_FULL_INT); - local_irq_restore(flag); - return 0; - } - ch->opt[ch->curr_desc] = opt; - /* byte offset----to adjust the starting address of the data buffer, - * should be multiple of the burst length.*/ - byte_offset = ((u32)CPHYSADDR((u32)dataptr)) % - (dma_dev->tx_burst_len * 4); -#ifndef CONFIG_MIPS_UNCACHED - dma_cache_wback((unsigned long)dataptr, len); - wmb(); -#endif - tx_desc_p->data_pointer = (u32)CPHYSADDR((u32)dataptr) - byte_offset; - wmb(); - tx_desc_p->status.word = (DMA_OWN << 31) - | DMA_DESC_SOP_SET - | DMA_DESC_EOP_SET - | (byte_offset << 23) - | len; - wmb(); - - if (ch->xfer_cnt == 0) { - mbs_grab(); - dma_w32(chan_no, cs); - dma_w32_mask(0, DMA_CCTRL_ON_OFF, cctrl); - mbs_release(); - } - - ch->xfer_cnt++; - ch->curr_desc++; - if (ch->curr_desc == ch->desc_len) - ch->curr_desc = 0; - - local_irq_restore(flag); - return len; -} -EXPORT_SYMBOL(dma_device_write); - -/** - * Display descriptor list via proc file - * - * \param chan_no - logical channel number - * \ingroup Internal - */ -int desc_list_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int len = 0; - int i; - static int chan_no; - u32 *p; - - if ((chan_no == 0) && (offset > count)) { - *eof = 1; - return 0; - } - - if (chan_no != 0) { - *start = buf; - } else { - buf = buf + offset; - *start = buf; - } - - p = (u32 *)dma_chan[chan_no].desc_base; - - if (dma_chan[chan_no].dir == DIR_RX) - len += sprintf(buf + len, - "channel %d %s Rx descriptor list:\n", - chan_no, dma_chan[chan_no].dma_dev->device_name); - else - len += sprintf(buf + len, - "channel %d %s Tx descriptor list:\n", - chan_no, dma_chan[chan_no].dma_dev->device_name); - len += sprintf(buf + len, - " no address data pointer command bits " - "(Own, Complete, SoP, EoP, Offset) \n"); - len += sprintf(buf + len, - "----------------------------------------------" - "-----------------------------------\n"); - for (i = 0; i < dma_chan[chan_no].desc_len; i++) { - len += sprintf(buf + len, "%3d ", i); - len += sprintf(buf + len, "0x%08x ", (u32)(p + (i * 2))); - len += sprintf(buf + len, "%08x ", *(p + (i * 2 + 1))); - len += sprintf(buf + len, "%08x ", *(p + (i * 2))); - - if (*(p + (i * 2)) & 0x80000000) - len += sprintf(buf + len, "D "); - else - len += sprintf(buf + len, "C "); - if (*(p + (i * 2)) & 0x40000000) - len += sprintf(buf + len, "C "); - else - len += sprintf(buf + len, "c "); - if (*(p + (i * 2)) & 0x20000000) - len += sprintf(buf + len, "S "); - else - len += sprintf(buf + len, "s "); - if (*(p + (i * 2)) & 0x10000000) - len += sprintf(buf + len, "E "); - else - len += sprintf(buf + len, "e "); - - /* byte offset is different for rx and tx descriptors*/ - if (dma_chan[chan_no].dir == DIR_RX) { - len += sprintf(buf + len, "%01x ", - (*(p + (i * 2)) & 0x01800000) >> 23); - } else { - len += sprintf(buf + len, "%02x ", - (*(p + (i * 2)) & 0x0F800000) >> 23); - } - - if (dma_chan[chan_no].curr_desc == i) - len += sprintf(buf + len, "<- CURR"); - - if (dma_chan[chan_no].prev_desc == i) - len += sprintf(buf + len, "<- PREV"); - - len += sprintf(buf + len, "\n"); - - } - - len += sprintf(buf + len, "\n"); - chan_no++; - if (chan_no > LTQ_MAX_DMA_CHANNEL_NUM - 1) - chan_no = 0; - - *eof = 1; - return len; -} - -/** - * Displays the weight of all DMA channels via proc file - * - * - * - * \param *buf - * \param **start - * \param offset - * \param count - * \param *eof - * \param *data - * \return len - amount of bytes written to file - */ -int channel_weight_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int i; - int len = 0; - len += sprintf(buf + len, "Qos dma channel weight list\n"); - len += sprintf(buf + len, "channel_num default_weight " - "current_weight device Tx/Rx\n"); - len += sprintf(buf + len, "---------------------------" - "---------------------------------\n"); - for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { - struct dma_channel_info *ch = &dma_chan[i]; - - if (ch->dir == DIR_RX) { - len += sprintf(buf + len, - " %2d %08x " - "%08x %10s Rx\n", - i, ch->default_weight, ch->weight, - ch->dma_dev->device_name); - } else { - len += sprintf(buf + len, - " %2d %08x " - "%08x %10s Tx\n", - i, ch->default_weight, ch->weight, - ch->dma_dev->device_name); - } - } - - return len; -} - -/** - * Provides DMA Register Content to proc file - * This function reads the content of general DMA Registers, DMA Channel - * Registers and DMA Port Registers and performs a structures output to the - * DMA proc file - * - * \param *buf - * \param **start - * \param offset - * \param count - * \param *eof - * \param *data - * \return len - amount of bytes written to file - */ -int dma_register_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int len = 0; - int i; - int limit = count; - unsigned long flags; - static int blockcount; - static int channel_no; - - if ((blockcount == 0) && (offset > count)) { - *eof = 1; - return 0; - } - - switch (blockcount) { - case 0: - len += sprintf(buf + len, "\nGeneral DMA Registers\n"); - len += sprintf(buf + len, "-------------------------" - "----------------\n"); - len += sprintf(buf + len, "CLC= %08x\n", dma_r32(clc)); - len += sprintf(buf + len, "ID= %08x\n", dma_r32(id)); - len += sprintf(buf + len, "DMA_CPOLL= %08x\n", dma_r32(cpoll)); - len += sprintf(buf + len, "DMA_CS= %08x\n", dma_r32(cs)); - len += sprintf(buf + len, "DMA_PS= %08x\n", dma_r32(ps)); - len += sprintf(buf + len, "DMA_IRNEN= %08x\n", dma_r32(irnen)); - len += sprintf(buf + len, "DMA_IRNCR= %08x\n", dma_r32(irncr)); - len += sprintf(buf + len, "DMA_IRNICR= %08x\n", - dma_r32(irnicr)); - len += sprintf(buf + len, "\nDMA Channel Registers\n"); - blockcount = 1; - return len; - break; - case 1: - /* If we had an overflow start at beginning of buffer - * otherwise use offset */ - if (channel_no != 0) { - *start = buf; - } else { - buf = buf + offset; - *start = buf; - } - - local_irq_save(flags); - for (i = channel_no; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { - struct dma_channel_info *ch = &dma_chan[i]; - - if (len + 300 > limit) { - local_irq_restore(flags); - channel_no = i; - blockcount = 1; - return len; - } - len += sprintf(buf + len, "----------------------" - "-------------------\n"); - if (ch->dir == DIR_RX) { - len += sprintf(buf + len, - "Channel %d - Device %s Rx\n", - i, ch->dma_dev->device_name); - } else { - len += sprintf(buf + len, - "Channel %d - Device %s Tx\n", - i, ch->dma_dev->device_name); - } - dma_w32(i, cs); - len += sprintf(buf + len, "DMA_CCTRL= %08x\n", - dma_r32(cctrl)); - len += sprintf(buf + len, "DMA_CDBA= %08x\n", - dma_r32(cdba)); - len += sprintf(buf + len, "DMA_CIE= %08x\n", - dma_r32(cie)); - len += sprintf(buf + len, "DMA_CIS= %08x\n", - dma_r32(cis)); - len += sprintf(buf + len, "DMA_CDLEN= %08x\n", - dma_r32(cdlen)); - } - local_irq_restore(flags); - blockcount = 2; - channel_no = 0; - return len; - break; - case 2: - *start = buf; - /* - * display port dependent registers - */ - len += sprintf(buf + len, "\nDMA Port Registers\n"); - len += sprintf(buf + len, - "-----------------------------------------\n"); - local_irq_save(flags); - for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { - dma_w32(i, ps); - len += sprintf(buf + len, - "Port %d DMA_PCTRL= %08x\n", - i, dma_r32(pctrl)); - } - local_irq_restore(flags); - blockcount = 0; - *eof = 1; - return len; - break; - } - - blockcount = 0; - *eof = 1; - return 0; -} - -/** - * Open Method of DMA Device Driver - * This function increments the device driver's use counter. - * - * - * \param - * \return - */ -static int dma_open(struct inode *inode, struct file *file) -{ - return 0; -} - -/** - * Release Method of DMA Device driver. - * This function decrements the device driver's use counter. - * - * - * \param - * \return - */ -static int dma_release(struct inode *inode, struct file *file) -{ - /* release the resources */ - return 0; -} - -/** - * Ioctl Interface to DMA Module - * - * \param None - * \return 0 - initialization successful - * <0 - failed initialization - */ -static long dma_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - int result = 0; - /* TODO: add some user controled functions here */ - return result; -} - -const static struct file_operations dma_fops = { - .owner = THIS_MODULE, - .open = dma_open, - .release = dma_release, - .unlocked_ioctl = dma_ioctl, -}; - -void map_dma_chan(struct dma_channel_info *map) -{ - int i; - - /* assign default values for channel settings */ - for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { - dma_chan[i].byte_offset = 0; - dma_chan[i].open = &open_chan; - dma_chan[i].close = &close_chan; - dma_chan[i].reset = &reset_chan; - dma_chan[i].enable_irq = enable_ch_irq; - dma_chan[i].disable_irq = disable_ch_irq; - dma_chan[i].tx_weight = 1; - dma_chan[i].control = 0; - dma_chan[i].default_weight = LTQ_DMA_CH_DEFAULT_WEIGHT; - dma_chan[i].weight = dma_chan[i].default_weight; - dma_chan[i].curr_desc = 0; - dma_chan[i].prev_desc = 0; - } - - /* assign default values for port settings */ - for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { - /*set default tx channel number to be one*/ - dma_devices[i].num_tx_chan = 1; - /*set default rx channel number to be one*/ - dma_devices[i].num_rx_chan = 1; - dma_devices[i].buffer_alloc = common_buffer_alloc; - dma_devices[i].buffer_free = common_buffer_free; - dma_devices[i].intr_handler = NULL; - dma_devices[i].tx_burst_len = 4; - dma_devices[i].rx_burst_len = 4; -#ifdef CONFIG_CPU_LITTLE_ENDIAN - dma_devices[i].tx_endianness_mode = 0; - dma_devices[i].rx_endianness_mode = 0; -#else - dma_devices[i].tx_endianness_mode = 3; - dma_devices[i].rx_endianness_mode = 3; -#endif - } -} - -void dma_chip_init(void) -{ - int i; - - sys1_w32(SYS1_CLKENR_DMA, clkenr); - wmb(); - /* reset DMA */ - dma_w32(DMA_CTRL_RST, ctrl); - wmb(); - /* disable all the interrupts first */ - dma_w32(0, irnen); - - /* enable polling for all channels */ - dma_w32(DMA_CPOLL_EN | DMA_CPOLL_CNT_VAL(DMA_POLL_COUNTER), cpoll); - - /****************************************************/ - for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) - disable_ch_irq(&dma_chan[i]); -} - -int ltq_dma_init(void) -{ - int result = 0; - int i; - unsigned long flag; - static int dma_initialized; - - if (dma_initialized == 1) - return 0; - dma_initialized = 1; - - result = register_chrdev(DMA_MAJOR, "dma-core", &dma_fops); - if (result) { - DMA_EMSG("cannot register device dma-core!\n"); - return result; - } - - dma_chip_init(); - map_dma_chan(dma_chan); - - /* allocate DMA memory for buffer descriptors */ - for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) { - g_desc_list[i] = (u64 *)__get_free_page(GFP_DMA); - if (g_desc_list[i] == NULL) { - DMA_EMSG("no memory for desriptor\n"); - return -ENOMEM; - } - g_desc_list[i] = (u64 *)KSEG1ADDR(g_desc_list[i]); - memset(g_desc_list[i], 0, PAGE_SIZE); - } - - for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { - int page_index, ch_per_page; - /* cross-link relative channels of a port to - * corresponding absolute channels */ - if (dma_chan[i].dir == DIR_RX) { - ((struct dma_device_info *)(dma_chan[i].dma_dev))-> - rx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; - } else { - ((struct dma_device_info *)(dma_chan[i].dma_dev))-> - tx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; - } - dma_chan[i].abs_chan_no = i; - - page_index = i * DMA_DESCR_CH_SIZE / PAGE_SIZE; - ch_per_page = PAGE_SIZE / DMA_DESCR_CH_SIZE + - ((PAGE_SIZE % DMA_DESCR_CH_SIZE) > 0); - dma_chan[i].desc_base = - (u32)g_desc_list[page_index] + - (i - page_index*ch_per_page) * DMA_DESCR_NUM*8; - dma_chan[i].curr_desc = 0; - dma_chan[i].desc_len = DMA_DESCR_NUM; - - local_irq_save(flag); - mbs_grab(); - dma_w32(i, cs); - dma_w32((u32)CPHYSADDR(dma_chan[i].desc_base), cdba); - mbs_release(); - local_irq_restore(flag); - } - - g_dma_dir = proc_mkdir("driver/" DRV_NAME, NULL); - - create_proc_read_entry("dma_register", - 0, - g_dma_dir, - dma_register_proc_read, - NULL); - - create_proc_read_entry("g_desc_list", - 0, - g_dma_dir, - desc_list_proc_read, - NULL); - - create_proc_read_entry("channel_weight", - 0, - g_dma_dir, - channel_weight_proc_read, - NULL); - - printk(KERN_NOTICE "SVIP DMA engine initialized\n"); - - return 0; -} - -/** - * Cleanup DMA device - * This function releases all resources used by the DMA device driver on - * module removal. - * - * - * \param None - * \return Nothing - */ -void dma_cleanup(void) -{ - int i; - unregister_chrdev(DMA_MAJOR, "dma-core"); - - for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) - free_page(KSEG0ADDR((unsigned long)g_desc_list[i])); - remove_proc_entry("channel_weight", g_dma_dir); - remove_proc_entry("g_desc_list", g_dma_dir); - remove_proc_entry("dma_register", g_dma_dir); - remove_proc_entry("driver/" DRV_NAME, NULL); - /* release the resources */ - for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) - free_irq(dma_chan[i].irq, (void *)&dma_chan[i]); -} - -arch_initcall(ltq_dma_init); - -MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/gpio.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/gpio.c deleted file mode 100644 index 398339201e..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/gpio.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/gpio.h> -#include <linux/ioport.h> -#include <linux/io.h> -#include <linux/types.h> -#include <linux/errno.h> -#include <linux/proc_fs.h> -#include <linux/init.h> -#include <linux/ioctl.h> -#include <linux/timer.h> -#include <linux/interrupt.h> -#include <linux/kobject.h> -#include <linux/workqueue.h> -#include <linux/skbuff.h> -#include <linux/netlink.h> -#include <linux/platform_device.h> -#include <net/sock.h> -#include <linux/uaccess.h> -#include <linux/version.h> -#include <linux/semaphore.h> - -#include <lantiq_soc.h> -#include <svip_mux.h> -#include <base_reg.h> -#include <port_reg.h> - -#define DRV_NAME "ifxmips_gpio" - -int gpio_to_irq(unsigned int gpio) -{ - return -EINVAL; -} -EXPORT_SYMBOL(gpio_to_irq); - -int irq_to_gpio(unsigned int gpio) -{ - return -EINVAL; -} -EXPORT_SYMBOL(irq_to_gpio); - -struct ltq_port_base { - struct svip_reg_port *base; - u32 pins; -}; - -/* Base addresses for ports */ -static const struct ltq_port_base ltq_port_base[] = { - { (struct svip_reg_port *)LTQ_PORT_P0_BASE, 20 }, - { (struct svip_reg_port *)LTQ_PORT_P1_BASE, 20 }, - { (struct svip_reg_port *)LTQ_PORT_P2_BASE, 19 }, - { (struct svip_reg_port *)LTQ_PORT_P3_BASE, 20 }, - { (struct svip_reg_port *)LTQ_PORT_P4_BASE, 24 } -}; - -#define MAX_PORTS ARRAY_SIZE(ltq_port_base) -#define PINS_PER_PORT(port) (ltq_port_base[port].pins) - -static inline -void ltq_port_set_exintcr0(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->exintcr0) | (1 << pin), - ltq_port_base[port].base->exintcr0); -} - -static inline -void ltq_port_clear_exintcr0(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->exintcr0) & ~(1 << pin), - ltq_port_base[port].base->exintcr0); -} - -static inline -void ltq_port_set_exintcr1(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->exintcr1) | (1 << pin), - ltq_port_base[port].base->exintcr1); -} - -static inline -void ltq_port_clear_exintcr1(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->exintcr1) & ~(1 << pin), - ltq_port_base[port].base->exintcr1); -} - -static inline -void ltq_port_set_irncfg(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->irncfg) | (1 << pin), - ltq_port_base[port].base->irncfg); -} - -static inline -void ltq_port_clear_irncfg(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->irncfg) & ~(1 << pin), - ltq_port_base[port].base->irncfg); -} - -static inline -void ltq_port_set_irnen(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(1 << pin, ltq_port_base[port].base->irnenset); -} - -static inline -void ltq_port_clear_irnen(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(1 << pin, ltq_port_base[port].base->irnenclr); -} - -static inline -void ltq_port_set_dir_out(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->dir) | (1 << pin), - ltq_port_base[port].base->dir); -} - -static inline -void ltq_port_set_dir_in(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->dir) & ~(1 << pin), - ltq_port_base[port].base->dir); -} - -static inline -void ltq_port_set_output(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->out) | (1 << pin), - ltq_port_base[port].base->out); -} - -static inline -void ltq_port_clear_output(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->out) & ~(1 << pin), - ltq_port_base[port].base->out); -} - -static inline -int ltq_port_get_input(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return -EINVAL; - - return (port_r32(ltq_port_base[port].base->in) & (1 << pin)) == 0; -} - -static inline -void ltq_port_set_puen(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->puen) | (1 << pin), - ltq_port_base[port].base->puen); -} - -static inline -void ltq_port_clear_puen(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->puen) & ~(1 << pin), - ltq_port_base[port].base->puen); -} - -static inline -void ltq_port_set_altsel0(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->altsel0) | (1 << pin), - ltq_port_base[port].base->altsel0); -} - -static inline -void ltq_port_clear_altsel0(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->altsel0) & ~(1 << pin), - ltq_port_base[port].base->altsel0); -} - -static inline -void ltq_port_set_altsel1(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->altsel1) | (1 << pin), - ltq_port_base[port].base->altsel1); -} - -static inline -void ltq_port_clear_altsel1(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return; - - port_w32(port_r32(ltq_port_base[port].base->altsel1) & ~(1 << pin), - ltq_port_base[port].base->altsel1); -} - -void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, - bool altsel0, bool altsel1) -{ - if (dirin) - ltq_port_set_dir_in(port, pin); - else - ltq_port_set_dir_out(port, pin); - - if (puen) - ltq_port_set_puen(port, pin); - else - ltq_port_clear_puen(port, pin); - - if (altsel0) - ltq_port_set_altsel0(port, pin); - else - ltq_port_clear_altsel0(port, pin); - - if (altsel1) - ltq_port_set_altsel1(port, pin); - else - ltq_port_clear_altsel1(port, pin); -} - -int ltq_port_get_dir(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return -EINVAL; - - return (port_r32(ltq_port_base[port].base->dir) & (1 << pin)) != 0; -} - -int ltq_port_get_puden(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return -EINVAL; - - return (port_r32(ltq_port_base[port].base->puen) & (1 << pin)) != 0; -} - -int ltq_port_get_altsel0(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return -EINVAL; - - return (port_r32(ltq_port_base[port].base->altsel0) & (1 << pin)) != 0; -} - -int ltq_port_get_altsel1(unsigned int port, unsigned int pin) -{ - if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) - return -EINVAL; - - return (port_r32(ltq_port_base[port].base->altsel1) & (1 << pin)) != 0; -} - -struct ltq_gpio_port { - struct gpio_chip gpio_chip; - unsigned int irq_base; - unsigned int chained_irq; -}; - -static struct ltq_gpio_port ltq_gpio_port[MAX_PORTS]; - -static int gpio_exported; -static int __init gpio_export_setup(char *str) -{ - get_option(&str, &gpio_exported); - return 1; -} -__setup("gpio_exported=", gpio_export_setup); - -static inline unsigned int offset2port(unsigned int offset) -{ - unsigned int i; - unsigned int prev = 0; - - for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { - if (offset >= prev && - offset < prev + ltq_port_base[i].pins) - return i; - - prev = ltq_port_base[i].pins; - } - - return 0; -} - -static inline unsigned int offset2pin(unsigned int offset) -{ - unsigned int i; - unsigned int prev = 0; - - for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { - if (offset >= prev && - offset < prev + ltq_port_base[i].pins) - return offset - prev; - - prev = ltq_port_base[i].pins; - } - - return 0; -} - -static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) -{ - ltq_port_set_dir_in(offset2port(offset), offset2pin(offset)); - return 0; -} - -static int ltq_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - ltq_port_set_dir_out(offset2port(offset), offset2pin(offset)); - return 0; -} - -static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - return ltq_port_get_input(offset2port(offset), offset2pin(offset)); -} - -static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) -{ - if (value) - ltq_port_set_output(offset2port(offset), offset2pin(offset)); - else - ltq_port_clear_output(offset2port(offset), offset2pin(offset)); -} - -static int svip_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - return 0; -} - -static void ltq_gpio_free(struct gpio_chip *chip, unsigned offset) -{ -} - -static int ltq_gpio_probe(struct platform_device *pdev) -{ - int ret = 0; - struct ltq_gpio_port *gpio_port; - - if (pdev->id >= MAX_PORTS) - return -ENODEV; - - gpio_port = <q_gpio_port[pdev->id]; - gpio_port->gpio_chip.label = "ltq-gpio"; - - gpio_port->gpio_chip.direction_input = ltq_gpio_direction_input; - gpio_port->gpio_chip.direction_output = ltq_gpio_direction_output; - gpio_port->gpio_chip.get = ltq_gpio_get; - gpio_port->gpio_chip.set = ltq_gpio_set; - gpio_port->gpio_chip.request = svip_gpio_request; - gpio_port->gpio_chip.free = ltq_gpio_free; - gpio_port->gpio_chip.base = 100 * pdev->id; - gpio_port->gpio_chip.ngpio = 32; - gpio_port->gpio_chip.dev = &pdev->dev; - gpio_port->gpio_chip.exported = gpio_exported; - - ret = gpiochip_add(&gpio_port->gpio_chip); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", - pdev->id, ret); - goto err; - } - platform_set_drvdata(pdev, gpio_port); - - return 0; - -err: - return ret; -} - -static int ltq_gpio_remove(struct platform_device *pdev) -{ - struct ltq_gpio_port *gpio_port = platform_get_drvdata(pdev); - int ret; - - ret = gpiochip_remove(&gpio_port->gpio_chip); - - return ret; -} - -static struct platform_driver ltq_gpio_driver = { - .probe = ltq_gpio_probe, - .remove = __devexit_p(ltq_gpio_remove), - .driver = { - .name = DRV_NAME, - .owner = THIS_MODULE, - }, -}; - -int __init ltq_gpio_init(void) -{ - int ret = platform_driver_register(<q_gpio_driver); - if (ret) - printk(KERN_INFO DRV_NAME - ": Error registering platform driver!"); - return ret; -} - -postcore_initcall(ltq_gpio_init); - -/** - * Convert interrupt number to corresponding port/pin pair - * Returns the port/pin pair serving the selected external interrupt; - * needed since mapping not linear. - * - * \param exint External interrupt number - * \param port Pointer for resulting port - * \param pin Pointer for resutling pin - * \return -EINVAL Invalid exint - * \return 0 port/pin updated - * \ingroup API - */ -static int ltq_exint2port(u32 exint, int *port, int *pin) -{ - if ((exint >= 0) && (exint <= 10)) { - *port = 0; - *pin = exint + 7; - } else if ((exint >= 11) && (exint <= 14)) { - *port = 1; - *pin = 18 - (exint - 11) ; - } else if (exint == 15) { - *port = 1; - *pin = 19; - } else if (exint == 16) { - *port = 0; - *pin = 19; - } else { - return -EINVAL; - } - return 0; -} - -/** - * Enable external interrupt. - * This function enables an external interrupt and sets the given mode. - * valid values for mode are: - * - 0 = Interrupt generation disabled - * - 1 = Interrupt on rising edge - * - 2 = Interrupt on falling edge - * - 3 = Interrupt on rising and falling edge - * - 5 = Interrupt on high level detection - * - 6 = Interrupt on low level detection - * - * \param exint - Number of external interrupt - * \param mode - Trigger mode - * \return 0 on success - * \ingroup API - */ -int ifx_enable_external_int(u32 exint, u32 mode) -{ - int port; - int pin; - - if ((mode < 0) || (mode > 6)) - return -EINVAL; - - if (ltq_exint2port(exint, &port, &pin)) - return -EINVAL; - - ltq_port_clear_exintcr0(port, pin); - ltq_port_clear_exintcr1(port, pin); - ltq_port_clear_irncfg(port, pin); - - if (mode & 0x1) - ltq_port_set_exintcr0(port, pin); - if (mode & 0x2) - ltq_port_set_exintcr1(port, pin); - if (mode & 0x4) - ltq_port_set_irncfg(port, pin); - - ltq_port_set_irnen(port, pin); - return 0; -} -EXPORT_SYMBOL(ifx_enable_external_int); - -/** - * Disable external interrupt. - * This function disables an external interrupt and sets mode to 0x00. - * - * \param exint - Number of external interrupt - * \return 0 on success - * \ingroup API - */ -int ifx_disable_external_int(u32 exint) -{ - int port; - int pin; - - if (ltq_exint2port(exint, &port, &pin)) - return -EINVAL; - - ltq_port_clear_irnen(port, pin); - return 0; -} -EXPORT_SYMBOL(ifx_disable_external_int); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy33016.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy33016.c deleted file mode 100644 index c5993efd6d..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy33016.c +++ /dev/null @@ -1,73 +0,0 @@ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/gpio_buttons.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/input.h> -#include <linux/interrupt.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#include "../machtypes.h" - -#include <sys1_reg.h> -#include <sys2_reg.h> -#include <svip_pms.h> - -#include "devices.h" - -static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { - LTQ_MUX_P0_0_SSC0_MTSR, - LTQ_MUX_P0_1_SSC0_MRST, - LTQ_MUX_P0_2_SSC0_SCLK, - LTQ_MUX_P0_3_SSC1_MTSR, - LTQ_MUX_P0_4_SSC1_MRST, - LTQ_MUX_P0_5_SSC1_SCLK, - LTQ_MUX_P0_6_SSC0_CS0, - LTQ_MUX_P0_7_SSC0_CS1, - LTQ_MUX_P0_8_SSC0_CS2, - LTQ_MUX_P0_9, - LTQ_MUX_P0_10, - LTQ_MUX_P0_11_EXINT4, - LTQ_MUX_P0_12, - LTQ_MUX_P0_13, - LTQ_MUX_P0_14_ASC0_TXD, - LTQ_MUX_P0_15_ASC0_RXD, - LTQ_MUX_P0_16_EXINT9, - LTQ_MUX_P0_17_EXINT10, - LTQ_MUX_P0_18_EJ_BRKIN, - LTQ_MUX_P0_19_EXINT16 -}; - -static void __init easy33016_init(void) -{ - svip_sys1_clk_enable(SYS1_CLKENR_L2C | - SYS1_CLKENR_DDR2 | - SYS1_CLKENR_SMI2 | - SYS1_CLKENR_SMI1 | - SYS1_CLKENR_SMI0 | - SYS1_CLKENR_FMI0 | - SYS1_CLKENR_DMA | - SYS1_CLKENR_SSC0 | - SYS1_CLKENR_SSC1 | - SYS1_CLKENR_EBU); - - svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | - SYS2_CLKENR_MBS | - SYS2_CLKENR_SWINT); - - svip_register_mux(mux_p0, NULL, NULL, NULL, NULL); - svip_register_asc(0); - svip_register_eth(); - svip_register_virtual_eth(); - ltq_register_wdt(); - svip_register_gpio(); - svip_register_spi(); - svip_register_nand(); -} - -MIPS_MACHINE(LANTIQ_MACH_EASY33016, - "EASY33016", - "EASY33016", - easy33016_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy336.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy336.c deleted file mode 100644 index 460bb7d85d..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy336.c +++ /dev/null @@ -1,221 +0,0 @@ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/gpio_buttons.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/input.h> -#include <linux/interrupt.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#include "../machtypes.h" - -#include <sys1_reg.h> -#include <sys2_reg.h> -#include <svip_pms.h> - -#include "devices.h" - -static struct mtd_partition easy336_sflash_partitions[] = { - { - .name = "SPI flash", - .size = MTDPART_SIZ_FULL, - .offset = 0, - }, -}; - -static struct flash_platform_data easy336_sflash_data = { - .name = "m25p32", - .parts = (void *)&easy336_sflash_partitions, - .nr_parts = ARRAY_SIZE(easy336_sflash_partitions), - .type = "m25p32", -}; - -static struct spi_board_info bdinfo[] __initdata = { - { - .modalias = "m25p80", - .platform_data = &easy336_sflash_data, - .mode = SPI_MODE_0, - .irq = -1, - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 0, - } -}; - -static struct mtd_partition easy336_partitions[] = { - { - .name = "uboot", - .offset = 0x0, - .size = 0x40000, - }, - { - .name = "uboot_env", - .offset = 0x40000, - .size = 0x20000, - }, - { - .name = "linux", - .offset = 0x60000, - .size = 0x1a0000, - }, - { - .name = "rootfs", - .offset = 0x200000, - .size = 0x500000, - }, -}; - -static struct physmap_flash_data easy336_flash_data = { - .nr_parts = ARRAY_SIZE(easy336_partitions), - .parts = easy336_partitions, -}; - -static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { - LTQ_MUX_P0_0_SSC0_MTSR, - LTQ_MUX_P0_1_SSC0_MRST, - LTQ_MUX_P0_2_SSC0_SCLK, - LTQ_MUX_P0_3_SSC1_MTSR, - LTQ_MUX_P0_4_SSC1_MRST, - LTQ_MUX_P0_5_SSC1_SCLK, - LTQ_MUX_P0_6_SSC0_CS0, - LTQ_MUX_P0_7_SSC0_CS1, - LTQ_MUX_P0_8_SSC0_CS2, - LTQ_MUX_P0_9_SSC0_CS3, - LTQ_MUX_P0_10_SSC0_CS4, - LTQ_MUX_P0_11_SSC0_CS5, - LTQ_MUX_P0_12_EXINT5, - LTQ_MUX_P0_13_EXINT6, - LTQ_MUX_P0_14_ASC0_TXD, - LTQ_MUX_P0_15_ASC0_RXD, - LTQ_MUX_P0_16_EXINT9, - LTQ_MUX_P0_17_EXINT10, - LTQ_MUX_P0_18_EJ_BRKIN, - LTQ_MUX_P0_19_EXINT16 -}; - -static const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS] = { - LTQ_MUX_P2_0_EBU_A0, - LTQ_MUX_P2_1_EBU_A1, - LTQ_MUX_P2_2_EBU_A2, - LTQ_MUX_P2_3_EBU_A3, - LTQ_MUX_P2_4_EBU_A4, - LTQ_MUX_P2_5_EBU_A5, - LTQ_MUX_P2_6_EBU_A6, - LTQ_MUX_P2_7_EBU_A7, - LTQ_MUX_P2_8_EBU_A8, - LTQ_MUX_P2_9_EBU_A9, - LTQ_MUX_P2_10_EBU_A10, - LTQ_MUX_P2_11_EBU_A11, - LTQ_MUX_P2_12_EBU_RD, - LTQ_MUX_P2_13_EBU_WR, - LTQ_MUX_P2_14_EBU_ALE, - LTQ_MUX_P2_15_EBU_WAIT, - LTQ_MUX_P2_16_EBU_RDBY, - LTQ_MUX_P2_17_EBU_BC0, - LTQ_MUX_P2_18_EBU_BC1 -}; - -static const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS] = { - LTQ_MUX_P3_0_EBU_AD0, - LTQ_MUX_P3_1_EBU_AD1, - LTQ_MUX_P3_2_EBU_AD2, - LTQ_MUX_P3_3_EBU_AD3, - LTQ_MUX_P3_4_EBU_AD4, - LTQ_MUX_P3_5_EBU_AD5, - LTQ_MUX_P3_6_EBU_AD6, - LTQ_MUX_P3_7_EBU_AD7, - LTQ_MUX_P3_8_EBU_AD8, - LTQ_MUX_P3_9_EBU_AD9, - LTQ_MUX_P3_10_EBU_AD10, - LTQ_MUX_P3_11_EBU_AD11, - LTQ_MUX_P3_12_EBU_AD12, - LTQ_MUX_P3_13_EBU_AD13, - LTQ_MUX_P3_14_EBU_AD14, - LTQ_MUX_P3_15_EBU_AD15, - LTQ_MUX_P3_16_EBU_CS0, - LTQ_MUX_P3_17_EBU_CS1, - LTQ_MUX_P3_18_EBU_CS2, - LTQ_MUX_P3_19_EBU_CS3 -}; - -static void __init easy336_init_common(void) -{ - svip_sys1_clk_enable(SYS1_CLKENR_L2C | - SYS1_CLKENR_DDR2 | - SYS1_CLKENR_SMI2 | - SYS1_CLKENR_SMI1 | - SYS1_CLKENR_SMI0 | - SYS1_CLKENR_FMI0 | - SYS1_CLKENR_DMA | - SYS1_CLKENR_GPTC | - SYS1_CLKENR_EBU); - - svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | - SYS2_CLKENR_MBS | - SYS2_CLKENR_SWINT | - SYS2_CLKENR_HWACC3 | - SYS2_CLKENR_HWACC2 | - SYS2_CLKENR_HWACC1 | - SYS2_CLKENR_HWACC0 | - SYS2_CLKENR_SIF7 | - SYS2_CLKENR_SIF6 | - SYS2_CLKENR_SIF5 | - SYS2_CLKENR_SIF4 | - SYS2_CLKENR_SIF3 | - SYS2_CLKENR_SIF2 | - SYS2_CLKENR_SIF1 | - SYS2_CLKENR_SIF0 | - SYS2_CLKENR_DFEV7 | - SYS2_CLKENR_DFEV6 | - SYS2_CLKENR_DFEV5 | - SYS2_CLKENR_DFEV4 | - SYS2_CLKENR_DFEV3 | - SYS2_CLKENR_DFEV2 | - SYS2_CLKENR_DFEV1 | - SYS2_CLKENR_DFEV0); - - svip_register_mux(mux_p0, NULL, mux_p2, mux_p3, NULL); - svip_register_asc(0); - svip_register_eth(); - svip_register_virtual_eth(); - /* ltq_register_wdt(); - conflicts with lq_switch */ - svip_register_gpio(); - svip_register_spi(); - ltq_register_tapi(); -} - -static void __init easy336_init(void) -{ - easy336_init_common(); - ltq_register_nor(&easy336_flash_data); -} - -static void __init easy336sf_init(void) -{ - easy336_init_common(); - svip_register_spi_flash(bdinfo); -} - -static void __init easy336nand_init(void) -{ - easy336_init_common(); - svip_register_nand(); -} - -MIPS_MACHINE(LANTIQ_MACH_EASY336, - "EASY336", - "EASY336", - easy336_init); - -MIPS_MACHINE(LANTIQ_MACH_EASY336SF, - "EASY336SF", - "EASY336 (Serial Flash)", - easy336sf_init); - -MIPS_MACHINE(LANTIQ_MACH_EASY336NAND, - "EASY336NAND", - "EASY336 (NAND Flash)", - easy336nand_init); - diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/mux.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/mux.c deleted file mode 100644 index 56805e55bb..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/mux.c +++ /dev/null @@ -1,187 +0,0 @@ -/************************************************************************ - * - * Copyright (c) 2007 - * Infineon Technologies AG - * St. Martin Strasse 53; 81669 Muenchen; Germany - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - ************************************************************************/ - -#include <linux/module.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/proc_fs.h> -#include <linux/init.h> -#include <asm/addrspace.h> -#include <linux/platform_device.h> - -#include <lantiq_soc.h> -#include <svip_mux.h> -#include <sys1_reg.h> -#include <sys2_reg.h> -#include <svip_pms.h> - -#define DRV_NAME "ltq_mux" - -static void ltq_mux_port_init(const int port, - const struct ltq_mux_pin *pins, - const int pin_max) -{ - unsigned int i; - - for (i = 0; i < pin_max; i++) - ltq_gpio_configure(port, - i, - pins[i].dirin, - pins[i].puen, - pins[i].altsel0, - pins[i].altsel1); -} - -static int ltq_mux_probe(struct platform_device *pdev) -{ - struct ltq_mux_settings *mux_settings = dev_get_platdata(&pdev->dev); - - if (mux_settings->mux_p0) - ltq_mux_port_init(0, - mux_settings->mux_p0, - LTQ_MUX_P0_PINS); - - if (mux_settings->mux_p1) - ltq_mux_port_init(1, - mux_settings->mux_p1, - LTQ_MUX_P1_PINS); - - if (mux_settings->mux_p2) - ltq_mux_port_init(2, - mux_settings->mux_p2, - LTQ_MUX_P2_PINS); - - if (mux_settings->mux_p3) - ltq_mux_port_init(3, - mux_settings->mux_p3, - LTQ_MUX_P3_PINS); - - if (mux_settings->mux_p4) - ltq_mux_port_init(4, - mux_settings->mux_p4, - LTQ_MUX_P4_PINS); - - return 0; -} - -int ltq_mux_read_procmem(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int len = 0; - int t = 0, i = 0; - u32 port_clk[5] = { - SYS1_CLKENR_PORT0, - SYS1_CLKENR_PORT1, - SYS1_CLKENR_PORT2, - SYS1_CLKENR_PORT3, - SYS2_CLKENR_PORT4, - }; - -#define PROC_PRINT(fmt, args...) \ - do { \ - int c_len = 0; \ - c_len = snprintf(buf + len, count - len, fmt, ## args); \ - if (c_len <= 0) \ - goto out; \ - if (c_len >= (count - len)) { \ - len += (count - len); \ - goto out; \ - } \ - len += c_len; \ - if (offset > 0) { \ - if (len > offset) { \ - len -= offset; \ - memmove(buf, buf + offset, len); \ - offset = 0; \ - } else { \ - offset -= len; \ - len = 0; \ - } \ - } \ - } while (0) - - PROC_PRINT("\nVINETIC-SVIP Multiplex Settings\n"); - PROC_PRINT(" 3 2 1 0\n"); - PROC_PRINT(" 10987654321098765432109876543210\n"); - PROC_PRINT(" --------------------------------\n"); - - for (i = 0; i < ARRAY_SIZE(port_clk); i++) { - if (i < 4) { - if (!svip_sys1_clk_is_enabled(port_clk[i])) - continue; - } else { - if (!svip_sys2_clk_is_enabled(port_clk[i])) - continue; - } - - PROC_PRINT("P%d.%-10s", i, "DIR:"); - - for (t = 31; t != -1; t--) - PROC_PRINT("%d", ltq_port_get_dir(i, t) == 1 ? 1 : 0); - PROC_PRINT("\n"); - - PROC_PRINT("P%d.%-10s", i, "PUEN:"); - for (t = 31; t != -1; t--) - PROC_PRINT("%d", ltq_port_get_puden(i, t) == 1 ? 1 : 0); - PROC_PRINT("\n"); - - PROC_PRINT("P%d.%-10s", i, "ALTSEL0:"); - for (t = 31; t != -1; t--) - PROC_PRINT("%d", - ltq_port_get_altsel0(i, t) == 1 ? 1 : 0); - PROC_PRINT("\n"); - - PROC_PRINT("P%d.%-10s", i, "ALTSEL1:"); - for (t = 31; t != -1; t--) - PROC_PRINT("%d", - ltq_port_get_altsel1(i, t) == 1 ? 1 : 0); - PROC_PRINT("\n\n"); - } - -out: - if (len < 0) { - len = 0; - *eof = 1; - } else if (len < count) { - *eof = 1; - } else { - len = count; - } - - *start = buf; - - return len; -} - -static struct platform_driver ltq_mux_driver = { - .probe = ltq_mux_probe, - .driver = { - .name = DRV_NAME, - .owner = THIS_MODULE, - }, -}; - -int __init ltq_mux_init(void) -{ - int ret = platform_driver_register(<q_mux_driver); - if (ret) { - printk(KERN_INFO DRV_NAME - ": Error registering platform driver!"); - return ret; - } - - return create_proc_read_entry("driver/ltq_mux", 0, NULL, - ltq_mux_read_procmem, NULL) == NULL; -} - -module_init(ltq_mux_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/pms.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/pms.c deleted file mode 100644 index 5c0c808a04..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/pms.c +++ /dev/null @@ -1,101 +0,0 @@ -/************************************************************************ - * - * Copyright (c) 2007 - * Infineon Technologies AG - * St. Martin Strasse 53; 81669 Muenchen; Germany - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - ************************************************************************/ - -#include <linux/module.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/proc_fs.h> -#include <linux/init.h> -#include <asm/addrspace.h> - -#include <base_reg.h> -#include <sys1_reg.h> -#include <sys2_reg.h> -#include <lantiq_soc.h> - -static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; -static struct svip_reg_sys2 *const sys2 = (struct svip_reg_sys2 *)LTQ_SYS2_BASE; - -void svip_sys1_clk_enable(u32 mask) -{ - sys1_w32(sys1_r32(clksr) | mask, clkenr); - asm("sync;"); -} -EXPORT_SYMBOL(svip_sys1_clk_enable); - -int svip_sys1_clk_is_enabled(u32 mask) -{ - return (sys1_r32(clksr) & mask) != 0; -} -EXPORT_SYMBOL(svip_sys1_clk_is_enabled); - -void svip_sys2_clk_enable(u32 mask) -{ - sys2_w32(sys2_r32(clksr) | mask, clkenr); - asm("sync;"); -} -EXPORT_SYMBOL(svip_sys2_clk_enable); - -int svip_sys2_clk_is_enabled(u32 mask) -{ - return (sys2_r32(clksr) & mask) != 0; -} -EXPORT_SYMBOL(svip_sys2_clk_is_enabled); - -int ltq_pms_read_procmem(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - long len = 0; - int t = 0; - u32 bit = 0; - u32 reg_tmp, bits_tmp; - - len = sprintf(buf, "\nSVIP PMS Settings\n"); - len = len + sprintf(buf + len, - " 3 2 1 0\n"); - len = len + sprintf(buf + len, - " 210987654321098765432109876543210\n"); - len = len + sprintf(buf + len, - "---------------------------------------------\n"); - len = len + sprintf(buf + len, - "SYS1_CLKSR: "); - reg_tmp = sys1_r32(clksr); - bit = 0x80000000; - for (t = 31; t != -1; t--) { - bits_tmp = (reg_tmp & bit) >> t; - len = len + sprintf(buf + len, "%d", bits_tmp); - bit = bit >> 1; - } - len = len + sprintf(buf + len, "\n\n"); - len = len + sprintf(buf + len, "SYS2_CLKSR: "); - reg_tmp = sys2_r32(clksr); - bit = 0x80000000; - for (t = 31; t != -1; t--) { - bits_tmp = (reg_tmp & bit) >> t; - len = len + sprintf(buf + len, "%d", bits_tmp); - bit = bit >> 1; - } - len = len + sprintf(buf + len, "\n\n"); - - *eof = 1; - - return len; -} - -int __init ltq_pms_init_proc(void) -{ - return create_proc_read_entry("driver/ltq_pms", 0, NULL, - ltq_pms_read_procmem, NULL) == NULL; -} - -module_init(ltq_pms_init_proc); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/prom.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/prom.c deleted file mode 100644 index 1c17531606..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/prom.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/module.h> -#include <linux/clk.h> -#include <linux/time.h> -#include <asm/bootinfo.h> - -#include <lantiq_soc.h> - -#include "../prom.h" -#include "../clk.h" -#include "../machtypes.h" - -#include <base_reg.h> -#include <ebu_reg.h> - -#define SOC_SVIP "SVIP" - -#define PART_SHIFT 12 -#define PART_MASK 0x0FFFF000 -#define REV_SHIFT 28 -#define REV_MASK 0xF0000000 - -static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; - -void __init ltq_soc_init(void) -{ - clkdev_add_static(ltq_svip_cpu_hz(), ltq_svip_fpi_hz(), - ltq_svip_io_region_clock()); -} - -void __init -ltq_soc_setup(void) -{ - if (mips_machtype == LANTIQ_MACH_EASY33016 || - mips_machtype == LANTIQ_MACH_EASY336) { - ebu_w32(0x120000f1, addr_sel_2); - ebu_w32(LTQ_EBU_CON_0_ADSWP | - LTQ_EBU_CON_0_SETUP | - LTQ_EBU_CON_0_BCGEN_VAL(0x02) | - LTQ_EBU_CON_0_WAITWRC_VAL(7) | - LTQ_EBU_CON_0_WAITRDC_VAL(3) | - LTQ_EBU_CON_0_HOLDC_VAL(3) | - LTQ_EBU_CON_0_RECOVC_VAL(3) | - LTQ_EBU_CON_0_CMULT_VAL(3), con_2); - } -} - -void __init -ltq_soc_detect(struct ltq_soc_info *i) -{ - i->partnum = (ltq_r32(LTQ_STATUS_CHIPID) & PART_MASK) >> PART_SHIFT; - i->rev = (ltq_r32(LTQ_STATUS_CHIPID) & REV_MASK) >> REV_SHIFT; - sprintf(i->rev_type, "1.%d", i->rev); - switch (i->partnum) { - case SOC_ID_SVIP: - i->name = SOC_SVIP; - i->type = SOC_TYPE_SVIP; - break; - - default: - printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum); - while (1); - break; - } -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/reset.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/reset.c deleted file mode 100644 index 5551875da6..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/reset.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/pm.h> -#include <linux/module.h> -#include <asm/reboot.h> - -#include <lantiq_soc.h> -#include "../machtypes.h" -#include <base_reg.h> -#include <sys1_reg.h> -#include <boot_reg.h> -#include <ebu_reg.h> - -static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; -static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; - -#define CPLD_CMDREG3 ((volatile unsigned char*)(KSEG1 + 0x120000f3)) -extern void switchip_reset(void); - -static void ltq_machine_restart(char *command) -{ - printk(KERN_NOTICE "System restart\n"); - local_irq_disable(); - - if (mips_machtype == LANTIQ_MACH_EASY33016 || - mips_machtype == LANTIQ_MACH_EASY336) { - /* We just use the CPLD function to reset the entire system as a - workaround for the switch reset problem */ - local_irq_disable(); - ebu_w32(0x120000f1, addr_sel_2); - ebu_w32(0x404027ff, con_2); - - if (mips_machtype == LANTIQ_MACH_EASY336) - /* set bit 0 to reset SVIP */ - *CPLD_CMDREG3 = (1<<0); - else - /* set bit 7 to reset SVIP, set bit 3 to reset xT */ - *CPLD_CMDREG3 = (1<<7) | (1<<3); - } else { - *LTQ_BOOT_RVEC(0) = 0; - /* reset all except PER, SUBSYS and CPU0 */ - sys1_w32(0x00043F3E, rreqr); - /* release WDT0 reset */ - sys1_w32(0x00000100, rrlsr); - /* restore reset value for clock enables */ - sys1_w32(~0x0c000040, clkclr); - /* reset SUBSYS (incl. DDR2) and CPU0 */ - sys1_w32(0x00030001, rbtr); - } - - for (;;) - ; -} - -static void ltq_machine_halt(void) -{ - printk(KERN_NOTICE "System halted.\n"); - local_irq_disable(); - for (;;) - ; -} - -static void ltq_machine_power_off(void) -{ - printk(KERN_NOTICE "Please turn off the power now.\n"); - local_irq_disable(); - for (;;) - ; -} - -/* This function is used by the watchdog driver */ -int ltq_reset_cause(void) -{ - return 0; -} -EXPORT_SYMBOL_GPL(ltq_reset_cause); - -static int __init mips_reboot_setup(void) -{ - _machine_restart = ltq_machine_restart; - _machine_halt = ltq_machine_halt; - pm_power_off = ltq_machine_power_off; - return 0; -} - -arch_initcall(mips_reboot_setup); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/switchip_setup.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/switchip_setup.c deleted file mode 100644 index 5da15327ea..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/svip/switchip_setup.c +++ /dev/null @@ -1,666 +0,0 @@ -/****************************************************************************** - Copyright (c) 2007, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. - ****************************************************************************** - Module : switchip_setup.c - Date : 2007-11-09 - Description : Basic setup of embedded ethernet switch "SwitchIP" - Remarks: andreas.schmidt@infineon.com - - *****************************************************************************/ - -/* TODO: get rid of #ifdef CONFIG_LANTIQ_MACH_EASY336 */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/version.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/workqueue.h> -#include <linux/time.h> - -#include <base_reg.h> -#include <es_reg.h> -#include <sys1_reg.h> -#include <dma_reg.h> -#include <lantiq_soc.h> - -static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; -static struct svip_reg_es *const es = (struct svip_reg_es *)LTQ_ES_BASE; - -/* PHY Organizationally Unique Identifier (OUI) */ -#define PHY_OUI_PMC 0x00E004 -#define PHY_OUI_VITESSE 0x008083 -#define PHY_OUI_DEFAULT 0xFFFFFF - -unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr); -void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, - unsigned short data); - -static int phy_address[2] = {0, 1}; -static u32 phy_oui; -static void switchip_mdio_poll_init(void); -static void _switchip_mdio_poll(struct work_struct *work); - -/* struct workqueue_struct mdio_poll_task; */ -static struct workqueue_struct *mdio_poll_workqueue; -DECLARE_DELAYED_WORK(mdio_poll_work, _switchip_mdio_poll); -static int old_link_status[2] = {-1, -1}; - -/** - * Autonegotiation check. - * This funtion checks for link changes. If a link change has occured it will - * update certain switch registers. - */ -static void _switchip_check_phy_status(int port) -{ - int new_link_status; - unsigned short reg1; - - reg1 = switchip_phy_read(phy_address[port], 1); - if ((reg1 == 0xFFFF) || (reg1 == 0x0000)) - return; /* no PHY connected */ - - new_link_status = reg1 & 4; - if (old_link_status[port] ^ new_link_status) { - /* link status change */ - if (!new_link_status) { - if (port == 0) - es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p0_ctl); - else - es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p1_ctl); - - /* read again; link bit is latched low! */ - reg1 = switchip_phy_read(phy_address[port], 1); - new_link_status = reg1 & 4; - } - - if (new_link_status) { - unsigned short reg0, reg4, reg5, reg9, reg10; - int phy_pause, phy_speed, phy_duplex; - int aneg_enable, aneg_cmpt; - - reg0 = switchip_phy_read(phy_address[port], 0); - reg4 = switchip_phy_read(phy_address[port], 4); - aneg_enable = reg0 & 0x1000; - aneg_cmpt = reg1 & 0x20; - - if (aneg_enable && aneg_cmpt) { - reg5 = switchip_phy_read(phy_address[port], 5); - switch (phy_oui) { -#ifdef CONFIG_LANTIQ_MACH_EASY336 - case PHY_OUI_PMC: - /* PMC Sierra supports 1Gigabit FD, - * only. On successful - * auto-negotiation, we are sure this - * is what the LP can. */ - phy_pause = ((reg4 & reg5) & 0x0080) >> 7; - phy_speed = 2; - phy_duplex = 1; - break; -#endif - case PHY_OUI_VITESSE: - case PHY_OUI_DEFAULT: - reg9 = switchip_phy_read(phy_address[port], 9); - reg10 = switchip_phy_read(phy_address[port], 10); - - /* Check if advertise and partner - * agree on pause */ - phy_pause = ((reg4 & reg5) & 0x0400) >> 10; - - /* Find the best mode both partners - * support - * Priority: 1GB-FD, 1GB-HD, 100MB-FD, - * 100MB-HD, 10MB-FD, 10MB-HD */ - phy_speed = ((((reg9<<2) & reg10) - & 0x0c00) >> 6) | - (((reg4 & reg5) & 0x01e0) >> 5); - - if (phy_speed >= 0x0020) { - phy_speed = 2; - phy_duplex = 1; - } else if (phy_speed >= 0x0010) { - phy_speed = 2; - phy_duplex = 0; - } else if (phy_speed >= 0x0008) { - phy_speed = 1; - phy_duplex = 1; - } else if (phy_speed >= 0x0004) { - phy_speed = 1; - phy_duplex = 0; - } else if (phy_speed >= 0x0002) { - phy_speed = 0; - phy_duplex = 1; - } else { - phy_speed = 0; - phy_duplex = 0; - } - break; - default: - phy_pause = (reg4 & 0x0400) >> 10; - phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); - phy_duplex = (reg0 >> 8)&1; - break; - } - } else { - /* parallel detection or fixed speed */ - phy_pause = (reg4 & 0x0400) >> 10; - phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); - phy_duplex = (reg0 >> 8)&1; - } - - if (port == 0) { - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0SPD, - LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(phy_speed), - rgmii_ctl); - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0DUP, - LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(phy_duplex), - rgmii_ctl); - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0FCE, - LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), - rgmii_ctl); - - es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); - } else { - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1SPD, - LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(phy_speed), - rgmii_ctl); - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1DUP, - LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(phy_duplex), - rgmii_ctl); - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1FCE, - LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), - rgmii_ctl); - - es_w32_mask(1, LTQ_ES_P0_CTL_REG_FLP, p1_ctl); - } - } - } - old_link_status[port] = new_link_status; -} - -static void _switchip_mdio_poll(struct work_struct *work) -{ - if (es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) { - _switchip_check_phy_status(0); - _switchip_check_phy_status(1); - } - - queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); -} - -static void switchip_mdio_poll_init(void) -{ - mdio_poll_workqueue = create_workqueue("SVIP MDIP poll"); - INIT_DELAYED_WORK(&mdio_poll_work, _switchip_mdio_poll); - - queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); - -} - -unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr) -{ - /* TODO: protect MDIO access with semaphore */ - es_w32(LTQ_ES_MDIO_CTL_REG_MBUSY - | LTQ_ES_MDIO_CTL_REG_OP_VAL(2) /* read operation */ - | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) - | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); - while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); - - return es_r32(mdio_data) & 0xFFFF; -} -EXPORT_SYMBOL(switchip_phy_read); - -void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, - unsigned short data) -{ - /* TODO: protect MDIO access with semaphore */ - es_w32(LTQ_ES_MDIO_CTL_REG_WD_VAL(data) - | LTQ_ES_MDIO_CTL_REG_MBUSY - | LTQ_ES_MDIO_CTL_REG_OP_VAL(1) /* write operation */ - | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) - | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); - while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); - - return; -} -EXPORT_SYMBOL(switchip_phy_write); - -const static u32 switch_reset_offset_000[] = { - /*b8000000:*/ 0xffffffff, 0x00000001, 0x00000001, 0x00000003, - /*b8000010:*/ 0x04070001, 0x04070001, 0x04070001, 0xffffffff, - /*b8000020:*/ 0x00001be8, 0x00001be8, 0x00001be8, 0xffffffff, - /*b8000030:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, - /*b8000040:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, - /*b8000050:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, - /*b8000060:*/ 0x00000000, 0x00000000, 0x00081000, 0x001f7777, - /*b8000070:*/ 0x00000000, 0x00000000, 0x0c00ac2b, 0x0000fa50, - /*b8000080:*/ 0x00001000, 0x00001800, 0x00000000, 0x00000000, - /*b8000090:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b80000a0:*/ 0x00000000, 0x00000050, 0x00000010, 0x00000000, - /*b80000b0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b80000c0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b80000d0:*/ 0xffffffff, 0x00000000, 0x00000000 -}; -const static u32 switch_reset_offset_100[] = { - /*b8000100:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b8000110:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b8000120:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b8000130:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b8000140:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b8000150:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b8000160:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b8000170:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b8000180:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b8000190:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b80001a0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /*b80001b0:*/ 0x00000000, 0x00000000 -}; - -/* - * Switch Reset. - */ -void switchip_reset(void) -{ - volatile unsigned int *reg; - volatile unsigned int rdreg; - int i; - - sys1_w32(SYS1_CLKENR_ETHSW, clkenr); - asm("sync"); - - /* disable P0 */ - es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p0_ctl); - /* disable P1 */ - es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p1_ctl); - /* disable P2 */ - es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p2_ctl); - - /************************************** - * BEGIN: Procedure to clear MAC table - **************************************/ - for (i = 0; i < 3; i++) { - int result; - - /* check if access engine is available */ - while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); - - /* initialise to first address */ - es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(3) - | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(0), adr_tb_ctl2); - - /* wait while busy */ - while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); - - /* setup the portmap */ - es_w32_mask(0, LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1 << i), - adr_tb_ctl1); - - do { - /* search for addresses by port */ - es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(2) - | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(9), adr_tb_ctl2); - - /* wait while busy */ - while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); - - result = LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(es_r32(adr_tb_st2)); - if (result == 0x101) { - printk(KERN_ERR "%s, cmd error\n", __func__); - return; - } - /* if Command OK, address found... */ - if (result == 0) { - unsigned char mac[6]; - - mac[5] = (es_r32(adr_tb_st0) >> 0) & 0xff; - mac[4] = (es_r32(adr_tb_st0) >> 8) & 0xff; - mac[3] = (es_r32(adr_tb_st0) >> 16) & 0xff; - mac[2] = (es_r32(adr_tb_st0) >> 24) & 0xff; - mac[1] = (es_r32(adr_tb_st1) >> 0) & 0xff; - mac[0] = (es_r32(adr_tb_st1) >> 8) & 0xff; - - /* setup address */ - es_w32((mac[5] << 0) | - (mac[4] << 8) | - (mac[3] << 16) | - (mac[2] << 24), adr_tb_ctl0); - es_w32(LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1<<i) | - LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(0) | - (mac[0] << 8) | - (mac[1] << 0), adr_tb_ctl1); - /* erase address */ - - es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(1) | - LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(15), - adr_tb_ctl2); - - /* wait, while busy */ - while (es_r32(adr_tb_st2) & - LTQ_ES_ADR_TB_ST2_REG_BUSY); - } - } while (result == 0); - } - /************************************** - * END: Procedure to clear MAC table - **************************************/ - - /* reset RMON counters */ - es_w32(LTQ_ES_RMON_CTL_REG_BAS | LTQ_ES_RMON_CTL_REG_CAC_VAL(3), - rmon_ctl); - - /* bring all registers to reset state */ - reg = LTQ_ES_PS_REG; - for (i = 0; i < ARRAY_SIZE(switch_reset_offset_000); i++) { - if ((reg == LTQ_ES_PS_REG) || - (reg >= LTQ_ES_ADR_TB_CTL0_REG && - reg <= LTQ_ES_ADR_TB_ST2_REG)) - continue; - - if (switch_reset_offset_000[i] != 0xFFFFFFFF) { - /* write reset value to register */ - *reg = switch_reset_offset_000[i]; - /* read register value back */ - rdreg = *reg; - if (reg == LTQ_ES_SW_GCTL1_REG) - rdreg &= ~LTQ_ES_SW_GCTL1_REG_BISTDN; - /* compare read value with written one */ - if (rdreg != switch_reset_offset_000[i]) { - printk(KERN_ERR "%s,%d: reg %08x mismatch " - "[has:%08x, expect:%08x]\n", - __func__, __LINE__, - (unsigned int)reg, rdreg, - switch_reset_offset_000[i]); - } - } - reg++; - } - - reg = LTQ_ES_VLAN_FLT0_REG; - for (i = 0; i < ARRAY_SIZE(switch_reset_offset_100); i++) { - *reg = switch_reset_offset_100[i]; - rdreg = *reg; - if (rdreg != switch_reset_offset_100[i]) { - printk(KERN_ERR "%s,%d: reg %08x mismatch " - "[has:%08x, expect:%08x]\n", __func__, __LINE__, - (unsigned int)reg, rdreg, - switch_reset_offset_100[i]); - } - reg++; - } -} -EXPORT_SYMBOL(switchip_reset); - -static u32 get_phy_oui(unsigned char phy_addr) -{ - u32 oui; - int i, bit, byte, shift, w; - u16 reg_id[2]; - - /* read PHY identifier registers 1 and 2 */ - reg_id[0] = switchip_phy_read(phy_addr, 2); - reg_id[1] = switchip_phy_read(phy_addr, 3); - - oui = 0; - w = 1; - shift = 7; - byte = 1; - for (i = 0, bit = 10; i <= 21; i++, bit++) { - oui |= ((reg_id[w] & (1<<bit)) ? 1 : 0) << shift; - if (!(shift % 8)) { - byte++; - if (byte == 2) - shift = 15; - else - shift = 21; - } else { - shift--; - } - if (w == 1 && bit == 15) { - bit = -1; - w = 0; - } - } - return oui; -} - -/* - * Switch Initialization. - */ -int switchip_init(void) -{ - int eth_port, phy_present = 0; - u16 reg, mode; - - sys1_w32(SYS1_CLKENR_ETHSW, clkenr); - asm("sync"); - - /* Enable Switch, if not already done so */ - if ((es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) == 0) - es_w32_mask(0, LTQ_ES_SW_GCTL0_REG_SE, sw_gctl0); - /* Wait for completion of MBIST */ - while (LTQ_ES_SW_GCTL1_REG_BISTDN_GET(es_r32(sw_gctl1)) == 0); - - switchip_reset(); - - mode = LTQ_ES_RGMII_CTL_REG_IS_GET(es_r32(rgmii_ctl)); - eth_port = (mode == 2 ? 1 : 0); - - /* Set the primary port(port toward backplane) as sniffer port, - changing from P2 which is the reset setting */ - es_w32_mask(LTQ_ES_SW_GCTL0_REG_SNIFFPN, - LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(eth_port), - sw_gctl0); - - /* Point MDIO state machine to invalid PHY addresses 8 and 9 */ - es_w32_mask(0, LTQ_ES_SW_GCTL0_REG_PHYBA, sw_gctl0); - - /* Add CRC for packets from DMA to PMAC. - Remove CRC for packets from PMAC to DMA. */ - es_w32(LTQ_ES_PMAC_HD_CTL_RC | LTQ_ES_PMAC_HD_CTL_AC, pmac_hd_ctl); - - phy_oui = get_phy_oui(0); - switch (phy_oui) { -#ifdef CONFIG_LANTIQ_MACH_EASY336 - case PHY_OUI_PMC: - phy_address[0] = (mode == 2 ? -1 : 2); - phy_address[1] = (mode == 2 ? 2 : -1); - break; -#endif - case PHY_OUI_VITESSE: - default: - phy_oui = PHY_OUI_DEFAULT; - phy_address[0] = (mode == 2 ? 1 : 0); - phy_address[1] = (mode == 2 ? 0 : 1); - break; - } - - /****** PORT 0 *****/ - reg = switchip_phy_read(phy_address[0], 1); - if ((reg != 0x0000) && (reg != 0xffff)) { - /* PHY connected? */ - phy_present |= 1; - /* Set Rx- and TxDelay in case of RGMII */ - switch (mode) { - case 0: /* *RGMII,RGMII */ - case 2: /* RGMII,*GMII */ - /* program clock delay in PHY, not in SVIP */ - - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0RDLY, 0, rgmii_ctl); - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0TDLY, 0, rgmii_ctl); - if (phy_oui == PHY_OUI_VITESSE || - phy_oui == PHY_OUI_DEFAULT) { - switchip_phy_write(phy_address[0], 31, 0x0001); - switchip_phy_write(phy_address[0], 28, 0xA000); - switchip_phy_write(phy_address[0], 31, 0x0000); - } - default: - break; - } - if (phy_oui == PHY_OUI_VITESSE || - phy_oui == PHY_OUI_DEFAULT) { - /* Program PHY advertisements and - * restart auto-negotiation */ - switchip_phy_write(phy_address[0], 4, 0x05E1); - switchip_phy_write(phy_address[0], 9, 0x0300); - switchip_phy_write(phy_address[0], 0, 0x3300); - } else { - reg = switchip_phy_read(phy_address[1], 0); - reg |= 0x1000; /* auto-negotiation enable */ - switchip_phy_write(phy_address[1], 0, reg); - reg |= 0x0200; /* auto-negotiation restart */ - switchip_phy_write(phy_address[1], 0, reg); - } - } else { - /* Force SWITCH link with highest capability: - * 100M FD for MII - * 1G FD for GMII/RGMII - */ - switch (mode) { - case 1: /* *MII,MII */ - case 3: /* *MII,RGMII */ - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(1), - rgmii_ctl); - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(1), - rgmii_ctl); - break; - case 0: /* *RGMII,RGMII */ - case 2: /* RGMII,*GMII */ - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(2), - rgmii_ctl); - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(1), - rgmii_ctl); - - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0RDLY, 0, rgmii_ctl); - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(2), - rgmii_ctl); - break; - } - - es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); - } - - /****** PORT 1 *****/ - reg = switchip_phy_read(phy_address[1], 1); - if ((reg != 0x0000) && (reg != 0xffff)) { - /* PHY connected? */ - phy_present |= 2; - /* Set Rx- and TxDelay in case of RGMII */ - switch (mode) { - case 0: /* *RGMII,RGMII */ - case 3: /* *MII,RGMII */ - /* program clock delay in PHY, not in SVIP */ - - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1RDLY, 0, rgmii_ctl); - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1TDLY, 0, rgmii_ctl); - if (phy_oui == PHY_OUI_VITESSE || - phy_oui == PHY_OUI_DEFAULT) { - switchip_phy_write(phy_address[1], 31, 0x0001); - switchip_phy_write(phy_address[1], 28, 0xA000); - switchip_phy_write(phy_address[1], 31, 0x0000); - } - break; - case 2: /* RGMII,*GMII */ - - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2), - rgmii_ctl); - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); -#ifdef CONFIG_LANTIQ_MACH_EASY336 - if (phy_oui == PHY_OUI_PMC) { - switchip_phy_write(phy_address[1], 24, 0x0510); - switchip_phy_write(phy_address[1], 17, 0xA38C); - switchip_phy_write(phy_address[1], 17, 0xA384); - } -#endif - break; - default: - break; - } - /* Program PHY advertisements and restart auto-negotiation */ - if (phy_oui == PHY_OUI_VITESSE || - phy_oui == PHY_OUI_DEFAULT) { - switchip_phy_write(phy_address[1], 4, 0x05E1); - switchip_phy_write(phy_address[1], 9, 0x0300); - switchip_phy_write(phy_address[1], 0, 0x3300); - } else { - reg = switchip_phy_read(phy_address[1], 0); - reg |= 0x1000; /* auto-negotiation enable */ - switchip_phy_write(phy_address[1], 0, reg); - reg |= 0x0200; /* auto-negotiation restart */ - switchip_phy_write(phy_address[1], 0, reg); - } - } else { - /* Force SWITCH link with highest capability: - * 100M FD for MII - * 1G FD for GMII/RGMII - */ - switch (mode) { - case 1: /* *MII,MII */ - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(1), - rgmii_ctl); - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); - break; - case 0: /* *RGMII,RGMII */ - case 3: /* *MII,RGMII */ - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2), - rgmii_ctl); - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); - es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1RDLY, 0, rgmii_ctl); - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(2), - rgmii_ctl); - break; - case 2: /* RGMII,*GMII */ - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2), - rgmii_ctl); - es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); - break; - } - es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); - } - - /* - * Allow unknown unicast/multicast and broadcasts - * on all ports. - */ - - es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_UP_VAL(7), sw_gctl1); - es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_BP_VAL(7), sw_gctl1); - es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_MP_VAL(7), sw_gctl1); - es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_RP_VAL(7), sw_gctl1); - - /* Enable LAN port(s) */ - if (eth_port == 0) - es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p0_ctl); - else - es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p1_ctl); - /* Enable CPU Port (Forwarding State) */ - es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p2_ctl); - - if (phy_present) - switchip_mdio_poll_init(); - - return 0; -} -EXPORT_SYMBOL(switchip_init); - -device_initcall(switchip_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/clk.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/clk.c deleted file mode 100644 index 5d850dc7b3..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/clk.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/io.h> -#include <linux/export.h> -#include <linux/init.h> -#include <linux/clk.h> - -#include <asm/time.h> -#include <asm/irq.h> -#include <asm/div64.h> - -#include <lantiq_soc.h> - -#include "../clk.h" - -static unsigned int ltq_ram_clocks[] = { - CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; -#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] - -#define BASIC_FREQUENCY_1 35328000 -#define BASIC_FREQUENCY_2 36000000 -#define BASIS_REQUENCY_USB 12000000 - -#define GET_BITS(x, msb, lsb) \ - (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) - -/* legacy xway clock */ -#define LTQ_CGU_PLL0_CFG 0x0004 -#define LTQ_CGU_PLL1_CFG 0x0008 -#define LTQ_CGU_PLL2_CFG 0x000C -#define LTQ_CGU_SYS 0x0010 -#define LTQ_CGU_UPDATE 0x0014 -#define LTQ_CGU_IF_CLK 0x0018 -#define LTQ_CGU_OSC_CON 0x001C -#define LTQ_CGU_SMD 0x0020 -#define LTQ_CGU_CT1SR 0x0028 -#define LTQ_CGU_CT2SR 0x002C -#define LTQ_CGU_PCMCR 0x0030 -#define LTQ_CGU_PCI_CR 0x0034 -#define LTQ_CGU_PD_PC 0x0038 -#define LTQ_CGU_FMR 0x003C - -#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) -#define CGU_PLL0_BYPASS \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) -#define CGU_PLL0_CFG_DSMSEL \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) -#define CGU_PLL0_CFG_FRAC_EN \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) -#define CGU_PLL1_SRC \ - (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) -#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ - (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) -#define CGU_SYS_FPI_SEL (1 << 6) -#define CGU_SYS_DDR_SEL 0x3 -#define CGU_PLL0_SRC (1 << 29) - -#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) -#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) -#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) -#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) -#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) - -/* vr9 clock */ -#define LTQ_CGU_SYS_VR9 0x0c -#define LTQ_CGU_IF_CLK_VR9 0x24 - - -static unsigned int ltq_get_pll0_fdiv(void); - -static inline unsigned int get_input_clock(int pll) -{ - switch (pll) { - case 0: - if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) - return BASIS_REQUENCY_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_FREQUENCY_1; - else - return BASIC_FREQUENCY_2; - case 1: - if (CGU_PLL1_SRC) - return BASIS_REQUENCY_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_FREQUENCY_1; - else - return BASIC_FREQUENCY_2; - case 2: - switch (CGU_PLL2_SRC) { - case 0: - return ltq_get_pll0_fdiv(); - case 1: - return CGU_PLL2_PHASE_DIVIDER_ENABLE ? - BASIC_FREQUENCY_1 : - BASIC_FREQUENCY_2; - case 2: - return BASIS_REQUENCY_USB; - } - default: - return 0; - } -} - -static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) -{ - u64 res, clock = get_input_clock(pll); - - res = num * clock; - do_div(res, den); - return res; -} - -static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 10) + K; - unsigned int den = (M + 1) << 10; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 11) + K + 512; - unsigned int den = (M + 1) << 11; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = K >= 512 ? - ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; - unsigned int den = (M + 1) << 12; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, - unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) -{ - if (!dsmsel) - return mash_dsm(pll, M, N, K); - else if (!phase_div_en) - return mash_dsm(pll, M, N, K); - else - return ssff_dsm_2(pll, M, N, K); -} - -static inline unsigned int ltq_get_pll0_fosc(void) -{ - if (CGU_PLL0_BYPASS) - return get_input_clock(0); - else - return !CGU_PLL0_CFG_FRAC_EN - ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, - CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE) - : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, - CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE); -} - -static unsigned int ltq_get_pll0_fdiv(void) -{ - unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; - - return (ltq_get_pll0_fosc() + (div >> 1)) / div; -} - -unsigned long ltq_danube_io_region_clock(void) -{ - unsigned int ret = ltq_get_pll0_fosc(); - - switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0x3) { - default: - case 0: - return (ret + 1) / 2; - case 1: - return (ret * 2 + 2) / 5; - case 2: - return (ret + 1) / 3; - case 3: - return (ret + 2) / 4; - } -} - -unsigned long ltq_danube_fpi_bus_clock(int fpi) -{ - unsigned long ret = ltq_danube_io_region_clock(); - - if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) - ret >>= 1; - return ret; -} - -unsigned long ltq_danube_fpi_hz(void) -{ - unsigned long ddr_clock = DDR_HZ; - - if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) - return ddr_clock >> 1; - return ddr_clock; -} - -unsigned long ltq_danube_cpu_hz(void) -{ - switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { - case 0: - return CLOCK_333M; - case 4: - return DDR_HZ; - case 8: - return DDR_HZ << 1; - default: - return DDR_HZ >> 1; - } -} - -unsigned long ltq_ar9_sys_hz(void) -{ - if (((ltq_cgu_r32(LTQ_CGU_SYS) >> 3) & 0x3) == 0x2) - return CLOCK_393M; - return CLOCK_333M; -} - -unsigned long ltq_ar9_fpi_hz(void) -{ - unsigned long sys = ltq_ar9_sys_hz(); - - if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(0)) - return sys; - return sys >> 1; -} - -unsigned long ltq_ar9_cpu_hz(void) -{ - if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(2)) - return ltq_ar9_fpi_hz(); - else - return ltq_ar9_sys_hz(); -} - -unsigned long ltq_vr9_cpu_hz(void) -{ - unsigned int cpu_sel; - unsigned long clk; - - cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf; - - switch (cpu_sel) { - case 0: - clk = CLOCK_600M; - break; - case 1: - clk = CLOCK_500M; - break; - case 2: - clk = CLOCK_393M; - break; - case 3: - clk = CLOCK_333M; - break; - case 5: - case 6: - clk = CLOCK_196_608M; - break; - case 7: - clk = CLOCK_167M; - break; - case 4: - case 8: - case 9: - clk = CLOCK_125M; - break; - default: - clk = 0; - break; - } - - return clk; -} - -unsigned long ltq_vr9_fpi_hz(void) -{ - unsigned int ocp_sel, cpu_clk; - unsigned long clk; - - cpu_clk = ltq_vr9_cpu_hz(); - ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3; - - switch (ocp_sel) { - case 0: - /* OCP ratio 1 */ - clk = cpu_clk; - break; - case 2: - /* OCP ratio 2 */ - clk = cpu_clk / 2; - break; - case 3: - /* OCP ratio 2.5 */ - clk = (cpu_clk * 2) / 5; - break; - case 4: - /* OCP ratio 3 */ - clk = cpu_clk / 3; - break; - default: - clk = 0; - break; - } - - return clk; -} - -unsigned long ltq_vr9_fpi_bus_clock(int fpi) -{ - return ltq_vr9_fpi_hz(); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-dwc_otg.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-dwc_otg.c deleted file mode 100644 index 56086fa139..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-dwc_otg.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/string.h> -#include <linux/mtd/physmap.h> -#include <linux/kernel.h> -#include <linux/reboot.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/etherdevice.h> -#include <linux/reboot.h> -#include <linux/time.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/leds.h> - -#include <asm/bootinfo.h> -#include <asm/irq.h> - -#include <lantiq_soc.h> -#include <lantiq_irq.h> -#include <lantiq_platform.h> - -#define LTQ_USB_IOMEM_BASE 0x1e101000 -#define LTQ_USB_IOMEM_SIZE 0x00001000 - -static struct resource resources[] = -{ - [0] = { - .name = "dwc_otg_membase", - .start = LTQ_USB_IOMEM_BASE, - .end = LTQ_USB_IOMEM_BASE + LTQ_USB_IOMEM_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "dwc_otg_irq", - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 dwc_dmamask = (u32)0x1fffffff; - -static struct platform_device platform_dev = { - .name = "dwc_otg", - .dev = { - .dma_mask = &dwc_dmamask, - }, - .resource = resources, - .num_resources = ARRAY_SIZE(resources), -}; - -int __init -xway_register_dwc(int pin) -{ - struct irq_data d; - d.irq = resources[1].start; - ltq_enable_irq(&d); - resources[1].start = ltq_is_ase() ? LTQ_USB_ASE_INT : LTQ_USB_INT; - platform_dev.dev.platform_data = (void*) pin; - return platform_device_register(&platform_dev); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-dwc_otg.h b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-dwc_otg.h deleted file mode 100644 index 521fad05ef..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-dwc_otg.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#ifndef _LTQ_DEV_DWC_H__ -#define _LTQ_DEV_DWC_H__ - -#include <lantiq_platform.h> - -extern void __init xway_register_dwc(int pin); - -#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.c deleted file mode 100644 index ea08a359ff..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Copyright (C) 2012 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/string.h> -#include <linux/mtd/physmap.h> -#include <linux/kernel.h> -#include <linux/reboot.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/etherdevice.h> -#include <linux/reboot.h> -#include <linux/time.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/leds.h> - -#include <asm/bootinfo.h> -#include <asm/irq.h> - -#include <lantiq_soc.h> -#include <lantiq_irq.h> -#include <lantiq_platform.h> - -static u64 dmamask = (u32)0x1fffffff; - -static struct platform_device platform_dev = { - .name = "ifxusb_hcd", - .dev.dma_mask = &dmamask, -}; - -int __init -xway_register_hcd(int *pins) -{ - platform_dev.dev.platform_data = pins; - return platform_device_register(&platform_dev); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.h b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.h deleted file mode 100644 index 18b3d2dae4..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Copyright (C) 2012 John Crispin <blogic@openwrt.org> - */ - -#ifndef _LTQ_DEV_HCD_H__ -#define _LTQ_DEV_HCD_H__ - -#include <lantiq_platform.h> - -extern void __init xway_register_hcd(int *pin); - -#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-athxk.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-athxk.c deleted file mode 100644 index a75abe3e00..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-athxk.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - * Copyright (C) 2011 Andrej VlaÅ¡ić <andrej.vlasic0@gmail.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/ath5k_platform.h> -#include <linux/ath9k_platform.h> -#include <linux/pci.h> - -#include "dev-wifi-athxk.h" - -extern int (*ltqpci_plat_dev_init)(struct pci_dev *dev); -struct ath5k_platform_data ath5k_pdata; -struct ath9k_platform_data ath9k_pdata = { - .led_pin = -1, - .endian_check = true, -}; - -static int -ath5k_pci_plat_dev_init(struct pci_dev *dev) -{ - dev->dev.platform_data = &ath5k_pdata; - return 0; -} - -static int -ath9k_pci_plat_dev_init(struct pci_dev *dev) -{ - dev->dev.platform_data = &ath9k_pdata; - return 0; -} - -void __init -ltq_register_ath5k(u16 *eeprom_data, u8 *macaddr) -{ - ath5k_pdata.eeprom_data = eeprom_data; - ath5k_pdata.macaddr = macaddr; - ltqpci_plat_dev_init = ath5k_pci_plat_dev_init; -} - -void __init -ltq_register_ath9k(u16 *eeprom_data, u8 *macaddr) -{ - memcpy(ath9k_pdata.eeprom_data, eeprom_data, sizeof(ath9k_pdata.eeprom_data)); - ath9k_pdata.macaddr = macaddr; - ltqpci_plat_dev_init = ath9k_pci_plat_dev_init; -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-athxk.h b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-athxk.h deleted file mode 100644 index 5fdb46b612..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-athxk.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - * Copyright (C) 2011 Andrej VlaÅ¡ić <andrej.vlasic0@gmail.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _DEV_WIFI_ATHXK_H__ -#define _DEV_WIFI_ATHXK_H__ - -extern void ltq_register_ath5k(u16 *eeprom_data, u8 *macaddr); -extern void ltq_register_ath9k(u16 *eeprom_data, u8 *macaddr); - -#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-rt2x00.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-rt2x00.c deleted file mode 100644 index 8e271f06ec..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-rt2x00.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/rt2x00_platform.h> -#include <linux/pci.h> - -#include "dev-wifi-rt2x00.h" - -extern int (*ltqpci_plat_dev_init)(struct pci_dev *dev); -struct rt2x00_platform_data rt2x00_pdata; - -static int -rt2x00_pci_plat_dev_init(struct pci_dev *dev) -{ - dev->dev.platform_data = &rt2x00_pdata; - return 0; -} - -void __init -ltq_register_rt2x00(const char *firmware, const u8 *mac) -{ - rt2x00_pdata.eeprom_file_name = kstrdup(firmware, GFP_KERNEL); - rt2x00_pdata.mac_address = mac; - ltqpci_plat_dev_init = rt2x00_pci_plat_dev_init; -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-rt2x00.h b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-rt2x00.h deleted file mode 100644 index 941c26535f..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-wifi-rt2x00.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _DEV_WIFI_RT2X00_H__ -#define _DEV_WIFI_RT2X00_H__ - -extern void ltq_register_rt2x00(const char *firmware, const u8 *mac); - -#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/gptu.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/gptu.c deleted file mode 100644 index ac82c37eba..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/gptu.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2012 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/pm.h> -#include <linux/export.h> -#include <linux/delay.h> -#include <linux/interrupt.h> -#include <asm/reboot.h> - -#include <lantiq_soc.h> -#include "../clk.h" - -#include "../devices.h" - -#define ltq_gptu_w32(x, y) ltq_w32((x), ltq_gptu_membase + (y)) -#define ltq_gptu_r32(x) ltq_r32(ltq_gptu_membase + (x)) - - -/* the magic ID byte of the core */ -#define GPTU_MAGIC 0x59 -/* clock control register */ -#define GPTU_CLC 0x00 -/* id register */ -#define GPTU_ID 0x08 -/* interrupt node enable */ -#define GPTU_IRNEN 0xf4 -/* interrupt control register */ -#define GPTU_IRCR 0xf8 -/* interrupt capture register */ -#define GPTU_IRNCR 0xfc -/* there are 3 identical blocks of 2 timers. calculate register offsets */ -#define GPTU_SHIFT(x) (x % 2 ? 4 : 0) -#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10) -/* timer control register */ -#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00) -/* timer auto reload register */ -#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08) -/* timer manual reload register */ -#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10) -/* timer count register */ -#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18) - -/* GPTU_CON(x) */ -#define CON_CNT BIT(2) -#define CON_EDGE_FALL BIT(7) -#define CON_SYNC BIT(8) -#define CON_CLK_INT BIT(10) - -/* GPTU_RUN(x) */ -#define RUN_SEN BIT(0) -#define RUN_RL BIT(2) - -/* set clock to runmode */ -#define CLC_RMC BIT(8) -/* bring core out of suspend */ -#define CLC_SUSPEND BIT(4) -/* the disable bit */ -#define CLC_DISABLE BIT(0) - -#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) - -enum gptu_timer { - TIMER1A = 0, - TIMER1B, - TIMER2A, - TIMER2B, - TIMER3A, - TIMER3B -}; - -static struct resource ltq_gptu_resource = - MEM_RES("GPTU", LTQ_GPTU_BASE_ADDR, LTQ_GPTU_SIZE); - -static void __iomem *ltq_gptu_membase; - -static irqreturn_t timer_irq_handler(int irq, void *priv) -{ - int timer = irq - TIMER_INTERRUPT; - ltq_gptu_w32(1 << timer, GPTU_IRNCR); - return IRQ_HANDLED; -} - -static void gptu_hwinit(void) -{ - struct clk *clk = clk_get_sys("ltq_gptu", NULL); - clk_enable(clk); - ltq_gptu_w32(0x00, GPTU_IRNEN); - ltq_gptu_w32(0xff, GPTU_IRNCR); - ltq_gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC); -} - -static void gptu_hwexit(void) -{ - ltq_gptu_w32(0x00, GPTU_IRNEN); - ltq_gptu_w32(0xff, GPTU_IRNCR); - ltq_gptu_w32(CLC_DISABLE, GPTU_CLC); -} - -static int ltq_gptu_enable(struct clk *clk) -{ - int ret = request_irq(TIMER_INTERRUPT + clk->bits, timer_irq_handler, - IRQF_TIMER, "timer", NULL); - if (ret) { - pr_err("gptu: failed to request irq\n"); - return ret; - } - - ltq_gptu_w32(CON_CNT | CON_EDGE_FALL | CON_SYNC | CON_CLK_INT, - GPTU_CON(clk->bits)); - ltq_gptu_w32(1, GPTU_RLD(clk->bits)); - ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) | clk->bits, GPTU_IRNEN); - ltq_gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); - return 0; -} - -static void ltq_gptu_disable(struct clk *clk) -{ - ltq_gptu_w32(0, GPTU_RUN(clk->bits)); - ltq_gptu_w32(0, GPTU_CON(clk->bits)); - ltq_gptu_w32(0, GPTU_RLD(clk->bits)); - ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) & ~clk->bits, GPTU_IRNEN); - free_irq(TIMER_INTERRUPT + clk->bits, NULL); -} - -static inline void clkdev_add_gptu(const char *con, unsigned int timer) -{ - struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); - - clk->cl.dev_id = "ltq_gptu"; - clk->cl.con_id = con; - clk->cl.clk = clk; - clk->enable = ltq_gptu_enable; - clk->disable = ltq_gptu_disable; - clk->bits = timer; - clkdev_add(&clk->cl); -} - -static int __init gptu_setup(void) -{ - /* remap gptu register range */ - ltq_gptu_membase = ltq_remap_resource(<q_gptu_resource); - if (!ltq_gptu_membase) - panic("Failed to remap gptu memory"); - - /* power up the core */ - gptu_hwinit(); - - /* the gptu has a ID register */ - if (((ltq_gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) { - pr_err("gptu: failed to find magic\n"); - gptu_hwexit(); - return -ENAVAIL; - } - - /* register the clocks */ - clkdev_add_gptu("timer1a", TIMER1A); - clkdev_add_gptu("timer1b", TIMER1B); - clkdev_add_gptu("timer2a", TIMER2A); - clkdev_add_gptu("timer2b", TIMER2B); - clkdev_add_gptu("timer3a", TIMER3A); - clkdev_add_gptu("timer3b", TIMER3B); - - pr_info("gptu: 6 timers loaded\n"); - - return 0; -} - -arch_initcall(gptu_setup); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-arv.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-arv.c deleted file mode 100644 index 6857e993d2..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-arv.c +++ /dev/null @@ -1,793 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/gpio_buttons.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/input.h> -#include <linux/etherdevice.h> -#include <linux/ath5k_platform.h> -#include <linux/ath9k_platform.h> -#include <linux/pci.h> - -#include <lantiq_soc.h> -#include <lantiq_platform.h> -#include <dev-gpio-leds.h> -#include <dev-gpio-buttons.h> - -#include "../machtypes.h" -#include "dev-wifi-rt2x00.h" -#include "dev-wifi-athxk.h" -#include "devices.h" -#include "dev-dwc_otg.h" -#include "pci-ath-fixup.h" - -static struct mtd_partition arv45xx_brnboot_partitions[] = -{ - { - .name = "brn-boot", - .offset = 0x0, - .size = 0x20000, - }, - { - .name = "config", - .offset = 0x20000, - .size = 0x30000, - }, - { - .name = "linux", - .offset = 0x50000, - .size = 0x390000, - }, - { - .name = "reserved", /* 12-byte signature at 0x3efff4 :/ */ - .offset = 0x3e0000, - .size = 0x010000, - }, - { - .name = "eeprom", - .offset = 0x3f0000, - .size = 0x10000, - }, -}; - -static struct mtd_partition arv75xx_brnboot_partitions[] = -{ - { - .name = "brn-boot", - .offset = 0x0, - .size = 0x20000, - }, - { - .name = "config", - .offset = 0x20000, - .size = 0x40000, - }, - { - .name = "linux", - .offset = 0x440000, - .size = 0x3a0000, - }, - { - .name = "reserved", /* 12-byte signature at 0x7efff4 :/ */ - .offset = 0x7e0000, - .size = 0x010000, - }, - { - .name = "board_config", - .offset = 0x7f0000, - .size = 0x10000, - }, -}; - -/* - * this is generic configuration for all arv based boards, note that it can be - * rewriten in arv_load_nor() - */ -static struct mtd_partition arv_partitions[] = -{ - { - .name = "uboot", - .offset = 0x0, - .size = 0x20000, - }, - { - .name = "uboot_env", - .offset = 0x20000, - .size = 0x10000, - }, - { - .name = "linux", - .offset = 0x30000, - .size = 0x3c0000, - }, - { - .name = "board_config", - .offset = 0x3f0000, - .size = 0x10000, - }, -}; - -static struct physmap_flash_data arv45xx_brnboot_flash_data = { - .nr_parts = ARRAY_SIZE(arv45xx_brnboot_partitions), - .parts = arv45xx_brnboot_partitions, -}; - -static struct physmap_flash_data arv75xx_brnboot_flash_data = { - .nr_parts = ARRAY_SIZE(arv75xx_brnboot_partitions), - .parts = arv75xx_brnboot_partitions, -}; - -static struct physmap_flash_data arv_flash_data = { - .nr_parts = ARRAY_SIZE(arv_partitions), - .parts = arv_partitions, -}; - -static struct ltq_pci_data ltq_pci_data = { - .clock = PCI_CLOCK_EXT, - .gpio = PCI_GNT1 | PCI_REQ1, - .irq = { - [14] = INT_NUM_IM0_IRL0 + 22, - }, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_RMII, -}; - -static struct gpio_led -arv4510pw_gpio_leds[] __initdata = { - { .name = "soc:green:foo", .gpio = 4, .active_low = 1, }, -}; - -static struct gpio_led -arv4518pw_gpio_leds[] __initdata = { - { .name = "soc:green:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:adsl", .gpio = 4, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:wifi", .gpio = 6, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:fail", .gpio = 8, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:usb", .gpio = 19, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:voip", .gpio = 100, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:fxs1", .gpio = 101, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:fxs2", .gpio = 102, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:fxo", .gpio = 103, .active_low = 1, .default_trigger = "default-on" }, -}; - -static struct gpio_keys_button -arv4518pw_gpio_keys[] __initdata = { - { - .desc = "wifi", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 28, - .active_low = 1, - }, - { - .desc = "reset", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 30, - .active_low = 1, - }, - { - .desc = "wps", - .type = EV_KEY, - .code = BTN_2, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 29, - .active_low = 1, - }, -}; - -static struct gpio_led -arv4519pw_gpio_leds[] __initdata = { - { .name = "soc:red:power", .gpio = 7, .active_low = 1, }, - { .name = "soc:green:power", .gpio = 2, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:wifi", .gpio = 6, .active_low = 1, }, - { .name = "soc:green:adsl", .gpio = 4, .active_low = 1, }, - { .name = "soc:green:internet", .gpio = 5, .active_low = 1, }, - { .name = "soc:red:internet", .gpio = 8, .active_low = 1, }, - { .name = "soc:green:voip", .gpio = 100, .active_low = 1, }, - { .name = "soc:green:phone1", .gpio = 101, .active_low = 1, }, - { .name = "soc:green:phone2", .gpio = 102, .active_low = 1, }, - { .name = "soc:green:fxo", .gpio = 103, .active_low = 1, }, - { .name = "soc:green:usb", .gpio = 19, .active_low = 1, }, - { .name = "soc:orange:wps", .gpio = 104, .active_low = 1, }, - { .name = "soc:green:wps", .gpio = 105, .active_low = 1, }, - { .name = "soc:red:wps", .gpio = 106, .active_low = 1, }, - -}; - -static struct gpio_keys_button -arv4519pw_gpio_keys[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 30, - .active_low = 1, - }, - { - .desc = "wlan", - .type = EV_KEY, - .code = BTN_2, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 28, - .active_low = 1, - }, -}; - -static struct gpio_led -arv4520pw_gpio_leds[] __initdata = { - { .name = "soc:blue:power", .gpio = 3, .active_low = 1, }, - { .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, }, - { .name = "soc:blue:internet", .gpio = 5, .active_low = 1, }, - { .name = "soc:red:power", .gpio = 6, .active_low = 1, }, - { .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, }, - { .name = "soc:red:wps", .gpio = 9, .active_low = 1, }, - { .name = "soc:blue:voip", .gpio = 100, .active_low = 1, }, - { .name = "soc:blue:fxs1", .gpio = 101, .active_low = 1, }, - { .name = "soc:blue:fxs2", .gpio = 102, .active_low = 1, }, - { .name = "soc:blue:fxo", .gpio = 103, .active_low = 1, }, - { .name = "soc:blue:voice", .gpio = 104, .active_low = 1, }, - { .name = "soc:blue:usb", .gpio = 105, .active_low = 1, }, - { .name = "soc:blue:wifi", .gpio = 106, .active_low = 1, }, -}; - -static struct gpio_led -arv452cpw_gpio_leds[] __initdata = { - { .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:isdn", .gpio = 5, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:wps", .gpio = 9, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:fxs1", .gpio = 100, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:fxs2", .gpio = 101, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:wps", .gpio = 102, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:fxo", .gpio = 103, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:voice", .gpio = 104, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:usb", .gpio = 105, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:wifi", .gpio = 106, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:internet", .gpio = 108, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:internet", .gpio = 109, .active_low = 1, .default_trigger = "default-on" }, -}; - -static struct gpio_led -arv4525pw_gpio_leds[] __initdata = { - { .name = "soc:green:dsl", .gpio = 6, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:wifi", .gpio = 8, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:online", .gpio = 9, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:fxs-internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:fxs-festnetz", .gpio = 4, .active_low = 1, .default_trigger = "default-on" }, -}; - -#define ARV4525PW_PHYRESET 13 -#define ARV4525PW_RELAY 31 - -static struct gpio -arv4525pw_gpios[] __initdata = { - { ARV4525PW_PHYRESET, GPIOF_OUT_INIT_HIGH, "phyreset" }, - { ARV4525PW_RELAY, GPIOF_OUT_INIT_HIGH, "relay" }, -}; - - -static struct gpio_led -arv752dpw22_gpio_leds[] __initdata = { - { .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:wps", .gpio = 8, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:fxo", .gpio = 103, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:voice", .gpio = 104, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:usb", .gpio = 105, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:wifi", .gpio = 106, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:wifi1", .gpio = 107, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:wifi", .gpio = 108, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:blue:wifi1", .gpio = 109, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:eth1", .gpio = 111, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:eth2", .gpio = 112, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:eth3", .gpio = 113, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:eth4", .gpio = 114, .active_low = 1, .default_trigger = "default-on", }, -}; - -static struct gpio_keys_button -arv752dpw22_gpio_keys[] __initdata = { - { - .desc = "btn0", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 12, - .active_low = 1, - }, - { - .desc = "btn1", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 13, - .active_low = 1, - }, - { - .desc = "btn2", - .type = EV_KEY, - .code = BTN_2, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 28, - .active_low = 1, - }, -}; - -static struct gpio_led -arv7518pw_gpio_leds[] __initdata = { - { .name = "soc:red:power", .gpio = 7, .active_low = 1, }, - { .name = "soc:green:power", .gpio = 2, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:wifi", .gpio = 6, .active_low = 1, }, - { .name = "soc:green:adsl", .gpio = 4, .active_low = 1, }, - { .name = "soc:green:internet", .gpio = 5, .active_low = 1, }, - { .name = "soc:red:internet", .gpio = 8, .active_low = 1, }, - { .name = "soc:green:voip", .gpio = 100, .active_low = 1, }, - { .name = "soc:green:phone1", .gpio = 101, .active_low = 1, }, - { .name = "soc:green:phone2", .gpio = 102, .active_low = 1, }, - { .name = "soc:orange:fail", .gpio = 103, .active_low = 1, }, - { .name = "soc:green:usb", .gpio = 19, .active_low = 1, }, - { .name = "soc:orange:wps", .gpio = 104, .active_low = 1, }, - { .name = "soc:green:wps", .gpio = 105, .active_low = 1, }, - { .name = "soc:red:wps", .gpio = 106, .active_low = 1, }, - -}; - -static struct gpio_keys_button -arv7518pw_gpio_keys[] __initdata = { - /*{ - .desc = "reset", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 23, - .active_low = 1, - },*/ - { - .desc = "wifi", - .type = EV_KEY, - .code = BTN_2, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 25, - .active_low = 1, - }, -}; - -static struct gpio_keys_button -arv7525pw_gpio_keys[] __initdata = { - { - .desc = "restart", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 29, - .active_low = 1, - }, -}; - -static void __init -arv_load_nor(unsigned int max) -{ -#define UBOOT_MAGIC 0x27051956 - - int i; - int sector = -1; - - if (ltq_brn_boot) { - if (max == 0x800000) - ltq_register_nor(&arv75xx_brnboot_flash_data); - else - ltq_register_nor(&arv45xx_brnboot_flash_data); - return; - } - - for (i = 1; i < 4 && sector < 0; i++) { - unsigned int uboot_magic; - memcpy_fromio(&uboot_magic, (void *)KSEG1ADDR(LTQ_FLASH_START) + (i * 0x10000), 4); - if (uboot_magic == UBOOT_MAGIC) - sector = i; - } - - if (sector < 0) - return; - - arv_partitions[0].size = arv_partitions[1].offset = (sector - 1) * 0x10000; - arv_partitions[2].offset = arv_partitions[0].size + 0x10000; - arv_partitions[2].size = max - arv_partitions[2].offset - 0x10000; - arv_partitions[3].offset = max - 0x10000; - ltq_register_nor(&arv_flash_data); -} - -static void __init -arv_register_ethernet(unsigned int mac_addr) -{ - memcpy_fromio(<q_eth_data.mac.sa_data, - (void *)KSEG1ADDR(LTQ_FLASH_START + mac_addr), 6); - ltq_register_etop(<q_eth_data); -} - -static u16 arv_ath5k_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS]; -static u16 arv_ath9k_eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS]; -static u8 arv_athxk_eeprom_mac[6]; - -static void __init -arv_register_ath5k(unsigned int ath_addr, unsigned int mac_addr) -{ - int i; - - memcpy_fromio(arv_athxk_eeprom_mac, - (void *)KSEG1ADDR(LTQ_FLASH_START + mac_addr), 6); - arv_athxk_eeprom_mac[5]++; - memcpy_fromio(arv_ath5k_eeprom_data, - (void *)KSEG1ADDR(LTQ_FLASH_START + ath_addr), ATH5K_PLAT_EEP_MAX_WORDS); - // swap eeprom bytes - for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS>>1; i++) { - arv_ath5k_eeprom_data[i] = swab16(arv_ath5k_eeprom_data[i]); - if (i == 0x17e>>1) { - /* - * regdomain is invalid. it's unknown how did original - * fw convered value to 0x82d4 so for now force to 0x67 - */ - arv_ath5k_eeprom_data[i] &= 0x0000; - arv_ath5k_eeprom_data[i] |= 0x67; - } - } -} - -static void __init -arv_register_ath9k(unsigned int ath_addr, unsigned int mac_addr) -{ - int i; - u16 *eepdata, sum, el; - - memcpy_fromio(arv_athxk_eeprom_mac, - (void *)KSEG1ADDR(LTQ_FLASH_START + mac_addr), 6); - arv_athxk_eeprom_mac[5]++; - memcpy_fromio(arv_ath9k_eeprom_data, - (void *)KSEG1ADDR(LTQ_FLASH_START + ath_addr), ATH9K_PLAT_EEP_MAX_WORDS); - - // force regdomain to 0x67 - arv_ath9k_eeprom_data[0x208>>1] = 0x67; - - // calculate new checksum - sum = arv_ath9k_eeprom_data[0x200>>1]; - el = sum / sizeof(u16) - 2; /* skip length and (old) checksum */ - eepdata = (u16 *) (&arv_ath9k_eeprom_data[0x204>>1]); /* after checksum */ - for (i = 0; i < el; i++) - sum ^= *eepdata++; - sum ^= 0xffff; - arv_ath9k_eeprom_data[0x202>>1] = sum; -} - -static void __init -arv3527p_init(void) -{ -#define ARV3527P_MAC_ADDR 0x3f0016 - - ltq_register_gpio_stp(); - // ltq_add_device_gpio_leds(arv3527p_gpio_leds, ARRAY_SIZE(arv3527p_gpio_leds)); - arv_load_nor(0x400000); - arv_register_ethernet(ARV3527P_MAC_ADDR); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV3527P, - "ARV3527P", - "ARV3527P - Arcor Easybox 401", - arv3527p_init); - -static void __init -arv4510pw_init(void) -{ -#define ARV4510PW_MAC_ADDR 0x3f0014 - - ltq_register_gpio_stp(); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4510pw_gpio_leds), arv4510pw_gpio_leds); - arv_load_nor(0x400000); - ltq_pci_data.irq[12] = (INT_NUM_IM2_IRL0 + 31); - ltq_pci_data.irq[15] = (INT_NUM_IM0_IRL0 + 26); - ltq_pci_data.gpio |= PCI_EXIN2 | PCI_REQ2; - ltq_register_pci(<q_pci_data); - arv_register_ethernet(ARV4510PW_MAC_ADDR); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV4510PW, - "ARV4510PW", - "ARV4510PW - Wippies Homebox", - arv4510pw_init); - -static void __init -arv4518pw_init(void) -{ -#define ARV4518PW_EBU 0 -#define ARV4518PW_USB 14 -#define ARV4518PW_SWITCH_RESET 13 -#define ARV4518PW_ATH_ADDR 0x3f0400 -#define ARV4518PW_MAC_ADDR 0x3f0016 - - ltq_register_gpio_ebu(ARV4518PW_EBU); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4518pw_gpio_leds), arv4518pw_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, - ARRAY_SIZE(arv4518pw_gpio_keys), arv4518pw_gpio_keys); - arv_load_nor(0x400000); - ltq_pci_data.gpio = PCI_GNT2 | PCI_REQ2; - ltq_register_pci(<q_pci_data); - xway_register_dwc(ARV4518PW_USB); - arv_register_ethernet(ARV4518PW_MAC_ADDR); - arv_register_ath5k(ARV4518PW_ATH_ADDR, ARV4518PW_MAC_ADDR); - ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac); - ltq_register_tapi(); - - gpio_request(ARV4518PW_SWITCH_RESET, "switch"); - gpio_direction_output(ARV4518PW_SWITCH_RESET, 1); - gpio_export(ARV4518PW_SWITCH_RESET, 0); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV4518PW, - "ARV4518PW", - "ARV4518PW - SMC7908A-ISP, Airties WAV-221", - arv4518pw_init); - -static void __init -arv4519pw_init(void) -{ -#define ARV4519PW_EBU 0 -#define ARV4519PW_USB 14 -#define ARV4519PW_RELAY 31 -#define ARV4519PW_SWITCH_RESET 13 -#define ARV4519PW_ATH_ADDR 0x3f0400 -#define ARV4519PW_MAC_ADDR 0x3f0016 - - arv_load_nor(0x400000); - ltq_register_gpio_ebu(ARV4519PW_EBU); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4519pw_gpio_leds), arv4519pw_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, - ARRAY_SIZE(arv4519pw_gpio_keys), arv4519pw_gpio_keys); - ltq_pci_data.gpio = PCI_GNT2 | PCI_REQ1; - ltq_register_pci(<q_pci_data); - xway_register_dwc(ARV4519PW_USB); - arv_register_ethernet(ARV4519PW_MAC_ADDR); - arv_register_ath5k(ARV4519PW_ATH_ADDR, ARV4519PW_MAC_ADDR); - ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac); - ltq_register_tapi(); - - gpio_request(ARV4519PW_RELAY, "relay"); - gpio_direction_output(ARV4519PW_RELAY, 1); - gpio_export(ARV4519PW_RELAY, 0); - - gpio_request(ARV4519PW_SWITCH_RESET, "switch"); - gpio_set_value(ARV4519PW_SWITCH_RESET, 1); - gpio_export(ARV4519PW_SWITCH_RESET, 0); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV4519PW, - "ARV4519PW", - "ARV4519PW - Vodafone, Pirelli", - arv4519pw_init); - -static void __init -arv4520pw_init(void) -{ -#define ARV4520PW_EBU 0x400 -#define ARV4520PW_USB 28 -#define ARV4520PW_SWITCH_RESET 110 -#define ARV4520PW_MAC_ADDR 0x3f0016 - - ltq_register_gpio_ebu(ARV4520PW_EBU); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4520pw_gpio_leds), arv4520pw_gpio_leds); - arv_load_nor(0x400000); - ltq_register_pci(<q_pci_data); - ltq_register_tapi(); - arv_register_ethernet(ARV4520PW_MAC_ADDR); - ltq_register_rt2x00(NULL, (const u8 *) ltq_eth_data.mac.sa_data); - xway_register_dwc(ARV4520PW_USB); - ltq_register_tapi(); - - gpio_request(ARV4520PW_SWITCH_RESET, "switch"); - gpio_set_value(ARV4520PW_SWITCH_RESET, 1); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV4520PW, - "ARV4520PW", - "ARV4520PW - Airties WAV-281, Arcor A800", - arv4520pw_init); - -static void __init -arv452Cpw_init(void) -{ -#define ARV452CPW_EBU 0x77f -#define ARV452CPW_USB 28 -#define ARV452CPW_RELAY1 31 -#define ARV452CPW_RELAY2 107 -#define ARV452CPW_SWITCH_RESET 110 -#define ARV452CPW_ATH_ADDR 0x3f0400 -#define ARV452CPW_MAC_ADDR 0x3f0016 - - ltq_register_gpio_ebu(ARV452CPW_EBU); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv452cpw_gpio_leds), arv452cpw_gpio_leds); - arv_load_nor(0x400000); - ltq_register_pci(<q_pci_data); - xway_register_dwc(ARV452CPW_USB); - arv_register_ethernet(ARV452CPW_MAC_ADDR); - arv_register_ath5k(ARV452CPW_ATH_ADDR, ARV452CPW_MAC_ADDR); - ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac); - ltq_register_tapi(); - - gpio_request(ARV452CPW_SWITCH_RESET, "switch"); - gpio_set_value(ARV452CPW_SWITCH_RESET, 1); - gpio_export(ARV452CPW_SWITCH_RESET, 0); - - gpio_request(ARV452CPW_RELAY1, "relay1"); - gpio_direction_output(ARV452CPW_RELAY1, 1); - gpio_export(ARV452CPW_RELAY1, 0); - - gpio_request(ARV452CPW_RELAY2, "relay2"); - gpio_set_value(ARV452CPW_RELAY2, 1); - gpio_export(ARV452CPW_RELAY2, 0); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV452CPW, - "ARV452CPW", - "ARV452CPW - Arcor A801", - arv452Cpw_init); - -static void __init -arv4525pw_init(void) -{ -#define ARV4525PW_ATH_ADDR 0x3f0400 -#define ARV4525PW_MAC_ADDR 0x3f0016 - - arv_load_nor(0x400000); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4525pw_gpio_leds), arv4525pw_gpio_leds); - gpio_request_array(arv4525pw_gpios, ARRAY_SIZE(arv4525pw_gpios)); - gpio_export(ARV4525PW_RELAY, false); - gpio_export(ARV4525PW_PHYRESET, false); - ltq_pci_data.clock = PCI_CLOCK_INT; - ltq_register_pci(<q_pci_data); - arv_register_ath5k(ARV4525PW_ATH_ADDR, ARV4525PW_MAC_ADDR); - ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac); - ltq_eth_data.mii_mode = PHY_INTERFACE_MODE_MII; - arv_register_ethernet(ARV4525PW_MAC_ADDR); - ltq_register_tapi(); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV4525PW, - "ARV4525PW", - "ARV4525PW - Speedport W502V", - arv4525pw_init); - -static void __init -arv7525pw_init(void) -{ -#define ARV7525P_MAC_ADDR 0x3f0016 - - arv_load_nor(0x400000); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4525pw_gpio_leds), arv4525pw_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, - ARRAY_SIZE(arv7525pw_gpio_keys), arv7525pw_gpio_keys); - ltq_pci_data.clock = PCI_CLOCK_INT; - ltq_pci_data.gpio = PCI_GNT1 | PCI_EXIN1; - ltq_pci_data.irq[14] = (INT_NUM_IM3_IRL0 + 31); - ltq_register_pci(<q_pci_data); - ltq_eth_data.mii_mode = PHY_INTERFACE_MODE_MII; - ltq_register_rt2x00("RT2860.eeprom", NULL); - ltq_register_tapi(); - arv_register_ethernet(ARV7525P_MAC_ADDR); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV7525PW, - "ARV7525PW", - "ARV7525PW - Speedport W303V", - arv7525pw_init); - -static void __init -arv7518pw_init(void) -{ -#define ARV7518PW_EBU 0x2 -#define ARV7518PW_USB 14 -#define ARV7518PW_SWITCH_RESET 13 -#define ARV7518PW_ATH_ADDR 0x7f0400 -#define ARV7518PW_MAC_ADDR 0x7f0016 - - arv_load_nor(0x800000); - ltq_register_gpio_ebu(ARV7518PW_EBU); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv7518pw_gpio_leds), arv7518pw_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, - ARRAY_SIZE(arv7518pw_gpio_keys), arv7518pw_gpio_keys); - ltq_register_pci(<q_pci_data); - ltq_register_tapi(); - xway_register_dwc(ARV7518PW_USB); - arv_register_ethernet(ARV7518PW_MAC_ADDR); - arv_register_ath9k(ARV7518PW_ATH_ADDR, ARV7518PW_MAC_ADDR); - ltq_register_ath9k(arv_ath9k_eeprom_data, arv_athxk_eeprom_mac); - ltq_pci_ath_fixup(14, arv_ath9k_eeprom_data); - ltq_register_tapi(); - - gpio_request(ARV7518PW_SWITCH_RESET, "switch"); - gpio_direction_output(ARV7518PW_SWITCH_RESET, 1); - gpio_export(ARV7518PW_SWITCH_RESET, 0); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV7518PW, - "ARV7518PW", - "ARV7518PW - ASTORIA", - arv7518pw_init); - -static void __init -arv752dpw22_init(void) -{ -#define ARV752DPW22_EBU 0x2 -#define ARV752DPW22_USB 100 -#define ARV752DPW22_RELAY 101 -#define ARV752DPW22_MAC_ADDR 0x7f0016 - - arv_load_nor(0x800000); - ltq_register_gpio_ebu(ARV752DPW22_EBU); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv752dpw22_gpio_leds), arv752dpw22_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, - ARRAY_SIZE(arv752dpw22_gpio_keys), arv752dpw22_gpio_keys); - ltq_pci_data.irq[15] = (INT_NUM_IM3_IRL0 + 31); - ltq_pci_data.gpio |= PCI_EXIN1 | PCI_REQ2; - ltq_register_pci(<q_pci_data); - xway_register_dwc(ARV752DPW22_USB); - arv_register_ethernet(ARV752DPW22_MAC_ADDR); - ltq_register_tapi(); - - gpio_request(ARV752DPW22_RELAY, "relay"); - gpio_set_value(ARV752DPW22_RELAY, 1); - gpio_export(ARV752DPW22_RELAY, 0); -} - -MIPS_MACHINE(LANTIQ_MACH_ARV752DPW22, - "ARV752DPW22", - "ARV752DPW22 - Arcor A803", - arv752dpw22_init); - -static void __init -arv752dpw_init(void) -{ -#define ARV752DPW22_EBU 0x2 -#define ARV752DPW22_USB 100 -#define ARV752DPW22_RELAY 101 -#define ARV752DPW22_MAC_ADDR 0x7f0016 - - arv_load_nor(0x800000); - ltq_register_gpio_ebu(ARV752DPW22_EBU); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv752dpw22_gpio_leds), arv752dpw22_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(arv752dpw22_gpio_keys), arv752dpw22_gpio_keys); - ltq_pci_data.irq[14] = (INT_NUM_IM3_IRL0 + 31); - ltq_pci_data.gpio |= PCI_EXIN1 | PCI_REQ2; - ltq_register_pci(<q_pci_data); - ltq_register_tapi(); - xway_register_dwc(ARV752DPW22_USB); - ltq_register_rt2x00("RT2860.eeprom", NULL); - arv_register_ethernet(ARV752DPW22_MAC_ADDR); - gpio_request(ARV752DPW22_RELAY, "relay"); - gpio_set_value(ARV752DPW22_RELAY, 1); - gpio_export(ARV752DPW22_RELAY, 0); - -} - -MIPS_MACHINE(LANTIQ_MACH_ARV752DPW, - "ARV752DPW", - "ARV752DPW - Arcor A802", - arv752dpw_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-bthomehubv2b.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-bthomehubv2b.c deleted file mode 100644 index 44fe2f4efe..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-bthomehubv2b.c +++ /dev/null @@ -1,542 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Andrej VlaÅ¡ić - * Copyright (C) 2011 Luka Perkov - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/input.h> -#include <linux/ath5k_platform.h> -#include <linux/ath9k_platform.h> -#include <linux/pci.h> -#include <linux/phy.h> -#include <linux/io.h> -#include <linux/string.h> -#include <linux/delay.h> -#include <linux/module.h> - -#include <irq.h> -#include <lantiq_soc.h> -#include <lantiq_platform.h> -#include <dev-gpio-leds.h> -#include <dev-gpio-buttons.h> - -#include "../machtypes.h" -//#include "dev-wifi-ath9k.h" -#include "devices.h" -#include "dev-dwc_otg.h" - -#undef USE_BTHH_GPIO_INIT - -// this reads certain data from u-boot if it's there -#define USE_UBOOT_ENV_DATA - -#define UBOOT_ENV_OFFSET 0x040000 -#define UBOOT_ENV_SIZE 0x010000 - -#ifdef NAND_ORGLAYOUT -// this is only here for reference -// definition of NAND flash area -static struct mtd_partition bthomehubv2b_nand_partitions[] = -{ - { - .name = "ART", - .offset = 0x0000000, - .size = 0x0004000, - }, - { - .name = "image1", - .offset = 0x0004000, - .size = 0x0E00000, - }, - { - .name = "unknown1", - .offset = 0x0E04000, - .size = 0x00FC000, - }, - { - .name = "image2", - .offset = 0x0F00000, - .size = 0x0E00000, - }, - { - .name = "unknown2", - .offset = 0x1D00000, - .size = 0x0300000, - }, - -}; -#endif - -#ifdef NAND_KEEPOPENRG -// this allows both firmwares to co-exist - -static struct mtd_partition bthomehubv2b_nand_partitions[] = -{ - { - .name = "art", - .offset = 0x0000000, - .size = 0x0004000, - }, - { - .name = "Image1", - .offset = 0x0004000, - .size = 0x0E00000, - }, - { - .name = "linux", - .offset = 0x0E04000, - .size = 0x11fC000, - }, - { - .name = "wholeflash", - .offset = 0x0000000, - .size = 0x2000000, - }, - -}; -#endif - -// this gives more jffs2 by overwriting openrg - -static struct mtd_partition bthomehubv2b_nand_partitions[] = -{ - { - .name = "art", - .offset = 0x0000000, - .size = 0x0004000, - }, - { - .name = "linux", - .offset = 0x0004000, - .size = 0x1ffC000, - }, - { - .name = "wholeflash", - .offset = 0x0000000, - .size = 0x2000000, - }, - -}; - -extern void __init xway_register_nand(struct mtd_partition *parts, int count); - -// end BTHH_USE_NAND - -static struct gpio_led -bthomehubv2b_gpio_leds[] __initdata = { - - { .name = "soc:orange:upgrading", .gpio = 213, }, - { .name = "soc:orange:phone", .gpio = 214, }, - { .name = "soc:blue:phone", .gpio = 215, }, - { .name = "soc:orange:wireless", .gpio = 216, }, - { .name = "soc:blue:wireless", .gpio = 217, }, - { .name = "soc:red:broadband", .gpio = 218, }, - { .name = "soc:orange:broadband", .gpio = 219, }, - { .name = "soc:blue:broadband", .gpio = 220, }, - { .name = "soc:red:power", .gpio = 221, }, - { .name = "soc:orange:power", .gpio = 222, }, - { .name = "soc:blue:power", .gpio = 223, }, -}; - -static struct gpio_keys_button -bthomehubv2b_gpio_keys[] __initdata = { - { - .desc = "restart", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 2, - .active_low = 1, - }, - { - .desc = "findhandset", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 15, - .active_low = 1, - }, - { - .desc = "wps", - .type = EV_KEY, - .code = BTN_2, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 22, - .active_low = 1, - }, -}; - -// definition of NOR flash area - as per original. -static struct mtd_partition bthomehubv2b_partitions[] = -{ - { - .name = "uboot", - .offset = 0x000000, - .size = 0x040000, - }, - { - .name = "uboot_env", - .offset = UBOOT_ENV_OFFSET, - .size = UBOOT_ENV_SIZE, - }, - { - .name = "rg_conf_1", - .offset = 0x050000, - .size = 0x010000, - }, - { - .name = "rg_conf_2", - .offset = 0x060000, - .size = 0x010000, - }, - { - .name = "rg_conf_factory", - .offset = 0x070000, - .size = 0x010000, - }, -}; - - -/* nor flash */ -/* bt homehubv2b has a very small nor flash */ -/* so make it look for a small one, else we get a lot of alias chips identified - */ -/* not a bug problem, but fills the logs. */ -static struct resource bthhv2b_nor_resource = - MEM_RES("nor", LTQ_FLASH_START, 0x80000); - -static struct platform_device ltq_nor = { - .name = "ltq_nor", - .resource = &bthhv2b_nor_resource, - .num_resources = 1, -}; - -static void __init bthhv2b_register_nor(struct physmap_flash_data *data) -{ - ltq_nor.dev.platform_data = data; - platform_device_register(<q_nor); -} - -static struct physmap_flash_data bthomehubv2b_flash_data = { - .nr_parts = ARRAY_SIZE(bthomehubv2b_partitions), - .parts = bthomehubv2b_partitions, -}; - - - - -static struct ltq_pci_data ltq_pci_data = { - .clock = PCI_CLOCK_INT, - .gpio = PCI_GNT1 | PCI_REQ1, - .irq = { [14] = INT_NUM_IM0_IRL0 + 22, }, -}; - - - - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_MII, -}; - - - - -static char __init *get_uboot_env_var(char *haystack, int haystack_len, char *needle, int needle_len) { - int i; - for (i = 0; i <= haystack_len - needle_len; i++) { - if (memcmp(haystack + i, needle, needle_len) == 0) { - return haystack + i + needle_len; - } - } - return NULL; -} - -/* - * bthomehubv2b_parse_hex_* are not uniq. in arm/orion there are also duplicates: - * dns323_parse_hex_* - * TODO: one day write a patch for this :) - */ -static int __init bthomehubv2b_parse_hex_nibble(char n) { - if (n >= '0' && n <= '9') - return n - '0'; - - if (n >= 'A' && n <= 'F') - return n - 'A' + 10; - - if (n >= 'a' && n <= 'f') - return n - 'a' + 10; - - return -1; -} - -static int __init bthomehubv2b_parse_hex_byte(const char *b) { - int hi; - int lo; - - hi = bthomehubv2b_parse_hex_nibble(b[0]); - lo = bthomehubv2b_parse_hex_nibble(b[1]); - - if (hi < 0 || lo < 0) - return -1; - - return (hi << 4) | lo; -} - -static int __init bthomehubv2b_register_ethernet(void) { - u_int8_t addr[6]; - int i; - char *mac = "01:02:03:04:05:06"; - int gotmac = 0; - char *boardid = "BTHHV2B"; - int gotboardid = 0; - - char *uboot_env_page; - uboot_env_page = ioremap(LTQ_FLASH_START + UBOOT_ENV_OFFSET, UBOOT_ENV_SIZE); - if (uboot_env_page) - { - char *Data = NULL; - Data = get_uboot_env_var(uboot_env_page, UBOOT_ENV_SIZE, "\0ethaddr=", 9); - if (Data) - { - mac = Data; - } - - Data = get_uboot_env_var(uboot_env_page, UBOOT_ENV_SIZE, "\0boardid=", 9); - - if (Data) - boardid = Data; - } - else - { - printk("bthomehubv2b: Failed to get uboot_env_page"); - } - - if (!mac) { - goto error_fail; - } - - if (!boardid) { - goto error_fail; - } - - /* Sanity check the string we're looking at */ - for (i = 0; i < 5; i++) { - if (*(mac + (i * 3) + 2) != ':') { - goto error_fail; - } - } - - for (i = 0; i < 6; i++) { - int byte; - byte = bthomehubv2b_parse_hex_byte(mac + (i * 3)); - if (byte < 0) { - goto error_fail; - } - addr[i] = byte; - } - - if (gotmac) - printk("bthomehubv2b: Found ethernet MAC address: "); - else - printk("bthomehubv2b: using default MAC (pls set ethaddr in u-boot): "); - - for (i = 0; i < 6; i++) - printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); - - memcpy(<q_eth_data.mac.sa_data, addr, 6); - ltq_register_etop(<q_eth_data); - - //memcpy(&bthomehubv2b_ath5k_eeprom_mac, addr, 6); - //bthomehubv2b_ath5k_eeprom_mac[5]++; - - if (gotboardid) - printk("bthomehubv2b: Board id is %s.", boardid); - else - printk("bthomehubv2b: Default Board id is %s.", boardid); - - if (strncmp(boardid, "BTHHV2B", 7) == 0) { - // read in dev-wifi-ath9k - //memcpy(&bthomehubv2b_ath5k_eeprom_data, sx763_eeprom_data, ATH5K_PLAT_EEP_MAX_WORDS); - } - else { - printk("bthomehubv2b: Board id is unknown, fix uboot_env data."); - } - - - // should not unmap while we are using the ram? - if (uboot_env_page) - iounmap(uboot_env_page); - - return 0; - -error_fail: - if (uboot_env_page) - iounmap(uboot_env_page); - return -EINVAL; -} - - -#define PORTA2_HW_PASS1 0 -#define PORTA2_HW_PASS1_SC14480 1 -#define PORTA2_HW_PASS2 2 - -int porta2_hw_revision = -1; -EXPORT_SYMBOL(porta2_hw_revision); - -#define LTQ_GPIO_OUT 0x00 -#define LTQ_GPIO_IN 0x04 -#define LTQ_GPIO_DIR 0x08 -#define LTQ_GPIO_ALTSEL0 0x0C -#define LTQ_GPIO_ALTSEL1 0x10 -#define LTQ_GPIO_OD 0x14 -#define LTQ_GPIO_PUDSEL 0x1C -#define LTQ_GPIO_PUDEN 0x20 - -#ifdef USE_BTHH_GPIO_INIT -static void bthomehubv2b_board_prom_init(void) -{ - int revision = 0; - unsigned int gpio = 0; - void __iomem *mem = ioremap(LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE*2); - -#define DANUBE_GPIO_P0_OUT (unsigned short *)(mem + LTQ_GPIO_OUT) -#define DANUBE_GPIO_P0_IN (unsigned short *)(mem + LTQ_GPIO_IN) -#define DANUBE_GPIO_P0_DIR (unsigned short *)(mem + LTQ_GPIO_DIR) -#define DANUBE_GPIO_P0_ALTSEL0 (unsigned short *)(mem + LTQ_GPIO_ALTSEL0) -#define DANUBE_GPIO_P0_ALTSEL1 (unsigned short *)(mem + LTQ_GPIO_ALTSEL1) - -#define DANUBE_GPIO_P1_OUT (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_OUT) -#define DANUBE_GPIO_P1_IN (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_IN) -#define DANUBE_GPIO_P1_DIR (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_DIR) -#define DANUBE_GPIO_P1_ALTSEL0 (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_ALTSEL0) -#define DANUBE_GPIO_P1_ALTSEL1 (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_ALTSEL1) -#define DANUBE_GPIO_P1_OD (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_OD) - - printk("About to sense board using GPIOs at %8.8X\n", (unsigned int)mem); - - - /* First detect HW revision of the board. For that we need to set the GPIO - * lines according to table 7.2.1/7.2.2 in HSI */ - *DANUBE_GPIO_P0_OUT = 0x0200; - *DANUBE_GPIO_P0_DIR = 0x2610; - *DANUBE_GPIO_P0_ALTSEL0 = 0x7812; - *DANUBE_GPIO_P0_ALTSEL1 = 0x0000; - - *DANUBE_GPIO_P1_OUT = 0x7008; - *DANUBE_GPIO_P1_DIR = 0xF3AE; - *DANUBE_GPIO_P1_ALTSEL0 = 0x83A7; - *DANUBE_GPIO_P1_ALTSEL1 = 0x0400; - - gpio = (*DANUBE_GPIO_P0_IN & 0xFFFF) | - ((*DANUBE_GPIO_P1_IN & 0xFFFF) << 16); - - revision |= (gpio & (1 << 27)) ? (1 << 0) : 0; - revision |= (gpio & (1 << 20)) ? (1 << 1) : 0; - revision |= (gpio & (1 << 8)) ? (1 << 2) : 0; - revision |= (gpio & (1 << 6)) ? (1 << 3) : 0; - revision |= (gpio & (1 << 5)) ? (1 << 4) : 0; - revision |= (gpio & (1 << 0)) ? (1 << 5) : 0; - - porta2_hw_revision = revision; - printk("PORTA2: detected HW revision %d\n", revision); - - /* Set GPIO lines according to HW revision. */ - /* !!! Note that we are setting SPI_CS5 (GPIO 9) to be GPIO out with value - * of HIGH since the FXO does not use the SPI CS mechanism, it does it - * manually by controlling the GPIO line. We need the CS line to be disabled - * (HIGH) until needed since it will intefere with other devices on the SPI - * bus. */ - *DANUBE_GPIO_P0_OUT = 0x0200; - /* - * During the manufacturing process a different machine takes over uart0 - * so set it as input (so it wouldn't drive the line) - */ -#define cCONFIG_SHC_BT_MFG_TEST 0 - *DANUBE_GPIO_P0_DIR = 0x2671 | (cCONFIG_SHC_BT_MFG_TEST ? 0 : (1 << 12)); - - if (revision == PORTA2_HW_PASS1_SC14480 || revision == PORTA2_HW_PASS2) - *DANUBE_GPIO_P0_ALTSEL0 = 0x7873; - else - *DANUBE_GPIO_P0_ALTSEL0 = 0x3873; - - *DANUBE_GPIO_P0_ALTSEL1 = 0x0001; - - - //################################################################################### - // Register values before patch - // P1_ALTSEL0 = 0x83A7 - // P1_ALTSEL1 = 0x0400 - // P1_OU T = 0x7008 - // P1_DIR = 0xF3AE - // P1_OD = 0xE3Fc - printk("\nApplying Patch for CPU1 IRQ Issue\n"); - *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<12); // switch P1.12 (GPIO28) to GPIO functionality - *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<12); // switch P1.12 (GPIO28) to GPIO functionality - *DANUBE_GPIO_P1_OUT &= ~(1<<12); // set P1.12 (GPIO28) to 0 - *DANUBE_GPIO_P1_DIR |= (1<<12); // configure P1.12 (GPIO28) as output - *DANUBE_GPIO_P1_OD |= (1<<12); // activate Push/Pull mode - udelay(100); // wait a little bit (100us) - *DANUBE_GPIO_P1_OD &= ~(1<<12); // switch back from Push/Pull to Open Drain - // important: before! setting output to 1 (3,3V) the mode must be switched - // back to Open Drain because the reset pin of the SC14488 is internally - // pulled to 1,8V - *DANUBE_GPIO_P1_OUT |= (1<<12); // set output P1.12 (GPIO28) to 1 - // Register values after patch, should be the same as before - // P1_ALTSEL0 = 0x83A7 - // P1_ALTSEL1 = 0x0400 - // P1_OUT = 0x7008 - // P1_DIR = 0xF3AE - // P1_OD = 0xE3Fc - //################################################################################### - - - *DANUBE_GPIO_P1_OUT = 0x7008; - *DANUBE_GPIO_P1_DIR = 0xEBAE | (revision == PORTA2_HW_PASS2 ? 0x1000 : 0); - *DANUBE_GPIO_P1_ALTSEL0 = 0x8BA7; - *DANUBE_GPIO_P1_ALTSEL1 = 0x0400; - - iounmap(mem); -} -#endif -static void __init bthomehubv2b_init(void) { -#define bthomehubv2b_USB 13 - - // read the board version -#ifdef USE_BTHH_GPIO_INIT - bthomehubv2b_board_prom_init(); -#endif - - // register extra GPPOs used by LEDs as GPO 0x200+ - ltq_register_gpio_stp(); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(bthomehubv2b_gpio_leds), bthomehubv2b_gpio_leds); - bthhv2b_register_nor(&bthomehubv2b_flash_data); - xway_register_nand(bthomehubv2b_nand_partitions, ARRAY_SIZE(bthomehubv2b_nand_partitions)); - ltq_register_pci(<q_pci_data); - ltq_register_tapi(); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(bthomehubv2b_gpio_keys), bthomehubv2b_gpio_keys); -// ltq_register_ath9k(); - xway_register_dwc(bthomehubv2b_USB); - bthomehubv2b_register_ethernet(); - -} - -MIPS_MACHINE(LANTIQ_MACH_BTHOMEHUBV2BOPENRG, - "BTHOMEHUBV2BOPENRG", - "BTHOMEHUBV2B - BT Homehub V2.0 Type B with OpenRG image retained", - bthomehubv2b_init); - -MIPS_MACHINE(LANTIQ_MACH_BTHOMEHUBV2B, - "BTHOMEHUBV2B", - "BTHOMEHUBV2B - BT Homehub V2.0 Type B", - bthomehubv2b_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-fritz_ar9.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-fritz_ar9.c deleted file mode 100644 index 5bd6341809..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-fritz_ar9.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/input.h> -#include <linux/phy.h> -#include <linux/spi/spi_gpio.h> -#include <linux/spi/flash.h> - -#include <lantiq_soc.h> -#include <irq.h> - -#include "../machtypes.h" -#include "devices.h" -#include "dev-ifxhcd.h" -#include "dev-gpio-leds.h" -#include "dev-gpio-buttons.h" - -static struct mtd_partition fritz7320_partitions[] = { - { - .name = "urlader", - .offset = 0x0, - .size = 0x20000, - }, - { - .name = "linux", - .offset = 0x20000, - .size = 0xf60000, - }, - { - .name = "tffs (1)", - .offset = 0xf80000, - .size = 0x40000, - }, - { - .name = "tffs (2)", - .offset = 0xfc0000, - .size = 0x40000, - }, -}; - -static struct physmap_flash_data fritz7320_flash_data = { - .nr_parts = ARRAY_SIZE(fritz7320_partitions), - .parts = fritz7320_partitions, -}; - -static struct gpio_led -fritz7320_gpio_leds[] __initdata = { - { .name = "soc:green:power", .gpio = 44, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:internet", .gpio = 47, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:dect", .gpio = 38, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:wlan", .gpio = 37, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:dual1", .gpio = 35, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:dual2", .gpio = 45, .active_low = 1, .default_trigger = "default-on" }, -}; - -static struct gpio_keys_button -fritz7320_gpio_keys[] __initdata = { - { - .desc = "wifi", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 1, - .active_low = 1, - }, - { - .desc = "dect", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 2, - .active_low = 1, - }, -}; - -static struct ltq_pci_data ltq_pci_data = { - .clock = PCI_CLOCK_INT, - .gpio = PCI_GNT1 | PCI_REQ1, - .irq = { - [14] = INT_NUM_IM0_IRL0 + 22, - }, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_RMII, -}; - -static int usb_pins[2] = { 50, 51 }; - -static void __init -fritz7320_init(void) -{ - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, - ARRAY_SIZE(fritz7320_gpio_keys), fritz7320_gpio_keys); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(fritz7320_gpio_leds), fritz7320_gpio_leds); - ltq_register_pci(<q_pci_data); - ltq_register_etop(<q_eth_data); - ltq_register_nor(&fritz7320_flash_data); - xway_register_hcd(usb_pins); -} - -MIPS_MACHINE(LANTIQ_MACH_FRITZ7320, - "FRITZ7320", - "FRITZ!BOX 7320", - fritz7320_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-fritz_vr9.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-fritz_vr9.c deleted file mode 100644 index 293c7b750a..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-fritz_vr9.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/input.h> -#include <linux/phy.h> -#include <linux/spi/spi_gpio.h> -#include <linux/spi/flash.h> - -#include <lantiq_soc.h> -#include <irq.h> - -#include "../machtypes.h" -#include "devices.h" -#include "dev-ifxhcd.h" -#include "dev-gpio-leds.h" -#include "dev-gpio-buttons.h" - -static struct mtd_partition fritz3370_partitions[] = { - { - .name = "linux", - .offset = 0x0, - .size = 0x400000, - }, - { - .name = "filesystem", - .offset = 0x400000, - .size = 0x3000000, - }, - { - .name = "reserved-kernel", - .offset = 0x3400000, - .size = 0x400000, - }, - { - .name = "reserved", - .offset = 0x3800000, - .size = 0x3000000, - }, - { - .name = "config", - .offset = 0x6800000, - .size = 0x200000, - }, - { - .name = "nand-filesystem", - .offset = 0x6a00000, - .size = 0x1600000, - }, -}; - -static struct mtd_partition spi_flash_partitions[] = { - { - .name = "urlader", - .offset = 0x0, - .size = 0x20000, - }, - { - .name = "tffs", - .offset = 0x20000, - .size = 0x10000, - }, - { - .name = "tffs", - .offset = 0x30000, - .size = 0x10000, - }, -}; - -static struct gpio_led -fritz3370_gpio_leds[] __initdata = { - { .name = "soc:green:1", .gpio = 32, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:2", .gpio = 33, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:red:3", .gpio = 34, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:4", .gpio = 35, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:5", .gpio = 36, .active_low = 1, .default_trigger = "default-on" }, - { .name = "soc:green:6", .gpio = 47, .active_low = 1, .default_trigger = "default-on" }, -}; - -static struct gpio_keys_button -fritz3370_gpio_keys[] __initdata = { - { - .desc = "wifi", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 29, - .active_low = 1, - }, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_RMII, -}; - -static int usb_pins[2] = { 5, 14 }; - -#define SPI_GPIO_MRST 16 -#define SPI_GPIO_MTSR 17 -#define SPI_GPIO_CLK 18 -#define SPI_GPIO_CS0 10 - -static struct spi_gpio_platform_data spi_gpio_data = { - .sck = SPI_GPIO_CLK, - .mosi = SPI_GPIO_MTSR, - .miso = SPI_GPIO_MRST, - .num_chipselect = 2, -}; - -static struct platform_device spi_gpio_device = { - .name = "spi_gpio", - .dev.platform_data = &spi_gpio_data, -}; - -static struct flash_platform_data spi_flash_data = { - .name = "SPL", - .parts = spi_flash_partitions, - .nr_parts = ARRAY_SIZE(spi_flash_partitions), -}; - -static struct spi_board_info spi_flash __initdata = { - .modalias = "m25p80", - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 10 * 1000 * 1000, - .mode = SPI_MODE_3, - .chip_select = 0, - .controller_data = (void *) SPI_GPIO_CS0, - .platform_data = &spi_flash_data -}; - -static void __init -spi_gpio_init(void) -{ - spi_register_board_info(&spi_flash, 1); - platform_device_register(&spi_gpio_device); -} - -static void __init -fritz3370_init(void) -{ - spi_gpio_init(); - platform_device_register_simple("pcie-xway", 0, NULL, 0); - xway_register_nand(fritz3370_partitions, ARRAY_SIZE(fritz3370_partitions)); - xway_register_hcd(usb_pins); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(fritz3370_gpio_leds), fritz3370_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, - ARRAY_SIZE(fritz3370_gpio_keys), fritz3370_gpio_keys); - ltq_register_vrx200(<q_eth_data); -} - -MIPS_MACHINE(LANTIQ_MACH_FRITZ3370, - "FRITZ3370", - "FRITZ!BOX 3370", - fritz3370_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-gigasx76x.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-gigasx76x.c deleted file mode 100644 index af27825cbb..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-gigasx76x.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Andrej VlaÅ¡ić - * Copyright (C) 2011 Luka Perkov - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/input.h> -#include <linux/pci.h> -#include <linux/phy.h> -#include <linux/io.h> -#include <linux/if_ether.h> -#include <linux/etherdevice.h> -#include <linux/string.h> - -#include <irq.h> -#include <lantiq_soc.h> -#include <lantiq_platform.h> -#include <dev-gpio-leds.h> -#include <dev-gpio-buttons.h> - -#include "../machtypes.h" -#include "dev-wifi-athxk.h" -#include "devices.h" -#include "dev-dwc_otg.h" - -#include "mach-gigasx76x.h" - -static u8 ltq_ethaddr[6] = { 0 }; - -static int __init -setup_ethaddr(char *str) -{ - if (!mac_pton(str, ltq_ethaddr)) - memset(ltq_ethaddr, 0, 6); - return 0; -} -__setup("ethaddr=", setup_ethaddr); - - -enum { - UNKNOWN = 0, - SX761, - SX762, - SX763, -}; -static u8 board __initdata = SX763; - -static int __init -setup_board(char *str) -{ - if (!strcmp(str, "sx761")) - board = SX761; - else if (!strcmp(str, "sx762")) - board = SX762; - else if (!strcmp(str, "sx763")) - board = SX763; - else - board = UNKNOWN; - return 0; -} -__setup("board=", setup_board); - -static struct mtd_partition gigasx76x_partitions[] = -{ - { - .name = "uboot", - .offset = 0x0, - .size = 0x10000, - }, - { - .name = "uboot_env", - .offset = 0x10000, - .size = 0x10000, - }, - { - .name = "linux", - .offset = 0x20000, - .size = 0x7e0000, - }, -}; - -static struct gpio_led -gigasx76x_gpio_leds[] __initdata = { - { .name = "soc:green:voip", .gpio = 216, }, - { .name = "soc:green:adsl", .gpio = 217, }, - { .name = "soc:green:usb", .gpio = 218, }, - { .name = "soc:green:wifi", .gpio = 219, }, - { .name = "soc:green:phone2", .gpio = 220, }, - { .name = "soc:green:phone1", .gpio = 221, }, - { .name = "soc:green:line", .gpio = 222, }, - { .name = "soc:green:online", .gpio = 223, }, -}; - -static struct gpio_keys_button -gigasx76x_gpio_keys[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 22, - .active_low = 1, - }, - { - .desc = "reset", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 14, - .active_low = 0, - }, -}; - -static struct physmap_flash_data gigasx76x_flash_data = { - .nr_parts = ARRAY_SIZE(gigasx76x_partitions), - .parts = gigasx76x_partitions, -}; - -static struct ltq_pci_data ltq_pci_data = { - .clock = PCI_CLOCK_INT, - .gpio = PCI_GNT1 | PCI_REQ1, - .irq = { [14] = INT_NUM_IM0_IRL0 + 22, }, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_MII, -}; - -static void __init -gigasx76x_init(void) -{ -#define GIGASX76X_USB 29 - - ltq_register_gpio_stp(); - ltq_register_nor(&gigasx76x_flash_data); - ltq_register_pci(<q_pci_data); - ltq_register_tapi(); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(gigasx76x_gpio_leds), gigasx76x_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(gigasx76x_gpio_keys), gigasx76x_gpio_keys); - xway_register_dwc(GIGASX76X_USB); - - if (!is_valid_ether_addr(ltq_ethaddr)) - random_ether_addr(ltq_ethaddr); - - memcpy(<q_eth_data.mac.sa_data, ltq_ethaddr, 6); - ltq_register_etop(<q_eth_data); - if (board == SX762) - ltq_register_ath5k(sx762_eeprom_data, ltq_ethaddr); - else - ltq_register_ath5k(sx763_eeprom_data, ltq_ethaddr); -} - -MIPS_MACHINE(LANTIQ_MACH_GIGASX76X, - "GIGASX76X", - "GIGASX76X - Gigaset SX761,SX762,SX763", - gigasx76x_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-gigasx76x.h b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-gigasx76x.h deleted file mode 100644 index 74e5ba28fe..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-gigasx76x.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Andrej VlaÅ¡ić - * Copyright (C) 2011 Luka Perkov - * - */ - -#ifndef _MACH_GIGASX76X_H__ -#define _MACH_GIGASX76X_H__ - -#include <linux/ath5k_platform.h> - -static u16 sx763_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS] = -{ -0x0013,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100, -0x0000,0x01c2,0x0002,0xc606,0x0001,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xf165,0x7fbe,0x0003,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x5aa5,0x0000,0x0000,0x0313,0x4943, -0x2053,0x7104,0x1202,0x0400,0x0306,0x0001,0x0000,0x0500,0x410e,0x39b1,0x1eb5, -0x4e2d,0x3056,0xffff,0xe902,0x0700,0x0106,0x0000,0x0100,0x1500,0x0752,0x4101, -0x6874,0x7265,0x736f,0x4320,0x6d6f,0x756d,0x696e,0x6163,0x6974,0x6e6f,0x2c73, -0x4920,0x636e,0x002e,0x5241,0x3035,0x3130,0x302d,0x3030,0x2d30,0x3030,0x3030, -0x5700,0x7269,0x6c65,0x7365,0x2073,0x414c,0x204e,0x6552,0x6566,0x6572,0x636e, -0x2065,0x6143,0x6472,0x3000,0x0030,0x00ff,0x2100,0x0602,0x2201,0x0205,0x8d80, -0x005b,0x0522,0x4002,0x8954,0x2200,0x0205,0x1b00,0x00b7,0x0522,0x8002,0x12a8, -0x2201,0x0205,0x3600,0x016e,0x0522,0x0002,0x2551,0x2202,0x0205,0x6c00,0x02dc, -0x0522,0x8002,0x37f9,0x2203,0x0205,0xa200,0x044a,0x0222,0x0803,0x0822,0x0604, -0x0300,0xbe7f,0x65f1,0x0222,0x0105,0x00ff,0x0000,0x0000,0x0000,0x0000,0x0000, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0x0037,0x971f,0x5003,0x9a66,0x0001,0x81c4,0x016a, -0x02ff,0x84ff,0x15a3,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x2d2c,0x0000,0x0000,0x0000,0x0000,0xe028,0xa492,0x1c00, -0x000e,0xb8ca,0x0013,0x0000,0x0000,0x6b4b,0xc059,0x1571,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x2370,0x00a5,0x9618,0x419a,0x68a2,0xda35,0x001c,0x0007,0xb0ff,0x01b5,0x0000, -0x0000,0xff70,0x19ff,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x3170,0x00a5,0x9618,0x419a,0x68a2,0xda35, -0x001c,0x000e,0xb0ff,0x21b5,0x0000,0x2fd8,0xff70,0x1226,0x19ff,0x07be,0x6201, -0x032e,0x0587,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x1112, -0x1441,0x4231,0x3234,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x8000,0x0000,0x0000,0x0000,0x0000,0x8000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x4d31,0x7f54,0x3c93,0x1205,0x1931, -0x492d,0x7f50,0x3c93,0x0e01,0x192d,0x0070,0x0000,0x8140,0x724b,0x2ba9,0x3a09, -0x99d9,0x1949,0x0070,0x0000,0x80e0,0x624a,0x2af8,0x35c7,0x9d47,0x1938,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x7082,0x0820,0xb882,0x0820,0x7092,0x28a0,0x8992, -0x28a0,0xa292,0x28a0,0x70a2,0xa7ac,0x0000,0x0000,0x2464,0x6424,0x0000,0x0000, -0x70a2,0xa7ac,0x0000,0x0000,0x2464,0x6424,0x0000,0x0000,0x8989,0x0000,0x0000, -0x0000,0x2424,0x0000,0x0000,0x0000,0x7075,0xa2ac,0xb800,0x0000,0x2464,0x2424, -0x2400,0x0000,0x7075,0xa2ac,0x0000,0x0000,0x2464,0x2424,0x0000,0x0000,0x7075, -0xa7ac,0x0000,0x0000,0x2464,0x6424,0x0000,0x0000,0x7075,0xa7ac,0x0000,0x0000, -0x2464,0x6424,0x0000,0x0000,0x8989,0x0000,0x0000,0x0000,0x2424,0x0000,0x0000, -0x0000,0x0000,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff}; - -static u16 sx762_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS] = -{ -0x001a,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100, -0x0000,0x01c2,0x0002,0xc606,0x0001,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xf165,0x7fbe,0x0003,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x5aa5,0x0000,0x0000,0x0313,0x4943, -0x2053,0x7104,0x1202,0x0400,0x0306,0x0001,0x0000,0x0500,0x410e,0x39b1,0x1eb5, -0x4e2d,0x3056,0xffff,0xe902,0x0700,0x0106,0x0000,0x0100,0x1500,0x0752,0x4101, -0x6874,0x7265,0x736f,0x4320,0x6d6f,0x756d,0x696e,0x6163,0x6974,0x6e6f,0x2c73, -0x4920,0x636e,0x002e,0x5241,0x3035,0x3130,0x302d,0x3030,0x2d30,0x3030,0x3030, -0x5700,0x7269,0x6c65,0x7365,0x2073,0x414c,0x204e,0x6552,0x6566,0x6572,0x636e, -0x2065,0x6143,0x6472,0x3000,0x0030,0x00ff,0x2100,0x0602,0x2201,0x0205,0x8d80, -0x005b,0x0522,0x4002,0x8954,0x2200,0x0205,0x1b00,0x00b7,0x0522,0x8002,0x12a8, -0x2201,0x0205,0x3600,0x016e,0x0522,0x0002,0x2551,0x2202,0x0205,0x6c00,0x02dc, -0x0522,0x8002,0x37f9,0x2203,0x0205,0xa200,0x044a,0x0222,0x0803,0x0822,0x0604, -0x0300,0xbe7f,0x65f1,0x0222,0x0105,0x00ff,0x0000,0x0000,0x0000,0x0000,0x0000, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0x0037,0x6aaa,0x5003,0x9a66,0x0001,0x81c4,0x016a, -0x02ff,0x84ff,0x15a3,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x2d2c,0x0000,0x0000,0x0000,0x0000,0xe028,0xa492,0x1c00, -0x000e,0xb8ca,0x0013,0x0000,0x0000,0x6b4b,0xc059,0x1571,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x2370,0x00a5,0x9618,0x419a,0x68a2,0xda35,0x001c,0x0007,0xb0ff,0x01b5,0x0000, -0x0000,0xff70,0x19ff,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x3170,0x00a5,0x9618,0x419a,0x68a2,0xda35, -0x001c,0x000e,0xb0ff,0x21b5,0x0000,0x2fd8,0xff70,0x1226,0x19ff,0x07fa,0x6201, -0x032e,0x0587,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x1112, -0x1441,0x4231,0x3234,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x8000,0x0000,0x0000,0x0000,0x0000,0x8000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x4d31,0x7f54,0x3c93,0x1205,0x1931, -0x492d,0x7f50,0x3c93,0x0e01,0x192d,0x0070,0x0000,0x8180,0x724d,0xab59,0x3a08, -0xdd79,0x2559,0x0070,0x0000,0x81a0,0x6e4d,0x2b99,0x3a09,0x9989,0x2157,0x0000, -0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, -0x0000,0x0000,0x0000,0x0000,0x7092,0x4924,0xb892,0x4924,0x7092,0x289e,0x8992, -0x289e,0xa292,0x289e,0x70a2,0xa7ac,0x0000,0x0000,0x2462,0x5e13,0x0000,0x0000, -0x70a2,0xa7ac,0x0000,0x0000,0x1e5c,0x5713,0x0000,0x0000,0x8989,0x0000,0x0000, -0x0000,0x2424,0x0000,0x0000,0x0000,0x7075,0xa2ac,0xb800,0x0000,0x2868,0x2828, -0x2800,0x0000,0x7075,0xa2ac,0x0000,0x0000,0x2868,0x2828,0x0000,0x0000,0x7075, -0xac00,0x0000,0x0000,0x2161,0x2100,0x0000,0x0000,0x7075,0xac00,0x0000,0x0000, -0x1b5b,0x1b00,0x0000,0x0000,0x8989,0x0000,0x0000,0x0000,0x2121,0x0000,0x0000, -0x0000,0x0000,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff, -0xffff,0xffff}; - -#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-h201l.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-h201l.c deleted file mode 100644 index 86101f5888..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-h201l.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2012 Luka Perkov <openwrt@lukaperkov.net> - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/input.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/if_ether.h> -#include <linux/etherdevice.h> -#include <linux/string.h> - -#include <lantiq_soc.h> -#include <lantiq_platform.h> -#include <dev-gpio-leds.h> -#include <dev-gpio-buttons.h> - -#include "../machtypes.h" -#include "devices.h" -#include "dev-dwc_otg.h" - -static u8 ltq_ethaddr[6] = { 0 }; - -static int __init -setup_ethaddr(char *str) -{ - if (!mac_pton(str, ltq_ethaddr)) - memset(ltq_ethaddr, 0, 6); - return 0; -} -__setup("ethaddr=", setup_ethaddr); - -static struct mtd_partition h201l_partitions[] __initdata = -{ - { - .name = "uboot", - .offset = 0x0, - .size = 0x20000, - }, - { - .name = "uboot_env", - .offset = 0x20000, - .size = 0x10000, - }, - { - .name = "linux", - .offset = 0x30000, - .size = 0x7d0000, - }, -}; - -static struct physmap_flash_data h201l_flash_data __initdata = { - .nr_parts = ARRAY_SIZE(h201l_partitions), - .parts = h201l_partitions, -}; - -static struct gpio_led -h201l_leds_gpio[] __initdata = { -}; - -static struct gpio_keys_button -h201l_gpio_keys[] __initdata = { -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_RMII, -}; - -static void __init -h201l_init(void) -{ - ltq_register_gpio_stp(); - ltq_register_nor(&h201l_flash_data); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(h201l_leds_gpio), h201l_leds_gpio); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(h201l_gpio_keys), h201l_gpio_keys); - - if (!is_valid_ether_addr(ltq_ethaddr)) - random_ether_addr(ltq_ethaddr); - - memcpy(<q_eth_data.mac.sa_data, ltq_ethaddr, 6); - ltq_register_etop(<q_eth_data); - - xway_register_dwc(-1); -} - -MIPS_MACHINE(LANTIQ_MACH_H201L, - "H201L", - "ZTE ZXV10 H201L", - h201l_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-netgear.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-netgear.c deleted file mode 100644 index 29b0728102..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-netgear.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - * Copyright (C) 2012 Pieter Voorthuijsen <p.voorthuijsen@gmail.com> - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/input.h> -#include <linux/phy.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi_gpio.h> -#include <linux/ath9k_platform.h> -#include <linux/if_ether.h> -#include <linux/etherdevice.h> -#include <linux/kobject.h> -#include <linux/sysfs.h> - -#include <lantiq_soc.h> -#include <irq.h> -#include <dev-gpio-leds.h> -#include <dev-gpio-buttons.h> -#include "dev-wifi-athxk.h" - -#include "../machtypes.h" -#include "devices.h" -#include "dev-dwc_otg.h" -#include "pci-ath-fixup.h" -#include <mtd/mtd-abi.h> -#include <asm-generic/sizes.h> - -static struct mtd_partition dgn3500_partitions[] = { - { - .name = "u-boot", - .offset = 0, - .size = 0x10000, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "environment", - .offset = 0x10000, - .size = 0x10000, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "calibration", - .offset = 0x20000, - .size = 0x10000, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "linux", - .offset = 0x50000, - .size = 0xfa0000, - }, -}; - -static struct ltq_pci_data ltq_pci_data = { - .clock = PCI_CLOCK_INT, - .gpio = PCI_GNT1 | PCI_REQ1, - .irq = { - [14] = INT_NUM_IM0_IRL0 + 22, - }, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_MII, -}; - -static struct gpio_led -dgn3500_gpio_leds[] __initdata = { - { .name = "soc:green:power", .gpio = 34, .active_low = 1, }, - { .name = "soc:red:power", .gpio = 39, .active_low = 1, }, - { .name = "soc:orange:wlan", .gpio = 51, .active_low = 1, }, - { .name = "soc:green:wps", .gpio = 52, .active_low = 1, }, - { .name = "soc:green:usb", .gpio = 22, .active_low = 1, }, - { .name = "soc:green:dsl", .gpio = 4, .active_low = 1, }, - { .name = "soc:green:internet", .gpio = 2, .active_low = 1, }, -}; - -static struct gpio_keys_button -dgn3500_gpio_keys[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 54, - .active_low = 1, - }, - { - .desc = "reset", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 36, - .active_low = 1, - }, -}; - -#define SPI_GPIO_MRST 16 -#define SPI_GPIO_MTSR 17 -#define SPI_GPIO_CLK 18 -#define SPI_GPIO_CS0 10 - -static struct spi_gpio_platform_data spi_gpio_data = { - .sck = SPI_GPIO_CLK, - .mosi = SPI_GPIO_MTSR, - .miso = SPI_GPIO_MRST, - .num_chipselect = 2, -}; - -static struct platform_device spi_gpio_device = { - .name = "spi_gpio", - .dev.platform_data = &spi_gpio_data, -}; - -static struct flash_platform_data spi_flash_data = { - .name = "sflash", - .parts = dgn3500_partitions, - .nr_parts = ARRAY_SIZE(dgn3500_partitions), -}; - -static struct spi_board_info spi_flash __initdata = { - .modalias = "m25p80", - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 10 * 1000 * 1000, - .mode = SPI_MODE_3, - .chip_select = 0, - .controller_data = (void *) SPI_GPIO_CS0, - .platform_data = &spi_flash_data -}; - -static u8 ltq_ethaddr[6] = { 0 }; - -static int __init setup_ethaddr(char *str) -{ - if (!mac_pton(str, ltq_ethaddr)) - memset(ltq_ethaddr, 0, 6); - return 0; -} -__setup("ethaddr=", setup_ethaddr); - -static u16 dgn3500_eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS] = {0}; - -static ssize_t ath_eeprom_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, char *buf, - loff_t offset, size_t count) -{ - if (unlikely(offset >= sizeof(dgn3500_eeprom_data))) - return 0; - if ((offset + count) > sizeof(dgn3500_eeprom_data)) - count = sizeof(dgn3500_eeprom_data) - offset; - if (unlikely(!count)) - return count; - - memcpy(buf, (char *)(dgn3500_eeprom_data) + offset, count); - - return count; -} - -extern struct ath9k_platform_data ath9k_pdata; - -static ssize_t ath_eeprom_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, char *buf, - loff_t offset, size_t count) -{ - int i; - char *eeprom_bytes = (char *)dgn3500_eeprom_data; - - if (unlikely(offset >= sizeof(dgn3500_eeprom_data))) - return -EFBIG; - if ((offset + count) > sizeof(dgn3500_eeprom_data)) - count = sizeof(dgn3500_eeprom_data) - offset; - if (unlikely(!count)) - return count; - if (count % 2) - return 0; - - /* The PCI fixup routine requires an endian swap of the calibartion data - * stored in flash */ - for (i = 0; i < count; i += 2) { - eeprom_bytes[offset + i + 1] = buf[i]; - eeprom_bytes[offset + i] = buf[i+1]; - } - - /* The original data does not contain a checksum. Set the country and - * calculate new checksum when all data is received */ - if ((count + offset) == sizeof(dgn3500_eeprom_data)) - memcpy(ath9k_pdata.eeprom_data, dgn3500_eeprom_data, - sizeof(ath9k_pdata.eeprom_data)); - - return count; -} - -static struct bin_attribute dev_attr_ath_eeprom = { - .attr = { - .name = "ath_eeprom", - .mode = S_IRUGO|S_IWUSR, - }, - .read = ath_eeprom_read, - .write = ath_eeprom_write, -}; - -static void __init dgn3500_init(void) -{ - if (sysfs_create_bin_file(firmware_kobj, &dev_attr_ath_eeprom)) - printk(KERN_INFO "Failed to create ath eeprom sysfs entry\n"); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(dgn3500_gpio_leds), - dgn3500_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, - ARRAY_SIZE(dgn3500_gpio_keys), dgn3500_gpio_keys); - platform_device_register(&spi_gpio_device); - ltq_register_pci(<q_pci_data); - spi_register_board_info(&spi_flash, 1); - if (!is_valid_ether_addr(ltq_ethaddr)) { - printk(KERN_INFO "MAC invalid using random\n"); - random_ether_addr(ltq_ethaddr); - } - memcpy(<q_eth_data.mac.sa_data, ltq_ethaddr, 6); - ltq_register_etop(<q_eth_data); - ltq_register_ath9k(dgn3500_eeprom_data, ltq_ethaddr); - ltq_pci_ath_fixup(14, dgn3500_eeprom_data); - /* The usb power is always enabled, protected by a fuse */ - xway_register_dwc(-1); -} - -MIPS_MACHINE(LANTIQ_MACH_DGN3500B, - "DGN3500B", - "Netgear DGN3500B", - dgn3500_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-p2601hnfx.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-p2601hnfx.c deleted file mode 100644 index 247dfb572c..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-p2601hnfx.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/gpio_buttons.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/input.h> -#include <linux/etherdevice.h> -#include <linux/mdio-gpio.h> -#include <linux/kernel.h> -#include <linux/delay.h> - -#include <lantiq_soc.h> -#include <lantiq_platform.h> -#include <dev-gpio-leds.h> -#include <dev-gpio-buttons.h> - -#include "../machtypes.h" -#include "devices.h" -#include "dev-dwc_otg.h" - -static struct mtd_partition p2601hnfx_partitions[] __initdata = -{ - { - .name = "uboot", - .offset = 0x0, - .size = 0x20000, - }, - { - .name = "uboot_env", - .offset = 0x20000, - .size = 0x20000, - }, - { - .name = "linux", - .offset = 0x40000, - .size = 0xfc0000, - }, -}; - -static struct physmap_flash_data p2601hnfx_flash_data __initdata = { - .nr_parts = ARRAY_SIZE(p2601hnfx_partitions), - .parts = p2601hnfx_partitions, -}; - -static struct gpio_led -p2601hnfx_leds_gpio[] __initdata = { - { .name = "soc:yellow:phone", .gpio = 216, .active_low = 1 }, - { .name = "soc:green:phone", .gpio = 217, .active_low = 1 }, - { .name = "soc:yellow:wifi", .gpio = 218, .active_low = 1 }, - { .name = "soc:green:power", .gpio = 219, .active_low = 1 }, - { .name = "soc:red:internet", .gpio = 220, .active_low = 1 }, - { .name = "soc:green:internet", .gpio = 221, .active_low = 1 }, - { .name = "soc:green:dsl", .gpio = 222, .active_low = 1 }, - { .name = "soc:green:wifi", .gpio = 223, .active_low = 1 }, -}; - -static struct gpio_keys_button -p2601hnfx_gpio_keys[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 53, - .active_low = 1, - }, - { - .desc = "wifi", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 54, - .active_low = 1, - }, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_RMII, -}; - -static void __init -p2601hnfx_init(void) -{ -#define P2601HNFX_USB 9 - - ltq_register_gpio_stp(); - ltq_register_nor(&p2601hnfx_flash_data); - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(p2601hnfx_leds_gpio), p2601hnfx_leds_gpio); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(p2601hnfx_gpio_keys), p2601hnfx_gpio_keys); - ltq_register_etop(<q_eth_data); - xway_register_dwc(P2601HNFX_USB); - - // enable the ethernet ports on the SoC -// ltq_w32((ltq_r32(LTQ_GPORT_P0_CTL) & ~(1 << 17)) | (1 << 18), LTQ_GPORT_P0_CTL); -// ltq_w32((ltq_r32(LTQ_GPORT_P1_CTL) & ~(1 << 17)) | (1 << 18), LTQ_GPORT_P1_CTL); -// ltq_w32((ltq_r32(LTQ_GPORT_P2_CTL) & ~(1 << 17)) | (1 << 18), LTQ_GPORT_P2_CTL); -} - -MIPS_MACHINE(LANTIQ_MACH_P2601HNFX, - "P2601HNFX", - "ZyXEL P-2601HN-Fx", - p2601hnfx_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-wbmr.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-wbmr.c deleted file mode 100644 index a57e092123..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-wbmr.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/gpio_buttons.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/input.h> - -#include <lantiq_soc.h> -#include <irq.h> -#include <dev-gpio-leds.h> -#include <dev-gpio-buttons.h> - -#include "../machtypes.h" -#include "devices.h" -#include "dev-dwc_otg.h" - -static struct mtd_partition wbmr_partitions[] = -{ - { - .name = "uboot", - .offset = 0x0, - .size = 0x40000, - }, - { - .name = "uboot-env", - .offset = 0x40000, - .size = 0x20000, - }, - { - .name = "linux", - .offset = 0x60000, - .size = 0x1f20000, - }, - { - .name = "calibration", - .offset = 0x1fe0000, - .size = 0x20000, - }, -}; - -static struct physmap_flash_data wbmr_flash_data = { - .nr_parts = ARRAY_SIZE(wbmr_partitions), - .parts = wbmr_partitions, -}; - -static struct gpio_led -wbmr_gpio_leds[] __initdata = { - { .name = "soc:blue:movie", .gpio = 20, .active_low = 1, }, - { .name = "soc:red:internet", .gpio = 18, .active_low = 1, }, - { .name = "soc:green:internet", .gpio = 17, .active_low = 1, }, - { .name = "soc:green:adsl", .gpio = 16, .active_low = 1, }, - { .name = "soc:green:wlan", .gpio = 15, .active_low = 1, }, - { .name = "soc:red:security", .gpio = 14, .active_low = 1, }, - { .name = "soc:green:power", .gpio = 1, .active_low = 1, }, - { .name = "soc:red:power", .gpio = 5, .active_low = 1, }, - { .name = "soc:green:usb", .gpio = 28, .active_low = 1, }, -}; - -static struct gpio_keys_button -wbmr_gpio_keys[] __initdata = { - { - .desc = "aoss", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 0, - .active_low = 1, - }, - { - .desc = "reset", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL, - .gpio = 37, - .active_low = 1, - }, -}; - -static struct ltq_pci_data ltq_pci_data = { - .clock = PCI_CLOCK_INT, - .gpio = PCI_GNT1 | PCI_REQ1, - .irq = { - [14] = INT_NUM_IM0_IRL0 + 22, - }, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_RGMII, -}; - -static void __init -wbmr_init(void) -{ -#define WMBR_BRN_MAC 0x1fd0024 - - ltq_add_device_gpio_leds(-1, ARRAY_SIZE(wbmr_gpio_leds), wbmr_gpio_leds); - ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(wbmr_gpio_keys), wbmr_gpio_keys); - ltq_register_nor(&wbmr_flash_data); - ltq_register_pci(<q_pci_data); - memcpy_fromio(<q_eth_data.mac.sa_data, - (void *)KSEG1ADDR(LTQ_FLASH_START + WMBR_BRN_MAC), 6); - ltq_register_etop(<q_eth_data); - xway_register_dwc(36); -} - -MIPS_MACHINE(LANTIQ_MACH_WBMR, - "WBMR", - "WBMR", - wbmr_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/nand.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/nand.c deleted file mode 100644 index 9ab91d8819..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/nand.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/mtd/physmap.h> -#include <linux/mtd/nand.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <lantiq_soc.h> -#include <lantiq_irq.h> -#include <lantiq_platform.h> - -#include "devices.h" - -/* nand registers */ -#define LTQ_EBU_NAND_WAIT 0xB4 -#define LTQ_EBU_NAND_ECC0 0xB8 -#define LTQ_EBU_NAND_ECC_AC 0xBC -#define LTQ_EBU_NAND_CON 0xB0 -#define LTQ_EBU_ADDSEL1 0x24 - -/* gpio definitions */ -#define PIN_ALE 13 -#define PIN_CLE 24 -#define PIN_CS1 23 -#define PIN_RDY 48 /* NFLASH_READY */ -#define PIN_RD 49 /* NFLASH_READ_N */ - -#define NAND_CMD_ALE (1 << 2) -#define NAND_CMD_CLE (1 << 3) -#define NAND_CMD_CS (1 << 4) -#define NAND_WRITE_CMD_RESET 0xff -#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) -#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) -#define NAND_WRITE_DATA (NAND_CMD_CS) -#define NAND_READ_DATA (NAND_CMD_CS) -#define NAND_WAIT_WR_C (1 << 3) -#define NAND_WAIT_RD (0x1) - -#define ADDSEL1_MASK(x) (x << 4) -#define ADDSEL1_REGEN 1 -#define BUSCON1_SETUP (1 << 22) -#define BUSCON1_BCGEN_RES (0x3 << 12) -#define BUSCON1_WAITWRC2 (2 << 8) -#define BUSCON1_WAITRDC2 (2 << 6) -#define BUSCON1_HOLDC1 (1 << 4) -#define BUSCON1_RECOVC1 (1 << 2) -#define BUSCON1_CMULT4 1 -#define NAND_CON_NANDM 1 -#define NAND_CON_CSMUX (1 << 1) -#define NAND_CON_CS_P (1 << 4) -#define NAND_CON_SE_P (1 << 5) -#define NAND_CON_WP_P (1 << 6) -#define NAND_CON_PRE_P (1 << 7) -#define NAND_CON_IN_CS0 0 -#define NAND_CON_OUT_CS0 0 -#define NAND_CON_IN_CS1 (1 << 8) -#define NAND_CON_OUT_CS1 (1 << 10) -#define NAND_CON_CE (1 << 20) - -#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000) - -static const char *part_probes[] = { "cmdlinepart", NULL }; - -static void xway_select_chip(struct mtd_info *mtd, int chip) -{ - switch (chip) { - case -1: - ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON); - ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON); - break; - case 0: - ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON); - ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON); - /* reset the nand chip */ - while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) - ; - ltq_w32(NAND_WRITE_CMD_RESET, - ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD))); - break; - default: - BUG(); - } -} - -static void xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if (ctrl & NAND_CLE) - this->IO_ADDR_W = (void __iomem *) - (NAND_BASE_ADDRESS | NAND_WRITE_CMD); - else if (ctrl & NAND_ALE) - this->IO_ADDR_W = (void __iomem *) - (NAND_BASE_ADDRESS | NAND_WRITE_ADDR); - } - - if (data != NAND_CMD_NONE) { - *(volatile u8*) ((u32) this->IO_ADDR_W) = data; - while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) - ; - } -} - -static int xway_dev_ready(struct mtd_info *mtd) -{ - return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD; -} - -void nand_write(unsigned int addr, unsigned int val) -{ - ltq_w32(val, ((u32 *) (NAND_BASE_ADDRESS | addr))); - while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) - ; -} - -unsigned char xway_read_byte(struct mtd_info *mtd) -{ - return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); -} - -static void xway_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - { - unsigned char res8 = ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); - buf[i] = res8; - } -} - -static void xway_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - { - ltq_w8(buf[i], ((u32*)(NAND_BASE_ADDRESS | (NAND_WRITE_DATA)))); - while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); - } -} - -int xway_probe(struct platform_device *pdev) -{ - /* might need this later ? - ltq_gpio_request(PIN_CS1, 2, 1, "NAND_CS1"); - */ - ltq_gpio_request(&pdev->dev, PIN_CLE, 2, 1, "NAND_CLE"); - ltq_gpio_request(&pdev->dev, PIN_ALE, 2, 1, "NAND_ALE"); - if (ltq_is_ar9() || ltq_is_vr9()) { - ltq_gpio_request(&pdev->dev, PIN_RDY, 2, 0, "NAND_BSY"); - ltq_gpio_request(&pdev->dev, PIN_RD, 2, 1, "NAND_RD"); - } - - ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00) - | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1); - - ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 - | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 - | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); - - ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P - | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P - | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON); - - ltq_w32(NAND_WRITE_CMD_RESET, - ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD))); - while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) - ; - - return 0; -} - -static struct platform_nand_data falcon_flash_nand_data = { - .chip = { - .nr_chips = 1, - .chip_delay = 30, - .part_probe_types = part_probes, - }, - .ctrl = { - .probe = xway_probe, - .cmd_ctrl = xway_cmd_ctrl, - .dev_ready = xway_dev_ready, - .select_chip = xway_select_chip, - .read_byte = xway_read_byte, - .read_buf = xway_read_buf, - .write_buf = xway_write_buf, - } -}; - -static struct resource ltq_nand_res = - MEM_RES("nand", 0x14000000, 0x7ffffff); - -static struct platform_device ltq_flash_nand = { - .name = "gen_nand", - .id = -1, - .num_resources = 1, - .resource = <q_nand_res, - .dev = { - .platform_data = &falcon_flash_nand_data, - }, -}; - -void __init xway_register_nand(struct mtd_partition *parts, int count) -{ - falcon_flash_nand_data.chip.partitions = parts; - falcon_flash_nand_data.chip.nr_partitions = count; - platform_device_register(<q_flash_nand); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/pci-ath-fixup.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/pci-ath-fixup.c deleted file mode 100644 index c87ffb2091..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/pci-ath-fixup.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Atheros AP94 reference board PCI initialization - * - * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/pci.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <lantiq_soc.h> - -#define LTQ_PCI_MEM_BASE 0x18000000 - -struct ath_fixup { - u16 *cal_data; - unsigned slot; -}; - -static int ath_num_fixups; -static struct ath_fixup ath_fixups[2]; - -static void ath_pci_fixup(struct pci_dev *dev) -{ - void __iomem *mem; - u16 *cal_data = NULL; - u16 cmd; - u32 bar0; - u32 val; - unsigned i; - - for (i = 0; i < ath_num_fixups; i++) { - if (ath_fixups[i].cal_data == NULL) - continue; - - if (ath_fixups[i].slot != PCI_SLOT(dev->devfn)) - continue; - - cal_data = ath_fixups[i].cal_data; - break; - } - - if (cal_data == NULL) - return; - - if (*cal_data != 0xa55a) { - pr_err("pci %s: invalid calibration data\n", pci_name(dev)); - return; - } - - pr_info("pci %s: fixup device configuration\n", pci_name(dev)); - - mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000); - if (!mem) { - pr_err("pci %s: ioremap error\n", pci_name(dev)); - return; - } - - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE); - pci_read_config_word(dev, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(dev, PCI_COMMAND, cmd); - - /* set pointer to first reg address */ - cal_data += 3; - while (*cal_data != 0xffff) { - u32 reg; - reg = *cal_data++; - val = *cal_data++; - val |= (*cal_data++) << 16; - - ltq_w32(swab32(val), mem + reg); - udelay(100); - } - - pci_read_config_dword(dev, PCI_VENDOR_ID, &val); - dev->vendor = val & 0xffff; - dev->device = (val >> 16) & 0xffff; - - pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); - dev->revision = val & 0xff; - dev->class = val >> 8; /* upper 3 bytes */ - - pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n", - pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class); - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config_word(dev, PCI_COMMAND, cmd); - - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); - - iounmap(mem); -} -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup); - -void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) -{ - if (ath_num_fixups >= ARRAY_SIZE(ath_fixups)) - return; - - ath_fixups[ath_num_fixups].slot = slot; - ath_fixups[ath_num_fixups].cal_data = cal_data; - ath_num_fixups++; -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/pci-ath-fixup.h b/target/linux/lantiq/files/arch/mips/lantiq/xway/pci-ath-fixup.h deleted file mode 100644 index 095d2619ce..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/pci-ath-fixup.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _PCI_ATH_FIXUP -#define _PCI_ATH_FIXUP - -void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init; - -#endif /* _PCI_ATH_FIXUP */ diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/prom.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/prom.c deleted file mode 100644 index f776d5a914..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/prom.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/export.h> -#include <linux/clk.h> -#include <asm/bootinfo.h> -#include <asm/time.h> - -#include <lantiq_soc.h> - -#include "../prom.h" -#include "devices.h" - -#define SOC_DANUBE "Danube" -#define SOC_TWINPASS "Twinpass" -#define SOC_AMAZON_SE "Amazon_SE" -#define SOC_AR9 "AR9" -#define SOC_GR9 "GR9" -#define SOC_VR9 "VR9" - -#define PART_SHIFT 12 -#define PART_MASK 0x0FFFFFFF -#define REV_SHIFT 28 -#define REV_MASK 0xF0000000 - - -void __init ltq_soc_detect(struct ltq_soc_info *i) -{ - i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; - i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; - sprintf(i->rev_type, "1.%d", i->rev); - switch (i->partnum) { - case SOC_ID_DANUBE1: - case SOC_ID_DANUBE2: - i->name = SOC_DANUBE; - i->type = SOC_TYPE_DANUBE; - break; - - case SOC_ID_TWINPASS: - i->name = SOC_TWINPASS; - i->type = SOC_TYPE_DANUBE; - break; - - case SOC_ID_ARX188: - case SOC_ID_ARX168_1: - case SOC_ID_ARX168_2: - case SOC_ID_ARX182: - i->name = SOC_AR9; - i->type = SOC_TYPE_AR9; - break; - - case SOC_ID_GRX188: - case SOC_ID_GRX168: - i->name = SOC_GR9; - i->type = SOC_TYPE_AR9; - break; - - case SOC_ID_AMAZON_SE_1: - case SOC_ID_AMAZON_SE_2: - i->name = SOC_AMAZON_SE; - i->type = SOC_TYPE_AMAZON_SE; -#ifdef CONFIG_PCI - panic("ase is only supported for non pci kernels"); -#endif - break; - - case SOC_ID_VRX282: - case SOC_ID_VRX268: - case SOC_ID_VRX288: - i->name = SOC_VR9; - i->type = SOC_TYPE_VR9_1; - break; - - case SOC_ID_GRX268: - case SOC_ID_GRX288: - i->name = SOC_GR9; - i->type = SOC_TYPE_VR9_1; - break; - - case SOC_ID_VRX268_2: - case SOC_ID_VRX288_2: - i->name = SOC_VR9; - i->type = SOC_TYPE_VR9_2; - break; - - case SOC_ID_GRX282_2: - case SOC_ID_GRX288_2: - i->name = SOC_GR9; - i->type = SOC_TYPE_VR9_2; - - default: - unreachable(); - break; - } -} - -void __init ltq_soc_setup(void) -{ - if (ltq_is_ase()) - ltq_register_ase_asc(); - else - ltq_register_asc(1); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/sysctrl.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/sysctrl.c deleted file mode 100644 index de4ce8f1cb..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/sysctrl.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> - */ - -#include <linux/ioport.h> -#include <linux/export.h> -#include <linux/clkdev.h> - -#include <lantiq_soc.h> - -#include "../clk.h" -#include "../devices.h" - -/* clock control register */ -#define CGU_IFCCR 0x0018 -/* system clock register */ -#define CGU_SYS 0x0010 -/* pci control register */ -#define CGU_PCICR 0x0034 -/* ephy configuration register */ -#define CGU_EPHY 0x10 -/* power control register */ -#define PMU_PWDCR 0x1C -/* power status register */ -#define PMU_PWDSR 0x20 -/* power control register */ -#define PMU_PWDCR1 0x24 -/* power status register */ -#define PMU_PWDSR1 0x28 -/* power control register */ -#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) -/* power status register */ -#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) - -/* PMU - power management unit */ -#define PMU_USB0_P BIT(0) -#define PMU_PCI BIT(4) -#define PMU_DMA BIT(5) -#define PMU_USB0 BIT(6) -#define PMU_EPHY BIT(7) /* ase */ -#define PMU_SPI BIT(8) -#define PMU_DFE BIT(9) -#define PMU_EBU BIT(10) -#define PMU_STP BIT(11) -#define PMU_GPT BIT(12) -#define PMU_PPE BIT(13) -#define PMU_AHBS BIT(13) /* vr9 */ -#define PMU_FPI BIT(14) -#define PMU_AHBM BIT(15) -#define PMU_PPE_QSB BIT(18) -#define PMU_PPE_SLL01 BIT(19) -#define PMU_PPE_TC BIT(21) -#define PMU_PPE_EMA BIT(22) -#define PMU_PPE_DPLUM BIT(23) -#define PMU_PPE_DPLUS BIT(24) -#define PMU_USB1_P BIT(26) -#define PMU_USB1 BIT(27) -#define PMU_SWITCH BIT(28) -#define PMU_PPE_TOP BIT(29) -#define PMU_GPHY BIT(30) -#define PMU_PCIE_CLK BIT(31) - -#define PMU1_PCIE_PHY BIT(0) -#define PMU1_PCIE_CTL BIT(1) -#define PMU1_PCIE_PDI BIT(4) -#define PMU1_PCIE_MSI BIT(5) - -#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) -#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) - -static struct resource ltq_cgu_resource = - MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE); - -static struct resource ltq_pmu_resource = - MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE); - -static struct resource ltq_ebu_resource = - MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); - -void __iomem *ltq_cgu_membase; -void __iomem *ltq_ebu_membase; -static void __iomem *ltq_pmu_membase; - -static int ltq_cgu_enable(struct clk *clk) -{ - ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR); - return 0; -} - -static void ltq_cgu_disable(struct clk *clk) -{ - ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR); -} - -static int ltq_pmu_enable(struct clk *clk) -{ - int err = 1000000; - - ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits, - PWDCR(clk->module)); - do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits)); - - if (!err) - panic("activating PMU module failed!\n"); - - return 0; -} - -static void ltq_pmu_disable(struct clk *clk) -{ - ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) | clk->bits, - PWDCR(clk->module)); -} - -static int ltq_pci_enable(struct clk *clk) -{ - unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); - /* set clock bus speed */ - if (ltq_is_ar9()) { - ifccr &= ~0x1f00000; - if (clk->rate == CLOCK_33M) - ifccr |= 0xe00000; - else - ifccr |= 0x700000; /* 62.5M */ - } else { - ifccr &= ~0xf00000; - if (clk->rate == CLOCK_33M) - ifccr |= 0x800000; - else - ifccr |= 0x400000; /* 62.5M */ - } - ltq_cgu_w32(ifccr, CGU_IFCCR); - return 0; -} - -static int ltq_pci_ext_enable(struct clk *clk) -{ - /* enable external pci clock */ - ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16), - CGU_IFCCR); - ltq_cgu_w32((1 << 30), CGU_PCICR); - return 0; -} - -static void ltq_pci_ext_disable(struct clk *clk) -{ - /* disable external pci clock (internal) */ - ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16), - CGU_IFCCR); - ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR); -} - -/* manage the clock gates via PMU */ -static inline void clkdev_add_pmu(const char *dev, const char *con, - unsigned int module, unsigned int bits) -{ - struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); - - clk->cl.dev_id = dev; - clk->cl.con_id = con; - clk->cl.clk = clk; - clk->enable = ltq_pmu_enable; - clk->disable = ltq_pmu_disable; - clk->module = module; - clk->bits = bits; - clkdev_add(&clk->cl); -} - -/* manage the clock generator */ -static inline void clkdev_add_cgu(const char *dev, const char *con, - unsigned int bits) -{ - struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); - - clk->cl.dev_id = dev; - clk->cl.con_id = con; - clk->cl.clk = clk; - clk->enable = ltq_cgu_enable; - clk->disable = ltq_cgu_disable; - clk->bits = bits; - clkdev_add(&clk->cl); -} - -/* pci needs its own enable function */ -static inline void clkdev_add_pci(void) -{ - struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); - struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); - - /* main pci clock */ - clk->cl.dev_id = "ltq_pci"; - clk->cl.con_id = NULL; - clk->cl.clk = clk; - clk->rate = CLOCK_33M; - clk->enable = ltq_pci_enable; - clk->disable = ltq_pmu_disable; - clk->module = 0; - clk->bits = PMU_PCI; - clkdev_add(&clk->cl); - - /* use internal/external bus clock */ - clk_ext->cl.dev_id = "ltq_pci"; - clk_ext->cl.con_id = "external"; - clk_ext->cl.clk = clk_ext; - clk_ext->enable = ltq_pci_ext_enable; - clk_ext->disable = ltq_pci_ext_disable; - clkdev_add(&clk_ext->cl); - -} - -void __init ltq_soc_init(void) -{ - ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource); - if (!ltq_pmu_membase) - panic("Failed to remap pmu memory\n"); - - ltq_cgu_membase = ltq_remap_resource(<q_cgu_resource); - if (!ltq_cgu_membase) - panic("Failed to remap cgu memory\n"); - - ltq_ebu_membase = ltq_remap_resource(<q_ebu_resource); - if (!ltq_ebu_membase) - panic("Failed to remap ebu memory\n"); - - /* make sure to unprotect the memory region where flash is located */ - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); - - /* add our clocks */ - clkdev_add_pmu("ltq_fpi", NULL, 0, PMU_FPI); - clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); - clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); - clkdev_add_pmu("ltq_spi.0", NULL, 0, PMU_SPI); - clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT); - clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU); - if (!ltq_is_vr9()) - clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); - if (!ltq_is_ase()) - clkdev_add_pci(); - if (ltq_is_ase()) { - if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) - clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); - else - clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); - clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY), - clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); - clkdev_add_pmu("ltq_dsl", NULL, 0, - PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | - PMU_AHBS | PMU_DFE); - } else if (ltq_is_vr9()) { - clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), - ltq_vr9_fpi_hz()); - clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY); - clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK); - clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI); - clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI); - clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL); - clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); - clkdev_add_pmu("usb0", NULL, 0, PMU_USB0 | PMU_USB0_P); - clkdev_add_pmu("usb1", NULL, 0, PMU_USB1 | PMU_USB1_P); - clkdev_add_pmu("ltq_vrx200", NULL, 0, - PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | - PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | - PMU_PPE_QSB); - clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS); - } else if (ltq_is_ar9()) { - clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), - ltq_ar9_fpi_hz()); - clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); - clkdev_add_pmu("ltq_dsl", NULL, 0, - PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | - PMU_PPE_QSB | PMU_AHBS | PMU_DFE); - } else { - clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), - ltq_danube_io_region_clock()); - clkdev_add_pmu("ltq_dsl", NULL, 0, - PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | - PMU_PPE_QSB | PMU_AHBS | PMU_DFE); - } -} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/timer.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/timer.c deleted file mode 100644 index 9794c87c73..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/timer.c +++ /dev/null @@ -1,846 +0,0 @@ -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/version.h> -#include <linux/types.h> -#include <linux/fs.h> -#include <linux/miscdevice.h> -#include <linux/init.h> -#include <linux/uaccess.h> -#include <linux/unistd.h> -#include <linux/errno.h> -#include <linux/interrupt.h> -#include <linux/sched.h> - -#include <asm/irq.h> -#include <asm/div64.h> -#include "../clk.h" - -#include <lantiq_soc.h> -#include <lantiq_irq.h> -#include <lantiq_timer.h> - -#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 - -#ifdef TIMER1A -#define FIRST_TIMER TIMER1A -#else -#define FIRST_TIMER 2 -#endif - -/* - * GPTC divider is set or not. - */ -#define GPTU_CLC_RMC_IS_SET 0 - -/* - * Timer Interrupt (IRQ) - */ -/* Must be adjusted when ICU driver is available */ -#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) - -/* - * Bits Operation - */ -#define GET_BITS(x, msb, lsb) \ - (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -#define SET_BITS(x, msb, lsb, value) \ - (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ - (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) - -/* - * GPTU Register Mapping - */ -#define LQ_GPTU (KSEG1 + 0x1E100A00) -#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) -#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) -#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) -#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) -#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) - -/* - * Clock Control Register - */ -#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) -#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) -#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) -#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) -#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) -#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) -#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) - -#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) -#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) -#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) -#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) -#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) -#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) -#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) - -/* - * ID Register - */ -#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) -#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) -#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) - -/* - * Control Register of Timer/Counter nX - * n is the index of block (1 based index) - * X is either A or B - */ -#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) -#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) -#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) -#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) -#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) -#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ -#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) -#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) -#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) -#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) - -#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) -#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) -#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) -#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) -#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) -#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) -#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) -#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) -#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) - -#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) -#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) -#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) - -#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) - -#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) -#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) -#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) -#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) -#define TIMER_FLAG_NONE_EDGE 0x0000 -#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) -#define TIMER_FLAG_REAL 0x0000 -#define TIMER_FLAG_INVERT 0x0040 -#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) -#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) -#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) -#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 -#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) -#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) - -struct timer_dev_timer { - unsigned int f_irq_on; - unsigned int irq; - unsigned int flag; - unsigned long arg1; - unsigned long arg2; -}; - -struct timer_dev { - struct mutex gptu_mutex; - unsigned int number_of_timers; - unsigned int occupation; - unsigned int f_gptu_on; - struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; -}; - -unsigned long ltq_danube_fpi_bus_clock(int fpi); -unsigned long ltq_vr9_fpi_bus_clock(int fpi); - -unsigned int ltq_get_fpi_bus_clock(int fpi) { - if (ltq_is_ase()) - return CLOCK_133M; - else if (ltq_is_vr9()) - return ltq_vr9_fpi_bus_clock(fpi); - - return ltq_danube_fpi_bus_clock(fpi); -} - - -static long gptu_ioctl(struct file *, unsigned int, unsigned long); -static int gptu_open(struct inode *, struct file *); -static int gptu_release(struct inode *, struct file *); - -static struct file_operations gptu_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = gptu_ioctl, - .open = gptu_open, - .release = gptu_release -}; - -static struct miscdevice gptu_miscdev = { - .minor = MISC_DYNAMIC_MINOR, - .name = "gptu", - .fops = &gptu_fops, -}; - -static struct timer_dev timer_dev; - -static irqreturn_t timer_irq_handler(int irq, void *p) -{ - unsigned int timer; - unsigned int flag; - struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; - - timer = irq - TIMER_INTERRUPT; - if (timer < timer_dev.number_of_timers - && dev_timer == &timer_dev.timer[timer]) { - /* Clear interrupt. */ - ltq_w32(1 << timer, LQ_GPTU_IRNCR); - - /* Call user hanler or signal. */ - flag = dev_timer->flag; - if (!(timer & 0x01) - || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { - /* 16-bit timer or timer A of 32-bit timer */ - switch (TIMER_FLAG_MASK_HANDLE(flag)) { - case TIMER_FLAG_CALLBACK_IN_IRQ: - case TIMER_FLAG_CALLBACK_IN_HB: - if (dev_timer->arg1) - (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); - break; - case TIMER_FLAG_SIGNAL: - send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); - break; - } - } - } - return IRQ_HANDLED; -} - -static inline void lq_enable_gptu(void) -{ - struct clk *clk = clk_get_sys("ltq_gptu", NULL); - clk_enable(clk); - - //ltq_pmu_enable(PMU_GPT); - - /* Set divider as 1, disable write protection for SPEN, enable module. */ - *LQ_GPTU_CLC = - GPTU_CLC_SMC_SET(0x00) | - GPTU_CLC_RMC_SET(0x01) | - GPTU_CLC_FSOE_SET(0) | - GPTU_CLC_SBWE_SET(1) | - GPTU_CLC_EDIS_SET(0) | - GPTU_CLC_SPEN_SET(0) | - GPTU_CLC_DISR_SET(0); -} - -static inline void lq_disable_gptu(void) -{ - struct clk *clk = clk_get_sys("ltq_gptu", NULL); - ltq_w32(0x00, LQ_GPTU_IRNEN); - ltq_w32(0xfff, LQ_GPTU_IRNCR); - - /* Set divider as 0, enable write protection for SPEN, disable module. */ - *LQ_GPTU_CLC = - GPTU_CLC_SMC_SET(0x00) | - GPTU_CLC_RMC_SET(0x00) | - GPTU_CLC_FSOE_SET(0) | - GPTU_CLC_SBWE_SET(0) | - GPTU_CLC_EDIS_SET(0) | - GPTU_CLC_SPEN_SET(0) | - GPTU_CLC_DISR_SET(1); - - clk_enable(clk); -} - -int lq_request_timer(unsigned int timer, unsigned int flag, - unsigned long value, unsigned long arg1, unsigned long arg2) -{ - int ret = 0; - unsigned int con_reg, irnen_reg; - int n, X; - - if (timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", - timer, flag, value); - - if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) - value &= 0xFFFF; - else - timer &= ~0x01; - - mutex_lock(&timer_dev.gptu_mutex); - - /* - * Allocate timer. - */ - if (timer < FIRST_TIMER) { - unsigned int mask; - unsigned int shift; - /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ - unsigned int offset = TIMER2A; - - /* - * Pick up a free timer. - */ - if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { - mask = 1 << offset; - shift = 1; - } else { - mask = 3 << offset; - shift = 2; - } - for (timer = offset; - timer < offset + timer_dev.number_of_timers; - timer += shift, mask <<= shift) - if (!(timer_dev.occupation & mask)) { - timer_dev.occupation |= mask; - break; - } - if (timer >= offset + timer_dev.number_of_timers) { - printk("failed![%d]\n", __LINE__); - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } else - ret = timer; - } else { - register unsigned int mask; - - /* - * Check if the requested timer is free. - */ - mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if ((timer_dev.occupation & mask)) { - printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", - __LINE__, mask, timer_dev.occupation); - mutex_unlock(&timer_dev.gptu_mutex); - return -EBUSY; - } else { - timer_dev.occupation |= mask; - ret = 0; - } - } - - /* - * Prepare control register value. - */ - switch (TIMER_FLAG_MASK_EDGE(flag)) { - default: - case TIMER_FLAG_NONE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x00); - break; - case TIMER_FLAG_RISE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x01); - break; - case TIMER_FLAG_FALL_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x02); - break; - case TIMER_FLAG_ANY_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x03); - break; - } - if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) - con_reg |= - TIMER_FLAG_MASK_SRC(flag) == - TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : - GPTU_CON_SRC_EXT_SET(0); - else - con_reg |= - TIMER_FLAG_MASK_SRC(flag) == - TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : - GPTU_CON_SRC_EG_SET(0); - con_reg |= - TIMER_FLAG_MASK_SYNC(flag) == - TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : - GPTU_CON_SYNC_SET(1); - con_reg |= - TIMER_FLAG_MASK_INVERT(flag) == - TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); - con_reg |= - TIMER_FLAG_MASK_SIZE(flag) == - TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : - GPTU_CON_EXT_SET(1); - con_reg |= - TIMER_FLAG_MASK_STOP(flag) == - TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); - con_reg |= - TIMER_FLAG_MASK_TYPE(flag) == - TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : - GPTU_CON_CNT_SET(1); - con_reg |= - TIMER_FLAG_MASK_DIR(flag) == - TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); - - /* - * Fill up running data. - */ - timer_dev.timer[timer - FIRST_TIMER].flag = flag; - timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; - timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; - - /* - * Enable GPTU module. - */ - if (!timer_dev.f_gptu_on) { - lq_enable_gptu(); - timer_dev.f_gptu_on = 1; - } - - /* - * Enable IRQ. - */ - if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { - if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) - timer_dev.timer[timer - FIRST_TIMER].arg1 = - (unsigned long) find_task_by_vpid((int) arg1); - - irnen_reg = 1 << (timer - FIRST_TIMER); - - if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL - || (TIMER_FLAG_MASK_HANDLE(flag) == - TIMER_FLAG_CALLBACK_IN_IRQ - && timer_dev.timer[timer - FIRST_TIMER].arg1)) { - enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); - timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; - } - } else - irnen_reg = 0; - - /* - * Write config register, reload value and enable interrupt. - */ - n = timer >> 1; - X = timer & 0x01; - *LQ_GPTU_CON(n, X) = con_reg; - *LQ_GPTU_RELOAD(n, X) = value; - /* printk("reload value = %d\n", (u32)value); */ - *LQ_GPTU_IRNEN |= irnen_reg; - - mutex_unlock(&timer_dev.gptu_mutex); - printk("successful!\n"); - return ret; -} -EXPORT_SYMBOL(lq_request_timer); - -int lq_free_timer(unsigned int timer) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - if (GPTU_CON_EN(n, X)) - *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); - - *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); - *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); - - if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { - disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); - timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; - } - - timer_dev.occupation &= ~mask; - if (!timer_dev.occupation && timer_dev.f_gptu_on) { - lq_disable_gptu(); - timer_dev.f_gptu_on = 0; - } - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} -EXPORT_SYMBOL(lq_free_timer); - -int lq_start_timer(unsigned int timer, int is_resume) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(flag) == - TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} -EXPORT_SYMBOL(lq_start_timer); - -int lq_stop_timer(unsigned int timer) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER - || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} -EXPORT_SYMBOL(lq_stop_timer); - -int lq_reset_counter_flags(u32 timer, u32 flags) -{ - unsigned int oflag; - unsigned int mask, con_reg; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - oflag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - switch (TIMER_FLAG_MASK_EDGE(flags)) { - default: - case TIMER_FLAG_NONE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x00); - break; - case TIMER_FLAG_RISE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x01); - break; - case TIMER_FLAG_FALL_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x02); - break; - case TIMER_FLAG_ANY_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x03); - break; - } - if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) - con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); - else - con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); - con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); - con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); - con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); - con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); - con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); - con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); - - timer_dev.timer[timer - FIRST_TIMER].flag = flags; - if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) - timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; - - n = timer >> 1; - X = timer & 0x01; - - *LQ_GPTU_CON(n, X) = con_reg; - smp_wmb(); - printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X)); - mutex_unlock(&timer_dev.gptu_mutex); - return 0; -} -EXPORT_SYMBOL(lq_reset_counter_flags); - -int lq_get_count_value(unsigned int timer, unsigned long *value) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER - || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - *value = *LQ_GPTU_COUNT(n, X); - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} -EXPORT_SYMBOL(lq_get_count_value); - -u32 lq_cal_divider(unsigned long freq) -{ - u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); - u32 clock_divider = 1; - module_freq = fpi * 1000; - do_div(module_freq, clock_divider * freq); - return module_freq; -} -EXPORT_SYMBOL(lq_cal_divider); - -int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, - int is_ext_src, unsigned int handle_flag, unsigned long arg1, - unsigned long arg2) -{ - unsigned long divider; - unsigned int flag; - - divider = lq_cal_divider(freq); - if (divider == 0) - return -EINVAL; - flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) - | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) - | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) - | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN - | TIMER_FLAG_MASK_HANDLE(handle_flag); - - printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", - timer, freq, divider); - return lq_request_timer(timer, flag, divider, arg1, arg2); -} -EXPORT_SYMBOL(lq_set_timer); - -int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, - unsigned long arg1, unsigned long arg2) -{ - printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); - return lq_request_timer(timer, flag, reload, arg1, arg2); -} -EXPORT_SYMBOL(lq_set_counter); - -static long gptu_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - int ret; - struct gptu_ioctl_param param; - - if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) - return -EFAULT; - copy_from_user(¶m, (void *) arg, sizeof(param)); - - if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER - || GPTU_SET_COUNTER) && param.timer < 2) - || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) - && !access_ok(VERIFY_WRITE, arg, - sizeof(struct gptu_ioctl_param))) - return -EFAULT; - - switch (cmd) { - case GPTU_REQUEST_TIMER: - ret = lq_request_timer(param.timer, param.flag, param.value, - (unsigned long) param.pid, - (unsigned long) param.sig); - if (ret > 0) { - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - timer, &ret, sizeof(&ret)); - ret = 0; - } - break; - case GPTU_FREE_TIMER: - ret = lq_free_timer(param.timer); - break; - case GPTU_START_TIMER: - ret = lq_start_timer(param.timer, param.flag); - break; - case GPTU_STOP_TIMER: - ret = lq_stop_timer(param.timer); - break; - case GPTU_GET_COUNT_VALUE: - ret = lq_get_count_value(param.timer, ¶m.value); - if (!ret) - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - value, ¶m.value, - sizeof(param.value)); - break; - case GPTU_CALCULATE_DIVIDER: - param.value = lq_cal_divider(param.value); - if (param.value == 0) - ret = -EINVAL; - else { - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - value, ¶m.value, - sizeof(param.value)); - ret = 0; - } - break; - case GPTU_SET_TIMER: - ret = lq_set_timer(param.timer, param.value, - TIMER_FLAG_MASK_STOP(param.flag) != - TIMER_FLAG_ONCE ? 1 : 0, - TIMER_FLAG_MASK_SRC(param.flag) == - TIMER_FLAG_EXT_SRC ? 1 : 0, - TIMER_FLAG_MASK_HANDLE(param.flag) == - TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : - TIMER_FLAG_NO_HANDLE, - (unsigned long) param.pid, - (unsigned long) param.sig); - if (ret > 0) { - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - timer, &ret, sizeof(&ret)); - ret = 0; - } - break; - case GPTU_SET_COUNTER: - lq_set_counter(param.timer, param.flag, param.value, 0, 0); - if (ret > 0) { - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - timer, &ret, sizeof(&ret)); - ret = 0; - } - break; - default: - ret = -ENOTTY; - } - - return ret; -} - -static int gptu_open(struct inode *inode, struct file *file) -{ - return 0; -} - -static int gptu_release(struct inode *inode, struct file *file) -{ - return 0; -} - -int __init lq_gptu_init(void) -{ - int ret; - unsigned int i; - - ltq_w32(0, LQ_GPTU_IRNEN); - ltq_w32(0xfff, LQ_GPTU_IRNCR); - - memset(&timer_dev, 0, sizeof(timer_dev)); - mutex_init(&timer_dev.gptu_mutex); - - lq_enable_gptu(); - timer_dev.number_of_timers = GPTU_ID_CFG * 2; - lq_disable_gptu(); - if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) - timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; - printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); - - ret = misc_register(&gptu_miscdev); - if (ret) { - printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); - return ret; - } else { - printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); - } - - for (i = 0; i < timer_dev.number_of_timers; i++) { - ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); - if (ret) { - for (; i >= 0; i--) - free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); - misc_deregister(&gptu_miscdev); - printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); - return ret; - } else { - timer_dev.timer[i].irq = TIMER_INTERRUPT + i; - disable_irq(timer_dev.timer[i].irq); - printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); - } - } - - return 0; -} - -void __exit lq_gptu_exit(void) -{ - unsigned int i; - - for (i = 0; i < timer_dev.number_of_timers; i++) { - if (timer_dev.timer[i].f_irq_on) - disable_irq(timer_dev.timer[i].irq); - free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); - } - lq_disable_gptu(); - misc_deregister(&gptu_miscdev); -} - -module_init(lq_gptu_init); -module_exit(lq_gptu_exit); diff --git a/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq-pcie.c b/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq-pcie.c deleted file mode 100644 index 84517dfbc3..0000000000 --- a/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq-pcie.c +++ /dev/null @@ -1,81 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_fixup_pcie.c -** PROJECT : IFX UEIP for VRX200 -** MODULES : PCIe -** -** DATE : 02 Mar 2009 -** AUTHOR : Lei Chuanhua -** DESCRIPTION : PCIe Root Complex Driver -** COPYRIGHT : Copyright (c) 2009 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** HISTORY -** $Version $Date $Author $Comment -** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -*******************************************************************************/ -/*! - \file ifxmips_fixup_pcie.c - \ingroup IFX_PCIE - \brief PCIe Fixup functions source file -*/ -#include <linux/pci.h> -#include <linux/pci_regs.h> -#include <linux/pci_ids.h> - -#include <lantiq_soc.h> - -#include "pcie-lantiq.h" - -#define PCI_VENDOR_ID_INFINEON 0x15D1 -#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F -#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 -#define PCI_VENDOR_ID_LANTIQ 0x1BEF -#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 - - - -static void __devinit -ifx_pcie_fixup_resource(struct pci_dev *dev) -{ - u32 reg; - - IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); - - IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s: fixup host controller %s (%04x:%04x)\n", - __func__, pci_name(dev), dev->vendor, dev->device); - - /* Setup COMMAND register */ - reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | - PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; - pci_write_config_word(dev, PCI_COMMAND, reg); - IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -} -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); - -static void __devinit -ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) -{ - IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); - - if (dev->devfn == PCI_DEVFN(0, 0) && - (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { - - dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); - - printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); - } - IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -} - -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, - ifx_pcie_rc_class_early_fixup); - -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, - ifx_pcie_rc_class_early_fixup); diff --git a/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq.c b/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq.c deleted file mode 100644 index daf5ae9e42..0000000000 --- a/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2012 John Crispin <blogic@openwrt.org> - */ - -#include <linux/of_irq.h> -#include <linux/of_pci.h> - -int (*ltqpci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin) = NULL; -int (*ltqpci_plat_arch_init)(struct pci_dev *dev) = NULL; -int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; -int *ltq_pci_irq_map; - -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - if (ltqpci_plat_arch_init) - return ltqpci_plat_arch_init(dev); - - if (ltqpci_plat_dev_init) - return ltqpci_plat_dev_init(dev); - - return 0; -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - if (ltqpci_map_irq) - return ltqpci_map_irq(dev, slot, pin); - if (ltq_pci_irq_map[slot]) { - dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, ltq_pci_irq_map[slot]); - return ltq_pci_irq_map[slot]; - } - printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n", - slot); - - return 0; -} - - diff --git a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-msi.c b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-msi.c deleted file mode 100644 index 9cbf639bb1..0000000000 --- a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-msi.c +++ /dev/null @@ -1,399 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_pcie_msi.c -** PROJECT : IFX UEIP for VRX200 -** MODULES : PCI MSI sub module -** -** DATE : 02 Mar 2009 -** AUTHOR : Lei Chuanhua -** DESCRIPTION : PCIe MSI Driver -** COPYRIGHT : Copyright (c) 2009 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** HISTORY -** $Date $Author $Comment -** 02 Mar,2009 Lei Chuanhua Initial version -*******************************************************************************/ -/*! - \defgroup IFX_PCIE_MSI MSI OS APIs - \ingroup IFX_PCIE - \brief PCIe bus driver OS interface functions -*/ - -/*! - \file ifxmips_pcie_msi.c - \ingroup IFX_PCIE - \brief PCIe MSI OS interface file -*/ - -#include <linux/init.h> -#include <linux/sched.h> -#include <linux/slab.h> -#include <linux/interrupt.h> -#include <linux/kernel_stat.h> -#include <linux/pci.h> -#include <linux/msi.h> -#include <linux/module.h> -#include <asm/bootinfo.h> -#include <asm/irq.h> -#include <asm/traps.h> - -#include "pcie-lantiq.h" - -#define IFX_MSI_IRQ_NUM 16 -#define SM(_v, _f) (((_v) << _f##_S) & (_f)) - -#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000) -#define IFX_PCIE_MSI_IR0 (INT_NUM_IM4_IRL0 + 27) -#define IFX_PCIE_MSI_IR1 (INT_NUM_IM4_IRL0 + 28) -#define IFX_PCIE_MSI_IR2 (INT_NUM_IM4_IRL0 + 29) -#define IFX_PCIE_MSI_IR3 (INT_NUM_IM0_IRL0 + 30) - -#define IFX_MSI_PCI_INT_DISABLE 0x80000000 -#define IFX_MSI_PIC_INT_LINE 0x30000000 -#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000 -#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF -#define IFX_MSI_PIC_BIG_ENDIAN 1 -#define IFX_MSI_PIC_INT_LINE_S 28 -#define IFX_MSI_PIC_MSG_ADDR_S 16 -#define IFX_MSI_PIC_MSG_DATA_S 0x0 - -enum { - IFX_PCIE_MSI_IDX0 = 0, - IFX_PCIE_MSI_IDX1, - IFX_PCIE_MSI_IDX2, - IFX_PCIE_MSI_IDX3, -}; - -typedef struct ifx_msi_irq_idx { - const int irq; - const int idx; -}ifx_msi_irq_idx_t; - -struct ifx_msi_pic { - volatile u32 pic_table[IFX_MSI_IRQ_NUM]; - volatile u32 pic_endian; /* 0x40 */ -}; -typedef struct ifx_msi_pic *ifx_msi_pic_t; - -typedef struct ifx_msi_irq { - const volatile ifx_msi_pic_t msi_pic_p; - const u32 msi_phy_base; - const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; - /* - * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is - * in use. - */ - u16 msi_free_irq_bitmask; - - /* - * Each bit in msi_multiple_irq_bitmask tells that the device using - * this bit in msi_free_irq_bitmask is also using the next bit. This - * is used so we can disable all of the MSI interrupts when a device - * uses multiple. - */ - u16 msi_multiple_irq_bitmask; -}ifx_msi_irq_t; - -static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { - { - .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, - .msi_phy_base = PCIE_MSI_PHY_BASE, - .msi_irq_idx = { - {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, - {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, - {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, - {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, - {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, - {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, - {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, - {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, - }, - .msi_free_irq_bitmask = 0, - .msi_multiple_irq_bitmask= 0, - }, -#ifdef CONFIG_IFX_PCIE_2ND_CORE - { - .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, - .msi_phy_base = PCIE1_MSI_PHY_BASE, - .msi_irq_idx = { - {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, - {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, - {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, - {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, - {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, - {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, - {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, - {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, - }, - .msi_free_irq_bitmask = 0, - .msi_multiple_irq_bitmask= 0, - - }, -#endif /* CONFIG_IFX_PCIE_2ND_CORE */ -}; - -/* - * This lock controls updates to msi_free_irq_bitmask, - * msi_multiple_irq_bitmask and pic register settting - */ -static DEFINE_SPINLOCK(ifx_pcie_msi_lock); - -void pcie_msi_pic_init(int pcie_port) -{ - spin_lock(&ifx_pcie_msi_lock); - msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; - spin_unlock(&ifx_pcie_msi_lock); -} - -/** - * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) - * \brief Called when a driver request MSI interrupts instead of the - * legacy INT A-D. This routine will allocate multiple interrupts - * for MSI devices that support them. A device can override this by - * programming the MSI control bits [6:4] before calling - * pci_enable_msi(). - * - * \param[in] pdev Device requesting MSI interrupts - * \param[in] desc MSI descriptor - * - * \return -EINVAL Invalid pcie root port or invalid msi bit - * \return 0 OK - * \ingroup IFX_PCIE_MSI - */ -int -arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -{ - int irq, pos; - u16 control; - int irq_idx; - int irq_step; - int configured_private_bits; - int request_private_bits; - struct msi_msg msg; - u16 search_mask; - struct ifx_pci_controller *ctrl = pdev->bus->sysdata; - int pcie_port = ctrl->port; - - IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); - - /* XXX, skip RC MSI itself */ - if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { - IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); - return -EINVAL; - } - - /* - * Read the MSI config to figure out how many IRQs this device - * wants. Most devices only want 1, which will give - * configured_private_bits and request_private_bits equal 0. - */ - pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); - - /* - * If the number of private bits has been configured then use - * that value instead of the requested number. This gives the - * driver the chance to override the number of interrupts - * before calling pci_enable_msi(). - */ - configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; - if (configured_private_bits == 0) { - /* Nothing is configured, so use the hardware requested size */ - request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; - } - else { - /* - * Use the number of configured bits, assuming the - * driver wanted to override the hardware request - * value. - */ - request_private_bits = configured_private_bits; - } - - /* - * The PCI 2.3 spec mandates that there are at most 32 - * interrupts. If this device asks for more, only give it one. - */ - if (request_private_bits > 5) { - request_private_bits = 0; - } -again: - /* - * The IRQs have to be aligned on a power of two based on the - * number being requested. - */ - irq_step = (1 << request_private_bits); - - /* Mask with one bit for each IRQ */ - search_mask = (1 << irq_step) - 1; - - /* - * We're going to search msi_free_irq_bitmask_lock for zero - * bits. This represents an MSI interrupt number that isn't in - * use. - */ - spin_lock(&ifx_pcie_msi_lock); - for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { - if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { - msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; - msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; - break; - } - } - spin_unlock(&ifx_pcie_msi_lock); - - /* Make sure the search for available interrupts didn't fail */ - if (pos >= IFX_MSI_IRQ_NUM) { - if (request_private_bits) { - IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " - "interrupts, trying just one", __func__, 1 << request_private_bits); - request_private_bits = 0; - goto again; - } - else { - printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); - return -EINVAL; - } - } - irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; - irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; - - IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); - - /* - * Initialize MSI. This has to match the memory-write endianess from the device - * Address bits [23:12] - */ - spin_lock(&ifx_pcie_msi_lock); - msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | - SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | - SM((1 << pos), IFX_MSI_PIC_MSG_DATA); - - /* Enable this entry */ - msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; - spin_unlock(&ifx_pcie_msi_lock); - - IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", - pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); - - /* Update the number of IRQs the device has available to it */ - control &= ~PCI_MSI_FLAGS_QSIZE; - control |= (request_private_bits << 4); - pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); - - irq_set_msi_desc(irq, desc); - msg.address_hi = 0x0; - msg.address_lo = msi_irqs[pcie_port].msi_phy_base; - msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); - IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); - - write_msi_msg(irq, &msg); - IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); - return 0; -} - -static int -pcie_msi_irq_to_port(unsigned int irq, int *port) -{ - int ret = 0; - - if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || - irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { - *port = IFX_PCIE_PORT0; - } -#ifdef CONFIG_IFX_PCIE_2ND_CORE - else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || - irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { - *port = IFX_PCIE_PORT1; - } -#endif /* CONFIG_IFX_PCIE_2ND_CORE */ - else { - printk(KERN_ERR "%s: Attempted to teardown illegal " - "MSI interrupt (%d)\n", __func__, irq); - ret = -EINVAL; - } - return ret; -} - -/** - * \fn void arch_teardown_msi_irq(unsigned int irq) - * \brief Called when a device no longer needs its MSI interrupts. All - * MSI interrupts for the device are freed. - * - * \param irq The devices first irq number. There may be multple in sequence. - * \return none - * \ingroup IFX_PCIE_MSI - */ -void -arch_teardown_msi_irq(unsigned int irq) -{ - int pos; - int number_irqs; - u16 bitmask; - int pcie_port; - - IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); - - BUG_ON(irq > (INT_NUM_IM4_IRL0 + 31)); - - if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { - return; - } - - /* Shift the mask to the correct bit location, not always correct - * Probally, the first match will be chosen. - */ - for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { - if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) - && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { - break; - } - } - if (pos >= IFX_MSI_IRQ_NUM) { - printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); - return; - } - spin_lock(&ifx_pcie_msi_lock); - /* Disable this entry */ - msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; - msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); - spin_unlock(&ifx_pcie_msi_lock); - /* - * Count the number of IRQs we need to free by looking at the - * msi_multiple_irq_bitmask. Each bit set means that the next - * IRQ is also owned by this device. - */ - number_irqs = 0; - while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && - (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { - number_irqs++; - } - number_irqs++; - - /* Mask with one bit for each IRQ */ - bitmask = (1 << number_irqs) - 1; - - bitmask <<= pos; - if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { - printk(KERN_ERR "%s: Attempted to teardown MSI " - "interrupt (%d) not in use\n", __func__, irq); - return; - } - /* Checks are done, update the in use bitmask */ - spin_lock(&ifx_pcie_msi_lock); - msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; - msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); - spin_unlock(&ifx_pcie_msi_lock); - IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); -} - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); -MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); - diff --git a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-phy.c b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-phy.c deleted file mode 100644 index 9f5027d7cc..0000000000 --- a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-phy.c +++ /dev/null @@ -1,408 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_pcie_phy.c -** PROJECT : IFX UEIP for VRX200 -** MODULES : PCIe PHY sub module -** -** DATE : 14 May 2009 -** AUTHOR : Lei Chuanhua -** DESCRIPTION : PCIe Root Complex Driver -** COPYRIGHT : Copyright (c) 2009 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** HISTORY -** $Version $Date $Author $Comment -** 0.0.1 14 May,2009 Lei Chuanhua Initial version -*******************************************************************************/ -/*! - \file ifxmips_pcie_phy.c - \ingroup IFX_PCIE - \brief PCIe PHY PLL register programming source file -*/ -#include <linux/types.h> -#include <linux/kernel.h> -#include <asm/paccess.h> -#include <linux/delay.h> - -#include "pcie-lantiq.h" - -/* PCIe PDI only supports 16 bit operation */ - -#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ - ((*(volatile u16 *) (__addr)) = (__data)) - -#define IFX_PCIE_PHY_REG_READ16(__addr) \ - (*(volatile u16 *) (__addr)) - -#define IFX_PCIE_PHY_REG16(__addr) \ - (*(volatile u16 *) (__addr)) - -#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ - u16 read_data; \ - u16 write_data; \ - read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ - write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ - IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ -} while (0) - -#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ - -static void -pcie_phy_comm_setup(int pcie_port) -{ - /* PLL Setting */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); - - /* increase the bias reference voltage */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); - - /* Endcnt */ - IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); - - /* force */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); - - /* predrv_ser_en */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); - - /* ctrl_lim */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); - - /* ctrl */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); - - /* predrv_ser_en */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); - - /* RTERM*/ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); - - /* Improved 100MHz clock output */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); - - /* Reduced CDR BW to avoid glitches */ - IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); -} - -#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE -static void -pcie_phy_36mhz_mode_setup(int pcie_port) -{ - IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); - - /* en_ext_mmd_div_ratio */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); - - /* ext_mmd_div_ratio*/ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); - - /* pll_ensdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); - - /* en_const_sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); - - /* mmd */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); - - /* lf_mode */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); - - /* const_sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); - - /* const sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); - - /* pllmod */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); - - IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -} -#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ - -#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE -static void -pcie_phy_36mhz_ssc_mode_setup(int pcie_port) -{ - IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); - - /* PLL Setting */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); - - /* Increase the bias reference voltage */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); - - /* Endcnt */ - IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); - - /* Force */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); - - /* Predrv_ser_en */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); - - /* ctrl_lim */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); - - /* ctrl */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); - - /* predrv_ser_en */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); - - /* RTERM*/ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); - - /* en_ext_mmd_div_ratio */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); - - /* ext_mmd_div_ratio*/ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); - - /* pll_ensdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); - - /* en_const_sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); - - /* mmd */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); - - /* lf_mode */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); - - /* const_sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); - - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); - /* const sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); - - /* pllmod */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); - - /* improved 100MHz clock output */ - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); - - /* reduced CDR BW to avoid glitches */ - IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); - - IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -} -#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ - -#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE -static void -pcie_phy_25mhz_mode_setup(int pcie_port) -{ - IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); - /* en_const_sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); - - /* pll_ensdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); - - /* en_ext_mmd_div_ratio*/ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); - - /* ext_mmd_div_ratio*/ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); - - /* mmd */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); - - /* lf_mode */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); - - IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -} -#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ - -#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE -static void -pcie_phy_100mhz_mode_setup(int pcie_port) -{ - IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); - /* en_ext_mmd_div_ratio */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); - - /* ext_mmd_div_ratio*/ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); - - /* pll_ensdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); - - /* en_const_sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); - - /* mmd */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); - - /* lf_mode */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); - - /* const_sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); - - /* const sdm */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); - - /* pllmod */ - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); - - IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -} -#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ - -static int -pcie_phy_wait_startup_ready(int pcie_port) -{ - int i; - - for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { - if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { - break; - } - udelay(10); - } - if (i >= IFX_PCIE_PLL_TIMEOUT) { - printk(KERN_ERR "%s PLL Link timeout\n", __func__); - return -1; - } - return 0; -} - -static void -pcie_phy_load_enable(int pcie_port, int slice) -{ - /* Set the load_en of tx/rx slice to '1' */ - switch (slice) { - case 1: - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); - break; - case 2: - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); - break; - case 3: - IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); - break; - } -} - -static void -pcie_phy_load_disable(int pcie_port, int slice) -{ - /* set the load_en of tx/rx slice to '0' */ - switch (slice) { - case 1: - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); - break; - case 2: - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); - break; - case 3: - IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); - break; - } -} - -static void pcie_phy_load_war(int pcie_port) -{ - int slice; - - for (slice = 1; slice < 4; slice++) { - pcie_phy_load_enable(pcie_port, slice); - udelay(1); - pcie_phy_load_disable(pcie_port, slice); - } -} - -static void pcie_phy_tx2_modulation(int pcie_port) -{ - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); - mdelay(1); - IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); -} - -static void pcie_phy_tx1_modulation(int pcie_port) -{ - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); - mdelay(1); - IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); -} - -static void pcie_phy_tx_modulation_war(int pcie_port) -{ - int i; -#define PCIE_PHY_MODULATION_NUM 5 - for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { - pcie_phy_tx2_modulation(pcie_port); - pcie_phy_tx1_modulation(pcie_port); - } -#undef PCIE_PHY_MODULATION_NUM -} - -void pcie_phy_clock_mode_setup(int pcie_port) -{ - pcie_pdi_big_endian(pcie_port); - - /* Enable PDI to access PCIe PHY register */ - pcie_pdi_pmu_enable(pcie_port); - - /* Configure PLL and PHY clock */ - pcie_phy_comm_setup(pcie_port); - -#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE - pcie_phy_36mhz_mode_setup(pcie_port); -#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) - pcie_phy_36mhz_ssc_mode_setup(pcie_port); -#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) - pcie_phy_25mhz_mode_setup(pcie_port); -#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) - pcie_phy_100mhz_mode_setup(pcie_port); -#else - #error "PCIE PHY Clock Mode must be chosen first!!!!" -#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ - - /* Enable PCIe PHY and make PLL setting take effect */ - pcie_phy_pmu_enable(pcie_port); - - /* Check if we are in startup_ready status */ - pcie_phy_wait_startup_ready(pcie_port); - - pcie_phy_load_war(pcie_port); - - /* Apply TX modulation workarounds */ - pcie_phy_tx_modulation_war(pcie_port); - -#ifdef IFX_PCI_PHY_REG_DUMP - IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); - pcie_phy_reg_dump(pcie_port); -#endif -} - diff --git a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.c b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.c deleted file mode 100644 index 1df55b5c02..0000000000 --- a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.c +++ /dev/null @@ -1,1146 +0,0 @@ -#include <linux/types.h> -#include <linux/module.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/mm.h> -#include <asm/paccess.h> -#include <linux/pci.h> -#include <linux/pci_regs.h> -#include <linux/platform_device.h> - -#define CONFIG_IFX_PCIE_1ST_CORE - -#include "pcie-lantiq.h" - -#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) -#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) -#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) -#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) -#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) -#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) -#define SM(_v, _f) (((_v) << _f##_S) & (_f)) -#define IFX_REG_SET_BIT(_f, _r) \ - IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) -#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 -#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 -#define IFX_PCIE_PHY_LOOP_CNT 5 - -static DEFINE_SPINLOCK(ifx_pcie_lock); - -int pcibios_1st_host_bus_nr(void); - -unsigned int g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); - -static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { - { - .ir_irq = { - .irq = IFX_PCIE_IR, - .name = "ifx_pcie_rc0", - }, - - .legacy_irq = { - { - .irq_bit = PCIE_IRN_INTA, - .irq = IFX_PCIE_INTA, - }, - { - .irq_bit = PCIE_IRN_INTB, - .irq = IFX_PCIE_INTB, - }, - { - .irq_bit = PCIE_IRN_INTC, - .irq = IFX_PCIE_INTC, - }, - { - .irq_bit = PCIE_IRN_INTD, - .irq = IFX_PCIE_INTD, - }, - }, - }, -}; - -static inline int pcie_ltssm_enable(int pcie_port) -{ - int i; - - IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); /* Enable LTSSM */ - - /* Wait for the link to come up */ - for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { - if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) { - break; - } - udelay(10); - } - if (i >= IFX_PCIE_LTSSM_ENABLE_TIMEOUT) { - IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s link timeout!!!!!\n", __func__); - return -1; - } - return 0; -} - -static inline void pcie_status_register_clear(int pcie_port) -{ - IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); - IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); - IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); - IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); - IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); - IFX_REG_W32(0, PCIE_RSTS(pcie_port)); - IFX_REG_W32(0, PCIE_UES_R(pcie_port)); - IFX_REG_W32(0, PCIE_UEMR(pcie_port)); - IFX_REG_W32(0, PCIE_UESR(pcie_port)); - IFX_REG_W32(0, PCIE_CESR(pcie_port)); - IFX_REG_W32(0, PCIE_CEMR(pcie_port)); - IFX_REG_W32(0, PCIE_RESR(pcie_port)); - IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); - IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); - IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); - IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); - IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); - IFX_REG_W32(0, PCIE_QSR(pcie_port)); - IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); -} - -static inline int ifx_pcie_link_up(int pcie_port) -{ - return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; -} - -static inline void pcie_mem_io_setup(int pcie_port) -{ - unsigned int reg; - /* - * BAR[0:1] readonly register - * RC contains only minimal BARs for packets mapped to this device - * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that - * reside on the downstream side fo the bridge. - */ - reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) - | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); - IFX_REG_W32(reg, PCIE_MBML(pcie_port)); - - /* PCIe_PBML, same as MBML */ - IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); - - /* IO Address Range */ - reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) - | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); - reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; - IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); - - reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) - | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); - IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); -} - -static inline void pcie_msi_setup(int pcie_port) -{ - unsigned int reg; - - /* XXX, MSI stuff should only apply to EP */ - /* MSI Capability: Only enable 32-bit addresses */ - reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); - reg &= ~PCIE_MCAPR_ADDR64_CAP; - reg |= PCIE_MCAPR_MSI_ENABLE; - - /* Disable multiple message */ - reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); - IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); -} - -static inline void pcie_pm_setup(int pcie_port) -{ - unsigned int reg; - - /* Enable PME, Soft reset enabled */ - reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); - reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; - IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); -} - -static inline void pcie_bus_setup(int pcie_port) -{ - unsigned int reg; - - reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); - IFX_REG_W32(reg, PCIE_BNR(pcie_port)); -} - -static inline void pcie_device_setup(int pcie_port) -{ - unsigned int reg; - - /* Device capability register, set up Maximum payload size */ - reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); - reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; - reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); - - /* Only available for EP */ - reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); - IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); - - /* Device control and status register */ - /* Set Maximum Read Request size for the device as a Requestor */ - reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); - - /* - * Request size can be larger than the MPS used, but the completions returned - * for the read will be bounded by the MPS size. - * In our system, Max request size depends on AHB burst size. It is 64 bytes. - * but we set it as 128 as minimum one. - */ - reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) - | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); - - /* Enable relaxed ordering, no snoop, and all kinds of errors */ - reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; - - IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); -} - -static inline void pcie_link_setup(int pcie_port) -{ - unsigned int reg; - - /* - * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM - * L0s is reported during link training via TS1 order set by N_FTS - */ - reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); - reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; - reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); - IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); - - /* Link control and status register */ - reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); - - /* Link Enable, ASPM enabled */ - reg &= ~PCIE_LCTLSTS_LINK_DISABLE; - -#ifdef CONFIG_PCIEASPM - /* - * We use the same physical reference clock that the platform provides on the connector - * It paved the way for ASPM to calculate the new exit Latency - */ - reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; - reg |= PCIE_LCTLSTS_COM_CLK_CFG; - /* - * We should disable ASPM by default except that we have dedicated power management support - * Enable ASPM will cause the system hangup/instability, performance degration - */ - reg |= PCIE_LCTLSTS_ASPM_ENABLE; -#else - reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; -#endif /* CONFIG_PCIEASPM */ - - /* - * The maximum size of any completion with data packet is bounded by the MPS setting - * in device control register - */ - /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ - reg &= ~ PCIE_LCTLSTS_RCB128; - IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); -} - -static inline void pcie_error_setup(int pcie_port) -{ - unsigned int reg; - - /* - * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone - * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE - */ - reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); - reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; - - IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); - - /* Uncorrectable Error Mask Register, Unmask <enable> all bits in PCIE_UESR */ - reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); - reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; - IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); - - /* Uncorrectable Error Severity Register, ALL errors are FATAL */ - IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); - - /* Correctable Error Mask Register, unmask <enable> all bits */ - reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); - reg &= ~PCIE_CORRECTABLE_ERR; - IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); - - /* Advanced Error Capabilities and Control Registr */ - reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); - reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; - IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); - - /* Root Error Command Register, Report all types of errors */ - reg = IFX_REG_R32(PCIE_RECR(pcie_port)); - reg |= PCIE_RECR_ERR_REPORT_EN; - IFX_REG_W32(reg, PCIE_RECR(pcie_port)); - - /* Clear the Root status register */ - reg = IFX_REG_R32(PCIE_RESR(pcie_port)); - IFX_REG_W32(reg, PCIE_RESR(pcie_port)); -} - -static inline void pcie_root_setup(int pcie_port) -{ - unsigned int reg; - - /* Root control and capabilities register */ - reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); - reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; - IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); -} - -static inline void pcie_vc_setup(int pcie_port) -{ - unsigned int reg; - - /* Port VC Capability Register 2 */ - reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); - reg &= ~PCIE_PVC2_VC_ARB_WRR; - reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; - IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); - - /* VC0 Resource Capability Register */ - reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); - reg &= ~PCIE_VC0_RC_REJECT_SNOOP; - IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); -} - -static inline void pcie_port_logic_setup(int pcie_port) -{ - unsigned int reg; - - /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ - reg = IFX_REG_R32(PCIE_AFR(pcie_port)); - reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); - reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) - | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); - /* L0s and L1 entry latency */ - reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); - reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) - | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); - IFX_REG_W32(reg, PCIE_AFR(pcie_port)); - - /* Port Link Control Register */ - reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); - reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ - IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); - - /* Lane Skew Register */ - reg = IFX_REG_R32(PCIE_LSR(pcie_port)); - /* Enable ACK/NACK and FC */ - reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); - IFX_REG_W32(reg, PCIE_LSR(pcie_port)); - - /* Symbol Timer Register and Filter Mask Register 1 */ - reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); - - /* Default SKP interval is very accurate already, 5us */ - /* Enable IO/CFG transaction */ - reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; - /* Disable FC WDT */ - reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; - IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); - - /* Filter Masker Register 2 */ - reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); - reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; - IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); - - /* VC0 Completion Receive Queue Control Register */ - reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); - reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; - reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); - IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); -} - -static inline void pcie_rc_cfg_reg_setup(int pcie_port) -{ - /* diable ltssm */ - IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); - - pcie_mem_io_setup(pcie_port); - pcie_msi_setup(pcie_port); - pcie_pm_setup(pcie_port); - pcie_bus_setup(pcie_port); - pcie_device_setup(pcie_port); - pcie_link_setup(pcie_port); - pcie_error_setup(pcie_port); - pcie_root_setup(pcie_port); - pcie_vc_setup(pcie_port); - pcie_port_logic_setup(pcie_port); -} - -static int ifx_pcie_wait_phy_link_up(int pcie_port) -{ - int i; - - /* Wait for PHY link is up */ - for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { - if (ifx_pcie_link_up(pcie_port)) { - break; - } - udelay(100); - } - if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { - printk(KERN_ERR "%s timeout\n", __func__); - return -1; - } - - /* Check data link up or not */ - if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { - printk(KERN_ERR "%s DLL link is still down\n", __func__); - return -1; - } - - /* Check Data link active or not */ - if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { - printk(KERN_ERR "%s DLL is not active\n", __func__); - return -1; - } - return 0; -} - -static inline int pcie_app_loigc_setup(int pcie_port) -{ - IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); - - /* Pull PCIe EP out of reset */ - pcie_device_rst_deassert(pcie_port); - - /* Start LTSSM training between RC and EP */ - pcie_ltssm_enable(pcie_port); - - /* Check PHY status after enabling LTSSM */ - if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) { - return -1; - } - return 0; -} - -/* - * Must be done after ltssm due to based on negotiated link - * width and payload size - * Update the Replay Time Limit. Empirically, some PCIe - * devices take a little longer to respond than expected under - * load. As a workaround for this we configure the Replay Time - * Limit to the value expected for a 512 byte MPS instead of - * our actual 128 byte MPS. The numbers below are directly - * from the PCIe spec table 3-4/5. - */ -static inline void pcie_replay_time_update(int pcie_port) -{ - unsigned int reg; - int nlw; - int rtl; - - reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); - - nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); - switch (nlw) { - case PCIE_MAX_LENGTH_WIDTH_X1: - rtl = 1677; - break; - case PCIE_MAX_LENGTH_WIDTH_X2: - rtl = 867; - break; - case PCIE_MAX_LENGTH_WIDTH_X4: - rtl = 462; - break; - case PCIE_MAX_LENGTH_WIDTH_X8: - rtl = 258; - break; - default: - rtl = 1677; - break; - } - reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); - reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; - reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); - IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); - - IFX_PCIE_PRINT(PCIE_MSG_REG, "%s PCIE_ALTRT 0x%08x\n", - __func__, IFX_REG_R32(PCIE_ALTRT(pcie_port))); -} - -/* - * Table 359 Enhanced Configuration Address Mapping1) - * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 - * Memory Address PCI Express Configuration Space - * A[(20+n-1):20] Bus Number 1 < n < 8 - * A[19:15] Device Number - * A[14:12] Function Number - * A[11:8] Extended Register Number - * A[7:2] Register Number - * A[1:0] Along with size of the access, used to generate Byte Enables - * For VR9, only the address bits [22:0] are mapped to the configuration space: - * . Address bits [22:20] select the target bus (1-of-8)1) - * . Address bits [19:15] select the target device (1-of-32) on the bus - * . Address bits [14:12] select the target function (1-of-8) within the device. - * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space - * . Address bits [1:0] define the start byte location within the selected dword. - */ -static inline unsigned int pcie_bus_addr(u8 bus_num, u16 devfn, int where) -{ - unsigned int addr; - u8 bus; - - if (!bus_num) { - /* type 0 */ - addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); - } else { - bus = bus_num; - /* type 1, only support 8 buses */ - addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | - ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); - } - IFX_PCIE_PRINT(PCIE_MSG_CFG, "%s: bus addr : %02x:%02x.%01x/%02x, addr=%08x\n", - __func__, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), where, addr); - return addr; -} - -static int pcie_valid_config(int pcie_port, int bus, int dev) -{ - /* RC itself */ - if ((bus == 0) && (dev == 0)) - return 1; - - /* No physical link */ - if (!ifx_pcie_link_up(pcie_port)) - return 0; - - /* Bus zero only has RC itself - * XXX, check if EP will be integrated - */ - if ((bus == 0) && (dev != 0)) - return 0; - - /* Maximum 8 buses supported for VRX */ - if (bus > 9) - return 0; - - /* - * PCIe is PtP link, one bus only supports only one device - * except bus zero and PCIe switch which is virtual bus device - * The following two conditions really depends on the system design - * and attached the device. - * XXX, how about more new switch - */ - if ((bus == 1) && (dev != 0)) - return 0; - - if ((bus >= 3) && (dev != 0)) - return 0; - return 1; -} - -static inline unsigned int ifx_pcie_cfg_rd(int pcie_port, unsigned int reg) -{ - return IFX_REG_R32((volatile unsigned int *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -} - -static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, unsigned int val) -{ - IFX_REG_W32( val, (volatile unsigned int *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -} - -static inline unsigned int ifx_pcie_rc_cfg_rd(int pcie_port, unsigned int reg) -{ - return IFX_REG_R32((volatile unsigned int *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -} - -static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, unsigned int val) -{ - IFX_REG_W32(val, (volatile unsigned int *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -} - -unsigned int ifx_pcie_bus_enum_read_hack(int where, unsigned int value) -{ - unsigned int tvalue = value; - - if (where == PCI_PRIMARY_BUS) { - u8 primary, secondary, subordinate; - - primary = tvalue & 0xFF; - secondary = (tvalue >> 8) & 0xFF; - subordinate = (tvalue >> 16) & 0xFF; - primary += pcibios_1st_host_bus_nr(); - secondary += pcibios_1st_host_bus_nr(); - subordinate += pcibios_1st_host_bus_nr(); - tvalue = (tvalue & 0xFF000000) | (unsigned int)primary | (unsigned int)(secondary << 8) | (unsigned int)(subordinate << 16); - } - return tvalue; -} - -unsigned int ifx_pcie_bus_enum_write_hack(int where, unsigned int value) -{ - unsigned int tvalue = value; - - if (where == PCI_PRIMARY_BUS) { - u8 primary, secondary, subordinate; - - primary = tvalue & 0xFF; - secondary = (tvalue >> 8) & 0xFF; - subordinate = (tvalue >> 16) & 0xFF; - if (primary > 0 && primary != 0xFF) - primary -= pcibios_1st_host_bus_nr(); - if (secondary > 0 && secondary != 0xFF) - secondary -= pcibios_1st_host_bus_nr(); - if (subordinate > 0 && subordinate != 0xFF) - subordinate -= pcibios_1st_host_bus_nr(); - tvalue = (tvalue & 0xFF000000) | (unsigned int)primary | (unsigned int)(secondary << 8) | (unsigned int)(subordinate << 16); - } else if (where == PCI_SUBORDINATE_BUS) { - u8 subordinate = tvalue & 0xFF; - subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; - tvalue = subordinate; - } - return tvalue; -} - -/** - * \fn static int ifx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, - * int where, int size, unsigned int *value) - * \brief Read a value from configuration space - * - * \param[in] bus Pointer to pci bus - * \param[in] devfn PCI device function number - * \param[in] where PCI register number - * \param[in] size Register read size - * \param[out] value Pointer to return value - * \return PCIBIOS_BAD_REGISTER_NUMBER Invalid register number - * \return PCIBIOS_FUNC_NOT_SUPPORTED PCI function not supported - * \return PCIBIOS_DEVICE_NOT_FOUND PCI device not found - * \return PCIBIOS_SUCCESSFUL OK - * \ingroup IFX_PCIE_OS - */ -static int ifx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, unsigned int *value) -{ - unsigned int data = 0; - int bus_number = bus->number; - static const unsigned int mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; - int ret = PCIBIOS_SUCCESSFUL; - struct ifx_pci_controller *ctrl = bus->sysdata; - int pcie_port = ctrl->port; - - if (unlikely(size != 1 && size != 2 && size != 4)){ - ret = PCIBIOS_BAD_REGISTER_NUMBER; - goto out; - } - - /* Make sure the address is aligned to natural boundary */ - if (unlikely(((size - 1) & where))) { - ret = PCIBIOS_BAD_REGISTER_NUMBER; - goto out; - } - - /* - * If we are second controller, we have to cheat OS so that it assume - * its bus number starts from 0 in host controller - */ - bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); - - /* - * We need to force the bus number to be zero on the root - * bus. Linux numbers the 2nd root bus to start after all - * busses on root 0. - */ - if (bus->parent == NULL) - bus_number = 0; - - /* - * PCIe only has a single device connected to it. It is - * always device ID 0. Don't bother doing reads for other - * device IDs on the first segment. - */ - if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { - ret = PCIBIOS_FUNC_NOT_SUPPORTED; - goto out; - } - - if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { - *value = 0xffffffff; - ret = PCIBIOS_DEVICE_NOT_FOUND; - goto out; - } - - IFX_PCIE_PRINT(PCIE_MSG_READ_CFG, "%s: %02x:%02x.%01x/%02x:%01d\n", __func__, bus_number, - PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); - - PCIE_IRQ_LOCK(ifx_pcie_lock); - if (bus_number == 0) { /* RC itself */ - unsigned int t; - - t = (where & ~3); - data = ifx_pcie_rc_cfg_rd(pcie_port, t); - IFX_PCIE_PRINT(PCIE_MSG_READ_CFG, "%s: rd local cfg, offset:%08x, data:%08x\n", - __func__, t, data); - } else { - unsigned int addr = pcie_bus_addr(bus_number, devfn, where); - - data = ifx_pcie_cfg_rd(pcie_port, addr); - if (pcie_port == IFX_PCIE_PORT0) { -#ifdef CONFIG_IFX_PCIE_HW_SWAP - data = le32_to_cpu(data); -#endif /* CONFIG_IFX_PCIE_HW_SWAP */ - } else { -#ifdef CONFIG_IFX_PCIE1_HW_SWAP - data = le32_to_cpu(data); -#endif /* CONFIG_IFX_PCIE_HW_SWAP */ - } - } - /* To get a correct PCI topology, we have to restore the bus number to OS */ - data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); - - PCIE_IRQ_UNLOCK(ifx_pcie_lock); - IFX_PCIE_PRINT(PCIE_MSG_READ_CFG, "%s: read config: data=%08x raw=%08x\n", - __func__, (data >> (8 * (where & 3))) & mask[size & 7], data); - - *value = (data >> (8 * (where & 3))) & mask[size & 7]; -out: - return ret; -} - -static unsigned int ifx_pcie_size_to_value(int where, int size, unsigned int data, unsigned int value) -{ - unsigned int shift; - unsigned int tdata = data; - - switch (size) { - case 1: - shift = (where & 0x3) << 3; - tdata &= ~(0xffU << shift); - tdata |= ((value & 0xffU) << shift); - break; - case 2: - shift = (where & 3) << 3; - tdata &= ~(0xffffU << shift); - tdata |= ((value & 0xffffU) << shift); - break; - case 4: - tdata = value; - break; - } - return tdata; -} - -/** - * \fn static static int ifx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, - * int where, int size, unsigned int value) - * \brief Write a value to PCI configuration space - * - * \param[in] bus Pointer to pci bus - * \param[in] devfn PCI device function number - * \param[in] where PCI register number - * \param[in] size The register size to be written - * \param[in] value The valule to be written - * \return PCIBIOS_BAD_REGISTER_NUMBER Invalid register number - * \return PCIBIOS_DEVICE_NOT_FOUND PCI device not found - * \return PCIBIOS_SUCCESSFUL OK - * \ingroup IFX_PCIE_OS - */ -static int ifx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, unsigned int value) -{ - int bus_number = bus->number; - int ret = PCIBIOS_SUCCESSFUL; - struct ifx_pci_controller *ctrl = bus->sysdata; - int pcie_port = ctrl->port; - unsigned int tvalue = value; - unsigned int data; - - /* Make sure the address is aligned to natural boundary */ - if (unlikely(((size - 1) & where))) { - ret = PCIBIOS_BAD_REGISTER_NUMBER; - goto out; - } - /* - * If we are second controller, we have to cheat OS so that it assume - * its bus number starts from 0 in host controller - */ - bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); - - /* - * We need to force the bus number to be zero on the root - * bus. Linux numbers the 2nd root bus to start after all - * busses on root 0. - */ - if (bus->parent == NULL) - bus_number = 0; - - if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { - ret = PCIBIOS_DEVICE_NOT_FOUND; - goto out; - } - - IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG, "%s: %02x:%02x.%01x/%02x:%01d value=%08x\n", __func__, - bus_number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, value); - - /* XXX, some PCIe device may need some delay */ - PCIE_IRQ_LOCK(ifx_pcie_lock); - - /* - * To configure the correct bus topology using native way, we have to cheat Os so that - * it can configure the PCIe hardware correctly. - */ - tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); - - if (bus_number == 0) { /* RC itself */ - unsigned int t; - - t = (where & ~3); - IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: wr local cfg, offset:%08x, fill:%08x\n", __func__, t, value); - data = ifx_pcie_rc_cfg_rd(pcie_port, t); - IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: rd local cfg, offset:%08x, data:%08x\n", __func__, t, data); - - data = ifx_pcie_size_to_value(where, size, data, tvalue); - - IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: wr local cfg, offset:%08x, value:%08x\n", __func__, t, data); - ifx_pcie_rc_cfg_wr(pcie_port, t, data); - IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: rd local cfg, offset:%08x, value:%08x\n", - __func__, t, ifx_pcie_rc_cfg_rd(pcie_port, t)); - } else { - unsigned int addr = pcie_bus_addr(bus_number, devfn, where); - - IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: wr cfg, offset:%08x, fill:%08x\n", __func__, addr, value); - data = ifx_pcie_cfg_rd(pcie_port, addr); - if (pcie_port == IFX_PCIE_PORT0) { -#ifdef CONFIG_IFX_PCIE_HW_SWAP - data = le32_to_cpu(data); -#endif /* CONFIG_IFX_PCIE_HW_SWAP */ - } else { -#ifdef CONFIG_IFX_PCIE1_HW_SWAP - data = le32_to_cpu(data); -#endif /* CONFIG_IFX_PCIE_HW_SWAP */ - } - IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: rd cfg, offset:%08x, data:%08x\n", __func__, addr, data); - - data = ifx_pcie_size_to_value(where, size, data, tvalue); - if (pcie_port == IFX_PCIE_PORT0) { -#ifdef CONFIG_IFX_PCIE_HW_SWAP - data = cpu_to_le32(data); -#endif /* CONFIG_IFX_PCIE_HW_SWAP */ - } else { -#ifdef CONFIG_IFX_PCIE1_HW_SWAP - data = cpu_to_le32(data); -#endif /* CONFIG_IFX_PCIE_HW_SWAP */ - } - IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG, "%s: wr cfg, offset:%08x, value:%08x\n", __func__, addr, data); - ifx_pcie_cfg_wr(pcie_port, addr, data); - IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG, "%s: rd cfg, offset:%08x, value:%08x\n", - __func__, addr, ifx_pcie_cfg_rd(pcie_port, addr)); - } - PCIE_IRQ_UNLOCK(ifx_pcie_lock); -out: - return ret; -} - -static struct resource ifx_pcie_io_resource = { - .name = "PCIe0 I/O space", - .start = PCIE_IO_PHY_BASE, - .end = PCIE_IO_PHY_END, - .flags = IORESOURCE_IO, -}; - -static struct resource ifx_pcie_mem_resource = { - .name = "PCIe0 Memory space", - .start = PCIE_MEM_PHY_BASE, - .end = PCIE_MEM_PHY_END, - .flags = IORESOURCE_MEM, -}; - -static struct pci_ops ifx_pcie_ops = { - .read = ifx_pcie_read_config, - .write = ifx_pcie_write_config, -}; - -static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { - { - .pcic = { - .pci_ops = &ifx_pcie_ops, - .mem_resource = &ifx_pcie_mem_resource, - .io_resource = &ifx_pcie_io_resource, - }, - .port = IFX_PCIE_PORT0, - }, -}; - -static inline void pcie_core_int_clear_all(int pcie_port) -{ - unsigned int reg; - reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); - reg &= PCIE_RC_CORE_COMBINED_INT; - IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); -} - -static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) -{ - struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; - int pcie_port = ctrl->port; - - IFX_PCIE_PRINT(PCIE_MSG_ISR, "PCIe RC error intr %d\n", irq); - pcie_core_int_clear_all(pcie_port); - return IRQ_HANDLED; -} - -static int pcie_rc_core_int_init(int pcie_port) -{ - int ret; - - /* Enable core interrupt */ - IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); - - /* Clear it first */ - IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); - ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, IRQF_DISABLED, - pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); - if (ret) - printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); - - return ret; -} - -int ifx_pcie_bios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned int irq_bit = 0; - int irq = 0; - struct ifx_pci_controller *ctrl = dev->bus->sysdata; - int pcie_port = ctrl->port; - - IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); - - if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { - printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); - return -1; - } - /* Pin index so minus one */ - irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; - irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; - IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); - IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); - IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); - return irq; -} - -/** - * \fn int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) - * \brief Called to perform platform specific PCI setup - * - * \param[in] dev The Linux PCI device structure for the device to map - * \return OK - * \ingroup IFX_PCIE_OS - */ -int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) -{ - u16 config; - unsigned int dconfig; - int pos; - /* Enable reporting System errors and parity errors on all devices */ - /* Enable parity checking and error reporting */ - pci_read_config_word(dev, PCI_COMMAND, &config); - config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | - PCI_COMMAND_FAST_BACK*/; - pci_write_config_word(dev, PCI_COMMAND, config); - - if (dev->subordinate) { - /* Set latency timers on sub bridges */ - pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ - /* More bridge error detection */ - pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); - config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; - pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); - } - /* Enable the PCIe normal error reporting */ - pos = pci_find_capability(dev, PCI_CAP_ID_EXP); - if (pos) { - /* Disable system error generation in response to error messages */ - pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); - config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); - pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); - - /* Clear PCIE Capability's Device Status */ - pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); - pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); - - /* Update Device Control */ - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); - /* Correctable Error Reporting */ - config |= PCI_EXP_DEVCTL_CERE; - /* Non-Fatal Error Reporting */ - config |= PCI_EXP_DEVCTL_NFERE; - /* Fatal Error Reporting */ - config |= PCI_EXP_DEVCTL_FERE; - /* Unsupported Request */ - config |= PCI_EXP_DEVCTL_URRE; - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); - } - - /* Find the Advanced Error Reporting capability */ - pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); - if (pos) { - /* Clear Uncorrectable Error Status */ - pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); - pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); - /* Enable reporting of all uncorrectable errors */ - /* Uncorrectable Error Mask - turned on bits disable errors */ - pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); - /* - * Leave severity at HW default. This only controls if - * errors are reported as uncorrectable or - * correctable, not if the error is reported. - */ - /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ - /* Clear Correctable Error Status */ - pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); - pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); - /* Enable reporting of all correctable errors */ - /* Correctable Error Mask - turned on bits disable errors */ - pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); - /* Advanced Error Capabilities */ - pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); - /* ECRC Generation Enable */ - if (dconfig & PCI_ERR_CAP_ECRC_GENC) - dconfig |= PCI_ERR_CAP_ECRC_GENE; - /* ECRC Check Enable */ - if (dconfig & PCI_ERR_CAP_ECRC_CHKC) - dconfig |= PCI_ERR_CAP_ECRC_CHKE; - pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); - - /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ - /* Enable Root Port's interrupt in response to error messages */ - pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, - PCI_ERR_ROOT_CMD_COR_EN | - PCI_ERR_ROOT_CMD_NONFATAL_EN | - PCI_ERR_ROOT_CMD_FATAL_EN); - /* Clear the Root status register */ - pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); - pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); - } - /* WAR, only 128 MRRS is supported, force all EPs to support this value */ - pcie_set_readrq(dev, 128); - return 0; -} - -static void pcie_phy_rst(int pcie_port) -{ - pcie_phy_rst_assert(pcie_port); - pcie_phy_rst_deassert(pcie_port); - /* Make sure PHY PLL is stable */ - udelay(20); -} - -static int pcie_rc_initialize(int pcie_port) -{ - int i; - - pcie_rcu_endian_setup(pcie_port); - - pcie_ep_gpio_rst_init(pcie_port); - - /* - * XXX, PCIe elastic buffer bug will cause not to be detected. One more - * reset PCIe PHY will solve this issue - */ - for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { - /* Disable PCIe PHY Analog part for sanity check */ - pcie_phy_pmu_disable(pcie_port); - pcie_phy_rst(pcie_port); - /* PCIe Core reset enabled, low active, sw programmed */ - pcie_core_rst_assert(pcie_port); - /* Put PCIe EP in reset status */ - pcie_device_rst_assert(pcie_port); - /* PCI PHY & Core reset disabled, high active, sw programmed */ - pcie_core_rst_deassert(pcie_port); - /* Already in a quiet state, program PLL, enable PHY, check ready bit */ - pcie_phy_clock_mode_setup(pcie_port); - /* Enable PCIe PHY and Clock */ - pcie_core_pmu_setup(pcie_port); - /* Clear status registers */ - pcie_status_register_clear(pcie_port); -#ifdef CONFIG_PCI_MSI - pcie_msi_init(pcie_port); -#endif /* CONFIG_PCI_MSI */ - pcie_rc_cfg_reg_setup(pcie_port); - - /* Once link is up, break out */ - if (pcie_app_loigc_setup(pcie_port) == 0) - break; - } - if (i >= IFX_PCIE_PHY_LOOP_CNT) { - printk(KERN_ERR "%s link up failed!!!!!\n", __func__); - return -EIO; - } - /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ - pcie_replay_time_update(pcie_port); - return 0; -} - -static int inline ifx_pcie_startup_port_nr(void) -{ - int pcie_port = IFX_PCIE_PORT0; - - pcie_port = IFX_PCIE_PORT0; - return pcie_port; -} - -/** - * \fn static int __init ifx_pcie_bios_init(void) - * \brief Initialize the IFX PCIe controllers - * - * \return -EIO PCIe PHY link is not up - * \return -ENOMEM Configuration/IO space failed to map - * \return 0 OK - * \ingroup IFX_PCIE_OS - */ -extern int (*ltqpci_plat_arch_init)(struct pci_dev *dev); -extern int (*ltqpci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); -static int __devinit ltq_pcie_probe(struct platform_device *pdev) -{ - char ver_str[128] = {0}; - void __iomem *io_map_base; - int pcie_port; - int startup_port; - ltqpci_map_irq = ifx_pcie_bios_map_irq; - ltqpci_plat_arch_init = ifx_pcie_bios_plat_dev_init; - /* Enable AHB Master/ Slave */ - pcie_ahb_pmu_setup(); - - startup_port = ifx_pcie_startup_port_nr(); - - ltq_gpio_request(&pdev->dev, IFX_PCIE_GPIO_RESET, 0, 1, "pcie-reset"); - - for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ - if (pcie_rc_initialize(pcie_port) == 0) { - /* Otherwise, warning will pop up */ - io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); - if (io_map_base == NULL) - return -ENOMEM; - ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; - register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); - /* XXX, clear error status */ - pcie_rc_core_int_init(pcie_port); - } - } - - printk(KERN_INFO "%s", ver_str); -return 0; -} - -static struct platform_driver ltq_pcie_driver = { - .probe = ltq_pcie_probe, - .driver = { - .name = "pcie-xway", - .owner = THIS_MODULE, - }, -}; - -int __init pciebios_init(void) -{ - return platform_driver_register(<q_pcie_driver); -} - -arch_initcall(pciebios_init); diff --git a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.h b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.h deleted file mode 100644 index d877c23a8a..0000000000 --- a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.h +++ /dev/null @@ -1,1305 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_pcie_reg.h -** PROJECT : IFX UEIP for VRX200 -** MODULES : PCIe module -** -** DATE : 02 Mar 2009 -** AUTHOR : Lei Chuanhua -** DESCRIPTION : PCIe Root Complex Driver -** COPYRIGHT : Copyright (c) 2009 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** HISTORY -** $Version $Date $Author $Comment -** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -*******************************************************************************/ -#ifndef IFXMIPS_PCIE_REG_H -#define IFXMIPS_PCIE_REG_H -#include <linux/version.h> -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -/*! - \file ifxmips_pcie_reg.h - \ingroup IFX_PCIE - \brief header file for PCIe module register definition -*/ -/* PCIe Address Mapping Base */ -#define PCIE_CFG_PHY_BASE 0x1D000000UL -#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) -#define PCIE_CFG_SIZE (8 * 1024 * 1024) - -#define PCIE_MEM_PHY_BASE 0x1C000000UL -#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) -#define PCIE_MEM_SIZE (16 * 1024 * 1024) -#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) - -#define PCIE_IO_PHY_BASE 0x1D800000UL -#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) -#define PCIE_IO_SIZE (1 * 1024 * 1024) -#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) - -#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) -#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) -#define PCIE_MSI_PHY_BASE 0x1F600000UL - -#define PCIE_PDI_PHY_BASE 0x1F106800UL -#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) -#define PCIE_PDI_SIZE 0x400 - -#define PCIE1_CFG_PHY_BASE 0x19000000UL -#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) -#define PCIE1_CFG_SIZE (8 * 1024 * 1024) - -#define PCIE1_MEM_PHY_BASE 0x18000000UL -#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) -#define PCIE1_MEM_SIZE (16 * 1024 * 1024) -#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) - -#define PCIE1_IO_PHY_BASE 0x19800000UL -#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) -#define PCIE1_IO_SIZE (1 * 1024 * 1024) -#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) - -#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) -#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) -#define PCIE1_MSI_PHY_BASE 0x1F400000UL - -#define PCIE1_PDI_PHY_BASE 0x1F700400UL -#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) -#define PCIE1_PDI_SIZE 0x400 - -#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) -#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) -#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) -#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) -#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) -#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) -#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) -#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) -#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) -#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) - -/* PCIe Application Logic Register */ -/* RC Core Control Register */ -#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) -/* This should be enabled after initializing configuratin registers - * Also should check link status retraining bit - */ -#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ - -/* RC Core Debug Register */ -#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) -#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ -#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ -#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 -#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ -#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 - -#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ -#define PCIE_RC_DR_PM_DEV_STATE_S 9 - -#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ -#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ -#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ - -/* Current Power State Definition */ -enum { - PCIE_RC_DR_D0 = 0, - PCIE_RC_DR_D1, /* Not supported */ - PCIE_RC_DR_D2, /* Not supported */ - PCIE_RC_DR_D3, - PCIE_RC_DR_UN, -}; - -/* PHY Link Status Register */ -#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) -#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ - -/* Electromechanical Control Register */ -#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) -#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ -#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ -#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ -#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ -#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ -#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ -#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ -#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ - -/* Interrupt Status Register */ -#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) -#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ -#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ -#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ -#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ -#define PCIE_IR_SR_AHB_LU_ERR_S 4 -#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ -#define PCIE_IR_SR_INT_MSG_NUM_S 9 -#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 - -/* Message Control Register */ -#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) -#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ -#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ - -#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) - -/* Vendor-Defined Message Requester ID Register */ -#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) -#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF -#define PCIE_VDM_RID_VDMRID_S 0 - -/* ASPM Control Register */ -#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) -#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ -#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ -#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ - -/* Vendor Message DW0 Register */ -#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) -#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ -#define PCIE_VM_MSG_DW0_TYPE_S 0 -#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ -#define PCIE_VM_MSG_DW0_FORMAT_S 5 -#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ -#define PCIE_VM_MSG_DW0_TC_S 12 -#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ -#define PCIE_VM_MSG_DW0_ATTR_S 18 -#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ -#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ -#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ -#define PCIE_VM_MSG_DW0_LEN_S 22 - -/* Format Definition */ -enum { - PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ - PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ - PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ - PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ -}; - -/* Traffic Class Definition */ -enum { - PCIE_VM_MSG_TC0 = 0, - PCIE_VM_MSG_TC1, - PCIE_VM_MSG_TC2, - PCIE_VM_MSG_TC3, - PCIE_VM_MSG_TC4, - PCIE_VM_MSG_TC5, - PCIE_VM_MSG_TC6, - PCIE_VM_MSG_TC7, -}; - -/* Attributes Definition */ -enum { - PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ - PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ - PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ - PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ -}; - -/* Payload Size Definition */ -#define PCIE_VM_MSG_LEN_MIN 0 -#define PCIE_VM_MSG_LEN_MAX 1024 - -/* Vendor Message DW1 Register */ -#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) -#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ -#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 -#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ -#define PCIE_VM_MSG_DW1_CODE_S 16 -#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ -#define PCIE_VM_MSG_DW1_TAG_S 24 - -#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) -#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) - -/* Vendor Message Request Register */ -#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) -#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ - - -/* AHB Slave Side Band Control Register */ -#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) -#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ -#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ -#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ -#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ -#define PCIE_AHB_SSB_REQ_ATTR_S 3 -#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ -#define PCIE_AHB_SSB_REQ_TC_S 5 - -/* AHB Master SideBand Ctrl Register */ -#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) -#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ -#define PCIE_AHB_MSB_RESP_ATTR_S 0 -#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ -#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ -#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ -#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ -#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ -#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 - -/* AHB Control Register, fixed bus enumeration exception */ -#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) -#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 - -/* Interrupt Enalbe Register */ -#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) -#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) -#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) - -/* PCIe interrupt enable/control/capture register definition */ -#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ -#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ -#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ -#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ -#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ -#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ -#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ -#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ -#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ -#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ -#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ -#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ -#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ -#define PCIE_IRN_INTA 0x00002000 /* INTA */ -#define PCIE_IRN_INTB 0x00004000 /* INTB */ -#define PCIE_IRN_INTC 0x00008000 /* INTC */ -#define PCIE_IRN_INTD 0x00010000 /* INTD */ -#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ - -#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ - PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ - PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ - PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ - PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) -/* PCIe RC Configuration Register */ -#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) - -/* Bit definition from pci_reg.h */ -#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) -#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) -#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ -/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ -#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ -#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ - -#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ -/* Bus Number Register bits */ -#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF -#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 -#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 -#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 -#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 -#define PCIE_PNR_SUB_BUS_NUM_S 16 - -/* IO Base/Limit Register bits */ -#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ -#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 -#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 -#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 -#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 -#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 -#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 - -/* Non-prefetchable Memory Base/Limit Register bit */ -#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ -#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 -#define PCIE_MBML_MEM_BASE_ADDR_S 4 -#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 -#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 - -/* Prefetchable Memory Base/Limit Register bit */ -#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ -#define PCIE_PMBL_64BIT_ADDR 0x00000001 -#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 -#define PCIE_PMBL_UPPER_12BIT_S 4 -#define PCIE_PMBL_E64MA 0x00010000 -#define PCIE_PMBL_END_ADDR 0xFFF00000 -#define PCIE_PMBL_END_ADDR_S 20 -#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ -#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ - -/* I/O Base/Limit Upper 16 bits register */ -#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ -#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF -#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 -#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 -#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 - -#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) -#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) - -/* Interrupt and Secondary Bridge Control Register */ -#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) - -#define PCIE_INTRBCTRL_INT_LINE 0x000000FF -#define PCIE_INTRBCTRL_INT_LINE_S 0 -#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 -#define PCIE_INTRBCTRL_INT_PIN_S 8 -#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ -#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ -#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ -#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ -#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ -#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ -/* Others are read only */ -enum { - PCIE_INTRBCTRL_INT_NON = 0, - PCIE_INTRBCTRL_INTA, - PCIE_INTRBCTRL_INTB, - PCIE_INTRBCTRL_INTC, - PCIE_INTRBCTRL_INTD, -}; - -#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) - -/* Power Management Control and Status Register */ -#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) - -#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ -#define PCIE_PM_CSR_POWER_STATE_S 0 -#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ -#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ -#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ - -/* MSI Capability Register for EP */ -#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) - -#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ -#define PCIE_MCAPR_MSI_CAP_ID_S 0 -#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ -#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 -#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ -#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ -#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 -#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ -#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 -#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ - -/* MSI Message Address Register */ -#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) - -#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ - -/* MSI Message Upper Address Register */ -#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) - -/* MSI Message Data Register */ -#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) - -#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ -#define PCIE_MD_DATA_S 0 - -/* PCI Express Capability Register */ -#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) - -#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ -#define PCIE_XCAP_ID_S 0 -#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ -#define PCIE_XCAP_NEXT_CAP_S 8 -#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ -#define PCIE_XCAP_VER_S 16 -#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ -#define PCIE_XCAP_DEV_PORT_TYPE_S 20 -#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ -#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ -#define PCIE_XCAP_MSG_INT_NUM_S 25 - -/* Device Capability Register */ -#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) - -#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ -#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 -#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ -#define PCIE_DCAP_PHANTOM_FUNC_S 3 -#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ -#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ -#define PCIE_DCAP_EP_L0S_LATENCY_S 6 -#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ -#define PCIE_DCAP_EP_L1_LATENCY_S 9 -#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ - -/* Maximum payload size supported */ -enum { - PCIE_MAX_PAYLOAD_128 = 0, - PCIE_MAX_PAYLOAD_256, - PCIE_MAX_PAYLOAD_512, - PCIE_MAX_PAYLOAD_1024, - PCIE_MAX_PAYLOAD_2048, - PCIE_MAX_PAYLOAD_4096, -}; - -/* Device Control and Status Register */ -#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) - -#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ -#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ -#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ -#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ -#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ -#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ -#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 -#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ -#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ -#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ -#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ -#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ -#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 -#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ -#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ -#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ -#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ -#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ -#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ - -#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ - PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ - PCIE_DCTLSYS_UR_REQ_EN) - -/* Link Capability Register */ -#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) -#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ -#define PCIE_LCAP_MAX_LINK_SPEED_S 0 -#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ -#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 -#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ -#define PCIE_LCAP_ASPM_LEVEL_S 10 -#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ -#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 -#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ -#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 -#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ -#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ -#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ -#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ -#define PCIE_LCAP_PORT_NUM_S 24 - -/* Maximum Length width definition */ -#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 -#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ -#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 -#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 -#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 -#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C -#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 -#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 - -/* Active State Link PM definition */ -enum { - PCIE_ASPM_RES0 = 0, - PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ - PCIE_ASPM_RES1, - PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ -}; - -/* L0s Exit Latency definition */ -enum { - PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ - PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ - PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ - PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ - PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ - PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ - PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ - PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ -}; - -/* L1 Exit Latency definition */ -enum { - PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ - PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ - PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ - PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ - PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ - PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ - PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ - PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ -}; - -/* Link Control and Status Register */ -#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) -#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ -#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 -#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ -#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ -#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ -#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ -#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ -#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ -#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ -#define PCIE_LCTLSTS_LINK_SPEED_S 16 -#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ -#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 -#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ -#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ -#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ - -/* Slot Capabilities Register */ -#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) - -/* Slot Capabilities */ -#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) - -/* Root Control and Capability Register */ -#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) -#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ -#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ -#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ -#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ -#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ - PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) -/* Root Status Register */ -#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) -#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ -#define PCIE_RSTS_PME_REQ_ID_S 0 -#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ -#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ - -/* PCI Express Enhanced Capability Header */ -#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) -#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ -#define PCIE_ENHANCED_CAP_ID_S 0 -#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ -#define PCIE_ENHANCED_CAP_VER_S 16 -#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ -#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 - -/* Uncorrectable Error Status Register */ -#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) -#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ -#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ -#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ -#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ -#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ -#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ -#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ -#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ -#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ -#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ -#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ -#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ - PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ - PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ - PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) - -/* Uncorrectable Error Mask Register, Mask means no report */ -#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) - -/* Uncorrectable Error Severity Register */ -#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) - -/* Correctable Error Status Register */ -#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) -#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ -#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ -#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ -#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ -#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ -#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ -#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ - PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) - -/* Correctable Error Mask Register */ -#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) - -/* Advanced Error Capabilities and Control Register */ -#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) -#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ -#define PCIE_AECCR_FIRST_ERR_PTR_S 0 -#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ -#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ -#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ -#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ - -/* Header Log Register 1 */ -#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) - -/* Header Log Register 2 */ -#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) - -/* Header Log Register 3 */ -#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) - -/* Header Log Register 4 */ -#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) - -/* Root Error Command Register */ -#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) -#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ -#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ -#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ -#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ - PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) - -/* Root Error Status Register */ -#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) -#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ -#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ -#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ -#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ -#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ -#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ -#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ -#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -#define PCIE_RESR_AER_INT_MSG_NUM_S 27 - -/* Error Source Indentification Register */ -#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) -#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF -#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 -#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 -#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 - -/* VC Enhanced Capability Header */ -#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) - -/* Port VC Capability Register */ -#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) -#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ -#define PCIE_PVC1_EXT_VC_CNT_S 0 -#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ -#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 -#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ -#define PCIE_PVC1_REF_CLK_S 8 -#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ -#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 - -/* Extended Virtual Channel Count Defintion */ -#define PCIE_EXT_VC_CNT_MIN 0 -#define PCIE_EXT_VC_CNT_MAX 7 - -/* Port Arbitration Table Entry Size Definition */ -enum { - PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, - PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, - PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, - PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, -}; - -/* Port VC Capability Register 2 */ -#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) -#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ -#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -#define PCIE_PVC2_VC_ARB_WRR 0x0000000F -#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ -#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 - -/* Port VC Control and Status Register */ -#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) -#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ -#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ -#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 -#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ - -/* VC0 Resource Capability Register */ -#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) -#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ -#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ -#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ -#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ - PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ - PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) - -#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ -#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ -#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 -#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ -#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 - -/* VC0 Resource Control Register */ -#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) -#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ -#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ -#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ -#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ -#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ -#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ -#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ -#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ -#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ - -#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ -#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ -#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 -#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ -#define PCIE_VC0_RC0_VC_ID_S 24 -#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ - -/* VC0 Resource Status Register */ -#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) -#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ -#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ - -/* Ack Latency Timer and Replay Timer Register */ -#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) -#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ -#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 -#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ -#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 - -/* Other Message Register */ -#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) - -/* Port Force Link Register */ -#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) -#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ -#define PCIE_PFLR_LINK_NUM_S 0 -#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ -#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ -#define PCIE_PFLR_LINK_STATE_S 16 -#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ -#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 - -/* Ack Frequency Register */ -#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) -#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ -#define PCIE_AFR_AF_S 0 -#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ -#define PCIE_AFR_FTS_NUM_S 8 -#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ -#define PCIE_AFR_COM_FTS_NUM_S 16 -#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ -#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 -#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ -#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 -#define PCIE_AFR_FTS_NUM_DEFAULT 32 -#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 -#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 - -/* Port Link Control Register */ -#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) -#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ -#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ -#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ -#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ -#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ -#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ -#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ -#define PCIE_PLCR_LINK_MODE_S 16 -#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ - -/* Lane Skew Register */ -#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) -#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ -#define PCIE_LSR_LANE_SKEW_NUM_S 0 -#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ -#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ -#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ - -/* Symbol Number Register */ -#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) -#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ -#define PCIE_SNR_TS_S 0 -#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ -#define PCIE_SNR_SKP_S 8 -#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ -#define PCIE_SNR_REPLAY_TIMER_S 14 -#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ -#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 -#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ -#define PCIE_SNR_FC_TIMER_S 28 - -/* Symbol Timer Register and Filter Mask Register 1 */ -#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) -#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ -#define PCIE_STRFMR_SKP_INTERVAL_S 0 -#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ -#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ -#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ -#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ -#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ -#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ -#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ -#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ -#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ -#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ -#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ -#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ -#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ -#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ -#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ -#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ -#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ - -#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ - -/* Filter Masker Register 2 */ -#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) -#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ -#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ - -/* Debug Register 0 */ -#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) - -/* Debug Register 1 */ -#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) - -/* Transmit Posted FC Credit Status Register */ -#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) -#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ -#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 -#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ -#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 - -/* Transmit Non-Posted FC Credit Status */ -#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) -#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ -#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 -#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ -#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 - -/* Transmit Complete FC Credit Status Register */ -#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) -#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ -#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 -#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ -#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 - -/* Queue Status Register */ -#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) -#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ -#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ -#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ - -/* VC Transmit Arbitration Register 1 */ -#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) -#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ -#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ -#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ -#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ - -/* VC Transmit Arbitration Register 2 */ -#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) -#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ -#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ -#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ -#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ - -/* VC0 Posted Receive Queue Control Register */ -#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) -#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ -#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 -#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ -#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 -#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ -#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 -#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ -#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ - -/* VC0 Non-Posted Receive Queue Control */ -#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) -#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ -#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 -#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ -#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 -#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ -#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 - -/* VC0 Completion Receive Queue Control */ -#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) -#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ -#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 -#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ -#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 -#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ -#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 - -/* Applicable to the above three registers */ -enum { - PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, - PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, - PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, -}; - -/* VC0 Posted Buffer Depth Register */ -#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) -#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ -#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 -#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ -#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 - -/* VC0 Non-Posted Buffer Depth Register */ -#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) -#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ -#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 -#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ -#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 - -/* VC0 Completion Buffer Depth Register */ -#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) -#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ -#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 -#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ -#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 - -/* PHY Status Register, all zeros in VR9 */ -#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) - -/* PHY Control Register, all zeros in VR9 */ -#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) - -/* - * PCIe PDI PHY register definition, suppose all the following - * stuff is confidential. - * XXX, detailed bit definition - */ -#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) -#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) -#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) -#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) -#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) -#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) -#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) -#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) -#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) -#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) -#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) - -#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) -#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) -#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) -#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) -#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) -#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) -#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) -#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) - -#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) -#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) -#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) -#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) -#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) -#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) -#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) - -#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) -#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) -#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) -#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) -#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) - -/* Interrupt related stuff */ -#define PCIE_LEGACY_DISABLE 0 -#define PCIE_LEGACY_INTA 1 -#define PCIE_LEGACY_INTB 2 -#define PCIE_LEGACY_INTC 3 -#define PCIE_LEGACY_INTD 4 -#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD - -#define PCIE_IRQ_LOCK(lock) do { \ - unsigned long flags; \ - spin_lock_irqsave(&(lock), flags); -#define PCIE_IRQ_UNLOCK(lock) \ - spin_unlock_irqrestore(&(lock), flags); \ -} while (0) - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -#define IRQF_SHARED SA_SHIRQ -#endif - -#define PCIE_MSG_MSI 0x00000001 -#define PCIE_MSG_ISR 0x00000002 -#define PCIE_MSG_FIXUP 0x00000004 -#define PCIE_MSG_READ_CFG 0x00000008 -#define PCIE_MSG_WRITE_CFG 0x00000010 -#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) -#define PCIE_MSG_REG 0x00000020 -#define PCIE_MSG_INIT 0x00000040 -#define PCIE_MSG_ERR 0x00000080 -#define PCIE_MSG_PHY 0x00000100 -#define PCIE_MSG_ANY 0x000001ff - -#define IFX_PCIE_PORT0 0 -#define IFX_PCIE_PORT1 1 - -#ifdef CONFIG_IFX_PCIE_2ND_CORE -#define IFX_PCIE_CORE_NR 2 -#else -#define IFX_PCIE_CORE_NR 1 -#endif - -//#define IFX_PCIE_ERROR_INT - -//#define IFX_PCIE_DBG - -#if defined(IFX_PCIE_DBG) -#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ - if (g_pcie_debug_flag & (_m)) { \ - ifx_pcie_debug((_fmt), ##args); \ - } \ -} while (0) - -#define INLINE -#else -#define IFX_PCIE_PRINT(_m, _fmt, args...) \ - do {} while(0) -#define INLINE inline -#endif - -struct ifx_pci_controller { - struct pci_controller pcic; - - /* RC specific, per host bus information */ - u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ -}; - -typedef struct ifx_pcie_ir_irq { - const unsigned int irq; - const char name[16]; -}ifx_pcie_ir_irq_t; - -typedef struct ifx_pcie_legacy_irq{ - const u32 irq_bit; - const int irq; -}ifx_pcie_legacy_irq_t; - -typedef struct ifx_pcie_irq { - ifx_pcie_ir_irq_t ir_irq; - ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; -}ifx_pcie_irq_t; - -extern u32 g_pcie_debug_flag; -extern void ifx_pcie_debug(const char *fmt, ...); -extern void pcie_phy_clock_mode_setup(int pcie_port); -extern void pcie_msi_pic_init(int pcie_port); -extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); -extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); - - -#include <linux/types.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/clk.h> - -#include <lantiq_soc.h> - -#define IFX_PCIE_GPIO_RESET 38 -#define IFX_REG_R32 ltq_r32 -#define IFX_REG_W32 ltq_w32 -#define CONFIG_IFX_PCIE_HW_SWAP -#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ - -#define IFX_RCU (KSEG1 | 0x1F203000) -#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE - -#define IFX_PMU1_MODULE_PCIE_PHY (0) -#define IFX_PMU1_MODULE_PCIE_CTRL (1) -#define IFX_PMU1_MODULE_PDI (4) -#define IFX_PMU1_MODULE_MSI (5) - -#define IFX_PMU_MODULE_PCIE_L0_CLK (31) - - -static inline void pcie_ep_gpio_rst_init(int pcie_port) -{ -} - -static inline void pcie_ahb_pmu_setup(void) -{ - struct clk *clk; - clk = clk_get_sys("ltq_pcie", "ahb"); - clk_enable(clk); - //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); -} - -static inline void pcie_rcu_endian_setup(int pcie_port) -{ - u32 reg; - - reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -#ifdef CONFIG_IFX_PCIE_HW_SWAP - reg |= IFX_RCU_AHB_BE_PCIE_M; - reg |= IFX_RCU_AHB_BE_PCIE_S; - reg &= ~IFX_RCU_AHB_BE_XBAR_M; -#else - reg |= IFX_RCU_AHB_BE_PCIE_M; - reg &= ~IFX_RCU_AHB_BE_PCIE_S; - reg &= ~IFX_RCU_AHB_BE_XBAR_M; -#endif /* CONFIG_IFX_PCIE_HW_SWAP */ - IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); - IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -} - -static inline void pcie_phy_pmu_enable(int pcie_port) -{ - struct clk *clk; - clk = clk_get_sys("ltq_pcie", "phy"); - clk_enable(clk); - //ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PCIE_PHY); -} - -static inline void pcie_phy_pmu_disable(int pcie_port) -{ - struct clk *clk; - clk = clk_get_sys("ltq_pcie", "phy"); - clk_disable(clk); - //ltq_pmu1_disable(1<<IFX_PMU1_MODULE_PCIE_PHY); -} - -static inline void pcie_pdi_big_endian(int pcie_port) -{ - u32 reg; - - /* SRAM2PDI endianness control. */ - reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); - /* Config AHB->PCIe and PDI endianness */ - reg |= IFX_RCU_AHB_BE_PCIE_PDI; - IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -} - -static inline void pcie_pdi_pmu_enable(int pcie_port) -{ - struct clk *clk; - clk = clk_get_sys("ltq_pcie", "pdi"); - clk_enable(clk); - //ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PDI); -} - -static inline void pcie_core_rst_assert(int pcie_port) -{ - u32 reg; - - reg = IFX_REG_R32(IFX_RCU_RST_REQ); - - /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ - reg |= 0x00400000; - IFX_REG_W32(reg, IFX_RCU_RST_REQ); -} - -static inline void pcie_core_rst_deassert(int pcie_port) -{ - u32 reg; - - /* Make sure one micro-second delay */ - udelay(1); - - /* Reset PCIe PHY & Core, bit 22 */ - reg = IFX_REG_R32(IFX_RCU_RST_REQ); - reg &= ~0x00400000; - IFX_REG_W32(reg, IFX_RCU_RST_REQ); -} - -static inline void pcie_phy_rst_assert(int pcie_port) -{ - u32 reg; - - reg = IFX_REG_R32(IFX_RCU_RST_REQ); - reg |= 0x00001000; /* Bit 12 */ - IFX_REG_W32(reg, IFX_RCU_RST_REQ); -} - -static inline void pcie_phy_rst_deassert(int pcie_port) -{ - u32 reg; - - /* Make sure one micro-second delay */ - udelay(1); - - reg = IFX_REG_R32(IFX_RCU_RST_REQ); - reg &= ~0x00001000; /* Bit 12 */ - IFX_REG_W32(reg, IFX_RCU_RST_REQ); -} - -static inline void pcie_device_rst_assert(int pcie_port) -{ - gpio_set_value(IFX_PCIE_GPIO_RESET, 0); - // ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -} - -static inline void pcie_device_rst_deassert(int pcie_port) -{ - mdelay(100); - gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -// ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -} - -static inline void pcie_core_pmu_setup(int pcie_port) -{ - struct clk *clk; - clk = clk_get_sys("ltq_pcie", "ctl"); - clk_enable(clk); - clk = clk_get_sys("ltq_pcie", "bus"); - clk_enable(clk); - - //ltq_pmu1_enable(1 << IFX_PMU1_MODULE_PCIE_CTRL); - //ltq_pmu_enable(1 << IFX_PMU_MODULE_PCIE_L0_CLK); -} - -static inline void pcie_msi_init(int pcie_port) -{ - struct clk *clk; - pcie_msi_pic_init(pcie_port); - clk = clk_get_sys("ltq_pcie", "msi"); - clk_enable(clk); - //ltq_pmu1_enable(1 << IFX_PMU1_MODULE_MSI); -} - -static inline u32 -ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) -{ - u32 tbus_number = bus_number; - -#ifdef CONFIG_IFX_PCI - if (pcibios_host_nr() > 1) { - tbus_number -= pcibios_1st_host_bus_nr(); - } -#endif /* CONFIG_IFX_PCI */ - return tbus_number; -} - -static inline u32 -ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -{ - struct pci_dev *pdev; - u32 tvalue = value; - - /* Sanity check */ - pdev = pci_get_slot(bus, devfn); - if (pdev == NULL) { - return tvalue; - } - - /* Only care about PCI bridge */ - if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { - return tvalue; - } - - if (read) { /* Read hack */ - #ifdef CONFIG_IFX_PCI - if (pcibios_host_nr() > 1) { - tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); - } - #endif /* CONFIG_IFX_PCI */ - } - else { /* Write hack */ - #ifdef CONFIG_IFX_PCI - if (pcibios_host_nr() > 1) { - tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); - } - #endif - } - return tvalue; -} - -#endif /* IFXMIPS_PCIE_VR9_H */ - |