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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-24 23:00:20 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-24 23:00:20 +0000
commit19bc341ecffe96af51c3b90107244840efb6489f (patch)
treeaecb9ea9f0a77d1b37f812d9c417a21ff732415b /target/linux/ifxmips/files/include/asm-mips
parent2b0c4d151c846caf3fda3195538b5ec9a2c14bf0 (diff)
add ifxmips mei driver, untested and uncleaned
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9898 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ifxmips/files/include/asm-mips')
-rw-r--r--target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h22
-rw-r--r--target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei.h270
-rw-r--r--target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app.h116
-rw-r--r--target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app_ioctl.h1191
-rw-r--r--target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_bsp.h308
-rw-r--r--target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_ioctl.h734
-rw-r--r--target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_linux.h111
7 files changed, 2752 insertions, 0 deletions
diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h
new file mode 100644
index 0000000000..c4a9929f6b
--- /dev/null
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h
@@ -0,0 +1,22 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+
+extern void ifxmips_led_set(unsigned int led);
+extern void ifxmips_led_clear(unsigned int led);
+extern void ifxmips_led_blink_set(unsigned int led);
+extern void ifxmips_led_blink_clear(unsigned int led);
diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei.h
new file mode 100644
index 0000000000..d8a4b8867f
--- /dev/null
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+**
+** FILE NAME : danube_mei.h
+** PROJECT : Danube
+** MODULES : MEI
+**
+** DATE : 1 Jan 2006
+** AUTHOR : TC Chen
+** DESCRIPTION : MEI Driver
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Version $Date $Author $Comment
+*******************************************************************************/
+#ifndef _IFXMIPS_MEI_H
+#define _IFXMIPS_MEI_H
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#include "ifxmips_mei_app.h"
+
+#define IFXMIPS_MEI_DEBUG
+#define IFXMIPS_MEI_CMV_EXTRA
+#define IFXMIPS_MEI_MAJOR 106
+
+/*
+** Define where in ME Processor's memory map the Stratify chip lives
+*/
+
+#define MAXSWAPSIZE 8 * 1024 //8k *(32bits)
+
+// Mailboxes
+#define MSG_LENGTH 16 // x16 bits
+#define YES_REPLY 1
+#define NO_REPLY 0
+
+#define CMV_TIMEOUT 100 //jiffies
+#define MIB_INTERVAL 10000 //msec
+
+/*** Bit definitions ***/
+
+#define FALSE 0
+#define TRUE 1
+#define BIT0 1<<0
+#define BIT1 1<<1
+#define BIT2 1<<2
+#define BIT3 1<<3
+#define BIT4 1<<4
+#define BIT5 1<<5
+#define BIT6 1<<6
+#define BIT7 1<<7
+#define BIT8 1<<8
+#define BIT9 1<<9
+#define BIT10 1<<10
+#define BIT11 1<<11
+#define BIT12 1<<12
+#define BIT13 1<<13
+#define BIT14 1<<14
+#define BIT15 1<<15
+#define BIT16 1<<16
+#define BIT17 1<<17
+#define BIT18 1<<18
+#define BIT19 1<<19
+#define BIT20 1<<20
+#define BIT21 1<<21
+#define BIT22 1<<22
+#define BIT23 1<<23
+#define BIT24 1<<24
+#define BIT25 1<<25
+#define BIT26 1<<26
+#define BIT27 1<<27
+#define BIT28 1<<28
+#define BIT29 1<<29
+#define BIT30 1<<30
+#define BIT31 1<<31
+
+// ARC register addresss
+#define ARC_STATUS 0x0
+#define ARC_LP_START 0x2
+#define ARC_LP_END 0x3
+#define ARC_DEBUG 0x5
+#define ARC_INT_MASK 0x10A
+
+#define IRAM0_BASE (0x00000)
+#define IRAM1_BASE (0x04000)
+#define BRAM_BASE (0x0A000)
+
+#define ADSL_BASE (0x20000)
+#define CRI_BASE (ADSL_BASE + 0x11F00)
+#define CRI_CCR0 (CRI_BASE + 0x00)
+#define CRI_RST (CRI_BASE + 0x04*4)
+#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
+
+//
+#define IRAM0_ADDR_BIT_MASK 0xFFF
+#define IRAM1_ADDR_BIT_MASK 0xFFF
+#define BRAM_ADDR_BIT_MASK 0xFFF
+#define RX_DILV_ADDR_BIT_MASK 0x1FFF
+
+// CRI_CCR0 Register definitions
+#define CLK_2M_MODE_ENABLE BIT6
+#define ACL_CLK_MODE_ENABLE BIT4
+#define FDF_CLK_MODE_ENABLE BIT2
+#define STM_CLK_MODE_ENABLE BIT0
+
+// CRI_RST Register definitions
+#define FDF_SRST BIT3
+#define MTE_SRST BIT2
+#define FCI_SRST BIT1
+#define AAI_SRST BIT0
+
+// MEI_TO_ARC_INTERRUPT Register definitions
+#define MEI_TO_ARC_INT1 BIT3
+#define MEI_TO_ARC_INT0 BIT2
+#define MEI_TO_ARC_CS_DONE BIT1 //need to check
+#define MEI_TO_ARC_MSGAV BIT0
+
+// ARC_TO_MEI_INTERRUPT Register definitions
+#define ARC_TO_MEI_INT1 BIT8
+#define ARC_TO_MEI_INT0 BIT7
+#define ARC_TO_MEI_CS_REQ BIT6
+#define ARC_TO_MEI_DBG_DONE BIT5
+#define ARC_TO_MEI_MSGACK BIT4
+#define ARC_TO_MEI_NO_ACCESS BIT3
+#define ARC_TO_MEI_CHECK_AAITX BIT2
+#define ARC_TO_MEI_CHECK_AAIRX BIT1
+#define ARC_TO_MEI_MSGAV BIT0
+
+// ARC_TO_MEI_INTERRUPT_MASK Register definitions
+#define GP_INT1_EN BIT8
+#define GP_INT0_EN BIT7
+#define CS_REQ_EN BIT6
+#define DBG_DONE_EN BIT5
+#define MSGACK_EN BIT4
+#define NO_ACC_EN BIT3
+#define AAITX_EN BIT2
+#define AAIRX_EN BIT1
+#define MSGAV_EN BIT0
+
+#define MEI_SOFT_RESET BIT0
+
+#define HOST_MSTR BIT0
+
+#define JTAG_MASTER_MODE 0x0
+#define MEI_MASTER_MODE HOST_MSTR
+
+// MEI_DEBUG_DECODE Register definitions
+#define MEI_DEBUG_DEC_MASK (0x3)
+#define MEI_DEBUG_DEC_AUX_MASK (0x0)
+#define MEI_DEBUG_DEC_DMP1_MASK (0x1)
+#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
+#define MEI_DEBUG_DEC_CORE_MASK (0x3)
+
+#define AUX_STATUS (0x0)
+// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
+// page swap requests.
+#define MEI_TO_ARC_MAILBOX (0xDFD0)
+#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
+
+#define ARC_TO_MEI_MAILBOX (0xDFA0)
+#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
+
+// Codeswap request messages are indicated by setting BIT31
+#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
+
+// Clear Eoc messages received are indicated by setting BIT17
+#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
+
+/*
+** Swap page header
+*/
+// Page must be loaded at boot time if size field has BIT31 set
+#define BOOT_FLAG (BIT31)
+#define BOOT_FLAG_MASK ~BOOT_FLAG
+
+#define FREE_RELOAD 1
+#define FREE_SHOWTIME 2
+#define FREE_ALL 3
+
+#define IFX_POP_EOC_DONE 0
+#define IFX_POP_EOC_FAIL -1
+
+#define CLREOC_BUFF_SIZE 12 //number of clreoc commands being buffered
+
+// marcos
+#define IFXMIPS_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data);} while (0)
+#define IFXMIPS_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
+#define SET_BIT(reg, mask) reg |= (mask)
+#define CLEAR_BIT(reg, mask) reg &= (~mask)
+#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
+#define SET_BITS(reg, mask) SET_BIT(reg, mask)
+#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
+
+#define ALIGN_SIZE ( 1L<<10 ) //1K size align
+#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
+
+// swap marco
+#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
+#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
+
+// Swap page header describes size in 32-bit words, load location, and image offset
+// for program and/or data segments
+typedef struct _arc_swp_page_hdr {
+ u32 p_offset; //Offset bytes of progseg from beginning of image
+ u32 p_dest; //Destination addr of progseg on processor
+ u32 p_size; //Size in 32-bitwords of program segment
+ u32 d_offset; //Offset bytes of dataseg from beginning of image
+ u32 d_dest; //Destination addr of dataseg on processor
+ u32 d_size; //Size in 32-bitwords of data segment
+} ARC_SWP_PAGE_HDR;
+
+#ifdef CONFIG_PROC_FS
+typedef struct reg_entry {
+ int *flag;
+ char name[30]; // big enough to hold names
+ char description[100]; // big enough to hold description
+ unsigned short low_ino;
+} reg_entry_t;
+#endif
+
+/*
+** Swap image header
+*/
+#define GET_PROG 0 // Flag used for program mem segment
+#define GET_DATA 1 // Flag used for data mem segment
+
+// Image header contains size of image, checksum for image, and count of
+// page headers. Following that are 'count' page headers followed by
+// the code and/or data segments to be loaded
+typedef struct _arc_img_hdr {
+ u32 size; // Size of binary image in bytes
+ u32 checksum; // Checksum for image
+ u32 count; // Count of swp pages in image
+ ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
+} ARC_IMG_HDR;
+
+typedef struct smmu_mem_info {
+ int type;
+ unsigned long nCopy;
+ unsigned long size;
+ unsigned char *address;
+ unsigned char *org_address;
+} smmu_mem_info_t;
+
+/*
+** Native size for the Stratiphy interface is 32-bits. All reads and writes
+** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or
+** byte data. Read routines are provided. Write routines are probably a bad idea, as the
+** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle
+** could very well have unintended results.
+*/
+MEI_ERROR meiCMV (u16 *, int, u16 *); // first arg is CMV to ARC, second to indicate whether need reply
+
+MEI_ERROR meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize);
+extern int ifx_mei_hdlc_send (char *hdlc_pkt, int hdlc_pkt_len);
+extern int ifx_mei_hdlc_read (char *hdlc_pkt, int max_hdlc_pkt_len);
+#if defined(__KERNEL__) || defined (IFXMIPS_PORT_RTEMS)
+extern void makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size,
+ u16 * data, u16 * CMVMSG);
+int ifx_mei_hdlc_send (char *, int);
+int ifx_mei_hdlc_read (char *, int);
+#endif
+
+#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app.h
new file mode 100644
index 0000000000..cba742e58a
--- /dev/null
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+**
+** FILE NAME : ifxmips_mei_app.h
+** PROJECT : Danube
+** MODULES : MEI
+**
+** DATE : 1 Jan 2006
+** AUTHOR : TC Chen
+** DESCRIPTION : MEI Driver
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Version $Date $Author $Comment
+*******************************************************************************/
+#ifndef _IFXMIPS_MEI_APP_H
+#define _IFXMIPS_MEI_APP_H
+ // ioctl control
+#define IFXMIPS_MEI_START 300
+#define IFXMIPS_MEI_REPLY 301
+#define IFXMIPS_MEI_NOREPLY 302
+
+#define IFXMIPS_MEI_RESET 303
+#define IFXMIPS_MEI_REBOOT 304
+#define IFXMIPS_MEI_HALT 305
+#define IFXMIPS_MEI_CMV_WINHOST 306
+#define IFXMIPS_MEI_CMV_READ 307
+#define IFXMIPS_MEI_CMV_WRITE 308
+#define IFXMIPS_MEI_MIB_DAEMON 309
+#define IFXMIPS_MEI_SHOWTIME 310
+#define IFXMIPS_MEI_REMOTE 311
+#define IFXMIPS_MEI_READDEBUG 312
+#define IFXMIPS_MEI_WRITEDEBUG 313
+#define IFXMIPS_MEI_LOP 314
+
+#define IFXMIPS_MEI_PCM_SETUP 315
+#define IFXMIPS_MEI_PCM_START_TIMER 316
+#define IFXMIPS_MEI_PCM_STOP_TIMER 317
+#define IFXMIPS_MEI_PCM_CHECK 318
+#define IFXMIPS_MEI_GET_EOC_LEN 319
+#define IFXMIPS_MEI_GET_EOC_DATA 320
+#define IFXMIPS_MEI_PCM_GETDATA 321
+#define IFXMIPS_MEI_PCM_GPIO 322
+#define IFXMIPS_MEI_EOC_SEND 323
+#define IFXMIPS_MEI_DOWNLOAD 326
+#define IFXMIPS_MEI_JTAG_ENABLE 327
+#define IFXMIPS_MEI_RUN 328
+#define IFXMIPS_MEI_DEBUG_MODE 329
+
+/* Loop diagnostics mode of the ADSL line related constants */
+#define SET_ADSL_LOOP_DIAGNOSTICS_MODE 330
+#define GET_ADSL_LOOP_DIAGNOSTICS_MODE 331
+#define LOOP_DIAGNOSTIC_MODE_COMPLETE 332
+#define IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE 333
+
+/* L3 Power Mode */
+/* Get current Power Moaagement Mode Status*/
+#define GET_POWER_MANAGEMENT_MODE 334
+/* Set L3 Power Mode /disable L3 power mode */
+#define SET_L3_POWER_MODE 335
+
+/* get current dual latency configuration */
+#define GET_ADSL_DUAL_LATENCY 336
+/* enable/disable dual latency path */
+#define SET_ADSL_DUAL_LATENCY 337
+
+/* Enable/Disable autoboot mode. */
+/* When the autoboot mode is disabled, the driver will excute some cmv
+ commands for led control and dual latency when DSL startup.*/
+#define AUTOBOOT_ENABLE_SET 338
+
+/* Enable/Disable Quiet Mode*/
+/* Quiet mode is used for firmware debug. if the quiet mode enable, the autoboot daemon will not reset arc when the arc need to reboot */
+#define QUIET_MODE_GET 339
+#define QUIET_MODE_SET 340
+
+/* Enable/Disable showtime lock*/
+/* showtime lock is used for firmware debug. if the showtime lock enable, the autoboot daemon will not reset arc when the arc reach showtime and need to reboot */
+#define SHOWTIME_LOCK_GET 341
+#define SHOWTIME_LOCK_SET 342
+
+#define L0_POWER_MODE 0
+#define L2_POWER_MODE 2
+#define L3_POWER_MODE 3
+
+#define DUAL_LATENCY_US_DS_DISABLE 0
+#define DUAL_LATENCY_US_ENABLE (1<<0)
+#define DUAL_LATENCY_DS_ENABLE (1<<1)
+#define DUAL_LATENCY_US_DS_ENABLE (DUAL_LATENCY_US_ENABLE|DUAL_LATENCY_DS_ENABLE)
+
+#define ME_HDLC_IDLE 0
+#define ME_HDLC_INVALID_MSG 1
+#define ME_HDLC_MSG_QUEUED 2
+#define ME_HDLC_MSG_SENT 3
+#define ME_HDLC_RESP_RCVD 4
+#define ME_HDLC_RESP_TIMEOUT 5
+#define ME_HDLC_RX_BUF_OVERFLOW 6
+#define ME_HDLC_UNRESOLVED 1
+#define ME_HDLC_RESOLVED 2
+
+/*** Enums ***/
+typedef enum mei_error {
+ MEI_SUCCESS = 0,
+ MEI_FAILURE = -1,
+ MEI_MAILBOX_FULL = -2,
+ MEI_MAILBOX_EMPTY = -3,
+ MEI_MAILBOX_TIMEOUT = -4,
+} MEI_ERROR;
+
+#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app_ioctl.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app_ioctl.h
new file mode 100644
index 0000000000..08c3dd3fc1
--- /dev/null
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app_ioctl.h
@@ -0,0 +1,1191 @@
+/******************************************************************************
+**
+** FILE NAME : ifxmips_mei_app_ioctl.h
+** PROJECT : Danube
+** MODULES : MEI
+**
+** DATE : 1 Jan 2006
+** AUTHOR : TC Chen
+** DESCRIPTION : MEI Driver
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Version $Date $Author $Comment
+*******************************************************************************/
+#ifndef __IFXMIPS_MEI_APP_IOCTL_H
+#define __IFXMIPS_MEI_APP_IOCTL_H
+
+#ifdef __KERNEL__
+#include "ifxmips_mei_ioctl.h"
+#endif
+
+/* Interface Name */
+//#define INTERFACE_NAME <define the interface>
+
+/* adslLineTable constants */
+#define GET_ADSL_LINE_CODE 1
+
+/* adslAtucPhysTable constants */
+#define GET_ADSL_ATUC_PHY 4
+
+/* adslAturPhysTable constants */
+#define GET_ADSL_ATUR_PHY 10
+
+/* adslAtucChanTable constants */
+#define GET_ADSL_ATUC_CHAN_INFO 15
+
+/* adslAturChanTable constants */
+#define GET_ADSL_ATUR_CHAN_INFO 18
+
+/* adslAtucPerfDataTable constants */
+#define GET_ADSL_ATUC_PERF_DATA 21
+
+/* adslAturPerfDataTable constants */
+#define GET_ADSL_ATUR_PERF_DATA 40
+
+/* adslAtucIntervalTable constants */
+#define GET_ADSL_ATUC_INTVL_INFO 60
+
+/* adslAturIntervalTable constants */
+#define GET_ADSL_ATUR_INTVL_INFO 65
+
+/* adslAtucChanPerfDataTable constants */
+#define GET_ADSL_ATUC_CHAN_PERF_DATA 70
+
+/* adslAturChanPerfDataTable constants */
+#define GET_ADSL_ATUR_CHAN_PERF_DATA 90
+
+/* adslAtucChanIntervalTable constants */
+#define GET_ADSL_ATUC_CHAN_INTVL_INFO 110
+
+/* adslAturChanIntervalTable constants */
+#define GET_ADSL_ATUR_CHAN_INTVL_INFO 115
+
+/* adslLineAlarmConfProfileTable constants */
+#define GET_ADSL_ALRM_CONF_PROF 120
+#define SET_ADSL_ALRM_CONF_PROF 121
+
+/* adslAturTrap constants */
+#define ADSL_ATUR_TRAPS 135
+
+////////////////// RFC-3440 //////////////
+
+#ifdef IFXMIPS_MEI_MIB_RFC3440
+/* adslLineExtTable */
+#define GET_ADSL_ATUC_LINE_EXT 201
+#define SET_ADSL_ATUC_LINE_EXT 203
+
+/* adslAtucPerfDateExtTable */
+#define GET_ADSL_ATUC_PERF_DATA_EXT 205
+
+/* adslAtucIntervalExtTable */
+#define GET_ADSL_ATUC_INTVL_EXT_INFO 221
+
+/* adslAturPerfDataExtTable */
+#define GET_ADSL_ATUR_PERF_DATA_EXT 225
+
+/* adslAturIntervalExtTable */
+#define GET_ADSL_ATUR_INTVL_EXT_INFO 233
+
+/* adslAlarmConfProfileExtTable */
+#define GET_ADSL_ALRM_CONF_PROF_EXT 235
+#define SET_ADSL_ALRM_CONF_PROF_EXT 236
+
+/* adslAturExtTrap */
+#define ADSL_ATUR_EXT_TRAPS 240
+
+#endif
+
+/* The following constants are added to support the WEB related ADSL Statistics */
+
+/* adslLineStatus constants */
+#define GET_ADSL_LINE_STATUS 245
+
+/* adslLineRate constants */
+#define GET_ADSL_LINE_RATE 250
+
+/* adslLineInformation constants */
+#define GET_ADSL_LINE_INFO 255
+
+/* adslNearEndPerformanceStats constants */
+#define GET_ADSL_NEAREND_STATS 270
+
+/* adslFarEndPerformanceStats constants */
+#define GET_ADSL_FAREND_STATS 290
+
+/* Sub-carrier related parameters */
+#define GET_ADSL_LINE_INIT_STATS 150
+#define GET_ADSL_POWER_SPECTRAL_DENSITY 151
+
+#define IFXMIPS_MIB_LO_ATUC 295
+#define IFXMIPS_MIB_LO_ATUR 296
+
+#define GET_ADSL_ATUC_SUBCARRIER_STATS 297
+#define GET_ADSL_ATUR_SUBCARRIER_STATS 298
+
+
+
+///////////////////////////////////////////////////////////
+// makeCMV(Opcode, Group, Address, Index, Size, Data)
+
+/* adslLineCode Flags */
+#define LINE_CODE_FLAG 0x1 /* BIT 0th position */
+
+/* adslAtucPhysTable Flags */
+#define ATUC_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */
+#define ATUC_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 57, 0, 12, data,TxMessage)
+#define ATUC_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 57, 12, 4, data,TxMessage)
+
+#define ATUC_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */
+#define ATUC_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 64, 0, 4, data,TxMessage)
+
+#define ATUC_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */
+#define ATUC_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 58, 0, 8, data,TxMessage)
+
+#define ATUC_CURR_STAT_FLAG 0x8 /* BIT 3 */
+
+#define ATUC_CURR_OUT_PWR_FLAG 0x10 /* BIT 4 */
+#define ATUC_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 5, 1, data,TxMessage)
+
+#define ATUC_CURR_ATTR_FLAG 0x20 /* BIT 5 */
+#define ATUC_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 0, 2, data,TxMessage)
+
+
+/* adslAturPhysTable Flags */
+#define ATUR_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */
+#define ATUR_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 62, 0, 12, data,TxMessage)
+#define ATUR_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 62, 12, 4, data,TxMessage)
+
+#define ATUR_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */
+#define ATUR_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 65, 0, 4, data,TxMessage)
+
+#define ATUR_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */
+#define ATUR_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 61, 0, 8, data,TxMessage)
+
+#define ATUR_SNRMGN_FLAG 0x8
+#if 0 /* [ Ritesh. Use PLAM 45 0 for 0.1dB resolution rather than INFO 68 3 */
+#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 1, data,TxMessage)
+#else
+#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, PLAM_SNRMargin_0_1db, 0, 1, data, TxMessage)
+#endif
+
+#define ATUR_ATTN_FLAG 0x10
+#define ATUR_ATTN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data,TxMessage)
+
+#define ATUR_CURR_STAT_FLAG 0x20 /* BIT 3 */
+
+#define ATUR_CURR_OUT_PWR_FLAG 0x40 /* BIT 4 */
+#define ATUR_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 5, 1, data,TxMessage)
+
+#define ATUR_CURR_ATTR_FLAG 0x80 /* BIT 5 */
+#define ATUR_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 0, 2, data,TxMessage)
+
+/* adslAtucChanTable Flags */
+#define ATUC_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */
+//KD #define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 1, 1, data,TxMessage)
+#define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 92, 1, 1, data,TxMessage)
+
+#define ATUC_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */
+#define ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data,TxMessage)
+
+#define ATUC_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */
+
+/* adslAturChanTable Flags */
+#define ATUR_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */
+//KD #define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 2, 1, 1, data,TxMessage)
+#define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 93, 1, 1, data,TxMessage)
+
+#define ATUR_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */
+#define ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data,TxMessage)
+
+#define ATUR_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */
+
+#define ATUR_CHAN_CRC_BLK_LEN_FLAG 0x8 /* BIT 3 */
+
+/* adslAtucPerfDataTable Flags */
+#define ATUC_PERF_LOFS_FLAG 0x1 /* BIT 0th position */
+#define ATUC_PERF_LOSS_FLAG 0x2 /* BIT 1 */
+#define ATUC_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data,TxMessage)
+#define ATUC_PERF_ESS_FLAG 0x4 /* BIT 2 */
+#define ATUC_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data,TxMessage)
+#define ATUC_PERF_INITS_FLAG 0x8 /* BIT 3 */
+#define ATUC_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */
+#define ATUC_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */
+#define ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
+#define ATUC_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */
+#define ATUC_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */
+#define ATUC_PERF_CURR_15MIN_ESS_FLAG 0x200 /* BIT 9 */
+#define ATUC_PERF_CURR_15MIN_INIT_FLAG 0x400 /* BIT 10 */
+#define ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */
+#define ATUC_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */
+#define ATUC_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */
+#define ATUC_PERF_CURR_1DAY_ESS_FLAG 0x4000 /* BIT 14 */
+#define ATUC_PERF_CURR_1DAY_INIT_FLAG 0x8000 /* BIT 15 */
+#define ATUC_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */
+#define ATUC_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */
+#define ATUC_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */
+#define ATUC_PERF_PREV_1DAY_ESS_FLAG 0x80000 /* BIT 19 */
+#define ATUC_PERF_PREV_1DAY_INITS_FLAG 0x100000 /* BIT 20 */
+
+/* adslAturPerfDataTable Flags */
+#define ATUR_PERF_LOFS_FLAG 0x1 /* BIT 0th position */
+#define ATUR_PERF_LOSS_FLAG 0x2 /* BIT 1 */
+#define ATUR_PERF_LPR_FLAG 0x4 /* BIT 2 */
+#define ATUR_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data,TxMessage)
+#define ATUR_PERF_ESS_FLAG 0x8 /* BIT 3 */
+#define ATUR_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data,TxMessage)
+#define ATUR_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */
+#define ATUR_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */
+#define ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
+#define ATUR_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */
+#define ATUR_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */
+#define ATUR_PERF_CURR_15MIN_LPR_FLAG 0x200 /* BIT 9 */
+#define ATUR_PERF_CURR_15MIN_ESS_FLAG 0x400 /* BIT 10 */
+#define ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */
+#define ATUR_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */
+#define ATUR_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */
+#define ATUR_PERF_CURR_1DAY_LPR_FLAG 0x4000 /* BIT 14 */
+#define ATUR_PERF_CURR_1DAY_ESS_FLAG 0x8000 /* BIT 15 */
+#define ATUR_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */
+#define ATUR_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */
+#define ATUR_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */
+#define ATUR_PERF_PREV_1DAY_LPR_FLAG 0x80000 /* BIT 19 */
+#define ATUR_PERF_PREV_1DAY_ESS_FLAG 0x100000 /* BIT 20 */
+
+/* adslAtucIntervalTable Flags */
+#define ATUC_INTVL_LOF_FLAG 0x1 /* BIT 0th position */
+#define ATUC_INTVL_LOS_FLAG 0x2 /* BIT 1 */
+#define ATUC_INTVL_ESS_FLAG 0x4 /* BIT 2 */
+#define ATUC_INTVL_INIT_FLAG 0x8 /* BIT 3 */
+#define ATUC_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */
+
+/* adslAturIntervalTable Flags */
+#define ATUR_INTVL_LOF_FLAG 0x1 /* BIT 0th position */
+#define ATUR_INTVL_LOS_FLAG 0x2 /* BIT 1 */
+#define ATUR_INTVL_LPR_FLAG 0x4 /* BIT 2 */
+#define ATUR_INTVL_ESS_FLAG 0x8 /* BIT 3 */
+#define ATUR_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */
+
+/* adslAtucChanPerfDataTable Flags */
+#define ATUC_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */
+#define ATUC_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */
+#define ATUC_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */
+#define ATUC_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */
+#define ATUC_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */
+#define ATUC_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */
+#define ATUC_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
+#define ATUC_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */
+#define ATUC_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */
+#define ATUC_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */
+#define ATUC_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */
+#define ATUC_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11*/
+#define ATUC_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */
+#define ATUC_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */
+#define ATUC_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */
+#define ATUC_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */
+#define ATUC_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */
+#define ATUC_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */
+#define ATUC_CHAN_PERF_PREV_1DAY_TX_BLK_FLAG 0x40000 /* BIT 18 */
+#define ATUC_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */
+#define ATUC_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */
+
+
+/* adslAturChanPerfDataTable Flags */
+#define ATUR_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */
+#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data,TxMessage)
+#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data,TxMessage)
+#define ATUR_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */
+#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data,TxMessage)
+#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data,TxMessage)
+#define ATUR_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */
+#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data,TxMessage)
+#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data,TxMessage)
+#define ATUR_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */
+#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data,TxMessage)
+#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data,TxMessage)
+#define ATUR_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */
+#define ATUR_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */
+#define ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
+#define ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */
+#define ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */
+#define ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */
+#define ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */
+#define ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */
+#define ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */
+#define ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */
+#define ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */
+#define ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */
+#define ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */
+#define ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */
+#define ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG 0x40000 /* BIT 18 */
+#define ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */
+#define ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */
+
+/* adslAtucChanIntervalTable Flags */
+#define ATUC_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th position */
+#define ATUC_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */
+#define ATUC_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */
+#define ATUC_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */
+#define ATUC_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */
+#define ATUC_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */
+
+/* adslAturChanIntervalTable Flags */
+#define ATUR_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th Position */
+#define ATUR_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */
+#define ATUR_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */
+#define ATUR_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */
+#define ATUR_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */
+#define ATUR_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */
+
+/* adslLineAlarmConfProfileTable Flags */
+#define ATUC_THRESH_15MIN_LOFS_FLAG 0x01 /* BIT 0th position */
+#define ATUC_THRESH_15MIN_LOSS_FLAG 0x02 /* BIT 1 */
+#define ATUC_THRESH_15MIN_ESS_FLAG 0x04 /* BIT 2 */
+#define ATUC_THRESH_FAST_RATEUP_FLAG 0x08 /* BIT 3 */
+#define ATUC_THRESH_INTERLEAVE_RATEUP_FLAG 0x10 /* BIT 4 */
+#define ATUC_THRESH_FAST_RATEDOWN_FLAG 0x20 /* BIT 5 */
+#define ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x40 /* BIT 6 */
+#define ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG 0x80 /* BIT 7 */
+#define ATUR_THRESH_15MIN_LOFS_FLAG 0x100 /* BIT 8 */
+#define ATUR_THRESH_15MIN_LOSS_FLAG 0x200 /* BIT 9 */
+#define ATUR_THRESH_15MIN_LPRS_FLAG 0x400 /* BIT 10 */
+#define ATUR_THRESH_15MIN_ESS_FLAG 0x800 /* BIT 11 */
+#define ATUR_THRESH_FAST_RATEUP_FLAG 0x1000 /* BIT 12 */
+#define ATUR_THRESH_INTERLEAVE_RATEUP_FLAG 0x2000 /* BIT 13 */
+#define ATUR_THRESH_FAST_RATEDOWN_FLAG 0x4000 /* BIT 14 */
+#define ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x8000 /* BIT 15 */
+#define LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG 0x10000 /* BIT 16 */
+
+
+/* adslAturTraps Flags */
+#define ATUC_PERF_LOFS_THRESH_FLAG 0x1 /* BIT 0th position */
+#define ATUC_PERF_LOSS_THRESH_FLAG 0x2 /* BIT 1 */
+#define ATUC_PERF_ESS_THRESH_FLAG 0x4 /* BIT 2 */
+#define ATUC_RATE_CHANGE_FLAG 0x8 /* BIT 3 */
+#define ATUR_PERF_LOFS_THRESH_FLAG 0x10 /* BIT 4 */
+#define ATUR_PERF_LOSS_THRESH_FLAG 0x20 /* BIT 5 */
+#define ATUR_PERF_LPRS_THRESH_FLAG 0x40 /* BIT 6 */
+#define ATUR_PERF_ESS_THRESH_FLAG 0x80 /* BIT 7 */
+#define ATUR_RATE_CHANGE_FLAG 0x100 /* BIT 8 */
+
+//RFC- 3440 FLAG DEFINITIONS
+
+#ifdef IFXMIPS_MEI_MIB_RFC3440
+/* adslLineExtTable flags */
+#define ATUC_LINE_TRANS_CAP_FLAG 0x1 /* BIT 0th position */
+#define ATUC_LINE_TRANS_CAP_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data,TxMessage)
+#define ATUC_LINE_TRANS_CONFIG_FLAG 0x2 /* BIT 1 */
+#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data,TxMessage)
+#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR makeCMV(H2D_CMV_WRITE,INFO, 67, 0, 1, data,TxMessage)
+#define ATUC_LINE_TRANS_ACTUAL_FLAG 0x4 /* BIT 2 */
+#define ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 1, 0, 1, data,TxMessage)
+#define LINE_GLITE_POWER_STATE_FLAG 0x8 /* BIT 3 */
+#define LINE_GLITE_POWER_STATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 0, 0, 1, data,TxMessage)
+
+/* adslAtucPerfDataExtTable flags */
+#define ATUC_PERF_STAT_FASTR_FLAG 0x1 /* BIT 0th position */
+#define ATUC_PERF_STAT_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data, TxMessage)
+#define ATUC_PERF_STAT_FAILED_FASTR_FLAG 0x2 /* BIT 1 */
+#define ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data, TxMessage)
+#define ATUC_PERF_STAT_SESL_FLAG 0X4 /* BIT 2 */
+#define ATUC_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data, TxMessage)
+#define ATUC_PERF_STAT_UASL_FLAG 0X8 /* BIT 3 */
+#define ATUC_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data, TxMessage)
+#define ATUC_PERF_CURR_15MIN_FASTR_FLAG 0X10 /* BIT 4 */
+#define ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG 0X20 /* BIT 5 */
+#define ATUC_PERF_CURR_15MIN_SESL_FLAG 0X40 /* BIT 6 */
+#define ATUC_PERF_CURR_15MIN_UASL_FLAG 0X80 /* BIT 7 */
+#define ATUC_PERF_CURR_1DAY_FASTR_FLAG 0X100 /* BIT 8 */
+#define ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG 0X200 /* BIT 9 */
+#define ATUC_PERF_CURR_1DAY_SESL_FLAG 0X400 /* BIT 10 */
+#define ATUC_PERF_CURR_1DAY_UASL_FLAG 0X800 /* BIT 11 */
+#define ATUC_PERF_PREV_1DAY_FASTR_FLAG 0X1000 /* BIT 12 */
+#define ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG 0X2000 /* BIT 13 */
+#define ATUC_PERF_PREV_1DAY_SESL_FLAG 0X4000 /* BIT 14 */
+#define ATUC_PERF_PREV_1DAY_UASL_FLAG 0X8000 /* BIT 15 */
+
+/* adslAturPerfDataExtTable */
+#define ATUR_PERF_STAT_SESL_FLAG 0X1 /* BIT 0th position */
+#define ATUR_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data, TxMessage)
+#define ATUR_PERF_STAT_UASL_FLAG 0X2 /* BIT 1 */
+#define ATUR_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data, TxMessage)
+#define ATUR_PERF_CURR_15MIN_SESL_FLAG 0X4 /* BIT 2 */
+#define ATUR_PERF_CURR_15MIN_UASL_FLAG 0X8 /* BIT 3 */
+#define ATUR_PERF_CURR_1DAY_SESL_FLAG 0X10 /* BIT 4 */
+#define ATUR_PERF_CURR_1DAY_UASL_FLAG 0X20 /* BIT 5 */
+#define ATUR_PERF_PREV_1DAY_SESL_FLAG 0X40 /* BIT 6 */
+#define ATUR_PERF_PREV_1DAY_UASL_FLAG 0X80 /* BIT 7 */
+
+/* adslAutcIntervalExtTable flags */
+#define ATUC_INTERVAL_FASTR_FLAG 0x1 /* Bit 0 */
+#define ATUC_INTERVAL_FAILED_FASTR_FLAG 0x2 /* Bit 1 */
+#define ATUC_INTERVAL_SESL_FLAG 0x4 /* Bit 2 */
+#define ATUC_INTERVAL_UASL_FLAG 0x8 /* Bit 3 */
+
+/* adslAturIntervalExtTable */
+#define ATUR_INTERVAL_SESL_FLAG 0X1 /* BIT 0th position */
+#define ATUR_INTERVAL_UASL_FLAG 0X2 /* BIT 1 */
+
+/* adslAlarmConfProfileExtTable */
+#define ATUC_THRESH_15MIN_FAILED_FASTR_FLAG 0X1/* BIT 0th position */
+#define ATUC_THRESH_15MIN_SESL_FLAG 0X2 /* BIT 1 */
+#define ATUC_THRESH_15MIN_UASL_FLAG 0X4 /* BIT 2 */
+#define ATUR_THRESH_15MIN_SESL_FLAG 0X8 /* BIT 3 */
+#define ATUR_THRESH_15MIN_UASL_FLAG 0X10 /* BIT 4 */
+
+/* adslAturExtTraps */
+#define ATUC_15MIN_FAILED_FASTR_TRAP_FLAG 0X1 /* BIT 0th position */
+#define ATUC_15MIN_SESL_TRAP_FLAG 0X2 /* BIT 1 */
+#define ATUC_15MIN_UASL_TRAP_FLAG 0X4 /* BIT 2 */
+#define ATUR_15MIN_SESL_TRAP_FLAG 0X8 /* BIT 3 */
+#define ATUR_15MIN_UASL_TRAP_FLAG 0X10 /* BIT 4 */
+
+#endif
+
+/* adslLineStatus Flags */
+#define LINE_STAT_MODEM_STATUS_FLAG 0x1 /* BIT 0th position */
+#define LINE_STAT_MODEM_STATUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data, TxMessage)
+#define LINE_STAT_MODE_SEL_FLAG 0x2 /* BIT 1 */
+#define LINE_STAT_MODE_SEL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data, TxMessage)
+#define LINE_STAT_TRELLCOD_ENABLE_FLAG 0x4 /* BIT 2 */
+#define LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, OPTN, 2, 0, 1, data, TxMessage)
+#define LINE_STAT_LATENCY_FLAG 0x8 /* BIT 3 */
+#define LINE_STAT_LATENCY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 12, 0, 1, data, TxMessage)
+
+/* adslLineRate Flags */
+#define LINE_RATE_DATA_RATEDS_FLAG 0x1 /* BIT 0th position */
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data, TxMessage)
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 2, 2, data, TxMessage)
+
+
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 0, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 0, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 0, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 0, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 0, 2, data, TxMessage)
+
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 1, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 1, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 1, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 1, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 2, 2, data, TxMessage)
+
+#define LINE_RATE_DATA_RATEUS_FLAG 0x2 /* BIT 1 */
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data, TxMessage)
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 2, 2, data, TxMessage)
+
+
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 0, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 0, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 0, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 0, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 0, 2, data, TxMessage)
+
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 1, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 1, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 1, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 1, 1, data, TxMessage)
+#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 2, 2, data, TxMessage)
+
+#define LINE_RATE_ATTNDRDS_FLAG 0x4 /* BIT 2 */
+#define LINE_RATE_ATTNDRDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 2, data, TxMessage)
+
+#define LINE_RATE_ATTNDRUS_FLAG 0x8 /* BIT 3 */
+#define LINE_RATE_ATTNDRUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 4, 2, data, TxMessage)
+
+/* adslLineInformation Flags */
+#define LINE_INFO_INTLV_DEPTHDS_FLAG 0x1 /* BIT 0th position */
+#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 0, 1, data, TxMessage)
+#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 1, 1, data, TxMessage)
+#define LINE_INFO_INTLV_DEPTHUS_FLAG 0x2 /* BIT 1 */
+#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 0, 1, data, TxMessage)
+#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 1, 1, data, TxMessage)
+#define LINE_INFO_LATNDS_FLAG 0x4 /* BIT 2 */
+#define LINE_INFO_LATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 1, 1, data, TxMessage)
+#define LINE_INFO_LATNUS_FLAG 0x8 /* BIT 3 */
+#define LINE_INFO_LATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 1, 1, data, TxMessage)
+#define LINE_INFO_SATNDS_FLAG 0x10 /* BIT 4 */
+#define LINE_INFO_SATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data, TxMessage)
+#define LINE_INFO_SATNUS_FLAG 0x20 /* BIT 5 */
+#define LINE_INFO_SATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 2, 1, data, TxMessage)
+#define LINE_INFO_SNRMNDS_FLAG 0x40 /* BIT 6 */
+#define LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 3, 1, data, TxMessage)
+#define LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 0, 1, data, TxMessage)
+#define LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 46, 0, 1, data, TxMessage)
+#define LINE_INFO_SNRMNUS_FLAG 0x80 /* BIT 7 */
+#define LINE_INFO_SNRMNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 3, 1, data, TxMessage)
+#define LINE_INFO_ACATPDS_FLAG 0x100 /* BIT 8 */
+#define LINE_INFO_ACATPDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 6, 1, data, TxMessage)
+#define LINE_INFO_ACATPUS_FLAG 0x200 /* BIT 9 */
+#define LINE_INFO_ACATPUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 6, 1, data, TxMessage)
+
+/* adslNearEndPerformanceStats Flags */
+#define NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data, TxMessage)
+#define NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data, TxMessage)
+#define NEAREND_PERF_SUPERFRAME_FLAG 0x1 /* BIT 0th position */
+#define NEAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data, TxMessage)
+#define NEAREND_PERF_LOS_FLAG 0x2 /* BIT 1 */
+#define NEAREND_PERF_LOF_FLAG 0x4 /* BIT 2 */
+#define NEAREND_PERF_LPR_FLAG 0x8 /* BIT 3 */
+#define NEAREND_PERF_NCD_FLAG 0x10 /* BIT 4 */
+#define NEAREND_PERF_LCD_FLAG 0x20 /* BIT 5 */
+#define NEAREND_PERF_CRC_FLAG 0x40 /* BIT 6 */
+#define NEAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data, TxMessage)
+#define NEAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data, TxMessage)
+#define NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data, TxMessage)
+#define NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data, TxMessage)
+#define NEAREND_PERF_RSCORR_FLAG 0x80 /* BIT 7 */
+#define NEAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 6, 0, 1, data, TxMessage)
+#define NEAREND_PERF_FECS_FLAG 0x100 /* BIT 8 */
+#define NEAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data, TxMessage)
+#define NEAREND_PERF_ES_FLAG 0x200 /* BIT 9 */
+#define NEAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data, TxMessage)
+#define NEAREND_PERF_SES_FLAG 0x400 /* BIT 10 */
+#define NEAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 9, 0, 1, data, TxMessage)
+#define NEAREND_PERF_LOSS_FLAG 0x800 /* BIT 11 */
+#define NEAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data, TxMessage)
+#define NEAREND_PERF_UAS_FLAG 0x1000 /* BIT 12 */
+#define NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 0, 2, data, TxMessage)
+#define NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 2, 2, data, TxMessage)
+#define NEAREND_PERF_HECERR_FLAG 0x2000 /* BIT 13 */
+
+/* adslFarEndPerformanceStats Flags */
+#define FAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data, TxMessage)
+#define FAREND_PERF_LOS_FLAG 0x1 /* BIT 0th position */
+#define FAREND_PERF_LOF_FLAG 0x2 /* BIT 1 */
+#define FAREND_PERF_LPR_FLAG 0x4 /* BIT 2 */
+#define FAREND_PERF_NCD_FLAG 0x8 /* BIT 3 */
+#define FAREND_PERF_LCD_FLAG 0x10 /* BIT 4 */
+#define FAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 0, 1, data, TxMessage)
+#define FAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 1, 1, data, TxMessage)
+#define FAREND_PERF_CRC_FLAG 0x20 /* BIT 5 */
+#define FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 0, 1, data, TxMessage)
+#define FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 1, 1, data, TxMessage)
+#define FAREND_PERF_RSCORR_FLAG 0x40 /* BIT 6 */
+#define FAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 32, 0, 1, data, TxMessage)
+#define FAREND_PERF_FECS_FLAG 0x80 /* BIT 7 */
+#define FAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data, TxMessage)
+#define FAREND_PERF_ES_FLAG 0x100 /* BIT 8 */
+#define FAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data, TxMessage)
+#define FAREND_PERF_SES_FLAG 0x200 /* BIT 9 */
+#define FAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 35, 0, 1, data, TxMessage)
+#define FAREND_PERF_LOSS_FLAG 0x400 /* BIT 10 */
+#define FAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data, TxMessage)
+#define FAREND_PERF_UAS_FLAG 0x800 /* BIT 11 */
+#define FAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 0, 2, data, TxMessage)
+#define FAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 2, 2, data, TxMessage)
+#define FAREND_PERF_HECERR_FLAG 0x1000 /* BIT 12 */
+// 603221:tc.chen end
+/* TR-69 related additional parameters - defines */
+/* Defines for struct adslATURSubcarrierInfo */
+#define NEAREND_HLINSC 0x1
+#define NEAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 71, 2, 1, data, TxMessage)
+#define NEAREND_HLINPS 0x2
+#define NEAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 73, idx, size, data, TxMessage)
+#define NEAREND_HLOGMT 0x4
+#define NEAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 0, 1, data, TxMessage)
+#define NEAREND_HLOGPS 0x8
+#define NEAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 75, idx, size, data, TxMessage)
+#define NEAREND_QLNMT 0x10
+#define NEAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 1, 1, data, TxMessage)
+#define NEAREND_QLNPS 0x20
+#define NEAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 77, idx, size, data, TxMessage)
+#define NEAREND_SNRMT 0x40
+#define NEAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 2, 1, data, TxMessage)
+#define NEAREND_SNRPS 0x80
+#define NEAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 78, idx, size, data, TxMessage)
+#define NEAREND_BITPS 0x100
+#define NEAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 22, idx, size, data, TxMessage)
+#define NEAREND_GAINPS 0x200
+#define NEAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 24, idx, size, data, TxMessage)
+
+/* Defines for struct adslATUCSubcarrierInfo */
+#define FAREND_HLINSC 0x1
+
+/* As per the feedback from Knut on 21/08/2006, the cmv command of HLINSC should be INFO 70 2 */
+#define FAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 70, 2, 1, data, TxMessage)
+#define FAREND_HLINPS 0x2
+#define FAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 72, idx, size, data, TxMessage)
+#define FAREND_HLOGMT 0x4
+#define FAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 0, 1, data, TxMessage)
+#define FAREND_HLOGPS 0x8
+#define FAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 74, idx, size, data, TxMessage)
+#define FAREND_QLNMT 0x10
+#define FAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 1, 1, data, TxMessage)
+#define FAREND_QLNPS 0x20
+#define FAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 76, idx, size, data, TxMessage)
+#define FAREND_SNRMT 0x40
+#define FAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 2, 1, data, TxMessage)
+#define FAREND_SNRPS 0x80
+#define FAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 11, idx, size, data, TxMessage)
+#define FAREND_SNRPS_DIAG_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 10, idx, size, data, TxMessage)
+#define FAREND_BITPS 0x100
+#define FAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 23, idx, size, data, TxMessage)
+#define FAREND_GAINPS 0x200
+#define FAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 25, idx, size, data, TxMessage)
+
+
+// GET_ADSL_POWER_SPECTRAL_DENSITY
+#define NOMPSD_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 0, 1, data, TxMessage)
+#define NOMPSD_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 1, 1, data, TxMessage)
+#define PCB_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 6, 1, data, TxMessage)
+#define PCB_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 7, 1, data, TxMessage)
+#define RMSGI_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 10, 1, data, TxMessage)
+#define RMSGI_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 11, 1, data, TxMessage)
+
+/////////////////////////////////////////////////Macro Definitions ? FLAG Setting & Testing
+
+#define SET_FLAG(flags, flag_val) ((*flags) = ((*flags) | flag_val))
+// -- This macro sets the flags with the flag_val. Here flags is passed as a pointer
+
+#define IS_FLAG_SET(flags, test_flag) (((*flags) & (test_flag)) == (test_flag)? test_flag:0)
+// -- This macro verifies whether test_flag has been set in flags. Here flags is passed as a pointer
+
+
+#define CLR_FLAG(flags, flag_bit) ((*flags) = (*flags) & (~flag_bit))
+// -- This macro resets the specified flag_bit in the flags. Here flags is passed as a pointer
+
+
+////////////////////////////////////////////////DATA STRUCTURES ORGANIZATION
+
+//Here are the data structures used for accessing mib parameters. The ioctl call includes the third parameter as a void pointer. This parameter has to be type-casted in the driver code to the corresponding structure depending upon the command type. For Ex: consider the ioctl used to get the adslLineCode type, ioctl(fd,GET_ADSL_LINE_CODE,void *struct_adslLineTableEntry). In the driver code we check on the type of the command, i.e GET_ADSL_LINE_CODE and type-cast the void pointer to struct adslLineTableEntry type.
+ //
+#define u32 unsigned int
+#define u16 unsigned short
+#define s16 short
+#define u8 unsigned char
+
+
+typedef u32 AdslPerfTimeElapsed;
+typedef u32 AdslPerfPrevDayCount;
+typedef u32 PerfCurrentCount;
+typedef u32 PerfIntervalCount;
+typedef u32 AdslPerfCurrDayCount;
+
+
+//ioctl(int fd, GET_ADSL_LINE_CODE, void *struct_adslLineTableEntry)
+
+typedef struct adslLineTableEntry {
+ int ifIndex;
+ int adslLineCode;
+ u8 flags;
+} adslLineTableEntry;
+
+#ifdef IFXMIPS_MEI_MIB_RFC3440
+typedef struct adslLineExtTableEntry {
+ int ifIndex;
+ u16 adslLineTransAtucCap;
+ u16 adslLineTransAtucConfig;
+ u16 adslLineTransAtucActual;
+ int adslLineGlitePowerState;
+ u32 flags;
+}adslLineExtTableEntry;
+#endif
+//ioctl(int fd, GET_ADSL_ATUC_PHY, void *struct_adslAtucPhysEntry)
+#ifndef u_char
+#define u_char u8
+#endif
+
+typedef struct adslVendorId {
+ u16 country_code;
+ u_char provider_id[4]; /* Ascii characters */
+ u_char revision_info[2];
+}adslVendorId;
+
+typedef struct adslAtucPhysEntry {
+ int ifIndex;
+ char serial_no[32];
+ union {
+ char vendor_id[16];
+ adslVendorId vendor_info;
+ } vendor_id;
+ char version_no[16];
+ u32 status;
+ int outputPwr;
+ u32 attainableRate;
+ u8 flags;
+} adslAtucPhysEntry;
+
+
+//ioctl(int fd, GET_ADSL_ATUR_PHY, void *struct_adslAturPhysEntry)
+
+typedef struct adslAturPhysEntry {
+ int ifIndex;
+ char serial_no[32];
+ union {
+ char vendor_id[16];
+ adslVendorId vendor_info;
+ } vendor_id;
+ char version_no[16];
+ int SnrMgn;
+ u32 Attn;
+ u32 status;
+ int outputPwr;
+ u32 attainableRate;
+ u8 flags;
+} adslAturPhysEntry;
+
+
+//ioctl(int fd, GET_ADSL_ATUC_CHAN_INFO, void *struct_adslAtucChanInfo)
+
+typedef struct adslAtucChanInfo {
+ int ifIndex;
+ u32 interleaveDelay;
+ u32 currTxRate;
+ u32 prevTxRate;
+ u8 flags;
+} adslAtucChanInfo;
+
+
+//ioctl(int fd, GET_ADSL_ATUR_CHAN_INFO, void *struct_adslAturChanInfo)
+
+typedef struct adslAturChanInfo {
+ int ifIndex;
+ u32 interleaveDelay;
+ u32 currTxRate;
+ u32 prevTxRate;
+ u32 crcBlkLen;
+ u8 flags;
+} adslAturChanInfo;
+
+
+//ioctl(int fd, GET_ADSL_ATUC_PERF_DATA, void *struct_atucPerfDataEntry)
+
+typedef struct atucPerfDataEntry
+{
+ int ifIndex;
+ u32 adslAtucPerfLofs;
+ u32 adslAtucPerfLoss;
+ u32 adslAtucPerfESs;
+ u32 adslAtucPerfInits;
+ int adslAtucPerfValidIntervals;
+ int adslAtucPerfInvalidIntervals;
+ AdslPerfTimeElapsed adslAtucPerfCurr15MinTimeElapsed;
+ PerfCurrentCount adslAtucPerfCurr15MinLofs;
+ PerfCurrentCount adslAtucPerfCurr15MinLoss;
+ PerfCurrentCount adslAtucPerfCurr15MinESs;
+ PerfCurrentCount adslAtucPerfCurr15MinInits;
+ AdslPerfTimeElapsed adslAtucPerfCurr1DayTimeElapsed;
+ AdslPerfCurrDayCount adslAtucPerfCurr1DayLofs;
+ AdslPerfCurrDayCount adslAtucPerfCurr1DayLoss;
+ AdslPerfCurrDayCount adslAtucPerfCurr1DayESs;
+ AdslPerfCurrDayCount adslAtucPerfCurr1DayInits;
+ int adslAtucPerfPrev1DayMoniSecs;
+ AdslPerfPrevDayCount adslAtucPerfPrev1DayLofs;
+ AdslPerfPrevDayCount adslAtucPerfPrev1DayLoss;
+ AdslPerfPrevDayCount adslAtucPerfPrev1DayESs;
+ AdslPerfPrevDayCount adslAtucPerfPrev1DayInits;
+ u32 flags;
+} atucPerfDataEntry;
+
+#ifdef IFXMIPS_MEI_MIB_RFC3440
+typedef struct atucPerfDataExtEntry
+ {
+ int ifIndex;
+ u32 adslAtucPerfStatFastR;
+ u32 adslAtucPerfStatFailedFastR;
+ u32 adslAtucPerfStatSesL;
+ u32 adslAtucPerfStatUasL;
+ u32 adslAtucPerfCurr15MinFastR;
+ u32 adslAtucPerfCurr15MinFailedFastR;
+ u32 adslAtucPerfCurr15MinSesL;
+ u32 adslAtucPerfCurr15MinUasL;
+ u32 adslAtucPerfCurr1DayFastR;
+ u32 adslAtucPerfCurr1DayFailedFastR;
+ u32 adslAtucPerfCurr1DaySesL;
+ u32 adslAtucPerfCurr1DayUasL;
+ u32 adslAtucPerfPrev1DayFastR;
+ u32 adslAtucPerfPrev1DayFailedFastR;
+ u32 adslAtucPerfPrev1DaySesL;
+ u32 adslAtucPerfPrev1DayUasL;
+ u32 flags;
+} atucPerfDataExtEntry;
+
+#endif
+//ioctl(int fd, GET_ADSL_ATUR_PERF_DATA, void *struct_aturPerfDataEntry)
+
+typedef struct aturPerfDataEntry
+{
+ int ifIndex;
+ u32 adslAturPerfLofs;
+ u32 adslAturPerfLoss;
+ u32 adslAturPerfLprs;
+ u32 adslAturPerfESs;
+ int adslAturPerfValidIntervals;
+ int adslAturPerfInvalidIntervals;
+ AdslPerfTimeElapsed adslAturPerfCurr15MinTimeElapsed;
+ PerfCurrentCount adslAturPerfCurr15MinLofs;
+ PerfCurrentCount adslAturPerfCurr15MinLoss;
+ PerfCurrentCount adslAturPerfCurr15MinLprs;
+ PerfCurrentCount adslAturPerfCurr15MinESs;
+ AdslPerfTimeElapsed adslAturPerfCurr1DayTimeElapsed;
+ AdslPerfCurrDayCount adslAturPerfCurr1DayLofs;
+ AdslPerfCurrDayCount adslAturPerfCurr1DayLoss;
+ AdslPerfCurrDayCount adslAturPerfCurr1DayLprs;
+ AdslPerfCurrDayCount adslAturPerfCurr1DayESs;
+ int adslAturPerfPrev1DayMoniSecs;
+ AdslPerfPrevDayCount adslAturPerfPrev1DayLofs;
+ AdslPerfPrevDayCount adslAturPerfPrev1DayLoss;
+ AdslPerfPrevDayCount adslAturPerfPrev1DayLprs;
+ AdslPerfPrevDayCount adslAturPerfPrev1DayESs;
+ u32 flags;
+} aturPerfDataEntry;
+
+#ifdef IFXMIPS_MEI_MIB_RFC3440
+typedef struct aturPerfDataExtEntry
+ {
+ int ifIndex;
+ u32 adslAturPerfStatSesL;
+ u32 adslAturPerfStatUasL;
+ u32 adslAturPerfCurr15MinSesL;
+ u32 adslAturPerfCurr15MinUasL;
+ u32 adslAturPerfCurr1DaySesL;
+ u32 adslAturPerfCurr1DayUasL;
+ u32 adslAturPerfPrev1DaySesL;
+ u32 adslAturPerfPrev1DayUasL;
+ u32 flags;
+} aturPerfDataExtEntry;
+#endif
+//ioctl(int fd, GET_ADSL_ATUC_INTVL_INFO, void *struct_adslAtucInvtInfo)
+
+typedef struct adslAtucIntvlInfo {
+ int ifIndex;
+ int IntervalNumber;
+ PerfIntervalCount intervalLOF;
+ PerfIntervalCount intervalLOS;
+ PerfIntervalCount intervalES;
+ PerfIntervalCount intervalInits;
+ int intervalValidData;
+ u8 flags;
+} adslAtucIntvlInfo;
+
+#ifdef IFXMIPS_MEI_MIB_RFC3440
+typedef struct adslAtucInvtlExtInfo
+ {
+ int ifIndex;
+ int IntervalNumber;
+ u32 adslAtucIntervalFastR;
+ u32 adslAtucIntervalFailedFastR;
+ u32 adslAtucIntervalSesL;
+ u32 adslAtucIntervalUasL;
+ u32 flags;
+} adslAtucInvtlExtInfo;
+#endif
+//ioctl(int fd, GET_ADSL_ATUR_INTVL_INFO, void *struct_adslAturInvtlInfo)
+
+typedef struct adslAturIntvlInfo {
+ int ifIndex;
+ int IntervalNumber;
+ PerfIntervalCount intervalLOF;
+ PerfIntervalCount intervalLOS;
+ PerfIntervalCount intervalLPR;
+ PerfIntervalCount intervalES;
+ int intervalValidData;
+ u8 flags;
+} adslAturIntvlInfo;
+
+#ifdef IFXMIPS_MEI_MIB_RFC3440
+typedef struct adslAturInvtlExtInfo
+ {
+ int ifIndex;
+ int IntervalNumber;
+ u32 adslAturIntervalSesL;
+ u32 adslAturIntervalUasL;
+ u32 flags;
+} adslAturInvtlExtInfo;
+#endif
+//ioctl(int fd, GET_ADSL_ATUC_CHAN_PERF_DATA, void *struct_atucChannelPerfDataEntry)
+
+typedef struct atucChannelPerfDataEntry
+{
+ int ifIndex;
+ u32 adslAtucChanReceivedBlks;
+ u32 adslAtucChanTransmittedBlks;
+ u32 adslAtucChanCorrectedBlks;
+ u32 adslAtucChanUncorrectBlks;
+ int adslAtucChanPerfValidIntervals;
+ int adslAtucChanPerfInvalidIntervals;
+ AdslPerfTimeElapsed adslAtucChanPerfCurr15MinTimeElapsed;
+ PerfCurrentCount adslAtucChanPerfCurr15MinReceivedBlks;
+ PerfCurrentCount adslAtucChanPerfCurr15MinTransmittedBlks;
+ PerfCurrentCount adslAtucChanPerfCurr15MinCorrectedBlks;
+ PerfCurrentCount adslAtucChanPerfCurr15MinUncorrectBlks;
+ AdslPerfTimeElapsed adslAtucChanPerfCurr1DayTimeElapsed;
+ AdslPerfCurrDayCount adslAtucChanPerfCurr1DayReceivedBlks;
+ AdslPerfCurrDayCount adslAtucChanPerfCurr1DayTransmittedBlks;
+ AdslPerfCurrDayCount adslAtucChanPerfCurr1DayCorrectedBlks;
+ AdslPerfCurrDayCount adslAtucChanPerfCurr1DayUncorrectBlks;
+ int adslAtucChanPerfPrev1DayMoniSecs;
+ AdslPerfPrevDayCount adslAtucChanPerfPrev1DayReceivedBlks;
+ AdslPerfPrevDayCount adslAtucChanPerfPrev1DayTransmittedBlks;
+ AdslPerfPrevDayCount adslAtucChanPerfPrev1DayCorrectedBlks;
+ AdslPerfPrevDayCount adslAtucChanPerfPrev1DayUncorrectBlks;
+ u32 flags;
+}atucChannelPerfDataEntry;
+
+
+//ioctl(int fd, GET_ADSL_ATUR_CHAN_PERF_DATA, void *struct_aturChannelPerfDataEntry)
+
+typedef struct aturChannelPerfDataEntry
+{
+ int ifIndex;
+ u32 adslAturChanReceivedBlks;
+ u32 adslAturChanTransmittedBlks;
+ u32 adslAturChanCorrectedBlks;
+ u32 adslAturChanUncorrectBlks;
+ int adslAturChanPerfValidIntervals;
+ int adslAturChanPerfInvalidIntervals;
+ AdslPerfTimeElapsed adslAturChanPerfCurr15MinTimeElapsed;
+ PerfCurrentCount adslAturChanPerfCurr15MinReceivedBlks;
+ PerfCurrentCount adslAturChanPerfCurr15MinTransmittedBlks;
+ PerfCurrentCount adslAturChanPerfCurr15MinCorrectedBlks;
+ PerfCurrentCount adslAturChanPerfCurr15MinUncorrectBlks;
+ AdslPerfTimeElapsed adslAturChanPerfCurr1DayTimeElapsed;
+ AdslPerfCurrDayCount adslAturChanPerfCurr1DayReceivedBlks;
+ AdslPerfCurrDayCount adslAturChanPerfCurr1DayTransmittedBlks;
+ AdslPerfCurrDayCount adslAturChanPerfCurr1DayCorrectedBlks;
+ AdslPerfCurrDayCount adslAturChanPerfCurr1DayUncorrectBlks;
+ int adslAturChanPerfPrev1DayMoniSecs;
+ AdslPerfPrevDayCount adslAturChanPerfPrev1DayReceivedBlks;
+ AdslPerfPrevDayCount adslAturChanPerfPrev1DayTransmittedBlks;
+ AdslPerfPrevDayCount adslAturChanPerfPrev1DayCorrectedBlks;
+ AdslPerfPrevDayCount adslAturChanPerfPrev1DayUncorrectBlks;
+ u32 flags;
+} aturChannelPerfDataEntry;
+
+
+//ioctl(int fd, GET_ADSL_ATUC_CHAN_INTVL_INFO, void *struct_adslAtucChanIntvlInfo)
+
+typedef struct adslAtucChanIntvlInfo {
+ int ifIndex;
+ int IntervalNumber;
+ PerfIntervalCount chanIntervalRecvdBlks;
+ PerfIntervalCount chanIntervalXmitBlks;
+ PerfIntervalCount chanIntervalCorrectedBlks;
+ PerfIntervalCount chanIntervalUncorrectBlks;
+ int intervalValidData;
+ u8 flags;
+} adslAtucChanIntvlInfo;
+
+
+//ioctl(int fd, GET_ADSL_ATUR_CHAN_INTVL_INFO, void *struct_adslAturChanIntvlInfo)
+
+typedef struct adslAturChanIntvlInfo {
+ int ifIndex;
+ int IntervalNumber;
+ PerfIntervalCount chanIntervalRecvdBlks;
+ PerfIntervalCount chanIntervalXmitBlks;
+ PerfIntervalCount chanIntervalCorrectedBlks;
+ PerfIntervalCount chanIntervalUncorrectBlks;
+ int intervalValidData;
+ u8 flags;
+} adslAturChanIntvlInfo;
+
+
+//ioctl(int fd, GET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry)
+//ioctl(int fd, SET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry)
+
+typedef struct adslLineAlarmConfProfileEntry
+ {
+ unsigned char adslLineAlarmConfProfileName[32];
+ int adslAtucThresh15MinLofs;
+ int adslAtucThresh15MinLoss;
+ int adslAtucThresh15MinESs;
+ u32 adslAtucThreshFastRateUp;
+ u32 adslAtucThreshInterleaveRateUp;
+ u32 adslAtucThreshFastRateDown;
+ u32 adslAtucThreshInterleaveRateDown;
+ int adslAtucInitFailureTrapEnable;
+ int adslAturThresh15MinLofs;
+ int adslAturThresh15MinLoss;
+ int adslAturThresh15MinLprs;
+ int adslAturThresh15MinESs;
+ u32 adslAturThreshFastRateUp;
+ u32 adslAturThreshInterleaveRateUp;
+ u32 adslAturThreshFastRateDown;
+ u32 adslAturThreshInterleaveRateDown;
+ int adslLineAlarmConfProfileRowStatus;
+ u32 flags;
+} adslLineAlarmConfProfileEntry;
+
+#ifdef IFXMIPS_MEI_MIB_RFC3440
+typedef struct adslLineAlarmConfProfileExtEntry
+ {
+ u8 adslLineAlarmConfProfileExtName[32];
+ u32 adslAtucThreshold15MinFailedFastR;
+ u32 adslAtucThreshold15MinSesL;
+ u32 adslAtucThreshold15MinUasL;
+ u32 adslAturThreshold15MinSesL;
+ u32 adslAturThreshold15MinUasL;
+ u32 flags;
+} adslLineAlarmConfProfileExtEntry;
+#endif
+//TRAPS
+
+/* The following Data Sturctures are added to support the WEB related parameters for ADSL Statistics */
+typedef struct adslLineStatus
+ {
+ int adslModemStatus;
+ u32 adslModeSelected;
+ int adslAtucThresh15MinESs;
+ int adslTrellisCodeEnable;
+ int adslLatency;
+ u8 flags;
+ } adslLineStatusInfo;
+
+typedef struct adslLineRate
+ {
+ u32 adslDataRateds;
+ u32 adslDataRateus;
+ u32 adslATTNDRds;
+ u32 adslATTNDRus;
+ u8 flags;
+ } adslLineRateInfo;
+
+typedef struct adslLineInfo
+ {
+ u32 adslInterleaveDepthds;
+ u32 adslInterleaveDepthus;
+ u32 adslLATNds;
+ u32 adslLATNus;
+ u32 adslSATNds;
+ u32 adslSATNus;
+ int adslSNRMds;
+ int adslSNRMus;
+ int adslACATPds;
+ int adslACATPus;
+ u32 flags;
+ } adslLineInfo;
+
+typedef struct adslNearEndPerfStats
+ {
+ u32 adslSuperFrames;
+ u32 adslneLOS;
+ u32 adslneLOF;
+ u32 adslneLPR;
+ u32 adslneNCD;
+ u32 adslneLCD;
+ u32 adslneCRC;
+ u32 adslneRSCorr;
+ u32 adslneFECS;
+ u32 adslneES;
+ u32 adslneSES;
+ u32 adslneLOSS;
+ u32 adslneUAS;
+ u32 adslneHECErrors;
+ u32 flags;
+ } adslNearEndPerfStats;
+
+typedef struct adslFarEndPerfStats
+ {
+ u32 adslfeLOS;
+ u32 adslfeLOF;
+ u32 adslfeLPR;
+ u32 adslfeNCD;
+ u32 adslfeLCD;
+ u32 adslfeCRC;
+ u32 adslfeRSCorr;
+ u32 adslfeFECS;
+ u32 adslfeES;
+ u32 adslfeSES;
+ u32 adslfeLOSS;
+ u32 adslfeUAS;
+ u32 adslfeHECErrors;
+ u32 flags;
+ } adslFarEndPerfStats;
+
+/* The number of tones (and hence indexes) is dependent on the ADSL mode - G.992.1, G.992.2, G.992.3, * G.992.4 and G.992.5 */
+typedef struct adslATURSubcarrierInfo {
+ int ifindex;
+ u16 HLINSCds;
+ u16 HLINpsds[1024];/* Even index = real part; Odd Index
+ = imaginary part for each tone */
+ u16 HLOGMTds;
+ u16 HLOGpsds[512];
+ u16 QLNMTds;
+ u16 QLNpsds[512];
+ u16 SNRMTds;
+ u16 SNRpsds[512];
+ u16 BITpsds[512];
+ s16 GAINpsds[512]; /* Signed value in 0.1dB units. i.e dB * 10.
+ Needs to be converted into linear scale*/
+ u16 flags;
+}adslATURSubcarrierInfo;
+
+typedef struct adslATUCSubcarrierInfo {
+ int ifindex;
+ u16 HLINSCus;
+ u16 HLINpsus[128];/* Even index = real part; Odd Index
+ = imaginary part for each tone */
+ u16 HLOGMTus;
+ u16 HLOGpsus[64];
+ u16 QLNMTus;
+ u16 QLNpsus[64];
+ u16 SNRMTus;
+ u16 SNRpsus[64];
+ u16 BITpsus[64];
+ s16 GAINpsus[64]; /* Signed value in 0.1dB units. i.e dB * 10.
+ Needs to be converted into linear scale*/
+ u16 flags;
+}adslATUCSubcarrierInfo;
+
+#ifndef u_int16
+#define u_int16 u16
+#endif
+
+typedef struct adslInitStats {
+ u_int16 FullInitializationCount;
+ u_int16 FailedFullInitializationCount;
+ u_int16 LINIT_Errors;
+ u_int16 Init_Timeouts;
+}adslInitStats;
+
+typedef struct adslPowerSpectralDensity {
+ int ACTPSDds;
+ int ACTPSDus;
+}adslPowerSpectralDensity;
+
+//ioctl(int fd, ADSL_ATUR_TRAPS, void *uint16_flags)
+typedef union structpts {
+ adslLineTableEntry * adslLineTableEntry_pt;
+ adslAtucPhysEntry * adslAtucPhysEntry_pt;
+ adslAturPhysEntry * adslAturPhysEntry_pt;
+ adslAtucChanInfo * adslAtucChanInfo_pt;
+ adslAturChanInfo * adslAturChanInfo_pt;
+ atucPerfDataEntry * atucPerfDataEntry_pt;
+ aturPerfDataEntry * aturPerfDataEntry_pt;
+ adslAtucIntvlInfo * adslAtucIntvlInfo_pt;
+ adslAturIntvlInfo * adslAturIntvlInfo_pt;
+ atucChannelPerfDataEntry * atucChannelPerfDataEntry_pt;
+ aturChannelPerfDataEntry * aturChannelPerfDataEntry_pt;
+ adslAtucChanIntvlInfo * adslAtucChanIntvlInfo_pt;
+ adslAturChanIntvlInfo * adslAturChanIntvlInfo_pt;
+ adslLineAlarmConfProfileEntry * adslLineAlarmConfProfileEntry_pt;
+ // RFC 3440
+
+ #ifdef IFXMIPS_MEI_MIB_RFC3440
+ adslLineExtTableEntry * adslLineExtTableEntry_pt;
+ atucPerfDataExtEntry * atucPerfDataExtEntry_pt;
+ adslAtucInvtlExtInfo * adslAtucInvtlExtInfo_pt;
+ aturPerfDataExtEntry * aturPerfDataExtEntry_pt;
+ adslAturInvtlExtInfo * adslAturInvtlExtInfo_pt;
+ adslLineAlarmConfProfileExtEntry * adslLineAlarmConfProfileExtEntry_pt;
+ #endif
+ adslLineStatusInfo * adslLineStatusInfo_pt;
+ adslLineRateInfo * adslLineRateInfo_pt;
+ adslLineInfo * adslLineInfo_pt;
+ adslNearEndPerfStats * adslNearEndPerfStats_pt;
+ adslFarEndPerfStats * adslFarEndPerfStats_pt;
+ adslATUCSubcarrierInfo * adslATUCSubcarrierInfo_pt;
+ adslATURSubcarrierInfo * adslATURSubcarrierInfo_pt;
+ adslPowerSpectralDensity * adslPowerSpectralDensity_pt;
+}structpts;
+
+#endif /* ] __IFXMIPS_MEI_APP_IOCTL_H */
diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_bsp.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_bsp.h
new file mode 100644
index 0000000000..c34662013c
--- /dev/null
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_bsp.h
@@ -0,0 +1,308 @@
+/******************************************************************************
+**
+** FILE NAME : ifxmips_mei_bsp.h
+** PROJECT : Danube
+** MODULES : MEI
+**
+** DATE : 1 Jan 2006
+** AUTHOR : TC Chen
+** DESCRIPTION : MEI Driver
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Version $Date $Author $Comment
+*******************************************************************************/
+#ifndef _IFXMIPS_MEI_BSP_H_
+#define _IFXMIPS_MEI_BSP_H_
+
+/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
+#define MEI_DATA_XFR_OFFSET (0x0000)
+#define MEI_VERSION_OFFSET (0x0004)
+#define MEI_ARC_GP_STAT_OFFSET (0x0008)
+#define MEI_DATA_XFR_STAT_OFFSET (0x000C)
+#define MEI_XFR_ADDR_OFFSET (0x0010)
+#define MEI_MAX_WAIT_OFFSET (0x0014)
+#define MEI_TO_ARC_INT_OFFSET (0x0018)
+#define ARC_TO_MEI_INT_OFFSET (0x001C)
+#define ARC_TO_MEI_INT_MASK_OFFSET (0x0020)
+#define MEI_DEBUG_WAD_OFFSET (0x0024)
+#define MEI_DEBUG_RAD_OFFSET (0x0028)
+#define MEI_DEBUG_DATA_OFFSET (0x002C)
+#define MEI_DEBUG_DEC_OFFSET (0x0030)
+#define MEI_CONFIG_OFFSET (0x0034)
+#define MEI_RST_CONTROL_OFFSET (0x0038)
+#define MEI_DBG_MASTER_OFFSET (0x003C)
+#define MEI_CLK_CONTROL_OFFSET (0x0040)
+#define MEI_BIST_CONTROL_OFFSET (0x0044)
+#define MEI_BIST_STAT_OFFSET (0x0048)
+#define MEI_XDATA_BASE_SH_OFFSET (0x004c)
+#define MEI_XDATA_BASE_OFFSET (0x0050)
+#define MEI_XMEM_BAR_BASE_OFFSET (0x0054)
+#define MEI_XMEM_BAR0_OFFSET (0x0054)
+#define MEI_XMEM_BAR1_OFFSET (0x0058)
+#define MEI_XMEM_BAR2_OFFSET (0x005C)
+#define MEI_XMEM_BAR3_OFFSET (0x0060)
+#define MEI_XMEM_BAR4_OFFSET (0x0064)
+#define MEI_XMEM_BAR5_OFFSET (0x0068)
+#define MEI_XMEM_BAR6_OFFSET (0x006C))
+#define MEI_XMEM_BAR7_OFFSET (0x0070)
+#define MEI_XMEM_BAR8_OFFSET (0x0074)
+#define MEI_XMEM_BAR9_OFFSET (0x0078)
+#define MEI_XMEM_BAR10_OFFSET (0x007C)
+#define MEI_XMEM_BAR11_OFFSET (0x0080)
+#define MEI_XMEM_BAR12_OFFSET (0x0084)
+#define MEI_XMEM_BAR13_OFFSET (0x0088)
+#define MEI_XMEM_BAR14_OFFSET (0x008C)
+#define MEI_XMEM_BAR15_OFFSET (0x0090)
+#define MEI_XMEM_BAR16_OFFSET (0x0094)
+
+#define WHILE_DELAY 20000
+/*
+** Define where in ME Processor's memory map the Stratify chip lives
+*/
+
+#define MAXSWAPSIZE 8 * 1024 //8k *(32bits)
+
+// Mailboxes
+#define MSG_LENGTH 16 // x16 bits
+#define YES_REPLY 1
+#define NO_REPLY 0
+
+#define CMV_TIMEOUT 1000 //jiffies
+
+// Block size per BAR
+#define SDRAM_SEGMENT_SIZE (64*1024)
+// Number of Bar registers
+#define MAX_BAR_REGISTERS (17)
+
+#define XDATA_REGISTER (15)
+
+#define IFXMIPS_MEI_IOCTL_CMV_WINHOST IFX_ADSL_IOC_CMV_WINHOST
+
+#define IFXMIPS_MEI_IOCTL_CMV_READ IFX_ADSL_IOC_CMV_READ
+#define IFXMIPS_MEI_IOCTL_CMV_WRITE IFX_ADSL_IOC_CMV_WRITE
+
+#define IFXMIPS_MEI_IOCTL_GET_BASE_ADDRESS IFX_ADSL_IOC_GET_BASE_ADDRESS
+
+// ARC register addresss
+#define ARC_STATUS 0x0
+#define ARC_LP_START 0x2
+#define ARC_LP_END 0x3
+#define ARC_DEBUG 0x5
+#define ARC_INT_MASK 0x10A
+
+#define IRAM0_BASE (0x00000)
+#define IRAM1_BASE (0x04000)
+#define BRAM_BASE (0x0A000)
+
+#define ADSL_BASE (0x20000)
+#define CRI_BASE (ADSL_BASE + 0x11F00)
+#define CRI_CCR0 (CRI_BASE + 0x00)
+#define CRI_RST (CRI_BASE + 0x04*4)
+#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
+
+//
+#define IRAM0_ADDR_BIT_MASK 0xFFF
+#define IRAM1_ADDR_BIT_MASK 0xFFF
+#define BRAM_ADDR_BIT_MASK 0xFFF
+#define RX_DILV_ADDR_BIT_MASK 0x1FFF
+
+/*** Bit definitions ***/
+
+#define FALSE 0
+#define TRUE 1
+#define BIT0 1<<0
+#define BIT1 1<<1
+#define BIT2 1<<2
+#define BIT3 1<<3
+#define BIT4 1<<4
+#define BIT5 1<<5
+#define BIT6 1<<6
+#define BIT7 1<<7
+#define BIT8 1<<8
+#define BIT9 1<<9
+#define BIT10 1<<10
+#define BIT11 1<<11
+#define BIT12 1<<12
+#define BIT13 1<<13
+#define BIT14 1<<14
+#define BIT15 1<<15
+#define BIT16 1<<16
+#define BIT17 1<<17
+#define BIT18 1<<18
+#define BIT19 1<<19
+#define BIT20 1<<20
+#define BIT21 1<<21
+#define BIT22 1<<22
+#define BIT23 1<<23
+#define BIT24 1<<24
+#define BIT25 1<<25
+#define BIT26 1<<26
+#define BIT27 1<<27
+#define BIT28 1<<28
+#define BIT29 1<<29
+#define BIT30 1<<30
+#define BIT31 1<<31
+
+// CRI_CCR0 Register definitions
+#define CLK_2M_MODE_ENABLE BIT6
+#define ACL_CLK_MODE_ENABLE BIT4
+#define FDF_CLK_MODE_ENABLE BIT2
+#define STM_CLK_MODE_ENABLE BIT0
+
+// CRI_RST Register definitions
+#define FDF_SRST BIT3
+#define MTE_SRST BIT2
+#define FCI_SRST BIT1
+#define AAI_SRST BIT0
+
+// MEI_TO_ARC_INTERRUPT Register definitions
+#define MEI_TO_ARC_INT1 BIT3
+#define MEI_TO_ARC_INT0 BIT2
+#define MEI_TO_ARC_CS_DONE BIT1 //need to check
+#define MEI_TO_ARC_MSGAV BIT0
+
+// ARC_TO_MEI_INTERRUPT Register definitions
+#define ARC_TO_MEI_INT1 BIT8
+#define ARC_TO_MEI_INT0 BIT7
+#define ARC_TO_MEI_CS_REQ BIT6
+#define ARC_TO_MEI_DBG_DONE BIT5
+#define ARC_TO_MEI_MSGACK BIT4
+#define ARC_TO_MEI_NO_ACCESS BIT3
+#define ARC_TO_MEI_CHECK_AAITX BIT2
+#define ARC_TO_MEI_CHECK_AAIRX BIT1
+#define ARC_TO_MEI_MSGAV BIT0
+
+// ARC_TO_MEI_INTERRUPT_MASK Register definitions
+#define GP_INT1_EN BIT8
+#define GP_INT0_EN BIT7
+#define CS_REQ_EN BIT6
+#define DBG_DONE_EN BIT5
+#define MSGACK_EN BIT4
+#define NO_ACC_EN BIT3
+#define AAITX_EN BIT2
+#define AAIRX_EN BIT1
+#define MSGAV_EN BIT0
+
+#define MEI_SOFT_RESET BIT0
+
+#define HOST_MSTR BIT0
+
+#define JTAG_MASTER_MODE 0x0
+#define MEI_MASTER_MODE HOST_MSTR
+
+// MEI_DEBUG_DECODE Register definitions
+#define MEI_DEBUG_DEC_MASK (0x3)
+#define MEI_DEBUG_DEC_AUX_MASK (0x0)
+#define MEI_DEBUG_DEC_DMP1_MASK (0x1)
+#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
+#define MEI_DEBUG_DEC_CORE_MASK (0x3)
+
+#define AUX_STATUS (0x0)
+// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
+// page swap requests.
+#define MEI_TO_ARC_MAILBOX (0xDFD0)
+#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
+
+#define ARC_TO_MEI_MAILBOX (0xDFA0)
+#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
+
+// Codeswap request messages are indicated by setting BIT31
+#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
+
+// Clear Eoc messages received are indicated by setting BIT17
+#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
+
+/*
+** Swap page header
+*/
+// Page must be loaded at boot time if size field has BIT31 set
+#define BOOT_FLAG (BIT31)
+#define BOOT_FLAG_MASK ~BOOT_FLAG
+
+#define FREE_RELOAD 1
+#define FREE_SHOWTIME 2
+#define FREE_ALL 3
+
+// marcos
+#define IFXMIPS_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data);} while (0)
+#define IFXMIPS_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
+#define SET_BIT(reg, mask) reg |= (mask)
+#define CLEAR_BIT(reg, mask) reg &= (~mask)
+#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
+#define SET_BITS(reg, mask) SET_BIT(reg, mask)
+#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
+
+#define ALIGN_SIZE ( 1L<<10 ) //1K size align
+#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
+
+// swap marco
+#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
+#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
+
+// Swap page header describes size in 32-bit words, load location, and image offset
+// for program and/or data segments
+typedef struct _arc_swp_page_hdr {
+ u32 p_offset; //Offset bytes of progseg from beginning of image
+ u32 p_dest; //Destination addr of progseg on processor
+ u32 p_size; //Size in 32-bitwords of program segment
+ u32 d_offset; //Offset bytes of dataseg from beginning of image
+ u32 d_dest; //Destination addr of dataseg on processor
+ u32 d_size; //Size in 32-bitwords of data segment
+} ARC_SWP_PAGE_HDR;
+
+/*
+** Swap image header
+*/
+#define GET_PROG 0 // Flag used for program mem segment
+#define GET_DATA 1 // Flag used for data mem segment
+
+// Image header contains size of image, checksum for image, and count of
+// page headers. Following that are 'count' page headers followed by
+// the code and/or data segments to be loaded
+typedef struct _arc_img_hdr {
+ u32 size; // Size of binary image in bytes
+ u32 checksum; // Checksum for image
+ u32 count; // Count of swp pages in image
+ ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
+} ARC_IMG_HDR;
+
+typedef struct smmu_mem_info {
+ int type;
+ unsigned long nCopy;
+ unsigned long size;
+ unsigned char *address;
+ unsigned char *org_address;
+} smmu_mem_info_t;
+
+typedef struct ifxmips_mei_device_private {
+ int modem_ready;
+ int arcmsgav;
+ int cmv_reply;
+ int cmv_waiting;
+ // Mei to ARC CMV count, reply count, ARC Indicator count
+ int indicator_count;
+ int cmv_count;
+ int reply_count;
+ unsigned long image_size;
+ int nBar;
+ u16 Recent_indicator[MSG_LENGTH];
+
+ u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
+
+ smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
+ ARC_IMG_HDR *img_hdr;
+ // to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
+ wait_queue_head_t wait_queue_arcmsgav;
+ wait_queue_head_t wait_queue_modemready;
+ MEI_mutex_t mei_cmv_sema;
+} ifxmips_mei_device_private_t;
+
+#endif //_IFXMIPS_MEI_BSP_H_
diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_ioctl.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_ioctl.h
new file mode 100644
index 0000000000..d11f04ea97
--- /dev/null
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_ioctl.h
@@ -0,0 +1,734 @@
+/******************************************************************************
+**
+** FILE NAME : ifxmips_mei_ioctl.h
+** PROJECT : Danube
+** MODULES : MEI
+**
+** DATE : 1 Jan 2006
+** AUTHOR : TC Chen
+** DESCRIPTION : MEI Driver
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Version $Date $Author $Comment
+*******************************************************************************/
+#ifndef _IFXMIPS_MEI_IOCTL_H
+#define _IFXMIPS_MEI_IOCTL_H
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////
+#define PCM_BUFF_SIZE 1024 //bytes
+// interrupt numbers
+
+#if !(defined(_IFXMIPS_ADSL_APP) || defined (_AMAZON_ADSL_APP))
+
+// Number of intervals
+#define INTERVAL_NUM 192 //two days
+typedef struct ifxmips_mei_mib {
+ struct list_head list;
+ struct timeval start_time; //start of current interval
+
+ int AtucPerfLof;
+ int AtucPerfLos;
+ int AtucPerfEs;
+ int AtucPerfInit;
+
+ int AturPerfLof;
+ int AturPerfLos;
+ int AturPerfLpr;
+ int AturPerfEs;
+
+ int AturChanPerfRxBlk;
+ int AturChanPerfTxBlk;
+ int AturChanPerfCorrBlk;
+ int AturChanPerfUncorrBlk;
+
+ //RFC-3440
+ int AtucPerfStatFastR;
+ int AtucPerfStatFailedFastR;
+ int AtucPerfStatSesL;
+ int AtucPerfStatUasL;
+ int AturPerfStatSesL;
+ int AturPerfStatUasL;
+} ifxmips_mei_mib;
+
+typedef struct adslChanPrevTxRate {
+ u32 adslAtucChanPrevTxRate;
+ u32 adslAturChanPrevTxRate;
+} adslChanPrevTxRate;
+
+typedef struct adslPhysCurrStatus {
+ u32 adslAtucCurrStatus;
+ u32 adslAturCurrStatus;
+} adslPhysCurrStatus;
+
+typedef struct ChanType {
+ int interleave;
+ int fast;
+ int bearchannel0;
+ int bearchannel1;
+} ChanType;
+
+typedef struct mib_previous_read {
+ u16 ATUC_PERF_ESS;
+ u16 ATUR_PERF_ESS;
+ u32 ATUR_CHAN_RECV_BLK;
+ u16 ATUR_CHAN_CORR_BLK_INTL;
+ u16 ATUR_CHAN_CORR_BLK_FAST;
+ u16 ATUR_CHAN_UNCORR_BLK_INTL;
+ u16 ATUR_CHAN_UNCORR_BLK_FAST;
+ u16 ATUC_PERF_STAT_FASTR;
+ u16 ATUC_PERF_STAT_FAILED_FASTR;
+ u16 ATUC_PERF_STAT_SESL;
+ u16 ATUC_PERF_STAT_UASL;
+ u16 ATUR_PERF_STAT_SESL;
+} mib_previous_read;
+
+typedef struct mib_flags_pretime {
+ struct timeval ATUC_PERF_LOSS_PTIME;
+ struct timeval ATUC_PERF_LOFS_PTIME;
+ struct timeval ATUR_PERF_LOSS_PTIME;
+ struct timeval ATUR_PERF_LOFS_PTIME;
+ struct timeval ATUR_PERF_LPR_PTIME;
+} mib_flags_pretime;
+
+ // cmv message structures
+#define MP_PAYLOAD_SIZE 12
+typedef struct mpmessage {
+ u16 iFunction;
+ u16 iGroup;
+ u16 iAddress;
+ u16 iIndex;
+ u16 iPayload[MP_PAYLOAD_SIZE];
+} MPMessage;
+#endif
+
+typedef struct meireg {
+ u32 iAddress;
+ u32 iData;
+} meireg;
+
+#define MEIDEBUG_BUFFER_SIZES 50
+typedef struct meidebug {
+ u32 iAddress;
+ u32 iCount;
+ u32 buffer[MEIDEBUG_BUFFER_SIZES];
+} meidebug;
+
+//==============================================================================
+// Group definitions
+//==============================================================================
+#define OPTN 5
+#define CNFG 8
+#define CNTL 1
+#define STAT 2
+#define RATE 6
+#define PLAM 7
+#define INFO 3
+#define TEST 4
+//==============================================================================
+// Opcode definitions
+//==============================================================================
+#define H2D_CMV_READ 0x00
+#define H2D_CMV_WRITE 0x04
+#define H2D_CMV_INDICATE_REPLY 0x10
+#define H2D_ERROR_OPCODE_UNKNOWN 0x20
+#define H2D_ERROR_CMV_UNKNOWN 0x30
+
+#define D2H_CMV_READ_REPLY 0x01
+#define D2H_CMV_WRITE_REPLY 0x05
+#define D2H_CMV_INDICATE 0x11
+#define D2H_ERROR_OPCODE_UNKNOWN 0x21
+#define D2H_ERROR_CMV_UNKNOWN 0x31
+#define D2H_ERROR_CMV_READ_NOT_AVAILABLE 0x41
+#define D2H_ERROR_CMV_WRITE_ONLY 0x51
+#define D2H_ERROR_CMV_READ_ONLY 0x61
+
+#define H2D_DEBUG_READ_DM 0x02
+#define H2D_DEBUG_READ_PM 0x06
+#define H2D_DEBUG_WRITE_DM 0x0a
+#define H2D_DEBUG_WRITE_PM 0x0e
+
+#define D2H_DEBUG_READ_DM_REPLY 0x03
+#define D2H_DEBUG_READ_FM_REPLY 0x07
+#define D2H_DEBUG_WRITE_DM_REPLY 0x0b
+#define D2H_DEBUG_WRITE_FM_REPLY 0x0f
+#define D2H_ERROR_ADDR_UNKNOWN 0x33
+
+#define D2H_AUTONOMOUS_MODEM_READY_MSG 0xf1
+//==============================================================================
+// INFO register address field definitions
+//==============================================================================
+
+#define INFO_TxState 0
+#define INFO_RxState 1
+#define INFO_TxNextState 2
+#define INFO_RxNextState 3
+#define INFO_TxStateJumpFrom 4
+#define INFO_RxStateJumpFrom 5
+
+#define INFO_ReverbSnrBuf 8
+#define INFO_ReverbEchoSnrBuf 9
+#define INFO_MedleySnrBuf 10
+#define INFO_RxShowtimeSnrBuf 11
+#define INFO_DECdelay 12
+#define INFO_DECExponent 13
+#define INFO_DECTaps 14
+#define INFO_AECdelay 15
+#define INFO_AECExponent 16
+#define INFO_AECTaps 17
+#define INFO_TDQExponent 18
+#define INFO_TDQTaps 19
+#define INFO_FDQExponent 20
+#define INFO_FDQTaps 21
+#define INFO_USBat 22
+#define INFO_DSBat 23
+#define INFO_USFineGains 24
+#define INFO_DSFineGains 25
+#define INFO_BitloadFirstChannel 26
+#define INFO_BitloadLastChannel 27
+#define INFO_PollEOCData 28 // CO specific
+#define INFO_CSNRMargin 29 // CO specific
+#define INFO_RCMsgs1 30
+#define INFO_RMsgs1 31
+#define INFO_RMsgRA 32
+#define INFO_RCMsgRA 33
+#define INFO_RMsg2 34
+#define INFO_RCMsg2 35
+#define INFO_BitLoadOK 36
+#define INFO_RCRates1 37
+#define INFO_RRates1Tab 38
+#define INFO_RMsgs1Tab 39
+#define INFO_RMsgRATab 40
+#define INFO_RRatesRA 41
+#define INFO_RCRatesRA 42
+#define INFO_RRates2 43
+#define INFO_RCRates2 44
+#define INFO_PackedRMsg2 45
+#define INFO_RxBitSwapFlag 46
+#define INFO_TxBitSwapFlag 47
+#define INFO_ShowtimeSNRUpdateCount 48
+#define INFO_ShowtimeFDQUpdateCount 49
+#define INFO_ShowtimeDECUpdateCount 50
+#define INFO_CopyRxBuffer 51
+#define INFO_RxToneBuf 52
+#define INFO_TxToneBuf 53
+#define INFO_Version 54
+#define INFO_TimeStamp 55
+#define INFO_feVendorID 56
+#define INFO_feSerialNum 57
+#define INFO_feVersionNum 58
+#define INFO_BulkMemory 59 //Points to start of bulk memory
+#define INFO_neVendorID 60
+#define INFO_neVersionNum 61
+#define INFO_neSerialNum 62
+
+//==============================================================================
+// RATE register address field definitions
+//==============================================================================
+
+#define RATE_UsRate 0
+#define RATE_DsRate 1
+
+//==============================================================================
+// PLAM (Physical Layer Management) register address field definitions
+// (See G997.1 for reference)
+//==============================================================================
+
+ // ///
+ // Failure Flags ///
+ // ///
+
+#define PLAM_NearEndFailureFlags 0
+#define PLAM_FarEndFailureFlags 1
+
+ // ///
+ // Near End Failure Flags Bit Definitions ///
+ // ///
+
+// ADSL Failures ///
+#define PLAM_LOS_FailureBit 0x0001
+#define PLAM_LOF_FailureBit 0x0002
+#define PLAM_LPR_FailureBit 0x0004
+#define PLAM_RFI_FailureBit 0x0008
+
+// ATM Failures ///
+#define PLAM_NCD_LP0_FailureBit 0x0010
+#define PLAM_NCD_LP1_FailureBit 0x0020
+#define PLAM_LCD_LP0_FailureBit 0x0040
+#define PLAM_LCD_LP1_FailureBit 0x0080
+
+#define PLAM_NCD_BC0_FailureBit 0x0100
+#define PLAM_NCD_BC1_FailureBit 0x0200
+#define PLAM_LCD_BC0_FailureBit 0x0400
+#define PLAM_LCD_BC1_FailureBit 0x0800
+ // ///
+ // Performance Counts ///
+ // ///
+
+#define PLAM_NearEndCrcCnt 2
+#define PLAM_CorrectedRSErrors 3
+
+#define PLAM_NearEndECSCnt 6
+#define PLAM_NearEndESCnt 7
+#define PLAM_NearEndSESCnt 8
+#define PLAM_NearEndLOSSCnt 9
+#define PLAM_NearEndUASLCnt 10
+
+#define PLAM_NearEndHECErrCnt 11
+
+#define PLAM_NearEndHECTotCnt 16
+#define PLAM_NearEndCellTotCnt 18
+#define PLAM_NearEndSfCntLSW 20
+#define PLAM_NearEndSfCntMSW 21
+
+#define PLAM_FarEndFebeCnt 24
+
+#define PLAM_FarEndFecCnt 28
+
+#define PLAM_FarEndFECSCnt 32
+#define PLAM_FarEndESCnt 33
+#define PLAM_FarEndSESCnt 34
+#define PLAM_FarEndLOSSCnt 35
+#define PLAM_FarEndUASLCnt 36
+
+#define PLAM_FarEndHECErrCnt 37
+
+#define PLAM_FarEndHECTotCnt 41
+
+#define PLAM_FarEndCellTotCnt 43
+
+#define PLAM_SNRMargin_0_1db 45
+
+#define PLAM_SNRMargin 46
+
+//==============================================================================
+// CNTL register address and bit field definitions
+//==============================================================================
+
+#define CNTL_ModemControl 0
+
+#define CNTL_ModemReset 0x0
+#define CNTL_ModemStart 0x2
+
+//==============================================================================
+// STAT register address and bit field definitions
+//==============================================================================
+
+#define STAT_MacroState 0
+#define STAT_Mode 1
+#define STAT_DMTFramingMode 2
+#define STAT_SleepState 3
+#define STAT_Misc 4
+#define STAT_FailureState 5
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // STAT_OLRStatus provides status of OLR
+ //16-bit STAT_OLRStatus_DS
+ // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
+ // [3:2]: Reserved
+ // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
+ // [7:6]: Reserved
+ // [10:8]: >0=Request. 0=not. For DS, # of request transmissions/retransmissions (3 bits).
+ // [11]: 1=Receive Response, 0=not
+ // [15:12]: Reserved
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ ///
+#define STAT_OLRStatus_DS 6
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // STAT_OLRStatus provides status of OLR
+ // 16-bit STAT_OLRStatus_US CMV
+ // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
+ // [3:2]: Reserved
+ // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
+ // [7:6]: Reserved
+ // [8]: 1=Request Received. 0=not.
+ // [10:9]: Reserved
+ // [11]: 1=Response Sent, 0=not
+ // [15:12]: Reserved
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+///
+#define STAT_OLRStatus_US 7
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // STAT_PMStatus provides status of PM
+ // 16-bit STAT_PMStatus CMV
+ // [1:0] : PM Status 00=IDLE, 01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted
+ // [2] : 0=ATU_R initiated PM; 1 = ATU_C initiated PM
+ // [3]: Reserved
+ // [5:4]: PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim)
+ // [7:6]: Reserved
+ // [10:8]: >0=Request. 0=not. # of request transmissions/retransmissions (3 bits).
+ // [11]: 1=Response, 0=not
+ // [15:12]: Reserved
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ ///
+#define STAT_PMStatus 8
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError
+ // [3:0]: OLR/PM response reason code
+ // [7:4]: OLR/PM Internal error code
+ // [15:8]: OLR/PM Reserved for future
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ ///
+#define STAT_OLRError_DS 9
+#define STAT_OLRError_US 10
+#define STAT_PMError 11
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// STAT_MacroState
+// MacroState reflects the high level state of the modem
+
+#define STAT_InitState 0x0000
+#define STAT_ReadyState 0x0001
+#define STAT_FailState 0x0002
+#define STAT_IdleState 0x0003
+#define STAT_QuietState 0x0004
+#define STAT_GhsState 0x0005
+#define STAT_FullInitState 0x0006
+#define STAT_ShowTimeState 0x0007
+#define STAT_FastRetrainState 0x0008
+#define STAT_LoopDiagMode 0x0009
+#define STAT_ShortInit 0x000A // Bis short initialization ///
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// STAT_Mode
+// ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use
+// G.Hs or some other mechanism to negotiate the specific mode of operation.
+// The OPTN_modeControl CMV is used to select a set of desired modes.
+// The STAT_Mode CMV indicates which mode was actually selected.
+
+#define STAT_ConfigMode_T1413 0x0001
+#define STAT_ConfigMode_G992_2_AB 0x0002
+#define STAT_ConfigMode_G992_1_A 0x0004
+#define STAT_ConfigMode_G992_1_B 0x0008
+#define STAT_ConfigMode_G992_1_C 0x0010
+#define STAT_ConfigMode_G992_2_C 0x0020
+
+#define STAT_ConfigMode_G992_3_A 0x0100
+#define STAT_ConfigMode_G992_3_B 0x0200
+#define STAT_ConfigMode_G992_3_I 0x0400
+#define STAT_ConfigMode_G992_3_J 0x0800
+#define STAT_ConfigMode_G992_3_L 0x1000
+
+#define STAT_ConfigMode_G992_4_A 0x2000
+#define STAT_ConfigMode_G992_4_I 0x4000
+
+#define STAT_ConfigMode_G992_5 0x8000
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// STAT_DMTFramingMode
+// FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode
+// status is not applicable in BIS mode and its value is undefined
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define STAT_FramingModeMask 0x0003
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// STAT_Misc
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define STAT_OverlappedSpectrum 0x0008
+#define STAT_TCM 0x0010
+#define STAT_TDQ_at_1104 0x0020
+#define STAT_T1413_Signal_Detected 0x0040
+#define STAT_AnnexL_US_Mask1_PSD 0x1000 //indicate we actually selected G992.3 AnnexL US PSD mask1
+#define STAT_AnnexL_US_Mask2_PSD 0x2000 //indicate we actually selected G992.3 AnnexL US PSD mask2
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// STAT_FailureState
+// when the MacroSTate indicates the fail state, FailureState provides a failure code
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define E_CODE_NO_ERROR 0
+#define E_CODE_BAT_TX 1 // TX BAT table is incorrect */
+#define E_CODE_BAT_RX 2 // RX BAT table is incorrect */
+#define E_CODE_PROFILE 3 // profile is not selected in fast retrain */
+#define E_CODE_TX_AOC_FIFO_OVERFLOW 4
+#define E_CODE_TRUNCATE_FR 5 //Fast Retrain truncated due to no stored profiles*/
+#define E_CODE_BITLOAD 6 // bit loading fails */
+#define E_CODE_ST_ERROR 7 // showtime CRC error */
+#define E_CODE_RESERVED 8 // using parameters reserved by the ITU-T */
+#define E_CODE_C_TONES 9 // detected C_TONES */
+#define E_CODE_CODESWAP_ERR 10 // codeswap not finished in time */
+#define E_CODE_FIFO_OVERFLOW 11 // we have run out of fifo space */
+#define E_CODE_C_BG_DECODE_ERR 12 // error in decoding C-BG message */
+#define E_CODE_C_RATES2_DECODE_ERR 13 // error in decoding C-MSGS2 and C-RATES2 */
+#define E_CODE_RCMedleyRx_C_SEGUE2_Failure 14 // Timeout after RCMedleyRx waiting for C_SEGUE2 */
+#define E_CODE_RReverbRATx_C_SEGUE2_Failure 15 // Timeout after RReverbRATx waiting for C_SEGUE2 */
+#define E_CODE_RReverb3Tx_C_SEGUE1_Failure 16 // Timeout after RReverb3Tx waiting for C_SEGUE1 */
+#define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR 17 // Received CRC not equal to computed CRC */
+#define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR 18 // Received CRC not equal to computed CRC */
+#define E_CODE_RReverb5Tx_C_SEGUE2_Failure 19 // Timeout after RReverb5Tx waiting for C_SEGUE2 */
+#define E_CODE_RReverb6Tx_C_SEGUE3_Failure 20 // Timeout after RReverb6Tx waiting for C_SEGUE3 */
+#define E_CODE_RSegue5Tx_C_SEGUE3_Failure 21 // Timeout after RSegue5Tx waiting for C_SEGUE3 */
+#define E_CODE_RCReverb5Rx_C_SEGUE_Failure 22 // Timeout after RCReverb5Rx waiting for C_SEGUE */
+#define E_CODE_RCReverbRARx_C_SEGUE2_Failure 23 // Timeout after RCReverbRARx waiting for C_SEGUE2 */
+#define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR 24 // Received CRC not equal to computed CRC */
+#define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR 25 // Received CRC not equal to computed CRC */
+#define E_CODE_RCCRC3Rx_DECOD_ERR 26 // Received CRC not equal to computed CRC */
+#define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT 27 // DEC Path Delay timeout */
+#define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT 28 // DEC Training timeout */
+#define E_CODE_RCReverb3Rx_C_SEGUE1_Failure 29 // Timeout after RCReverb3Rx waiting for C_SEGUE1 */
+#define E_CODE_RCReverb2Rx_SignalEnd_Failure 30 // Timeout waiting for the end of RCReverb2Rx signal */
+#define E_CODE_RQuiet2_SignalEnd_Failure 31 // Timeout waiting for the end of RQuiet2 signal */
+#define E_CODE_RCReverbFR1Rx_Failure 32 // Timeout waiting for the end of RCReverbFR1Rx signal */
+#define E_CODE_RCPilotFR1Rx_SignalEnd_Failure 33 // Timeout waiting for the end of RCPilotFR1Rx signal */
+#define E_CODE_RCReverbFR2Rx_C_Segue_Failure 34 // Timeout after RCReverbFR2Rx waiting for C_SEGUE */
+#define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT 35 // Timeout waiting for the end of RCReverbFR5Rx signal */
+#define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure 36 // Timeout after RCReverbFR6Rx waiting for C_SEGUE */
+#define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure 37 // Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */
+#define E_CODE_RCReverbFR8Rx_No_PROFILE 38 // Timeout since no profile was selected */
+#define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT 39 // Timeout waiting for the end of RCReverbFR8Rx signal */
+#define E_CODE_RCCRCFR1_DECOD_ERR 40 // Received CRC not equal to computed CRC */
+#define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT 41 // Timeout waiting for the end of RCRecovRx signal */
+#define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT 42 // Timeout after RSegueFR5Tx waiting for C_SEGUE2 */
+#define E_CODE_RRecovTx_SignalEnd_TIMEOUT 43 // Timeout waiting for the end of RRecovTx signal */
+#define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure 44 // Timeout after RCMedleyFRRx waiting for C_SEGUE2 */
+#define E_CODE_CONFIGURATION_PARAMETERS_ERROR 45 // one of the configuration parameters do not meet the standard */
+#define E_CODE_BAD_MEM_ACCESS 46
+#define E_CODE_BAD_INSTRUCTION_ACCESS 47
+#define E_CODE_TX_EOC_FIFO_OVERFLOW 48
+#define E_CODE_RX_EOC_FIFO_OVERFLOW 49
+#define E_CODE_GHS_CD_FLAG_TIME_OUT 50 // Timeout when transmitting Flag in handshake cleardown */
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//STAT_OLRStatus:
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define STAT_OLRPM_IDLE 0x0000
+#define STAT_OLRPM_IN_PROGRESS 0x0001
+#define STAT_OLRPM_COMPLETE 0x0002
+#define STAT_OLRPM_ABORTED 0x0003
+#define STAT_OLRPM_RESPONSE 0x0800
+
+#define STAT_OLR_BITSWAP 0x0010
+#define STAT_OLR_DRR 0x0020
+#define STAT_OLR_SRA 0x0030
+
+//STAT_PMStatus_US:
+#define STAT_PM_CO_REQ 0x0004
+#define STAT_PM_SIMPLE_REQ 0x0010
+#define STAT_PM_L2_REQ 0x0020
+#define STAT_PM_L2_TRIM_REQ 0x0030
+
+// STAT_OLRError_DS, STAT_OLRError_US
+//4 bit response reason code:
+#define RESP_BUSY 0x01
+#define RESP_INVALID_PARAMETERS 0x02
+#define RESP_NOT_ENABLED 0x03
+#define RESP_NOT_SUPPORTED 0x04
+
+//4 bit internal error code (common for OLR and PM)
+#define REQ_INVALID_BiGi 0x10
+#define REQ_INVALID_Lp 0x20
+#define REQ_INVALID_Bpn 0x30
+#define REQ_INVALID_FRAMING_CONSTRAINT 0x40
+#define REQ_NOT_IN_L0_STATE 0x50
+#define REQ_NOT_IN_L2_STATE 0x60
+#define REQ_INVALID_PCB 0x70
+#define REQ_VIOLATES_MARGIN 0x80
+
+//STAT_PMError
+//4 bit response reason code:
+#define RESP_STATE_NOT_DESIRED 0x03
+#define RESP_INFEASIBLE_PARAMETERS 0x04
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// OPTN register address and bit field definitions
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define OPTN_ModeControl 0
+#define OPTN_DMTLnkCtl 1
+// Reserved 2
+#define OPTN_GhsControl 3
+// Reserved 4
+#define OPTN_PwrManControl 5
+#define OPTN_AnnexControl 6
+#define OPTN_ModeControl1 7
+// Reserved 8
+#define OPTN_StateMachineCtrl 9
+// Reserved 10
+// Reserved 11
+#define OPTN_BisLinkControl 12
+#define OPTN_ATMAddrConfig 13
+#define OPTN_ATMNumCellConfig 14
+
+// Mode control defines the allowable operating modes of an ADSL link. In general, a modem may ///
+// use G.Hs or some other mechanism to negotiate the specific mode of operation. ///
+// The OPTN_ModeControl CMV is used to select a set of desired modes ///
+// The STAT_ModeControl CMV indicates which mode was actually selected ///
+
+// OPTN_ModeControl
+#define OPTN_ConfigMode_T1413 0x0001
+#define OPTN_ConfigMode_G992_2_AB 0x0002
+#define OPTN_ConfigMode_G992_1_A 0x0004
+#define OPTN_ConfigMode_G992_1_B 0x0008
+#define OPTN_ConfigMode_G992_1_C 0x0010
+#define OPTN_ConfigMode_G992_2_C 0x0020
+
+#define OPTN_ConfigMode_G992_3_A 0x0100
+#define OPTN_ConfigMode_G992_3_B 0x0200
+#define OPTN_ConfigMode_G992_3_I 0x0400
+#define OPTN_ConfigMode_G992_3_J 0x0800
+#define OPTN_ConfigMode_G992_3_L 0x1000
+
+#define OPTN_ConfigMode_G992_4_A 0x2000
+#define OPTN_ConfigMode_G992_4_I 0x4000
+
+#define OPTN_ConfigMode_G992_5 0x8000
+
+// OPTN_PwrManControl
+#define OPTN_PwrManWakeUpGhs 0x1
+#define OPTN_PwrManWakeUpFR 0x2
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// OPTN_DMT Link Control
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define OPTN_DMT_DualLatency_Dis 0x200
+#define OPTN_DMT_S_Dis 0x100
+#define OPTN_DMT_FRAMINGMODE 0x1
+#define OPTN_DMT_FRAMINGMODE_MASK 0x7
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// OPTN_BIS Link Control
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define OPTN_BisLinkContrl_LineProbeDis 0x1
+#define OPTN_BisLinkContrl_DSBlackBitsEn 0x2
+#define OPTN_BisLinkContrl_DiagnosticModeEn 0x4
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// OPTN_GhsControl
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//
+// for OPTN_GhsControl, we will assign 16bit word as follows
+// bit 0~3: set the control over which start(initial) message CPE will send:
+//
+// BIT: 2 1 0
+// 0 0 1 CLR
+// 0 1 0 MR
+// 0 1 1 MS
+// 1 0 0 MP
+//
+// // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange
+// BIT: 5 4
+// 0 1 MS
+// 1 0 MR
+// 1 1 MP
+//
+// // bit 15: RT initiated G.hs sample sessions one through eight. Session one is default.
+// BIT: 15
+// 1 means session one
+//
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define OPTN_GHS_ST_GHS 0x8000
+#define OPTN_GHS_INIT_MASK 0x000F
+#define OPTN_GHS_RESP_MASK 0x00F0
+
+#define OPTN_RTInitTxMsg_CLR 0x0001
+#define OPTN_RTInitTxMsg_MR 0x0002
+#define OPTN_RTInitTxMsg_MS 0x0003
+#define OPTN_RTInitTxMsg_MP 0x0004
+
+#define OPTN_RTRespTxMsg_MS 0x0010
+#define OPTN_RTRespTxMsg_MR 0x0020
+#define OPTN_RTRespTxMsg_MP 0x0030
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// OPTN_AnnexControl
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// G.992.3 Annex A/L1/L2 US PSD Mask preferred
+
+#define OPTN_G992_3_AnnexA_PreferredModeMask 0x3000
+#define OPTN_G992_3_AnnexA_PreferredModeA 0x0000 // default AnnexA PSD mask ///
+#define OPTN_G992_3_AnnexA_PreferredModeL1 0x1000 // AnnexL wide spectrum upstream PSD mask ///
+#define OPTN_G992_3_AnnexA_PreferredModeL2 0x2000 // AnnexL narrow spectrum upstream PSD mask ///
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//OPTN_ATMAddrConfig
+// Bits 4:0 are Utopia address for BC1
+// Bits 9:5 are Utopia address for BC0
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define OPTN_UTPADDR_BC1 0x001F
+#define OPTN_UTPADDR_BC0 0x03E0
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//OPTN_ATMNumCellConfig
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define OPTN_BC1_NUM_CELL_PAGES 0x000F // Bits 0:3 ///
+#define OPTN_BC0_NUM_CELL_PAGES 0x00F0 // Bits 4:7 ///
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// CNFG register address field ///
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+///////////////////////////////////////////
+// these cmvs are used by bis handshake ///
+///////////////////////////////////////////
+
+// Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t)
+#define CNFG_TPS_TC_DS0 0
+#define CNFG_TPS_TC_DS1 1
+#define CNFG_TPS_TC_US0 2
+#define CNFG_TPS_TC_US1 3
+
+#define CNFG_HDLC_Overhead_Requirements 4
+
+// Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t)
+#define CNFG_PMS_TC_DS0 5
+#define CNFG_PMS_TC_DS1 6
+#define CNFG_PMS_TC_US0 7
+#define CNFG_PMS_TC_US1 8
+
+// CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t)
+#define CNFG_PMD_PARAMETERS 9
+
+////////////////////////////////////////////////////////////
+// these cmvs are used by bis training and showtime code ///
+////////////////////////////////////////////////////////////
+
+////////////////
+// Tx Config ///
+////////////////
+#define CNFG_tx_Cnfg_Nbc 10
+#define CNFG_tx_Cnfg_Nlp 11
+#define CNFG_tx_Cnfg_Rp 12
+#define CNFG_tx_Cnfg_Mp 13
+#define CNFG_tx_Cnfg_Lp 14
+#define CNFG_tx_Cnfg_Tp 15
+#define CNFG_tx_Cnfg_Dp 16
+#define CNFG_tx_Cnfg_Bpn 17
+#define CNFG_tx_Cnfg_FramingMode 18
+#define CNFG_tx_Cnfg_MSGLp 19
+#define CNFG_tx_Cnfg_MSGc 20
+
+////////////////
+// Rx Config ///
+////////////////
+#define CNFG_rx_Cnfg_Nbc 21
+#define CNFG_rx_Cnfg_Nlp 22
+#define CNFG_rx_Cnfg_Rp 23
+#define CNFG_rx_Cnfg_Mp 24
+#define CNFG_rx_Cnfg_Lp 25
+#define CNFG_rx_Cnfg_Tp 26
+#define CNFG_rx_Cnfg_Dp 27
+#define CNFG_rx_Cnfg_Bpn 28
+#define CNFG_rx_Cnfg_FramingMode 29
+#define CNFG_rx_Cnfg_MSGLp 30
+#define CNFG_rx_Cnfg_MSGc 31
+
+#define CNFG_tx_Cnfg_BCnToLPp 32
+#define CNFG_rx_Cnfg_BCnToLPp 33
+
+#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_linux.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_linux.h
new file mode 100644
index 0000000000..b1c12d1d01
--- /dev/null
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_linux.h
@@ -0,0 +1,111 @@
+/******************************************************************************
+**
+** FILE NAME : ifxmips_mei_linux.h
+** PROJECT : Danube
+** MODULES : MEI
+**
+** DATE : 1 Jan 2006
+** AUTHOR : TC Chen
+** DESCRIPTION : MEI Driver
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Version $Date $Author $Comment
+*******************************************************************************/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <asm/semaphore.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <asm/uaccess.h>
+
+#undef CONFIG_DEVFS_FS //165204:henryhsu devfs will make mei open file fail.
+
+#ifdef CONFIG_DEVFS_FS
+#include <linux/devfs_fs_kernel.h>
+#endif
+#ifdef CONFIG_PROC_FS
+#include <linux/proc_fs.h>
+#endif
+
+#include <linux/list.h>
+#include <linux/delay.h>
+#define __LINUX__
+
+#ifdef CONFIG_PROC_FS
+#define PROC_ITEMS 8
+#define MEI_DIRNAME "mei"
+#endif
+
+#include <asm/ifxmips/ifxmips.h>
+#include <asm/ifxmips/ifxmips_irq.h>
+#include <asm/ifxmips/ifxmips_mei.h>
+#include <asm/ifxmips/ifxmips_mei_app.h>
+#include <asm/ifxmips/ifxmips_mei_ioctl.h>
+#include <asm/ifxmips/ifxmips_mei_app_ioctl.h>
+#include <asm/ifxmips/ifxmips_gpio.h>
+#include <asm/ifxmips/ifxmips_led.h>
+
+#ifdef CONFIG_DEVFS_FS
+#define IFXMIPS_DEVNAME "ifxmips"
+#endif //ifdef CONFIG_DEVFS_FS
+
+#define MEI_LOCKINT(var) \
+ local_save_flags(var);\
+ local_irq_disable()
+#define MEI_UNLOCKINT(var) \
+ local_irq_restore(var)
+
+#define MEI_MUTEX_INIT(id,flag) \
+ sema_init(&id,flag)
+#define MEI_MUTEX_LOCK(id) \
+ down_interruptible(&id)
+#define MEI_MUTEX_UNLOCK(id) \
+ up(&id)
+
+#define MEI_MASK_AND_ACK_IRQ \
+ mask_and_ack_ifxmips_irq
+
+#define MEI_DISABLE_IRQ \
+ disable_irq
+#define MEI_ENABLE_IRQ \
+ enable_irq
+
+#define MEI_WAIT(ms) \
+ {\
+ set_current_state(TASK_INTERRUPTIBLE);\
+ schedule_timeout(ms);\
+ }
+
+#define MEI_INIT_WAKELIST(name,queue) \
+ init_waitqueue_head(&queue)
+
+#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
+ interruptible_sleep_on_timeout(&ev,timeout)
+
+#define MEI_WAIT_EVENT(ev)\
+ interruptible_sleep_on(&ev)
+#define MEI_WAKEUP_EVENT(ev)\
+ wake_up_interruptible(&ev)
+
+typedef unsigned long MEI_intstat_t;
+typedef struct semaphore MEI_mutex_t;
+typedef struct file MEI_file_t;
+typedef struct inode MEI_inode_t;
+
+extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 09:56:03 +0000