diff options
| author | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-09-06 16:27:37 +0000 |
|---|---|---|
| committer | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-09-06 16:27:37 +0000 |
| commit | 17c7b6c3fdc48301e50d22cc6138ede16bd1be24 (patch) | |
| tree | a5d41b991a151e72663527a96fbc6c494565d65c /target/linux/at91-2.6 | |
| parent | 5389989abaa52926b22f9f030d1481df1e73d745 (diff) | |
strip the kernel version suffix from target directories, except for brcm-2.4 (the -2.4 will be included in the board name here). CONFIG_LINUX_<ver>_<board> becomes CONFIG_TARGET_<board>, same for profiles.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8653 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/at91-2.6')
75 files changed, 0 insertions, 45335 deletions
diff --git a/target/linux/at91-2.6/Makefile b/target/linux/at91-2.6/Makefile deleted file mode 100644 index f8ca6f6be3..0000000000 --- a/target/linux/at91-2.6/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=at91 -BOARDNAME:=AT91 -FEATURES:=squashfs usb - -#LINUX_VERSION:=2.6.21.5 -LINUX_VERSION:=2.6.22.4 - -define Target/Description - Build fimware images for Figment Design Labs VersaLink board. -endef - -include $(INCLUDE_DIR)/kernel-build.mk - -#include the profiles --include profiles/*.mk - -KERNELNAME:="uImage" -$(eval $(call BuildKernel)) diff --git a/target/linux/at91-2.6/base-files/default/etc/inittab b/target/linux/at91-2.6/base-files/default/etc/inittab deleted file mode 100644 index a627ce5ffa..0000000000 --- a/target/linux/at91-2.6/base-files/default/etc/inittab +++ /dev/null @@ -1,6 +0,0 @@ -::sysinit:/etc/init.d/rcS S boot -::shutdown:/etc/init.d/rcS K stop -tts/0::askfirst:/bin/ash --login -ttyS0::askfirst:/bin/ash --login - -ttyS2::respawn:/sbin/getty -L ttyS2 115200 vt100 diff --git a/target/linux/at91-2.6/base-files/default/etc/ipkg.conf b/target/linux/at91-2.6/base-files/default/etc/ipkg.conf deleted file mode 100644 index 10c4f67c66..0000000000 --- a/target/linux/at91-2.6/base-files/default/etc/ipkg.conf +++ /dev/null @@ -1,3 +0,0 @@ -src snapshots http://vlink.guthrie.homedns.org/vlink3 -dest root / -dest ram /tmp diff --git a/target/linux/at91-2.6/config/default b/target/linux/at91-2.6/config/default deleted file mode 100644 index 5e74bd616e..0000000000 --- a/target/linux/at91-2.6/config/default +++ /dev/null @@ -1,305 +0,0 @@ -# CONFIG_AEABI is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ARCH_AAEC2000 is not set -CONFIG_ARCH_AT91=y -CONFIG_ARCH_AT91RM9200=y -# CONFIG_ARCH_AT91RM9200DK is not set -# CONFIG_ARCH_AT91SAM9260 is not set -# CONFIG_ARCH_AT91SAM9261 is not set -# CONFIG_ARCH_AT91SAM9263 is not set -# CONFIG_ARCH_AT91SAM9RL is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_ARCH_VERSATILE is not set -CONFIG_ARM=y -CONFIG_ARM_AT91_ETHER=y -CONFIG_ARM_THUMB=y -# CONFIG_ARPD is not set -# CONFIG_ARTHUR is not set -# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set -CONFIG_AT91_SPI=y -# CONFIG_AT91_SPIDEV is not set -# CONFIG_ATMEL_TCLIB is not set -CONFIG_ATM_DRIVERS=y -# CONFIG_ATM_DUMMY is not set -# CONFIG_ATM_TCP is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BINFMT_AOUT is not set -CONFIG_BITREVERSE=y -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BONDING is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_BT is not set -# CONFIG_CIFS_STATS is not set -# CONFIG_CLS_U32_MARK is not set -# CONFIG_CLS_U32_PERF is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_CPU_32=y -CONFIG_CPU_32v4T=y -CONFIG_CPU_ABRT_EV4T=y -CONFIG_CPU_ARM920T=y -CONFIG_CPU_CACHE_V4WT=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_TLB_V4WBI=y -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_BLKCIPHER=m -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_CBC=m -# CONFIG_CRYPTO_CRC32C is not set -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HMAC=y -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=m -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_WP512 is not set -CONFIG_DAVICOM_PHY=y -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_USER is not set -# CONFIG_DM9000 is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FIXED_PHY is not set -# CONFIG_FPE_FASTFPE is not set -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -CONFIG_FRAME_POINTER=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FW_LOADER=m -# CONFIG_GENERIC_CLOCKEVENTS is not set -CONFIG_GENERIC_GPIO=y -# CONFIG_GENERIC_TIME is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HID=y -CONFIG_HW_CONSOLE=y -# CONFIG_HW_RANDOM is not set -# CONFIG_I2C is not set -# CONFIG_IKCONFIG is not set -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -# CONFIG_INPUT_EVDEV is not set -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_RAW is not set -# CONFIG_IP6_NF_TARGET_HL is not set -# CONFIG_IP6_NF_TARGET_LOG is not set -# CONFIG_IP_NF_ARPTABLES is not set -# CONFIG_IP_NF_MATCH_ADDRTYPE is not set -# CONFIG_IP_NF_TARGET_LOG is not set -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_NF_TARGET_SAME is not set -# CONFIG_IP_ROUTE_VERBOSE is not set -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_LEDS=y -CONFIG_LEDS_CPU=y -CONFIG_LEDS_TIMER=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=32 -# CONFIG_LIBCRC32C is not set -# CONFIG_LLC2 is not set -# CONFIG_MACH_AT91RM9200EK is not set -# CONFIG_MACH_ATEB9200 is not set -# CONFIG_MACH_CARMEVA is not set -# CONFIG_MACH_CHUB is not set -# CONFIG_MACH_CSB337 is not set -# CONFIG_MACH_CSB637 is not set -# CONFIG_MACH_KAFA is not set -# CONFIG_MACH_KB9200 is not set -# CONFIG_MACH_ONEARM is not set -# CONFIG_MACH_PICOTUX2XX is not set -CONFIG_MMC=m -CONFIG_MMC_AT91=m -CONFIG_MMC_BLOCK=m -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_AFS_PARTS is not set -CONFIG_MTD_AT91_DATAFLASH=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CHAR=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DATAFLASH26 is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_ONENAND is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ROOTFS_ROOT_DEV is not set -# CONFIG_MTD_ROOTFS_SPLIT is not set -# CONFIG_MTD_SLRAM is not set -CONFIG_NETDEV_1000=y -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_IPGRE_BROADCAST is not set -# CONFIG_NET_PKTGEN is not set -CONFIG_NET_SCH_FIFO=y -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_NO_IDLE_HZ is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_NVRAM is not set -# CONFIG_OUTER_CACHE is not set -CONFIG_PHYLIB=y -# CONFIG_PNPACPI is not set -# CONFIG_PPPOATM is not set -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_SYNC_TTY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_ROMFS_FS is not set -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_WAIT_SCAN=m -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_ATMEL=y -CONFIG_SERIAL_ATMEL_CONSOLE=y -# CONFIG_SERIAL_ATMEL_TTYAT is not set -CONFIG_SERIO=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SMC91X is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_SOUND is not set -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TICK_ONESHOT is not set -CONFIG_UID16=y -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB_ATM is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -CONFIG_USB_LIBUSUAL=y -CONFIG_USB_MON=y -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_HCD=m -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_USBNET is not set -# CONFIG_USB_USBNET_MII is not set -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VGASTATE is not set -# CONFIG_VGA_CONSOLE is not set -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_WATCHDOG is not set -# CONFIG_XIP_KERNEL is not set -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/at91-2.6/files/drivers/mtd/at91part.c b/target/linux/at91-2.6/files/drivers/mtd/at91part.c deleted file mode 100644 index bfa9590492..0000000000 --- a/target/linux/at91-2.6/files/drivers/mtd/at91part.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * $Id: at91part.c 6948 2007-04-15 04:01:45Z hcg $ - * - * Copyright (C) 2007 OpenWrt.org - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Atmel AT91 flash partition table. (Modified by Hamish Guthrie). - * Based on ar7 map by Felix Fietkau. - * - */ - -#include <linux/kernel.h> -#include <linux/slab.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/bootmem.h> -#include <linux/squashfs_fs.h> - -static struct mtd_partition at91_parts[6]; - -static int create_mtd_partitions(struct mtd_info *master, - struct mtd_partition **pparts, - unsigned long origin) -{ - unsigned int offset, len; - unsigned int pre_size = 0x42000, root_max = 0x362400; - unsigned char buf[512]; - struct squashfs_super_block *sb = (struct squashfs_super_block *) buf; - - printk("Parsing AT91 partition map...\n"); - - at91_parts[0].name = "loaders"; - at91_parts[0].offset = 0; - at91_parts[0].size = 0x21000; - at91_parts[0].mask_flags = MTD_WRITEABLE; - - at91_parts[1].name = "ubparams"; - at91_parts[1].offset = 0x21000; - at91_parts[1].size = 0x8400; - at91_parts[1].mask_flags = 0; - - at91_parts[2].name = "kernel"; - at91_parts[2].offset = pre_size; - at91_parts[2].size = 0; - at91_parts[2].mask_flags = 0; - - at91_parts[3].name = "rootfs"; - at91_parts[3].offset = 0; - at91_parts[3].size = 0; - at91_parts[3].mask_flags = 0; - - for(offset = pre_size; offset < root_max; offset += master->erasesize) { - - memset(&buf, 0xe5, sizeof(buf)); - - if (master->read(master, offset, sizeof(buf), &len, buf) || len != sizeof(buf)) - break; - - if (*((__u32 *) buf) == SQUASHFS_MAGIC) { - printk(KERN_INFO "%s: Filesystem type: squashfs, size=0x%x\n", - master->name, (u32) sb->bytes_used); - - at91_parts[3].size = sb->bytes_used; - at91_parts[3].offset = offset; - len = at91_parts[3].offset + at91_parts[3].size; - len = ((len / (master->erasesize * 8)) + 1) * master->erasesize * 8; - at91_parts[3].size = len - at91_parts[3].offset; - at91_parts[2].size = offset - at91_parts[2].offset; - break; - } - } - - if (at91_parts[3].size == 0) { - printk(KERN_NOTICE "%s: Couldn't find root filesystem\n", master->name); - return -1; - } - - at91_parts[4].name = "rootfs_data"; - at91_parts[4].offset = root_max; - at91_parts[4].size = master->size - root_max; - at91_parts[4].mask_flags = 0; - - at91_parts[5].name = "complete"; - at91_parts[5].offset = 0; - at91_parts[5].size = master->size; - at91_parts[5].mask_flags = 0; - - *pparts = at91_parts; - return 6; -} - -static struct mtd_part_parser at91_parser = { - .owner = THIS_MODULE, - .parse_fn = create_mtd_partitions, - .name = "at91part", -}; - -static int __init at91_parser_init(void) -{ - return register_mtd_parser(&at91_parser); -} - -module_init(at91_parser_init); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Felix Fietkau, Eugene Konev, Hamish Guthrie"); -MODULE_DESCRIPTION("MTD partitioning for Atmel at91"); diff --git a/target/linux/at91-2.6/image/Config.in b/target/linux/at91-2.6/image/Config.in deleted file mode 100644 index 6607f6c325..0000000000 --- a/target/linux/at91-2.6/image/Config.in +++ /dev/null @@ -1,35 +0,0 @@ -config AT91_DFBOOT - bool "Build dataflashboot loader" - depends LINUX_2_6_AT91 - default y - -config AT91_UBOOT - bool "Build u-boot loader" - depends LINUX_2_6_AT91 - default y - -config UBOOT_TARGET - string "U-Boot Board Configuration" - depends LINUX_2_6_AT91 - depends AT91_UBOOT - default "vlink" - help - For all supported boards there are ready-to-use default - configurations available; just type "<board_name>". - -config UBOOT_IPADDR - string "IP Address for U-Boot" - depends LINUX_2_6_AT91 - depends AT91_UBOOT - default "192.168.0.178" - help - IP address of device to be used in U-Boot - -config UBOOT_SERVERIP - string "IP Address of TFTP server" - depends LINUX_2_6_AT91 - depends AT91_UBOOT - default "192.168.0.232" - help - IP address of TFTP server for U-Boot - diff --git a/target/linux/at91-2.6/image/Makefile b/target/linux/at91-2.6/image/Makefile deleted file mode 100644 index 7e855f06ef..0000000000 --- a/target/linux/at91-2.6/image/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Build/Clean - $(MAKE) -C dfboot clean - $(MAKE) -C u-boot clean -endef - -define Build/Compile - $(MAKE) -C dfboot compile - $(MAKE) -C u-boot compile - $(KDIR)/u-boot-1.1.4/tools/ubparams - cp params $(KDIR) -endef - -define Image/Prepare - cp $(LINUX_DIR)/arch/arm/boot/uImage $(KDIR)/uImage - cp $(KDIR)/dfboot/dfboot.bin $(KDIR)/dfboot.bin - cp $(KDIR)/dfboot/dfbptest.bin $(KDIR)/dfbptest.bin - cp $(KDIR)/u-boot-1.1.4/u-boot.bin $(KDIR)/u-boot.bin - dd if=$(KDIR)/u-boot.bin of=$(KDIR)/u-boot.block bs=100k count=1 conv=sync - cat $(KDIR)/u-boot.block $(KDIR)/params > $(KDIR)/u-boot.full -endef - -define Image/BuildKernel - cp $(KDIR)/uImage $(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-uImage -endef - -define Image/Build - dd if=$(KDIR)/uImage of=$(KDIR)/uImage.block bs=8448 conv=sync - dd if=$(KDIR)/root.squashfs of=$(KDIR)/root.block bs=8448 conv=sync - cat $(KDIR)/uImage.block $(KDIR)/root.block > $(KDIR)/knlroot.bin - $(STAGING_DIR_HOST)/bin/trx -o $(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL).trx -f $(KDIR)/dfboot.bin -f$(KDIR)/u-boot.full -f$(KDIR)/knlroot.bin - cp $(KDIR)/dfbptest.bin $(BIN_DIR) - $(call Image/Build/$(1),$(1)) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/at91-2.6/image/dfboot/Makefile b/target/linux/at91-2.6/image/dfboot/Makefile deleted file mode 100644 index 355a4b540f..0000000000 --- a/target/linux/at91-2.6/image/dfboot/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -# $Id$ - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=dfboot -PKG_VERSION:=0.1 -PKG_RELEASE:=1 - -PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME) - -include $(INCLUDE_DIR)/package.mk - -define Build/Prepare - mkdir -p $(PKG_BUILD_DIR) - $(CP) ./src/* $(PKG_BUILD_DIR)/ -endef - -define Build/Compile - $(MAKE) -C $(PKG_BUILD_DIR) \ - $(TARGET_CONFIGURE_OPTS) \ - CFLAGS="$(TARGET_CFLAGS)" -endef - -define Build/InstallDev - dd if=$(PKG_BUILD_DIR)/binary/dfboot.bin of=$(PKG_BUILD_DIR)/binary/dfboot.block bs=32k count=1 conv=sync -endef - -$(eval $(call Build/DefaultTargets)) diff --git a/target/linux/at91-2.6/image/dfboot/src/Makefile b/target/linux/at91-2.6/image/dfboot/src/Makefile deleted file mode 100644 index ff92e0d499..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -# Makefile for DataFlashBoot.bin -# Must use toolchain with H/W FLoating Point - -BASENAME=dfboot -BINNAME=$(BASENAME).bin -OUTNAME=$(BASENAME).out -LSSNAME=$(BASENAME).lss -MAPNAME=$(BASENAME).map - -BASENAME2=dfbptest -BINNAME2=$(BASENAME2).bin -OUTNAME2=$(BASENAME2).out -LSSNAME2=$(BASENAME2).lss -MAPNAME2=$(BASENAME2).map - -INCPATH=include - -CFLAGS_LOCAL=-Os -Wall -I$(INCPATH) -BUILD=$(CC) $(CFLAGS) $(CFLAGS_LOCAL) - -LDFLAGS+=-T elf32-littlearm.lds -Ttext 0 -LINK=$(LD) $(LDFLAGS) - -OBJS=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\ - objs/div0.o objs/init.o objs/main.o objs/asm_isr.o objs/asm_mci_isr.o\ - objs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o - -OBJS2=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\ - objs/div0.o objs/init.o objs/ptmain.o objs/asm_isr.o objs/asm_mci_isr.o\ - objs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o - -I=config.h com.h dataflash.h embedded_services.h main.h stdio.h include/AT91RM9200.h include/lib_AT91RM9200.h - -all:clean $(BASENAME) $(BASENAME2) - -$(BASENAME): $(OBJS) - $(LINK) -n -o $(OUTNAME) $(OBJS) - $(OBJCOPY) $(OUTNAME) -O binary $(BINNAME) - $(OBJDUMP) -h -s $(OUTNAME) > $(LSSNAME) - $(NM) -n $(OUTNAME) | grep -v '\( [aUw] \)\|\(__crc_\)\|\( \$[adt]\)' > $(MAPNAME) - cp $(BINNAME) binary - -$(BASENAME2): $(OBJS2) - $(LINK) -n -o $(OUTNAME2) $(OBJS2) - $(OBJCOPY) $(OUTNAME2) -O binary $(BINNAME2) - $(OBJDUMP) -h -s $(OUTNAME2) > $(LSSNAME2) - $(NM) -n $(OUTNAME2) | grep -v '\( [aUw] \)\|\(__crc_\)\|\( \$[adt]\)' > $(MAPNAME2) - cp $(BINNAME2) binary - -# C objects here -objs/at45.o: at45.c $(I) - $(BUILD) -c -o objs/at45.o at45.c -objs/com.o: com.c $(I) - $(BUILD) -c -o objs/com.o com.c -objs/dataflash.o: dataflash.c $(I) - $(BUILD) -c -o objs/dataflash.o dataflash.c -objs/mci_device.o: mci_device.c $(I) - $(BUILD) -c -o objs/mci_device.o mci_device.c -objs/div0.o: div0.c $(I) - $(BUILD) -c -o objs/div0.o div0.c -objs/init.o: init.c $(I) - $(BUILD) -c -o objs/init.o init.c -objs/main.o: main.c $(I) - $(BUILD) -c -o objs/main.o main.c -objs/ptmain.o: main.c $(I) - $(BUILD) -c -D PRODTEST -o objs/ptmain.o main.c - -# ASM objects here -objs/asm_isr.o: asm_isr.S - $(BUILD) -c -o objs/asm_isr.o asm_isr.S -objs/asm_mci_isr.o: asm_mci_isr.S - $(BUILD) -c -o objs/asm_mci_isr.o asm_mci_isr.S -objs/cstartup_ram.o: cstartup_ram.S - $(BUILD) -c -o objs/cstartup_ram.o cstartup_ram.S -objs/jump.o: jump.S - $(BUILD) -c -o objs/jump.o jump.S -objs/_udivsi3.o: _udivsi3.S - $(BUILD) -c -o objs/_udivsi3.o _udivsi3.S -objs/_umodsi3.o: _umodsi3.S - $(BUILD) -c -o objs/_umodsi3.o _umodsi3.S - -install: $(BINNAME) $(BINNAME2) - cp $(BINNAME) binary - cp $(BINNAME2) binary - -clean: - rm -f *~ - rm -f objs/* - rm -f *.out - rm -f *.bin - rm -f *.lss - rm -f *.map - rm -f .unpacked - mkdir -p objs diff --git a/target/linux/at91-2.6/image/dfboot/src/_udivsi3.S b/target/linux/at91-2.6/image/dfboot/src/_udivsi3.S deleted file mode 100644 index 2cdcd48b49..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/_udivsi3.S +++ /dev/null @@ -1,77 +0,0 @@ -/* # 1 "libgcc1.S" */ -@ libgcc1 routines for ARM cpu. -@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) -dividend .req r0 -divisor .req r1 -result .req r2 -curbit .req r3 -/* ip .req r12 */ -/* sp .req r13 */ -/* lr .req r14 */ -/* pc .req r15 */ - .text - .globl __udivsi3 - .type __udivsi3 ,function - .align 0 - __udivsi3 : - cmp divisor, #0 - beq Ldiv0 - mov curbit, #1 - mov result, #0 - cmp dividend, divisor - bcc Lgot_result -Loop1: - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. - cmp divisor, #0x10000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #4 - movcc curbit, curbit, lsl #4 - bcc Loop1 -Lbignum: - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. - cmp divisor, #0x80000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #1 - movcc curbit, curbit, lsl #1 - bcc Lbignum -Loop3: - @ Test for possible subtractions, and note which bits - @ are done in the result. On the final pass, this may subtract - @ too much from the dividend, but the result will be ok, since the - @ "bit" will have been shifted out at the bottom. - cmp dividend, divisor - subcs dividend, dividend, divisor - orrcs result, result, curbit - cmp dividend, divisor, lsr #1 - subcs dividend, dividend, divisor, lsr #1 - orrcs result, result, curbit, lsr #1 - cmp dividend, divisor, lsr #2 - subcs dividend, dividend, divisor, lsr #2 - orrcs result, result, curbit, lsr #2 - cmp dividend, divisor, lsr #3 - subcs dividend, dividend, divisor, lsr #3 - orrcs result, result, curbit, lsr #3 - cmp dividend, #0 @ Early termination? - movnes curbit, curbit, lsr #4 @ No, any more bits to do? - movne divisor, divisor, lsr #4 - bne Loop3 -Lgot_result: - mov r0, result - mov pc, lr -Ldiv0: - str lr, [sp, #-4]! - bl __div0 (PLT) - mov r0, #0 @ about as wrong as it could be - ldmia sp!, {pc} - .size __udivsi3 , . - __udivsi3 -/* # 235 "libgcc1.S" */ -/* # 320 "libgcc1.S" */ -/* # 421 "libgcc1.S" */ -/* # 433 "libgcc1.S" */ -/* # 456 "libgcc1.S" */ -/* # 500 "libgcc1.S" */ -/* # 580 "libgcc1.S" */ diff --git a/target/linux/at91-2.6/image/dfboot/src/_umodsi3.S b/target/linux/at91-2.6/image/dfboot/src/_umodsi3.S deleted file mode 100644 index e4aebe84ca..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/_umodsi3.S +++ /dev/null @@ -1,88 +0,0 @@ -/* # 1 "libgcc1.S" */ -@ libgcc1 routines for ARM cpu. -@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) -/* # 145 "libgcc1.S" */ -dividend .req r0 -divisor .req r1 -overdone .req r2 -curbit .req r3 -/* ip .req r12 */ -/* sp .req r13 */ -/* lr .req r14 */ -/* pc .req r15 */ - .text - .globl __umodsi3 - .type __umodsi3 ,function - .align 0 - __umodsi3 : - cmp divisor, #0 - beq Ldiv0 - mov curbit, #1 - cmp dividend, divisor - movcc pc, lr -Loop1: - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. - cmp divisor, #0x10000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #4 - movcc curbit, curbit, lsl #4 - bcc Loop1 -Lbignum: - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. - cmp divisor, #0x80000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #1 - movcc curbit, curbit, lsl #1 - bcc Lbignum -Loop3: - @ Test for possible subtractions. On the final pass, this may - @ subtract too much from the dividend, so keep track of which - @ subtractions are done, we can fix them up afterwards... - mov overdone, #0 - cmp dividend, divisor - subcs dividend, dividend, divisor - cmp dividend, divisor, lsr #1 - subcs dividend, dividend, divisor, lsr #1 - orrcs overdone, overdone, curbit, ror #1 - cmp dividend, divisor, lsr #2 - subcs dividend, dividend, divisor, lsr #2 - orrcs overdone, overdone, curbit, ror #2 - cmp dividend, divisor, lsr #3 - subcs dividend, dividend, divisor, lsr #3 - orrcs overdone, overdone, curbit, ror #3 - mov ip, curbit - cmp dividend, #0 @ Early termination? - movnes curbit, curbit, lsr #4 @ No, any more bits to do? - movne divisor, divisor, lsr #4 - bne Loop3 - @ Any subtractions that we should not have done will be recorded in - @ the top three bits of "overdone". Exactly which were not needed - @ are governed by the position of the bit, stored in ip. - @ If we terminated early, because dividend became zero, - @ then none of the below will match, since the bit in ip will not be - @ in the bottom nibble. - ands overdone, overdone, #0xe0000000 - moveq pc, lr @ No fixups needed - tst overdone, ip, ror #3 - addne dividend, dividend, divisor, lsr #3 - tst overdone, ip, ror #2 - addne dividend, dividend, divisor, lsr #2 - tst overdone, ip, ror #1 - addne dividend, dividend, divisor, lsr #1 - mov pc, lr -Ldiv0: - str lr, [sp, #-4]! - bl __div0 (PLT) - mov r0, #0 @ about as wrong as it could be - ldmia sp!, {pc} - .size __umodsi3 , . - __umodsi3 -/* # 320 "libgcc1.S" */ -/* # 421 "libgcc1.S" */ -/* # 433 "libgcc1.S" */ -/* # 456 "libgcc1.S" */ -/* # 500 "libgcc1.S" */ -/* # 580 "libgcc1.S" */ diff --git a/target/linux/at91-2.6/image/dfboot/src/asm_isr.S b/target/linux/at91-2.6/image/dfboot/src/asm_isr.S deleted file mode 100644 index 8d1d52e191..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/asm_isr.S +++ /dev/null @@ -1,75 +0,0 @@ -#include "AT91RM9200_inc.h" - -#define ARM_MODE_USER 0x10 -#define ARM_MODE_FIQ 0x11 -#define ARM_MODE_IRQ 0x12 -#define ARM_MODE_SVC 0x13 -#define ARM_MODE_ABORT 0x17 -#define ARM_MODE_UNDEF 0x1B -#define ARM_MODE_SYS 0x1F - -#define I_BIT 0x80 -#define F_BIT 0x40 -#define T_BIT 0x20 - - -/* ----------------------------------------------------------------------------- - AT91F_ASM_SPI_Handler - --------------------- - Handler called by the AIC - - Save context - Call C handler - Restore context - ----------------------------------------------------------------------------- */ - -.global AT91F_ST_ASM_HANDLER - -AT91F_ST_ASM_HANDLER: -/* Adjust and save LR_irq in IRQ stack */ - sub r14, r14, #4 - stmfd sp!, {r14} - -/* Write in the IVR to support Protect Mode - No effect in Normal Mode - De-assert the NIRQ and clear the source in Protect Mode */ - ldr r14, =AT91C_BASE_AIC - str r14, [r14, #AIC_IVR] - -/* Save SPSR and r0 in IRQ stack */ - mrs r14, SPSR - stmfd sp!, {r0, r14} - -/* Enable Interrupt and Switch in SYS Mode */ - mrs r0, CPSR - bic r0, r0, #I_BIT - orr r0, r0, #ARM_MODE_SYS - msr CPSR_c, r0 - -/* Save scratch/used registers and LR in User Stack */ - stmfd sp!, { r1-r3, r12, r14} - - ldr r1, =AT91F_ST_HANDLER - mov r14, pc - bx r1 - -/* Restore scratch/used registers and LR from User Stack */ - ldmia sp!, { r1-r3, r12, r14} - -/* Disable Interrupt and switch back in IRQ mode */ - mrs r0, CPSR - bic r0, r0, #ARM_MODE_SYS - orr r0, r0, #I_BIT | ARM_MODE_IRQ - msr CPSR_c, r0 - -/* Mark the End of Interrupt on the AIC */ - ldr r0, =AT91C_BASE_AIC - str r0, [r0, #AIC_EOICR] - -/* Restore SPSR_irq and r0 from IRQ stack */ - ldmia sp!, {r0, r14} - msr SPSR_cxsf, r14 - -/* Restore adjusted LR_irq from IRQ stack directly in the PC */ - ldmia sp!, {pc}^ - diff --git a/target/linux/at91-2.6/image/dfboot/src/asm_mci_isr.S b/target/linux/at91-2.6/image/dfboot/src/asm_mci_isr.S deleted file mode 100644 index 0f66fc0d69..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/asm_mci_isr.S +++ /dev/null @@ -1,75 +0,0 @@ -#include <AT91RM9200_inc.h> - -#define ARM_MODE_USER 0x10 -#define ARM_MODE_FIQ 0x11 -#define ARM_MODE_IRQ 0x12 -#define ARM_MODE_SVC 0x13 -#define ARM_MODE_ABORT 0x17 -#define ARM_MODE_UNDEF 0x1B -#define ARM_MODE_SYS 0x1F - -#define I_BIT 0x80 -#define F_BIT 0x40 -#define T_BIT 0x20 - - -/* ----------------------------------------------------------------------------- - AT91F_ASM_MCI_Handler - --------------------- - Handler called by the AIC - - Save context - Call C handler - Restore context - ----------------------------------------------------------------------------- */ - -.global AT91F_ASM_MCI_Handler - -AT91F_ASM_MCI_Handler: -/* Adjust and save LR_irq in IRQ stack */ - sub r14, r14, #4 - stmfd sp!, {r14} - -/* Write in the IVR to support Protect Mode - No effect in Normal Mode - De-assert the NIRQ and clear the source in Protect Mode */ - ldr r14, =AT91C_BASE_AIC - str r14, [r14, #AIC_IVR] - -/* Save SPSR and r0 in IRQ stack */ - mrs r14, SPSR - stmfd sp!, {r0, r14} - -/* Enable Interrupt and Switch in SYS Mode */ - mrs r0, CPSR - bic r0, r0, #I_BIT - orr r0, r0, #ARM_MODE_SYS - msr CPSR_c, r0 - -/* Save scratch/used registers and LR in User Stack */ - stmfd sp!, { r1-r3, r12, r14} - - ldr r1, =AT91F_MCI_Handler - mov r14, pc - bx r1 - -/* Restore scratch/used registers and LR from User Stack */ - ldmia sp!, { r1-r3, r12, r14} - -/* Disable Interrupt and switch back in IRQ mode */ - mrs r0, CPSR - bic r0, r0, #ARM_MODE_SYS - orr r0, r0, #I_BIT | ARM_MODE_IRQ - msr CPSR_c, r0 - -/* Mark the End of Interrupt on the AIC */ - ldr r0, =AT91C_BASE_AIC - str r0, [r0, #AIC_EOICR] - -/* Restore SPSR_irq and r0 from IRQ stack */ - ldmia sp!, {r0, r14} - msr SPSR_cxsf, r14 - -/* Restore adjusted LR_irq from IRQ stack directly in the PC */ - ldmia sp!, {pc}^ - diff --git a/target/linux/at91-2.6/image/dfboot/src/at45.c b/target/linux/at91-2.6/image/dfboot/src/at45.c deleted file mode 100644 index 8830d7e9b8..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/at45.c +++ /dev/null @@ -1,595 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : at45c.h - * Object : - * - * 1.0 10/12/03 HIi : Creation. - * 1.01 03/05/04 HIi : Bug Fix in AT91F_DataFlashWaitReady() Function. - *---------------------------------------------------------------------------- - */ -#include "config.h" -#include "stdio.h" -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" -#include "dataflash.h" -#include "main.h" - - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiInit */ -/* \brief SPI Low level Init */ -/*----------------------------------------------------------------------------*/ -void AT91F_SpiInit(void) { - /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | - AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | - AT91C_PA2_SPCK; - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | - AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | - AT91C_PA2_SPCK; - /* Enable CLock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; - - /* Reset the SPI */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); -} - - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiEnable */ -/* \brief Enable SPI chip select */ -/*----------------------------------------------------------------------------*/ -static void AT91F_SpiEnable(int cs) { - switch(cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH << 16) & AT91C_SPI_PCS); - break; - case 3: /* Configure SPI CS3 for Serial DataFlash Card */ - /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ - AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; - /* Configure PCS */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -} - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiWrite */ -/* \brief Set the PDC registers for a transfert */ -/*----------------------------------------------------------------------------*/ -static unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) -{ - unsigned int timeout; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; - AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; - - if ( pDesc->tx_data_size != 0 ) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; - AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; - AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; - } - - /* ARM simple, non interrupt dependent timer */ - timeout = 0; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF)); - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - if (timeout >= AT91C_DATAFLASH_TIMEOUT){ - return AT91C_DATAFLASH_ERROR; - } - - return AT91C_DATAFLASH_OK; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashSendCommand */ -/* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress) -{ - unsigned int adr; - - /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) - << pDataFlash->pDevice->page_offset) + - (DataflashAddress % (pDataFlash->pDevice->pages_size)); - - /* fill the command buffer */ - pDataFlash->pDataFlashDesc->command[0] = OpCode; - if (pDataFlash->pDevice->pages_number >= 16384) - { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); - } - else - { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - } - pDataFlash->pDataFlashDesc->command[5] = 0; - pDataFlash->pDataFlashDesc->command[6] = 0; - pDataFlash->pDataFlashDesc->command[7] = 0; - - /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashGetStatus */ -/* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -{ - AT91S_DataFlashStatus status; - - /* first send the read status command (D7H) */ - pDesc->command[0] = DB_STATUS; - pDesc->command[1] = 0; - - pDesc->DataFlash_state = GET_STATUS; - pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ - pDesc->tx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_size = 2 ; - pDesc->tx_cmd_size = 2 ; - status = AT91F_SpiWrite (pDesc); - - pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); - return status; -} - -/*----------------------------------------------------------------------------- - * Function Name : AT91F_DataFlashWaitReady - * Object : wait for dataflash ready (bit7 of the status register == 1) - * Input Parameters : DataFlash Service and timeout - * Return value : DataFlash status "ready or not" - *----------------------------------------------------------------------------- - */ -static AT91S_DataFlashStatus AT91F_DataFlashWaitReady( - AT91PS_DataflashDesc pDataFlashDesc, - unsigned int timeout) -{ - pDataFlashDesc->DataFlash_state = IDLE; - do { - AT91F_DataFlashGetStatus(pDataFlashDesc); - timeout--; - } - while(((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0)); - - if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) - return AT91C_DATAFLASH_ERROR; - - return AT91C_DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashContinuousRead */ -/* Object : Continuous stream Read */ -/* Input Parameters : DataFlash Service */ -/* : <src> = dataflash address */ -/* : <*dataBuffer> = data buffer pointer */ -/* : <sizeToRead> = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_DataFlashContinuousRead( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ) -{ - AT91S_DataFlashStatus status; - /* Test the size to read in the device */ - if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return AT91C_DATAFLASH_MEMORY_OVERFLOW; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - - status = AT91F_DataFlashSendCommand(pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); - /* Send the command to the dataflash */ - return(status); -} - - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_MainMemoryToBufferTransfer */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfer( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) - return AT91C_DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize, - page*pDataFlash->pDevice->pages_size)); -} - - - -/*----------------------------------------------------------------------------- */ -/* Function Name : AT91F_DataFlashWriteBuffer */ -/* Object : Write data to the internal sram buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : <BufferCommand> = command to write buffer1 or buffer2 */ -/* : <*dataBuffer> = data buffer to write */ -/* : <bufferAddress> = address in the internal buffer */ -/* : <SizeToWrite> = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) - return AT91C_DATAFLASH_BAD_COMMAND; - - /* buffer address must be lower than page size */ - if (bufferAddress > pDataFlash->pDevice->pages_size) - return AT91C_DATAFLASH_BAD_ADDRESS; - - /* Send first Write Command */ - pDataFlash->pDataFlashDesc->command[0] = BufferCommand; - pDataFlash->pDataFlashDesc->command[1] = 0; - if (pDataFlash->pDevice->pages_number >= 16384) - { - pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - cmdsize = 5; - } - else - { - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - cmdsize = 4; - } - - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PageErase */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_ERASE, cmdsize, - page*pDataFlash->pDevice->pages_size)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_WriteBufferToMain */ -/* Object : Write buffer to the main memory */ -/* Input Parameters : DataFlash Service */ -/* : <BufferCommand> = command to send to buf1 or buf2 */ -/* : <dest> = main memory address */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ) -{ - int cmdsize; - /* Test if the buffer command is correct */ - if ((BufferCommand != DB_BUF1_PAGE_PGM) && - (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && - (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) - return AT91C_DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - /* Send the command to the dataflash */ - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PartialPageWrite */ -/* Object : Erase partially a page */ -/* Input Parameters : <page> = page number */ -/* : <AdrInpage> = adr to begin the fading */ -/* : <length> = Number of bytes to erase */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) -{ - unsigned int page; - unsigned int AdrInPage; - - page = dest / (pDataFlash->pDevice->pages_size); - AdrInPage = dest % (pDataFlash->pDevice->pages_size); - - /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfer(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - /* Erase page if a 128 Mbits device */ - if (pDataFlash->pDevice->pages_number >= 16384) - { - AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - } - - /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, - (page*pDataFlash->pDevice->pages_size))); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashWrite */ -/* Object : */ -/* Input Parameters : <*src> = Source buffer */ -/* : <dest> = dataflash adress */ -/* : <size> = data buffer size */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ) -{ - unsigned int length; - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return AT91C_DATAFLASH_MEMORY_OVERFLOW; - - /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); - - if (size < length) - length = size; - - if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) - return AT91C_DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - /* Update size, source and destination pointers */ - size -= length; - dest += length; - src += length; - } - - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) - { - /* program dataflash page */ - page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - - status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, - 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - if (!status) - return AT91C_DATAFLASH_ERROR; - - status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); - if(!status) - return AT91C_DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - /* Update size, source and destination pointers */ - size -= pDataFlash->pDevice->pages_size ; - dest += pDataFlash->pDevice->pages_size ; - src += pDataFlash->pDevice->pages_size ; - } - - /* If still some bytes to read */ - if ( size > 0 ) { - /* program dataflash page */ - if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) - return AT91C_DATAFLASH_ERROR; - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - } - return AT91C_DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashRead */ -/* Object : Read a block in dataflash */ -/* Input Parameters : */ -/* Return value : */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer) -{ - unsigned long SizeToRead; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT) != AT91C_DATAFLASH_OK) - return -1; - - while (size) - { - SizeToRead = (size < 0x8000)? size:0x8000; - - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT) - != AT91C_DATAFLASH_OK) - return -1; - - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (unsigned char *)buffer, - SizeToRead) != AT91C_DATAFLASH_OK) - return -1; - - size -= SizeToRead; - addr += SizeToRead; - buffer += SizeToRead; - } - - return AT91C_DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashProbe */ -/* Object : */ -/* Input Parameters : */ -/* Return value : Dataflash status register */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -{ - AT91F_SpiEnable(cs); - AT91F_DataFlashGetStatus(pDesc); - return ((pDesc->command[1] == 0xFF)? 0: (pDesc->command[1] & 0x3C)); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashErase */ -/* Object : */ -/* Input Parameters : <*pDataFlash> = Device info */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash) -{ - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - for(page=0; page < pDataFlash->pDevice->pages_number; page++) - { - /* Erase dataflash page */ - if ((page & 0x00FF) == 0) - printf("\rERA %d/%d", page, pDataFlash->pDevice->pages_number); - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - if (!status) - return AT91C_DATAFLASH_ERROR; - } - - return AT91C_DATAFLASH_OK; -} - diff --git a/target/linux/at91-2.6/image/dfboot/src/com.c b/target/linux/at91-2.6/image/dfboot/src/com.c deleted file mode 100644 index aacfb55558..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/com.c +++ /dev/null @@ -1,368 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : com.c - * Object : - * Creation : HIi 03/27/2003 - * - *---------------------------------------------------------------------------- - */ -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" -#include "config.h" -#include "com.h" -#include "stdio.h" - -static char erase_seq[] = "\b \b"; /* erase sequence */ - -#define MAX_UARTS 1 - -//unsigned int usa[2] = {(unsigned int)AT91C_BASE_DBGU, (unsigned int)AT91C_ALTERNATE_USART}; -unsigned int usa[1] = {(unsigned int)AT91C_BASE_DBGU}; -unsigned int us; -int port_detected; - -void at91_init_uarts(void) -{ - int i; - - port_detected = 0; - AT91F_DBGU_CfgPIO(); - AT91F_US0_CfgPIO(); - AT91F_US0_CfgPMC(); - - for(i=0; i<MAX_UARTS; i++) { - us = usa[i]; - AT91F_US_ResetRx((AT91PS_USART)us); - AT91F_US_ResetTx((AT91PS_USART)us); - - // Configure DBGU - AT91F_US_Configure( - (AT91PS_USART)us, // DBGU base address - AT91C_MASTER_CLOCK, // 60 MHz - AT91C_US_ASYNC_MODE, // mode Register to be programmed - 115200, // baudrate to be programmed - 0 // timeguard to be programmed - ); - - // Enable Transmitter - AT91F_US_EnableTx((AT91PS_USART)us); - // Enable Receiver - AT91F_US_EnableRx((AT91PS_USART)us); - } - us = usa[0]; -} - -int at91_serial_putc(int ch) -{ - if (ch == '\n') - at91_serial_putc('\r'); - while (!AT91F_US_TxReady((AT91PS_USART)us)); - AT91F_US_PutChar((AT91PS_USART)us, (char)ch); - return ch; -} - -/* This getc is modified to be able work on more than one port. On certain - * boards (i.e. Figment Designs VersaLink), the debug port is not available - * once the unit is in it's enclosure, so, if one needs to get into dfboot - * for any reason it is impossible. With this getc, it scans between the debug - * port and another port and once it receives a character, it sets that port - * as the debug port. */ -int at91_serial_getc() -{ - while(1) { -#if 0 - if (!port_detected) { - if (us == usa[0]) { - us = usa[1]; - } - else { - us = usa[0]; - } - } -#endif - if(AT91F_US_RxReady((AT91PS_USART)us)) { -#if 0 - port_detected = 1; -#endif - return((int)AT91F_US_GetChar((AT91PS_USART)us)); - } - } -} - -/*----------------------------------------------------------------------------- - * Function Name : AT91F_ReadLine() - * Object : - * Input Parameters : - * Return value : - *----------------------------------------------------------------------------- - */ -int AT91F_ReadLine (const char *const prompt, char *console_buffer) -{ - char *p = console_buffer; - int n = 0; /* buffer index */ - int plen = strlen (prompt); /* prompt length */ - int col; /* output column cnt */ - char c; - - /* print prompt */ - if (prompt) - printf(prompt); - col = plen; - - for (;;) { - c = getc(); - - switch (c) { - case '\r': /* Enter */ - case '\n': - *p = '\0'; - puts ("\n"); - return (p - console_buffer); - - case 0x03: /* ^C - break */ - console_buffer[0] = '\0'; /* discard input */ - return (-1); - - case 0x08: /* ^H - backspace */ - case 0x7F: /* DEL - backspace */ - if (n) { - --p; - printf(erase_seq); - col--; - n--; - } - continue; - - default: - /* - * Must be a normal character then - */ - if (n < (AT91C_CB_SIZE -2)) - { - ++col; /* echo input */ - putc(c); - *p++ = c; - ++n; - } - else - { /* Buffer full */ - putc('\a'); - } - } - } -} - - -/*----------------------------------------------------------------------------- - * Function Name : AT91F_WaitKeyPressed() - * Object : - * Input Parameters : - * Return value : - *----------------------------------------------------------------------------- - */ -void AT91F_WaitKeyPressed(void) -{ - int c; - puts("KEY"); - c = getc(); - putc('\n'); -} - -int puts(const char *str) -{ - while(*str != 0) { - at91_serial_putc(*str); - str++; - } - return 1; -} - -int putc(int c) -{ - return at91_serial_putc(c); -} - -int putchar(c) -{ - return putc(c); -} - -int getc() -{ - return at91_serial_getc(); -} - -int strlen(const char *str) -{ - int len = 0; - - if(str == (char *)0) - return 0; - - while(*str++ != 0) - len++; - - return len; -} - -#define ZEROPAD 1 /* pad with zero */ -#define SIGN 2 /* unsigned/signed long */ -#define LEFT 4 /* left justified */ -#define LARGE 8 /* use 'ABCDEF' instead of 'abcdef' */ - -#define do_div(n,base) ({ \ - int __res; \ - __res = ((unsigned) n) % (unsigned) base; \ - n = ((unsigned) n) / (unsigned) base; \ - __res; \ -}) - -static int number(int num, int base, int size, - int precision, int type) -{ - char c, sign, tmp[66]; - const char *digits="0123456789ABCDEF"; - int i; - - if (type & LEFT) - type &= ~ZEROPAD; - if (base < 2 || base > 16) - return 0; - c = (type & ZEROPAD) ? '0' : ' '; - sign = 0; - - if(type & SIGN && num < 0) - { - sign = '-'; - num = -num; - size--; - } - - i = 0; - if(num == 0) - tmp[i++] = digits[0]; - else while(num != 0) - tmp[i++] = digits[do_div(num, base)]; - - if(i > precision) - precision = i; - size -= precision; - - if(!(type&(ZEROPAD+LEFT))) - while(size-->0) - putc(' '); - - if(sign) - putc(sign); - - if (!(type & LEFT)) - while (size-- > 0) - putc(c); - - while (i < precision--) - putc('0'); - - while (i-- > 0) - putc(tmp[i]); - - while (size-- > 0) - putc(' ');; - - return 1; -} - -int hvfprintf(const char *fmt, va_list va) -{ - char *s; - - do { - if(*fmt == '%') { - bool done = false; - - int type = 0; - int precision = 0; - - do { - fmt++; - switch(*fmt) { - case '0' : - if(!precision) - type |= ZEROPAD; - case '1' : - case '2' : - case '3' : - case '4' : - case '5' : - case '6' : - case '7' : - case '8' : - case '9' : - precision = precision * 10 + (*fmt - '0'); - break; - case '.' : - break; - case 's' : - s = va_arg(va, char *); - if(!s) - puts("<NULL>"); - else - puts(s); - done = true; - break; - case 'c' : - putc(va_arg(va, int)); - done = true; - break; - case 'd' : - number(va_arg(va, int), 10, 0, precision, type); - done = true; - break; - case 'x' : - case 'X' : - number(va_arg(va, int), 16, 0, precision, type); - done = true; - break; - case '%' : - putc(*fmt); - done = true; - default: - putc('%'); - putc(*fmt); - done = true; - break; - } - } while(!done); - } else if(*fmt == '\\') { - fmt++; - if(*fmt == 'r') { - putc('\r'); - } else if(*fmt == 'n') { - putc('\n'); - } - } else { - putc(*fmt); - } - fmt++; - } while(*fmt != 0); - - return 0; -} - -int printf(const char *fmt, ...) -{ - va_list ap; - int i; - - va_start(ap, fmt); - i = hvfprintf(fmt, ap); - va_end(ap); - - return i; -} diff --git a/target/linux/at91-2.6/image/dfboot/src/com.h b/target/linux/at91-2.6/image/dfboot/src/com.h deleted file mode 100644 index 7af09e4d6d..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/com.h +++ /dev/null @@ -1,28 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : com.h - * Object : - * - * 1.0 27/03/03 HIi : Creation - *---------------------------------------------------------------------------- - */ -#ifndef com_h -#define com_h - -#define AT91C_CB_SIZE 20 /* size of the console buffer */ - -/* Escape sequences */ -#define ESC \033 - -extern int AT91F_ReadLine (const char *const prompt, char *console_buffer); -extern void AT91F_WaitKeyPressed(void); - -#endif - diff --git a/target/linux/at91-2.6/image/dfboot/src/config.h b/target/linux/at91-2.6/image/dfboot/src/config.h deleted file mode 100644 index 3be8d499a0..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/config.h +++ /dev/null @@ -1,17 +0,0 @@ - -#ifndef _CONFIG_H -#define _CONFIG_H - -//#define PAGESZ_1056 1 -#undef PAGESZ_1056 -#define SPI_LOW_SPEED 1 -#define AT91C_DELAY_TO_BOOT 1500 - -#define CRC_RETRIES 0x100 - -#define AT91C_MASTER_CLOCK 59904000 -#define AT91C_BAUD_RATE 115200 - -#define AT91C_ALTERNATE_USART AT91C_BASE_US0 - -#endif diff --git a/target/linux/at91-2.6/image/dfboot/src/cstartup_ram.S b/target/linux/at91-2.6/image/dfboot/src/cstartup_ram.S deleted file mode 100644 index 223900098d..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/cstartup_ram.S +++ /dev/null @@ -1,144 +0,0 @@ -#include "AT91RM9200_inc.h" - -/*--------------------------- -ARM Core Mode and Status Bits ----------------------------*/ -.section start - .text - -#define ARM_MODE_USER 0x10 -#define ARM_MODE_FIQ 0x11 -#define ARM_MODE_IRQ 0x12 -#define ARM_MODE_SVC 0x13 -#define ARM_MODE_ABORT 0x17 -#define ARM_MODE_UNDEF 0x1B -#define ARM_MODE_SYS 0x1F - -#define I_BIT 0x80 -#define F_BIT 0x40 -#define T_BIT 0x20 - -/*---------------------------------------------------------------------------- - Area Definition ----------------- - Must be defined as function to put first in the code as it must be mapped - at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap. -_---------------------------------------------------------------------------*/ - - .align 4 - .globl _start -_start: - -/*---------------------------------------------------------------------------- - Exception vectors ( before Remap ) ------------------------------------- - These vectors are read at address 0. - They absolutely requires to be in relative addresssing mode in order to - guarantee a valid jump. For the moment, all are just looping (what may be - dangerous in a final system). If an exception occurs before remap, this - would result in an infinite loop. -----------------------------------------------------------------------------*/ - b reset /* reset */ - b undefvec /* Undefined Instruction */ - b swivec /* Software Interrupt */ - b pabtvec /* Prefetch Abort */ - b dabtvec /* Data Abort */ - b rsvdvec /* reserved */ - b aicvec /* IRQ : read the AIC */ - b fiqvec /* FIQ */ - -undefvec: -swivec: -pabtvec: -dabtvec: -rsvdvec: -aicvec: -fiqvec: - b undefvec - -reset: - -#define MEMEND 0x00004000 - -/* ---------------------------- - Setup the stack for each mode ----------------------------- */ - -#define IRQ_STACK_SIZE 0x10 -#define FIQ_STACK_SIZE 0x04 -#define ABT_STACK_SIZE 0x04 -#define UND_STACK_SIZE 0x04 -#define SVC_STACK_SIZE 0x10 -#define USER_STACK_SIZE 0x400 - - ldr r0,= MEMEND - -/*- Set up Supervisor Mode and set Supervisor Mode Stack*/ - msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT - mov r13, r0 /* Init stack Undef*/ - sub r0, r0, #SVC_STACK_SIZE - -/*- Set up Interrupt Mode and set IRQ Mode Stack*/ - msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT - mov r13, r0 /* Init stack IRQ*/ - sub r0, r0, #IRQ_STACK_SIZE - -/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/ - msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT - mov r13, r0 /* Init stack FIQ*/ - sub r0, r0, #FIQ_STACK_SIZE - -/*- Set up Abort Mode and set Abort Mode Stack*/ - msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT - mov r13, r0 /* Init stack Abort*/ - sub r0, r0, #ABT_STACK_SIZE - -/*- Set up Undefined Instruction Mode and set Undef Mode Stack*/ - msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT - mov r13, r0 /* Init stack Undef*/ - sub r0, r0, #UND_STACK_SIZE - -/*- Set up user Mode and set System Mode Stack*/ - msr CPSR_c, #ARM_MODE_SYS | I_BIT | F_BIT - bic r0, r0, #3 /* Insure word alignement */ - mov sp, r0 /* Init stack System */ - - - ldr r0, = AT91F_LowLevelInit - mov lr, pc - bx r0 - -/*---------------------------------------- - Read/modify/write CP15 control register -----------------------------------------*/ - mrc p15, 0, r0, c1, c0,0 /* read cp15 control registre (cp15 r1) in r0 */ - ldr r3,= 0xC0000080 /* Reset bit :Little Endian end fast bus mode */ - ldr r4,= 0xC0001000 /* Set bit :Asynchronous clock mode, Not Fast Bus, I-Cache enable */ - bic r0, r0, r3 - orr r0, r0, r4 - mcr p15, 0, r0, c1, c0,0 /* write r0 in cp15 control registre (cp15 r1) */ - -/* Enable interrupts */ - msr CPSR_c, #ARM_MODE_SYS | F_BIT - -/*------------------------------------------------------------------------------ -- Branch on C code Main function (with interworking) ----------------------------------------------------- -- Branch must be performed by an interworking call as either an ARM or Thumb -- _start function must be supported. This makes the code not position- -- independent. A Branch with link would generate errors -----------------------------------------------------------------------------*/ - -/*- Branch to _start by interworking*/ - ldr r4, = main - mov lr, pc - bx r4 - -/*----------------------------------------------------------------------------- -- Loop for ever ---------------- -- End of application. Normally, never occur. -- Could jump on Software Reset ( B 0x0 ). -------------------------------------------------------------------------------*/ -End: - b End diff --git a/target/linux/at91-2.6/image/dfboot/src/dataflash.c b/target/linux/at91-2.6/image/dfboot/src/dataflash.c deleted file mode 100644 index 5e54460b72..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/dataflash.c +++ /dev/null @@ -1,208 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : dataflash.c - * Object : High level functions for the dataflash - * Creation : HIi 10/10/2003 - *---------------------------------------------------------------------------- - */ -#include "config.h" -#include "stdio.h" -#include "dataflash.h" - - -AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; -static AT91S_DataFlash DataFlashInst; - -int cs[][CFG_MAX_DATAFLASH_BANKS] = { - {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ - {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} -}; - -int AT91F_DataflashInit(void) -{ - int i; - int dfcode; - int Nb_device = 0; - - AT91F_SpiInit(); - - for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { - dataflash_info[i].id = 0; - dataflash_info[i].Device.pages_number = 0; - dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc); - - switch (dfcode) { - case AT45DB161: - dataflash_info[i].Device.pages_number = 4096; - dataflash_info[i].Device.pages_size = 528; - dataflash_info[i].Device.page_offset = 10; - dataflash_info[i].Device.byte_mask = 0x300; - dataflash_info[i].Device.cs = cs[i][1]; - dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; - dataflash_info[i].id = dfcode; - Nb_device++; - break; - - case AT45DB321: - dataflash_info[i].Device.pages_number = 8192; - dataflash_info[i].Device.pages_size = 528; - dataflash_info[i].Device.page_offset = 10; - dataflash_info[i].Device.byte_mask = 0x300; - dataflash_info[i].Device.cs = cs[i][1]; - dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; - dataflash_info[i].id = dfcode; - Nb_device++; - break; - - case AT45DB642: - dataflash_info[i].Device.pages_number = 8192; - dataflash_info[i].Device.pages_size = 1056; - dataflash_info[i].Device.page_offset = 11; - dataflash_info[i].Device.byte_mask = 0x700; - dataflash_info[i].Device.cs = cs[i][1]; - dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; - dataflash_info[i].id = dfcode; - Nb_device++; - break; - case AT45DB128: - dataflash_info[i].Device.pages_number = 16384; - dataflash_info[i].Device.pages_size = 1056; - dataflash_info[i].Device.page_offset = 11; - dataflash_info[i].Device.byte_mask = 0x700; - dataflash_info[i].Device.cs = cs[i][1]; - dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; - dataflash_info[i].id = dfcode; - Nb_device++; - break; - default: - break; - } - } - return (Nb_device); -} - - -void AT91F_DataflashPrintInfo(void) -{ - int i; - for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { - if (dataflash_info[i].id != 0) { - printf ("DF:AT45DB"); - switch (dataflash_info[i].id) { - case AT45DB161: - printf ("161"); - break; - - case AT45DB321: - printf ("321"); - break; - - case AT45DB642: - printf ("642"); - break; - case AT45DB128: - printf ("128"); - break; - } - - printf ("\n# PG: %6d\n" - "PG SZ: %6d\n" - "SZ=%8d bytes\n" - "ADDR: %08X\n", - (unsigned int) dataflash_info[i].Device.pages_number, - (unsigned int) dataflash_info[i].Device.pages_size, - (unsigned int) dataflash_info[i].Device.pages_number * - dataflash_info[i].Device.pages_size, - (unsigned int) dataflash_info[i].logical_address); - } - } -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashSelect */ -/* Object : Select the correct device */ -/*------------------------------------------------------------------------------*/ -static AT91PS_DataFlash AT91F_DataflashSelect(AT91PS_DataFlash pFlash, - unsigned int *addr) -{ - char addr_valid = 0; - int i; - - for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) - if ((*addr & 0xFF000000) == dataflash_info[i].logical_address) { - addr_valid = 1; - break; - } - if (!addr_valid) { - pFlash = (AT91PS_DataFlash) 0; - return pFlash; - } - pFlash->pDataFlashDesc = &(dataflash_info[i].Desc); - pFlash->pDevice = &(dataflash_info[i].Device); - *addr -= dataflash_info[i].logical_address; - return (pFlash); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : read_dataflash */ -/* Object : dataflash memory read */ -/*------------------------------------------------------------------------------*/ -int read_dataflash(unsigned long addr, unsigned long size, char *result) -{ - unsigned int AddrToRead = addr; - AT91PS_DataFlash pFlash = &DataFlashInst; - - pFlash = AT91F_DataflashSelect (pFlash, &AddrToRead); - if (pFlash == 0) - return -1; - - return (AT91F_DataFlashRead(pFlash, AddrToRead, size, result)); -} - - -/*-----------------------------------------------------------------------------*/ -/* Function Name : write_dataflash */ -/* Object : write a block in dataflash */ -/*-----------------------------------------------------------------------------*/ -int write_dataflash(unsigned long addr_dest, unsigned int addr_src, - unsigned int size) -{ - unsigned int AddrToWrite = addr_dest; - AT91PS_DataFlash pFlash = &DataFlashInst; - - pFlash = AT91F_DataflashSelect(pFlash, &AddrToWrite); - if (AddrToWrite == -1) - return -1; - - return AT91F_DataFlashWrite(pFlash, (unsigned char *) addr_src, AddrToWrite, size); -} - -/*-----------------------------------------------------------------------------*/ -/* Function Name : erase_dataflash */ -/* Object : Erase entire dataflash */ -/*-----------------------------------------------------------------------------*/ -int erase_dataflash(unsigned long addr_dest) -{ - unsigned int AddrToWrite = addr_dest; - AT91PS_DataFlash pFlash = &DataFlashInst; - - pFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite); - if (AddrToWrite == -1) - return -1; - - return AT91F_DataFlashErase(pFlash); -} - diff --git a/target/linux/at91-2.6/image/dfboot/src/dataflash.h b/target/linux/at91-2.6/image/dfboot/src/dataflash.h deleted file mode 100644 index 8fab63fa9e..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/dataflash.h +++ /dev/null @@ -1,181 +0,0 @@ -//*--------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*--------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*--------------------------------------------------------------------------- -//* File Name : AT91_SpiDataFlash.h -//* Object : Data Flash Atmel Description File -//* Translator : -//* -//* 1.0 03/04/01 HI : Creation -//* -//*--------------------------------------------------------------------------- - -#ifndef _DataFlash_h -#define _DataFlash_h - -/* Max value = 15Mhz to be compliant with the Continuous array read function */ -#ifdef SPI_LOW_SPEED -#define AT91C_SPI_CLK 14976000/4 -#else -#define AT91C_SPI_CLK 14976000 -#endif - -/* AC characteristics */ -/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */ - -#define DATAFLASH_TCSS (0xf << 16) /* 250ns 15/60000000 */ -#define DATAFLASH_TCHS (0x1 << 24) /* 250ns 32*1/60000000 */ - - -#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ - -#define CFG_MAX_DATAFLASH_BANKS 2 -#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 -#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 - -typedef struct { - unsigned long base; /* logical base address for a bank */ - unsigned long size; /* total bank size */ - unsigned long page_count; - unsigned long page_size; - unsigned long id; /* device id */ -} dataflash_info_t; - -typedef unsigned int AT91S_DataFlashStatus; - -/*----------------------------------------------------------------------*/ -/* DataFlash Structures */ -/*----------------------------------------------------------------------*/ - -/*---------------------------------------------*/ -/* DataFlash Descriptor Structure Definition */ -/*---------------------------------------------*/ -typedef struct _AT91S_DataflashDesc { - unsigned char *tx_cmd_pt; - unsigned int tx_cmd_size; - unsigned char *rx_cmd_pt; - unsigned int rx_cmd_size; - unsigned char *tx_data_pt; - unsigned int tx_data_size; - unsigned char *rx_data_pt; - unsigned int rx_data_size; - volatile unsigned char DataFlash_state; - unsigned char command[8]; -} AT91S_DataflashDesc, *AT91PS_DataflashDesc; - -/*---------------------------------------------*/ -/* DataFlash device definition structure */ -/*---------------------------------------------*/ -typedef struct _AT91S_Dataflash { - int pages_number; /* dataflash page number */ - int pages_size; /* dataflash page size */ - int page_offset; /* page offset in command */ - int byte_mask; /* byte mask in command */ - int cs; -} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures; - - -/*---------------------------------------------*/ -/* DataFlash Structure Definition */ -/*---------------------------------------------*/ -typedef struct _AT91S_DataFlash { - AT91PS_DataflashDesc pDataFlashDesc; /* dataflash descriptor */ - AT91PS_DataflashFeatures pDevice; /* Pointer on a dataflash features array */ -} AT91S_DataFlash, *AT91PS_DataFlash; - - -typedef struct _AT91S_DATAFLASH_INFO { - - AT91S_DataflashDesc Desc; - AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */ - unsigned long logical_address; - unsigned int id; /* device id */ -} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO; - - -/*-------------------------------------------------------------------------------------------------*/ - -#define AT45DB161 0x2c -#define AT45DB321 0x34 -#define AT45DB642 0x3c -#define AT45DB128 0x10 - -#define AT91C_DATAFLASH_TIMEOUT 20000 /* For AT91F_DataFlashWaitReady */ - -/* DataFlash return value */ -#define AT91C_DATAFLASH_BUSY 0x00 -#define AT91C_DATAFLASH_OK 0x01 -#define AT91C_DATAFLASH_ERROR 0x02 -#define AT91C_DATAFLASH_MEMORY_OVERFLOW 0x03 -#define AT91C_DATAFLASH_BAD_COMMAND 0x04 -#define AT91C_DATAFLASH_BAD_ADDRESS 0x05 - - -/* Driver State */ -#define IDLE 0x0 -#define BUSY 0x1 -#define ERROR 0x2 - -/* DataFlash Driver State */ -#define GET_STATUS 0x0F - -/*-------------------------------------------------------------------------------------------------*/ -/* Command Definition */ -/*-------------------------------------------------------------------------------------------------*/ - -/* READ COMMANDS */ -#define DB_CONTINUOUS_ARRAY_READ 0xE8 /* Continuous array read */ -#define DB_BURST_ARRAY_READ 0xE8 /* Burst array read */ -#define DB_PAGE_READ 0xD2 /* Main memory page read */ -#define DB_BUF1_READ 0xD4 /* Buffer 1 read */ -#define DB_BUF2_READ 0xD6 /* Buffer 2 read */ -#define DB_STATUS 0xD7 /* Status Register */ - -/* PROGRAM and ERASE COMMANDS */ -#define DB_BUF1_WRITE 0x84 /* Buffer 1 write */ -#define DB_BUF2_WRITE 0x87 /* Buffer 2 write */ -#define DB_BUF1_PAGE_ERASE_PGM 0x83 /* Buffer 1 to main memory page program with built-In erase */ -#define DB_BUF1_PAGE_ERASE_FASTPGM 0x93 /* Buffer 1 to main memory page program with built-In erase, Fast program */ -#define DB_BUF2_PAGE_ERASE_PGM 0x86 /* Buffer 2 to main memory page program with built-In erase */ -#define DB_BUF2_PAGE_ERASE_FASTPGM 0x96 /* Buffer 1 to main memory page program with built-In erase, Fast program */ -#define DB_BUF1_PAGE_PGM 0x88 /* Buffer 1 to main memory page program without built-In erase */ -#define DB_BUF1_PAGE_FASTPGM 0x98 /* Buffer 1 to main memory page program without built-In erase, Fast program */ -#define DB_BUF2_PAGE_PGM 0x89 /* Buffer 2 to main memory page program without built-In erase */ -#define DB_BUF2_PAGE_FASTPGM 0x99 /* Buffer 1 to main memory page program without built-In erase, Fast program */ -#define DB_PAGE_ERASE 0x81 /* Page Erase */ -#define DB_BLOCK_ERASE 0x50 /* Block Erase */ -#define DB_PAGE_PGM_BUF1 0x82 /* Main memory page through buffer 1 */ -#define DB_PAGE_FASTPGM_BUF1 0x92 /* Main memory page through buffer 1, Fast program */ -#define DB_PAGE_PGM_BUF2 0x85 /* Main memory page through buffer 2 */ -#define DB_PAGE_FastPGM_BUF2 0x95 /* Main memory page through buffer 2, Fast program */ - -/* ADDITIONAL COMMANDS */ -#define DB_PAGE_2_BUF1_TRF 0x53 /* Main memory page to buffer 1 transfert */ -#define DB_PAGE_2_BUF2_TRF 0x55 /* Main memory page to buffer 2 transfert */ -#define DB_PAGE_2_BUF1_CMP 0x60 /* Main memory page to buffer 1 compare */ -#define DB_PAGE_2_BUF2_CMP 0x61 /* Main memory page to buffer 2 compare */ -#define DB_AUTO_PAGE_PGM_BUF1 0x58 /* Auto page rewrite throught buffer 1 */ -#define DB_AUTO_PAGE_PGM_BUF2 0x59 /* Auto page rewrite throught buffer 2 */ - -/*-------------------------------------------------------------------------------------------------*/ - -extern AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; - -extern void AT91F_SpiInit(void); -extern int AT91F_DataflashProbe(int i, AT91PS_DataflashDesc pDesc); -extern int AT91F_DataFlashRead(AT91PS_DataFlash, unsigned long , unsigned long, char *); -extern AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash ,unsigned char *, int, int); -extern AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash); -extern int AT91F_DataflashInit(void); -extern void AT91F_DataflashPrintInfo(void); -extern int read_dataflash(unsigned long addr, unsigned long size, char *result); -extern int write_dataflash(unsigned long addr_dest, unsigned int addr_src, unsigned int size); -extern int erase_dataflash(unsigned long addr_dest); - -#endif diff --git a/target/linux/at91-2.6/image/dfboot/src/div0.c b/target/linux/at91-2.6/image/dfboot/src/div0.c deleted file mode 100644 index d6fd90ec31..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/div0.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Replacement (=dummy) for GNU/Linux division-by zero handler */ -void __div0 (void) -{ - while(-1); -} diff --git a/target/linux/at91-2.6/image/dfboot/src/elf32-littlearm.lds b/target/linux/at91-2.6/image/dfboot/src/elf32-littlearm.lds deleted file mode 100644 index 4d4efb6ad8..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/elf32-littlearm.lds +++ /dev/null @@ -1,19 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : { *(.text) } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .bss : { *(.bss) } -}
\ No newline at end of file diff --git a/target/linux/at91-2.6/image/dfboot/src/embedded_services.h b/target/linux/at91-2.6/image/dfboot/src/embedded_services.h deleted file mode 100644 index 956b9edf06..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/embedded_services.h +++ /dev/null @@ -1,500 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : embedded_sevices.h -//* Object : Header File with all the embedded software services definitions -//* -//* 1.0 24 Jan 2003 FB : Creation -//*---------------------------------------------------------------------------- -#ifndef embedded_sevices_h -#define embedded_sevices_h - -#include "AT91RM9200.h" - -#define AT91C_BASE_ROM (char *)0x00100000 - -/* Return values */ -#define AT91C_BUFFER_SUCCESS 0 -#define AT91C_BUFFER_ERROR_SHIFT 16 -#define AT91C_BUFFER_ERROR (0x0F << AT91C_BUFFER_ERROR_SHIFT) - -#define AT91C_BUFFER_OVERFLOW (0x01 << AT91C_BUFFER_ERROR_SHIFT) -#define AT91C_BUFFER_UNDERRUN (0x02 << AT91C_BUFFER_ERROR_SHIFT) - -typedef unsigned int AT91S_BufferStatus; - -struct _AT91S_Pipe; - -// This structure is a virtual object of a buffer -typedef struct _AT91S_Buffer -{ - struct _AT91S_Pipe *pPipe; - void *pChild; - - // Functions invoked by the pipe - AT91S_BufferStatus (*SetRdBuffer) (struct _AT91S_Buffer *pSBuffer, char *pBuffer, unsigned int Size); - AT91S_BufferStatus (*SetWrBuffer) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer, unsigned int Size); - AT91S_BufferStatus (*RstRdBuffer) (struct _AT91S_Buffer *pSBuffer); - AT91S_BufferStatus (*RstWrBuffer) (struct _AT91S_Buffer *pSBuffer); - char (*MsgWritten) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer); - char (*MsgRead) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer); - // Functions invoked by the peripheral - AT91S_BufferStatus (*GetWrBuffer) (struct _AT91S_Buffer *pSBuffer, char const **pData, unsigned int *pSize); - AT91S_BufferStatus (*GetRdBuffer) (struct _AT91S_Buffer *pSBuffer, char **pData, unsigned int *pSize); - AT91S_BufferStatus (*EmptyWrBuffer) (struct _AT91S_Buffer *pSBuffer, unsigned int size); - AT91S_BufferStatus (*FillRdBuffer) (struct _AT91S_Buffer *pSBuffer, unsigned int size); - char (*IsWrEmpty) (struct _AT91S_Buffer *pSBuffer); - char (*IsRdFull) (struct _AT91S_Buffer *pSBuffer); -} AT91S_Buffer, *AT91PS_Buffer; - -// =========================================================================================== -// SimpleBuffer definition -// -// This structure is pointed by pRealBuffer field in the SBuffer -// It contains usefull information for a real implementation of -// a SBuffer object. -// The application just create an instance of SSBUffer and SBuffer, -// call OpenSimpleBuffer, and continue using SBuffer instance - -typedef struct _AT91S_SBuffer -{ - AT91S_Buffer parent; - char *pRdBuffer; - char const *pWrBuffer; - unsigned int szRdBuffer; - unsigned int szWrBuffer; - unsigned int stRdBuffer; - unsigned int stWrBuffer; -} AT91S_SBuffer, *AT91PS_SBuffer; - -typedef AT91PS_Buffer (*AT91PF_OpenSBuffer) (AT91PS_SBuffer); - -// This function is called by the application -extern AT91PS_Buffer AT91F_OpenSBuffer(AT91PS_SBuffer pBuffer); - -// Functions invoked by the pipe -extern AT91S_BufferStatus AT91F_SbSetRdBuffer (AT91PS_Buffer pBuffer, char *pData, unsigned int Size); -extern AT91S_BufferStatus AT91F_SbSetWrBuffer (AT91PS_Buffer pBuffer, char const *pData, unsigned int Size); -extern AT91S_BufferStatus AT91F_SbRstRdBuffer (AT91PS_Buffer pBuffer); -extern AT91S_BufferStatus AT91F_SbRstWrBuffer (AT91PS_Buffer pBuffer); -extern char AT91F_SbMsgWritten (AT91PS_Buffer pBuffer, char const *pMsg); -extern char AT91F_SbMsgRead (AT91PS_Buffer pBuffer, char const *pMsg); -// Functions invoked by the peripheral -extern AT91S_BufferStatus AT91F_SbGetWrBuffer (AT91PS_Buffer pBuffer, char const **pData, unsigned int *pSize); -extern AT91S_BufferStatus AT91F_SbGetRdBuffer (AT91PS_Buffer pBuffer, char **pData, unsigned int *pSize); -extern AT91S_BufferStatus AT91F_SbEmptyWrBuffer(AT91PS_Buffer pBuffer, unsigned int size); -extern AT91S_BufferStatus AT91F_SbFillRdBuffer (AT91PS_Buffer pBuffer, unsigned int size); -extern char AT91F_SbIsWrEmpty (AT91PS_Buffer pBuffer); -extern char AT91F_SbIsRdFull (AT91PS_Buffer pBuffer); - -#ifdef DBG_DRV_BUFFER -extern char const *AT91F_SbGetError(AT91S_BufferStatus errorNumber); -#endif - - -#define AT91C_OPEN_CTRLTEMPO_SUCCESS 0 -#define AT91C_ERROR_OPEN_CTRLTEMPO 1 -#define AT91C_START_OK 2 -#define AT91C_STOP_OK 3 -#define AT91C_TIMEOUT_REACHED 4 - -typedef enum _AT91E_SvcTempo { - AT91E_SVCTEMPO_DIS, - AT91E_SVCTEMPO_EN -} AT91E_SvcTempo; - -typedef unsigned int AT91S_TempoStatus; - -// AT91S_SvcTempo -typedef struct _AT91S_SvcTempo -{ - - // Methods: - AT91S_TempoStatus (*Start) ( - struct _AT91S_SvcTempo *pSvc, - unsigned int timeout, - unsigned int reload, - void (*callback) (AT91S_TempoStatus, void *), - void *pData); - AT91S_TempoStatus (*Stop) (struct _AT91S_SvcTempo *pSvc); - - struct _AT91S_SvcTempo *pPreviousTempo; - struct _AT91S_SvcTempo *pNextTempo; - - // Data - unsigned int TickTempo; //* timeout value - unsigned int ReloadTempo;//* Reload value for periodic execution - void (*TempoCallback)(AT91S_TempoStatus, void *); - void *pPrivateData; - AT91E_SvcTempo flag; -} AT91S_SvcTempo, *AT91PS_SvcTempo; - - -// AT91S_CtrlTempo -typedef struct _AT91S_CtlTempo -{ - // Members: - - // Start and stop for Timer hardware - AT91S_TempoStatus (*CtlTempoStart) (void *pTimer); - AT91S_TempoStatus (*CtlTempoStop) (void *pTimer); - - // Start and stop for Tempo service - AT91S_TempoStatus (*SvcTempoStart) ( - struct _AT91S_SvcTempo *pSvc, - unsigned int timeout, - unsigned int reload, - void (*callback) (AT91S_TempoStatus, void *), - void *pData); - AT91S_TempoStatus (*SvcTempoStop) (struct _AT91S_SvcTempo *pSvc); - AT91S_TempoStatus (*CtlTempoSetTime)(struct _AT91S_CtlTempo *pCtrl, unsigned int NewTime); - AT91S_TempoStatus (*CtlTempoGetTime)(struct _AT91S_CtlTempo *pCtrl); - AT91S_TempoStatus (*CtlTempoIsStart)(struct _AT91S_CtlTempo *pCtrl); - AT91S_TempoStatus (*CtlTempoCreate) ( - struct _AT91S_CtlTempo *pCtrl, - struct _AT91S_SvcTempo *pTempo); - AT91S_TempoStatus (*CtlTempoRemove) ( - struct _AT91S_CtlTempo *pCtrl, - struct _AT91S_SvcTempo *pTempo); - AT91S_TempoStatus (*CtlTempoTick) (struct _AT91S_CtlTempo *pCtrl); - - // Data: - - void *pPrivateData; // Pointer to devived class - void const *pTimer; // hardware - AT91PS_SvcTempo pFirstTempo; - AT91PS_SvcTempo pNewTempo; -} AT91S_CtlTempo, *AT91PS_CtlTempo; -typedef AT91S_TempoStatus (*AT91PF_OpenCtlTempo) ( AT91PS_CtlTempo, void const *); - -// This function is called by the application. -extern AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtrlTempo, void const *pTempoTimer ); - -extern AT91S_TempoStatus AT91F_STStart (void *); -extern AT91S_TempoStatus AT91F_STStop (void *); -extern AT91S_TempoStatus AT91F_STSetTime (AT91PS_CtlTempo, unsigned int); -extern AT91S_TempoStatus AT91F_STGetTime (AT91PS_CtlTempo); -extern AT91S_TempoStatus AT91F_STIsStart (AT91PS_CtlTempo); -extern AT91S_TempoStatus AT91F_CtlTempoCreate (AT91PS_CtlTempo, AT91PS_SvcTempo); -extern AT91S_TempoStatus AT91F_CtlTempoRemove (AT91PS_CtlTempo, AT91PS_SvcTempo); -extern AT91S_TempoStatus AT91F_CtlTempoTick (AT91PS_CtlTempo); -extern AT91S_TempoStatus AT91F_SvcTempoStart ( - AT91PS_SvcTempo pSvc, - unsigned int timeout, - unsigned int reload, - void (*callback) (AT91S_TempoStatus, void *), - void *pData); -extern AT91S_TempoStatus AT91F_SvcTempoStop (AT91PS_SvcTempo); - - -// Following types are defined in another header files -struct _AT91S_Buffer; - -// Constants: -#define AT91C_COMMSVC_SUCCESS 0 -#define AT91C_COMMSVC_ERROR_SHIFT 8 -#define AT91C_COMMSVC_ERROR (0x0f << AT91C_COMMSVC_ERROR_SHIFT) - -typedef unsigned int AT91S_SvcCommStatus; - -// AT91S_Service definition -// This structure is an abstraction of a communication peripheral -typedef struct _AT91S_Service -{ - // Methods: - AT91S_SvcCommStatus (*Reset) (struct _AT91S_Service *pService); - AT91S_SvcCommStatus (*StartTx)(struct _AT91S_Service *pService); - AT91S_SvcCommStatus (*StartRx)(struct _AT91S_Service *pService); - AT91S_SvcCommStatus (*StopTx) (struct _AT91S_Service *pService); - AT91S_SvcCommStatus (*StopRx) (struct _AT91S_Service *pService); - char (*TxReady)(struct _AT91S_Service *pService); - char (*RxReady)(struct _AT91S_Service *pService); - // Data: - struct _AT91S_Buffer *pBuffer; // Link to a buffer object - void *pChild; -} AT91S_SvcComm, *AT91PS_SvcComm; - -// Constants: -#define AT91C_XMODEM_SOH 0x01 /* Start of Heading for 128 bytes */ -#define AT91C_XMODEM_STX 0x02 /* Start of heading for 1024 bytes */ -#define AT91C_XMODEM_EOT 0x04 /* End of transmission */ -#define AT91C_XMODEM_ACK 0x06 /* Acknowledge */ -#define AT91C_XMODEM_NAK 0x15 /* Negative Acknowledge */ -#define AT91C_XMODEM_CRCCHR 'C' - -#define AT91C_XMODEM_PACKET_SIZE 2 // packet + packetCRC -#define AT91C_XMODEM_CRC_SIZE 2 // crcLSB + crcMSB -#define AT91C_XMODEM_DATA_SIZE_SOH 128 // data 128 corresponding to SOH header -#define AT91C_XMODEM_DATA_SIZE_STX 1024 // data 1024 corresponding to STX header - -//* Following structure is used by SPipe to refer to the USB device peripheral endpoint -typedef struct _AT91PS_SvcXmodem { - - // Public Methods: - AT91S_SvcCommStatus (*Handler) (struct _AT91PS_SvcXmodem *, unsigned int); - AT91S_SvcCommStatus (*StartTx) (struct _AT91PS_SvcXmodem *, unsigned int); - AT91S_SvcCommStatus (*StopTx) (struct _AT91PS_SvcXmodem *, unsigned int); - - // Private Methods: - AT91S_SvcCommStatus (*ReadHandler) (struct _AT91PS_SvcXmodem *, unsigned int csr); - AT91S_SvcCommStatus (*WriteHandler) (struct _AT91PS_SvcXmodem *, unsigned int csr); - unsigned short (*GetCrc) (char *ptr, unsigned int count); - char (*CheckHeader) (unsigned char currentPacket, char *packet); - char (*CheckData) (struct _AT91PS_SvcXmodem *); - - AT91S_SvcComm parent; // Base class - AT91PS_USART pUsart; - - AT91S_SvcTempo tempo; // Link to a AT91S_Tempo object - - char *pData; - unsigned int dataSize; // = XMODEM_DATA_STX or XMODEM_DATA_SOH - char packetDesc[AT91C_XMODEM_PACKET_SIZE]; - unsigned char packetId; // Current packet - char packetStatus; - char isPacketDesc; - char eot; // end of transmition -} AT91S_SvcXmodem, *AT91PS_SvcXmodem; - -typedef AT91PS_SvcComm (*AT91PF_OpenSvcXmodem) ( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo); - -// This function is called by the application. -extern AT91PS_SvcComm AT91F_OpenSvcXmodem( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo); - -extern unsigned short AT91F_SvcXmodemGetCrc (char *ptr, unsigned int count); -extern char AT91F_SvcXmodemCheckHeader(unsigned char currentPacket, char *packet); -extern char AT91F_SvcXmodemCheckData (AT91PS_SvcXmodem pSvcXmodem); -extern AT91S_SvcCommStatus AT91F_SvcXmodemReadHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr); -extern AT91S_SvcCommStatus AT91F_SvcXmodemWriteHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr); -extern AT91S_SvcCommStatus AT91F_SvcXmodemStartTx(AT91PS_SvcComm pSvcComm); -extern AT91S_SvcCommStatus AT91F_SvcXmodemStopTx(AT91PS_SvcComm pSvcComm); -extern AT91S_SvcCommStatus AT91F_SvcXmodemStartRx(AT91PS_SvcComm pSvcComm); -extern AT91S_SvcCommStatus AT91F_SvcXmodemStopRx(AT91PS_SvcComm pSvcComm); -extern char AT91F_SvcXmodemTxReady(AT91PS_SvcComm pService); -extern char AT91F_SvcXmodemRxReady(AT91PS_SvcComm pSvcComm); - - -// Constants: -#define AT91C_PIPE_SUCCESS 0 -#define AT91C_PIPE_ERROR_SHIFT 8 -#define AT91C_PIPE_ERROR (0x0F << AT91C_PIPE_ERROR_SHIFT) - -#define AT91C_PIPE_OPEN_FAILED (1 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_WRITE_FAILED (2 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_WRITE_ABORTED (3 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_READ_FAILED (4 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_READ_ABORTED (5 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_ABORT_FAILED (6 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_RESET_FAILED (7 << AT91C_PIPE_ERROR_SHIFT) - -/* _AT91S_Pipe stucture */ -typedef unsigned int AT91S_PipeStatus; - -typedef struct _AT91S_Pipe -{ - // A pipe is linked with a peripheral and a buffer - AT91PS_SvcComm pSvcComm; - AT91PS_Buffer pBuffer; - - // Callback functions with their arguments - void (*WriteCallback) (AT91S_PipeStatus, void *); - void (*ReadCallback) (AT91S_PipeStatus, void *); - void *pPrivateReadData; - void *pPrivateWriteData; - - // Pipe methods - AT91S_PipeStatus (*Write) ( - struct _AT91S_Pipe *pPipe, - char const * pData, - unsigned int size, - void (*callback) (AT91S_PipeStatus, void *), - void *privateData); - AT91S_PipeStatus (*Read) ( - struct _AT91S_Pipe *pPipe, - char *pData, - unsigned int size, - void (*callback) (AT91S_PipeStatus, void *), - void *privateData); - AT91S_PipeStatus (*AbortWrite) ( - struct _AT91S_Pipe *pPipe); - AT91S_PipeStatus (*AbortRead) ( - struct _AT91S_Pipe *pPipe); - AT91S_PipeStatus (*Reset) ( - struct _AT91S_Pipe *pPipe); - char (*IsWritten) ( - struct _AT91S_Pipe *pPipe, - char const *pVoid); - char (*IsReceived) ( - struct _AT91S_Pipe *pPipe, - char const *pVoid); -} AT91S_Pipe, *AT91PS_Pipe; - -// types used in AT91S_Pipe -typedef AT91PS_Pipe (*AT91PF_OpenPipe) (AT91PS_Pipe, AT91PS_SvcComm, AT91PS_Buffer); -typedef void (*AT91PF_PipeWriteCallBack) (AT91S_PipeStatus, void *); -typedef void (*AT91PF_PipeReadCallBack) (AT91S_PipeStatus, void *); -typedef AT91S_PipeStatus (*AT91PF_PipeWrite) (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *), void *); -typedef AT91S_PipeStatus (*AT91PF_PipeRead) (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *), void *); -typedef AT91S_PipeStatus (*AT91PF_PipeAbortWrite) (AT91PS_Pipe); -typedef AT91S_PipeStatus (*AT91PF_PipeAbortRead) (AT91PS_Pipe); -typedef AT91S_PipeStatus (*AT91PF_PipeReset) (AT91PS_Pipe); -typedef char (*AT91PF_PipeIsWritten) (AT91PS_Pipe, char const *); -typedef char (*AT91PF_PipeIsReceived) (AT91PS_Pipe, char const *); - -// This function is called by the application -extern AT91PS_Pipe AT91F_OpenPipe( - AT91PS_Pipe pPipe, - AT91PS_SvcComm pSvcComm, - AT91PS_Buffer pBuffer); - -// Following functions are called through AT91S_Pipe pointers - -extern AT91S_PipeStatus AT91F_PipeWrite( - AT91PS_Pipe pPipe, - char const *pVoid, - unsigned int size, - AT91PF_PipeWriteCallBack callback, - void *privateData); -extern AT91S_PipeStatus AT91F_PipeRead( - AT91PS_Pipe pPipe, - char *pVoid, - unsigned int Size, - AT91PF_PipeReadCallBack callback, - void *privateData); -extern AT91S_PipeStatus AT91F_PipeAbortWrite(AT91PS_Pipe pPipe); -extern AT91S_PipeStatus AT91F_PipeAbortRead(AT91PS_Pipe pPipe); -extern AT91S_PipeStatus AT91F_PipeReset(AT91PS_Pipe pPipe); -extern char AT91F_PipeMsgWritten(AT91PS_Pipe pPipe, char const *pVoid); -extern char AT91F_PipeMsgReceived(AT91PS_Pipe pPipe, char const *pVoid); - -#ifdef DBG_DRV_PIPE -// This function parse the error number and return a string -// describing the error message -extern char const *AT91F_PipeGetError(AT91S_PipeStatus msgId); -#endif - -extern const unsigned char bit_rev[256]; - -extern void CalculateCrc32(const unsigned char *,unsigned int, unsigned int *); -extern void CalculateCrc16(const unsigned char *, unsigned int , unsigned short *); -extern void CalculateCrcHdlc(const unsigned char *, unsigned int, unsigned short *); -extern void CalculateCrc16ccitt(const unsigned char *, unsigned int , unsigned short *); - -typedef const unsigned char* AT91PS_SVC_CRC_BIT_REV ; - -typedef void (*AT91PF_SVC_CRC32) (const unsigned char *, unsigned int, unsigned int *); -typedef void (*AT91PF_SVC_CRC16) (const unsigned char *, unsigned int, unsigned short *); -typedef void (*AT91PF_SVC_CRCHDLC) (const unsigned char *, unsigned int, unsigned short *); -typedef void (*AT91PF_SVC_CRCCCITT)(const unsigned char *, unsigned int , unsigned short *); - - -typedef short (*AT91PF_Sinus) (int angle); -typedef const short * AT91PS_SINE_TAB; - -extern short AT91F_Sinus(int angle); -extern const short AT91C_SINUS180_TAB[256]; - - -typedef void (TypeAICHandler) (void) ; - - -// ROM BOOT Structure Element Definition (liv v2) -typedef struct _AT91S_MEMCDesc -{ - AT91PS_MC memc_base ; /* Peripheral base */ - unsigned char periph_id ; /* MC Peripheral Identifier */ -} AT91S_MEMCDesc, *AT91PS_MEMCDesc ; - -typedef struct _AT91S_Pio2Desc -{ - AT91PS_PIO pio_base ; /* Base Address */ - unsigned char periph_id ; /* Peripheral Identifier */ - unsigned char pio_number ; /* Total Pin Number */ -} AT91S_Pio2Desc, *AT91PS_Pio2Desc ; - -typedef struct _AT91S_SPIDesc -{ - AT91PS_SPI spi_base ; - const AT91PS_PIO pio_base ; - unsigned char periph_id ; - unsigned char pin_spck ; - unsigned char pin_miso ; - unsigned char pin_mosi ; - unsigned char pin_npcs[4] ; -} AT91S_SPIDesc, *AT91PS_SPIDesc ; - -typedef struct _AT91S_USART2Desc -{ - AT91PS_USART usart_base ; /* Peripheral base */ - const AT91PS_PIO pio_base ; /* IO controller descriptor */ - unsigned int pin_rxd ; /* RXD pin number in the PIO */ - unsigned int pin_txd ; /* TXD pin number in the PIO */ - unsigned int pin_sck ; /* SCK pin number in the PIO */ - unsigned int pin_rts ; /* RTS pin number in the PIO */ - unsigned int pin_cts ; /* CTS pin number in the PIO */ - unsigned int pin_dtr ; /* DTR pin number in the PIO */ - unsigned int pin_ri ; /* RI pin number in the PIO */ - unsigned int pin_dsr ; /* DSR pin number in the PIO */ - unsigned int pin_dcd ; /* DCD pin number in the PIO */ - unsigned int periph_id ; /* USART Peripheral Identifier */ -} AT91S_USART2Desc, *AT91PS_USART2Desc ; - -typedef struct _AT91S_TWIDesc -{ - AT91PS_TWI TWI_base ; - const AT91PS_PIO pio_base ; - unsigned int pin_sck ; - unsigned int pin_sda ; - unsigned int periph_id; -}AT91S_TWIDesc, *AT91PS_TWIDesc; - -typedef struct _AT91S_STDesc -{ - AT91PS_ST st_base ; /* Peripheral base address */ - TypeAICHandler *AsmSTHandler ; /* Assembly interrupt handler */ - unsigned char PeriphId ; /* Peripheral Identifier */ -} AT91S_STDesc, *AT91PS_STDesc; - -typedef struct _AT91S_RomBoot { - const unsigned int version; - // Peripheral descriptors - const AT91S_MEMCDesc MEMC_DESC; - const AT91S_STDesc SYSTIMER_DESC; - const AT91S_Pio2Desc PIOA_DESC; - const AT91S_Pio2Desc PIOB_DESC; - const AT91S_USART2Desc DBGU_DESC; - const AT91S_USART2Desc USART0_DESC; - const AT91S_USART2Desc USART1_DESC; - const AT91S_USART2Desc USART2_DESC; - const AT91S_USART2Desc USART3_DESC; - const AT91S_TWIDesc TWI_DESC; - const AT91S_SPIDesc SPI_DESC; - - // Objects entry - const AT91PF_OpenPipe OpenPipe; - const AT91PF_OpenSBuffer OpenSBuffer; - const unsigned int reserved1; - const AT91PF_OpenSvcXmodem OpenSvcXmodem; - const AT91PF_OpenCtlTempo OpenCtlTempo; - const unsigned int reserved2; - const unsigned int reserved3; - const unsigned int reserved4; - const AT91PF_SVC_CRC16 CRC16; - const AT91PF_SVC_CRCCCITT CRCCCITT; - const AT91PF_SVC_CRCHDLC CRCHDLC; - const AT91PF_SVC_CRC32 CRC32; - const AT91PS_SVC_CRC_BIT_REV Bit_Reverse_Array; - const AT91PS_SINE_TAB SineTab; - const AT91PF_Sinus Sine; -} AT91S_RomBoot, *AT91PS_RomBoot; - -#define AT91C_ROM_BOOT_ADDRESS ((const AT91S_RomBoot *) ( *((unsigned int *) (AT91C_BASE_ROM + 0x20))) ) - -#endif - diff --git a/target/linux/at91-2.6/image/dfboot/src/include/AT91C_MCI_Device.h b/target/linux/at91-2.6/image/dfboot/src/include/AT91C_MCI_Device.h deleted file mode 100644 index 43d5835234..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/include/AT91C_MCI_Device.h +++ /dev/null @@ -1,379 +0,0 @@ -//*--------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*--------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*--------------------------------------------------------------------------- -//* File Name : AT91C_MCI_Device.h -//* Object : Data Flash Atmel Description File -//* Translator : -//* -//* 1.0 26/11/02 FB : Creation -//*--------------------------------------------------------------------------- - -#ifndef AT91C_MCI_Device_h -#define AT91C_MCI_Device_h - -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" - -typedef unsigned int AT91S_MCIDeviceStatus; - -///////////////////////////////////////////////////////////////////////////////////////////////////// - -#define AT91C_CARD_REMOVED 0 -#define AT91C_MMC_CARD_INSERTED 1 -#define AT91C_SD_CARD_INSERTED 2 - -#define AT91C_NO_ARGUMENT 0x0 - -#define AT91C_FIRST_RCA 0xCAFE -#define AT91C_MAX_MCI_CARDS 10 - -#define AT91C_BUS_WIDTH_1BIT 0x00 -#define AT91C_BUS_WIDTH_4BITS 0x02 - -/* Driver State */ -#define AT91C_MCI_IDLE 0x0 -#define AT91C_MCI_TIMEOUT_ERROR 0x1 -#define AT91C_MCI_RX_SINGLE_BLOCK 0x2 -#define AT91C_MCI_RX_MULTIPLE_BLOCK 0x3 -#define AT91C_MCI_RX_STREAM 0x4 -#define AT91C_MCI_TX_SINGLE_BLOCK 0x5 -#define AT91C_MCI_TX_MULTIPLE_BLOCK 0x6 -#define AT91C_MCI_TX_STREAM 0x7 - -/* TimeOut */ -#define AT91C_TIMEOUT_CMDRDY 30 - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// MMC & SDCard Structures -///////////////////////////////////////////////////////////////////////////////////////////////////// - -/*-----------------------------------------------*/ -/* SDCard Device Descriptor Structure Definition */ -/*-----------------------------------------------*/ -typedef struct _AT91S_MciDeviceDesc -{ - volatile unsigned char state; - unsigned char SDCard_bus_width; - -} AT91S_MciDeviceDesc, *AT91PS_MciDeviceDesc; - -/*---------------------------------------------*/ -/* MMC & SDCard Structure Device Features */ -/*---------------------------------------------*/ -typedef struct _AT91S_MciDeviceFeatures -{ - unsigned char Card_Inserted; // (0=AT91C_CARD_REMOVED) (1=AT91C_MMC_CARD_INSERTED) (2=AT91C_SD_CARD_INSERTED) - unsigned int Relative_Card_Address; // RCA - unsigned int Max_Read_DataBlock_Length; // 2^(READ_BL_LEN) in CSD - unsigned int Max_Write_DataBlock_Length; // 2^(WRITE_BL_LEN) in CSD - unsigned char Read_Partial; // READ_BL_PARTIAL - unsigned char Write_Partial; // WRITE_BL_PARTIAL - unsigned char Erase_Block_Enable; // ERASE_BLK_EN - unsigned char Read_Block_Misalignment; // READ_BLK_MISALIGN - unsigned char Write_Block_Misalignment; // WRITE_BLK_MISALIGN - unsigned char Sector_Size; // SECTOR_SIZE - unsigned int Memory_Capacity; // Size in bits of the device - -} AT91S_MciDeviceFeatures, *AT91PS_MciDeviceFeatures ; - -/*---------------------------------------------*/ -/* MCI Device Structure Definition */ -/*---------------------------------------------*/ -typedef struct _AT91S_MciDevice -{ - AT91PS_MciDeviceDesc pMCI_DeviceDesc; // MCI device descriptor - AT91PS_MciDeviceFeatures pMCI_DeviceFeatures;// Pointer on a MCI device features array -}AT91S_MciDevice, *AT91PS_MciDevice; - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// MCI_CMD Register Value -///////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_POWER_ON_INIT (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_INIT | AT91C_MCI_OPDCMD) - -///////////////////////////////////////////////////////////////// -// Class 0 & 1 commands: Basic commands and Read Stream commands -///////////////////////////////////////////////////////////////// - -#define AT91C_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE ) -#define AT91C_MMC_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_OPDCMD) -#define AT91C_MMC_SEND_OP_COND_CMD (1 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD) -#define AT91C_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 ) -#define AT91C_MMC_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_OPDCMD) -#define AT91C_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_MMC_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT | AT91C_MCI_OPDCMD) - -#define AT91C_SET_DSR_CMD (4 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_NO | AT91C_MCI_MAXLAT ) // no tested - -#define AT91C_SEL_DESEL_CARD_CMD (7 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_SEND_CSD_CMD (9 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT ) -#define AT91C_SEND_CID_CMD (10 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT ) -#define AT91C_MMC_READ_DAT_UNTIL_STOP_CMD (11 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT ) - -#define AT91C_STOP_TRANSMISSION_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_STOP_TRANSMISSION_SYNC_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_SYNC | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_SEND_STATUS_CMD (13 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_GO_INACTIVE_STATE_CMD (15 | AT91C_MCI_RSPTYP_NO ) - -//*------------------------------------------------ -//* Class 2 commands: Block oriented Read commands -//*------------------------------------------------ - -#define AT91C_SET_BLOCKLEN_CMD (16 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_READ_SINGLE_BLOCK_CMD (17 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_BLOCK | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT) -#define AT91C_READ_MULTIPLE_BLOCK_CMD (18 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_MULTIPLE | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT) - -//*-------------------------------------------- -//* Class 3 commands: Sequential write commands -//*-------------------------------------------- - -#define AT91C_MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 & ~(AT91C_MCI_TRDIR) | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT ) // MMC - -//*------------------------------------------------ -//* Class 4 commands: Block oriented write commands -//*------------------------------------------------ - -#define AT91C_WRITE_BLOCK_CMD (24 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_BLOCK & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) -#define AT91C_WRITE_MULTIPLE_BLOCK_CMD (25 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_MULTIPLE & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) -#define AT91C_PROGRAM_CSD_CMD (27 | AT91C_MCI_RSPTYP_48 ) - - -//*---------------------------------------- -//* Class 6 commands: Group Write protect -//*---------------------------------------- - -#define AT91C_SET_WRITE_PROT_CMD (28 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_CLR_WRITE_PROT_CMD (29 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_SEND_WRITE_PROT_CMD (30 | AT91C_MCI_RSPTYP_48 ) - - -//*---------------------------------------- -//* Class 5 commands: Erase commands -//*---------------------------------------- - -#define AT91C_TAG_SECTOR_START_CMD (32 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_TAG_SECTOR_END_CMD (33 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_MMC_UNTAG_SECTOR_CMD (34 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_MMC_TAG_ERASE_GROUP_START_CMD (35 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_MMC_TAG_ERASE_GROUP_END_CMD (36 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_MMC_UNTAG_ERASE_GROUP_CMD (37 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_ERASE_CMD (38 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT ) - -//*---------------------------------------- -//* Class 7 commands: Lock commands -//*---------------------------------------- - -#define AT91C_LOCK_UNLOCK (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested - -//*----------------------------------------------- -// Class 8 commands: Application specific commands -//*----------------------------------------------- - -#define AT91C_APP_CMD (55 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_GEN_CMD (56 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested - -#define AT91C_SDCARD_SET_BUS_WIDTH_CMD (6 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_STATUS_CMD (13 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_APP_OP_COND_CMD (41 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO ) -#define AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_SEND_SCR_CMD (51 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) - -#define AT91C_SDCARD_APP_ALL_CMD (AT91C_SDCARD_SET_BUS_WIDTH_CMD +\ - AT91C_SDCARD_STATUS_CMD +\ - AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD +\ - AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\ - AT91C_SDCARD_APP_OP_COND_CMD +\ - AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD +\ - AT91C_SDCARD_SEND_SCR_CMD) - -//*---------------------------------------- -//* Class 9 commands: IO Mode commands -//*---------------------------------------- - -#define AT91C_MMC_FAST_IO_CMD (39 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT) -#define AT91C_MMC_GO_IRQ_STATE_CMD (40 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// Functions returnals -///////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_CMD_SEND_OK 0 // Command ok -#define AT91C_CMD_SEND_ERROR -1 // Command failed -#define AT91C_INIT_OK 2 // Init Successfull -#define AT91C_INIT_ERROR 3 // Init Failed -#define AT91C_READ_OK 4 // Read Successfull -#define AT91C_READ_ERROR 5 // Read Failed -#define AT91C_WRITE_OK 6 // Write Successfull -#define AT91C_WRITE_ERROR 7 // Write Failed -#define AT91C_ERASE_OK 8 // Erase Successfull -#define AT91C_ERASE_ERROR 9 // Erase Failed -#define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull -#define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// MCI_SR Errors -///////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE |\ - AT91C_MCI_OVRE |\ - AT91C_MCI_DTOE |\ - AT91C_MCI_DCRCE |\ - AT91C_MCI_RTOE |\ - AT91C_MCI_RENDE |\ - AT91C_MCI_RCRCE |\ - AT91C_MCI_RDIRE |\ - AT91C_MCI_RINDE) - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// OCR Register -//////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_VDD_16_17 (1 << 4) -#define AT91C_VDD_17_18 (1 << 5) -#define AT91C_VDD_18_19 (1 << 6) -#define AT91C_VDD_19_20 (1 << 7) -#define AT91C_VDD_20_21 (1 << 8) -#define AT91C_VDD_21_22 (1 << 9) -#define AT91C_VDD_22_23 (1 << 10) -#define AT91C_VDD_23_24 (1 << 11) -#define AT91C_VDD_24_25 (1 << 12) -#define AT91C_VDD_25_26 (1 << 13) -#define AT91C_VDD_26_27 (1 << 14) -#define AT91C_VDD_27_28 (1 << 15) -#define AT91C_VDD_28_29 (1 << 16) -#define AT91C_VDD_29_30 (1 << 17) -#define AT91C_VDD_30_31 (1 << 18) -#define AT91C_VDD_31_32 (1 << 19) -#define AT91C_VDD_32_33 (1 << 20) -#define AT91C_VDD_33_34 (1 << 21) -#define AT91C_VDD_34_35 (1 << 22) -#define AT91C_VDD_35_36 (1 << 23) -#define AT91C_CARD_POWER_UP_BUSY (1 << 31) - -#define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 +\ - AT91C_VDD_28_29 +\ - AT91C_VDD_29_30 +\ - AT91C_VDD_30_31 +\ - AT91C_VDD_31_32 +\ - AT91C_VDD_32_33) - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1) -//////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus -#define AT91C_SR_IDLE (0 << 9) -#define AT91C_SR_READY (1 << 9) -#define AT91C_SR_IDENT (2 << 9) -#define AT91C_SR_STBY (3 << 9) -#define AT91C_SR_TRAN (4 << 9) -#define AT91C_SR_DATA (5 << 9) -#define AT91C_SR_RCV (6 << 9) -#define AT91C_SR_PRG (7 << 9) -#define AT91C_SR_DIS (8 << 9) - -#define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN) - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// MMC CSD register header File -// AT91C_CSD_xxx_S for shift value -// AT91C_CSD_xxx_M for mask value -///////////////////////////////////////////////////////////////////////////////////////////////////// - -// First Response INT <=> CSD[3] : bits 0 to 31 -#define AT91C_CSD_BIT0_S 0 // [0:0] -#define AT91C_CSD_BIT0_M 0x01 -#define AT91C_CSD_CRC_S 1 // [7:1] -#define AT91C_CSD_CRC_M 0x7F -#define AT91C_CSD_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility -#define AT91C_CSD_MMC_ECC_M 0x03 -#define AT91C_CSD_FILE_FMT_S 10 // [11:10] -#define AT91C_CSD_FILE_FMT_M 0x03 -#define AT91C_CSD_TMP_WP_S 12 // [12:12] -#define AT91C_CSD_TMP_WP_M 0x01 -#define AT91C_CSD_PERM_WP_S 13 // [13:13] -#define AT91C_CSD_PERM_WP_M 0x01 -#define AT91C_CSD_COPY_S 14 // [14:14] -#define AT91C_CSD_COPY_M 0x01 -#define AT91C_CSD_FILE_FMT_GRP_S 15 // [15:15] -#define AT91C_CSD_FILE_FMT_GRP_M 0x01 -// reserved 16 // [20:16] -// reserved 0x1F -#define AT91C_CSD_WBLOCK_P_S 21 // [21:21] -#define AT91C_CSD_WBLOCK_P_M 0x01 -#define AT91C_CSD_WBLEN_S 22 // [25:22] -#define AT91C_CSD_WBLEN_M 0x0F -#define AT91C_CSD_R2W_F_S 26 // [28:26] -#define AT91C_CSD_R2W_F_M 0x07 -#define AT91C_CSD_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility -#define AT91C_CSD_MMC_DEF_ECC_M 0x03 -#define AT91C_CSD_WP_GRP_EN_S 31 // [31:31] -#define AT91C_CSD_WP_GRP_EN_M 0x01 - -// Seconde Response INT <=> CSD[2] : bits 32 to 63 -#define AT91C_CSD_v21_WP_GRP_SIZE_S 0 // [38:32] -#define AT91C_CSD_v21_WP_GRP_SIZE_M 0x7F -#define AT91C_CSD_v21_SECT_SIZE_S 7 // [45:39] -#define AT91C_CSD_v21_SECT_SIZE_M 0x7F -#define AT91C_CSD_v21_ER_BLEN_EN_S 14 // [46:46] -#define AT91C_CSD_v21_ER_BLEN_EN_M 0x01 - -#define AT91C_CSD_v22_WP_GRP_SIZE_S 0 // [36:32] -#define AT91C_CSD_v22_WP_GRP_SIZE_M 0x1F -#define AT91C_CSD_v22_ER_GRP_SIZE_S 5 // [41:37] -#define AT91C_CSD_v22_ER_GRP_SIZE_M 0x1F -#define AT91C_CSD_v22_SECT_SIZE_S 10 // [46:42] -#define AT91C_CSD_v22_SECT_SIZE_M 0x1F - -#define AT91C_CSD_C_SIZE_M_S 15 // [49:47] -#define AT91C_CSD_C_SIZE_M_M 0x07 -#define AT91C_CSD_VDD_WMAX_S 18 // [52:50] -#define AT91C_CSD_VDD_WMAX_M 0x07 -#define AT91C_CSD_VDD_WMIN_S 21 // [55:53] -#define AT91C_CSD_VDD_WMIN_M 0x07 -#define AT91C_CSD_RCUR_MAX_S 24 // [58:56] -#define AT91C_CSD_RCUR_MAX_M 0x07 -#define AT91C_CSD_RCUR_MIN_S 27 // [61:59] -#define AT91C_CSD_RCUR_MIN_M 0x07 -#define AT91C_CSD_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE -#define AT91C_CSD_CSIZE_L_M 0x03 - -// Third Response INT <=> CSD[1] : bits 64 to 95 -#define AT91C_CSD_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE -#define AT91C_CSD_CSIZE_H_M 0x03FF -// reserved 10 // [75:74] -// reserved 0x03 -#define AT91C_CSD_DSR_I_S 12 // [76:76] -#define AT91C_CSD_DSR_I_M 0x01 -#define AT91C_CSD_RD_B_MIS_S 13 // [77:77] -#define AT91C_CSD_RD_B_MIS_M 0x01 -#define AT91C_CSD_WR_B_MIS_S 14 // [78:78] -#define AT91C_CSD_WR_B_MIS_M 0x01 -#define AT91C_CSD_RD_B_PAR_S 15 // [79:79] -#define AT91C_CSD_RD_B_PAR_M 0x01 -#define AT91C_CSD_RD_B_LEN_S 16 // [83:80] -#define AT91C_CSD_RD_B_LEN_M 0x0F -#define AT91C_CSD_CCC_S 20 // [95:84] -#define AT91C_CSD_CCC_M 0x0FFF - -// Fourth Response INT <=> CSD[0] : bits 96 to 127 -#define AT91C_CSD_TRANS_SPEED_S 0 // [103:96] -#define AT91C_CSD_TRANS_SPEED_M 0xFF -#define AT91C_CSD_NSAC_S 8 // [111:104] -#define AT91C_CSD_NSAC_M 0xFF -#define AT91C_CSD_TAAC_S 16 // [119:112] -#define AT91C_CSD_TAAC_M 0xFF -// reserved 24 // [121:120] -// reserved 0x03 -#define AT91C_CSD_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility -#define AT91C_CSD_MMC_SPEC_VERS_M 0x0F -#define AT91C_CSD_STRUCT_S 30 // [127:126] -#define AT91C_CSD_STRUCT_M 0x03 - -///////////////////////////////////////////////////////////////////////////////////////////////////// - -#endif - diff --git a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.h b/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.h deleted file mode 100644 index 0cd153b421..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.h +++ /dev/null @@ -1,2745 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// The software is delivered "AS IS" without warranty or condition of any -// kind, either express, implied or statutory. This includes without -// limitation any warranty or condition with respect to merchantability or -// fitness for any particular purpose, or against the infringements of -// intellectual property rights of others. -// ---------------------------------------------------------------------------- -// File Name : AT91RM9200.h -// Object : AT91RM9200 definitions -// Generated : AT91 SW Application Group 11/19/2003 (17:20:50) -// -// CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// -// CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// -// CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// -// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -// CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// -// CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// -// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// -// CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// -// CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// -// CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// -// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// -// CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// -// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// -// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// -// CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// -// CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// -// CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// -// CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// -// CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// -// CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// -// ---------------------------------------------------------------------------- - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_C1R; // Chip ID1 Register - AT91_REG DBGU_C2R; // Chip ID2 Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[85]; // - AT91_REG PIOC_PER; // PIO Enable Register - AT91_REG PIOC_PDR; // PIO Disable Register - AT91_REG PIOC_PSR; // PIO Status Register - AT91_REG Reserved20[1]; // - AT91_REG PIOC_OER; // Output Enable Register - AT91_REG PIOC_ODR; // Output Disable Registerr - AT91_REG PIOC_OSR; // Output Status Register - AT91_REG Reserved21[1]; // - AT91_REG PIOC_IFER; // Input Filter Enable Register - AT91_REG PIOC_IFDR; // Input Filter Disable Register - AT91_REG PIOC_IFSR; // Input Filter Status Register - AT91_REG Reserved22[1]; // - AT91_REG PIOC_SODR; // Set Output Data Register - AT91_REG PIOC_CODR; // Clear Output Data Register - AT91_REG PIOC_ODSR; // Output Data Status Register - AT91_REG PIOC_PDSR; // Pin Data Status Register - AT91_REG PIOC_IER; // Interrupt Enable Register - AT91_REG PIOC_IDR; // Interrupt Disable Register - AT91_REG PIOC_IMR; // Interrupt Mask Register - AT91_REG PIOC_ISR; // Interrupt Status Register - AT91_REG PIOC_MDER; // Multi-driver Enable Register - AT91_REG PIOC_MDDR; // Multi-driver Disable Register - AT91_REG PIOC_MDSR; // Multi-driver Status Register - AT91_REG Reserved23[1]; // - AT91_REG PIOC_PPUDR; // Pull-up Disable Register - AT91_REG PIOC_PPUER; // Pull-up Enable Register - AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved24[1]; // - AT91_REG PIOC_ASR; // Select A Register - AT91_REG PIOC_BSR; // Select B Register - AT91_REG PIOC_ABSR; // AB Select Status Register - AT91_REG Reserved25[9]; // - AT91_REG PIOC_OWER; // Output Write Enable Register - AT91_REG PIOC_OWDR; // Output Write Disable Register - AT91_REG PIOC_OWSR; // Output Write Status Register - AT91_REG Reserved26[85]; // - AT91_REG PIOD_PER; // PIO Enable Register - AT91_REG PIOD_PDR; // PIO Disable Register - AT91_REG PIOD_PSR; // PIO Status Register - AT91_REG Reserved27[1]; // - AT91_REG PIOD_OER; // Output Enable Register - AT91_REG PIOD_ODR; // Output Disable Registerr - AT91_REG PIOD_OSR; // Output Status Register - AT91_REG Reserved28[1]; // - AT91_REG PIOD_IFER; // Input Filter Enable Register - AT91_REG PIOD_IFDR; // Input Filter Disable Register - AT91_REG PIOD_IFSR; // Input Filter Status Register - AT91_REG Reserved29[1]; // - AT91_REG PIOD_SODR; // Set Output Data Register - AT91_REG PIOD_CODR; // Clear Output Data Register - AT91_REG PIOD_ODSR; // Output Data Status Register - AT91_REG PIOD_PDSR; // Pin Data Status Register - AT91_REG PIOD_IER; // Interrupt Enable Register - AT91_REG PIOD_IDR; // Interrupt Disable Register - AT91_REG PIOD_IMR; // Interrupt Mask Register - AT91_REG PIOD_ISR; // Interrupt Status Register - AT91_REG PIOD_MDER; // Multi-driver Enable Register - AT91_REG PIOD_MDDR; // Multi-driver Disable Register - AT91_REG PIOD_MDSR; // Multi-driver Status Register - AT91_REG Reserved30[1]; // - AT91_REG PIOD_PPUDR; // Pull-up Disable Register - AT91_REG PIOD_PPUER; // Pull-up Enable Register - AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved31[1]; // - AT91_REG PIOD_ASR; // Select A Register - AT91_REG PIOD_BSR; // Select B Register - AT91_REG PIOD_ABSR; // AB Select Status Register - AT91_REG Reserved32[9]; // - AT91_REG PIOD_OWER; // Output Write Enable Register - AT91_REG PIOD_OWDR; // Output Write Disable Register - AT91_REG PIOD_OWSR; // Output Write Status Register - AT91_REG Reserved33[85]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved34[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved35[1]; // - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG CKGR_PLLAR; // PLL A Register - AT91_REG CKGR_PLLBR; // PLL B Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved36[3]; // - AT91_REG PMC_PCKR[8]; // Programmable Clock Register - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved37[36]; // - AT91_REG ST_CR; // Control Register - AT91_REG ST_PIMR; // Period Interval Mode Register - AT91_REG ST_WDMR; // Watchdog Mode Register - AT91_REG ST_RTMR; // Real-time Mode Register - AT91_REG ST_SR; // Status Register - AT91_REG ST_IER; // Interrupt Enable Register - AT91_REG ST_IDR; // Interrupt Disable Register - AT91_REG ST_IMR; // Interrupt Mask Register - AT91_REG ST_RTAR; // Real-time Alarm Register - AT91_REG ST_CRTR; // Current Real-time Register - AT91_REG Reserved38[54]; // - AT91_REG RTC_CR; // Control Register - AT91_REG RTC_MR; // Mode Register - AT91_REG RTC_TIMR; // Time Register - AT91_REG RTC_CALR; // Calendar Register - AT91_REG RTC_TIMALR; // Time Alarm Register - AT91_REG RTC_CALALR; // Calendar Alarm Register - AT91_REG RTC_SR; // Status Register - AT91_REG RTC_SCCR; // Status Clear Command Register - AT91_REG RTC_IER; // Interrupt Enable Register - AT91_REG RTC_IDR; // Interrupt Disable Register - AT91_REG RTC_IMR; // Interrupt Mask Register - AT91_REG RTC_VER; // Valid Entry Register - AT91_REG Reserved39[52]; // - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved40[1]; // - AT91_REG MC_PUIA[16]; // MC Protection Unit Area - AT91_REG MC_PUP; // MC Protection Unit Peripherals - AT91_REG MC_PUER; // MC Protection Unit Enable Register - AT91_REG Reserved41[2]; // - AT91_REG EBI_CSA; // Chip Select Assignment Register - AT91_REG EBI_CFGR; // Configuration Register - AT91_REG Reserved42[2]; // - AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register - AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register - AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register - AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register - AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register - AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register - AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register - AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register - AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register - AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register - AT91_REG Reserved43[3]; // - AT91_REG EBI_BFC_MR; // BFC Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[1]; // - AT91_REG MC_PUIA[16]; // MC Protection Unit Area - AT91_REG MC_PUP; // MC Protection Unit Peripherals - AT91_REG MC_PUER; // MC Protection Unit Enable Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- -#define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection -#define AT91C_MC_PROT_PNAUNA ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access -#define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access -#define AT91C_MC_PROT_PRWURO ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only -#define AT91C_MC_PROT_PRWURW ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write -#define AT91C_MC_SIZE ((unsigned int) 0xF << 4) // (MC) Internal Area Size -#define AT91C_MC_SIZE_1KB ((unsigned int) 0x0 << 4) // (MC) Area size 1KByte -#define AT91C_MC_SIZE_2KB ((unsigned int) 0x1 << 4) // (MC) Area size 2KByte -#define AT91C_MC_SIZE_4KB ((unsigned int) 0x2 << 4) // (MC) Area size 4KByte -#define AT91C_MC_SIZE_8KB ((unsigned int) 0x3 << 4) // (MC) Area size 8KByte -#define AT91C_MC_SIZE_16KB ((unsigned int) 0x4 << 4) // (MC) Area size 16KByte -#define AT91C_MC_SIZE_32KB ((unsigned int) 0x5 << 4) // (MC) Area size 32KByte -#define AT91C_MC_SIZE_64KB ((unsigned int) 0x6 << 4) // (MC) Area size 64KByte -#define AT91C_MC_SIZE_128KB ((unsigned int) 0x7 << 4) // (MC) Area size 128KByte -#define AT91C_MC_SIZE_256KB ((unsigned int) 0x8 << 4) // (MC) Area size 256KByte -#define AT91C_MC_SIZE_512KB ((unsigned int) 0x9 << 4) // (MC) Area size 512KByte -#define AT91C_MC_SIZE_1MB ((unsigned int) 0xA << 4) // (MC) Area size 1MByte -#define AT91C_MC_SIZE_2MB ((unsigned int) 0xB << 4) // (MC) Area size 2MByte -#define AT91C_MC_SIZE_4MB ((unsigned int) 0xC << 4) // (MC) Area size 4MByte -#define AT91C_MC_SIZE_8MB ((unsigned int) 0xD << 4) // (MC) Area size 8MByte -#define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte -#define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte -#define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address -// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- -#define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface -// ***************************************************************************** -typedef struct _AT91S_RTC { - AT91_REG RTC_CR; // Control Register - AT91_REG RTC_MR; // Mode Register - AT91_REG RTC_TIMR; // Time Register - AT91_REG RTC_CALR; // Calendar Register - AT91_REG RTC_TIMALR; // Time Alarm Register - AT91_REG RTC_CALALR; // Calendar Alarm Register - AT91_REG RTC_SR; // Status Register - AT91_REG RTC_SCCR; // Status Clear Command Register - AT91_REG RTC_IER; // Interrupt Enable Register - AT91_REG RTC_IDR; // Interrupt Disable Register - AT91_REG RTC_IMR; // Interrupt Mask Register - AT91_REG RTC_VER; // Valid Entry Register -} AT91S_RTC, *AT91PS_RTC; - -// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- -#define AT91C_RTC_UPDTIM ((unsigned int) 0x1 << 0) // (RTC) Update Request Time Register -#define AT91C_RTC_UPDCAL ((unsigned int) 0x1 << 1) // (RTC) Update Request Calendar Register -#define AT91C_RTC_TIMEVSEL ((unsigned int) 0x3 << 8) // (RTC) Time Event Selection -#define AT91C_RTC_TIMEVSEL_MINUTE ((unsigned int) 0x0 << 8) // (RTC) Minute change. -#define AT91C_RTC_TIMEVSEL_HOUR ((unsigned int) 0x1 << 8) // (RTC) Hour change. -#define AT91C_RTC_TIMEVSEL_DAY24 ((unsigned int) 0x2 << 8) // (RTC) Every day at midnight. -#define AT91C_RTC_TIMEVSEL_DAY12 ((unsigned int) 0x3 << 8) // (RTC) Every day at noon. -#define AT91C_RTC_CALEVSEL ((unsigned int) 0x3 << 16) // (RTC) Calendar Event Selection -#define AT91C_RTC_CALEVSEL_WEEK ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). -#define AT91C_RTC_CALEVSEL_MONTH ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). -#define AT91C_RTC_CALEVSEL_YEAR ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). -// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- -#define AT91C_RTC_HRMOD ((unsigned int) 0x1 << 0) // (RTC) 12-24 hour Mode -// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- -#define AT91C_RTC_SEC ((unsigned int) 0x7F << 0) // (RTC) Current Second -#define AT91C_RTC_MIN ((unsigned int) 0x7F << 8) // (RTC) Current Minute -#define AT91C_RTC_HOUR ((unsigned int) 0x1F << 16) // (RTC) Current Hour -#define AT91C_RTC_AMPM ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator -// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- -#define AT91C_RTC_CENT ((unsigned int) 0x3F << 0) // (RTC) Current Century -#define AT91C_RTC_YEAR ((unsigned int) 0xFF << 8) // (RTC) Current Year -#define AT91C_RTC_MONTH ((unsigned int) 0x1F << 16) // (RTC) Current Month -#define AT91C_RTC_DAY ((unsigned int) 0x7 << 21) // (RTC) Current Day -#define AT91C_RTC_DATE ((unsigned int) 0x3F << 24) // (RTC) Current Date -// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- -#define AT91C_RTC_SECEN ((unsigned int) 0x1 << 7) // (RTC) Second Alarm Enable -#define AT91C_RTC_MINEN ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm -#define AT91C_RTC_HOUREN ((unsigned int) 0x1 << 23) // (RTC) Current Hour -// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- -#define AT91C_RTC_MONTHEN ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable -#define AT91C_RTC_DATEEN ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable -// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- -#define AT91C_RTC_ACKUPD ((unsigned int) 0x1 << 0) // (RTC) Acknowledge for Update -#define AT91C_RTC_ALARM ((unsigned int) 0x1 << 1) // (RTC) Alarm Flag -#define AT91C_RTC_SECEV ((unsigned int) 0x1 << 2) // (RTC) Second Event -#define AT91C_RTC_TIMEV ((unsigned int) 0x1 << 3) // (RTC) Time Event -#define AT91C_RTC_CALEV ((unsigned int) 0x1 << 4) // (RTC) Calendar event -// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- -// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- -// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- -// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- -// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- -#define AT91C_RTC_NVTIM ((unsigned int) 0x1 << 0) // (RTC) Non valid Time -#define AT91C_RTC_NVCAL ((unsigned int) 0x1 << 1) // (RTC) Non valid Calendar -#define AT91C_RTC_NVTIMALR ((unsigned int) 0x1 << 2) // (RTC) Non valid time Alarm -#define AT91C_RTC_NVCALALR ((unsigned int) 0x1 << 3) // (RTC) Nonvalid Calendar Alarm - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Timer Interface -// ***************************************************************************** -typedef struct _AT91S_ST { - AT91_REG ST_CR; // Control Register - AT91_REG ST_PIMR; // Period Interval Mode Register - AT91_REG ST_WDMR; // Watchdog Mode Register - AT91_REG ST_RTMR; // Real-time Mode Register - AT91_REG ST_SR; // Status Register - AT91_REG ST_IER; // Interrupt Enable Register - AT91_REG ST_IDR; // Interrupt Disable Register - AT91_REG ST_IMR; // Interrupt Mask Register - AT91_REG ST_RTAR; // Real-time Alarm Register - AT91_REG ST_CRTR; // Current Real-time Register -} AT91S_ST, *AT91PS_ST; - -// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- -#define AT91C_ST_WDRST ((unsigned int) 0x1 << 0) // (ST) Watchdog Timer Restart -// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- -#define AT91C_ST_PIV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart -// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- -#define AT91C_ST_WDV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart -#define AT91C_ST_RSTEN ((unsigned int) 0x1 << 16) // (ST) Reset Enable -#define AT91C_ST_EXTEN ((unsigned int) 0x1 << 17) // (ST) External Signal Assertion Enable -// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- -#define AT91C_ST_RTPRES ((unsigned int) 0xFFFF << 0) // (ST) Real-time Timer Prescaler Value -// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- -#define AT91C_ST_PITS ((unsigned int) 0x1 << 0) // (ST) Period Interval Timer Interrupt -#define AT91C_ST_WDOVF ((unsigned int) 0x1 << 1) // (ST) Watchdog Overflow -#define AT91C_ST_RTTINC ((unsigned int) 0x1 << 2) // (ST) Real-time Timer Increment -#define AT91C_ST_ALMS ((unsigned int) 0x1 << 3) // (ST) Alarm Status -// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- -// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- -// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- -// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- -#define AT91C_ST_ALMV ((unsigned int) 0xFFFFF << 0) // (ST) Alarm Value Value -// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- -#define AT91C_ST_CRTV ((unsigned int) 0xFFFFF << 0) // (ST) Current Real-time Value - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[5]; // - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved2[3]; // - AT91_REG PMC_PCKR[8]; // Programmable Clock Register - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) // (PMC) USB Device Port Clock -#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend -#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) // (PMC) USB Host Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected -#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division -#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same -#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock -#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is three times faster than the master clock -#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) // (PMC) The processor clock is four times faster than the master clock -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask -#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG CKGR_PLLAR; // PLL A Register - AT91_REG CKGR_PLLBR; // PLL B Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) // (CKGR) Oscillator Test -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- -#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL A Counter -#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range -#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier -#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source -// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL B Counter -#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range -#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier -#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) // (CKGR) Divider for USB Ports -#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) // (CKGR) PLL Use - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_C1R; // Chip ID1 Register - AT91_REG DBGU_C2R; // Chip ID2 Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral Data Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive -#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG SSC_RC0R; // Receive Compare 0 Register - AT91_REG SSC_RC1R; // Receive Compare 1 Register - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved2[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG US_XXR; // XON_XOFF Register - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved1[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG TWI_SMR; // Slave Mode Register - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved0[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled -#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read -#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access -#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Multimedia Card Interface -// ***************************************************************************** -typedef struct _AT91S_MCI { - AT91_REG MCI_CR; // MCI Control Register - AT91_REG MCI_MR; // MCI Mode Register - AT91_REG MCI_DTOR; // MCI Data Timeout Register - AT91_REG MCI_SDCR; // MCI SD Card Register - AT91_REG MCI_ARGR; // MCI Argument Register - AT91_REG MCI_CMDR; // MCI Command Register - AT91_REG Reserved0[2]; // - AT91_REG MCI_RSPR[4]; // MCI Response Register - AT91_REG MCI_RDR; // MCI Receive Data Register - AT91_REG MCI_TDR; // MCI Transmit Data Register - AT91_REG Reserved1[2]; // - AT91_REG MCI_SR; // MCI Status Register - AT91_REG MCI_IER; // MCI Interrupt Enable Register - AT91_REG MCI_IDR; // MCI Interrupt Disable Register - AT91_REG MCI_IMR; // MCI Interrupt Mask Register - AT91_REG Reserved2[44]; // - AT91_REG MCI_RPR; // Receive Pointer Register - AT91_REG MCI_RCR; // Receive Counter Register - AT91_REG MCI_TPR; // Transmit Pointer Register - AT91_REG MCI_TCR; // Transmit Counter Register - AT91_REG MCI_RNPR; // Receive Next Pointer Register - AT91_REG MCI_RNCR; // Receive Next Counter Register - AT91_REG MCI_TNPR; // Transmit Next Pointer Register - AT91_REG MCI_TNCR; // Transmit Next Counter Register - AT91_REG MCI_PTCR; // PDC Transfer Control Register - AT91_REG MCI_PTSR; // PDC Transfer Status Register -} AT91S_MCI, *AT91PS_MCI; - -// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- -#define AT91C_MCI_MCIEN ((unsigned int) 0x1 << 0) // (MCI) Multimedia Interface Enable -#define AT91C_MCI_MCIDIS ((unsigned int) 0x1 << 1) // (MCI) Multimedia Interface Disable -#define AT91C_MCI_PWSEN ((unsigned int) 0x1 << 2) // (MCI) Power Save Mode Enable -#define AT91C_MCI_PWSDIS ((unsigned int) 0x1 << 3) // (MCI) Power Save Mode Disable -// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- -#define AT91C_MCI_CLKDIV ((unsigned int) 0x1 << 0) // (MCI) Clock Divider -#define AT91C_MCI_PWSDIV ((unsigned int) 0x1 << 8) // (MCI) Power Saving Divider -#define AT91C_MCI_PDCPADV ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value -#define AT91C_MCI_PDCMODE ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode -#define AT91C_MCI_BLKLEN ((unsigned int) 0x1 << 18) // (MCI) Data Block Length -// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- -#define AT91C_MCI_DTOCYC ((unsigned int) 0x1 << 0) // (MCI) Data Timeout Cycle Number -#define AT91C_MCI_DTOMUL ((unsigned int) 0x7 << 4) // (MCI) Data Timeout Multiplier -#define AT91C_MCI_DTOMUL_1 ((unsigned int) 0x0 << 4) // (MCI) DTOCYC x 1 -#define AT91C_MCI_DTOMUL_16 ((unsigned int) 0x1 << 4) // (MCI) DTOCYC x 16 -#define AT91C_MCI_DTOMUL_128 ((unsigned int) 0x2 << 4) // (MCI) DTOCYC x 128 -#define AT91C_MCI_DTOMUL_256 ((unsigned int) 0x3 << 4) // (MCI) DTOCYC x 256 -#define AT91C_MCI_DTOMUL_1024 ((unsigned int) 0x4 << 4) // (MCI) DTOCYC x 1024 -#define AT91C_MCI_DTOMUL_4096 ((unsigned int) 0x5 << 4) // (MCI) DTOCYC x 4096 -#define AT91C_MCI_DTOMUL_65536 ((unsigned int) 0x6 << 4) // (MCI) DTOCYC x 65536 -#define AT91C_MCI_DTOMUL_1048576 ((unsigned int) 0x7 << 4) // (MCI) DTOCYC x 1048576 -// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- -#define AT91C_MCI_SCDSEL ((unsigned int) 0x1 << 0) // (MCI) SD Card Selector -#define AT91C_MCI_SCDBUS ((unsigned int) 0x1 << 7) // (MCI) SD Card Bus Width -// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- -#define AT91C_MCI_CMDNB ((unsigned int) 0x1F << 0) // (MCI) Command Number -#define AT91C_MCI_RSPTYP ((unsigned int) 0x3 << 6) // (MCI) Response Type -#define AT91C_MCI_RSPTYP_NO ((unsigned int) 0x0 << 6) // (MCI) No response -#define AT91C_MCI_RSPTYP_48 ((unsigned int) 0x1 << 6) // (MCI) 48-bit response -#define AT91C_MCI_RSPTYP_136 ((unsigned int) 0x2 << 6) // (MCI) 136-bit response -#define AT91C_MCI_SPCMD ((unsigned int) 0x7 << 8) // (MCI) Special CMD -#define AT91C_MCI_SPCMD_NONE ((unsigned int) 0x0 << 8) // (MCI) Not a special CMD -#define AT91C_MCI_SPCMD_INIT ((unsigned int) 0x1 << 8) // (MCI) Initialization CMD -#define AT91C_MCI_SPCMD_SYNC ((unsigned int) 0x2 << 8) // (MCI) Synchronized CMD -#define AT91C_MCI_SPCMD_IT_CMD ((unsigned int) 0x4 << 8) // (MCI) Interrupt command -#define AT91C_MCI_SPCMD_IT_REP ((unsigned int) 0x5 << 8) // (MCI) Interrupt response -#define AT91C_MCI_OPDCMD ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command -#define AT91C_MCI_MAXLAT ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond -#define AT91C_MCI_TRCMD ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD -#define AT91C_MCI_TRCMD_NO ((unsigned int) 0x0 << 16) // (MCI) No transfer -#define AT91C_MCI_TRCMD_START ((unsigned int) 0x1 << 16) // (MCI) Start transfer -#define AT91C_MCI_TRCMD_STOP ((unsigned int) 0x2 << 16) // (MCI) Stop transfer -#define AT91C_MCI_TRDIR ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction -#define AT91C_MCI_TRTYP ((unsigned int) 0x3 << 19) // (MCI) Transfer Type -#define AT91C_MCI_TRTYP_BLOCK ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type -#define AT91C_MCI_TRTYP_MULTIPLE ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type -#define AT91C_MCI_TRTYP_STREAM ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type -// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- -#define AT91C_MCI_CMDRDY ((unsigned int) 0x1 << 0) // (MCI) Command Ready flag -#define AT91C_MCI_RXRDY ((unsigned int) 0x1 << 1) // (MCI) RX Ready flag -#define AT91C_MCI_TXRDY ((unsigned int) 0x1 << 2) // (MCI) TX Ready flag -#define AT91C_MCI_BLKE ((unsigned int) 0x1 << 3) // (MCI) Data Block Transfer Ended flag -#define AT91C_MCI_DTIP ((unsigned int) 0x1 << 4) // (MCI) Data Transfer in Progress flag -#define AT91C_MCI_NOTBUSY ((unsigned int) 0x1 << 5) // (MCI) Data Line Not Busy flag -#define AT91C_MCI_ENDRX ((unsigned int) 0x1 << 6) // (MCI) End of RX Buffer flag -#define AT91C_MCI_ENDTX ((unsigned int) 0x1 << 7) // (MCI) End of TX Buffer flag -#define AT91C_MCI_RXBUFF ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag -#define AT91C_MCI_TXBUFE ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag -#define AT91C_MCI_RINDE ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag -#define AT91C_MCI_RDIRE ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag -#define AT91C_MCI_RCRCE ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag -#define AT91C_MCI_RENDE ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag -#define AT91C_MCI_RTOE ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag -#define AT91C_MCI_DCRCE ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag -#define AT91C_MCI_DTOE ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag -#define AT91C_MCI_OVRE ((unsigned int) 0x1 << 30) // (MCI) Overrun flag -#define AT91C_MCI_UNRE ((unsigned int) 0x1 << 31) // (MCI) Underrun flag -// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- -// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- -// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register - AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt -#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 -#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Host Interface -// ***************************************************************************** -typedef struct _AT91S_UHP { - AT91_REG UHP_HcRevision; // Revision - AT91_REG UHP_HcControl; // Operating modes for the Host Controller - AT91_REG UHP_HcCommandStatus; // Command & status Register - AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register - AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register - AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register - AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area - AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor - AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list - AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register - AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list - AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list - AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor - AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs - AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame - AT91_REG UHP_HcFmNumber; // Frame number - AT91_REG UHP_HcPeriodicStart; // Periodic Start - AT91_REG UHP_HcLSThreshold; // LS Threshold - AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A - AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B - AT91_REG UHP_HcRhStatus; // Root Hub Status register - AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register -} AT91S_UHP, *AT91PS_UHP; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_CTL; // Network Control Register - AT91_REG EMAC_CFG; // Network Configuration Register - AT91_REG EMAC_SR; // Network Status Register - AT91_REG EMAC_TAR; // Transmit Address Register - AT91_REG EMAC_TCR; // Transmit Control Register - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG Reserved0[1]; // - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG Reserved1[2]; // - AT91_REG EMAC_FRA; // Frames Transmitted OK Register - AT91_REG EMAC_SCOL; // Single Collision Frame Register - AT91_REG EMAC_MCOL; // Multiple Collision Frame Register - AT91_REG EMAC_OK; // Frames Received OK Register - AT91_REG EMAC_SEQE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTE; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_TUE; // Transmit Underrun Error Register - AT91_REG EMAC_CDE; // Code Error Register - AT91_REG EMAC_ELR; // Excessive Length Error Register - AT91_REG EMAC_RJB; // Receive Jabber Register - AT91_REG EMAC_USF; // Undersize Frame Register - AT91_REG EMAC_SQEE; // SQE Test Error Register - AT91_REG EMAC_DRFC; // Discarded RX Frame Register - AT91_REG Reserved2[3]; // - AT91_REG EMAC_HSH; // Hash Address High[63:32] - AT91_REG EMAC_HSL; // Hash Address Low[31:0] - AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 High, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Low, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 High, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Low, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 High, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Low, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) // (EMAC) Bit rate. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- -#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) // (EMAC) -#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) // (EMAC) -#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR External Bus Interface -// ***************************************************************************** -typedef struct _AT91S_EBI { - AT91_REG EBI_CSA; // Chip Select Assignment Register - AT91_REG EBI_CFGR; // Configuration Register -} AT91S_EBI, *AT91PS_EBI; - -// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- -#define AT91C_EBI_CS0A ((unsigned int) 0x1 << 0) // (EBI) Chip Select 0 Assignment -#define AT91C_EBI_CS0A_SMC ((unsigned int) 0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller. -#define AT91C_EBI_CS0A_BFC ((unsigned int) 0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. -#define AT91C_EBI_CS1A ((unsigned int) 0x1 << 1) // (EBI) Chip Select 1 Assignment -#define AT91C_EBI_CS1A_SMC ((unsigned int) 0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. -#define AT91C_EBI_CS1A_SDRAMC ((unsigned int) 0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. -#define AT91C_EBI_CS3A ((unsigned int) 0x1 << 3) // (EBI) Chip Select 3 Assignment -#define AT91C_EBI_CS3A_SMC ((unsigned int) 0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. -#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. -#define AT91C_EBI_CS4A ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 Assignment -#define AT91C_EBI_CS4A_SMC ((unsigned int) 0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. -#define AT91C_EBI_CS4A_SMC_CompactFlash ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. -// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- -#define AT91C_EBI_DBPUC ((unsigned int) 0x1 << 0) // (EBI) Data Bus Pull-Up Configuration -#define AT91C_EBI_EBSEN ((unsigned int) 0x1 << 1) // (EBI) Bus Sharing Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface -// ***************************************************************************** -typedef struct _AT91S_SMC2 { - AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register -} AT91S_SMC2, *AT91PS_SMC2; - -// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- -#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) // (SMC2) Number of Wait States -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) // (SMC2) Wait State Enable -#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) // (SMC2) Data Float Time -#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) // (SMC2) Byte Access Type -#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) // (SMC2) Data Bus Width -#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) // (SMC2) 16-bit. -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) // (SMC2) 8-bit. -#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) // (SMC2) Data Read Protocol -#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) // (SMC2) Address to Chip Select Setup -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. -#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access. -#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access. -#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access. -#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) // (SMC2) Read and Write Signal Setup Time -#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) // (SMC2) Read and Write Signal Hold Time - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR SDRAM Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SDRC { - AT91_REG SDRC_MR; // SDRAM Controller Mode Register - AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register - AT91_REG SDRC_CR; // SDRAM Controller Configuration Register - AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register - AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register - AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register - AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register - AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register - AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register -} AT91S_SDRC, *AT91PS_SDRC; - -// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- -#define AT91C_SDRC_MODE ((unsigned int) 0xF << 0) // (SDRC) Mode -#define AT91C_SDRC_MODE_NORMAL_CMD ((unsigned int) 0x0) // (SDRC) Normal Mode -#define AT91C_SDRC_MODE_NOP_CMD ((unsigned int) 0x1) // (SDRC) NOP Command -#define AT91C_SDRC_MODE_PRCGALL_CMD ((unsigned int) 0x2) // (SDRC) All Banks Precharge Command -#define AT91C_SDRC_MODE_LMR_CMD ((unsigned int) 0x3) // (SDRC) Load Mode Register Command -#define AT91C_SDRC_MODE_RFSH_CMD ((unsigned int) 0x4) // (SDRC) Refresh Command -#define AT91C_SDRC_DBW ((unsigned int) 0x1 << 4) // (SDRC) Data Bus Width -#define AT91C_SDRC_DBW_32_BITS ((unsigned int) 0x0 << 4) // (SDRC) 32 Bits datas bus -#define AT91C_SDRC_DBW_16_BITS ((unsigned int) 0x1 << 4) // (SDRC) 16 Bits datas bus -// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- -#define AT91C_SDRC_COUNT ((unsigned int) 0xFFF << 0) // (SDRC) Refresh Counter -// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- -#define AT91C_SDRC_NC ((unsigned int) 0x3 << 0) // (SDRC) Number of Column Bits -#define AT91C_SDRC_NC_8 ((unsigned int) 0x0) // (SDRC) 8 Bits -#define AT91C_SDRC_NC_9 ((unsigned int) 0x1) // (SDRC) 9 Bits -#define AT91C_SDRC_NC_10 ((unsigned int) 0x2) // (SDRC) 10 Bits -#define AT91C_SDRC_NC_11 ((unsigned int) 0x3) // (SDRC) 11 Bits -#define AT91C_SDRC_NR ((unsigned int) 0x3 << 2) // (SDRC) Number of Row Bits -#define AT91C_SDRC_NR_11 ((unsigned int) 0x0 << 2) // (SDRC) 11 Bits -#define AT91C_SDRC_NR_12 ((unsigned int) 0x1 << 2) // (SDRC) 12 Bits -#define AT91C_SDRC_NR_13 ((unsigned int) 0x2 << 2) // (SDRC) 13 Bits -#define AT91C_SDRC_NB ((unsigned int) 0x1 << 4) // (SDRC) Number of Banks -#define AT91C_SDRC_NB_2_BANKS ((unsigned int) 0x0 << 4) // (SDRC) 2 banks -#define AT91C_SDRC_NB_4_BANKS ((unsigned int) 0x1 << 4) // (SDRC) 4 banks -#define AT91C_SDRC_CAS ((unsigned int) 0x3 << 5) // (SDRC) CAS Latency -#define AT91C_SDRC_CAS_2 ((unsigned int) 0x2 << 5) // (SDRC) 2 cycles -#define AT91C_SDRC_TWR ((unsigned int) 0xF << 7) // (SDRC) Number of Write Recovery Time Cycles -#define AT91C_SDRC_TRC ((unsigned int) 0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles -#define AT91C_SDRC_TRP ((unsigned int) 0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles -#define AT91C_SDRC_TRCD ((unsigned int) 0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles -#define AT91C_SDRC_TRAS ((unsigned int) 0xF << 23) // (SDRC) Number of RAS Active Time Cycles -#define AT91C_SDRC_TXSR ((unsigned int) 0xF << 27) // (SDRC) Number of Command Recovery Time Cycles -// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- -#define AT91C_SDRC_SRCB ((unsigned int) 0x1 << 0) // (SDRC) Self-refresh Command Bit -// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- -#define AT91C_SDRC_LPCB ((unsigned int) 0x1 << 0) // (SDRC) Low-power Command Bit -// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- -#define AT91C_SDRC_RES ((unsigned int) 0x1 << 0) // (SDRC) Refresh Error Status -// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- -// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- -// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Burst Flash Controller Interface -// ***************************************************************************** -typedef struct _AT91S_BFC { - AT91_REG BFC_MR; // BFC Mode Register -} AT91S_BFC, *AT91PS_BFC; - -// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- -#define AT91C_BFC_BFCOM ((unsigned int) 0x3 << 0) // (BFC) Burst Flash Controller Operating Mode -#define AT91C_BFC_BFCOM_DISABLED ((unsigned int) 0x0) // (BFC) NPCS0 is driven by the SMC or remains high. -#define AT91C_BFC_BFCOM_ASYNC ((unsigned int) 0x1) // (BFC) Asynchronous -#define AT91C_BFC_BFCOM_BURST_READ ((unsigned int) 0x2) // (BFC) Burst Read -#define AT91C_BFC_BFCC ((unsigned int) 0x3 << 2) // (BFC) Burst Flash Controller Operating Mode -#define AT91C_BFC_BFCC_MCK ((unsigned int) 0x1 << 2) // (BFC) Master Clock. -#define AT91C_BFC_BFCC_MCK_DIV_2 ((unsigned int) 0x2 << 2) // (BFC) Master Clock divided by 2. -#define AT91C_BFC_BFCC_MCK_DIV_4 ((unsigned int) 0x3 << 2) // (BFC) Master Clock divided by 4. -#define AT91C_BFC_AVL ((unsigned int) 0xF << 4) // (BFC) Address Valid Latency -#define AT91C_BFC_PAGES ((unsigned int) 0x7 << 8) // (BFC) Page Size -#define AT91C_BFC_PAGES_NO_PAGE ((unsigned int) 0x0 << 8) // (BFC) No page handling. -#define AT91C_BFC_PAGES_16 ((unsigned int) 0x1 << 8) // (BFC) 16 bytes page size. -#define AT91C_BFC_PAGES_32 ((unsigned int) 0x2 << 8) // (BFC) 32 bytes page size. -#define AT91C_BFC_PAGES_64 ((unsigned int) 0x3 << 8) // (BFC) 64 bytes page size. -#define AT91C_BFC_PAGES_128 ((unsigned int) 0x4 << 8) // (BFC) 128 bytes page size. -#define AT91C_BFC_PAGES_256 ((unsigned int) 0x5 << 8) // (BFC) 256 bytes page size. -#define AT91C_BFC_PAGES_512 ((unsigned int) 0x6 << 8) // (BFC) 512 bytes page size. -#define AT91C_BFC_PAGES_1024 ((unsigned int) 0x7 << 8) // (BFC) 1024 bytes page size. -#define AT91C_BFC_OEL ((unsigned int) 0x3 << 12) // (BFC) Output Enable Latency -#define AT91C_BFC_BAAEN ((unsigned int) 0x1 << 16) // (BFC) Burst Address Advance Enable -#define AT91C_BFC_BFOEH ((unsigned int) 0x1 << 17) // (BFC) Burst Flash Output Enable Handling -#define AT91C_BFC_MUXEN ((unsigned int) 0x1 << 18) // (BFC) Multiplexed Bus Enable -#define AT91C_BFC_RDYEN ((unsigned int) 0x1 << 19) // (BFC) Ready Enable Mode - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91RM9200 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals -#define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for RTC peripheral ========== -#define AT91C_RTC_IMR ((AT91_REG *) 0xFFFFFE28) // (RTC) Interrupt Mask Register -#define AT91C_RTC_IER ((AT91_REG *) 0xFFFFFE20) // (RTC) Interrupt Enable Register -#define AT91C_RTC_SR ((AT91_REG *) 0xFFFFFE18) // (RTC) Status Register -#define AT91C_RTC_TIMALR ((AT91_REG *) 0xFFFFFE10) // (RTC) Time Alarm Register -#define AT91C_RTC_TIMR ((AT91_REG *) 0xFFFFFE08) // (RTC) Time Register -#define AT91C_RTC_CR ((AT91_REG *) 0xFFFFFE00) // (RTC) Control Register -#define AT91C_RTC_VER ((AT91_REG *) 0xFFFFFE2C) // (RTC) Valid Entry Register -#define AT91C_RTC_IDR ((AT91_REG *) 0xFFFFFE24) // (RTC) Interrupt Disable Register -#define AT91C_RTC_SCCR ((AT91_REG *) 0xFFFFFE1C) // (RTC) Status Clear Command Register -#define AT91C_RTC_CALALR ((AT91_REG *) 0xFFFFFE14) // (RTC) Calendar Alarm Register -#define AT91C_RTC_CALR ((AT91_REG *) 0xFFFFFE0C) // (RTC) Calendar Register -#define AT91C_RTC_MR ((AT91_REG *) 0xFFFFFE04) // (RTC) Mode Register -// ========== Register definition for ST peripheral ========== -#define AT91C_ST_CRTR ((AT91_REG *) 0xFFFFFD24) // (ST) Current Real-time Register -#define AT91C_ST_IMR ((AT91_REG *) 0xFFFFFD1C) // (ST) Interrupt Mask Register -#define AT91C_ST_IER ((AT91_REG *) 0xFFFFFD14) // (ST) Interrupt Enable Register -#define AT91C_ST_RTMR ((AT91_REG *) 0xFFFFFD0C) // (ST) Real-time Mode Register -#define AT91C_ST_PIMR ((AT91_REG *) 0xFFFFFD04) // (ST) Period Interval Mode Register -#define AT91C_ST_RTAR ((AT91_REG *) 0xFFFFFD20) // (ST) Real-time Alarm Register -#define AT91C_ST_IDR ((AT91_REG *) 0xFFFFFD18) // (ST) Interrupt Disable Register -#define AT91C_ST_SR ((AT91_REG *) 0xFFFFFD10) // (ST) Status Register -#define AT91C_ST_WDMR ((AT91_REG *) 0xFFFFFD08) // (ST) Watchdog Mode Register -#define AT91C_ST_CR ((AT91_REG *) 0xFFFFFD00) // (ST) Control Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_PLLAR ((AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PIOD peripheral ========== -#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) // (PIOD) Pin Data Status Register -#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) // (PIOD) Clear Output Data Register -#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) // (PIOD) Output Write Enable Register -#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) // (PIOD) Multi-driver Enable Register -#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) // (PIOD) Interrupt Mask Register -#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) // (PIOD) Interrupt Enable Register -#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) // (PIOD) Output Data Status Register -#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) // (PIOD) Set Output Data Register -#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) // (PIOD) PIO Enable Register -#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) // (PIOD) Output Write Disable Register -#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) // (PIOD) Pull-up Enable Register -#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) // (PIOD) Multi-driver Disable Register -#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) // (PIOD) Interrupt Status Register -#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) // (PIOD) Interrupt Disable Register -#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) // (PIOD) PIO Disable Register -#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) // (PIOD) Output Disable Registerr -#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) // (PIOD) Output Write Status Register -#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) // (PIOD) AB Select Status Register -#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) // (PIOD) Select A Register -#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) // (PIOD) Pad Pull-up Status Register -#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) // (PIOD) Pull-up Disable Register -#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) // (PIOD) Multi-driver Status Register -#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) // (PIOD) PIO Status Register -#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) // (PIOD) Output Enable Register -#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) // (PIOD) Output Status Register -#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) // (PIOD) Input Filter Enable Register -#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) // (PIOD) Select B Register -#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) // (PIOD) Input Filter Disable Register -#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) // (PIOD) Input Filter Status Register -// ========== Register definition for PIOC peripheral ========== -#define AT91C_PIOC_IFDR ((AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr -#define AT91C_PIOC_ABSR ((AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register -#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register -#define AT91C_PIOC_IFSR ((AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register -#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register -#define AT91C_PIOC_ODSR ((AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register -#define AT91C_PIOC_IER ((AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register -#define AT91C_PIOC_IMR ((AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register -#define AT91C_PIOC_OWDR ((AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register -#define AT91C_PIOC_MDDR ((AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register -#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register -#define AT91C_PIOC_IDR ((AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register -#define AT91C_PIOC_ISR ((AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register -#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register -#define AT91C_PIOC_OWSR ((AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register -#define AT91C_PIOC_OWER ((AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register -#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register -#define AT91C_PIOC_PPUSR ((AT91_REG *) 0xFFFFF868) // (PIOC) Pad Pull-up Status Register -#define AT91C_PIOC_PPUDR ((AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register -#define AT91C_PIOC_MDSR ((AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register -#define AT91C_PIOC_MDER ((AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register -#define AT91C_PIOC_IFER ((AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register -#define AT91C_PIOC_OSR ((AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register -#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register -#define AT91C_PIOC_PSR ((AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register -#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register -#define AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register -#define AT91C_PIOC_PPUER ((AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pad Pull-up Status Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_SSC2 peripheral ========== -#define AT91C_SSC2_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register -#define AT91C_SSC2_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register -#define AT91C_SSC2_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register -#define AT91C_SSC2_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register -#define AT91C_SSC2_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_SSC2) Receive Pointer Register -#define AT91C_SSC2_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register -#define AT91C_SSC2_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register -#define AT91C_SSC2_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register -#define AT91C_SSC2_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_SSC2) Transmit Counter Register -#define AT91C_SSC2_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_SSC2) Receive Counter Register -// ========== Register definition for SSC2 peripheral ========== -#define AT91C_SSC2_IMR ((AT91_REG *) 0xFFFD804C) // (SSC2) Interrupt Mask Register -#define AT91C_SSC2_IER ((AT91_REG *) 0xFFFD8044) // (SSC2) Interrupt Enable Register -#define AT91C_SSC2_RC1R ((AT91_REG *) 0xFFFD803C) // (SSC2) Receive Compare 1 Register -#define AT91C_SSC2_TSHR ((AT91_REG *) 0xFFFD8034) // (SSC2) Transmit Sync Holding Register -#define AT91C_SSC2_CMR ((AT91_REG *) 0xFFFD8004) // (SSC2) Clock Mode Register -#define AT91C_SSC2_IDR ((AT91_REG *) 0xFFFD8048) // (SSC2) Interrupt Disable Register -#define AT91C_SSC2_TCMR ((AT91_REG *) 0xFFFD8018) // (SSC2) Transmit Clock Mode Register -#define AT91C_SSC2_RCMR ((AT91_REG *) 0xFFFD8010) // (SSC2) Receive Clock ModeRegister -#define AT91C_SSC2_CR ((AT91_REG *) 0xFFFD8000) // (SSC2) Control Register -#define AT91C_SSC2_RFMR ((AT91_REG *) 0xFFFD8014) // (SSC2) Receive Frame Mode Register -#define AT91C_SSC2_TFMR ((AT91_REG *) 0xFFFD801C) // (SSC2) Transmit Frame Mode Register -#define AT91C_SSC2_THR ((AT91_REG *) 0xFFFD8024) // (SSC2) Transmit Holding Register -#define AT91C_SSC2_SR ((AT91_REG *) 0xFFFD8040) // (SSC2) Status Register -#define AT91C_SSC2_RC0R ((AT91_REG *) 0xFFFD8038) // (SSC2) Receive Compare 0 Register -#define AT91C_SSC2_RSHR ((AT91_REG *) 0xFFFD8030) // (SSC2) Receive Sync Holding Register -#define AT91C_SSC2_RHR ((AT91_REG *) 0xFFFD8020) // (SSC2) Receive Holding Register -// ========== Register definition for PDC_SSC1 peripheral ========== -#define AT91C_SSC1_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register -#define AT91C_SSC1_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register -#define AT91C_SSC1_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register -#define AT91C_SSC1_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register -#define AT91C_SSC1_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register -#define AT91C_SSC1_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register -#define AT91C_SSC1_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register -#define AT91C_SSC1_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register -#define AT91C_SSC1_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register -#define AT91C_SSC1_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register -// ========== Register definition for SSC1 peripheral ========== -#define AT91C_SSC1_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register -#define AT91C_SSC1_CMR ((AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register -#define AT91C_SSC1_IDR ((AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register -#define AT91C_SSC1_SR ((AT91_REG *) 0xFFFD4040) // (SSC1) Status Register -#define AT91C_SSC1_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC1) Receive Compare 0 Register -#define AT91C_SSC1_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register -#define AT91C_SSC1_RHR ((AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register -#define AT91C_SSC1_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register -#define AT91C_SSC1_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister -#define AT91C_SSC1_CR ((AT91_REG *) 0xFFFD4000) // (SSC1) Control Register -#define AT91C_SSC1_IMR ((AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register -#define AT91C_SSC1_IER ((AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register -#define AT91C_SSC1_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC1) Receive Compare 1 Register -#define AT91C_SSC1_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register -#define AT91C_SSC1_THR ((AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register -#define AT91C_SSC1_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register -// ========== Register definition for PDC_SSC0 peripheral ========== -#define AT91C_SSC0_PTCR ((AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register -#define AT91C_SSC0_TNPR ((AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register -#define AT91C_SSC0_RNPR ((AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register -#define AT91C_SSC0_TPR ((AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register -#define AT91C_SSC0_RPR ((AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register -#define AT91C_SSC0_PTSR ((AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register -#define AT91C_SSC0_TNCR ((AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register -#define AT91C_SSC0_RNCR ((AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register -#define AT91C_SSC0_TCR ((AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register -#define AT91C_SSC0_RCR ((AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register -// ========== Register definition for SSC0 peripheral ========== -#define AT91C_SSC0_IMR ((AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register -#define AT91C_SSC0_IER ((AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register -#define AT91C_SSC0_RC1R ((AT91_REG *) 0xFFFD003C) // (SSC0) Receive Compare 1 Register -#define AT91C_SSC0_TSHR ((AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register -#define AT91C_SSC0_THR ((AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register -#define AT91C_SSC0_TFMR ((AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register -#define AT91C_SSC0_RFMR ((AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register -#define AT91C_SSC0_CMR ((AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register -#define AT91C_SSC0_IDR ((AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register -#define AT91C_SSC0_SR ((AT91_REG *) 0xFFFD0040) // (SSC0) Status Register -#define AT91C_SSC0_RC0R ((AT91_REG *) 0xFFFD0038) // (SSC0) Receive Compare 0 Register -#define AT91C_SSC0_RSHR ((AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register -#define AT91C_SSC0_RHR ((AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register -#define AT91C_SSC0_TCMR ((AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register -#define AT91C_SSC0_RCMR ((AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister -#define AT91C_SSC0_CR ((AT91_REG *) 0xFFFD0000) // (SSC0) Control Register -// ========== Register definition for PDC_US3 peripheral ========== -#define AT91C_US3_PTSR ((AT91_REG *) 0xFFFCC124) // (PDC_US3) PDC Transfer Status Register -#define AT91C_US3_TNCR ((AT91_REG *) 0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register -#define AT91C_US3_RNCR ((AT91_REG *) 0xFFFCC114) // (PDC_US3) Receive Next Counter Register -#define AT91C_US3_TCR ((AT91_REG *) 0xFFFCC10C) // (PDC_US3) Transmit Counter Register -#define AT91C_US3_RCR ((AT91_REG *) 0xFFFCC104) // (PDC_US3) Receive Counter Register -#define AT91C_US3_PTCR ((AT91_REG *) 0xFFFCC120) // (PDC_US3) PDC Transfer Control Register -#define AT91C_US3_TNPR ((AT91_REG *) 0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register -#define AT91C_US3_RNPR ((AT91_REG *) 0xFFFCC110) // (PDC_US3) Receive Next Pointer Register -#define AT91C_US3_TPR ((AT91_REG *) 0xFFFCC108) // (PDC_US3) Transmit Pointer Register -#define AT91C_US3_RPR ((AT91_REG *) 0xFFFCC100) // (PDC_US3) Receive Pointer Register -// ========== Register definition for US3 peripheral ========== -#define AT91C_US3_IF ((AT91_REG *) 0xFFFCC04C) // (US3) IRDA_FILTER Register -#define AT91C_US3_NER ((AT91_REG *) 0xFFFCC044) // (US3) Nb Errors Register -#define AT91C_US3_RTOR ((AT91_REG *) 0xFFFCC024) // (US3) Receiver Time-out Register -#define AT91C_US3_THR ((AT91_REG *) 0xFFFCC01C) // (US3) Transmitter Holding Register -#define AT91C_US3_CSR ((AT91_REG *) 0xFFFCC014) // (US3) Channel Status Register -#define AT91C_US3_IDR ((AT91_REG *) 0xFFFCC00C) // (US3) Interrupt Disable Register -#define AT91C_US3_MR ((AT91_REG *) 0xFFFCC004) // (US3) Mode Register -#define AT91C_US3_XXR ((AT91_REG *) 0xFFFCC048) // (US3) XON_XOFF Register -#define AT91C_US3_FIDI ((AT91_REG *) 0xFFFCC040) // (US3) FI_DI_Ratio Register -#define AT91C_US3_TTGR ((AT91_REG *) 0xFFFCC028) // (US3) Transmitter Time-guard Register -#define AT91C_US3_BRGR ((AT91_REG *) 0xFFFCC020) // (US3) Baud Rate Generator Register -#define AT91C_US3_RHR ((AT91_REG *) 0xFFFCC018) // (US3) Receiver Holding Register -#define AT91C_US3_IMR ((AT91_REG *) 0xFFFCC010) // (US3) Interrupt Mask Register -#define AT91C_US3_IER ((AT91_REG *) 0xFFFCC008) // (US3) Interrupt Enable Register -#define AT91C_US3_CR ((AT91_REG *) 0xFFFCC000) // (US3) Control Register -// ========== Register definition for PDC_US2 peripheral ========== -#define AT91C_US2_PTSR ((AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register -#define AT91C_US2_TNCR ((AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register -#define AT91C_US2_RNCR ((AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register -#define AT91C_US2_TCR ((AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register -#define AT91C_US2_PTCR ((AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register -#define AT91C_US2_RCR ((AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register -#define AT91C_US2_TNPR ((AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register -#define AT91C_US2_RPR ((AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register -#define AT91C_US2_TPR ((AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register -#define AT91C_US2_RNPR ((AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register -// ========== Register definition for US2 peripheral ========== -#define AT91C_US2_XXR ((AT91_REG *) 0xFFFC8048) // (US2) XON_XOFF Register -#define AT91C_US2_FIDI ((AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register -#define AT91C_US2_TTGR ((AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register -#define AT91C_US2_BRGR ((AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register -#define AT91C_US2_RHR ((AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register -#define AT91C_US2_IMR ((AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register -#define AT91C_US2_IER ((AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register -#define AT91C_US2_CR ((AT91_REG *) 0xFFFC8000) // (US2) Control Register -#define AT91C_US2_IF ((AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register -#define AT91C_US2_NER ((AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register -#define AT91C_US2_RTOR ((AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register -#define AT91C_US2_THR ((AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register -#define AT91C_US2_CSR ((AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register -#define AT91C_US2_IDR ((AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register -#define AT91C_US2_MR ((AT91_REG *) 0xFFFC8004) // (US2) Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for PDC_MCI peripheral ========== -#define AT91C_MCI_PTCR ((AT91_REG *) 0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register -#define AT91C_MCI_TNPR ((AT91_REG *) 0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register -#define AT91C_MCI_RNPR ((AT91_REG *) 0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register -#define AT91C_MCI_TPR ((AT91_REG *) 0xFFFB4108) // (PDC_MCI) Transmit Pointer Register -#define AT91C_MCI_RPR ((AT91_REG *) 0xFFFB4100) // (PDC_MCI) Receive Pointer Register -#define AT91C_MCI_PTSR ((AT91_REG *) 0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register -#define AT91C_MCI_TNCR ((AT91_REG *) 0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register -#define AT91C_MCI_RNCR ((AT91_REG *) 0xFFFB4114) // (PDC_MCI) Receive Next Counter Register -#define AT91C_MCI_TCR ((AT91_REG *) 0xFFFB410C) // (PDC_MCI) Transmit Counter Register -#define AT91C_MCI_RCR ((AT91_REG *) 0xFFFB4104) // (PDC_MCI) Receive Counter Register -// ========== Register definition for MCI peripheral ========== -#define AT91C_MCI_IDR ((AT91_REG *) 0xFFFB4048) // (MCI) MCI Interrupt Disable Register -#define AT91C_MCI_SR ((AT91_REG *) 0xFFFB4040) // (MCI) MCI Status Register -#define AT91C_MCI_RDR ((AT91_REG *) 0xFFFB4030) // (MCI) MCI Receive Data Register -#define AT91C_MCI_RSPR ((AT91_REG *) 0xFFFB4020) // (MCI) MCI Response Register -#define AT91C_MCI_ARGR ((AT91_REG *) 0xFFFB4010) // (MCI) MCI Argument Register -#define AT91C_MCI_DTOR ((AT91_REG *) 0xFFFB4008) // (MCI) MCI Data Timeout Register -#define AT91C_MCI_CR ((AT91_REG *) 0xFFFB4000) // (MCI) MCI Control Register -#define AT91C_MCI_IMR ((AT91_REG *) 0xFFFB404C) // (MCI) MCI Interrupt Mask Register -#define AT91C_MCI_IER ((AT91_REG *) 0xFFFB4044) // (MCI) MCI Interrupt Enable Register -#define AT91C_MCI_TDR ((AT91_REG *) 0xFFFB4034) // (MCI) MCI Transmit Data Register -#define AT91C_MCI_CMDR ((AT91_REG *) 0xFFFB4014) // (MCI) MCI Command Register -#define AT91C_MCI_SDCR ((AT91_REG *) 0xFFFB400C) // (MCI) MCI SD Card Register -#define AT91C_MCI_MR ((AT91_REG *) 0xFFFB4004) // (MCI) MCI Mode Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -// ========== Register definition for TC5 peripheral ========== -#define AT91C_TC5_CMR ((AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register -#define AT91C_TC5_IDR ((AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register -#define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register -#define AT91C_TC5_RB ((AT91_REG *) 0xFFFA4098) // (TC5) Register B -#define AT91C_TC5_CV ((AT91_REG *) 0xFFFA4090) // (TC5) Counter Value -#define AT91C_TC5_CCR ((AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register -#define AT91C_TC5_IMR ((AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register -#define AT91C_TC5_IER ((AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register -#define AT91C_TC5_RC ((AT91_REG *) 0xFFFA409C) // (TC5) Register C -#define AT91C_TC5_RA ((AT91_REG *) 0xFFFA4094) // (TC5) Register A -// ========== Register definition for TC4 peripheral ========== -#define AT91C_TC4_IMR ((AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register -#define AT91C_TC4_IER ((AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register -#define AT91C_TC4_RC ((AT91_REG *) 0xFFFA405C) // (TC4) Register C -#define AT91C_TC4_RA ((AT91_REG *) 0xFFFA4054) // (TC4) Register A -#define AT91C_TC4_CMR ((AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register -#define AT91C_TC4_IDR ((AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register -#define AT91C_TC4_SR ((AT91_REG *) 0xFFFA4060) // (TC4) Status Register -#define AT91C_TC4_RB ((AT91_REG *) 0xFFFA4058) // (TC4) Register B -#define AT91C_TC4_CV ((AT91_REG *) 0xFFFA4050) // (TC4) Counter Value -#define AT91C_TC4_CCR ((AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register -// ========== Register definition for TC3 peripheral ========== -#define AT91C_TC3_IMR ((AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register -#define AT91C_TC3_CV ((AT91_REG *) 0xFFFA4010) // (TC3) Counter Value -#define AT91C_TC3_CCR ((AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register -#define AT91C_TC3_IER ((AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register -#define AT91C_TC3_CMR ((AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register -#define AT91C_TC3_RA ((AT91_REG *) 0xFFFA4014) // (TC3) Register A -#define AT91C_TC3_RC ((AT91_REG *) 0xFFFA401C) // (TC3) Register C -#define AT91C_TC3_IDR ((AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register -#define AT91C_TC3_RB ((AT91_REG *) 0xFFFA4018) // (TC3) Register B -#define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register -// ========== Register definition for TCB1 peripheral ========== -#define AT91C_TCB1_BCR ((AT91_REG *) 0xFFFA4140) // (TCB1) TC Block Control Register -#define AT91C_TCB1_BMR ((AT91_REG *) 0xFFFA4144) // (TCB1) TC Block Mode Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB0 peripheral ========== -#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register -#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register -// ========== Register definition for UHP peripheral ========== -#define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) 0x00300048) // (UHP) Root Hub characteristics A -#define AT91C_UHP_HcRhPortStatus ((AT91_REG *) 0x00300054) // (UHP) Root Hub Port Status Register -#define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) 0x0030004C) // (UHP) Root Hub characteristics B -#define AT91C_UHP_HcControl ((AT91_REG *) 0x00300004) // (UHP) Operating modes for the Host Controller -#define AT91C_UHP_HcInterruptStatus ((AT91_REG *) 0x0030000C) // (UHP) Interrupt Status Register -#define AT91C_UHP_HcRhStatus ((AT91_REG *) 0x00300050) // (UHP) Root Hub Status register -#define AT91C_UHP_HcRevision ((AT91_REG *) 0x00300000) // (UHP) Revision -#define AT91C_UHP_HcCommandStatus ((AT91_REG *) 0x00300008) // (UHP) Command & status Register -#define AT91C_UHP_HcInterruptEnable ((AT91_REG *) 0x00300010) // (UHP) Interrupt Enable Register -#define AT91C_UHP_HcHCCA ((AT91_REG *) 0x00300018) // (UHP) Pointer to the Host Controller Communication Area -#define AT91C_UHP_HcControlHeadED ((AT91_REG *) 0x00300020) // (UHP) First Endpoint Descriptor of the Control list -#define AT91C_UHP_HcInterruptDisable ((AT91_REG *) 0x00300014) // (UHP) Interrupt Disable Register -#define AT91C_UHP_HcPeriodCurrentED ((AT91_REG *) 0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor -#define AT91C_UHP_HcControlCurrentED ((AT91_REG *) 0x00300024) // (UHP) Endpoint Control and Status Register -#define AT91C_UHP_HcBulkCurrentED ((AT91_REG *) 0x0030002C) // (UHP) Current endpoint of the Bulk list -#define AT91C_UHP_HcFmInterval ((AT91_REG *) 0x00300034) // (UHP) Bit time between 2 consecutive SOFs -#define AT91C_UHP_HcBulkHeadED ((AT91_REG *) 0x00300028) // (UHP) First endpoint register of the Bulk list -#define AT91C_UHP_HcBulkDoneHead ((AT91_REG *) 0x00300030) // (UHP) Last completed transfer descriptor -#define AT91C_UHP_HcFmRemaining ((AT91_REG *) 0x00300038) // (UHP) Bit time remaining in the current Frame -#define AT91C_UHP_HcPeriodicStart ((AT91_REG *) 0x00300040) // (UHP) Periodic Start -#define AT91C_UHP_HcLSThreshold ((AT91_REG *) 0x00300044) // (UHP) LS Threshold -#define AT91C_UHP_HcFmNumber ((AT91_REG *) 0x0030003C) // (UHP) Frame number -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFBC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFBC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_HSH ((AT91_REG *) 0xFFFBC090) // (EMAC) Hash Address High[63:32] -#define AT91C_EMAC_MCOL ((AT91_REG *) 0xFFFBC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFBC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes -#define AT91C_EMAC_HSL ((AT91_REG *) 0xFFFBC094) // (EMAC) Hash Address Low[31:0] -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFBC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_OK ((AT91_REG *) 0xFFFBC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_CFG ((AT91_REG *) 0xFFFBC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes -#define AT91C_EMAC_SEQE ((AT91_REG *) 0xFFFBC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFBC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_ELR ((AT91_REG *) 0xFFFBC070) // (EMAC) Excessive Length Error Register -#define AT91C_EMAC_SR ((AT91_REG *) 0xFFFBC008) // (EMAC) Network Status Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFBC064) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_RJB ((AT91_REG *) 0xFFFBC074) // (EMAC) Receive Jabber Register -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFBC078) // (EMAC) Undersize Frame Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFBC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFBC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_FRA ((AT91_REG *) 0xFFFBC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes -#define AT91C_EMAC_SCOL ((AT91_REG *) 0xFFFBC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFBC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_TAR ((AT91_REG *) 0xFFFBC00C) // (EMAC) Transmit Address Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes -#define AT91C_EMAC_TUE ((AT91_REG *) 0xFFFBC068) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_DTE ((AT91_REG *) 0xFFFBC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TCR ((AT91_REG *) 0xFFFBC010) // (EMAC) Transmit Control Register -#define AT91C_EMAC_CTL ((AT91_REG *) 0xFFFBC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr -#define AT91C_EMAC_CDE ((AT91_REG *) 0xFFFBC06C) // (EMAC) Code Error Register -#define AT91C_EMAC_SQEE ((AT91_REG *) 0xFFFBC07C) // (EMAC) SQE Test Error Register -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFBC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_DRFC ((AT91_REG *) 0xFFFBC080) // (EMAC) Discarded RX Frame Register -// ========== Register definition for EBI peripheral ========== -#define AT91C_EBI_CFGR ((AT91_REG *) 0xFFFFFF64) // (EBI) Configuration Register -#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) // (EBI) Chip Select Assignment Register -// ========== Register definition for SMC2 peripheral ========== -#define AT91C_SMC2_CSR ((AT91_REG *) 0xFFFFFF70) // (SMC2) SMC2 Chip Select Register -// ========== Register definition for SDRC peripheral ========== -#define AT91C_SDRC_IMR ((AT91_REG *) 0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register -#define AT91C_SDRC_IER ((AT91_REG *) 0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register -#define AT91C_SDRC_SRR ((AT91_REG *) 0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register -#define AT91C_SDRC_TR ((AT91_REG *) 0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register -#define AT91C_SDRC_ISR ((AT91_REG *) 0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register -#define AT91C_SDRC_IDR ((AT91_REG *) 0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register -#define AT91C_SDRC_LPR ((AT91_REG *) 0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register -#define AT91C_SDRC_CR ((AT91_REG *) 0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register -#define AT91C_SDRC_MR ((AT91_REG *) 0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register -// ========== Register definition for BFC peripheral ========== -#define AT91C_BFC_MR ((AT91_REG *) 0xFFFFFFC0) // (BFC) BFC Mode Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) // SPI Master In Slave -#define AT91C_PA0_PCK3 ((unsigned int) AT91C_PIO_PA0) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) // SPI Master Out Slave -#define AT91C_PA1_PCK0 ((unsigned int) AT91C_PIO_PA1) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) // Ethernet MAC Transmit Data 1 -#define AT91C_PA10_MCDB1 ((unsigned int) AT91C_PIO_PA10) // Multimedia Card B Data 1 -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PA11_MCDB2 ((unsigned int) AT91C_PIO_PA11) // Multimedia Card B Data 2 -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) // Ethernet MAC Receive Data 0 -#define AT91C_PA12_MCDB3 ((unsigned int) AT91C_PIO_PA12) // Multimedia Card B Data 3 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) // Ethernet MAC Receive Data 1 -#define AT91C_PA13_TCLK0 ((unsigned int) AT91C_PIO_PA13) // Timer Counter 0 external clock input -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) // Ethernet MAC Receive Error -#define AT91C_PA14_TCLK1 ((unsigned int) AT91C_PIO_PA14) // Timer Counter 1 external clock input -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) // Ethernet MAC Management Data Clock -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) // Ethernet MAC Management Data Input/Output -#define AT91C_PA16_IRQ6 ((unsigned int) AT91C_PIO_PA16) // AIC Interrupt input 6 -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TXD0 ((unsigned int) AT91C_PIO_PA17) // USART 0 Transmit Data -#define AT91C_PA17_TIOA0 ((unsigned int) AT91C_PIO_PA17) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RXD0 ((unsigned int) AT91C_PIO_PA18) // USART 0 Receive Data -#define AT91C_PA18_TIOB0 ((unsigned int) AT91C_PIO_PA18) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_SCK0 ((unsigned int) AT91C_PIO_PA19) // USART 0 Serial Clock -#define AT91C_PA19_TIOA1 ((unsigned int) AT91C_PIO_PA19) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) // SPI Serial Clock -#define AT91C_PA2_IRQ4 ((unsigned int) AT91C_PIO_PA2) // AIC Interrupt Input 4 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CTS0 ((unsigned int) AT91C_PIO_PA20) // USART 0 Clear To Send -#define AT91C_PA20_TIOB1 ((unsigned int) AT91C_PIO_PA20) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RTS0 ((unsigned int) AT91C_PIO_PA21) // Usart 0 Ready To Send -#define AT91C_PA21_TIOA2 ((unsigned int) AT91C_PIO_PA21) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) // USART 2 Receive Data -#define AT91C_PA22_TIOB2 ((unsigned int) AT91C_PIO_PA22) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) // USART 2 Transmit Data -#define AT91C_PA23_IRQ3 ((unsigned int) AT91C_PIO_PA23) // Interrupt input 3 -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_SCK2 ((unsigned int) AT91C_PIO_PA24) // USART2 Serial Clock -#define AT91C_PA24_PCK1 ((unsigned int) AT91C_PIO_PA24) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_TWD ((unsigned int) AT91C_PIO_PA25) // TWI Two-wire Serial Data -#define AT91C_PA25_IRQ2 ((unsigned int) AT91C_PIO_PA25) // Interrupt input 2 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_TWCK ((unsigned int) AT91C_PIO_PA26) // TWI Two-wire Serial Clock -#define AT91C_PA26_IRQ1 ((unsigned int) AT91C_PIO_PA26) // Interrupt input 1 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_MCCK ((unsigned int) AT91C_PIO_PA27) // Multimedia Card Clock -#define AT91C_PA27_TCLK3 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 3 External Clock Input -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_MCCDA ((unsigned int) AT91C_PIO_PA28) // Multimedia Card A Command -#define AT91C_PA28_TCLK4 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 4 external Clock Input -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_MCDA0 ((unsigned int) AT91C_PIO_PA29) // Multimedia Card A Data 0 -#define AT91C_PA29_TCLK5 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 5 external clock input -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 0 -#define AT91C_PA3_IRQ5 ((unsigned int) AT91C_PIO_PA3) // AIC Interrupt Input 5 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) // DBGU Debug Receive Data -#define AT91C_PA30_CTS2 ((unsigned int) AT91C_PIO_PA30) // Usart 2 Clear To Send -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) // DBGU Debug Transmit Data -#define AT91C_PA31_RTS2 ((unsigned int) AT91C_PIO_PA31) // USART 2 Ready To Send -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) // SPI Peripheral Chip Select 1 -#define AT91C_PA4_PCK1 ((unsigned int) AT91C_PIO_PA4) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 2 -#define AT91C_PA5_TXD3 ((unsigned int) AT91C_PIO_PA5) // USART 3 Transmit Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) // SPI Peripheral Chip Select 3 -#define AT91C_PA6_RXD3 ((unsigned int) AT91C_PIO_PA6) // USART 3 Receive Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PA7_PCK2 ((unsigned int) AT91C_PIO_PA7) // PMC Programmable Clock 2 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) // Ethernet MAC Transmit Enable -#define AT91C_PA8_MCCDB ((unsigned int) AT91C_PIO_PA8) // Multimedia Card B Command -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) // Ethernet MAC Transmit Data 0 -#define AT91C_PA9_MCDB0 ((unsigned int) AT91C_PIO_PA9) // Multimedia Card B Data 0 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_TF0 ((unsigned int) AT91C_PIO_PB0) // SSC Transmit Frame Sync 0 -#define AT91C_PB0_TIOB3 ((unsigned int) AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_TK0 ((unsigned int) AT91C_PIO_PB1) // SSC Transmit Clock 0 -#define AT91C_PB1_CTS3 ((unsigned int) AT91C_PIO_PB1) // USART 3 Clear To Send -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_RK1 ((unsigned int) AT91C_PIO_PB10) // SSC Receive Clock 1 -#define AT91C_PB10_TIOA5 ((unsigned int) AT91C_PIO_PB10) // Timer Counter 5 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_RF1 ((unsigned int) AT91C_PIO_PB11) // SSC Receive Frame Sync 1 -#define AT91C_PB11_TIOB5 ((unsigned int) AT91C_PIO_PB11) // Timer Counter 5 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) // SSC Transmit Frame Sync 2 -#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmit Data 2 -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) // SSC Transmit Clock 2 -#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Transmit Data 3 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) // SSC Transmit Data 2 -#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Transmikt Coding Error -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) // SSC Receive Data 2 -#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data 2 -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) // SSC Receive Clock 2 -#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Receive Data 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) // SSC Receive Frame Sync 2 -#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) // USART 1 Ring Indicator -#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Collision Detected -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) // USART 1 Data Terminal ready -#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) // Ethernet MAC Receive Clock -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_TD0 ((unsigned int) AT91C_PIO_PB2) // SSC Transmit data -#define AT91C_PB2_SCK3 ((unsigned int) AT91C_PIO_PB2) // USART 3 Serial Clock -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_TXD1 ((unsigned int) AT91C_PIO_PB20) // USART 1 Transmit Data -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_RXD1 ((unsigned int) AT91C_PIO_PB21) // USART 1 Receive Data -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_SCK1 ((unsigned int) AT91C_PIO_PB22) // USART1 Serial Clock -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_CTS1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Clear To Send -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Set ready -#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_RTS1 ((unsigned int) AT91C_PIO_PB26) // Usart 0 Ready To Send -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_PCK0 ((unsigned int) AT91C_PIO_PB27) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_FIQ ((unsigned int) AT91C_PIO_PB28) // AIC Fast Interrupt Input -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_IRQ0 ((unsigned int) AT91C_PIO_PB29) // Interrupt input 0 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_RD0 ((unsigned int) AT91C_PIO_PB3) // SSC Receive Data -#define AT91C_PB3_MCDA1 ((unsigned int) AT91C_PIO_PB3) // Multimedia Card A Data 1 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_RK0 ((unsigned int) AT91C_PIO_PB4) // SSC Receive Clock -#define AT91C_PB4_MCDA2 ((unsigned int) AT91C_PIO_PB4) // Multimedia Card A Data 2 -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_RF0 ((unsigned int) AT91C_PIO_PB5) // SSC Receive Frame Sync 0 -#define AT91C_PB5_MCDA3 ((unsigned int) AT91C_PIO_PB5) // Multimedia Card A Data 3 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_TF1 ((unsigned int) AT91C_PIO_PB6) // SSC Transmit Frame Sync 1 -#define AT91C_PB6_TIOA3 ((unsigned int) AT91C_PIO_PB6) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_TK1 ((unsigned int) AT91C_PIO_PB7) // SSC Transmit Clock 1 -#define AT91C_PB7_TIOB3 ((unsigned int) AT91C_PIO_PB7) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_TD1 ((unsigned int) AT91C_PIO_PB8) // SSC Transmit Data 1 -#define AT91C_PB8_TIOA4 ((unsigned int) AT91C_PIO_PB8) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_RD1 ((unsigned int) AT91C_PIO_PB9) // SSC Receive Data 1 -#define AT91C_PB9_TIOB4 ((unsigned int) AT91C_PIO_PB9) // Timer Counter 4 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) // Pin Controlled by PC0 -#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) // Burst Flash Clock -#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) // Pin Controlled by PC1 -#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) // Burst Flash Ready -#define AT91C_PIO_PC10 ((unsigned int) 1 << 10) // Pin Controlled by PC10 -#define AT91C_PC10_NCS4_CFCS ((unsigned int) AT91C_PIO_PC10) // Compact Flash Chip Select -#define AT91C_PIO_PC11 ((unsigned int) 1 << 11) // Pin Controlled by PC11 -#define AT91C_PC11_NCS5_CFCE1 ((unsigned int) AT91C_PIO_PC11) // Chip Select 5 / Compact Flash Chip Enable 1 -#define AT91C_PIO_PC12 ((unsigned int) 1 << 12) // Pin Controlled by PC12 -#define AT91C_PC12_NCS6_CFCE2 ((unsigned int) AT91C_PIO_PC12) // Chip Select 6 / Compact Flash Chip Enable 2 -#define AT91C_PIO_PC13 ((unsigned int) 1 << 13) // Pin Controlled by PC13 -#define AT91C_PC13_NCS7 ((unsigned int) AT91C_PIO_PC13) // Chip Select 7 -#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) // Pin Controlled by PC14 -#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) // Pin Controlled by PC15 -#define AT91C_PIO_PC16 ((unsigned int) 1 << 16) // Pin Controlled by PC16 -#define AT91C_PC16_D16 ((unsigned int) AT91C_PIO_PC16) // Data Bus [16] -#define AT91C_PIO_PC17 ((unsigned int) 1 << 17) // Pin Controlled by PC17 -#define AT91C_PC17_D17 ((unsigned int) AT91C_PIO_PC17) // Data Bus [17] -#define AT91C_PIO_PC18 ((unsigned int) 1 << 18) // Pin Controlled by PC18 -#define AT91C_PC18_D18 ((unsigned int) AT91C_PIO_PC18) // Data Bus [18] -#define AT91C_PIO_PC19 ((unsigned int) 1 << 19) // Pin Controlled by PC19 -#define AT91C_PC19_D19 ((unsigned int) AT91C_PIO_PC19) // Data Bus [19] -#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) // Pin Controlled by PC2 -#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) // Burst Flash Address Valid -#define AT91C_PIO_PC20 ((unsigned int) 1 << 20) // Pin Controlled by PC20 -#define AT91C_PC20_D20 ((unsigned int) AT91C_PIO_PC20) // Data Bus [20] -#define AT91C_PIO_PC21 ((unsigned int) 1 << 21) // Pin Controlled by PC21 -#define AT91C_PC21_D21 ((unsigned int) AT91C_PIO_PC21) // Data Bus [21] -#define AT91C_PIO_PC22 ((unsigned int) 1 << 22) // Pin Controlled by PC22 -#define AT91C_PC22_D22 ((unsigned int) AT91C_PIO_PC22) // Data Bus [22] -#define AT91C_PIO_PC23 ((unsigned int) 1 << 23) // Pin Controlled by PC23 -#define AT91C_PC23_D23 ((unsigned int) AT91C_PIO_PC23) // Data Bus [23] -#define AT91C_PIO_PC24 ((unsigned int) 1 << 24) // Pin Controlled by PC24 -#define AT91C_PC24_D24 ((unsigned int) AT91C_PIO_PC24) // Data Bus [24] -#define AT91C_PIO_PC25 ((unsigned int) 1 << 25) // Pin Controlled by PC25 -#define AT91C_PC25_D25 ((unsigned int) AT91C_PIO_PC25) // Data Bus [25] -#define AT91C_PIO_PC26 ((unsigned int) 1 << 26) // Pin Controlled by PC26 -#define AT91C_PC26_D26 ((unsigned int) AT91C_PIO_PC26) // Data Bus [26] -#define AT91C_PIO_PC27 ((unsigned int) 1 << 27) // Pin Controlled by PC27 -#define AT91C_PC27_D27 ((unsigned int) AT91C_PIO_PC27) // Data Bus [27] -#define AT91C_PIO_PC28 ((unsigned int) 1 << 28) // Pin Controlled by PC28 -#define AT91C_PC28_D28 ((unsigned int) AT91C_PIO_PC28) // Data Bus [28] -#define AT91C_PIO_PC29 ((unsigned int) 1 << 29) // Pin Controlled by PC29 -#define AT91C_PC29_D29 ((unsigned int) AT91C_PIO_PC29) // Data Bus [29] -#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) // Pin Controlled by PC3 -#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) // Burst Flash Address Advance / SmartMedia Write Enable -#define AT91C_PIO_PC30 ((unsigned int) 1 << 30) // Pin Controlled by PC30 -#define AT91C_PC30_D30 ((unsigned int) AT91C_PIO_PC30) // Data Bus [30] -#define AT91C_PIO_PC31 ((unsigned int) 1 << 31) // Pin Controlled by PC31 -#define AT91C_PC31_D31 ((unsigned int) AT91C_PIO_PC31) // Data Bus [31] -#define AT91C_PIO_PC4 ((unsigned int) 1 << 4) // Pin Controlled by PC4 -#define AT91C_PC4_BFOE ((unsigned int) AT91C_PIO_PC4) // Burst Flash Output Enable -#define AT91C_PIO_PC5 ((unsigned int) 1 << 5) // Pin Controlled by PC5 -#define AT91C_PC5_BFWE ((unsigned int) AT91C_PIO_PC5) // Burst Flash Write Enable -#define AT91C_PIO_PC6 ((unsigned int) 1 << 6) // Pin Controlled by PC6 -#define AT91C_PC6_NWAIT ((unsigned int) AT91C_PIO_PC6) // NWAIT -#define AT91C_PIO_PC7 ((unsigned int) 1 << 7) // Pin Controlled by PC7 -#define AT91C_PC7_A23 ((unsigned int) AT91C_PIO_PC7) // Address Bus[23] -#define AT91C_PIO_PC8 ((unsigned int) 1 << 8) // Pin Controlled by PC8 -#define AT91C_PC8_A24 ((unsigned int) AT91C_PIO_PC8) // Address Bus[24] -#define AT91C_PIO_PC9 ((unsigned int) 1 << 9) // Pin Controlled by PC9 -#define AT91C_PC9_A25_CFRNW ((unsigned int) AT91C_PIO_PC9) // Address Bus[25] / Compact Flash Read Not Write -#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) // Pin Controlled by PD0 -#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) // Pin Controlled by PD1 -#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) // Pin Controlled by PD10 -#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) // PMC Programmable Clock Output 3 -#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) // ETM ARM9 pipeline status 1 -#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) // Pin Controlled by PD11 -#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) // -#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) // ETM ARM9 pipeline status 2 -#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) // Pin Controlled by PD12 -#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) // -#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) // ETM Trace Packet 0 -#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) // Pin Controlled by PD13 -#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) // -#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) // ETM Trace Packet 1 -#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) // Pin Controlled by PD14 -#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) // -#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) // ETM Trace Packet 2 -#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) // Pin Controlled by PD15 -#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) // SSC Transmit data -#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) // ETM Trace Packet 3 -#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) // Pin Controlled by PD16 -#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) // SSC Transmit Data 1 -#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) // ETM Trace Packet 4 -#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) // Pin Controlled by PD17 -#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) // SSC Transmit Data 2 -#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) // ETM Trace Packet 5 -#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) // Pin Controlled by PD18 -#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) // SPI Peripheral Chip Select 1 -#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) // ETM Trace Packet 6 -#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) // Pin Controlled by PD19 -#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) // SPI Peripheral Chip Select 2 -#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) // ETM Trace Packet 7 -#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) // Pin Controlled by PD2 -#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) // Ethernet MAC Transmit Data 2 -#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) // Pin Controlled by PD20 -#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) // SPI Peripheral Chip Select 3 -#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) // ETM Trace Packet 8 -#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) // Pin Controlled by PD21 -#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) // Usart 0 Ready To Send -#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) // ETM Trace Packet 9 -#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) // Pin Controlled by PD22 -#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) // Usart 0 Ready To Send -#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) // ETM Trace Packet 10 -#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) // Pin Controlled by PD23 -#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) // USART 2 Ready To Send -#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) // ETM Trace Packet 11 -#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) // Pin Controlled by PD24 -#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) // USART 3 Ready To Send -#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) // ETM Trace Packet 12 -#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) // Pin Controlled by PD25 -#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) // USART 1 Data Terminal ready -#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) // ETM Trace Packet 13 -#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) // Pin Controlled by PD26 -#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) // ETM Trace Packet 14 -#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) // Pin Controlled by PD27 -#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) // ETM Trace Packet 15 -#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) // Pin Controlled by PD3 -#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) // Ethernet MAC Transmit Data 3 -#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) // Pin Controlled by PD4 -#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) // Pin Controlled by PD5 -#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) // Ethernet MAC Transmikt Coding Error -#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) // Pin Controlled by PD6 -#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) // DBGU Debug Transmit Data -#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) // Pin Controlled by PD7 -#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) // PMC Programmable Clock Output 0 -#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) // ETM Synchronization signal -#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) // Pin Controlled by PD8 -#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) // PMC Programmable Clock Output 1 -#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) // ETM Trace Clock signal -#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) // Pin Controlled by PD9 -#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) // PMC Programmable Clock 2 -#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) // ETM ARM9 pipeline status 0 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_PIOC ((unsigned int) 4) // Parallel IO Controller C -#define AT91C_ID_PIOD ((unsigned int) 5) // Parallel IO Controller D -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_US2 ((unsigned int) 8) // USART 2 -#define AT91C_ID_US3 ((unsigned int) 9) // USART 3 -#define AT91C_ID_MCI ((unsigned int) 10) // Multimedia Card Interface -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TWI ((unsigned int) 12) // Two-Wire Interface -#define AT91C_ID_SPI ((unsigned int) 13) // Serial Peripheral Interface -#define AT91C_ID_SSC0 ((unsigned int) 14) // Serial Synchronous Controller 0 -#define AT91C_ID_SSC1 ((unsigned int) 15) // Serial Synchronous Controller 1 -#define AT91C_ID_SSC2 ((unsigned int) 16) // Serial Synchronous Controller 2 -#define AT91C_ID_TC0 ((unsigned int) 17) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 18) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 19) // Timer Counter 2 -#define AT91C_ID_TC3 ((unsigned int) 20) // Timer Counter 3 -#define AT91C_ID_TC4 ((unsigned int) 21) // Timer Counter 4 -#define AT91C_ID_TC5 ((unsigned int) 22) // Timer Counter 5 -#define AT91C_ID_UHP ((unsigned int) 23) // USB Host port -#define AT91C_ID_EMAC ((unsigned int) 24) // Ethernet MAC -#define AT91C_ID_IRQ0 ((unsigned int) 25) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 26) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ID_IRQ2 ((unsigned int) 27) // Advanced Interrupt Controller (IRQ2) -#define AT91C_ID_IRQ3 ((unsigned int) 28) // Advanced Interrupt Controller (IRQ3) -#define AT91C_ID_IRQ4 ((unsigned int) 29) // Advanced Interrupt Controller (IRQ4) -#define AT91C_ID_IRQ5 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ5) -#define AT91C_ID_IRQ6 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ6) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) // (RTC) Base Address -#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) // (ST) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) // (PIOD) Base Address -#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_SSC2 ((AT91PS_PDC) 0xFFFD8100) // (PDC_SSC2) Base Address -#define AT91C_BASE_SSC2 ((AT91PS_SSC) 0xFFFD8000) // (SSC2) Base Address -#define AT91C_BASE_PDC_SSC1 ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address -#define AT91C_BASE_SSC1 ((AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address -#define AT91C_BASE_PDC_SSC0 ((AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address -#define AT91C_BASE_SSC0 ((AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address -#define AT91C_BASE_PDC_US3 ((AT91PS_PDC) 0xFFFCC100) // (PDC_US3) Base Address -#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) // (US3) Base Address -#define AT91C_BASE_PDC_US2 ((AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address -#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) // (US2) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PDC_MCI ((AT91PS_PDC) 0xFFFB4100) // (PDC_MCI) Base Address -#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) // (MCI) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC5 ((AT91PS_TC) 0xFFFA4080) // (TC5) Base Address -#define AT91C_BASE_TC4 ((AT91PS_TC) 0xFFFA4040) // (TC4) Base Address -#define AT91C_BASE_TC3 ((AT91PS_TC) 0xFFFA4000) // (TC3) Base Address -#define AT91C_BASE_TCB1 ((AT91PS_TCB) 0xFFFA4080) // (TCB1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address -#define AT91C_BASE_UHP ((AT91PS_UHP) 0x00300000) // (UHP) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) // (EMAC) Base Address -#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFFFFF60) // (EBI) Base Address -#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) // (SMC2) Base Address -#define AT91C_BASE_SDRC ((AT91PS_SDRC) 0xFFFFFF90) // (SDRC) Base Address -#define AT91C_BASE_BFC ((AT91PS_BFC) 0xFFFFFFC0) // (BFC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte) -#define AT91C_IROM ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IROM_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) - -#endif diff --git a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.inc b/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.inc deleted file mode 100644 index 670e023fb5..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.inc +++ /dev/null @@ -1,2437 +0,0 @@ -;- ---------------------------------------------------------------------------- -;- ATMEL Microcontroller Software Support - ROUSSET - -;- ---------------------------------------------------------------------------- -;- The software is delivered "AS IS" without warranty or condition of any -;- kind, either express, implied or statutory. This includes without -;- limitation any warranty or condition with respect to merchantability or -;- fitness for any particular purpose, or against the infringements of -;- intellectual property rights of others. -;- ---------------------------------------------------------------------------- -;- File Name : AT91RM9200.h -;- Object : AT91RM9200 definitions -;- Generated : AT91 SW Application Group 11/19/2003 (17:20:51) -;- -;- CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// -;- CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// -;- CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// -;- CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -;- CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -;- CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// -;- CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// -;- CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -;- CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -;- CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// -;- CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// -;- CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// -;- CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// -;- CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// -;- CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// -;- CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// -;- CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// -;- CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// -;- CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// -;- CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// -;- CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// -;- CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// -;- CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// -;- ---------------------------------------------------------------------------- - -;- Hardware register definition - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR System Peripherals -;- ***************************************************************************** - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Memory Controller Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_MC -MC_RCR # 4 ;- MC Remap Control Register -MC_ASR # 4 ;- MC Abort Status Register -MC_AASR # 4 ;- MC Abort Address Status Register - # 4 ;- Reserved -MC_PUIA # 64 ;- MC Protection Unit Area -MC_PUP # 4 ;- MC Protection Unit Peripherals -MC_PUER # 4 ;- MC Protection Unit Enable Register -;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit -;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status -AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status -AT91C_MC_MPU EQU (0x1:SHL:2) ;- (MC) Memory protection Unit Abort Status -AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status -AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte -AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word -AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word -AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status -AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read -AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write -AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch -AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source -AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source -AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source -AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source -;- -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- -AT91C_MC_PROT EQU (0x3:SHL:0) ;- (MC) Protection -AT91C_MC_PROT_PNAUNA EQU (0x0) ;- (MC) Privilege: No Access, User: No Access -AT91C_MC_PROT_PRWUNA EQU (0x1) ;- (MC) Privilege: Read/Write, User: No Access -AT91C_MC_PROT_PRWURO EQU (0x2) ;- (MC) Privilege: Read/Write, User: Read Only -AT91C_MC_PROT_PRWURW EQU (0x3) ;- (MC) Privilege: Read/Write, User: Read/Write -AT91C_MC_SIZE EQU (0xF:SHL:4) ;- (MC) Internal Area Size -AT91C_MC_SIZE_1KB EQU (0x0:SHL:4) ;- (MC) Area size 1KByte -AT91C_MC_SIZE_2KB EQU (0x1:SHL:4) ;- (MC) Area size 2KByte -AT91C_MC_SIZE_4KB EQU (0x2:SHL:4) ;- (MC) Area size 4KByte -AT91C_MC_SIZE_8KB EQU (0x3:SHL:4) ;- (MC) Area size 8KByte -AT91C_MC_SIZE_16KB EQU (0x4:SHL:4) ;- (MC) Area size 16KByte -AT91C_MC_SIZE_32KB EQU (0x5:SHL:4) ;- (MC) Area size 32KByte -AT91C_MC_SIZE_64KB EQU (0x6:SHL:4) ;- (MC) Area size 64KByte -AT91C_MC_SIZE_128KB EQU (0x7:SHL:4) ;- (MC) Area size 128KByte -AT91C_MC_SIZE_256KB EQU (0x8:SHL:4) ;- (MC) Area size 256KByte -AT91C_MC_SIZE_512KB EQU (0x9:SHL:4) ;- (MC) Area size 512KByte -AT91C_MC_SIZE_1MB EQU (0xA:SHL:4) ;- (MC) Area size 1MByte -AT91C_MC_SIZE_2MB EQU (0xB:SHL:4) ;- (MC) Area size 2MByte -AT91C_MC_SIZE_4MB EQU (0xC:SHL:4) ;- (MC) Area size 4MByte -AT91C_MC_SIZE_8MB EQU (0xD:SHL:4) ;- (MC) Area size 8MByte -AT91C_MC_SIZE_16MB EQU (0xE:SHL:4) ;- (MC) Area size 16MByte -AT91C_MC_SIZE_64MB EQU (0xF:SHL:4) ;- (MC) Area size 64MByte -AT91C_MC_BA EQU (0x3FFFF:SHL:10) ;- (MC) Internal Area Base Address -;- -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -;- -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- -AT91C_MC_PUEB EQU (0x1:SHL:0) ;- (MC) Protection Unit enable Bit - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_RTC -RTC_CR # 4 ;- Control Register -RTC_MR # 4 ;- Mode Register -RTC_TIMR # 4 ;- Time Register -RTC_CALR # 4 ;- Calendar Register -RTC_TIMALR # 4 ;- Time Alarm Register -RTC_CALALR # 4 ;- Calendar Alarm Register -RTC_SR # 4 ;- Status Register -RTC_SCCR # 4 ;- Status Clear Command Register -RTC_IER # 4 ;- Interrupt Enable Register -RTC_IDR # 4 ;- Interrupt Disable Register -RTC_IMR # 4 ;- Interrupt Mask Register -RTC_VER # 4 ;- Valid Entry Register -;- -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- -AT91C_RTC_UPDTIM EQU (0x1:SHL:0) ;- (RTC) Update Request Time Register -AT91C_RTC_UPDCAL EQU (0x1:SHL:1) ;- (RTC) Update Request Calendar Register -AT91C_RTC_TIMEVSEL EQU (0x3:SHL:8) ;- (RTC) Time Event Selection -AT91C_RTC_TIMEVSEL_MINUTE EQU (0x0:SHL:8) ;- (RTC) Minute change. -AT91C_RTC_TIMEVSEL_HOUR EQU (0x1:SHL:8) ;- (RTC) Hour change. -AT91C_RTC_TIMEVSEL_DAY24 EQU (0x2:SHL:8) ;- (RTC) Every day at midnight. -AT91C_RTC_TIMEVSEL_DAY12 EQU (0x3:SHL:8) ;- (RTC) Every day at noon. -AT91C_RTC_CALEVSEL EQU (0x3:SHL:16) ;- (RTC) Calendar Event Selection -AT91C_RTC_CALEVSEL_WEEK EQU (0x0:SHL:16) ;- (RTC) Week change (every Monday at time 00:00:00). -AT91C_RTC_CALEVSEL_MONTH EQU (0x1:SHL:16) ;- (RTC) Month change (every 01 of each month at time 00:00:00). -AT91C_RTC_CALEVSEL_YEAR EQU (0x2:SHL:16) ;- (RTC) Year change (every January 1 at time 00:00:00). -;- -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- -AT91C_RTC_HRMOD EQU (0x1:SHL:0) ;- (RTC) 12-24 hour Mode -;- -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- -AT91C_RTC_SEC EQU (0x7F:SHL:0) ;- (RTC) Current Second -AT91C_RTC_MIN EQU (0x7F:SHL:8) ;- (RTC) Current Minute -AT91C_RTC_HOUR EQU (0x1F:SHL:16) ;- (RTC) Current Hour -AT91C_RTC_AMPM EQU (0x1:SHL:22) ;- (RTC) Ante Meridiem, Post Meridiem Indicator -;- -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- -AT91C_RTC_CENT EQU (0x3F:SHL:0) ;- (RTC) Current Century -AT91C_RTC_YEAR EQU (0xFF:SHL:8) ;- (RTC) Current Year -AT91C_RTC_MONTH EQU (0x1F:SHL:16) ;- (RTC) Current Month -AT91C_RTC_DAY EQU (0x7:SHL:21) ;- (RTC) Current Day -AT91C_RTC_DATE EQU (0x3F:SHL:24) ;- (RTC) Current Date -;- -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- -AT91C_RTC_SECEN EQU (0x1:SHL:7) ;- (RTC) Second Alarm Enable -AT91C_RTC_MINEN EQU (0x1:SHL:15) ;- (RTC) Minute Alarm -AT91C_RTC_HOUREN EQU (0x1:SHL:23) ;- (RTC) Current Hour -;- -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- -AT91C_RTC_MONTHEN EQU (0x1:SHL:23) ;- (RTC) Month Alarm Enable -AT91C_RTC_DATEEN EQU (0x1:SHL:31) ;- (RTC) Date Alarm Enable -;- -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- -AT91C_RTC_ACKUPD EQU (0x1:SHL:0) ;- (RTC) Acknowledge for Update -AT91C_RTC_ALARM EQU (0x1:SHL:1) ;- (RTC) Alarm Flag -AT91C_RTC_SECEV EQU (0x1:SHL:2) ;- (RTC) Second Event -AT91C_RTC_TIMEV EQU (0x1:SHL:3) ;- (RTC) Time Event -AT91C_RTC_CALEV EQU (0x1:SHL:4) ;- (RTC) Calendar event -;- -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- -;- -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- -;- -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- -;- -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- -;- -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- -AT91C_RTC_NVTIM EQU (0x1:SHL:0) ;- (RTC) Non valid Time -AT91C_RTC_NVCAL EQU (0x1:SHL:1) ;- (RTC) Non valid Calendar -AT91C_RTC_NVTIMALR EQU (0x1:SHL:2) ;- (RTC) Non valid time Alarm -AT91C_RTC_NVCALALR EQU (0x1:SHL:3) ;- (RTC) Nonvalid Calendar Alarm - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR System Timer Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_ST -ST_CR # 4 ;- Control Register -ST_PIMR # 4 ;- Period Interval Mode Register -ST_WDMR # 4 ;- Watchdog Mode Register -ST_RTMR # 4 ;- Real-time Mode Register -ST_SR # 4 ;- Status Register -ST_IER # 4 ;- Interrupt Enable Register -ST_IDR # 4 ;- Interrupt Disable Register -ST_IMR # 4 ;- Interrupt Mask Register -ST_RTAR # 4 ;- Real-time Alarm Register -ST_CRTR # 4 ;- Current Real-time Register -;- -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- -AT91C_ST_WDRST EQU (0x1:SHL:0) ;- (ST) Watchdog Timer Restart -;- -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- -AT91C_ST_PIV EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart -;- -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- -AT91C_ST_WDV EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart -AT91C_ST_RSTEN EQU (0x1:SHL:16) ;- (ST) Reset Enable -AT91C_ST_EXTEN EQU (0x1:SHL:17) ;- (ST) External Signal Assertion Enable -;- -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- -AT91C_ST_RTPRES EQU (0xFFFF:SHL:0) ;- (ST) Real-time Timer Prescaler Value -;- -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- -AT91C_ST_PITS EQU (0x1:SHL:0) ;- (ST) Period Interval Timer Interrupt -AT91C_ST_WDOVF EQU (0x1:SHL:1) ;- (ST) Watchdog Overflow -AT91C_ST_RTTINC EQU (0x1:SHL:2) ;- (ST) Real-time Timer Increment -AT91C_ST_ALMS EQU (0x1:SHL:3) ;- (ST) Alarm Status -;- -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- -;- -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- -;- -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- -;- -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- -AT91C_ST_ALMV EQU (0xFFFFF:SHL:0) ;- (ST) Alarm Value Value -;- -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- -AT91C_ST_CRTV EQU (0xFFFFF:SHL:0) ;- (ST) Current Real-time Value - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Power Management Controler -;- ***************************************************************************** - ^ 0 ;- AT91S_PMC -PMC_SCER # 4 ;- System Clock Enable Register -PMC_SCDR # 4 ;- System Clock Disable Register -PMC_SCSR # 4 ;- System Clock Status Register - # 4 ;- Reserved -PMC_PCER # 4 ;- Peripheral Clock Enable Register -PMC_PCDR # 4 ;- Peripheral Clock Disable Register -PMC_PCSR # 4 ;- Peripheral Clock Status Register - # 20 ;- Reserved -PMC_MCKR # 4 ;- Master Clock Register - # 12 ;- Reserved -PMC_PCKR # 32 ;- Programmable Clock Register -PMC_IER # 4 ;- Interrupt Enable Register -PMC_IDR # 4 ;- Interrupt Disable Register -PMC_SR # 4 ;- Status Register -PMC_IMR # 4 ;- Interrupt Mask Register -;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -AT91C_PMC_PCK EQU (0x1:SHL:0) ;- (PMC) Processor Clock -AT91C_PMC_UDP EQU (0x1:SHL:1) ;- (PMC) USB Device Port Clock -AT91C_PMC_MCKUDP EQU (0x1:SHL:2) ;- (PMC) USB Device Port Master Clock Automatic Disable on Suspend -AT91C_PMC_UHP EQU (0x1:SHL:4) ;- (PMC) USB Host Port Clock -AT91C_PMC_PCK0 EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK1 EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK2 EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK3 EQU (0x1:SHL:11) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK4 EQU (0x1:SHL:12) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK5 EQU (0x1:SHL:13) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK6 EQU (0x1:SHL:14) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK7 EQU (0x1:SHL:15) ;- (PMC) Programmable Clock Output -;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -AT91C_PMC_CSS EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection -AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected -AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected -AT91C_PMC_CSS_PLLA_CLK EQU (0x2) ;- (PMC) Clock from PLL A is selected -AT91C_PMC_CSS_PLLB_CLK EQU (0x3) ;- (PMC) Clock from PLL B is selected -AT91C_PMC_PRES EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler -AT91C_PMC_PRES_CLK EQU (0x0:SHL:2) ;- (PMC) Selected clock -AT91C_PMC_PRES_CLK_2 EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2 -AT91C_PMC_PRES_CLK_4 EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4 -AT91C_PMC_PRES_CLK_8 EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8 -AT91C_PMC_PRES_CLK_16 EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16 -AT91C_PMC_PRES_CLK_32 EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32 -AT91C_PMC_PRES_CLK_64 EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64 -AT91C_PMC_MDIV EQU (0x3:SHL:8) ;- (PMC) Master Clock Division -AT91C_PMC_MDIV_1 EQU (0x0:SHL:8) ;- (PMC) The master clock and the processor clock are the same -AT91C_PMC_MDIV_2 EQU (0x1:SHL:8) ;- (PMC) The processor clock is twice as fast as the master clock -AT91C_PMC_MDIV_3 EQU (0x2:SHL:8) ;- (PMC) The processor clock is three times faster than the master clock -AT91C_PMC_MDIV_4 EQU (0x3:SHL:8) ;- (PMC) The processor clock is four times faster than the master clock -;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -AT91C_PMC_MOSCS EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask -AT91C_PMC_LOCKA EQU (0x1:SHL:1) ;- (PMC) PLL A Status/Enable/Disable/Mask -AT91C_PMC_LOCKB EQU (0x1:SHL:2) ;- (PMC) PLL B Status/Enable/Disable/Mask -AT91C_PMC_MCKRDY EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK0RDY EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK1RDY EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK2RDY EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK3RDY EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK4RDY EQU (0x1:SHL:12) ;- (PMC) PCK4_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK5RDY EQU (0x1:SHL:13) ;- (PMC) PCK5_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK6RDY EQU (0x1:SHL:14) ;- (PMC) PCK6_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK7RDY EQU (0x1:SHL:15) ;- (PMC) PCK7_RDY Status/Enable/Disable/Mask -;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Clock Generator Controler -;- ***************************************************************************** - ^ 0 ;- AT91S_CKGR -CKGR_MOR # 4 ;- Main Oscillator Register -CKGR_MCFR # 4 ;- Main Clock Frequency Register -CKGR_PLLAR # 4 ;- PLL A Register -CKGR_PLLBR # 4 ;- PLL B Register -;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -AT91C_CKGR_MOSCEN EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable -AT91C_CKGR_OSCTEST EQU (0x1:SHL:1) ;- (CKGR) Oscillator Test -AT91C_CKGR_OSCOUNT EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time -;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -AT91C_CKGR_MAINF EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency -AT91C_CKGR_MAINRDY EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready -;- -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- -AT91C_CKGR_DIVA EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIVA_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIVA_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLACOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL A Counter -AT91C_CKGR_OUTA EQU (0x3:SHL:14) ;- (CKGR) PLL A Output Frequency Range -AT91C_CKGR_OUTA_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet -AT91C_CKGR_OUTA_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet -AT91C_CKGR_OUTA_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet -AT91C_CKGR_OUTA_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet -AT91C_CKGR_MULA EQU (0x7FF:SHL:16) ;- (CKGR) PLL A Multiplier -AT91C_CKGR_SRCA EQU (0x1:SHL:29) ;- (CKGR) PLL A Source -;- -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- -AT91C_CKGR_DIVB EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIVB_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIVB_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLBCOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL B Counter -AT91C_CKGR_OUTB EQU (0x3:SHL:14) ;- (CKGR) PLL B Output Frequency Range -AT91C_CKGR_OUTB_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet -AT91C_CKGR_OUTB_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet -AT91C_CKGR_OUTB_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet -AT91C_CKGR_OUTB_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet -AT91C_CKGR_MULB EQU (0x7FF:SHL:16) ;- (CKGR) PLL B Multiplier -AT91C_CKGR_USB_96M EQU (0x1:SHL:28) ;- (CKGR) Divider for USB Ports -AT91C_CKGR_USB_PLL EQU (0x1:SHL:29) ;- (CKGR) PLL Use - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler -;- ***************************************************************************** - ^ 0 ;- AT91S_PIO -PIO_PER # 4 ;- PIO Enable Register -PIO_PDR # 4 ;- PIO Disable Register -PIO_PSR # 4 ;- PIO Status Register - # 4 ;- Reserved -PIO_OER # 4 ;- Output Enable Register -PIO_ODR # 4 ;- Output Disable Registerr -PIO_OSR # 4 ;- Output Status Register - # 4 ;- Reserved -PIO_IFER # 4 ;- Input Filter Enable Register -PIO_IFDR # 4 ;- Input Filter Disable Register -PIO_IFSR # 4 ;- Input Filter Status Register - # 4 ;- Reserved -PIO_SODR # 4 ;- Set Output Data Register -PIO_CODR # 4 ;- Clear Output Data Register -PIO_ODSR # 4 ;- Output Data Status Register -PIO_PDSR # 4 ;- Pin Data Status Register -PIO_IER # 4 ;- Interrupt Enable Register -PIO_IDR # 4 ;- Interrupt Disable Register -PIO_IMR # 4 ;- Interrupt Mask Register -PIO_ISR # 4 ;- Interrupt Status Register -PIO_MDER # 4 ;- Multi-driver Enable Register -PIO_MDDR # 4 ;- Multi-driver Disable Register -PIO_MDSR # 4 ;- Multi-driver Status Register - # 4 ;- Reserved -PIO_PPUDR # 4 ;- Pull-up Disable Register -PIO_PPUER # 4 ;- Pull-up Enable Register -PIO_PPUSR # 4 ;- Pad Pull-up Status Register - # 4 ;- Reserved -PIO_ASR # 4 ;- Select A Register -PIO_BSR # 4 ;- Select B Register -PIO_ABSR # 4 ;- AB Select Status Register - # 36 ;- Reserved -PIO_OWER # 4 ;- Output Write Enable Register -PIO_OWDR # 4 ;- Output Write Disable Register -PIO_OWSR # 4 ;- Output Write Status Register - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Debug Unit -;- ***************************************************************************** - ^ 0 ;- AT91S_DBGU -DBGU_CR # 4 ;- Control Register -DBGU_MR # 4 ;- Mode Register -DBGU_IER # 4 ;- Interrupt Enable Register -DBGU_IDR # 4 ;- Interrupt Disable Register -DBGU_IMR # 4 ;- Interrupt Mask Register -DBGU_CSR # 4 ;- Channel Status Register -DBGU_RHR # 4 ;- Receiver Holding Register -DBGU_THR # 4 ;- Transmitter Holding Register -DBGU_BRGR # 4 ;- Baud Rate Generator Register - # 28 ;- Reserved -DBGU_C1R # 4 ;- Chip ID1 Register -DBGU_C2R # 4 ;- Chip ID2 Register -DBGU_FNTR # 4 ;- Force NTRST Register - # 180 ;- Reserved -DBGU_RPR # 4 ;- Receive Pointer Register -DBGU_RCR # 4 ;- Receive Counter Register -DBGU_TPR # 4 ;- Transmit Pointer Register -DBGU_TCR # 4 ;- Transmit Counter Register -DBGU_RNPR # 4 ;- Receive Next Pointer Register -DBGU_RNCR # 4 ;- Receive Next Counter Register -DBGU_TNPR # 4 ;- Transmit Next Pointer Register -DBGU_TNCR # 4 ;- Transmit Next Counter Register -DBGU_PTCR # 4 ;- PDC Transfer Control Register -DBGU_PTSR # 4 ;- PDC Transfer Status Register -;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver -AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter -AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable -AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable -AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable -AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable -;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type -AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity -AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity -AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space) -AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark) -AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity -AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode -AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode -AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt -AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt -AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt -AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt -AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt -AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt -AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt -AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt -AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt -AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt -AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt -AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt -;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Peripheral Data Controller -;- ***************************************************************************** - ^ 0 ;- AT91S_PDC -PDC_RPR # 4 ;- Receive Pointer Register -PDC_RCR # 4 ;- Receive Counter Register -PDC_TPR # 4 ;- Transmit Pointer Register -PDC_TCR # 4 ;- Transmit Counter Register -PDC_RNPR # 4 ;- Receive Next Pointer Register -PDC_RNCR # 4 ;- Receive Next Counter Register -PDC_TNPR # 4 ;- Transmit Next Pointer Register -PDC_TNCR # 4 ;- Transmit Next Counter Register -PDC_PTCR # 4 ;- PDC Transfer Control Register -PDC_PTSR # 4 ;- PDC Transfer Status Register -;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable -AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable -AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable -AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable -;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -;- ***************************************************************************** - ^ 0 ;- AT91S_AIC -AIC_SMR # 128 ;- Source Mode Register -AIC_SVR # 128 ;- Source Vector Register -AIC_IVR # 4 ;- IRQ Vector Register -AIC_FVR # 4 ;- FIQ Vector Register -AIC_ISR # 4 ;- Interrupt Status Register -AIC_IPR # 4 ;- Interrupt Pending Register -AIC_IMR # 4 ;- Interrupt Mask Register -AIC_CISR # 4 ;- Core Interrupt Status Register - # 8 ;- Reserved -AIC_IECR # 4 ;- Interrupt Enable Command Register -AIC_IDCR # 4 ;- Interrupt Disable Command Register -AIC_ICCR # 4 ;- Interrupt Clear Command Register -AIC_ISCR # 4 ;- Interrupt Set Command Register -AIC_EOICR # 4 ;- End of Interrupt Command Register -AIC_SPU # 4 ;- Spurious Vector Register -AIC_DCR # 4 ;- Debug Control Register (Protect) - # 4 ;- Reserved -AIC_FFER # 4 ;- Fast Forcing Enable Register -AIC_FFDR # 4 ;- Fast Forcing Disable Register -AIC_FFSR # 4 ;- Fast Forcing Status Register -;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level -AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level -AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level -AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type -AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive -AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered -AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered -;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status -AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status -;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection Mode -AT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Serial Parallel Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_SPI -SPI_CR # 4 ;- Control Register -SPI_MR # 4 ;- Mode Register -SPI_RDR # 4 ;- Receive Data Register -SPI_TDR # 4 ;- Transmit Data Register -SPI_SR # 4 ;- Status Register -SPI_IER # 4 ;- Interrupt Enable Register -SPI_IDR # 4 ;- Interrupt Disable Register -SPI_IMR # 4 ;- Interrupt Mask Register - # 16 ;- Reserved -SPI_CSR # 16 ;- Chip Select Register - # 192 ;- Reserved -SPI_RPR # 4 ;- Receive Pointer Register -SPI_RCR # 4 ;- Receive Counter Register -SPI_TPR # 4 ;- Transmit Pointer Register -SPI_TCR # 4 ;- Transmit Counter Register -SPI_RNPR # 4 ;- Receive Next Pointer Register -SPI_RNCR # 4 ;- Receive Next Counter Register -SPI_TNPR # 4 ;- Transmit Next Pointer Register -SPI_TNCR # 4 ;- Transmit Next Counter Register -SPI_PTCR # 4 ;- PDC Transfer Control Register -SPI_PTSR # 4 ;- PDC Transfer Status Register -;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI Enable -AT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI Disable -AT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset -;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode -AT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral Select -AT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select -AT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select -AT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode -AT91C_SPI_DIV32 EQU (0x1:SHL:3) ;- (SPI) Clock Selection -AT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection -AT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock Selection -AT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select -AT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects -;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data -AT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status -;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data -AT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status -;- -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full -AT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty -AT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error -AT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status -AT91C_SPI_SPENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer -AT91C_SPI_SPENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer -AT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt -AT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt -AT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status -;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock Polarity -AT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock Phase -AT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer -AT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer -AT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer -AT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer -AT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer -AT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer -AT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer -AT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer -AT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer -AT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer -AT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_SSC -SSC_CR # 4 ;- Control Register -SSC_CMR # 4 ;- Clock Mode Register - # 8 ;- Reserved -SSC_RCMR # 4 ;- Receive Clock ModeRegister -SSC_RFMR # 4 ;- Receive Frame Mode Register -SSC_TCMR # 4 ;- Transmit Clock Mode Register -SSC_TFMR # 4 ;- Transmit Frame Mode Register -SSC_RHR # 4 ;- Receive Holding Register -SSC_THR # 4 ;- Transmit Holding Register - # 8 ;- Reserved -SSC_RSHR # 4 ;- Receive Sync Holding Register -SSC_TSHR # 4 ;- Transmit Sync Holding Register -SSC_RC0R # 4 ;- Receive Compare 0 Register -SSC_RC1R # 4 ;- Receive Compare 1 Register -SSC_SR # 4 ;- Status Register -SSC_IER # 4 ;- Interrupt Enable Register -SSC_IDR # 4 ;- Interrupt Disable Register -SSC_IMR # 4 ;- Interrupt Mask Register - # 176 ;- Reserved -SSC_RPR # 4 ;- Receive Pointer Register -SSC_RCR # 4 ;- Receive Counter Register -SSC_TPR # 4 ;- Transmit Pointer Register -SSC_TCR # 4 ;- Transmit Counter Register -SSC_RNPR # 4 ;- Receive Next Pointer Register -SSC_RNCR # 4 ;- Receive Next Counter Register -SSC_TNPR # 4 ;- Transmit Next Pointer Register -SSC_TNCR # 4 ;- Transmit Next Counter Register -SSC_PTCR # 4 ;- PDC Transfer Control Register -SSC_PTSR # 4 ;- PDC Transfer Status Register -;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive Enable -AT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable -AT91C_SSC_TXEN EQU (0x1:SHL:8) ;- (SSC) Transmit Enable -AT91C_SSC_TXDIS EQU (0x1:SHL:9) ;- (SSC) Transmit Disable -AT91C_SSC_SWRST EQU (0x1:SHL:15) ;- (SSC) Software Reset -;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -AT91C_SSC_CKS EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection -AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock -AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal -AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin -AT91C_SSC_CKO EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection -AT91C_SSC_CKO_NONE EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -AT91C_SSC_CKO_CONTINOUS EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output -AT91C_SSC_CKO_DATA_TX EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -AT91C_SSC_CKI EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion -AT91C_SSC_CKG EQU (0x3:SHL:6) ;- (SSC) Receive/Transmit Clock Gating Selection -AT91C_SSC_CKG_NONE EQU (0x0:SHL:6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock -AT91C_SSC_CKG_LOW EQU (0x1:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low -AT91C_SSC_CKG_HIGH EQU (0x2:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF High -AT91C_SSC_START EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection -AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -AT91C_SSC_START_TX EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start -AT91C_SSC_START_LOW_RF EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input -AT91C_SSC_START_HIGH_RF EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input -AT91C_SSC_START_FALL_RF EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input -AT91C_SSC_START_RISE_RF EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input -AT91C_SSC_START_LEVEL_RF EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input -AT91C_SSC_START_EDGE_RF EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input -AT91C_SSC_START_0 EQU (0x8:SHL:8) ;- (SSC) Compare 0 -AT91C_SSC_STOP EQU (0x1:SHL:12) ;- (SSC) Receive Stop Selection -AT91C_SSC_STTOUT EQU (0x1:SHL:15) ;- (SSC) Receive/Transmit Start Output Selection -AT91C_SSC_STTDLY EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay -AT91C_SSC_PERIOD EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection -;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -AT91C_SSC_DATLEN EQU (0x1F:SHL:0) ;- (SSC) Data Length -AT91C_SSC_LOOP EQU (0x1:SHL:5) ;- (SSC) Loop Mode -AT91C_SSC_MSBF EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First -AT91C_SSC_DATNB EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame -AT91C_SSC_FSLEN EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length -AT91C_SSC_FSOS EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection -AT91C_SSC_FSOS_NONE EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -AT91C_SSC_FSOS_NEGATIVE EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -AT91C_SSC_FSOS_POSITIVE EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -AT91C_SSC_FSOS_LOW EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -AT91C_SSC_FSOS_HIGH EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -AT91C_SSC_FSOS_TOGGLE EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -AT91C_SSC_FSEDGE EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection -;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -AT91C_SSC_DATDEF EQU (0x1:SHL:5) ;- (SSC) Data Default Value -AT91C_SSC_FSDEN EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable -;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -AT91C_SSC_TXRDY EQU (0x1:SHL:0) ;- (SSC) Transmit Ready -AT91C_SSC_TXEMPTY EQU (0x1:SHL:1) ;- (SSC) Transmit Empty -AT91C_SSC_ENDTX EQU (0x1:SHL:2) ;- (SSC) End Of Transmission -AT91C_SSC_TXBUFE EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty -AT91C_SSC_RXRDY EQU (0x1:SHL:4) ;- (SSC) Receive Ready -AT91C_SSC_OVRUN EQU (0x1:SHL:5) ;- (SSC) Receive Overrun -AT91C_SSC_ENDRX EQU (0x1:SHL:6) ;- (SSC) End of Reception -AT91C_SSC_RXBUFF EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full -AT91C_SSC_CP0 EQU (0x1:SHL:8) ;- (SSC) Compare 0 -AT91C_SSC_CP1 EQU (0x1:SHL:9) ;- (SSC) Compare 1 -AT91C_SSC_TXSYN EQU (0x1:SHL:10) ;- (SSC) Transmit Sync -AT91C_SSC_RXSYN EQU (0x1:SHL:11) ;- (SSC) Receive Sync -AT91C_SSC_TXENA EQU (0x1:SHL:16) ;- (SSC) Transmit Enable -AT91C_SSC_RXENA EQU (0x1:SHL:17) ;- (SSC) Receive Enable -;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Usart -;- ***************************************************************************** - ^ 0 ;- AT91S_USART -US_CR # 4 ;- Control Register -US_MR # 4 ;- Mode Register -US_IER # 4 ;- Interrupt Enable Register -US_IDR # 4 ;- Interrupt Disable Register -US_IMR # 4 ;- Interrupt Mask Register -US_CSR # 4 ;- Channel Status Register -US_RHR # 4 ;- Receiver Holding Register -US_THR # 4 ;- Transmitter Holding Register -US_BRGR # 4 ;- Baud Rate Generator Register -US_RTOR # 4 ;- Receiver Time-out Register -US_TTGR # 4 ;- Transmitter Time-guard Register - # 20 ;- Reserved -US_FIDI # 4 ;- FI_DI_Ratio Register -US_NER # 4 ;- Nb Errors Register -US_XXR # 4 ;- XON_XOFF Register -US_IF # 4 ;- IRDA_FILTER Register - # 176 ;- Reserved -US_RPR # 4 ;- Receive Pointer Register -US_RCR # 4 ;- Receive Counter Register -US_TPR # 4 ;- Transmit Pointer Register -US_TCR # 4 ;- Transmit Counter Register -US_RNPR # 4 ;- Receive Next Pointer Register -US_RNCR # 4 ;- Receive Next Counter Register -US_TNPR # 4 ;- Transmit Next Pointer Register -US_TNCR # 4 ;- Transmit Next Counter Register -US_PTCR # 4 ;- PDC Transfer Control Register -US_PTSR # 4 ;- PDC Transfer Status Register -;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (USART) Reset Status Bits -AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break -AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break -AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out -AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address -AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations -AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge -AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out -AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable -AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable -AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable -AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable -;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode -AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal -AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 -AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking -AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem -AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 -AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 -AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA -AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking -AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock -AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1 -AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM) -AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK) -AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits -AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits -AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits -AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits -AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select -AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits -AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit -AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits -AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order -AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length -AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select -AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode -AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge -AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK -AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions -AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter -;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break -AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out -AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached -AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge -AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag -AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag -AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag -AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag -;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input -AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input -AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input -AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Two-wire Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_TWI -TWI_CR # 4 ;- Control Register -TWI_MMR # 4 ;- Master Mode Register -TWI_SMR # 4 ;- Slave Mode Register -TWI_IADR # 4 ;- Internal Address Register -TWI_CWGR # 4 ;- Clock Waveform Generator Register - # 12 ;- Reserved -TWI_SR # 4 ;- Status Register -TWI_IER # 4 ;- Interrupt Enable Register -TWI_IDR # 4 ;- Interrupt Disable Register -TWI_IMR # 4 ;- Interrupt Mask Register -TWI_RHR # 4 ;- Receive Holding Register -TWI_THR # 4 ;- Transmit Holding Register -;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -AT91C_TWI_START EQU (0x1:SHL:0) ;- (TWI) Send a START Condition -AT91C_TWI_STOP EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition -AT91C_TWI_MSEN EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled -AT91C_TWI_MSDIS EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled -AT91C_TWI_SVEN EQU (0x1:SHL:4) ;- (TWI) TWI Slave Transfer Enabled -AT91C_TWI_SVDIS EQU (0x1:SHL:5) ;- (TWI) TWI Slave Transfer Disabled -AT91C_TWI_SWRST EQU (0x1:SHL:7) ;- (TWI) Software Reset -;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -AT91C_TWI_IADRSZ EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size -AT91C_TWI_IADRSZ_NO EQU (0x0:SHL:8) ;- (TWI) No internal device address -AT91C_TWI_IADRSZ_1_BYTE EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address -AT91C_TWI_IADRSZ_2_BYTE EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address -AT91C_TWI_IADRSZ_3_BYTE EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address -AT91C_TWI_MREAD EQU (0x1:SHL:12) ;- (TWI) Master Read Direction -AT91C_TWI_DADR EQU (0x7F:SHL:16) ;- (TWI) Device Address -;- -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -AT91C_TWI_SADR EQU (0x7F:SHL:16) ;- (TWI) Slave Device Address -;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -AT91C_TWI_CLDIV EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider -AT91C_TWI_CHDIV EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider -AT91C_TWI_CKDIV EQU (0x7:SHL:16) ;- (TWI) Clock Divider -;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -AT91C_TWI_TXCOMP EQU (0x1:SHL:0) ;- (TWI) Transmission Completed -AT91C_TWI_RXRDY EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY -AT91C_TWI_TXRDY EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY -AT91C_TWI_SVREAD EQU (0x1:SHL:3) ;- (TWI) Slave Read -AT91C_TWI_SVACC EQU (0x1:SHL:4) ;- (TWI) Slave Access -AT91C_TWI_GCACC EQU (0x1:SHL:5) ;- (TWI) General Call Access -AT91C_TWI_OVRE EQU (0x1:SHL:6) ;- (TWI) Overrun Error -AT91C_TWI_UNRE EQU (0x1:SHL:7) ;- (TWI) Underrun Error -AT91C_TWI_NACK EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged -AT91C_TWI_ARBLST EQU (0x1:SHL:9) ;- (TWI) Arbitration Lost -;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Multimedia Card Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_MCI -MCI_CR # 4 ;- MCI Control Register -MCI_MR # 4 ;- MCI Mode Register -MCI_DTOR # 4 ;- MCI Data Timeout Register -MCI_SDCR # 4 ;- MCI SD Card Register -MCI_ARGR # 4 ;- MCI Argument Register -MCI_CMDR # 4 ;- MCI Command Register - # 8 ;- Reserved -MCI_RSPR # 16 ;- MCI Response Register -MCI_RDR # 4 ;- MCI Receive Data Register -MCI_TDR # 4 ;- MCI Transmit Data Register - # 8 ;- Reserved -MCI_SR # 4 ;- MCI Status Register -MCI_IER # 4 ;- MCI Interrupt Enable Register -MCI_IDR # 4 ;- MCI Interrupt Disable Register -MCI_IMR # 4 ;- MCI Interrupt Mask Register - # 176 ;- Reserved -MCI_RPR # 4 ;- Receive Pointer Register -MCI_RCR # 4 ;- Receive Counter Register -MCI_TPR # 4 ;- Transmit Pointer Register -MCI_TCR # 4 ;- Transmit Counter Register -MCI_RNPR # 4 ;- Receive Next Pointer Register -MCI_RNCR # 4 ;- Receive Next Counter Register -MCI_TNPR # 4 ;- Transmit Next Pointer Register -MCI_TNCR # 4 ;- Transmit Next Counter Register -MCI_PTCR # 4 ;- PDC Transfer Control Register -MCI_PTSR # 4 ;- PDC Transfer Status Register -;- -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- -AT91C_MCI_MCIEN EQU (0x1:SHL:0) ;- (MCI) Multimedia Interface Enable -AT91C_MCI_MCIDIS EQU (0x1:SHL:1) ;- (MCI) Multimedia Interface Disable -AT91C_MCI_PWSEN EQU (0x1:SHL:2) ;- (MCI) Power Save Mode Enable -AT91C_MCI_PWSDIS EQU (0x1:SHL:3) ;- (MCI) Power Save Mode Disable -;- -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- -AT91C_MCI_CLKDIV EQU (0x1:SHL:0) ;- (MCI) Clock Divider -AT91C_MCI_PWSDIV EQU (0x1:SHL:8) ;- (MCI) Power Saving Divider -AT91C_MCI_PDCPADV EQU (0x1:SHL:14) ;- (MCI) PDC Padding Value -AT91C_MCI_PDCMODE EQU (0x1:SHL:15) ;- (MCI) PDC Oriented Mode -AT91C_MCI_BLKLEN EQU (0x1:SHL:18) ;- (MCI) Data Block Length -;- -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- -AT91C_MCI_DTOCYC EQU (0x1:SHL:0) ;- (MCI) Data Timeout Cycle Number -AT91C_MCI_DTOMUL EQU (0x7:SHL:4) ;- (MCI) Data Timeout Multiplier -AT91C_MCI_DTOMUL_1 EQU (0x0:SHL:4) ;- (MCI) DTOCYC x 1 -AT91C_MCI_DTOMUL_16 EQU (0x1:SHL:4) ;- (MCI) DTOCYC x 16 -AT91C_MCI_DTOMUL_128 EQU (0x2:SHL:4) ;- (MCI) DTOCYC x 128 -AT91C_MCI_DTOMUL_256 EQU (0x3:SHL:4) ;- (MCI) DTOCYC x 256 -AT91C_MCI_DTOMUL_1024 EQU (0x4:SHL:4) ;- (MCI) DTOCYC x 1024 -AT91C_MCI_DTOMUL_4096 EQU (0x5:SHL:4) ;- (MCI) DTOCYC x 4096 -AT91C_MCI_DTOMUL_65536 EQU (0x6:SHL:4) ;- (MCI) DTOCYC x 65536 -AT91C_MCI_DTOMUL_1048576 EQU (0x7:SHL:4) ;- (MCI) DTOCYC x 1048576 -;- -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- -AT91C_MCI_SCDSEL EQU (0x1:SHL:0) ;- (MCI) SD Card Selector -AT91C_MCI_SCDBUS EQU (0x1:SHL:7) ;- (MCI) SD Card Bus Width -;- -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- -AT91C_MCI_CMDNB EQU (0x1F:SHL:0) ;- (MCI) Command Number -AT91C_MCI_RSPTYP EQU (0x3:SHL:6) ;- (MCI) Response Type -AT91C_MCI_RSPTYP_NO EQU (0x0:SHL:6) ;- (MCI) No response -AT91C_MCI_RSPTYP_48 EQU (0x1:SHL:6) ;- (MCI) 48-bit response -AT91C_MCI_RSPTYP_136 EQU (0x2:SHL:6) ;- (MCI) 136-bit response -AT91C_MCI_SPCMD EQU (0x7:SHL:8) ;- (MCI) Special CMD -AT91C_MCI_SPCMD_NONE EQU (0x0:SHL:8) ;- (MCI) Not a special CMD -AT91C_MCI_SPCMD_INIT EQU (0x1:SHL:8) ;- (MCI) Initialization CMD -AT91C_MCI_SPCMD_SYNC EQU (0x2:SHL:8) ;- (MCI) Synchronized CMD -AT91C_MCI_SPCMD_IT_CMD EQU (0x4:SHL:8) ;- (MCI) Interrupt command -AT91C_MCI_SPCMD_IT_REP EQU (0x5:SHL:8) ;- (MCI) Interrupt response -AT91C_MCI_OPDCMD EQU (0x1:SHL:11) ;- (MCI) Open Drain Command -AT91C_MCI_MAXLAT EQU (0x1:SHL:12) ;- (MCI) Maximum Latency for Command to respond -AT91C_MCI_TRCMD EQU (0x3:SHL:16) ;- (MCI) Transfer CMD -AT91C_MCI_TRCMD_NO EQU (0x0:SHL:16) ;- (MCI) No transfer -AT91C_MCI_TRCMD_START EQU (0x1:SHL:16) ;- (MCI) Start transfer -AT91C_MCI_TRCMD_STOP EQU (0x2:SHL:16) ;- (MCI) Stop transfer -AT91C_MCI_TRDIR EQU (0x1:SHL:18) ;- (MCI) Transfer Direction -AT91C_MCI_TRTYP EQU (0x3:SHL:19) ;- (MCI) Transfer Type -AT91C_MCI_TRTYP_BLOCK EQU (0x0:SHL:19) ;- (MCI) Block Transfer type -AT91C_MCI_TRTYP_MULTIPLE EQU (0x1:SHL:19) ;- (MCI) Multiple Block transfer type -AT91C_MCI_TRTYP_STREAM EQU (0x2:SHL:19) ;- (MCI) Stream transfer type -;- -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- -AT91C_MCI_CMDRDY EQU (0x1:SHL:0) ;- (MCI) Command Ready flag -AT91C_MCI_RXRDY EQU (0x1:SHL:1) ;- (MCI) RX Ready flag -AT91C_MCI_TXRDY EQU (0x1:SHL:2) ;- (MCI) TX Ready flag -AT91C_MCI_BLKE EQU (0x1:SHL:3) ;- (MCI) Data Block Transfer Ended flag -AT91C_MCI_DTIP EQU (0x1:SHL:4) ;- (MCI) Data Transfer in Progress flag -AT91C_MCI_NOTBUSY EQU (0x1:SHL:5) ;- (MCI) Data Line Not Busy flag -AT91C_MCI_ENDRX EQU (0x1:SHL:6) ;- (MCI) End of RX Buffer flag -AT91C_MCI_ENDTX EQU (0x1:SHL:7) ;- (MCI) End of TX Buffer flag -AT91C_MCI_RXBUFF EQU (0x1:SHL:14) ;- (MCI) RX Buffer Full flag -AT91C_MCI_TXBUFE EQU (0x1:SHL:15) ;- (MCI) TX Buffer Empty flag -AT91C_MCI_RINDE EQU (0x1:SHL:16) ;- (MCI) Response Index Error flag -AT91C_MCI_RDIRE EQU (0x1:SHL:17) ;- (MCI) Response Direction Error flag -AT91C_MCI_RCRCE EQU (0x1:SHL:18) ;- (MCI) Response CRC Error flag -AT91C_MCI_RENDE EQU (0x1:SHL:19) ;- (MCI) Response End Bit Error flag -AT91C_MCI_RTOE EQU (0x1:SHL:20) ;- (MCI) Response Time-out Error flag -AT91C_MCI_DCRCE EQU (0x1:SHL:21) ;- (MCI) data CRC Error flag -AT91C_MCI_DTOE EQU (0x1:SHL:22) ;- (MCI) Data timeout Error flag -AT91C_MCI_OVRE EQU (0x1:SHL:30) ;- (MCI) Overrun flag -AT91C_MCI_UNRE EQU (0x1:SHL:31) ;- (MCI) Underrun flag -;- -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- -;- -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- -;- -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR USB Device Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_UDP -UDP_NUM # 4 ;- Frame Number Register -UDP_GLBSTATE # 4 ;- Global State Register -UDP_FADDR # 4 ;- Function Address Register - # 4 ;- Reserved -UDP_IER # 4 ;- Interrupt Enable Register -UDP_IDR # 4 ;- Interrupt Disable Register -UDP_IMR # 4 ;- Interrupt Mask Register -UDP_ISR # 4 ;- Interrupt Status Register -UDP_ICR # 4 ;- Interrupt Clear Register - # 4 ;- Reserved -UDP_RSTEP # 4 ;- Reset Endpoint Register - # 4 ;- Reserved -UDP_CSR # 32 ;- Endpoint Control and Status Register -UDP_FDR # 32 ;- Endpoint FIFO Data Register -;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -AT91C_UDP_FRM_NUM EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats -AT91C_UDP_FRM_ERR EQU (0x1:SHL:16) ;- (UDP) Frame Error -AT91C_UDP_FRM_OK EQU (0x1:SHL:17) ;- (UDP) Frame OK -;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -AT91C_UDP_FADDEN EQU (0x1:SHL:0) ;- (UDP) Function Address Enable -AT91C_UDP_CONFG EQU (0x1:SHL:1) ;- (UDP) Configured -AT91C_UDP_RMWUPE EQU (0x1:SHL:2) ;- (UDP) Remote Wake Up Enable -AT91C_UDP_RSMINPR EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host -;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -AT91C_UDP_FADD EQU (0xFF:SHL:0) ;- (UDP) Function Address Value -AT91C_UDP_FEN EQU (0x1:SHL:8) ;- (UDP) Function Enable -;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -AT91C_UDP_EPINT0 EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT1 EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT2 EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt -AT91C_UDP_EPINT3 EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt -AT91C_UDP_EPINT4 EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 Interrupt -AT91C_UDP_EPINT5 EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 Interrupt -AT91C_UDP_EPINT6 EQU (0x1:SHL:6) ;- (UDP) Endpoint 6 Interrupt -AT91C_UDP_EPINT7 EQU (0x1:SHL:7) ;- (UDP) Endpoint 7 Interrupt -AT91C_UDP_RXSUSP EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt -AT91C_UDP_RXRSM EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt -AT91C_UDP_EXTRSM EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt -AT91C_UDP_SOFINT EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt -AT91C_UDP_WAKEUP EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt -;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -AT91C_UDP_ENDBUSRES EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt -;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -AT91C_UDP_EP0 EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0 -AT91C_UDP_EP1 EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1 -AT91C_UDP_EP2 EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2 -AT91C_UDP_EP3 EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3 -AT91C_UDP_EP4 EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4 -AT91C_UDP_EP5 EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5 -AT91C_UDP_EP6 EQU (0x1:SHL:6) ;- (UDP) Reset Endpoint 6 -AT91C_UDP_EP7 EQU (0x1:SHL:7) ;- (UDP) Reset Endpoint 7 -;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -AT91C_UDP_TXCOMP EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR -AT91C_UDP_RX_DATA_BK0 EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0 -AT91C_UDP_RXSETUP EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints) -AT91C_UDP_ISOERROR EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints) -AT91C_UDP_TXPKTRDY EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready -AT91C_UDP_FORCESTALL EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -AT91C_UDP_RX_DATA_BK1 EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -AT91C_UDP_DIR EQU (0x1:SHL:7) ;- (UDP) Transfer Direction -AT91C_UDP_EPTYPE EQU (0x7:SHL:8) ;- (UDP) Endpoint type -AT91C_UDP_EPTYPE_CTRL EQU (0x0:SHL:8) ;- (UDP) Control -AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1:SHL:8) ;- (UDP) Isochronous OUT -AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUT -AT91C_UDP_EPTYPE_INT_OUT EQU (0x3:SHL:8) ;- (UDP) Interrupt OUT -AT91C_UDP_EPTYPE_ISO_IN EQU (0x5:SHL:8) ;- (UDP) Isochronous IN -AT91C_UDP_EPTYPE_BULK_IN EQU (0x6:SHL:8) ;- (UDP) Bulk IN -AT91C_UDP_EPTYPE_INT_IN EQU (0x7:SHL:8) ;- (UDP) Interrupt IN -AT91C_UDP_DTGLE EQU (0x1:SHL:11) ;- (UDP) Data Toggle -AT91C_UDP_EPEDS EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable Disable -AT91C_UDP_RXBYTECNT EQU (0x7FF:SHL:16) ;- (UDP) Number Of Bytes Available in the FIFO - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_TC -TC_CCR # 4 ;- Channel Control Register -TC_CMR # 4 ;- Channel Mode Register - # 8 ;- Reserved -TC_CV # 4 ;- Counter Value -TC_RA # 4 ;- Register A -TC_RB # 4 ;- Register B -TC_RC # 4 ;- Register C -TC_SR # 4 ;- Status Register -TC_IER # 4 ;- Interrupt Enable Register -TC_IDR # 4 ;- Interrupt Disable Register -TC_IMR # 4 ;- Interrupt Mask Register -;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -AT91C_TC_CLKEN EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command -AT91C_TC_CLKDIS EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command -AT91C_TC_SWTRG EQU (0x1:SHL:2) ;- (TC) Software Trigger Command -;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -AT91C_TC_CPCSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare -AT91C_TC_CPCDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare -AT91C_TC_EEVTEDG EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection -AT91C_TC_EEVTEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None -AT91C_TC_EEVTEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge -AT91C_TC_EEVTEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge -AT91C_TC_EEVTEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge -AT91C_TC_EEVT EQU (0x3:SHL:10) ;- (TC) External Event Selection -AT91C_TC_EEVT_NONE EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input -AT91C_TC_EEVT_RISING EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output -AT91C_TC_EEVT_FALLING EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output -AT91C_TC_EEVT_BOTH EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output -AT91C_TC_ENETRG EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable -AT91C_TC_WAVESEL EQU (0x3:SHL:13) ;- (TC) Waveform Selection -AT91C_TC_WAVESEL_UP EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare -AT91C_TC_WAVESEL_UP_AUTO EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare -AT91C_TC_CPCTRG EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable -AT91C_TC_WAVE EQU (0x1:SHL:15) ;- (TC) -AT91C_TC_ACPA EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA -AT91C_TC_ACPA_NONE EQU (0x0:SHL:16) ;- (TC) Effect: none -AT91C_TC_ACPA_SET EQU (0x1:SHL:16) ;- (TC) Effect: set -AT91C_TC_ACPA_CLEAR EQU (0x2:SHL:16) ;- (TC) Effect: clear -AT91C_TC_ACPA_TOGGLE EQU (0x3:SHL:16) ;- (TC) Effect: toggle -AT91C_TC_ACPC EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA -AT91C_TC_ACPC_NONE EQU (0x0:SHL:18) ;- (TC) Effect: none -AT91C_TC_ACPC_SET EQU (0x1:SHL:18) ;- (TC) Effect: set -AT91C_TC_ACPC_CLEAR EQU (0x2:SHL:18) ;- (TC) Effect: clear -AT91C_TC_ACPC_TOGGLE EQU (0x3:SHL:18) ;- (TC) Effect: toggle -AT91C_TC_AEEVT EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA -AT91C_TC_AEEVT_NONE EQU (0x0:SHL:20) ;- (TC) Effect: none -AT91C_TC_AEEVT_SET EQU (0x1:SHL:20) ;- (TC) Effect: set -AT91C_TC_AEEVT_CLEAR EQU (0x2:SHL:20) ;- (TC) Effect: clear -AT91C_TC_AEEVT_TOGGLE EQU (0x3:SHL:20) ;- (TC) Effect: toggle -AT91C_TC_ASWTRG EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA -AT91C_TC_ASWTRG_NONE EQU (0x0:SHL:22) ;- (TC) Effect: none -AT91C_TC_ASWTRG_SET EQU (0x1:SHL:22) ;- (TC) Effect: set -AT91C_TC_ASWTRG_CLEAR EQU (0x2:SHL:22) ;- (TC) Effect: clear -AT91C_TC_ASWTRG_TOGGLE EQU (0x3:SHL:22) ;- (TC) Effect: toggle -AT91C_TC_BCPB EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB -AT91C_TC_BCPB_NONE EQU (0x0:SHL:24) ;- (TC) Effect: none -AT91C_TC_BCPB_SET EQU (0x1:SHL:24) ;- (TC) Effect: set -AT91C_TC_BCPB_CLEAR EQU (0x2:SHL:24) ;- (TC) Effect: clear -AT91C_TC_BCPB_TOGGLE EQU (0x3:SHL:24) ;- (TC) Effect: toggle -AT91C_TC_BCPC EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB -AT91C_TC_BCPC_NONE EQU (0x0:SHL:26) ;- (TC) Effect: none -AT91C_TC_BCPC_SET EQU (0x1:SHL:26) ;- (TC) Effect: set -AT91C_TC_BCPC_CLEAR EQU (0x2:SHL:26) ;- (TC) Effect: clear -AT91C_TC_BCPC_TOGGLE EQU (0x3:SHL:26) ;- (TC) Effect: toggle -AT91C_TC_BEEVT EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB -AT91C_TC_BEEVT_NONE EQU (0x0:SHL:28) ;- (TC) Effect: none -AT91C_TC_BEEVT_SET EQU (0x1:SHL:28) ;- (TC) Effect: set -AT91C_TC_BEEVT_CLEAR EQU (0x2:SHL:28) ;- (TC) Effect: clear -AT91C_TC_BEEVT_TOGGLE EQU (0x3:SHL:28) ;- (TC) Effect: toggle -AT91C_TC_BSWTRG EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB -AT91C_TC_BSWTRG_NONE EQU (0x0:SHL:30) ;- (TC) Effect: none -AT91C_TC_BSWTRG_SET EQU (0x1:SHL:30) ;- (TC) Effect: set -AT91C_TC_BSWTRG_CLEAR EQU (0x2:SHL:30) ;- (TC) Effect: clear -AT91C_TC_BSWTRG_TOGGLE EQU (0x3:SHL:30) ;- (TC) Effect: toggle -;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -AT91C_TC_COVFS EQU (0x1:SHL:0) ;- (TC) Counter Overflow -AT91C_TC_LOVRS EQU (0x1:SHL:1) ;- (TC) Load Overrun -AT91C_TC_CPAS EQU (0x1:SHL:2) ;- (TC) RA Compare -AT91C_TC_CPBS EQU (0x1:SHL:3) ;- (TC) RB Compare -AT91C_TC_CPCS EQU (0x1:SHL:4) ;- (TC) RC Compare -AT91C_TC_LDRAS EQU (0x1:SHL:5) ;- (TC) RA Loading -AT91C_TC_LDRBS EQU (0x1:SHL:6) ;- (TC) RB Loading -AT91C_TC_ETRCS EQU (0x1:SHL:7) ;- (TC) External Trigger -AT91C_TC_ETRGS EQU (0x1:SHL:16) ;- (TC) Clock Enabling -AT91C_TC_MTIOA EQU (0x1:SHL:17) ;- (TC) TIOA Mirror -AT91C_TC_MTIOB EQU (0x1:SHL:18) ;- (TC) TIOA Mirror -;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Timer Counter Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_TCB -TCB_TC0 # 48 ;- TC Channel 0 - # 16 ;- Reserved -TCB_TC1 # 48 ;- TC Channel 1 - # 16 ;- Reserved -TCB_TC2 # 48 ;- TC Channel 2 - # 16 ;- Reserved -TCB_BCR # 4 ;- TC Block Control Register -TCB_BMR # 4 ;- TC Block Mode Register -;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -AT91C_TCB_SYNC EQU (0x1:SHL:0) ;- (TCB) Synchro Command -;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -AT91C_TCB_TC0XC0S EQU (0x1:SHL:0) ;- (TCB) External Clock Signal 0 Selection -AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 -AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 -AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 -AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 -AT91C_TCB_TC1XC1S EQU (0x1:SHL:2) ;- (TCB) External Clock Signal 1 Selection -AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1 -AT91C_TCB_TC1XC1S_NONE EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1 -AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1 -AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1 -AT91C_TCB_TC2XC2S EQU (0x1:SHL:4) ;- (TCB) External Clock Signal 2 Selection -AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2 -AT91C_TCB_TC2XC2S_NONE EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2 -AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2 -AT91C_TCB_TC2XC2S_TIOA2 EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2 - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR USB Host Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_UHP -UHP_HcRevision # 4 ;- Revision -UHP_HcControl # 4 ;- Operating modes for the Host Controller -UHP_HcCommandStatus # 4 ;- Command & status Register -UHP_HcInterruptStatus # 4 ;- Interrupt Status Register -UHP_HcInterruptEnable # 4 ;- Interrupt Enable Register -UHP_HcInterruptDisable # 4 ;- Interrupt Disable Register -UHP_HcHCCA # 4 ;- Pointer to the Host Controller Communication Area -UHP_HcPeriodCurrentED # 4 ;- Current Isochronous or Interrupt Endpoint Descriptor -UHP_HcControlHeadED # 4 ;- First Endpoint Descriptor of the Control list -UHP_HcControlCurrentED # 4 ;- Endpoint Control and Status Register -UHP_HcBulkHeadED # 4 ;- First endpoint register of the Bulk list -UHP_HcBulkCurrentED # 4 ;- Current endpoint of the Bulk list -UHP_HcBulkDoneHead # 4 ;- Last completed transfer descriptor -UHP_HcFmInterval # 4 ;- Bit time between 2 consecutive SOFs -UHP_HcFmRemaining # 4 ;- Bit time remaining in the current Frame -UHP_HcFmNumber # 4 ;- Frame number -UHP_HcPeriodicStart # 4 ;- Periodic Start -UHP_HcLSThreshold # 4 ;- LS Threshold -UHP_HcRhDescriptorA # 4 ;- Root Hub characteristics A -UHP_HcRhDescriptorB # 4 ;- Root Hub characteristics B -UHP_HcRhStatus # 4 ;- Root Hub Status register -UHP_HcRhPortStatus # 8 ;- Root Hub Port Status Register - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Ethernet MAC -;- ***************************************************************************** - ^ 0 ;- AT91S_EMAC -EMAC_CTL # 4 ;- Network Control Register -EMAC_CFG # 4 ;- Network Configuration Register -EMAC_SR # 4 ;- Network Status Register -EMAC_TAR # 4 ;- Transmit Address Register -EMAC_TCR # 4 ;- Transmit Control Register -EMAC_TSR # 4 ;- Transmit Status Register -EMAC_RBQP # 4 ;- Receive Buffer Queue Pointer - # 4 ;- Reserved -EMAC_RSR # 4 ;- Receive Status Register -EMAC_ISR # 4 ;- Interrupt Status Register -EMAC_IER # 4 ;- Interrupt Enable Register -EMAC_IDR # 4 ;- Interrupt Disable Register -EMAC_IMR # 4 ;- Interrupt Mask Register -EMAC_MAN # 4 ;- PHY Maintenance Register - # 8 ;- Reserved -EMAC_FRA # 4 ;- Frames Transmitted OK Register -EMAC_SCOL # 4 ;- Single Collision Frame Register -EMAC_MCOL # 4 ;- Multiple Collision Frame Register -EMAC_OK # 4 ;- Frames Received OK Register -EMAC_SEQE # 4 ;- Frame Check Sequence Error Register -EMAC_ALE # 4 ;- Alignment Error Register -EMAC_DTE # 4 ;- Deferred Transmission Frame Register -EMAC_LCOL # 4 ;- Late Collision Register -EMAC_ECOL # 4 ;- Excessive Collision Register -EMAC_CSE # 4 ;- Carrier Sense Error Register -EMAC_TUE # 4 ;- Transmit Underrun Error Register -EMAC_CDE # 4 ;- Code Error Register -EMAC_ELR # 4 ;- Excessive Length Error Register -EMAC_RJB # 4 ;- Receive Jabber Register -EMAC_USF # 4 ;- Undersize Frame Register -EMAC_SQEE # 4 ;- SQE Test Error Register -EMAC_DRFC # 4 ;- Discarded RX Frame Register - # 12 ;- Reserved -EMAC_HSH # 4 ;- Hash Address High[63:32] -EMAC_HSL # 4 ;- Hash Address Low[31:0] -EMAC_SA1L # 4 ;- Specific Address 1 Low, First 4 bytes -EMAC_SA1H # 4 ;- Specific Address 1 High, Last 2 bytes -EMAC_SA2L # 4 ;- Specific Address 2 Low, First 4 bytes -EMAC_SA2H # 4 ;- Specific Address 2 High, Last 2 bytes -EMAC_SA3L # 4 ;- Specific Address 3 Low, First 4 bytes -EMAC_SA3H # 4 ;- Specific Address 3 High, Last 2 bytes -EMAC_SA4L # 4 ;- Specific Address 4 Low, First 4 bytes -EMAC_SA4H # 4 ;- Specific Address 4 High, Last 2 bytesr -;- -------- EMAC_CTL : (EMAC Offset: 0x0) -------- -AT91C_EMAC_LB EQU (0x1:SHL:0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. -AT91C_EMAC_LBL EQU (0x1:SHL:1) ;- (EMAC) Loopback local. -AT91C_EMAC_RE EQU (0x1:SHL:2) ;- (EMAC) Receive enable. -AT91C_EMAC_TE EQU (0x1:SHL:3) ;- (EMAC) Transmit enable. -AT91C_EMAC_MPE EQU (0x1:SHL:4) ;- (EMAC) Management port enable. -AT91C_EMAC_CSR EQU (0x1:SHL:5) ;- (EMAC) Clear statistics registers. -AT91C_EMAC_ISR EQU (0x1:SHL:6) ;- (EMAC) Increment statistics registers. -AT91C_EMAC_WES EQU (0x1:SHL:7) ;- (EMAC) Write enable for statistics registers. -AT91C_EMAC_BP EQU (0x1:SHL:8) ;- (EMAC) Back pressure. -;- -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- -AT91C_EMAC_SPD EQU (0x1:SHL:0) ;- (EMAC) Speed. -AT91C_EMAC_FD EQU (0x1:SHL:1) ;- (EMAC) Full duplex. -AT91C_EMAC_BR EQU (0x1:SHL:2) ;- (EMAC) Bit rate. -AT91C_EMAC_CAF EQU (0x1:SHL:4) ;- (EMAC) Copy all frames. -AT91C_EMAC_NBC EQU (0x1:SHL:5) ;- (EMAC) No broadcast. -AT91C_EMAC_MTI EQU (0x1:SHL:6) ;- (EMAC) Multicast hash enable -AT91C_EMAC_UNI EQU (0x1:SHL:7) ;- (EMAC) Unicast hash enable. -AT91C_EMAC_BIG EQU (0x1:SHL:8) ;- (EMAC) Receive 1522 bytes. -AT91C_EMAC_EAE EQU (0x1:SHL:9) ;- (EMAC) External address match enable. -AT91C_EMAC_CLK EQU (0x3:SHL:10) ;- (EMAC) -AT91C_EMAC_CLK_HCLK_8 EQU (0x0:SHL:10) ;- (EMAC) HCLK divided by 8 -AT91C_EMAC_CLK_HCLK_16 EQU (0x1:SHL:10) ;- (EMAC) HCLK divided by 16 -AT91C_EMAC_CLK_HCLK_32 EQU (0x2:SHL:10) ;- (EMAC) HCLK divided by 32 -AT91C_EMAC_CLK_HCLK_64 EQU (0x3:SHL:10) ;- (EMAC) HCLK divided by 64 -AT91C_EMAC_RTY EQU (0x1:SHL:12) ;- (EMAC) -AT91C_EMAC_RMII EQU (0x1:SHL:13) ;- (EMAC) -;- -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- -AT91C_EMAC_MDIO EQU (0x1:SHL:1) ;- (EMAC) -AT91C_EMAC_IDLE EQU (0x1:SHL:2) ;- (EMAC) -;- -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- -AT91C_EMAC_LEN EQU (0x7FF:SHL:0) ;- (EMAC) -AT91C_EMAC_NCRC EQU (0x1:SHL:15) ;- (EMAC) -;- -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- -AT91C_EMAC_OVR EQU (0x1:SHL:0) ;- (EMAC) -AT91C_EMAC_COL EQU (0x1:SHL:1) ;- (EMAC) -AT91C_EMAC_RLE EQU (0x1:SHL:2) ;- (EMAC) -AT91C_EMAC_TXIDLE EQU (0x1:SHL:3) ;- (EMAC) -AT91C_EMAC_BNQ EQU (0x1:SHL:4) ;- (EMAC) -AT91C_EMAC_COMP EQU (0x1:SHL:5) ;- (EMAC) -AT91C_EMAC_UND EQU (0x1:SHL:6) ;- (EMAC) -;- -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -AT91C_EMAC_BNA EQU (0x1:SHL:0) ;- (EMAC) -AT91C_EMAC_REC EQU (0x1:SHL:1) ;- (EMAC) -;- -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -AT91C_EMAC_DONE EQU (0x1:SHL:0) ;- (EMAC) -AT91C_EMAC_RCOM EQU (0x1:SHL:1) ;- (EMAC) -AT91C_EMAC_RBNA EQU (0x1:SHL:2) ;- (EMAC) -AT91C_EMAC_TOVR EQU (0x1:SHL:3) ;- (EMAC) -AT91C_EMAC_TUND EQU (0x1:SHL:4) ;- (EMAC) -AT91C_EMAC_RTRY EQU (0x1:SHL:5) ;- (EMAC) -AT91C_EMAC_TBRE EQU (0x1:SHL:6) ;- (EMAC) -AT91C_EMAC_TCOM EQU (0x1:SHL:7) ;- (EMAC) -AT91C_EMAC_TIDLE EQU (0x1:SHL:8) ;- (EMAC) -AT91C_EMAC_LINK EQU (0x1:SHL:9) ;- (EMAC) -AT91C_EMAC_ROVR EQU (0x1:SHL:10) ;- (EMAC) -AT91C_EMAC_HRESP EQU (0x1:SHL:11) ;- (EMAC) -;- -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -;- -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -;- -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -;- -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -AT91C_EMAC_DATA EQU (0xFFFF:SHL:0) ;- (EMAC) -AT91C_EMAC_CODE EQU (0x3:SHL:16) ;- (EMAC) -AT91C_EMAC_REGA EQU (0x1F:SHL:18) ;- (EMAC) -AT91C_EMAC_PHYA EQU (0x1F:SHL:23) ;- (EMAC) -AT91C_EMAC_RW EQU (0x3:SHL:28) ;- (EMAC) -AT91C_EMAC_HIGH EQU (0x1:SHL:30) ;- (EMAC) -AT91C_EMAC_LOW EQU (0x1:SHL:31) ;- (EMAC) - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR External Bus Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_EBI -EBI_CSA # 4 ;- Chip Select Assignment Register -EBI_CFGR # 4 ;- Configuration Register -;- -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- -AT91C_EBI_CS0A EQU (0x1:SHL:0) ;- (EBI) Chip Select 0 Assignment -AT91C_EBI_CS0A_SMC EQU (0x0) ;- (EBI) Chip Select 0 is assigned to the Static Memory Controller. -AT91C_EBI_CS0A_BFC EQU (0x1) ;- (EBI) Chip Select 0 is assigned to the Burst Flash Controller. -AT91C_EBI_CS1A EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 Assignment -AT91C_EBI_CS1A_SMC EQU (0x0:SHL:1) ;- (EBI) Chip Select 1 is assigned to the Static Memory Controller. -AT91C_EBI_CS1A_SDRAMC EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 is assigned to the SDRAM Controller. -AT91C_EBI_CS3A EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 Assignment -AT91C_EBI_CS3A_SMC EQU (0x0:SHL:3) ;- (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. -AT91C_EBI_CS3A_SMC_SmartMedia EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. -AT91C_EBI_CS4A EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 Assignment -AT91C_EBI_CS4A_SMC EQU (0x0:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. -AT91C_EBI_CS4A_SMC_CompactFlash EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. -;- -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- -AT91C_EBI_DBPUC EQU (0x1:SHL:0) ;- (EBI) Data Bus Pull-Up Configuration -AT91C_EBI_EBSEN EQU (0x1:SHL:1) ;- (EBI) Bus Sharing Enable - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_SMC2 -SMC2_CSR # 32 ;- SMC2 Chip Select Register -;- -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- -AT91C_SMC2_NWS EQU (0x7F:SHL:0) ;- (SMC2) Number of Wait States -AT91C_SMC2_WSEN EQU (0x1:SHL:7) ;- (SMC2) Wait State Enable -AT91C_SMC2_TDF EQU (0xF:SHL:8) ;- (SMC2) Data Float Time -AT91C_SMC2_BAT EQU (0x1:SHL:12) ;- (SMC2) Byte Access Type -AT91C_SMC2_DBW EQU (0x1:SHL:13) ;- (SMC2) Data Bus Width -AT91C_SMC2_DBW_16 EQU (0x1:SHL:13) ;- (SMC2) 16-bit. -AT91C_SMC2_DBW_8 EQU (0x2:SHL:13) ;- (SMC2) 8-bit. -AT91C_SMC2_DRP EQU (0x1:SHL:15) ;- (SMC2) Data Read Protocol -AT91C_SMC2_ACSS EQU (0x3:SHL:16) ;- (SMC2) Address to Chip Select Setup -AT91C_SMC2_ACSS_STANDARD EQU (0x0:SHL:16) ;- (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. -AT91C_SMC2_ACSS_1_CYCLE EQU (0x1:SHL:16) ;- (SMC2) One cycle less at the beginning and the end of the access. -AT91C_SMC2_ACSS_2_CYCLES EQU (0x2:SHL:16) ;- (SMC2) Two cycles less at the beginning and the end of the access. -AT91C_SMC2_ACSS_3_CYCLES EQU (0x3:SHL:16) ;- (SMC2) Three cycles less at the beginning and the end of the access. -AT91C_SMC2_RWSETUP EQU (0x7:SHL:24) ;- (SMC2) Read and Write Signal Setup Time -AT91C_SMC2_RWHOLD EQU (0x7:SHL:29) ;- (SMC2) Read and Write Signal Hold Time - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR SDRAM Controller Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_SDRC -SDRC_MR # 4 ;- SDRAM Controller Mode Register -SDRC_TR # 4 ;- SDRAM Controller Refresh Timer Register -SDRC_CR # 4 ;- SDRAM Controller Configuration Register -SDRC_SRR # 4 ;- SDRAM Controller Self Refresh Register -SDRC_LPR # 4 ;- SDRAM Controller Low Power Register -SDRC_IER # 4 ;- SDRAM Controller Interrupt Enable Register -SDRC_IDR # 4 ;- SDRAM Controller Interrupt Disable Register -SDRC_IMR # 4 ;- SDRAM Controller Interrupt Mask Register -SDRC_ISR # 4 ;- SDRAM Controller Interrupt Mask Register -;- -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- -AT91C_SDRC_MODE EQU (0xF:SHL:0) ;- (SDRC) Mode -AT91C_SDRC_MODE_NORMAL_CMD EQU (0x0) ;- (SDRC) Normal Mode -AT91C_SDRC_MODE_NOP_CMD EQU (0x1) ;- (SDRC) NOP Command -AT91C_SDRC_MODE_PRCGALL_CMD EQU (0x2) ;- (SDRC) All Banks Precharge Command -AT91C_SDRC_MODE_LMR_CMD EQU (0x3) ;- (SDRC) Load Mode Register Command -AT91C_SDRC_MODE_RFSH_CMD EQU (0x4) ;- (SDRC) Refresh Command -AT91C_SDRC_DBW EQU (0x1:SHL:4) ;- (SDRC) Data Bus Width -AT91C_SDRC_DBW_32_BITS EQU (0x0:SHL:4) ;- (SDRC) 32 Bits datas bus -AT91C_SDRC_DBW_16_BITS EQU (0x1:SHL:4) ;- (SDRC) 16 Bits datas bus -;- -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- -AT91C_SDRC_COUNT EQU (0xFFF:SHL:0) ;- (SDRC) Refresh Counter -;- -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- -AT91C_SDRC_NC EQU (0x3:SHL:0) ;- (SDRC) Number of Column Bits -AT91C_SDRC_NC_8 EQU (0x0) ;- (SDRC) 8 Bits -AT91C_SDRC_NC_9 EQU (0x1) ;- (SDRC) 9 Bits -AT91C_SDRC_NC_10 EQU (0x2) ;- (SDRC) 10 Bits -AT91C_SDRC_NC_11 EQU (0x3) ;- (SDRC) 11 Bits -AT91C_SDRC_NR EQU (0x3:SHL:2) ;- (SDRC) Number of Row Bits -AT91C_SDRC_NR_11 EQU (0x0:SHL:2) ;- (SDRC) 11 Bits -AT91C_SDRC_NR_12 EQU (0x1:SHL:2) ;- (SDRC) 12 Bits -AT91C_SDRC_NR_13 EQU (0x2:SHL:2) ;- (SDRC) 13 Bits -AT91C_SDRC_NB EQU (0x1:SHL:4) ;- (SDRC) Number of Banks -AT91C_SDRC_NB_2_BANKS EQU (0x0:SHL:4) ;- (SDRC) 2 banks -AT91C_SDRC_NB_4_BANKS EQU (0x1:SHL:4) ;- (SDRC) 4 banks -AT91C_SDRC_CAS EQU (0x3:SHL:5) ;- (SDRC) CAS Latency -AT91C_SDRC_CAS_2 EQU (0x2:SHL:5) ;- (SDRC) 2 cycles -AT91C_SDRC_TWR EQU (0xF:SHL:7) ;- (SDRC) Number of Write Recovery Time Cycles -AT91C_SDRC_TRC EQU (0xF:SHL:11) ;- (SDRC) Number of RAS Cycle Time Cycles -AT91C_SDRC_TRP EQU (0xF:SHL:15) ;- (SDRC) Number of RAS Precharge Time Cycles -AT91C_SDRC_TRCD EQU (0xF:SHL:19) ;- (SDRC) Number of RAS to CAS Delay Cycles -AT91C_SDRC_TRAS EQU (0xF:SHL:23) ;- (SDRC) Number of RAS Active Time Cycles -AT91C_SDRC_TXSR EQU (0xF:SHL:27) ;- (SDRC) Number of Command Recovery Time Cycles -;- -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- -AT91C_SDRC_SRCB EQU (0x1:SHL:0) ;- (SDRC) Self-refresh Command Bit -;- -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- -AT91C_SDRC_LPCB EQU (0x1:SHL:0) ;- (SDRC) Low-power Command Bit -;- -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- -AT91C_SDRC_RES EQU (0x1:SHL:0) ;- (SDRC) Refresh Error Status -;- -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- -;- -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- -;- -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Burst Flash Controller Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_BFC -BFC_MR # 4 ;- BFC Mode Register -;- -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- -AT91C_BFC_BFCOM EQU (0x3:SHL:0) ;- (BFC) Burst Flash Controller Operating Mode -AT91C_BFC_BFCOM_DISABLED EQU (0x0) ;- (BFC) NPCS0 is driven by the SMC or remains high. -AT91C_BFC_BFCOM_ASYNC EQU (0x1) ;- (BFC) Asynchronous -AT91C_BFC_BFCOM_BURST_READ EQU (0x2) ;- (BFC) Burst Read -AT91C_BFC_BFCC EQU (0x3:SHL:2) ;- (BFC) Burst Flash Controller Operating Mode -AT91C_BFC_BFCC_MCK EQU (0x1:SHL:2) ;- (BFC) Master Clock. -AT91C_BFC_BFCC_MCK_DIV_2 EQU (0x2:SHL:2) ;- (BFC) Master Clock divided by 2. -AT91C_BFC_BFCC_MCK_DIV_4 EQU (0x3:SHL:2) ;- (BFC) Master Clock divided by 4. -AT91C_BFC_AVL EQU (0xF:SHL:4) ;- (BFC) Address Valid Latency -AT91C_BFC_PAGES EQU (0x7:SHL:8) ;- (BFC) Page Size -AT91C_BFC_PAGES_NO_PAGE EQU (0x0:SHL:8) ;- (BFC) No page handling. -AT91C_BFC_PAGES_16 EQU (0x1:SHL:8) ;- (BFC) 16 bytes page size. -AT91C_BFC_PAGES_32 EQU (0x2:SHL:8) ;- (BFC) 32 bytes page size. -AT91C_BFC_PAGES_64 EQU (0x3:SHL:8) ;- (BFC) 64 bytes page size. -AT91C_BFC_PAGES_128 EQU (0x4:SHL:8) ;- (BFC) 128 bytes page size. -AT91C_BFC_PAGES_256 EQU (0x5:SHL:8) ;- (BFC) 256 bytes page size. -AT91C_BFC_PAGES_512 EQU (0x6:SHL:8) ;- (BFC) 512 bytes page size. -AT91C_BFC_PAGES_1024 EQU (0x7:SHL:8) ;- (BFC) 1024 bytes page size. -AT91C_BFC_OEL EQU (0x3:SHL:12) ;- (BFC) Output Enable Latency -AT91C_BFC_BAAEN EQU (0x1:SHL:16) ;- (BFC) Burst Address Advance Enable -AT91C_BFC_BFOEH EQU (0x1:SHL:17) ;- (BFC) Burst Flash Output Enable Handling -AT91C_BFC_MUXEN EQU (0x1:SHL:18) ;- (BFC) Multiplexed Bus Enable -AT91C_BFC_RDYEN EQU (0x1:SHL:19) ;- (BFC) Ready Enable Mode - -;- ***************************************************************************** -;- REGISTER ADDRESS DEFINITION FOR AT91RM9200 -;- ***************************************************************************** -;- ========== Register definition for SYS peripheral ========== -;- ========== Register definition for MC peripheral ========== -AT91C_MC_PUER EQU (0xFFFFFF54) ;- (MC) MC Protection Unit Enable Register -AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register -AT91C_MC_PUP EQU (0xFFFFFF50) ;- (MC) MC Protection Unit Peripherals -AT91C_MC_PUIA EQU (0xFFFFFF10) ;- (MC) MC Protection Unit Area -AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register -AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register -;- ========== Register definition for RTC peripheral ========== -AT91C_RTC_IMR EQU (0xFFFFFE28) ;- (RTC) Interrupt Mask Register -AT91C_RTC_IER EQU (0xFFFFFE20) ;- (RTC) Interrupt Enable Register -AT91C_RTC_SR EQU (0xFFFFFE18) ;- (RTC) Status Register -AT91C_RTC_TIMALR EQU (0xFFFFFE10) ;- (RTC) Time Alarm Register -AT91C_RTC_TIMR EQU (0xFFFFFE08) ;- (RTC) Time Register -AT91C_RTC_CR EQU (0xFFFFFE00) ;- (RTC) Control Register -AT91C_RTC_VER EQU (0xFFFFFE2C) ;- (RTC) Valid Entry Register -AT91C_RTC_IDR EQU (0xFFFFFE24) ;- (RTC) Interrupt Disable Register -AT91C_RTC_SCCR EQU (0xFFFFFE1C) ;- (RTC) Status Clear Command Register -AT91C_RTC_CALALR EQU (0xFFFFFE14) ;- (RTC) Calendar Alarm Register -AT91C_RTC_CALR EQU (0xFFFFFE0C) ;- (RTC) Calendar Register -AT91C_RTC_MR EQU (0xFFFFFE04) ;- (RTC) Mode Register -;- ========== Register definition for ST peripheral ========== -AT91C_ST_CRTR EQU (0xFFFFFD24) ;- (ST) Current Real-time Register -AT91C_ST_IMR EQU (0xFFFFFD1C) ;- (ST) Interrupt Mask Register -AT91C_ST_IER EQU (0xFFFFFD14) ;- (ST) Interrupt Enable Register -AT91C_ST_RTMR EQU (0xFFFFFD0C) ;- (ST) Real-time Mode Register -AT91C_ST_PIMR EQU (0xFFFFFD04) ;- (ST) Period Interval Mode Register -AT91C_ST_RTAR EQU (0xFFFFFD20) ;- (ST) Real-time Alarm Register -AT91C_ST_IDR EQU (0xFFFFFD18) ;- (ST) Interrupt Disable Register -AT91C_ST_SR EQU (0xFFFFFD10) ;- (ST) Status Register -AT91C_ST_WDMR EQU (0xFFFFFD08) ;- (ST) Watchdog Mode Register -AT91C_ST_CR EQU (0xFFFFFD00) ;- (ST) Control Register -;- ========== Register definition for PMC peripheral ========== -AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register -AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register -AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register -AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register -AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register -AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register -AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register -AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register -AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register -AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register -AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register -AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register -;- ========== Register definition for CKGR peripheral ========== -AT91C_CKGR_PLLBR EQU (0xFFFFFC2C) ;- (CKGR) PLL B Register -AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register -AT91C_CKGR_PLLAR EQU (0xFFFFFC28) ;- (CKGR) PLL A Register -AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register -;- ========== Register definition for PIOD peripheral ========== -AT91C_PIOD_PDSR EQU (0xFFFFFA3C) ;- (PIOD) Pin Data Status Register -AT91C_PIOD_CODR EQU (0xFFFFFA34) ;- (PIOD) Clear Output Data Register -AT91C_PIOD_OWER EQU (0xFFFFFAA0) ;- (PIOD) Output Write Enable Register -AT91C_PIOD_MDER EQU (0xFFFFFA50) ;- (PIOD) Multi-driver Enable Register -AT91C_PIOD_IMR EQU (0xFFFFFA48) ;- (PIOD) Interrupt Mask Register -AT91C_PIOD_IER EQU (0xFFFFFA40) ;- (PIOD) Interrupt Enable Register -AT91C_PIOD_ODSR EQU (0xFFFFFA38) ;- (PIOD) Output Data Status Register -AT91C_PIOD_SODR EQU (0xFFFFFA30) ;- (PIOD) Set Output Data Register -AT91C_PIOD_PER EQU (0xFFFFFA00) ;- (PIOD) PIO Enable Register -AT91C_PIOD_OWDR EQU (0xFFFFFAA4) ;- (PIOD) Output Write Disable Register -AT91C_PIOD_PPUER EQU (0xFFFFFA64) ;- (PIOD) Pull-up Enable Register -AT91C_PIOD_MDDR EQU (0xFFFFFA54) ;- (PIOD) Multi-driver Disable Register -AT91C_PIOD_ISR EQU (0xFFFFFA4C) ;- (PIOD) Interrupt Status Register -AT91C_PIOD_IDR EQU (0xFFFFFA44) ;- (PIOD) Interrupt Disable Register -AT91C_PIOD_PDR EQU (0xFFFFFA04) ;- (PIOD) PIO Disable Register -AT91C_PIOD_ODR EQU (0xFFFFFA14) ;- (PIOD) Output Disable Registerr -AT91C_PIOD_OWSR EQU (0xFFFFFAA8) ;- (PIOD) Output Write Status Register -AT91C_PIOD_ABSR EQU (0xFFFFFA78) ;- (PIOD) AB Select Status Register -AT91C_PIOD_ASR EQU (0xFFFFFA70) ;- (PIOD) Select A Register -AT91C_PIOD_PPUSR EQU (0xFFFFFA68) ;- (PIOD) Pad Pull-up Status Register -AT91C_PIOD_PPUDR EQU (0xFFFFFA60) ;- (PIOD) Pull-up Disable Register -AT91C_PIOD_MDSR EQU (0xFFFFFA58) ;- (PIOD) Multi-driver Status Register -AT91C_PIOD_PSR EQU (0xFFFFFA08) ;- (PIOD) PIO Status Register -AT91C_PIOD_OER EQU (0xFFFFFA10) ;- (PIOD) Output Enable Register -AT91C_PIOD_OSR EQU (0xFFFFFA18) ;- (PIOD) Output Status Register -AT91C_PIOD_IFER EQU (0xFFFFFA20) ;- (PIOD) Input Filter Enable Register -AT91C_PIOD_BSR EQU (0xFFFFFA74) ;- (PIOD) Select B Register -AT91C_PIOD_IFDR EQU (0xFFFFFA24) ;- (PIOD) Input Filter Disable Register -AT91C_PIOD_IFSR EQU (0xFFFFFA28) ;- (PIOD) Input Filter Status Register -;- ========== Register definition for PIOC peripheral ========== -AT91C_PIOC_IFDR EQU (0xFFFFF824) ;- (PIOC) Input Filter Disable Register -AT91C_PIOC_ODR EQU (0xFFFFF814) ;- (PIOC) Output Disable Registerr -AT91C_PIOC_ABSR EQU (0xFFFFF878) ;- (PIOC) AB Select Status Register -AT91C_PIOC_SODR EQU (0xFFFFF830) ;- (PIOC) Set Output Data Register -AT91C_PIOC_IFSR EQU (0xFFFFF828) ;- (PIOC) Input Filter Status Register -AT91C_PIOC_CODR EQU (0xFFFFF834) ;- (PIOC) Clear Output Data Register -AT91C_PIOC_ODSR EQU (0xFFFFF838) ;- (PIOC) Output Data Status Register -AT91C_PIOC_IER EQU (0xFFFFF840) ;- (PIOC) Interrupt Enable Register -AT91C_PIOC_IMR EQU (0xFFFFF848) ;- (PIOC) Interrupt Mask Register -AT91C_PIOC_OWDR EQU (0xFFFFF8A4) ;- (PIOC) Output Write Disable Register -AT91C_PIOC_MDDR EQU (0xFFFFF854) ;- (PIOC) Multi-driver Disable Register -AT91C_PIOC_PDSR EQU (0xFFFFF83C) ;- (PIOC) Pin Data Status Register -AT91C_PIOC_IDR EQU (0xFFFFF844) ;- (PIOC) Interrupt Disable Register -AT91C_PIOC_ISR EQU (0xFFFFF84C) ;- (PIOC) Interrupt Status Register -AT91C_PIOC_PDR EQU (0xFFFFF804) ;- (PIOC) PIO Disable Register -AT91C_PIOC_OWSR EQU (0xFFFFF8A8) ;- (PIOC) Output Write Status Register -AT91C_PIOC_OWER EQU (0xFFFFF8A0) ;- (PIOC) Output Write Enable Register -AT91C_PIOC_ASR EQU (0xFFFFF870) ;- (PIOC) Select A Register -AT91C_PIOC_PPUSR EQU (0xFFFFF868) ;- (PIOC) Pad Pull-up Status Register -AT91C_PIOC_PPUDR EQU (0xFFFFF860) ;- (PIOC) Pull-up Disable Register -AT91C_PIOC_MDSR EQU (0xFFFFF858) ;- (PIOC) Multi-driver Status Register -AT91C_PIOC_MDER EQU (0xFFFFF850) ;- (PIOC) Multi-driver Enable Register -AT91C_PIOC_IFER EQU (0xFFFFF820) ;- (PIOC) Input Filter Enable Register -AT91C_PIOC_OSR EQU (0xFFFFF818) ;- (PIOC) Output Status Register -AT91C_PIOC_OER EQU (0xFFFFF810) ;- (PIOC) Output Enable Register -AT91C_PIOC_PSR EQU (0xFFFFF808) ;- (PIOC) PIO Status Register -AT91C_PIOC_PER EQU (0xFFFFF800) ;- (PIOC) PIO Enable Register -AT91C_PIOC_BSR EQU (0xFFFFF874) ;- (PIOC) Select B Register -AT91C_PIOC_PPUER EQU (0xFFFFF864) ;- (PIOC) Pull-up Enable Register -;- ========== Register definition for PIOB peripheral ========== -AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register -AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pad Pull-up Status Register -AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register -AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register -AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register -AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register -AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register -AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register -AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register -AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register -AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register -AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register -AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register -AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr -AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register -AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register -AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register -AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register -AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register -AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register -AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register -AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register -AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register -AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register -AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register -AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register -AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register -AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register -AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register -;- ========== Register definition for PIOA peripheral ========== -AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register -AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register -AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register -AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register -AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register -AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register -AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register -AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register -AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register -AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register -AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register -AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register -AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register -AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register -AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr -AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register -AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register -AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register -AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pad Pull-up Status Register -AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register -AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register -AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register -AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register -AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register -AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register -AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register -AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register -AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register -AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register -;- ========== Register definition for DBGU peripheral ========== -AT91C_DBGU_C2R EQU (0xFFFFF244) ;- (DBGU) Chip ID2 Register -AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register -AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register -AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register -AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register -AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register -AT91C_DBGU_C1R EQU (0xFFFFF240) ;- (DBGU) Chip ID1 Register -AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register -AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register -AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register -AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register -AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register -;- ========== Register definition for PDC_DBGU peripheral ========== -AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register -AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register -AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register -AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register -AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register -AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register -AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register -AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register -AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register -AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register -;- ========== Register definition for AIC peripheral ========== -AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register -AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register -AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register -AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register -AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register -AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) -AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register -AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register -AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register -AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register -AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register -AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register -AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register -AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register -AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register -AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register -AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register -AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register -;- ========== Register definition for PDC_SPI peripheral ========== -AT91C_SPI_PTCR EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register -AT91C_SPI_TNPR EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register -AT91C_SPI_RNPR EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register -AT91C_SPI_TPR EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register -AT91C_SPI_RPR EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register -AT91C_SPI_PTSR EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register -AT91C_SPI_TNCR EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register -AT91C_SPI_RNCR EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register -AT91C_SPI_TCR EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register -AT91C_SPI_RCR EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register -;- ========== Register definition for SPI peripheral ========== -AT91C_SPI_CSR EQU (0xFFFE0030) ;- (SPI) Chip Select Register -AT91C_SPI_IDR EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register -AT91C_SPI_SR EQU (0xFFFE0010) ;- (SPI) Status Register -AT91C_SPI_RDR EQU (0xFFFE0008) ;- (SPI) Receive Data Register -AT91C_SPI_CR EQU (0xFFFE0000) ;- (SPI) Control Register -AT91C_SPI_IMR EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register -AT91C_SPI_IER EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register -AT91C_SPI_TDR EQU (0xFFFE000C) ;- (SPI) Transmit Data Register -AT91C_SPI_MR EQU (0xFFFE0004) ;- (SPI) Mode Register -;- ========== Register definition for PDC_SSC2 peripheral ========== -AT91C_SSC2_PTCR EQU (0xFFFD8120) ;- (PDC_SSC2) PDC Transfer Control Register -AT91C_SSC2_TNPR EQU (0xFFFD8118) ;- (PDC_SSC2) Transmit Next Pointer Register -AT91C_SSC2_RNPR EQU (0xFFFD8110) ;- (PDC_SSC2) Receive Next Pointer Register -AT91C_SSC2_TPR EQU (0xFFFD8108) ;- (PDC_SSC2) Transmit Pointer Register -AT91C_SSC2_RPR EQU (0xFFFD8100) ;- (PDC_SSC2) Receive Pointer Register -AT91C_SSC2_PTSR EQU (0xFFFD8124) ;- (PDC_SSC2) PDC Transfer Status Register -AT91C_SSC2_TNCR EQU (0xFFFD811C) ;- (PDC_SSC2) Transmit Next Counter Register -AT91C_SSC2_RNCR EQU (0xFFFD8114) ;- (PDC_SSC2) Receive Next Counter Register -AT91C_SSC2_TCR EQU (0xFFFD810C) ;- (PDC_SSC2) Transmit Counter Register -AT91C_SSC2_RCR EQU (0xFFFD8104) ;- (PDC_SSC2) Receive Counter Register -;- ========== Register definition for SSC2 peripheral ========== -AT91C_SSC2_IMR EQU (0xFFFD804C) ;- (SSC2) Interrupt Mask Register -AT91C_SSC2_IER EQU (0xFFFD8044) ;- (SSC2) Interrupt Enable Register -AT91C_SSC2_RC1R EQU (0xFFFD803C) ;- (SSC2) Receive Compare 1 Register -AT91C_SSC2_TSHR EQU (0xFFFD8034) ;- (SSC2) Transmit Sync Holding Register -AT91C_SSC2_CMR EQU (0xFFFD8004) ;- (SSC2) Clock Mode Register -AT91C_SSC2_IDR EQU (0xFFFD8048) ;- (SSC2) Interrupt Disable Register -AT91C_SSC2_TCMR EQU (0xFFFD8018) ;- (SSC2) Transmit Clock Mode Register -AT91C_SSC2_RCMR EQU (0xFFFD8010) ;- (SSC2) Receive Clock ModeRegister -AT91C_SSC2_CR EQU (0xFFFD8000) ;- (SSC2) Control Register -AT91C_SSC2_RFMR EQU (0xFFFD8014) ;- (SSC2) Receive Frame Mode Register -AT91C_SSC2_TFMR EQU (0xFFFD801C) ;- (SSC2) Transmit Frame Mode Register -AT91C_SSC2_THR EQU (0xFFFD8024) ;- (SSC2) Transmit Holding Register -AT91C_SSC2_SR EQU (0xFFFD8040) ;- (SSC2) Status Register -AT91C_SSC2_RC0R EQU (0xFFFD8038) ;- (SSC2) Receive Compare 0 Register -AT91C_SSC2_RSHR EQU (0xFFFD8030) ;- (SSC2) Receive Sync Holding Register -AT91C_SSC2_RHR EQU (0xFFFD8020) ;- (SSC2) Receive Holding Register -;- ========== Register definition for PDC_SSC1 peripheral ========== -AT91C_SSC1_PTCR EQU (0xFFFD4120) ;- (PDC_SSC1) PDC Transfer Control Register -AT91C_SSC1_TNPR EQU (0xFFFD4118) ;- (PDC_SSC1) Transmit Next Pointer Register -AT91C_SSC1_RNPR EQU (0xFFFD4110) ;- (PDC_SSC1) Receive Next Pointer Register -AT91C_SSC1_TPR EQU (0xFFFD4108) ;- (PDC_SSC1) Transmit Pointer Register -AT91C_SSC1_RPR EQU (0xFFFD4100) ;- (PDC_SSC1) Receive Pointer Register -AT91C_SSC1_PTSR EQU (0xFFFD4124) ;- (PDC_SSC1) PDC Transfer Status Register -AT91C_SSC1_TNCR EQU (0xFFFD411C) ;- (PDC_SSC1) Transmit Next Counter Register -AT91C_SSC1_RNCR EQU (0xFFFD4114) ;- (PDC_SSC1) Receive Next Counter Register -AT91C_SSC1_TCR EQU (0xFFFD410C) ;- (PDC_SSC1) Transmit Counter Register -AT91C_SSC1_RCR EQU (0xFFFD4104) ;- (PDC_SSC1) Receive Counter Register -;- ========== Register definition for SSC1 peripheral ========== -AT91C_SSC1_RFMR EQU (0xFFFD4014) ;- (SSC1) Receive Frame Mode Register -AT91C_SSC1_CMR EQU (0xFFFD4004) ;- (SSC1) Clock Mode Register -AT91C_SSC1_IDR EQU (0xFFFD4048) ;- (SSC1) Interrupt Disable Register -AT91C_SSC1_SR EQU (0xFFFD4040) ;- (SSC1) Status Register -AT91C_SSC1_RC0R EQU (0xFFFD4038) ;- (SSC1) Receive Compare 0 Register -AT91C_SSC1_RSHR EQU (0xFFFD4030) ;- (SSC1) Receive Sync Holding Register -AT91C_SSC1_RHR EQU (0xFFFD4020) ;- (SSC1) Receive Holding Register -AT91C_SSC1_TCMR EQU (0xFFFD4018) ;- (SSC1) Transmit Clock Mode Register -AT91C_SSC1_RCMR EQU (0xFFFD4010) ;- (SSC1) Receive Clock ModeRegister -AT91C_SSC1_CR EQU (0xFFFD4000) ;- (SSC1) Control Register -AT91C_SSC1_IMR EQU (0xFFFD404C) ;- (SSC1) Interrupt Mask Register -AT91C_SSC1_IER EQU (0xFFFD4044) ;- (SSC1) Interrupt Enable Register -AT91C_SSC1_RC1R EQU (0xFFFD403C) ;- (SSC1) Receive Compare 1 Register -AT91C_SSC1_TSHR EQU (0xFFFD4034) ;- (SSC1) Transmit Sync Holding Register -AT91C_SSC1_THR EQU (0xFFFD4024) ;- (SSC1) Transmit Holding Register -AT91C_SSC1_TFMR EQU (0xFFFD401C) ;- (SSC1) Transmit Frame Mode Register -;- ========== Register definition for PDC_SSC0 peripheral ========== -AT91C_SSC0_PTCR EQU (0xFFFD0120) ;- (PDC_SSC0) PDC Transfer Control Register -AT91C_SSC0_TNPR EQU (0xFFFD0118) ;- (PDC_SSC0) Transmit Next Pointer Register -AT91C_SSC0_RNPR EQU (0xFFFD0110) ;- (PDC_SSC0) Receive Next Pointer Register -AT91C_SSC0_TPR EQU (0xFFFD0108) ;- (PDC_SSC0) Transmit Pointer Register -AT91C_SSC0_RPR EQU (0xFFFD0100) ;- (PDC_SSC0) Receive Pointer Register -AT91C_SSC0_PTSR EQU (0xFFFD0124) ;- (PDC_SSC0) PDC Transfer Status Register -AT91C_SSC0_TNCR EQU (0xFFFD011C) ;- (PDC_SSC0) Transmit Next Counter Register -AT91C_SSC0_RNCR EQU (0xFFFD0114) ;- (PDC_SSC0) Receive Next Counter Register -AT91C_SSC0_TCR EQU (0xFFFD010C) ;- (PDC_SSC0) Transmit Counter Register -AT91C_SSC0_RCR EQU (0xFFFD0104) ;- (PDC_SSC0) Receive Counter Register -;- ========== Register definition for SSC0 peripheral ========== -AT91C_SSC0_IMR EQU (0xFFFD004C) ;- (SSC0) Interrupt Mask Register -AT91C_SSC0_IER EQU (0xFFFD0044) ;- (SSC0) Interrupt Enable Register -AT91C_SSC0_RC1R EQU (0xFFFD003C) ;- (SSC0) Receive Compare 1 Register -AT91C_SSC0_TSHR EQU (0xFFFD0034) ;- (SSC0) Transmit Sync Holding Register -AT91C_SSC0_THR EQU (0xFFFD0024) ;- (SSC0) Transmit Holding Register -AT91C_SSC0_TFMR EQU (0xFFFD001C) ;- (SSC0) Transmit Frame Mode Register -AT91C_SSC0_RFMR EQU (0xFFFD0014) ;- (SSC0) Receive Frame Mode Register -AT91C_SSC0_CMR EQU (0xFFFD0004) ;- (SSC0) Clock Mode Register -AT91C_SSC0_IDR EQU (0xFFFD0048) ;- (SSC0) Interrupt Disable Register -AT91C_SSC0_SR EQU (0xFFFD0040) ;- (SSC0) Status Register -AT91C_SSC0_RC0R EQU (0xFFFD0038) ;- (SSC0) Receive Compare 0 Register -AT91C_SSC0_RSHR EQU (0xFFFD0030) ;- (SSC0) Receive Sync Holding Register -AT91C_SSC0_RHR EQU (0xFFFD0020) ;- (SSC0) Receive Holding Register -AT91C_SSC0_TCMR EQU (0xFFFD0018) ;- (SSC0) Transmit Clock Mode Register -AT91C_SSC0_RCMR EQU (0xFFFD0010) ;- (SSC0) Receive Clock ModeRegister -AT91C_SSC0_CR EQU (0xFFFD0000) ;- (SSC0) Control Register -;- ========== Register definition for PDC_US3 peripheral ========== -AT91C_US3_PTSR EQU (0xFFFCC124) ;- (PDC_US3) PDC Transfer Status Register -AT91C_US3_TNCR EQU (0xFFFCC11C) ;- (PDC_US3) Transmit Next Counter Register -AT91C_US3_RNCR EQU (0xFFFCC114) ;- (PDC_US3) Receive Next Counter Register -AT91C_US3_TCR EQU (0xFFFCC10C) ;- (PDC_US3) Transmit Counter Register -AT91C_US3_RCR EQU (0xFFFCC104) ;- (PDC_US3) Receive Counter Register -AT91C_US3_PTCR EQU (0xFFFCC120) ;- (PDC_US3) PDC Transfer Control Register -AT91C_US3_TNPR EQU (0xFFFCC118) ;- (PDC_US3) Transmit Next Pointer Register -AT91C_US3_RNPR EQU (0xFFFCC110) ;- (PDC_US3) Receive Next Pointer Register -AT91C_US3_TPR EQU (0xFFFCC108) ;- (PDC_US3) Transmit Pointer Register -AT91C_US3_RPR EQU (0xFFFCC100) ;- (PDC_US3) Receive Pointer Register -;- ========== Register definition for US3 peripheral ========== -AT91C_US3_IF EQU (0xFFFCC04C) ;- (US3) IRDA_FILTER Register -AT91C_US3_NER EQU (0xFFFCC044) ;- (US3) Nb Errors Register -AT91C_US3_RTOR EQU (0xFFFCC024) ;- (US3) Receiver Time-out Register -AT91C_US3_THR EQU (0xFFFCC01C) ;- (US3) Transmitter Holding Register -AT91C_US3_CSR EQU (0xFFFCC014) ;- (US3) Channel Status Register -AT91C_US3_IDR EQU (0xFFFCC00C) ;- (US3) Interrupt Disable Register -AT91C_US3_MR EQU (0xFFFCC004) ;- (US3) Mode Register -AT91C_US3_XXR EQU (0xFFFCC048) ;- (US3) XON_XOFF Register -AT91C_US3_FIDI EQU (0xFFFCC040) ;- (US3) FI_DI_Ratio Register -AT91C_US3_TTGR EQU (0xFFFCC028) ;- (US3) Transmitter Time-guard Register -AT91C_US3_BRGR EQU (0xFFFCC020) ;- (US3) Baud Rate Generator Register -AT91C_US3_RHR EQU (0xFFFCC018) ;- (US3) Receiver Holding Register -AT91C_US3_IMR EQU (0xFFFCC010) ;- (US3) Interrupt Mask Register -AT91C_US3_IER EQU (0xFFFCC008) ;- (US3) Interrupt Enable Register -AT91C_US3_CR EQU (0xFFFCC000) ;- (US3) Control Register -;- ========== Register definition for PDC_US2 peripheral ========== -AT91C_US2_PTSR EQU (0xFFFC8124) ;- (PDC_US2) PDC Transfer Status Register -AT91C_US2_TNCR EQU (0xFFFC811C) ;- (PDC_US2) Transmit Next Counter Register -AT91C_US2_RNCR EQU (0xFFFC8114) ;- (PDC_US2) Receive Next Counter Register -AT91C_US2_TCR EQU (0xFFFC810C) ;- (PDC_US2) Transmit Counter Register -AT91C_US2_PTCR EQU (0xFFFC8120) ;- (PDC_US2) PDC Transfer Control Register -AT91C_US2_RCR EQU (0xFFFC8104) ;- (PDC_US2) Receive Counter Register -AT91C_US2_TNPR EQU (0xFFFC8118) ;- (PDC_US2) Transmit Next Pointer Register -AT91C_US2_RPR EQU (0xFFFC8100) ;- (PDC_US2) Receive Pointer Register -AT91C_US2_TPR EQU (0xFFFC8108) ;- (PDC_US2) Transmit Pointer Register -AT91C_US2_RNPR EQU (0xFFFC8110) ;- (PDC_US2) Receive Next Pointer Register -;- ========== Register definition for US2 peripheral ========== -AT91C_US2_XXR EQU (0xFFFC8048) ;- (US2) XON_XOFF Register -AT91C_US2_FIDI EQU (0xFFFC8040) ;- (US2) FI_DI_Ratio Register -AT91C_US2_TTGR EQU (0xFFFC8028) ;- (US2) Transmitter Time-guard Register -AT91C_US2_BRGR EQU (0xFFFC8020) ;- (US2) Baud Rate Generator Register -AT91C_US2_RHR EQU (0xFFFC8018) ;- (US2) Receiver Holding Register -AT91C_US2_IMR EQU (0xFFFC8010) ;- (US2) Interrupt Mask Register -AT91C_US2_IER EQU (0xFFFC8008) ;- (US2) Interrupt Enable Register -AT91C_US2_CR EQU (0xFFFC8000) ;- (US2) Control Register -AT91C_US2_IF EQU (0xFFFC804C) ;- (US2) IRDA_FILTER Register -AT91C_US2_NER EQU (0xFFFC8044) ;- (US2) Nb Errors Register -AT91C_US2_RTOR EQU (0xFFFC8024) ;- (US2) Receiver Time-out Register -AT91C_US2_THR EQU (0xFFFC801C) ;- (US2) Transmitter Holding Register -AT91C_US2_CSR EQU (0xFFFC8014) ;- (US2) Channel Status Register -AT91C_US2_IDR EQU (0xFFFC800C) ;- (US2) Interrupt Disable Register -AT91C_US2_MR EQU (0xFFFC8004) ;- (US2) Mode Register -;- ========== Register definition for PDC_US1 peripheral ========== -AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register -AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register -AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register -AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register -AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register -AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register -AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register -AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register -AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register -AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register -;- ========== Register definition for US1 peripheral ========== -AT91C_US1_XXR EQU (0xFFFC4048) ;- (US1) XON_XOFF Register -AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register -AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register -AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register -AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register -AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register -AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register -AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register -AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register -AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register -AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register -AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register -AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register -AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register -AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register -;- ========== Register definition for PDC_US0 peripheral ========== -AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register -AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register -AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register -AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register -AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register -AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register -AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register -AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register -AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register -AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register -;- ========== Register definition for US0 peripheral ========== -AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register -AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register -AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register -AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register -AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register -AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register -AT91C_US0_XXR EQU (0xFFFC0048) ;- (US0) XON_XOFF Register -AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register -AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register -AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register -AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register -AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register -AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register -AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register -AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register -;- ========== Register definition for TWI peripheral ========== -AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register -AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register -AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register -AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register -AT91C_TWI_SMR EQU (0xFFFB8008) ;- (TWI) Slave Mode Register -AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register -AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register -AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register -AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register -AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register -AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register -;- ========== Register definition for PDC_MCI peripheral ========== -AT91C_MCI_PTCR EQU (0xFFFB4120) ;- (PDC_MCI) PDC Transfer Control Register -AT91C_MCI_TNPR EQU (0xFFFB4118) ;- (PDC_MCI) Transmit Next Pointer Register -AT91C_MCI_RNPR EQU (0xFFFB4110) ;- (PDC_MCI) Receive Next Pointer Register -AT91C_MCI_TPR EQU (0xFFFB4108) ;- (PDC_MCI) Transmit Pointer Register -AT91C_MCI_RPR EQU (0xFFFB4100) ;- (PDC_MCI) Receive Pointer Register -AT91C_MCI_PTSR EQU (0xFFFB4124) ;- (PDC_MCI) PDC Transfer Status Register -AT91C_MCI_TNCR EQU (0xFFFB411C) ;- (PDC_MCI) Transmit Next Counter Register -AT91C_MCI_RNCR EQU (0xFFFB4114) ;- (PDC_MCI) Receive Next Counter Register -AT91C_MCI_TCR EQU (0xFFFB410C) ;- (PDC_MCI) Transmit Counter Register -AT91C_MCI_RCR EQU (0xFFFB4104) ;- (PDC_MCI) Receive Counter Register -;- ========== Register definition for MCI peripheral ========== -AT91C_MCI_IDR EQU (0xFFFB4048) ;- (MCI) MCI Interrupt Disable Register -AT91C_MCI_SR EQU (0xFFFB4040) ;- (MCI) MCI Status Register -AT91C_MCI_RDR EQU (0xFFFB4030) ;- (MCI) MCI Receive Data Register -AT91C_MCI_RSPR EQU (0xFFFB4020) ;- (MCI) MCI Response Register -AT91C_MCI_ARGR EQU (0xFFFB4010) ;- (MCI) MCI Argument Register -AT91C_MCI_DTOR EQU (0xFFFB4008) ;- (MCI) MCI Data Timeout Register -AT91C_MCI_CR EQU (0xFFFB4000) ;- (MCI) MCI Control Register -AT91C_MCI_IMR EQU (0xFFFB404C) ;- (MCI) MCI Interrupt Mask Register -AT91C_MCI_IER EQU (0xFFFB4044) ;- (MCI) MCI Interrupt Enable Register -AT91C_MCI_TDR EQU (0xFFFB4034) ;- (MCI) MCI Transmit Data Register -AT91C_MCI_CMDR EQU (0xFFFB4014) ;- (MCI) MCI Command Register -AT91C_MCI_SDCR EQU (0xFFFB400C) ;- (MCI) MCI SD Card Register -AT91C_MCI_MR EQU (0xFFFB4004) ;- (MCI) MCI Mode Register -;- ========== Register definition for UDP peripheral ========== -AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register -AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register -AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register -AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register -AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register -AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register -AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register -AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register -AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register -AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register -AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register -;- ========== Register definition for TC5 peripheral ========== -AT91C_TC5_CMR EQU (0xFFFA4084) ;- (TC5) Channel Mode Register -AT91C_TC5_IDR EQU (0xFFFA40A8) ;- (TC5) Interrupt Disable Register -AT91C_TC5_SR EQU (0xFFFA40A0) ;- (TC5) Status Register -AT91C_TC5_RB EQU (0xFFFA4098) ;- (TC5) Register B -AT91C_TC5_CV EQU (0xFFFA4090) ;- (TC5) Counter Value -AT91C_TC5_CCR EQU (0xFFFA4080) ;- (TC5) Channel Control Register -AT91C_TC5_IMR EQU (0xFFFA40AC) ;- (TC5) Interrupt Mask Register -AT91C_TC5_IER EQU (0xFFFA40A4) ;- (TC5) Interrupt Enable Register -AT91C_TC5_RC EQU (0xFFFA409C) ;- (TC5) Register C -AT91C_TC5_RA EQU (0xFFFA4094) ;- (TC5) Register A -;- ========== Register definition for TC4 peripheral ========== -AT91C_TC4_IMR EQU (0xFFFA406C) ;- (TC4) Interrupt Mask Register -AT91C_TC4_IER EQU (0xFFFA4064) ;- (TC4) Interrupt Enable Register -AT91C_TC4_RC EQU (0xFFFA405C) ;- (TC4) Register C -AT91C_TC4_RA EQU (0xFFFA4054) ;- (TC4) Register A -AT91C_TC4_CMR EQU (0xFFFA4044) ;- (TC4) Channel Mode Register -AT91C_TC4_IDR EQU (0xFFFA4068) ;- (TC4) Interrupt Disable Register -AT91C_TC4_SR EQU (0xFFFA4060) ;- (TC4) Status Register -AT91C_TC4_RB EQU (0xFFFA4058) ;- (TC4) Register B -AT91C_TC4_CV EQU (0xFFFA4050) ;- (TC4) Counter Value -AT91C_TC4_CCR EQU (0xFFFA4040) ;- (TC4) Channel Control Register -;- ========== Register definition for TC3 peripheral ========== -AT91C_TC3_IMR EQU (0xFFFA402C) ;- (TC3) Interrupt Mask Register -AT91C_TC3_CV EQU (0xFFFA4010) ;- (TC3) Counter Value -AT91C_TC3_CCR EQU (0xFFFA4000) ;- (TC3) Channel Control Register -AT91C_TC3_IER EQU (0xFFFA4024) ;- (TC3) Interrupt Enable Register -AT91C_TC3_CMR EQU (0xFFFA4004) ;- (TC3) Channel Mode Register -AT91C_TC3_RA EQU (0xFFFA4014) ;- (TC3) Register A -AT91C_TC3_RC EQU (0xFFFA401C) ;- (TC3) Register C -AT91C_TC3_IDR EQU (0xFFFA4028) ;- (TC3) Interrupt Disable Register -AT91C_TC3_RB EQU (0xFFFA4018) ;- (TC3) Register B -AT91C_TC3_SR EQU (0xFFFA4020) ;- (TC3) Status Register -;- ========== Register definition for TCB1 peripheral ========== -AT91C_TCB1_BCR EQU (0xFFFA4140) ;- (TCB1) TC Block Control Register -AT91C_TCB1_BMR EQU (0xFFFA4144) ;- (TCB1) TC Block Mode Register -;- ========== Register definition for TC2 peripheral ========== -AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register -AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register -AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C -AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A -AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register -AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register -AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register -AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B -AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value -AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register -;- ========== Register definition for TC1 peripheral ========== -AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register -AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register -AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C -AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A -AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register -AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register -AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register -AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B -AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value -AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register -;- ========== Register definition for TC0 peripheral ========== -AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register -AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register -AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C -AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A -AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register -AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register -AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register -AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B -AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value -AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register -;- ========== Register definition for TCB0 peripheral ========== -AT91C_TCB0_BMR EQU (0xFFFA00C4) ;- (TCB0) TC Block Mode Register -AT91C_TCB0_BCR EQU (0xFFFA00C0) ;- (TCB0) TC Block Control Register -;- ========== Register definition for UHP peripheral ========== -AT91C_UHP_HcRhDescriptorA EQU (0x00300048) ;- (UHP) Root Hub characteristics A -AT91C_UHP_HcRhPortStatus EQU (0x00300054) ;- (UHP) Root Hub Port Status Register -AT91C_UHP_HcRhDescriptorB EQU (0x0030004C) ;- (UHP) Root Hub characteristics B -AT91C_UHP_HcControl EQU (0x00300004) ;- (UHP) Operating modes for the Host Controller -AT91C_UHP_HcInterruptStatus EQU (0x0030000C) ;- (UHP) Interrupt Status Register -AT91C_UHP_HcRhStatus EQU (0x00300050) ;- (UHP) Root Hub Status register -AT91C_UHP_HcRevision EQU (0x00300000) ;- (UHP) Revision -AT91C_UHP_HcCommandStatus EQU (0x00300008) ;- (UHP) Command & status Register -AT91C_UHP_HcInterruptEnable EQU (0x00300010) ;- (UHP) Interrupt Enable Register -AT91C_UHP_HcHCCA EQU (0x00300018) ;- (UHP) Pointer to the Host Controller Communication Area -AT91C_UHP_HcControlHeadED EQU (0x00300020) ;- (UHP) First Endpoint Descriptor of the Control list -AT91C_UHP_HcInterruptDisable EQU (0x00300014) ;- (UHP) Interrupt Disable Register -AT91C_UHP_HcPeriodCurrentED EQU (0x0030001C) ;- (UHP) Current Isochronous or Interrupt Endpoint Descriptor -AT91C_UHP_HcControlCurrentED EQU (0x00300024) ;- (UHP) Endpoint Control and Status Register -AT91C_UHP_HcBulkCurrentED EQU (0x0030002C) ;- (UHP) Current endpoint of the Bulk list -AT91C_UHP_HcFmInterval EQU (0x00300034) ;- (UHP) Bit time between 2 consecutive SOFs -AT91C_UHP_HcBulkHeadED EQU (0x00300028) ;- (UHP) First endpoint register of the Bulk list -AT91C_UHP_HcBulkDoneHead EQU (0x00300030) ;- (UHP) Last completed transfer descriptor -AT91C_UHP_HcFmRemaining EQU (0x00300038) ;- (UHP) Bit time remaining in the current Frame -AT91C_UHP_HcPeriodicStart EQU (0x00300040) ;- (UHP) Periodic Start -AT91C_UHP_HcLSThreshold EQU (0x00300044) ;- (UHP) LS Threshold -AT91C_UHP_HcFmNumber EQU (0x0030003C) ;- (UHP) Frame number -;- ========== Register definition for EMAC peripheral ========== -AT91C_EMAC_RSR EQU (0xFFFBC020) ;- (EMAC) Receive Status Register -AT91C_EMAC_MAN EQU (0xFFFBC034) ;- (EMAC) PHY Maintenance Register -AT91C_EMAC_HSH EQU (0xFFFBC090) ;- (EMAC) Hash Address High[63:32] -AT91C_EMAC_MCOL EQU (0xFFFBC048) ;- (EMAC) Multiple Collision Frame Register -AT91C_EMAC_IER EQU (0xFFFBC028) ;- (EMAC) Interrupt Enable Register -AT91C_EMAC_SA2H EQU (0xFFFBC0A4) ;- (EMAC) Specific Address 2 High, Last 2 bytes -AT91C_EMAC_HSL EQU (0xFFFBC094) ;- (EMAC) Hash Address Low[31:0] -AT91C_EMAC_LCOL EQU (0xFFFBC05C) ;- (EMAC) Late Collision Register -AT91C_EMAC_OK EQU (0xFFFBC04C) ;- (EMAC) Frames Received OK Register -AT91C_EMAC_CFG EQU (0xFFFBC004) ;- (EMAC) Network Configuration Register -AT91C_EMAC_SA3L EQU (0xFFFBC0A8) ;- (EMAC) Specific Address 3 Low, First 4 bytes -AT91C_EMAC_SEQE EQU (0xFFFBC050) ;- (EMAC) Frame Check Sequence Error Register -AT91C_EMAC_ECOL EQU (0xFFFBC060) ;- (EMAC) Excessive Collision Register -AT91C_EMAC_ELR EQU (0xFFFBC070) ;- (EMAC) Excessive Length Error Register -AT91C_EMAC_SR EQU (0xFFFBC008) ;- (EMAC) Network Status Register -AT91C_EMAC_RBQP EQU (0xFFFBC018) ;- (EMAC) Receive Buffer Queue Pointer -AT91C_EMAC_CSE EQU (0xFFFBC064) ;- (EMAC) Carrier Sense Error Register -AT91C_EMAC_RJB EQU (0xFFFBC074) ;- (EMAC) Receive Jabber Register -AT91C_EMAC_USF EQU (0xFFFBC078) ;- (EMAC) Undersize Frame Register -AT91C_EMAC_IDR EQU (0xFFFBC02C) ;- (EMAC) Interrupt Disable Register -AT91C_EMAC_SA1L EQU (0xFFFBC098) ;- (EMAC) Specific Address 1 Low, First 4 bytes -AT91C_EMAC_IMR EQU (0xFFFBC030) ;- (EMAC) Interrupt Mask Register -AT91C_EMAC_FRA EQU (0xFFFBC040) ;- (EMAC) Frames Transmitted OK Register -AT91C_EMAC_SA3H EQU (0xFFFBC0AC) ;- (EMAC) Specific Address 3 High, Last 2 bytes -AT91C_EMAC_SA1H EQU (0xFFFBC09C) ;- (EMAC) Specific Address 1 High, Last 2 bytes -AT91C_EMAC_SCOL EQU (0xFFFBC044) ;- (EMAC) Single Collision Frame Register -AT91C_EMAC_ALE EQU (0xFFFBC054) ;- (EMAC) Alignment Error Register -AT91C_EMAC_TAR EQU (0xFFFBC00C) ;- (EMAC) Transmit Address Register -AT91C_EMAC_SA4L EQU (0xFFFBC0B0) ;- (EMAC) Specific Address 4 Low, First 4 bytes -AT91C_EMAC_SA2L EQU (0xFFFBC0A0) ;- (EMAC) Specific Address 2 Low, First 4 bytes -AT91C_EMAC_TUE EQU (0xFFFBC068) ;- (EMAC) Transmit Underrun Error Register -AT91C_EMAC_DTE EQU (0xFFFBC058) ;- (EMAC) Deferred Transmission Frame Register -AT91C_EMAC_TCR EQU (0xFFFBC010) ;- (EMAC) Transmit Control Register -AT91C_EMAC_CTL EQU (0xFFFBC000) ;- (EMAC) Network Control Register -AT91C_EMAC_SA4H EQU (0xFFFBC0B4) ;- (EMAC) Specific Address 4 High, Last 2 bytesr -AT91C_EMAC_CDE EQU (0xFFFBC06C) ;- (EMAC) Code Error Register -AT91C_EMAC_SQEE EQU (0xFFFBC07C) ;- (EMAC) SQE Test Error Register -AT91C_EMAC_TSR EQU (0xFFFBC014) ;- (EMAC) Transmit Status Register -AT91C_EMAC_DRFC EQU (0xFFFBC080) ;- (EMAC) Discarded RX Frame Register -;- ========== Register definition for EBI peripheral ========== -AT91C_EBI_CFGR EQU (0xFFFFFF64) ;- (EBI) Configuration Register -AT91C_EBI_CSA EQU (0xFFFFFF60) ;- (EBI) Chip Select Assignment Register -;- ========== Register definition for SMC2 peripheral ========== -AT91C_SMC2_CSR EQU (0xFFFFFF70) ;- (SMC2) SMC2 Chip Select Register -;- ========== Register definition for SDRC peripheral ========== -AT91C_SDRC_IMR EQU (0xFFFFFFAC) ;- (SDRC) SDRAM Controller Interrupt Mask Register -AT91C_SDRC_IER EQU (0xFFFFFFA4) ;- (SDRC) SDRAM Controller Interrupt Enable Register -AT91C_SDRC_SRR EQU (0xFFFFFF9C) ;- (SDRC) SDRAM Controller Self Refresh Register -AT91C_SDRC_TR EQU (0xFFFFFF94) ;- (SDRC) SDRAM Controller Refresh Timer Register -AT91C_SDRC_ISR EQU (0xFFFFFFB0) ;- (SDRC) SDRAM Controller Interrupt Mask Register -AT91C_SDRC_IDR EQU (0xFFFFFFA8) ;- (SDRC) SDRAM Controller Interrupt Disable Register -AT91C_SDRC_LPR EQU (0xFFFFFFA0) ;- (SDRC) SDRAM Controller Low Power Register -AT91C_SDRC_CR EQU (0xFFFFFF98) ;- (SDRC) SDRAM Controller Configuration Register -AT91C_SDRC_MR EQU (0xFFFFFF90) ;- (SDRC) SDRAM Controller Mode Register -;- ========== Register definition for BFC peripheral ========== -AT91C_BFC_MR EQU (0xFFFFFFC0) ;- (BFC) BFC Mode Register - -;- ***************************************************************************** -;- PIO DEFINITIONS FOR AT91RM9200 -;- ***************************************************************************** -AT91C_PIO_PA0 EQU (1:SHL:0) ;- Pin Controlled by PA0 -AT91C_PA0_MISO EQU (AT91C_PIO_PA0) ;- SPI Master In Slave -AT91C_PA0_PCK3 EQU (AT91C_PIO_PA0) ;- PMC Programmable Clock Output 3 -AT91C_PIO_PA1 EQU (1:SHL:1) ;- Pin Controlled by PA1 -AT91C_PA1_MOSI EQU (AT91C_PIO_PA1) ;- SPI Master Out Slave -AT91C_PA1_PCK0 EQU (AT91C_PIO_PA1) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PA10 EQU (1:SHL:10) ;- Pin Controlled by PA10 -AT91C_PA10_ETX1 EQU (AT91C_PIO_PA10) ;- Ethernet MAC Transmit Data 1 -AT91C_PA10_MCDB1 EQU (AT91C_PIO_PA10) ;- Multimedia Card B Data 1 -AT91C_PIO_PA11 EQU (1:SHL:11) ;- Pin Controlled by PA11 -AT91C_PA11_ECRS_ECRSDV EQU (AT91C_PIO_PA11) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -AT91C_PA11_MCDB2 EQU (AT91C_PIO_PA11) ;- Multimedia Card B Data 2 -AT91C_PIO_PA12 EQU (1:SHL:12) ;- Pin Controlled by PA12 -AT91C_PA12_ERX0 EQU (AT91C_PIO_PA12) ;- Ethernet MAC Receive Data 0 -AT91C_PA12_MCDB3 EQU (AT91C_PIO_PA12) ;- Multimedia Card B Data 3 -AT91C_PIO_PA13 EQU (1:SHL:13) ;- Pin Controlled by PA13 -AT91C_PA13_ERX1 EQU (AT91C_PIO_PA13) ;- Ethernet MAC Receive Data 1 -AT91C_PA13_TCLK0 EQU (AT91C_PIO_PA13) ;- Timer Counter 0 external clock input -AT91C_PIO_PA14 EQU (1:SHL:14) ;- Pin Controlled by PA14 -AT91C_PA14_ERXER EQU (AT91C_PIO_PA14) ;- Ethernet MAC Receive Error -AT91C_PA14_TCLK1 EQU (AT91C_PIO_PA14) ;- Timer Counter 1 external clock input -AT91C_PIO_PA15 EQU (1:SHL:15) ;- Pin Controlled by PA15 -AT91C_PA15_EMDC EQU (AT91C_PIO_PA15) ;- Ethernet MAC Management Data Clock -AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input -AT91C_PIO_PA16 EQU (1:SHL:16) ;- Pin Controlled by PA16 -AT91C_PA16_EMDIO EQU (AT91C_PIO_PA16) ;- Ethernet MAC Management Data Input/Output -AT91C_PA16_IRQ6 EQU (AT91C_PIO_PA16) ;- AIC Interrupt input 6 -AT91C_PIO_PA17 EQU (1:SHL:17) ;- Pin Controlled by PA17 -AT91C_PA17_TXD0 EQU (AT91C_PIO_PA17) ;- USART 0 Transmit Data -AT91C_PA17_TIOA0 EQU (AT91C_PIO_PA17) ;- Timer Counter 0 Multipurpose Timer I/O Pin A -AT91C_PIO_PA18 EQU (1:SHL:18) ;- Pin Controlled by PA18 -AT91C_PA18_RXD0 EQU (AT91C_PIO_PA18) ;- USART 0 Receive Data -AT91C_PA18_TIOB0 EQU (AT91C_PIO_PA18) ;- Timer Counter 0 Multipurpose Timer I/O Pin B -AT91C_PIO_PA19 EQU (1:SHL:19) ;- Pin Controlled by PA19 -AT91C_PA19_SCK0 EQU (AT91C_PIO_PA19) ;- USART 0 Serial Clock -AT91C_PA19_TIOA1 EQU (AT91C_PIO_PA19) ;- Timer Counter 1 Multipurpose Timer I/O Pin A -AT91C_PIO_PA2 EQU (1:SHL:2) ;- Pin Controlled by PA2 -AT91C_PA2_SPCK EQU (AT91C_PIO_PA2) ;- SPI Serial Clock -AT91C_PA2_IRQ4 EQU (AT91C_PIO_PA2) ;- AIC Interrupt Input 4 -AT91C_PIO_PA20 EQU (1:SHL:20) ;- Pin Controlled by PA20 -AT91C_PA20_CTS0 EQU (AT91C_PIO_PA20) ;- USART 0 Clear To Send -AT91C_PA20_TIOB1 EQU (AT91C_PIO_PA20) ;- Timer Counter 1 Multipurpose Timer I/O Pin B -AT91C_PIO_PA21 EQU (1:SHL:21) ;- Pin Controlled by PA21 -AT91C_PA21_RTS0 EQU (AT91C_PIO_PA21) ;- Usart 0 Ready To Send -AT91C_PA21_TIOA2 EQU (AT91C_PIO_PA21) ;- Timer Counter 2 Multipurpose Timer I/O Pin A -AT91C_PIO_PA22 EQU (1:SHL:22) ;- Pin Controlled by PA22 -AT91C_PA22_RXD2 EQU (AT91C_PIO_PA22) ;- USART 2 Receive Data -AT91C_PA22_TIOB2 EQU (AT91C_PIO_PA22) ;- Timer Counter 2 Multipurpose Timer I/O Pin B -AT91C_PIO_PA23 EQU (1:SHL:23) ;- Pin Controlled by PA23 -AT91C_PA23_TXD2 EQU (AT91C_PIO_PA23) ;- USART 2 Transmit Data -AT91C_PA23_IRQ3 EQU (AT91C_PIO_PA23) ;- Interrupt input 3 -AT91C_PIO_PA24 EQU (1:SHL:24) ;- Pin Controlled by PA24 -AT91C_PA24_SCK2 EQU (AT91C_PIO_PA24) ;- USART2 Serial Clock -AT91C_PA24_PCK1 EQU (AT91C_PIO_PA24) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA25 EQU (1:SHL:25) ;- Pin Controlled by PA25 -AT91C_PA25_TWD EQU (AT91C_PIO_PA25) ;- TWI Two-wire Serial Data -AT91C_PA25_IRQ2 EQU (AT91C_PIO_PA25) ;- Interrupt input 2 -AT91C_PIO_PA26 EQU (1:SHL:26) ;- Pin Controlled by PA26 -AT91C_PA26_TWCK EQU (AT91C_PIO_PA26) ;- TWI Two-wire Serial Clock -AT91C_PA26_IRQ1 EQU (AT91C_PIO_PA26) ;- Interrupt input 1 -AT91C_PIO_PA27 EQU (1:SHL:27) ;- Pin Controlled by PA27 -AT91C_PA27_MCCK EQU (AT91C_PIO_PA27) ;- Multimedia Card Clock -AT91C_PA27_TCLK3 EQU (AT91C_PIO_PA27) ;- Timer Counter 3 External Clock Input -AT91C_PIO_PA28 EQU (1:SHL:28) ;- Pin Controlled by PA28 -AT91C_PA28_MCCDA EQU (AT91C_PIO_PA28) ;- Multimedia Card A Command -AT91C_PA28_TCLK4 EQU (AT91C_PIO_PA28) ;- Timer Counter 4 external Clock Input -AT91C_PIO_PA29 EQU (1:SHL:29) ;- Pin Controlled by PA29 -AT91C_PA29_MCDA0 EQU (AT91C_PIO_PA29) ;- Multimedia Card A Data 0 -AT91C_PA29_TCLK5 EQU (AT91C_PIO_PA29) ;- Timer Counter 5 external clock input -AT91C_PIO_PA3 EQU (1:SHL:3) ;- Pin Controlled by PA3 -AT91C_PA3_NPCS0 EQU (AT91C_PIO_PA3) ;- SPI Peripheral Chip Select 0 -AT91C_PA3_IRQ5 EQU (AT91C_PIO_PA3) ;- AIC Interrupt Input 5 -AT91C_PIO_PA30 EQU (1:SHL:30) ;- Pin Controlled by PA30 -AT91C_PA30_DRXD EQU (AT91C_PIO_PA30) ;- DBGU Debug Receive Data -AT91C_PA30_CTS2 EQU (AT91C_PIO_PA30) ;- Usart 2 Clear To Send -AT91C_PIO_PA31 EQU (1:SHL:31) ;- Pin Controlled by PA31 -AT91C_PA31_DTXD EQU (AT91C_PIO_PA31) ;- DBGU Debug Transmit Data -AT91C_PA31_RTS2 EQU (AT91C_PIO_PA31) ;- USART 2 Ready To Send -AT91C_PIO_PA4 EQU (1:SHL:4) ;- Pin Controlled by PA4 -AT91C_PA4_NPCS1 EQU (AT91C_PIO_PA4) ;- SPI Peripheral Chip Select 1 -AT91C_PA4_PCK1 EQU (AT91C_PIO_PA4) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA5 EQU (1:SHL:5) ;- Pin Controlled by PA5 -AT91C_PA5_NPCS2 EQU (AT91C_PIO_PA5) ;- SPI Peripheral Chip Select 2 -AT91C_PA5_TXD3 EQU (AT91C_PIO_PA5) ;- USART 3 Transmit Data -AT91C_PIO_PA6 EQU (1:SHL:6) ;- Pin Controlled by PA6 -AT91C_PA6_NPCS3 EQU (AT91C_PIO_PA6) ;- SPI Peripheral Chip Select 3 -AT91C_PA6_RXD3 EQU (AT91C_PIO_PA6) ;- USART 3 Receive Data -AT91C_PIO_PA7 EQU (1:SHL:7) ;- Pin Controlled by PA7 -AT91C_PA7_ETXCK_EREFCK EQU (AT91C_PIO_PA7) ;- Ethernet MAC Transmit Clock/Reference Clock -AT91C_PA7_PCK2 EQU (AT91C_PIO_PA7) ;- PMC Programmable Clock 2 -AT91C_PIO_PA8 EQU (1:SHL:8) ;- Pin Controlled by PA8 -AT91C_PA8_ETXEN EQU (AT91C_PIO_PA8) ;- Ethernet MAC Transmit Enable -AT91C_PA8_MCCDB EQU (AT91C_PIO_PA8) ;- Multimedia Card B Command -AT91C_PIO_PA9 EQU (1:SHL:9) ;- Pin Controlled by PA9 -AT91C_PA9_ETX0 EQU (AT91C_PIO_PA9) ;- Ethernet MAC Transmit Data 0 -AT91C_PA9_MCDB0 EQU (AT91C_PIO_PA9) ;- Multimedia Card B Data 0 -AT91C_PIO_PB0 EQU (1:SHL:0) ;- Pin Controlled by PB0 -AT91C_PB0_TF0 EQU (AT91C_PIO_PB0) ;- SSC Transmit Frame Sync 0 -AT91C_PB0_TIOB3 EQU (AT91C_PIO_PB0) ;- Timer Counter 3 Multipurpose Timer I/O Pin B -AT91C_PIO_PB1 EQU (1:SHL:1) ;- Pin Controlled by PB1 -AT91C_PB1_TK0 EQU (AT91C_PIO_PB1) ;- SSC Transmit Clock 0 -AT91C_PB1_CTS3 EQU (AT91C_PIO_PB1) ;- USART 3 Clear To Send -AT91C_PIO_PB10 EQU (1:SHL:10) ;- Pin Controlled by PB10 -AT91C_PB10_RK1 EQU (AT91C_PIO_PB10) ;- SSC Receive Clock 1 -AT91C_PB10_TIOA5 EQU (AT91C_PIO_PB10) ;- Timer Counter 5 Multipurpose Timer I/O Pin A -AT91C_PIO_PB11 EQU (1:SHL:11) ;- Pin Controlled by PB11 -AT91C_PB11_RF1 EQU (AT91C_PIO_PB11) ;- SSC Receive Frame Sync 1 -AT91C_PB11_TIOB5 EQU (AT91C_PIO_PB11) ;- Timer Counter 5 Multipurpose Timer I/O Pin B -AT91C_PIO_PB12 EQU (1:SHL:12) ;- Pin Controlled by PB12 -AT91C_PB12_TF2 EQU (AT91C_PIO_PB12) ;- SSC Transmit Frame Sync 2 -AT91C_PB12_ETX2 EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmit Data 2 -AT91C_PIO_PB13 EQU (1:SHL:13) ;- Pin Controlled by PB13 -AT91C_PB13_TK2 EQU (AT91C_PIO_PB13) ;- SSC Transmit Clock 2 -AT91C_PB13_ETX3 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Transmit Data 3 -AT91C_PIO_PB14 EQU (1:SHL:14) ;- Pin Controlled by PB14 -AT91C_PB14_TD2 EQU (AT91C_PIO_PB14) ;- SSC Transmit Data 2 -AT91C_PB14_ETXER EQU (AT91C_PIO_PB14) ;- Ethernet MAC Transmikt Coding Error -AT91C_PIO_PB15 EQU (1:SHL:15) ;- Pin Controlled by PB15 -AT91C_PB15_RD2 EQU (AT91C_PIO_PB15) ;- SSC Receive Data 2 -AT91C_PB15_ERX2 EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data 2 -AT91C_PIO_PB16 EQU (1:SHL:16) ;- Pin Controlled by PB16 -AT91C_PB16_RK2 EQU (AT91C_PIO_PB16) ;- SSC Receive Clock 2 -AT91C_PB16_ERX3 EQU (AT91C_PIO_PB16) ;- Ethernet MAC Receive Data 3 -AT91C_PIO_PB17 EQU (1:SHL:17) ;- Pin Controlled by PB17 -AT91C_PB17_RF2 EQU (AT91C_PIO_PB17) ;- SSC Receive Frame Sync 2 -AT91C_PB17_ERXDV EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Data Valid -AT91C_PIO_PB18 EQU (1:SHL:18) ;- Pin Controlled by PB18 -AT91C_PB18_RI1 EQU (AT91C_PIO_PB18) ;- USART 1 Ring Indicator -AT91C_PB18_ECOL EQU (AT91C_PIO_PB18) ;- Ethernet MAC Collision Detected -AT91C_PIO_PB19 EQU (1:SHL:19) ;- Pin Controlled by PB19 -AT91C_PB19_DTR1 EQU (AT91C_PIO_PB19) ;- USART 1 Data Terminal ready -AT91C_PB19_ERXCK EQU (AT91C_PIO_PB19) ;- Ethernet MAC Receive Clock -AT91C_PIO_PB2 EQU (1:SHL:2) ;- Pin Controlled by PB2 -AT91C_PB2_TD0 EQU (AT91C_PIO_PB2) ;- SSC Transmit data -AT91C_PB2_SCK3 EQU (AT91C_PIO_PB2) ;- USART 3 Serial Clock -AT91C_PIO_PB20 EQU (1:SHL:20) ;- Pin Controlled by PB20 -AT91C_PB20_TXD1 EQU (AT91C_PIO_PB20) ;- USART 1 Transmit Data -AT91C_PIO_PB21 EQU (1:SHL:21) ;- Pin Controlled by PB21 -AT91C_PB21_RXD1 EQU (AT91C_PIO_PB21) ;- USART 1 Receive Data -AT91C_PIO_PB22 EQU (1:SHL:22) ;- Pin Controlled by PB22 -AT91C_PB22_SCK1 EQU (AT91C_PIO_PB22) ;- USART1 Serial Clock -AT91C_PIO_PB23 EQU (1:SHL:23) ;- Pin Controlled by PB23 -AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect -AT91C_PIO_PB24 EQU (1:SHL:24) ;- Pin Controlled by PB24 -AT91C_PB24_CTS1 EQU (AT91C_PIO_PB24) ;- USART 1 Clear To Send -AT91C_PIO_PB25 EQU (1:SHL:25) ;- Pin Controlled by PB25 -AT91C_PB25_DSR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Set ready -AT91C_PB25_EF100 EQU (AT91C_PIO_PB25) ;- Ethernet MAC Force 100 Mbits/sec -AT91C_PIO_PB26 EQU (1:SHL:26) ;- Pin Controlled by PB26 -AT91C_PB26_RTS1 EQU (AT91C_PIO_PB26) ;- Usart 0 Ready To Send -AT91C_PIO_PB27 EQU (1:SHL:27) ;- Pin Controlled by PB27 -AT91C_PB27_PCK0 EQU (AT91C_PIO_PB27) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB28 EQU (1:SHL:28) ;- Pin Controlled by PB28 -AT91C_PB28_FIQ EQU (AT91C_PIO_PB28) ;- AIC Fast Interrupt Input -AT91C_PIO_PB29 EQU (1:SHL:29) ;- Pin Controlled by PB29 -AT91C_PB29_IRQ0 EQU (AT91C_PIO_PB29) ;- Interrupt input 0 -AT91C_PIO_PB3 EQU (1:SHL:3) ;- Pin Controlled by PB3 -AT91C_PB3_RD0 EQU (AT91C_PIO_PB3) ;- SSC Receive Data -AT91C_PB3_MCDA1 EQU (AT91C_PIO_PB3) ;- Multimedia Card A Data 1 -AT91C_PIO_PB4 EQU (1:SHL:4) ;- Pin Controlled by PB4 -AT91C_PB4_RK0 EQU (AT91C_PIO_PB4) ;- SSC Receive Clock -AT91C_PB4_MCDA2 EQU (AT91C_PIO_PB4) ;- Multimedia Card A Data 2 -AT91C_PIO_PB5 EQU (1:SHL:5) ;- Pin Controlled by PB5 -AT91C_PB5_RF0 EQU (AT91C_PIO_PB5) ;- SSC Receive Frame Sync 0 -AT91C_PB5_MCDA3 EQU (AT91C_PIO_PB5) ;- Multimedia Card A Data 3 -AT91C_PIO_PB6 EQU (1:SHL:6) ;- Pin Controlled by PB6 -AT91C_PB6_TF1 EQU (AT91C_PIO_PB6) ;- SSC Transmit Frame Sync 1 -AT91C_PB6_TIOA3 EQU (AT91C_PIO_PB6) ;- Timer Counter 4 Multipurpose Timer I/O Pin A -AT91C_PIO_PB7 EQU (1:SHL:7) ;- Pin Controlled by PB7 -AT91C_PB7_TK1 EQU (AT91C_PIO_PB7) ;- SSC Transmit Clock 1 -AT91C_PB7_TIOB3 EQU (AT91C_PIO_PB7) ;- Timer Counter 3 Multipurpose Timer I/O Pin B -AT91C_PIO_PB8 EQU (1:SHL:8) ;- Pin Controlled by PB8 -AT91C_PB8_TD1 EQU (AT91C_PIO_PB8) ;- SSC Transmit Data 1 -AT91C_PB8_TIOA4 EQU (AT91C_PIO_PB8) ;- Timer Counter 4 Multipurpose Timer I/O Pin A -AT91C_PIO_PB9 EQU (1:SHL:9) ;- Pin Controlled by PB9 -AT91C_PB9_RD1 EQU (AT91C_PIO_PB9) ;- SSC Receive Data 1 -AT91C_PB9_TIOB4 EQU (AT91C_PIO_PB9) ;- Timer Counter 4 Multipurpose Timer I/O Pin B -AT91C_PIO_PC0 EQU (1:SHL:0) ;- Pin Controlled by PC0 -AT91C_PC0_BFCK EQU (AT91C_PIO_PC0) ;- Burst Flash Clock -AT91C_PIO_PC1 EQU (1:SHL:1) ;- Pin Controlled by PC1 -AT91C_PC1_BFRDY_SMOE EQU (AT91C_PIO_PC1) ;- Burst Flash Ready -AT91C_PIO_PC10 EQU (1:SHL:10) ;- Pin Controlled by PC10 -AT91C_PC10_NCS4_CFCS EQU (AT91C_PIO_PC10) ;- Compact Flash Chip Select -AT91C_PIO_PC11 EQU (1:SHL:11) ;- Pin Controlled by PC11 -AT91C_PC11_NCS5_CFCE1 EQU (AT91C_PIO_PC11) ;- Chip Select 5 / Compact Flash Chip Enable 1 -AT91C_PIO_PC12 EQU (1:SHL:12) ;- Pin Controlled by PC12 -AT91C_PC12_NCS6_CFCE2 EQU (AT91C_PIO_PC12) ;- Chip Select 6 / Compact Flash Chip Enable 2 -AT91C_PIO_PC13 EQU (1:SHL:13) ;- Pin Controlled by PC13 -AT91C_PC13_NCS7 EQU (AT91C_PIO_PC13) ;- Chip Select 7 -AT91C_PIO_PC14 EQU (1:SHL:14) ;- Pin Controlled by PC14 -AT91C_PIO_PC15 EQU (1:SHL:15) ;- Pin Controlled by PC15 -AT91C_PIO_PC16 EQU (1:SHL:16) ;- Pin Controlled by PC16 -AT91C_PC16_D16 EQU (AT91C_PIO_PC16) ;- Data Bus [16] -AT91C_PIO_PC17 EQU (1:SHL:17) ;- Pin Controlled by PC17 -AT91C_PC17_D17 EQU (AT91C_PIO_PC17) ;- Data Bus [17] -AT91C_PIO_PC18 EQU (1:SHL:18) ;- Pin Controlled by PC18 -AT91C_PC18_D18 EQU (AT91C_PIO_PC18) ;- Data Bus [18] -AT91C_PIO_PC19 EQU (1:SHL:19) ;- Pin Controlled by PC19 -AT91C_PC19_D19 EQU (AT91C_PIO_PC19) ;- Data Bus [19] -AT91C_PIO_PC2 EQU (1:SHL:2) ;- Pin Controlled by PC2 -AT91C_PC2_BFAVD EQU (AT91C_PIO_PC2) ;- Burst Flash Address Valid -AT91C_PIO_PC20 EQU (1:SHL:20) ;- Pin Controlled by PC20 -AT91C_PC20_D20 EQU (AT91C_PIO_PC20) ;- Data Bus [20] -AT91C_PIO_PC21 EQU (1:SHL:21) ;- Pin Controlled by PC21 -AT91C_PC21_D21 EQU (AT91C_PIO_PC21) ;- Data Bus [21] -AT91C_PIO_PC22 EQU (1:SHL:22) ;- Pin Controlled by PC22 -AT91C_PC22_D22 EQU (AT91C_PIO_PC22) ;- Data Bus [22] -AT91C_PIO_PC23 EQU (1:SHL:23) ;- Pin Controlled by PC23 -AT91C_PC23_D23 EQU (AT91C_PIO_PC23) ;- Data Bus [23] -AT91C_PIO_PC24 EQU (1:SHL:24) ;- Pin Controlled by PC24 -AT91C_PC24_D24 EQU (AT91C_PIO_PC24) ;- Data Bus [24] -AT91C_PIO_PC25 EQU (1:SHL:25) ;- Pin Controlled by PC25 -AT91C_PC25_D25 EQU (AT91C_PIO_PC25) ;- Data Bus [25] -AT91C_PIO_PC26 EQU (1:SHL:26) ;- Pin Controlled by PC26 -AT91C_PC26_D26 EQU (AT91C_PIO_PC26) ;- Data Bus [26] -AT91C_PIO_PC27 EQU (1:SHL:27) ;- Pin Controlled by PC27 -AT91C_PC27_D27 EQU (AT91C_PIO_PC27) ;- Data Bus [27] -AT91C_PIO_PC28 EQU (1:SHL:28) ;- Pin Controlled by PC28 -AT91C_PC28_D28 EQU (AT91C_PIO_PC28) ;- Data Bus [28] -AT91C_PIO_PC29 EQU (1:SHL:29) ;- Pin Controlled by PC29 -AT91C_PC29_D29 EQU (AT91C_PIO_PC29) ;- Data Bus [29] -AT91C_PIO_PC3 EQU (1:SHL:3) ;- Pin Controlled by PC3 -AT91C_PC3_BFBAA_SMWE EQU (AT91C_PIO_PC3) ;- Burst Flash Address Advance / SmartMedia Write Enable -AT91C_PIO_PC30 EQU (1:SHL:30) ;- Pin Controlled by PC30 -AT91C_PC30_D30 EQU (AT91C_PIO_PC30) ;- Data Bus [30] -AT91C_PIO_PC31 EQU (1:SHL:31) ;- Pin Controlled by PC31 -AT91C_PC31_D31 EQU (AT91C_PIO_PC31) ;- Data Bus [31] -AT91C_PIO_PC4 EQU (1:SHL:4) ;- Pin Controlled by PC4 -AT91C_PC4_BFOE EQU (AT91C_PIO_PC4) ;- Burst Flash Output Enable -AT91C_PIO_PC5 EQU (1:SHL:5) ;- Pin Controlled by PC5 -AT91C_PC5_BFWE EQU (AT91C_PIO_PC5) ;- Burst Flash Write Enable -AT91C_PIO_PC6 EQU (1:SHL:6) ;- Pin Controlled by PC6 -AT91C_PC6_NWAIT EQU (AT91C_PIO_PC6) ;- NWAIT -AT91C_PIO_PC7 EQU (1:SHL:7) ;- Pin Controlled by PC7 -AT91C_PC7_A23 EQU (AT91C_PIO_PC7) ;- Address Bus[23] -AT91C_PIO_PC8 EQU (1:SHL:8) ;- Pin Controlled by PC8 -AT91C_PC8_A24 EQU (AT91C_PIO_PC8) ;- Address Bus[24] -AT91C_PIO_PC9 EQU (1:SHL:9) ;- Pin Controlled by PC9 -AT91C_PC9_A25_CFRNW EQU (AT91C_PIO_PC9) ;- Address Bus[25] / Compact Flash Read Not Write -AT91C_PIO_PD0 EQU (1:SHL:0) ;- Pin Controlled by PD0 -AT91C_PD0_ETX0 EQU (AT91C_PIO_PD0) ;- Ethernet MAC Transmit Data 0 -AT91C_PIO_PD1 EQU (1:SHL:1) ;- Pin Controlled by PD1 -AT91C_PD1_ETX1 EQU (AT91C_PIO_PD1) ;- Ethernet MAC Transmit Data 1 -AT91C_PIO_PD10 EQU (1:SHL:10) ;- Pin Controlled by PD10 -AT91C_PD10_PCK3 EQU (AT91C_PIO_PD10) ;- PMC Programmable Clock Output 3 -AT91C_PD10_TPS1 EQU (AT91C_PIO_PD10) ;- ETM ARM9 pipeline status 1 -AT91C_PIO_PD11 EQU (1:SHL:11) ;- Pin Controlled by PD11 -AT91C_PD11_ EQU (AT91C_PIO_PD11) ;- -AT91C_PD11_TPS2 EQU (AT91C_PIO_PD11) ;- ETM ARM9 pipeline status 2 -AT91C_PIO_PD12 EQU (1:SHL:12) ;- Pin Controlled by PD12 -AT91C_PD12_ EQU (AT91C_PIO_PD12) ;- -AT91C_PD12_TPK0 EQU (AT91C_PIO_PD12) ;- ETM Trace Packet 0 -AT91C_PIO_PD13 EQU (1:SHL:13) ;- Pin Controlled by PD13 -AT91C_PD13_ EQU (AT91C_PIO_PD13) ;- -AT91C_PD13_TPK1 EQU (AT91C_PIO_PD13) ;- ETM Trace Packet 1 -AT91C_PIO_PD14 EQU (1:SHL:14) ;- Pin Controlled by PD14 -AT91C_PD14_ EQU (AT91C_PIO_PD14) ;- -AT91C_PD14_TPK2 EQU (AT91C_PIO_PD14) ;- ETM Trace Packet 2 -AT91C_PIO_PD15 EQU (1:SHL:15) ;- Pin Controlled by PD15 -AT91C_PD15_TD0 EQU (AT91C_PIO_PD15) ;- SSC Transmit data -AT91C_PD15_TPK3 EQU (AT91C_PIO_PD15) ;- ETM Trace Packet 3 -AT91C_PIO_PD16 EQU (1:SHL:16) ;- Pin Controlled by PD16 -AT91C_PD16_TD1 EQU (AT91C_PIO_PD16) ;- SSC Transmit Data 1 -AT91C_PD16_TPK4 EQU (AT91C_PIO_PD16) ;- ETM Trace Packet 4 -AT91C_PIO_PD17 EQU (1:SHL:17) ;- Pin Controlled by PD17 -AT91C_PD17_TD2 EQU (AT91C_PIO_PD17) ;- SSC Transmit Data 2 -AT91C_PD17_TPK5 EQU (AT91C_PIO_PD17) ;- ETM Trace Packet 5 -AT91C_PIO_PD18 EQU (1:SHL:18) ;- Pin Controlled by PD18 -AT91C_PD18_NPCS1 EQU (AT91C_PIO_PD18) ;- SPI Peripheral Chip Select 1 -AT91C_PD18_TPK6 EQU (AT91C_PIO_PD18) ;- ETM Trace Packet 6 -AT91C_PIO_PD19 EQU (1:SHL:19) ;- Pin Controlled by PD19 -AT91C_PD19_NPCS2 EQU (AT91C_PIO_PD19) ;- SPI Peripheral Chip Select 2 -AT91C_PD19_TPK7 EQU (AT91C_PIO_PD19) ;- ETM Trace Packet 7 -AT91C_PIO_PD2 EQU (1:SHL:2) ;- Pin Controlled by PD2 -AT91C_PD2_ETX2 EQU (AT91C_PIO_PD2) ;- Ethernet MAC Transmit Data 2 -AT91C_PIO_PD20 EQU (1:SHL:20) ;- Pin Controlled by PD20 -AT91C_PD20_NPCS3 EQU (AT91C_PIO_PD20) ;- SPI Peripheral Chip Select 3 -AT91C_PD20_TPK8 EQU (AT91C_PIO_PD20) ;- ETM Trace Packet 8 -AT91C_PIO_PD21 EQU (1:SHL:21) ;- Pin Controlled by PD21 -AT91C_PD21_RTS0 EQU (AT91C_PIO_PD21) ;- Usart 0 Ready To Send -AT91C_PD21_TPK9 EQU (AT91C_PIO_PD21) ;- ETM Trace Packet 9 -AT91C_PIO_PD22 EQU (1:SHL:22) ;- Pin Controlled by PD22 -AT91C_PD22_RTS1 EQU (AT91C_PIO_PD22) ;- Usart 0 Ready To Send -AT91C_PD22_TPK10 EQU (AT91C_PIO_PD22) ;- ETM Trace Packet 10 -AT91C_PIO_PD23 EQU (1:SHL:23) ;- Pin Controlled by PD23 -AT91C_PD23_RTS2 EQU (AT91C_PIO_PD23) ;- USART 2 Ready To Send -AT91C_PD23_TPK11 EQU (AT91C_PIO_PD23) ;- ETM Trace Packet 11 -AT91C_PIO_PD24 EQU (1:SHL:24) ;- Pin Controlled by PD24 -AT91C_PD24_RTS3 EQU (AT91C_PIO_PD24) ;- USART 3 Ready To Send -AT91C_PD24_TPK12 EQU (AT91C_PIO_PD24) ;- ETM Trace Packet 12 -AT91C_PIO_PD25 EQU (1:SHL:25) ;- Pin Controlled by PD25 -AT91C_PD25_DTR1 EQU (AT91C_PIO_PD25) ;- USART 1 Data Terminal ready -AT91C_PD25_TPK13 EQU (AT91C_PIO_PD25) ;- ETM Trace Packet 13 -AT91C_PIO_PD26 EQU (1:SHL:26) ;- Pin Controlled by PD26 -AT91C_PD26_TPK14 EQU (AT91C_PIO_PD26) ;- ETM Trace Packet 14 -AT91C_PIO_PD27 EQU (1:SHL:27) ;- Pin Controlled by PD27 -AT91C_PD27_TPK15 EQU (AT91C_PIO_PD27) ;- ETM Trace Packet 15 -AT91C_PIO_PD3 EQU (1:SHL:3) ;- Pin Controlled by PD3 -AT91C_PD3_ETX3 EQU (AT91C_PIO_PD3) ;- Ethernet MAC Transmit Data 3 -AT91C_PIO_PD4 EQU (1:SHL:4) ;- Pin Controlled by PD4 -AT91C_PD4_ETXEN EQU (AT91C_PIO_PD4) ;- Ethernet MAC Transmit Enable -AT91C_PIO_PD5 EQU (1:SHL:5) ;- Pin Controlled by PD5 -AT91C_PD5_ETXER EQU (AT91C_PIO_PD5) ;- Ethernet MAC Transmikt Coding Error -AT91C_PIO_PD6 EQU (1:SHL:6) ;- Pin Controlled by PD6 -AT91C_PD6_DTXD EQU (AT91C_PIO_PD6) ;- DBGU Debug Transmit Data -AT91C_PIO_PD7 EQU (1:SHL:7) ;- Pin Controlled by PD7 -AT91C_PD7_PCK0 EQU (AT91C_PIO_PD7) ;- PMC Programmable Clock Output 0 -AT91C_PD7_TSYNC EQU (AT91C_PIO_PD7) ;- ETM Synchronization signal -AT91C_PIO_PD8 EQU (1:SHL:8) ;- Pin Controlled by PD8 -AT91C_PD8_PCK1 EQU (AT91C_PIO_PD8) ;- PMC Programmable Clock Output 1 -AT91C_PD8_TCLK EQU (AT91C_PIO_PD8) ;- ETM Trace Clock signal -AT91C_PIO_PD9 EQU (1:SHL:9) ;- Pin Controlled by PD9 -AT91C_PD9_PCK2 EQU (AT91C_PIO_PD9) ;- PMC Programmable Clock 2 -AT91C_PD9_TPS0 EQU (AT91C_PIO_PD9) ;- ETM ARM9 pipeline status 0 - -;- ***************************************************************************** -;- PERIPHERAL ID DEFINITIONS FOR AT91RM9200 -;- ***************************************************************************** -AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) -AT91C_ID_SYS EQU ( 1) ;- System Peripheral -AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A -AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B -AT91C_ID_PIOC EQU ( 4) ;- Parallel IO Controller C -AT91C_ID_PIOD EQU ( 5) ;- Parallel IO Controller D -AT91C_ID_US0 EQU ( 6) ;- USART 0 -AT91C_ID_US1 EQU ( 7) ;- USART 1 -AT91C_ID_US2 EQU ( 8) ;- USART 2 -AT91C_ID_US3 EQU ( 9) ;- USART 3 -AT91C_ID_MCI EQU (10) ;- Multimedia Card Interface -AT91C_ID_UDP EQU (11) ;- USB Device Port -AT91C_ID_TWI EQU (12) ;- Two-Wire Interface -AT91C_ID_SPI EQU (13) ;- Serial Peripheral Interface -AT91C_ID_SSC0 EQU (14) ;- Serial Synchronous Controller 0 -AT91C_ID_SSC1 EQU (15) ;- Serial Synchronous Controller 1 -AT91C_ID_SSC2 EQU (16) ;- Serial Synchronous Controller 2 -AT91C_ID_TC0 EQU (17) ;- Timer Counter 0 -AT91C_ID_TC1 EQU (18) ;- Timer Counter 1 -AT91C_ID_TC2 EQU (19) ;- Timer Counter 2 -AT91C_ID_TC3 EQU (20) ;- Timer Counter 3 -AT91C_ID_TC4 EQU (21) ;- Timer Counter 4 -AT91C_ID_TC5 EQU (22) ;- Timer Counter 5 -AT91C_ID_UHP EQU (23) ;- USB Host port -AT91C_ID_EMAC EQU (24) ;- Ethernet MAC -AT91C_ID_IRQ0 EQU (25) ;- Advanced Interrupt Controller (IRQ0) -AT91C_ID_IRQ1 EQU (26) ;- Advanced Interrupt Controller (IRQ1) -AT91C_ID_IRQ2 EQU (27) ;- Advanced Interrupt Controller (IRQ2) -AT91C_ID_IRQ3 EQU (28) ;- Advanced Interrupt Controller (IRQ3) -AT91C_ID_IRQ4 EQU (29) ;- Advanced Interrupt Controller (IRQ4) -AT91C_ID_IRQ5 EQU (30) ;- Advanced Interrupt Controller (IRQ5) -AT91C_ID_IRQ6 EQU (31) ;- Advanced Interrupt Controller (IRQ6) - -;- ***************************************************************************** -;- BASE ADDRESS DEFINITIONS FOR AT91RM9200 -;- ***************************************************************************** -AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address -AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address -AT91C_BASE_RTC EQU (0xFFFFFE00) ;- (RTC) Base Address -AT91C_BASE_ST EQU (0xFFFFFD00) ;- (ST) Base Address -AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address -AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address -AT91C_BASE_PIOD EQU (0xFFFFFA00) ;- (PIOD) Base Address -AT91C_BASE_PIOC EQU (0xFFFFF800) ;- (PIOC) Base Address -AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address -AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address -AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address -AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address -AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address -AT91C_BASE_PDC_SPI EQU (0xFFFE0100) ;- (PDC_SPI) Base Address -AT91C_BASE_SPI EQU (0xFFFE0000) ;- (SPI) Base Address -AT91C_BASE_PDC_SSC2 EQU (0xFFFD8100) ;- (PDC_SSC2) Base Address -AT91C_BASE_SSC2 EQU (0xFFFD8000) ;- (SSC2) Base Address -AT91C_BASE_PDC_SSC1 EQU (0xFFFD4100) ;- (PDC_SSC1) Base Address -AT91C_BASE_SSC1 EQU (0xFFFD4000) ;- (SSC1) Base Address -AT91C_BASE_PDC_SSC0 EQU (0xFFFD0100) ;- (PDC_SSC0) Base Address -AT91C_BASE_SSC0 EQU (0xFFFD0000) ;- (SSC0) Base Address -AT91C_BASE_PDC_US3 EQU (0xFFFCC100) ;- (PDC_US3) Base Address -AT91C_BASE_US3 EQU (0xFFFCC000) ;- (US3) Base Address -AT91C_BASE_PDC_US2 EQU (0xFFFC8100) ;- (PDC_US2) Base Address -AT91C_BASE_US2 EQU (0xFFFC8000) ;- (US2) Base Address -AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address -AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address -AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address -AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address -AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address -AT91C_BASE_PDC_MCI EQU (0xFFFB4100) ;- (PDC_MCI) Base Address -AT91C_BASE_MCI EQU (0xFFFB4000) ;- (MCI) Base Address -AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address -AT91C_BASE_TC5 EQU (0xFFFA4080) ;- (TC5) Base Address -AT91C_BASE_TC4 EQU (0xFFFA4040) ;- (TC4) Base Address -AT91C_BASE_TC3 EQU (0xFFFA4000) ;- (TC3) Base Address -AT91C_BASE_TCB1 EQU (0xFFFA4080) ;- (TCB1) Base Address -AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address -AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address -AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address -AT91C_BASE_TCB0 EQU (0xFFFA0000) ;- (TCB0) Base Address -AT91C_BASE_UHP EQU (0x00300000) ;- (UHP) Base Address -AT91C_BASE_EMAC EQU (0xFFFBC000) ;- (EMAC) Base Address -AT91C_BASE_EBI EQU (0xFFFFFF60) ;- (EBI) Base Address -AT91C_BASE_SMC2 EQU (0xFFFFFF70) ;- (SMC2) Base Address -AT91C_BASE_SDRC EQU (0xFFFFFF90) ;- (SDRC) Base Address -AT91C_BASE_BFC EQU (0xFFFFFFC0) ;- (BFC) Base Address - -;- ***************************************************************************** -;- MEMORY MAPPING DEFINITIONS FOR AT91RM9200 -;- ***************************************************************************** -AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address -AT91C_ISRAM_SIZE EQU (0x00004000) ;- Internal SRAM size in byte (16 Kbyte) -AT91C_IROM EQU (0x00100000) ;- Internal ROM base address -AT91C_IROM_SIZE EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte) - - - END diff --git a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200_inc.h b/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200_inc.h deleted file mode 100644 index dabab01c77..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200_inc.h +++ /dev/null @@ -1,2401 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// The software is delivered "AS IS" without warranty or condition of any -// kind, either express, implied or statutory. This includes without -// limitation any warranty or condition with respect to merchantability or -// fitness for any particular purpose, or against the infringements of -// intellectual property rights of others. -// ---------------------------------------------------------------------------- -// File Name : AT91RM9200.h -// Object : AT91RM9200 definitions -// Generated : AT91 SW Application Group 11/19/2003 (17:20:51) -// -// CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// -// CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// -// CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// -// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -// CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// -// CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// -// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// -// CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// -// CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// -// CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// -// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// -// CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// -// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// -// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// -// CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// -// CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// -// CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// -// CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// -// CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// -// CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// -// ---------------------------------------------------------------------------- - -// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_MC structure *** -#define MC_RCR ( 0) // MC Remap Control Register -#define MC_ASR ( 4) // MC Abort Status Register -#define MC_AASR ( 8) // MC Abort Address Status Register -#define MC_PUIA (16) // MC Protection Unit Area -#define MC_PUP (80) // MC Protection Unit Peripherals -#define MC_PUER (84) // MC Protection Unit Enable Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- -#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection -#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access -#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access -#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only -#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write -#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size -#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte -#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte -#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte -#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte -#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte -#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte -#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte -#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte -#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte -#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte -#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte -#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte -#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte -#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte -#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte -#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte -#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address -// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- -#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface -// ***************************************************************************** -// *** Register offset in AT91S_RTC structure *** -#define RTC_CR ( 0) // Control Register -#define RTC_MR ( 4) // Mode Register -#define RTC_TIMR ( 8) // Time Register -#define RTC_CALR (12) // Calendar Register -#define RTC_TIMALR (16) // Time Alarm Register -#define RTC_CALALR (20) // Calendar Alarm Register -#define RTC_SR (24) // Status Register -#define RTC_SCCR (28) // Status Clear Command Register -#define RTC_IER (32) // Interrupt Enable Register -#define RTC_IDR (36) // Interrupt Disable Register -#define RTC_IMR (40) // Interrupt Mask Register -#define RTC_VER (44) // Valid Entry Register -// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- -#define AT91C_RTC_UPDTIM (0x1 << 0) // (RTC) Update Request Time Register -#define AT91C_RTC_UPDCAL (0x1 << 1) // (RTC) Update Request Calendar Register -#define AT91C_RTC_TIMEVSEL (0x3 << 8) // (RTC) Time Event Selection -#define AT91C_RTC_TIMEVSEL_MINUTE (0x0 << 8) // (RTC) Minute change. -#define AT91C_RTC_TIMEVSEL_HOUR (0x1 << 8) // (RTC) Hour change. -#define AT91C_RTC_TIMEVSEL_DAY24 (0x2 << 8) // (RTC) Every day at midnight. -#define AT91C_RTC_TIMEVSEL_DAY12 (0x3 << 8) // (RTC) Every day at noon. -#define AT91C_RTC_CALEVSEL (0x3 << 16) // (RTC) Calendar Event Selection -#define AT91C_RTC_CALEVSEL_WEEK (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). -#define AT91C_RTC_CALEVSEL_MONTH (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). -#define AT91C_RTC_CALEVSEL_YEAR (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). -// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- -#define AT91C_RTC_HRMOD (0x1 << 0) // (RTC) 12-24 hour Mode -// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- -#define AT91C_RTC_SEC (0x7F << 0) // (RTC) Current Second -#define AT91C_RTC_MIN (0x7F << 8) // (RTC) Current Minute -#define AT91C_RTC_HOUR (0x1F << 16) // (RTC) Current Hour -#define AT91C_RTC_AMPM (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator -// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- -#define AT91C_RTC_CENT (0x3F << 0) // (RTC) Current Century -#define AT91C_RTC_YEAR (0xFF << 8) // (RTC) Current Year -#define AT91C_RTC_MONTH (0x1F << 16) // (RTC) Current Month -#define AT91C_RTC_DAY (0x7 << 21) // (RTC) Current Day -#define AT91C_RTC_DATE (0x3F << 24) // (RTC) Current Date -// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- -#define AT91C_RTC_SECEN (0x1 << 7) // (RTC) Second Alarm Enable -#define AT91C_RTC_MINEN (0x1 << 15) // (RTC) Minute Alarm -#define AT91C_RTC_HOUREN (0x1 << 23) // (RTC) Current Hour -// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- -#define AT91C_RTC_MONTHEN (0x1 << 23) // (RTC) Month Alarm Enable -#define AT91C_RTC_DATEEN (0x1 << 31) // (RTC) Date Alarm Enable -// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- -#define AT91C_RTC_ACKUPD (0x1 << 0) // (RTC) Acknowledge for Update -#define AT91C_RTC_ALARM (0x1 << 1) // (RTC) Alarm Flag -#define AT91C_RTC_SECEV (0x1 << 2) // (RTC) Second Event -#define AT91C_RTC_TIMEV (0x1 << 3) // (RTC) Time Event -#define AT91C_RTC_CALEV (0x1 << 4) // (RTC) Calendar event -// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- -// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- -// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- -// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- -// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- -#define AT91C_RTC_NVTIM (0x1 << 0) // (RTC) Non valid Time -#define AT91C_RTC_NVCAL (0x1 << 1) // (RTC) Non valid Calendar -#define AT91C_RTC_NVTIMALR (0x1 << 2) // (RTC) Non valid time Alarm -#define AT91C_RTC_NVCALALR (0x1 << 3) // (RTC) Nonvalid Calendar Alarm - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Timer Interface -// ***************************************************************************** -// *** Register offset in AT91S_ST structure *** -#define ST_CR ( 0) // Control Register -#define ST_PIMR ( 4) // Period Interval Mode Register -#define ST_WDMR ( 8) // Watchdog Mode Register -#define ST_RTMR (12) // Real-time Mode Register -#define ST_SR (16) // Status Register -#define ST_IER (20) // Interrupt Enable Register -#define ST_IDR (24) // Interrupt Disable Register -#define ST_IMR (28) // Interrupt Mask Register -#define ST_RTAR (32) // Real-time Alarm Register -#define ST_CRTR (36) // Current Real-time Register -// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- -#define AT91C_ST_WDRST (0x1 << 0) // (ST) Watchdog Timer Restart -// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- -#define AT91C_ST_PIV (0xFFFF << 0) // (ST) Watchdog Timer Restart -// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- -#define AT91C_ST_WDV (0xFFFF << 0) // (ST) Watchdog Timer Restart -#define AT91C_ST_RSTEN (0x1 << 16) // (ST) Reset Enable -#define AT91C_ST_EXTEN (0x1 << 17) // (ST) External Signal Assertion Enable -// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- -#define AT91C_ST_RTPRES (0xFFFF << 0) // (ST) Real-time Timer Prescaler Value -// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- -#define AT91C_ST_PITS (0x1 << 0) // (ST) Period Interval Timer Interrupt -#define AT91C_ST_WDOVF (0x1 << 1) // (ST) Watchdog Overflow -#define AT91C_ST_RTTINC (0x1 << 2) // (ST) Real-time Timer Increment -#define AT91C_ST_ALMS (0x1 << 3) // (ST) Alarm Status -// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- -// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- -// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- -// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- -#define AT91C_ST_ALMV (0xFFFFF << 0) // (ST) Alarm Value Value -// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- -#define AT91C_ST_CRTV (0xFFFFF << 0) // (ST) Current Real-time Value - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -// *** Register offset in AT91S_PMC structure *** -#define PMC_SCER ( 0) // System Clock Enable Register -#define PMC_SCDR ( 4) // System Clock Disable Register -#define PMC_SCSR ( 8) // System Clock Status Register -#define PMC_PCER (16) // Peripheral Clock Enable Register -#define PMC_PCDR (20) // Peripheral Clock Disable Register -#define PMC_PCSR (24) // Peripheral Clock Status Register -#define PMC_MCKR (48) // Master Clock Register -#define PMC_PCKR (64) // Programmable Clock Register -#define PMC_IER (96) // Interrupt Enable Register -#define PMC_IDR (100) // Interrupt Disable Register -#define PMC_SR (104) // Status Register -#define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 1) // (PMC) USB Device Port Clock -#define AT91C_PMC_MCKUDP (0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend -#define AT91C_PMC_UHP (0x1 << 4) // (PMC) USB Host Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK4 (0x1 << 12) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK5 (0x1 << 13) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK6 (0x1 << 14) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK7 (0x1 << 15) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected -#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division -#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same -#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock -#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is three times faster than the master clock -#define AT91C_PMC_MDIV_4 (0x3 << 8) // (PMC) The processor clock is four times faster than the master clock -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask -#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK4RDY (0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK5RDY (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK6RDY (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK7RDY (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -// *** Register offset in AT91S_CKGR structure *** -#define CKGR_MOR ( 0) // Main Oscillator Register -#define CKGR_MCFR ( 4) // Main Clock Frequency Register -#define CKGR_PLLAR ( 8) // PLL A Register -#define CKGR_PLLBR (12) // PLL B Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCTEST (0x1 << 1) // (CKGR) Oscillator Test -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- -#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter -#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range -#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier -#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) PLL A Source -// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter -#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range -#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier -#define AT91C_CKGR_USB_96M (0x1 << 28) // (CKGR) Divider for USB Ports -#define AT91C_CKGR_USB_PLL (0x1 << 29) // (CKGR) PLL Use - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -// *** Register offset in AT91S_PIO structure *** -#define PIO_PER ( 0) // PIO Enable Register -#define PIO_PDR ( 4) // PIO Disable Register -#define PIO_PSR ( 8) // PIO Status Register -#define PIO_OER (16) // Output Enable Register -#define PIO_ODR (20) // Output Disable Registerr -#define PIO_OSR (24) // Output Status Register -#define PIO_IFER (32) // Input Filter Enable Register -#define PIO_IFDR (36) // Input Filter Disable Register -#define PIO_IFSR (40) // Input Filter Status Register -#define PIO_SODR (48) // Set Output Data Register -#define PIO_CODR (52) // Clear Output Data Register -#define PIO_ODSR (56) // Output Data Status Register -#define PIO_PDSR (60) // Pin Data Status Register -#define PIO_IER (64) // Interrupt Enable Register -#define PIO_IDR (68) // Interrupt Disable Register -#define PIO_IMR (72) // Interrupt Mask Register -#define PIO_ISR (76) // Interrupt Status Register -#define PIO_MDER (80) // Multi-driver Enable Register -#define PIO_MDDR (84) // Multi-driver Disable Register -#define PIO_MDSR (88) // Multi-driver Status Register -#define PIO_PPUDR (96) // Pull-up Disable Register -#define PIO_PPUER (100) // Pull-up Enable Register -#define PIO_PPUSR (104) // Pad Pull-up Status Register -#define PIO_ASR (112) // Select A Register -#define PIO_BSR (116) // Select B Register -#define PIO_ABSR (120) // AB Select Status Register -#define PIO_OWER (160) // Output Write Enable Register -#define PIO_OWDR (164) // Output Write Disable Register -#define PIO_OWSR (168) // Output Write Status Register - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -// *** Register offset in AT91S_DBGU structure *** -#define DBGU_CR ( 0) // Control Register -#define DBGU_MR ( 4) // Mode Register -#define DBGU_IER ( 8) // Interrupt Enable Register -#define DBGU_IDR (12) // Interrupt Disable Register -#define DBGU_IMR (16) // Interrupt Mask Register -#define DBGU_CSR (20) // Channel Status Register -#define DBGU_RHR (24) // Receiver Holding Register -#define DBGU_THR (28) // Transmitter Holding Register -#define DBGU_BRGR (32) // Baud Rate Generator Register -#define DBGU_C1R (64) // Chip ID1 Register -#define DBGU_C2R (68) // Chip ID2 Register -#define DBGU_FNTR (72) // Force NTRST Register -#define DBGU_RPR (256) // Receive Pointer Register -#define DBGU_RCR (260) // Receive Counter Register -#define DBGU_TPR (264) // Transmit Pointer Register -#define DBGU_TCR (268) // Transmit Counter Register -#define DBGU_RNPR (272) // Receive Next Pointer Register -#define DBGU_RNCR (276) // Receive Next Counter Register -#define DBGU_TNPR (280) // Transmit Next Pointer Register -#define DBGU_TNCR (284) // Transmit Next Counter Register -#define DBGU_PTCR (288) // PDC Transfer Control Register -#define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral Data Controller -// ***************************************************************************** -// *** Register offset in AT91S_PDC structure *** -#define PDC_RPR ( 0) // Receive Pointer Register -#define PDC_RCR ( 4) // Receive Counter Register -#define PDC_TPR ( 8) // Transmit Pointer Register -#define PDC_TCR (12) // Transmit Counter Register -#define PDC_RNPR (16) // Receive Next Pointer Register -#define PDC_RNCR (20) // Receive Next Counter Register -#define PDC_TNPR (24) // Transmit Next Pointer Register -#define PDC_TNCR (28) // Transmit Next Counter Register -#define PDC_PTCR (32) // PDC Transfer Control Register -#define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -// *** Register offset in AT91S_AIC structure *** -#define AIC_SMR ( 0) // Source Mode Register -#define AIC_SVR (128) // Source Vector Register -#define AIC_IVR (256) // IRQ Vector Register -#define AIC_FVR (260) // FIQ Vector Register -#define AIC_ISR (264) // Interrupt Status Register -#define AIC_IPR (268) // Interrupt Pending Register -#define AIC_IMR (272) // Interrupt Mask Register -#define AIC_CISR (276) // Core Interrupt Status Register -#define AIC_IECR (288) // Interrupt Enable Command Register -#define AIC_IDCR (292) // Interrupt Disable Command Register -#define AIC_ICCR (296) // Interrupt Clear Command Register -#define AIC_ISCR (300) // Interrupt Set Command Register -#define AIC_EOICR (304) // End of Interrupt Command Register -#define AIC_SPU (308) // Spurious Vector Register -#define AIC_DCR (312) // Debug Control Register (Protect) -#define AIC_FFER (320) // Fast Forcing Enable Register -#define AIC_FFDR (324) // Fast Forcing Disable Register -#define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive -#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -// *** Register offset in AT91S_SPI structure *** -#define SPI_CR ( 0) // Control Register -#define SPI_MR ( 4) // Mode Register -#define SPI_RDR ( 8) // Receive Data Register -#define SPI_TDR (12) // Transmit Data Register -#define SPI_SR (16) // Status Register -#define SPI_IER (20) // Interrupt Enable Register -#define SPI_IDR (24) // Interrupt Disable Register -#define SPI_IMR (28) // Interrupt Mask Register -#define SPI_CSR (48) // Chip Select Register -#define SPI_RPR (256) // Receive Pointer Register -#define SPI_RCR (260) // Receive Counter Register -#define SPI_TPR (264) // Transmit Pointer Register -#define SPI_TCR (268) // Transmit Counter Register -#define SPI_RNPR (272) // Receive Next Pointer Register -#define SPI_RNCR (276) // Receive Next Counter Register -#define SPI_TNPR (280) // Transmit Next Pointer Register -#define SPI_TNCR (284) // Transmit Next Counter Register -#define SPI_PTCR (288) // PDC Transfer Control Register -#define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_DIV32 (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_SPENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_SPENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SSC structure *** -#define SSC_CR ( 0) // Control Register -#define SSC_CMR ( 4) // Clock Mode Register -#define SSC_RCMR (16) // Receive Clock ModeRegister -#define SSC_RFMR (20) // Receive Frame Mode Register -#define SSC_TCMR (24) // Transmit Clock Mode Register -#define SSC_TFMR (28) // Transmit Frame Mode Register -#define SSC_RHR (32) // Receive Holding Register -#define SSC_THR (36) // Transmit Holding Register -#define SSC_RSHR (48) // Receive Sync Holding Register -#define SSC_TSHR (52) // Transmit Sync Holding Register -#define SSC_RC0R (56) // Receive Compare 0 Register -#define SSC_RC1R (60) // Receive Compare 1 Register -#define SSC_SR (64) // Status Register -#define SSC_IER (68) // Interrupt Enable Register -#define SSC_IDR (72) // Interrupt Disable Register -#define SSC_IMR (76) // Interrupt Mask Register -#define SSC_RPR (256) // Receive Pointer Register -#define SSC_RCR (260) // Receive Counter Register -#define SSC_TPR (264) // Transmit Pointer Register -#define SSC_TCR (268) // Transmit Counter Register -#define SSC_RNPR (272) // Receive Next Pointer Register -#define SSC_RNCR (276) // Receive Next Counter Register -#define SSC_TNPR (280) // Transmit Next Pointer Register -#define SSC_TNCR (284) // Transmit Next Counter Register -#define SSC_PTCR (288) // PDC Transfer Control Register -#define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -// *** Register offset in AT91S_USART structure *** -#define US_CR ( 0) // Control Register -#define US_MR ( 4) // Mode Register -#define US_IER ( 8) // Interrupt Enable Register -#define US_IDR (12) // Interrupt Disable Register -#define US_IMR (16) // Interrupt Mask Register -#define US_CSR (20) // Channel Status Register -#define US_RHR (24) // Receiver Holding Register -#define US_THR (28) // Transmitter Holding Register -#define US_BRGR (32) // Baud Rate Generator Register -#define US_RTOR (36) // Receiver Time-out Register -#define US_TTGR (40) // Transmitter Time-guard Register -#define US_FIDI (64) // FI_DI_Ratio Register -#define US_NER (68) // Nb Errors Register -#define US_XXR (72) // XON_XOFF Register -#define US_IF (76) // IRDA_FILTER Register -#define US_RPR (256) // Receive Pointer Register -#define US_RCR (260) // Receive Counter Register -#define US_TPR (264) // Transmit Pointer Register -#define US_TCR (268) // Transmit Counter Register -#define US_RNPR (272) // Receive Next Pointer Register -#define US_RNCR (276) // Receive Next Counter Register -#define US_TNPR (280) // Transmit Next Pointer Register -#define US_TNCR (284) // Transmit Next Counter Register -#define US_PTCR (288) // PDC Transfer Control Register -#define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -// *** Register offset in AT91S_TWI structure *** -#define TWI_CR ( 0) // Control Register -#define TWI_MMR ( 4) // Master Mode Register -#define TWI_SMR ( 8) // Slave Mode Register -#define TWI_IADR (12) // Internal Address Register -#define TWI_CWGR (16) // Clock Waveform Generator Register -#define TWI_SR (32) // Status Register -#define TWI_IER (36) // Interrupt Enable Register -#define TWI_IDR (40) // Interrupt Disable Register -#define TWI_IMR (44) // Interrupt Mask Register -#define TWI_RHR (48) // Receive Holding Register -#define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled -#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read -#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access -#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Multimedia Card Interface -// ***************************************************************************** -// *** Register offset in AT91S_MCI structure *** -#define MCI_CR ( 0) // MCI Control Register -#define MCI_MR ( 4) // MCI Mode Register -#define MCI_DTOR ( 8) // MCI Data Timeout Register -#define MCI_SDCR (12) // MCI SD Card Register -#define MCI_ARGR (16) // MCI Argument Register -#define MCI_CMDR (20) // MCI Command Register -#define MCI_RSPR (32) // MCI Response Register -#define MCI_RDR (48) // MCI Receive Data Register -#define MCI_TDR (52) // MCI Transmit Data Register -#define MCI_SR (64) // MCI Status Register -#define MCI_IER (68) // MCI Interrupt Enable Register -#define MCI_IDR (72) // MCI Interrupt Disable Register -#define MCI_IMR (76) // MCI Interrupt Mask Register -#define MCI_RPR (256) // Receive Pointer Register -#define MCI_RCR (260) // Receive Counter Register -#define MCI_TPR (264) // Transmit Pointer Register -#define MCI_TCR (268) // Transmit Counter Register -#define MCI_RNPR (272) // Receive Next Pointer Register -#define MCI_RNCR (276) // Receive Next Counter Register -#define MCI_TNPR (280) // Transmit Next Pointer Register -#define MCI_TNCR (284) // Transmit Next Counter Register -#define MCI_PTCR (288) // PDC Transfer Control Register -#define MCI_PTSR (292) // PDC Transfer Status Register -// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- -#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable -#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable -#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable -#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable -// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- -#define AT91C_MCI_CLKDIV (0x1 << 0) // (MCI) Clock Divider -#define AT91C_MCI_PWSDIV (0x1 << 8) // (MCI) Power Saving Divider -#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value -#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode -#define AT91C_MCI_BLKLEN (0x1 << 18) // (MCI) Data Block Length -// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- -#define AT91C_MCI_DTOCYC (0x1 << 0) // (MCI) Data Timeout Cycle Number -#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier -#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1 -#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16 -#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128 -#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256 -#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024 -#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096 -#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536 -#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576 -// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- -#define AT91C_MCI_SCDSEL (0x1 << 0) // (MCI) SD Card Selector -#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SD Card Bus Width -// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- -#define AT91C_MCI_CMDNB (0x1F << 0) // (MCI) Command Number -#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type -#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response -#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response -#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response -#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD -#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD -#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD -#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD -#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command -#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response -#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command -#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond -#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD -#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer -#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer -#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer -#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction -#define AT91C_MCI_TRTYP (0x3 << 19) // (MCI) Transfer Type -#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) Block Transfer type -#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) Multiple Block transfer type -#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) Stream transfer type -// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- -#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag -#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag -#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag -#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag -#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag -#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag -#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag -#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag -#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag -#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag -#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag -#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag -#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag -#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag -#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag -#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag -#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag -#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag -#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag -// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- -// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- -// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -// *** Register offset in AT91S_UDP structure *** -#define UDP_NUM ( 0) // Frame Number Register -#define UDP_GLBSTATE ( 4) // Global State Register -#define UDP_FADDR ( 8) // Function Address Register -#define UDP_IER (16) // Interrupt Enable Register -#define UDP_IDR (20) // Interrupt Disable Register -#define UDP_IMR (24) // Interrupt Mask Register -#define UDP_ISR (28) // Interrupt Status Register -#define UDP_ICR (32) // Interrupt Clear Register -#define UDP_RSTEP (40) // Reset Endpoint Register -#define UDP_CSR (48) // Endpoint Control and Status Register -#define UDP_FDR (80) // Endpoint FIFO Data Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt -#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 -#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_TC structure *** -#define TC_CCR ( 0) // Channel Control Register -#define TC_CMR ( 4) // Channel Mode Register -#define TC_CV (16) // Counter Value -#define TC_RA (20) // Register A -#define TC_RB (24) // Register B -#define TC_RC (28) // Register C -#define TC_SR (32) // Status Register -#define TC_IER (36) // Interrupt Enable Register -#define TC_IDR (40) // Interrupt Disable Register -#define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -// *** Register offset in AT91S_TCB structure *** -#define TCB_TC0 ( 0) // TC Channel 0 -#define TCB_TC1 (64) // TC Channel 1 -#define TCB_TC2 (128) // TC Channel 2 -#define TCB_BCR (192) // TC Block Control Register -#define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Host Interface -// ***************************************************************************** -// *** Register offset in AT91S_UHP structure *** -#define UHP_HcRevision ( 0) // Revision -#define UHP_HcControl ( 4) // Operating modes for the Host Controller -#define UHP_HcCommandStatus ( 8) // Command & status Register -#define UHP_HcInterruptStatus (12) // Interrupt Status Register -#define UHP_HcInterruptEnable (16) // Interrupt Enable Register -#define UHP_HcInterruptDisable (20) // Interrupt Disable Register -#define UHP_HcHCCA (24) // Pointer to the Host Controller Communication Area -#define UHP_HcPeriodCurrentED (28) // Current Isochronous or Interrupt Endpoint Descriptor -#define UHP_HcControlHeadED (32) // First Endpoint Descriptor of the Control list -#define UHP_HcControlCurrentED (36) // Endpoint Control and Status Register -#define UHP_HcBulkHeadED (40) // First endpoint register of the Bulk list -#define UHP_HcBulkCurrentED (44) // Current endpoint of the Bulk list -#define UHP_HcBulkDoneHead (48) // Last completed transfer descriptor -#define UHP_HcFmInterval (52) // Bit time between 2 consecutive SOFs -#define UHP_HcFmRemaining (56) // Bit time remaining in the current Frame -#define UHP_HcFmNumber (60) // Frame number -#define UHP_HcPeriodicStart (64) // Periodic Start -#define UHP_HcLSThreshold (68) // LS Threshold -#define UHP_HcRhDescriptorA (72) // Root Hub characteristics A -#define UHP_HcRhDescriptorB (76) // Root Hub characteristics B -#define UHP_HcRhStatus (80) // Root Hub Status register -#define UHP_HcRhPortStatus (84) // Root Hub Port Status Register - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC -// ***************************************************************************** -// *** Register offset in AT91S_EMAC structure *** -#define EMAC_CTL ( 0) // Network Control Register -#define EMAC_CFG ( 4) // Network Configuration Register -#define EMAC_SR ( 8) // Network Status Register -#define EMAC_TAR (12) // Transmit Address Register -#define EMAC_TCR (16) // Transmit Control Register -#define EMAC_TSR (20) // Transmit Status Register -#define EMAC_RBQP (24) // Receive Buffer Queue Pointer -#define EMAC_RSR (32) // Receive Status Register -#define EMAC_ISR (36) // Interrupt Status Register -#define EMAC_IER (40) // Interrupt Enable Register -#define EMAC_IDR (44) // Interrupt Disable Register -#define EMAC_IMR (48) // Interrupt Mask Register -#define EMAC_MAN (52) // PHY Maintenance Register -#define EMAC_FRA (64) // Frames Transmitted OK Register -#define EMAC_SCOL (68) // Single Collision Frame Register -#define EMAC_MCOL (72) // Multiple Collision Frame Register -#define EMAC_OK (76) // Frames Received OK Register -#define EMAC_SEQE (80) // Frame Check Sequence Error Register -#define EMAC_ALE (84) // Alignment Error Register -#define EMAC_DTE (88) // Deferred Transmission Frame Register -#define EMAC_LCOL (92) // Late Collision Register -#define EMAC_ECOL (96) // Excessive Collision Register -#define EMAC_CSE (100) // Carrier Sense Error Register -#define EMAC_TUE (104) // Transmit Underrun Error Register -#define EMAC_CDE (108) // Code Error Register -#define EMAC_ELR (112) // Excessive Length Error Register -#define EMAC_RJB (116) // Receive Jabber Register -#define EMAC_USF (120) // Undersize Frame Register -#define EMAC_SQEE (124) // SQE Test Error Register -#define EMAC_DRFC (128) // Discarded RX Frame Register -#define EMAC_HSH (144) // Hash Address High[63:32] -#define EMAC_HSL (148) // Hash Address Low[31:0] -#define EMAC_SA1L (152) // Specific Address 1 Low, First 4 bytes -#define EMAC_SA1H (156) // Specific Address 1 High, Last 2 bytes -#define EMAC_SA2L (160) // Specific Address 2 Low, First 4 bytes -#define EMAC_SA2H (164) // Specific Address 2 High, Last 2 bytes -#define EMAC_SA3L (168) // Specific Address 3 Low, First 4 bytes -#define EMAC_SA3H (172) // Specific Address 3 High, Last 2 bytes -#define EMAC_SA4L (176) // Specific Address 4 Low, First 4 bytes -#define EMAC_SA4H (180) // Specific Address 4 High, Last 2 bytesr -// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LBL (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CSR (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_ISR (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WES (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_BR (0x1 << 2) // (EMAC) Bit rate. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_RMII (0x1 << 13) // (EMAC) -// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- -#define AT91C_EMAC_LEN (0x7FF << 0) // (EMAC) -#define AT91C_EMAC_NCRC (0x1 << 15) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- -#define AT91C_EMAC_OVR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLE (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXIDLE (0x1 << 3) // (EMAC) -#define AT91C_EMAC_BNQ (0x1 << 4) // (EMAC) -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_DONE (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOM (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RBNA (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TOVR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUND (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RTRY (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TBRE (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOM (0x1 << 7) // (EMAC) -#define AT91C_EMAC_TIDLE (0x1 << 8) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_HIGH (0x1 << 30) // (EMAC) -#define AT91C_EMAC_LOW (0x1 << 31) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR External Bus Interface -// ***************************************************************************** -// *** Register offset in AT91S_EBI structure *** -#define EBI_CSA ( 0) // Chip Select Assignment Register -#define EBI_CFGR ( 4) // Configuration Register -// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- -#define AT91C_EBI_CS0A (0x1 << 0) // (EBI) Chip Select 0 Assignment -#define AT91C_EBI_CS0A_SMC (0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller. -#define AT91C_EBI_CS0A_BFC (0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. -#define AT91C_EBI_CS1A (0x1 << 1) // (EBI) Chip Select 1 Assignment -#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. -#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. -#define AT91C_EBI_CS3A (0x1 << 3) // (EBI) Chip Select 3 Assignment -#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. -#define AT91C_EBI_CS3A_SMC_SmartMedia (0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. -#define AT91C_EBI_CS4A (0x1 << 4) // (EBI) Chip Select 4 Assignment -#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. -#define AT91C_EBI_CS4A_SMC_CompactFlash (0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. -// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- -#define AT91C_EBI_DBPUC (0x1 << 0) // (EBI) Data Bus Pull-Up Configuration -#define AT91C_EBI_EBSEN (0x1 << 1) // (EBI) Bus Sharing Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface -// ***************************************************************************** -// *** Register offset in AT91S_SMC2 structure *** -#define SMC2_CSR ( 0) // SMC2 Chip Select Register -// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- -#define AT91C_SMC2_NWS (0x7F << 0) // (SMC2) Number of Wait States -#define AT91C_SMC2_WSEN (0x1 << 7) // (SMC2) Wait State Enable -#define AT91C_SMC2_TDF (0xF << 8) // (SMC2) Data Float Time -#define AT91C_SMC2_BAT (0x1 << 12) // (SMC2) Byte Access Type -#define AT91C_SMC2_DBW (0x1 << 13) // (SMC2) Data Bus Width -#define AT91C_SMC2_DBW_16 (0x1 << 13) // (SMC2) 16-bit. -#define AT91C_SMC2_DBW_8 (0x2 << 13) // (SMC2) 8-bit. -#define AT91C_SMC2_DRP (0x1 << 15) // (SMC2) Data Read Protocol -#define AT91C_SMC2_ACSS (0x3 << 16) // (SMC2) Address to Chip Select Setup -#define AT91C_SMC2_ACSS_STANDARD (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. -#define AT91C_SMC2_ACSS_1_CYCLE (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access. -#define AT91C_SMC2_ACSS_2_CYCLES (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access. -#define AT91C_SMC2_ACSS_3_CYCLES (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access. -#define AT91C_SMC2_RWSETUP (0x7 << 24) // (SMC2) Read and Write Signal Setup Time -#define AT91C_SMC2_RWHOLD (0x7 << 29) // (SMC2) Read and Write Signal Hold Time - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR SDRAM Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SDRC structure *** -#define SDRC_MR ( 0) // SDRAM Controller Mode Register -#define SDRC_TR ( 4) // SDRAM Controller Refresh Timer Register -#define SDRC_CR ( 8) // SDRAM Controller Configuration Register -#define SDRC_SRR (12) // SDRAM Controller Self Refresh Register -#define SDRC_LPR (16) // SDRAM Controller Low Power Register -#define SDRC_IER (20) // SDRAM Controller Interrupt Enable Register -#define SDRC_IDR (24) // SDRAM Controller Interrupt Disable Register -#define SDRC_IMR (28) // SDRAM Controller Interrupt Mask Register -#define SDRC_ISR (32) // SDRAM Controller Interrupt Mask Register -// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- -#define AT91C_SDRC_MODE (0xF << 0) // (SDRC) Mode -#define AT91C_SDRC_MODE_NORMAL_CMD (0x0) // (SDRC) Normal Mode -#define AT91C_SDRC_MODE_NOP_CMD (0x1) // (SDRC) NOP Command -#define AT91C_SDRC_MODE_PRCGALL_CMD (0x2) // (SDRC) All Banks Precharge Command -#define AT91C_SDRC_MODE_LMR_CMD (0x3) // (SDRC) Load Mode Register Command -#define AT91C_SDRC_MODE_RFSH_CMD (0x4) // (SDRC) Refresh Command -#define AT91C_SDRC_DBW (0x1 << 4) // (SDRC) Data Bus Width -#define AT91C_SDRC_DBW_32_BITS (0x0 << 4) // (SDRC) 32 Bits datas bus -#define AT91C_SDRC_DBW_16_BITS (0x1 << 4) // (SDRC) 16 Bits datas bus -// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- -#define AT91C_SDRC_COUNT (0xFFF << 0) // (SDRC) Refresh Counter -// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- -#define AT91C_SDRC_NC (0x3 << 0) // (SDRC) Number of Column Bits -#define AT91C_SDRC_NC_8 (0x0) // (SDRC) 8 Bits -#define AT91C_SDRC_NC_9 (0x1) // (SDRC) 9 Bits -#define AT91C_SDRC_NC_10 (0x2) // (SDRC) 10 Bits -#define AT91C_SDRC_NC_11 (0x3) // (SDRC) 11 Bits -#define AT91C_SDRC_NR (0x3 << 2) // (SDRC) Number of Row Bits -#define AT91C_SDRC_NR_11 (0x0 << 2) // (SDRC) 11 Bits -#define AT91C_SDRC_NR_12 (0x1 << 2) // (SDRC) 12 Bits -#define AT91C_SDRC_NR_13 (0x2 << 2) // (SDRC) 13 Bits -#define AT91C_SDRC_NB (0x1 << 4) // (SDRC) Number of Banks -#define AT91C_SDRC_NB_2_BANKS (0x0 << 4) // (SDRC) 2 banks -#define AT91C_SDRC_NB_4_BANKS (0x1 << 4) // (SDRC) 4 banks -#define AT91C_SDRC_CAS (0x3 << 5) // (SDRC) CAS Latency -#define AT91C_SDRC_CAS_2 (0x2 << 5) // (SDRC) 2 cycles -#define AT91C_SDRC_TWR (0xF << 7) // (SDRC) Number of Write Recovery Time Cycles -#define AT91C_SDRC_TRC (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles -#define AT91C_SDRC_TRP (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles -#define AT91C_SDRC_TRCD (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles -#define AT91C_SDRC_TRAS (0xF << 23) // (SDRC) Number of RAS Active Time Cycles -#define AT91C_SDRC_TXSR (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles -// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- -#define AT91C_SDRC_SRCB (0x1 << 0) // (SDRC) Self-refresh Command Bit -// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- -#define AT91C_SDRC_LPCB (0x1 << 0) // (SDRC) Low-power Command Bit -// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- -#define AT91C_SDRC_RES (0x1 << 0) // (SDRC) Refresh Error Status -// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- -// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- -// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Burst Flash Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_BFC structure *** -#define BFC_MR ( 0) // BFC Mode Register -// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- -#define AT91C_BFC_BFCOM (0x3 << 0) // (BFC) Burst Flash Controller Operating Mode -#define AT91C_BFC_BFCOM_DISABLED (0x0) // (BFC) NPCS0 is driven by the SMC or remains high. -#define AT91C_BFC_BFCOM_ASYNC (0x1) // (BFC) Asynchronous -#define AT91C_BFC_BFCOM_BURST_READ (0x2) // (BFC) Burst Read -#define AT91C_BFC_BFCC (0x3 << 2) // (BFC) Burst Flash Controller Operating Mode -#define AT91C_BFC_BFCC_MCK (0x1 << 2) // (BFC) Master Clock. -#define AT91C_BFC_BFCC_MCK_DIV_2 (0x2 << 2) // (BFC) Master Clock divided by 2. -#define AT91C_BFC_BFCC_MCK_DIV_4 (0x3 << 2) // (BFC) Master Clock divided by 4. -#define AT91C_BFC_AVL (0xF << 4) // (BFC) Address Valid Latency -#define AT91C_BFC_PAGES (0x7 << 8) // (BFC) Page Size -#define AT91C_BFC_PAGES_NO_PAGE (0x0 << 8) // (BFC) No page handling. -#define AT91C_BFC_PAGES_16 (0x1 << 8) // (BFC) 16 bytes page size. -#define AT91C_BFC_PAGES_32 (0x2 << 8) // (BFC) 32 bytes page size. -#define AT91C_BFC_PAGES_64 (0x3 << 8) // (BFC) 64 bytes page size. -#define AT91C_BFC_PAGES_128 (0x4 << 8) // (BFC) 128 bytes page size. -#define AT91C_BFC_PAGES_256 (0x5 << 8) // (BFC) 256 bytes page size. -#define AT91C_BFC_PAGES_512 (0x6 << 8) // (BFC) 512 bytes page size. -#define AT91C_BFC_PAGES_1024 (0x7 << 8) // (BFC) 1024 bytes page size. -#define AT91C_BFC_OEL (0x3 << 12) // (BFC) Output Enable Latency -#define AT91C_BFC_BAAEN (0x1 << 16) // (BFC) Burst Address Advance Enable -#define AT91C_BFC_BFOEH (0x1 << 17) // (BFC) Burst Flash Output Enable Handling -#define AT91C_BFC_MUXEN (0x1 << 18) // (BFC) Multiplexed Bus Enable -#define AT91C_BFC_RDYEN (0x1 << 19) // (BFC) Ready Enable Mode - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91RM9200 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_PUER (0xFFFFFF54) // (MC) MC Protection Unit Enable Register -#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_PUP (0xFFFFFF50) // (MC) MC Protection Unit Peripherals -#define AT91C_MC_PUIA (0xFFFFFF10) // (MC) MC Protection Unit Area -#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for RTC peripheral ========== -#define AT91C_RTC_IMR (0xFFFFFE28) // (RTC) Interrupt Mask Register -#define AT91C_RTC_IER (0xFFFFFE20) // (RTC) Interrupt Enable Register -#define AT91C_RTC_SR (0xFFFFFE18) // (RTC) Status Register -#define AT91C_RTC_TIMALR (0xFFFFFE10) // (RTC) Time Alarm Register -#define AT91C_RTC_TIMR (0xFFFFFE08) // (RTC) Time Register -#define AT91C_RTC_CR (0xFFFFFE00) // (RTC) Control Register -#define AT91C_RTC_VER (0xFFFFFE2C) // (RTC) Valid Entry Register -#define AT91C_RTC_IDR (0xFFFFFE24) // (RTC) Interrupt Disable Register -#define AT91C_RTC_SCCR (0xFFFFFE1C) // (RTC) Status Clear Command Register -#define AT91C_RTC_CALALR (0xFFFFFE14) // (RTC) Calendar Alarm Register -#define AT91C_RTC_CALR (0xFFFFFE0C) // (RTC) Calendar Register -#define AT91C_RTC_MR (0xFFFFFE04) // (RTC) Mode Register -// ========== Register definition for ST peripheral ========== -#define AT91C_ST_CRTR (0xFFFFFD24) // (ST) Current Real-time Register -#define AT91C_ST_IMR (0xFFFFFD1C) // (ST) Interrupt Mask Register -#define AT91C_ST_IER (0xFFFFFD14) // (ST) Interrupt Enable Register -#define AT91C_ST_RTMR (0xFFFFFD0C) // (ST) Real-time Mode Register -#define AT91C_ST_PIMR (0xFFFFFD04) // (ST) Period Interval Mode Register -#define AT91C_ST_RTAR (0xFFFFFD20) // (ST) Real-time Alarm Register -#define AT91C_ST_IDR (0xFFFFFD18) // (ST) Interrupt Disable Register -#define AT91C_ST_SR (0xFFFFFD10) // (ST) Status Register -#define AT91C_ST_WDMR (0xFFFFFD08) // (ST) Watchdog Mode Register -#define AT91C_ST_CR (0xFFFFFD00) // (ST) Control Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLBR (0xFFFFFC2C) // (CKGR) PLL B Register -#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_PLLAR (0xFFFFFC28) // (CKGR) PLL A Register -#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PIOD peripheral ========== -#define AT91C_PIOD_PDSR (0xFFFFFA3C) // (PIOD) Pin Data Status Register -#define AT91C_PIOD_CODR (0xFFFFFA34) // (PIOD) Clear Output Data Register -#define AT91C_PIOD_OWER (0xFFFFFAA0) // (PIOD) Output Write Enable Register -#define AT91C_PIOD_MDER (0xFFFFFA50) // (PIOD) Multi-driver Enable Register -#define AT91C_PIOD_IMR (0xFFFFFA48) // (PIOD) Interrupt Mask Register -#define AT91C_PIOD_IER (0xFFFFFA40) // (PIOD) Interrupt Enable Register -#define AT91C_PIOD_ODSR (0xFFFFFA38) // (PIOD) Output Data Status Register -#define AT91C_PIOD_SODR (0xFFFFFA30) // (PIOD) Set Output Data Register -#define AT91C_PIOD_PER (0xFFFFFA00) // (PIOD) PIO Enable Register -#define AT91C_PIOD_OWDR (0xFFFFFAA4) // (PIOD) Output Write Disable Register -#define AT91C_PIOD_PPUER (0xFFFFFA64) // (PIOD) Pull-up Enable Register -#define AT91C_PIOD_MDDR (0xFFFFFA54) // (PIOD) Multi-driver Disable Register -#define AT91C_PIOD_ISR (0xFFFFFA4C) // (PIOD) Interrupt Status Register -#define AT91C_PIOD_IDR (0xFFFFFA44) // (PIOD) Interrupt Disable Register -#define AT91C_PIOD_PDR (0xFFFFFA04) // (PIOD) PIO Disable Register -#define AT91C_PIOD_ODR (0xFFFFFA14) // (PIOD) Output Disable Registerr -#define AT91C_PIOD_OWSR (0xFFFFFAA8) // (PIOD) Output Write Status Register -#define AT91C_PIOD_ABSR (0xFFFFFA78) // (PIOD) AB Select Status Register -#define AT91C_PIOD_ASR (0xFFFFFA70) // (PIOD) Select A Register -#define AT91C_PIOD_PPUSR (0xFFFFFA68) // (PIOD) Pad Pull-up Status Register -#define AT91C_PIOD_PPUDR (0xFFFFFA60) // (PIOD) Pull-up Disable Register -#define AT91C_PIOD_MDSR (0xFFFFFA58) // (PIOD) Multi-driver Status Register -#define AT91C_PIOD_PSR (0xFFFFFA08) // (PIOD) PIO Status Register -#define AT91C_PIOD_OER (0xFFFFFA10) // (PIOD) Output Enable Register -#define AT91C_PIOD_OSR (0xFFFFFA18) // (PIOD) Output Status Register -#define AT91C_PIOD_IFER (0xFFFFFA20) // (PIOD) Input Filter Enable Register -#define AT91C_PIOD_BSR (0xFFFFFA74) // (PIOD) Select B Register -#define AT91C_PIOD_IFDR (0xFFFFFA24) // (PIOD) Input Filter Disable Register -#define AT91C_PIOD_IFSR (0xFFFFFA28) // (PIOD) Input Filter Status Register -// ========== Register definition for PIOC peripheral ========== -#define AT91C_PIOC_IFDR (0xFFFFF824) // (PIOC) Input Filter Disable Register -#define AT91C_PIOC_ODR (0xFFFFF814) // (PIOC) Output Disable Registerr -#define AT91C_PIOC_ABSR (0xFFFFF878) // (PIOC) AB Select Status Register -#define AT91C_PIOC_SODR (0xFFFFF830) // (PIOC) Set Output Data Register -#define AT91C_PIOC_IFSR (0xFFFFF828) // (PIOC) Input Filter Status Register -#define AT91C_PIOC_CODR (0xFFFFF834) // (PIOC) Clear Output Data Register -#define AT91C_PIOC_ODSR (0xFFFFF838) // (PIOC) Output Data Status Register -#define AT91C_PIOC_IER (0xFFFFF840) // (PIOC) Interrupt Enable Register -#define AT91C_PIOC_IMR (0xFFFFF848) // (PIOC) Interrupt Mask Register -#define AT91C_PIOC_OWDR (0xFFFFF8A4) // (PIOC) Output Write Disable Register -#define AT91C_PIOC_MDDR (0xFFFFF854) // (PIOC) Multi-driver Disable Register -#define AT91C_PIOC_PDSR (0xFFFFF83C) // (PIOC) Pin Data Status Register -#define AT91C_PIOC_IDR (0xFFFFF844) // (PIOC) Interrupt Disable Register -#define AT91C_PIOC_ISR (0xFFFFF84C) // (PIOC) Interrupt Status Register -#define AT91C_PIOC_PDR (0xFFFFF804) // (PIOC) PIO Disable Register -#define AT91C_PIOC_OWSR (0xFFFFF8A8) // (PIOC) Output Write Status Register -#define AT91C_PIOC_OWER (0xFFFFF8A0) // (PIOC) Output Write Enable Register -#define AT91C_PIOC_ASR (0xFFFFF870) // (PIOC) Select A Register -#define AT91C_PIOC_PPUSR (0xFFFFF868) // (PIOC) Pad Pull-up Status Register -#define AT91C_PIOC_PPUDR (0xFFFFF860) // (PIOC) Pull-up Disable Register -#define AT91C_PIOC_MDSR (0xFFFFF858) // (PIOC) Multi-driver Status Register -#define AT91C_PIOC_MDER (0xFFFFF850) // (PIOC) Multi-driver Enable Register -#define AT91C_PIOC_IFER (0xFFFFF820) // (PIOC) Input Filter Enable Register -#define AT91C_PIOC_OSR (0xFFFFF818) // (PIOC) Output Status Register -#define AT91C_PIOC_OER (0xFFFFF810) // (PIOC) Output Enable Register -#define AT91C_PIOC_PSR (0xFFFFF808) // (PIOC) PIO Status Register -#define AT91C_PIOC_PER (0xFFFFF800) // (PIOC) PIO Enable Register -#define AT91C_PIOC_BSR (0xFFFFF874) // (PIOC) Select B Register -#define AT91C_PIOC_PPUER (0xFFFFF864) // (PIOC) Pull-up Enable Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pad Pull-up Status Register -#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register -#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register -#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register -#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register -#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_SSC2 peripheral ========== -#define AT91C_SSC2_PTCR (0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register -#define AT91C_SSC2_TNPR (0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register -#define AT91C_SSC2_RNPR (0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register -#define AT91C_SSC2_TPR (0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register -#define AT91C_SSC2_RPR (0xFFFD8100) // (PDC_SSC2) Receive Pointer Register -#define AT91C_SSC2_PTSR (0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register -#define AT91C_SSC2_TNCR (0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register -#define AT91C_SSC2_RNCR (0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register -#define AT91C_SSC2_TCR (0xFFFD810C) // (PDC_SSC2) Transmit Counter Register -#define AT91C_SSC2_RCR (0xFFFD8104) // (PDC_SSC2) Receive Counter Register -// ========== Register definition for SSC2 peripheral ========== -#define AT91C_SSC2_IMR (0xFFFD804C) // (SSC2) Interrupt Mask Register -#define AT91C_SSC2_IER (0xFFFD8044) // (SSC2) Interrupt Enable Register -#define AT91C_SSC2_RC1R (0xFFFD803C) // (SSC2) Receive Compare 1 Register -#define AT91C_SSC2_TSHR (0xFFFD8034) // (SSC2) Transmit Sync Holding Register -#define AT91C_SSC2_CMR (0xFFFD8004) // (SSC2) Clock Mode Register -#define AT91C_SSC2_IDR (0xFFFD8048) // (SSC2) Interrupt Disable Register -#define AT91C_SSC2_TCMR (0xFFFD8018) // (SSC2) Transmit Clock Mode Register -#define AT91C_SSC2_RCMR (0xFFFD8010) // (SSC2) Receive Clock ModeRegister -#define AT91C_SSC2_CR (0xFFFD8000) // (SSC2) Control Register -#define AT91C_SSC2_RFMR (0xFFFD8014) // (SSC2) Receive Frame Mode Register -#define AT91C_SSC2_TFMR (0xFFFD801C) // (SSC2) Transmit Frame Mode Register -#define AT91C_SSC2_THR (0xFFFD8024) // (SSC2) Transmit Holding Register -#define AT91C_SSC2_SR (0xFFFD8040) // (SSC2) Status Register -#define AT91C_SSC2_RC0R (0xFFFD8038) // (SSC2) Receive Compare 0 Register -#define AT91C_SSC2_RSHR (0xFFFD8030) // (SSC2) Receive Sync Holding Register -#define AT91C_SSC2_RHR (0xFFFD8020) // (SSC2) Receive Holding Register -// ========== Register definition for PDC_SSC1 peripheral ========== -#define AT91C_SSC1_PTCR (0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register -#define AT91C_SSC1_TNPR (0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register -#define AT91C_SSC1_RNPR (0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register -#define AT91C_SSC1_TPR (0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register -#define AT91C_SSC1_RPR (0xFFFD4100) // (PDC_SSC1) Receive Pointer Register -#define AT91C_SSC1_PTSR (0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register -#define AT91C_SSC1_TNCR (0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register -#define AT91C_SSC1_RNCR (0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register -#define AT91C_SSC1_TCR (0xFFFD410C) // (PDC_SSC1) Transmit Counter Register -#define AT91C_SSC1_RCR (0xFFFD4104) // (PDC_SSC1) Receive Counter Register -// ========== Register definition for SSC1 peripheral ========== -#define AT91C_SSC1_RFMR (0xFFFD4014) // (SSC1) Receive Frame Mode Register -#define AT91C_SSC1_CMR (0xFFFD4004) // (SSC1) Clock Mode Register -#define AT91C_SSC1_IDR (0xFFFD4048) // (SSC1) Interrupt Disable Register -#define AT91C_SSC1_SR (0xFFFD4040) // (SSC1) Status Register -#define AT91C_SSC1_RC0R (0xFFFD4038) // (SSC1) Receive Compare 0 Register -#define AT91C_SSC1_RSHR (0xFFFD4030) // (SSC1) Receive Sync Holding Register -#define AT91C_SSC1_RHR (0xFFFD4020) // (SSC1) Receive Holding Register -#define AT91C_SSC1_TCMR (0xFFFD4018) // (SSC1) Transmit Clock Mode Register -#define AT91C_SSC1_RCMR (0xFFFD4010) // (SSC1) Receive Clock ModeRegister -#define AT91C_SSC1_CR (0xFFFD4000) // (SSC1) Control Register -#define AT91C_SSC1_IMR (0xFFFD404C) // (SSC1) Interrupt Mask Register -#define AT91C_SSC1_IER (0xFFFD4044) // (SSC1) Interrupt Enable Register -#define AT91C_SSC1_RC1R (0xFFFD403C) // (SSC1) Receive Compare 1 Register -#define AT91C_SSC1_TSHR (0xFFFD4034) // (SSC1) Transmit Sync Holding Register -#define AT91C_SSC1_THR (0xFFFD4024) // (SSC1) Transmit Holding Register -#define AT91C_SSC1_TFMR (0xFFFD401C) // (SSC1) Transmit Frame Mode Register -// ========== Register definition for PDC_SSC0 peripheral ========== -#define AT91C_SSC0_PTCR (0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register -#define AT91C_SSC0_TNPR (0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register -#define AT91C_SSC0_RNPR (0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register -#define AT91C_SSC0_TPR (0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register -#define AT91C_SSC0_RPR (0xFFFD0100) // (PDC_SSC0) Receive Pointer Register -#define AT91C_SSC0_PTSR (0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register -#define AT91C_SSC0_TNCR (0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register -#define AT91C_SSC0_RNCR (0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register -#define AT91C_SSC0_TCR (0xFFFD010C) // (PDC_SSC0) Transmit Counter Register -#define AT91C_SSC0_RCR (0xFFFD0104) // (PDC_SSC0) Receive Counter Register -// ========== Register definition for SSC0 peripheral ========== -#define AT91C_SSC0_IMR (0xFFFD004C) // (SSC0) Interrupt Mask Register -#define AT91C_SSC0_IER (0xFFFD0044) // (SSC0) Interrupt Enable Register -#define AT91C_SSC0_RC1R (0xFFFD003C) // (SSC0) Receive Compare 1 Register -#define AT91C_SSC0_TSHR (0xFFFD0034) // (SSC0) Transmit Sync Holding Register -#define AT91C_SSC0_THR (0xFFFD0024) // (SSC0) Transmit Holding Register -#define AT91C_SSC0_TFMR (0xFFFD001C) // (SSC0) Transmit Frame Mode Register -#define AT91C_SSC0_RFMR (0xFFFD0014) // (SSC0) Receive Frame Mode Register -#define AT91C_SSC0_CMR (0xFFFD0004) // (SSC0) Clock Mode Register -#define AT91C_SSC0_IDR (0xFFFD0048) // (SSC0) Interrupt Disable Register -#define AT91C_SSC0_SR (0xFFFD0040) // (SSC0) Status Register -#define AT91C_SSC0_RC0R (0xFFFD0038) // (SSC0) Receive Compare 0 Register -#define AT91C_SSC0_RSHR (0xFFFD0030) // (SSC0) Receive Sync Holding Register -#define AT91C_SSC0_RHR (0xFFFD0020) // (SSC0) Receive Holding Register -#define AT91C_SSC0_TCMR (0xFFFD0018) // (SSC0) Transmit Clock Mode Register -#define AT91C_SSC0_RCMR (0xFFFD0010) // (SSC0) Receive Clock ModeRegister -#define AT91C_SSC0_CR (0xFFFD0000) // (SSC0) Control Register -// ========== Register definition for PDC_US3 peripheral ========== -#define AT91C_US3_PTSR (0xFFFCC124) // (PDC_US3) PDC Transfer Status Register -#define AT91C_US3_TNCR (0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register -#define AT91C_US3_RNCR (0xFFFCC114) // (PDC_US3) Receive Next Counter Register -#define AT91C_US3_TCR (0xFFFCC10C) // (PDC_US3) Transmit Counter Register -#define AT91C_US3_RCR (0xFFFCC104) // (PDC_US3) Receive Counter Register -#define AT91C_US3_PTCR (0xFFFCC120) // (PDC_US3) PDC Transfer Control Register -#define AT91C_US3_TNPR (0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register -#define AT91C_US3_RNPR (0xFFFCC110) // (PDC_US3) Receive Next Pointer Register -#define AT91C_US3_TPR (0xFFFCC108) // (PDC_US3) Transmit Pointer Register -#define AT91C_US3_RPR (0xFFFCC100) // (PDC_US3) Receive Pointer Register -// ========== Register definition for US3 peripheral ========== -#define AT91C_US3_IF (0xFFFCC04C) // (US3) IRDA_FILTER Register -#define AT91C_US3_NER (0xFFFCC044) // (US3) Nb Errors Register -#define AT91C_US3_RTOR (0xFFFCC024) // (US3) Receiver Time-out Register -#define AT91C_US3_THR (0xFFFCC01C) // (US3) Transmitter Holding Register -#define AT91C_US3_CSR (0xFFFCC014) // (US3) Channel Status Register -#define AT91C_US3_IDR (0xFFFCC00C) // (US3) Interrupt Disable Register -#define AT91C_US3_MR (0xFFFCC004) // (US3) Mode Register -#define AT91C_US3_XXR (0xFFFCC048) // (US3) XON_XOFF Register -#define AT91C_US3_FIDI (0xFFFCC040) // (US3) FI_DI_Ratio Register -#define AT91C_US3_TTGR (0xFFFCC028) // (US3) Transmitter Time-guard Register -#define AT91C_US3_BRGR (0xFFFCC020) // (US3) Baud Rate Generator Register -#define AT91C_US3_RHR (0xFFFCC018) // (US3) Receiver Holding Register -#define AT91C_US3_IMR (0xFFFCC010) // (US3) Interrupt Mask Register -#define AT91C_US3_IER (0xFFFCC008) // (US3) Interrupt Enable Register -#define AT91C_US3_CR (0xFFFCC000) // (US3) Control Register -// ========== Register definition for PDC_US2 peripheral ========== -#define AT91C_US2_PTSR (0xFFFC8124) // (PDC_US2) PDC Transfer Status Register -#define AT91C_US2_TNCR (0xFFFC811C) // (PDC_US2) Transmit Next Counter Register -#define AT91C_US2_RNCR (0xFFFC8114) // (PDC_US2) Receive Next Counter Register -#define AT91C_US2_TCR (0xFFFC810C) // (PDC_US2) Transmit Counter Register -#define AT91C_US2_PTCR (0xFFFC8120) // (PDC_US2) PDC Transfer Control Register -#define AT91C_US2_RCR (0xFFFC8104) // (PDC_US2) Receive Counter Register -#define AT91C_US2_TNPR (0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register -#define AT91C_US2_RPR (0xFFFC8100) // (PDC_US2) Receive Pointer Register -#define AT91C_US2_TPR (0xFFFC8108) // (PDC_US2) Transmit Pointer Register -#define AT91C_US2_RNPR (0xFFFC8110) // (PDC_US2) Receive Next Pointer Register -// ========== Register definition for US2 peripheral ========== -#define AT91C_US2_XXR (0xFFFC8048) // (US2) XON_XOFF Register -#define AT91C_US2_FIDI (0xFFFC8040) // (US2) FI_DI_Ratio Register -#define AT91C_US2_TTGR (0xFFFC8028) // (US2) Transmitter Time-guard Register -#define AT91C_US2_BRGR (0xFFFC8020) // (US2) Baud Rate Generator Register -#define AT91C_US2_RHR (0xFFFC8018) // (US2) Receiver Holding Register -#define AT91C_US2_IMR (0xFFFC8010) // (US2) Interrupt Mask Register -#define AT91C_US2_IER (0xFFFC8008) // (US2) Interrupt Enable Register -#define AT91C_US2_CR (0xFFFC8000) // (US2) Control Register -#define AT91C_US2_IF (0xFFFC804C) // (US2) IRDA_FILTER Register -#define AT91C_US2_NER (0xFFFC8044) // (US2) Nb Errors Register -#define AT91C_US2_RTOR (0xFFFC8024) // (US2) Receiver Time-out Register -#define AT91C_US2_THR (0xFFFC801C) // (US2) Transmitter Holding Register -#define AT91C_US2_CSR (0xFFFC8014) // (US2) Channel Status Register -#define AT91C_US2_IDR (0xFFFC800C) // (US2) Interrupt Disable Register -#define AT91C_US2_MR (0xFFFC8004) // (US2) Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register -#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register -#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register -#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for PDC_MCI peripheral ========== -#define AT91C_MCI_PTCR (0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register -#define AT91C_MCI_TNPR (0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register -#define AT91C_MCI_RNPR (0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register -#define AT91C_MCI_TPR (0xFFFB4108) // (PDC_MCI) Transmit Pointer Register -#define AT91C_MCI_RPR (0xFFFB4100) // (PDC_MCI) Receive Pointer Register -#define AT91C_MCI_PTSR (0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register -#define AT91C_MCI_TNCR (0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register -#define AT91C_MCI_RNCR (0xFFFB4114) // (PDC_MCI) Receive Next Counter Register -#define AT91C_MCI_TCR (0xFFFB410C) // (PDC_MCI) Transmit Counter Register -#define AT91C_MCI_RCR (0xFFFB4104) // (PDC_MCI) Receive Counter Register -// ========== Register definition for MCI peripheral ========== -#define AT91C_MCI_IDR (0xFFFB4048) // (MCI) MCI Interrupt Disable Register -#define AT91C_MCI_SR (0xFFFB4040) // (MCI) MCI Status Register -#define AT91C_MCI_RDR (0xFFFB4030) // (MCI) MCI Receive Data Register -#define AT91C_MCI_RSPR (0xFFFB4020) // (MCI) MCI Response Register -#define AT91C_MCI_ARGR (0xFFFB4010) // (MCI) MCI Argument Register -#define AT91C_MCI_DTOR (0xFFFB4008) // (MCI) MCI Data Timeout Register -#define AT91C_MCI_CR (0xFFFB4000) // (MCI) MCI Control Register -#define AT91C_MCI_IMR (0xFFFB404C) // (MCI) MCI Interrupt Mask Register -#define AT91C_MCI_IER (0xFFFB4044) // (MCI) MCI Interrupt Enable Register -#define AT91C_MCI_TDR (0xFFFB4034) // (MCI) MCI Transmit Data Register -#define AT91C_MCI_CMDR (0xFFFB4014) // (MCI) MCI Command Register -#define AT91C_MCI_SDCR (0xFFFB400C) // (MCI) MCI SD Card Register -#define AT91C_MCI_MR (0xFFFB4004) // (MCI) MCI Mode Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register -// ========== Register definition for TC5 peripheral ========== -#define AT91C_TC5_CMR (0xFFFA4084) // (TC5) Channel Mode Register -#define AT91C_TC5_IDR (0xFFFA40A8) // (TC5) Interrupt Disable Register -#define AT91C_TC5_SR (0xFFFA40A0) // (TC5) Status Register -#define AT91C_TC5_RB (0xFFFA4098) // (TC5) Register B -#define AT91C_TC5_CV (0xFFFA4090) // (TC5) Counter Value -#define AT91C_TC5_CCR (0xFFFA4080) // (TC5) Channel Control Register -#define AT91C_TC5_IMR (0xFFFA40AC) // (TC5) Interrupt Mask Register -#define AT91C_TC5_IER (0xFFFA40A4) // (TC5) Interrupt Enable Register -#define AT91C_TC5_RC (0xFFFA409C) // (TC5) Register C -#define AT91C_TC5_RA (0xFFFA4094) // (TC5) Register A -// ========== Register definition for TC4 peripheral ========== -#define AT91C_TC4_IMR (0xFFFA406C) // (TC4) Interrupt Mask Register -#define AT91C_TC4_IER (0xFFFA4064) // (TC4) Interrupt Enable Register -#define AT91C_TC4_RC (0xFFFA405C) // (TC4) Register C -#define AT91C_TC4_RA (0xFFFA4054) // (TC4) Register A -#define AT91C_TC4_CMR (0xFFFA4044) // (TC4) Channel Mode Register -#define AT91C_TC4_IDR (0xFFFA4068) // (TC4) Interrupt Disable Register -#define AT91C_TC4_SR (0xFFFA4060) // (TC4) Status Register -#define AT91C_TC4_RB (0xFFFA4058) // (TC4) Register B -#define AT91C_TC4_CV (0xFFFA4050) // (TC4) Counter Value -#define AT91C_TC4_CCR (0xFFFA4040) // (TC4) Channel Control Register -// ========== Register definition for TC3 peripheral ========== -#define AT91C_TC3_IMR (0xFFFA402C) // (TC3) Interrupt Mask Register -#define AT91C_TC3_CV (0xFFFA4010) // (TC3) Counter Value -#define AT91C_TC3_CCR (0xFFFA4000) // (TC3) Channel Control Register -#define AT91C_TC3_IER (0xFFFA4024) // (TC3) Interrupt Enable Register -#define AT91C_TC3_CMR (0xFFFA4004) // (TC3) Channel Mode Register -#define AT91C_TC3_RA (0xFFFA4014) // (TC3) Register A -#define AT91C_TC3_RC (0xFFFA401C) // (TC3) Register C -#define AT91C_TC3_IDR (0xFFFA4028) // (TC3) Interrupt Disable Register -#define AT91C_TC3_RB (0xFFFA4018) // (TC3) Register B -#define AT91C_TC3_SR (0xFFFA4020) // (TC3) Status Register -// ========== Register definition for TCB1 peripheral ========== -#define AT91C_TCB1_BCR (0xFFFA4140) // (TCB1) TC Block Control Register -#define AT91C_TCB1_BMR (0xFFFA4144) // (TCB1) TC Block Mode Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register -#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register -#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register -#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB0 peripheral ========== -#define AT91C_TCB0_BMR (0xFFFA00C4) // (TCB0) TC Block Mode Register -#define AT91C_TCB0_BCR (0xFFFA00C0) // (TCB0) TC Block Control Register -// ========== Register definition for UHP peripheral ========== -#define AT91C_UHP_HcRhDescriptorA (0x00300048) // (UHP) Root Hub characteristics A -#define AT91C_UHP_HcRhPortStatus (0x00300054) // (UHP) Root Hub Port Status Register -#define AT91C_UHP_HcRhDescriptorB (0x0030004C) // (UHP) Root Hub characteristics B -#define AT91C_UHP_HcControl (0x00300004) // (UHP) Operating modes for the Host Controller -#define AT91C_UHP_HcInterruptStatus (0x0030000C) // (UHP) Interrupt Status Register -#define AT91C_UHP_HcRhStatus (0x00300050) // (UHP) Root Hub Status register -#define AT91C_UHP_HcRevision (0x00300000) // (UHP) Revision -#define AT91C_UHP_HcCommandStatus (0x00300008) // (UHP) Command & status Register -#define AT91C_UHP_HcInterruptEnable (0x00300010) // (UHP) Interrupt Enable Register -#define AT91C_UHP_HcHCCA (0x00300018) // (UHP) Pointer to the Host Controller Communication Area -#define AT91C_UHP_HcControlHeadED (0x00300020) // (UHP) First Endpoint Descriptor of the Control list -#define AT91C_UHP_HcInterruptDisable (0x00300014) // (UHP) Interrupt Disable Register -#define AT91C_UHP_HcPeriodCurrentED (0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor -#define AT91C_UHP_HcControlCurrentED (0x00300024) // (UHP) Endpoint Control and Status Register -#define AT91C_UHP_HcBulkCurrentED (0x0030002C) // (UHP) Current endpoint of the Bulk list -#define AT91C_UHP_HcFmInterval (0x00300034) // (UHP) Bit time between 2 consecutive SOFs -#define AT91C_UHP_HcBulkHeadED (0x00300028) // (UHP) First endpoint register of the Bulk list -#define AT91C_UHP_HcBulkDoneHead (0x00300030) // (UHP) Last completed transfer descriptor -#define AT91C_UHP_HcFmRemaining (0x00300038) // (UHP) Bit time remaining in the current Frame -#define AT91C_UHP_HcPeriodicStart (0x00300040) // (UHP) Periodic Start -#define AT91C_UHP_HcLSThreshold (0x00300044) // (UHP) LS Threshold -#define AT91C_UHP_HcFmNumber (0x0030003C) // (UHP) Frame number -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_RSR (0xFFFBC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_MAN (0xFFFBC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_HSH (0xFFFBC090) // (EMAC) Hash Address High[63:32] -#define AT91C_EMAC_MCOL (0xFFFBC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_IER (0xFFFBC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA2H (0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes -#define AT91C_EMAC_HSL (0xFFFBC094) // (EMAC) Hash Address Low[31:0] -#define AT91C_EMAC_LCOL (0xFFFBC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_OK (0xFFFBC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_CFG (0xFFFBC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_SA3L (0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes -#define AT91C_EMAC_SEQE (0xFFFBC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_ECOL (0xFFFBC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_ELR (0xFFFBC070) // (EMAC) Excessive Length Error Register -#define AT91C_EMAC_SR (0xFFFBC008) // (EMAC) Network Status Register -#define AT91C_EMAC_RBQP (0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_CSE (0xFFFBC064) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_RJB (0xFFFBC074) // (EMAC) Receive Jabber Register -#define AT91C_EMAC_USF (0xFFFBC078) // (EMAC) Undersize Frame Register -#define AT91C_EMAC_IDR (0xFFFBC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_SA1L (0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes -#define AT91C_EMAC_IMR (0xFFFBC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_FRA (0xFFFBC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_SA3H (0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes -#define AT91C_EMAC_SA1H (0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes -#define AT91C_EMAC_SCOL (0xFFFBC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_ALE (0xFFFBC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_TAR (0xFFFBC00C) // (EMAC) Transmit Address Register -#define AT91C_EMAC_SA4L (0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes -#define AT91C_EMAC_SA2L (0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes -#define AT91C_EMAC_TUE (0xFFFBC068) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_DTE (0xFFFBC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TCR (0xFFFBC010) // (EMAC) Transmit Control Register -#define AT91C_EMAC_CTL (0xFFFBC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4H (0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr -#define AT91C_EMAC_CDE (0xFFFBC06C) // (EMAC) Code Error Register -#define AT91C_EMAC_SQEE (0xFFFBC07C) // (EMAC) SQE Test Error Register -#define AT91C_EMAC_TSR (0xFFFBC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_DRFC (0xFFFBC080) // (EMAC) Discarded RX Frame Register -// ========== Register definition for EBI peripheral ========== -#define AT91C_EBI_CFGR (0xFFFFFF64) // (EBI) Configuration Register -#define AT91C_EBI_CSA (0xFFFFFF60) // (EBI) Chip Select Assignment Register -// ========== Register definition for SMC2 peripheral ========== -#define AT91C_SMC2_CSR (0xFFFFFF70) // (SMC2) SMC2 Chip Select Register -// ========== Register definition for SDRC peripheral ========== -#define AT91C_SDRC_IMR (0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register -#define AT91C_SDRC_IER (0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register -#define AT91C_SDRC_SRR (0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register -#define AT91C_SDRC_TR (0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register -#define AT91C_SDRC_ISR (0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register -#define AT91C_SDRC_IDR (0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register -#define AT91C_SDRC_LPR (0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register -#define AT91C_SDRC_CR (0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register -#define AT91C_SDRC_MR (0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register -// ========== Register definition for BFC peripheral ========== -#define AT91C_BFC_MR (0xFFFFFFC0) // (BFC) BFC Mode Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_MISO (AT91C_PIO_PA0) // SPI Master In Slave -#define AT91C_PA0_PCK3 (AT91C_PIO_PA0) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_MOSI (AT91C_PIO_PA1) // SPI Master Out Slave -#define AT91C_PA1_PCK0 (AT91C_PIO_PA1) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_ETX1 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 1 -#define AT91C_PA10_MCDB1 (AT91C_PIO_PA10) // Multimedia Card B Data 1 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_ECRS_ECRSDV (AT91C_PIO_PA11) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PA11_MCDB2 (AT91C_PIO_PA11) // Multimedia Card B Data 2 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_ERX0 (AT91C_PIO_PA12) // Ethernet MAC Receive Data 0 -#define AT91C_PA12_MCDB3 (AT91C_PIO_PA12) // Multimedia Card B Data 3 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_ERX1 (AT91C_PIO_PA13) // Ethernet MAC Receive Data 1 -#define AT91C_PA13_TCLK0 (AT91C_PIO_PA13) // Timer Counter 0 external clock input -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_ERXER (AT91C_PIO_PA14) // Ethernet MAC Receive Error -#define AT91C_PA14_TCLK1 (AT91C_PIO_PA14) // Timer Counter 1 external clock input -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_EMDC (AT91C_PIO_PA15) // Ethernet MAC Management Data Clock -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_EMDIO (AT91C_PIO_PA16) // Ethernet MAC Management Data Input/Output -#define AT91C_PA16_IRQ6 (AT91C_PIO_PA16) // AIC Interrupt input 6 -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TXD0 (AT91C_PIO_PA17) // USART 0 Transmit Data -#define AT91C_PA17_TIOA0 (AT91C_PIO_PA17) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RXD0 (AT91C_PIO_PA18) // USART 0 Receive Data -#define AT91C_PA18_TIOB0 (AT91C_PIO_PA18) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_SCK0 (AT91C_PIO_PA19) // USART 0 Serial Clock -#define AT91C_PA19_TIOA1 (AT91C_PIO_PA19) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SPCK (AT91C_PIO_PA2) // SPI Serial Clock -#define AT91C_PA2_IRQ4 (AT91C_PIO_PA2) // AIC Interrupt Input 4 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CTS0 (AT91C_PIO_PA20) // USART 0 Clear To Send -#define AT91C_PA20_TIOB1 (AT91C_PIO_PA20) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RTS0 (AT91C_PIO_PA21) // Usart 0 Ready To Send -#define AT91C_PA21_TIOA2 (AT91C_PIO_PA21) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_RXD2 (AT91C_PIO_PA22) // USART 2 Receive Data -#define AT91C_PA22_TIOB2 (AT91C_PIO_PA22) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TXD2 (AT91C_PIO_PA23) // USART 2 Transmit Data -#define AT91C_PA23_IRQ3 (AT91C_PIO_PA23) // Interrupt input 3 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_SCK2 (AT91C_PIO_PA24) // USART2 Serial Clock -#define AT91C_PA24_PCK1 (AT91C_PIO_PA24) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_TWD (AT91C_PIO_PA25) // TWI Two-wire Serial Data -#define AT91C_PA25_IRQ2 (AT91C_PIO_PA25) // Interrupt input 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_TWCK (AT91C_PIO_PA26) // TWI Two-wire Serial Clock -#define AT91C_PA26_IRQ1 (AT91C_PIO_PA26) // Interrupt input 1 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_MCCK (AT91C_PIO_PA27) // Multimedia Card Clock -#define AT91C_PA27_TCLK3 (AT91C_PIO_PA27) // Timer Counter 3 External Clock Input -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_MCCDA (AT91C_PIO_PA28) // Multimedia Card A Command -#define AT91C_PA28_TCLK4 (AT91C_PIO_PA28) // Timer Counter 4 external Clock Input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_MCDA0 (AT91C_PIO_PA29) // Multimedia Card A Data 0 -#define AT91C_PA29_TCLK5 (AT91C_PIO_PA29) // Timer Counter 5 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_NPCS0 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 0 -#define AT91C_PA3_IRQ5 (AT91C_PIO_PA3) // AIC Interrupt Input 5 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_DRXD (AT91C_PIO_PA30) // DBGU Debug Receive Data -#define AT91C_PA30_CTS2 (AT91C_PIO_PA30) // Usart 2 Clear To Send -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_DTXD (AT91C_PIO_PA31) // DBGU Debug Transmit Data -#define AT91C_PA31_RTS2 (AT91C_PIO_PA31) // USART 2 Ready To Send -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_NPCS1 (AT91C_PIO_PA4) // SPI Peripheral Chip Select 1 -#define AT91C_PA4_PCK1 (AT91C_PIO_PA4) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_NPCS2 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 2 -#define AT91C_PA5_TXD3 (AT91C_PIO_PA5) // USART 3 Transmit Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_NPCS3 (AT91C_PIO_PA6) // SPI Peripheral Chip Select 3 -#define AT91C_PA6_RXD3 (AT91C_PIO_PA6) // USART 3 Receive Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_ETXCK_EREFCK (AT91C_PIO_PA7) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PA7_PCK2 (AT91C_PIO_PA7) // PMC Programmable Clock 2 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_ETXEN (AT91C_PIO_PA8) // Ethernet MAC Transmit Enable -#define AT91C_PA8_MCCDB (AT91C_PIO_PA8) // Multimedia Card B Command -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_ETX0 (AT91C_PIO_PA9) // Ethernet MAC Transmit Data 0 -#define AT91C_PA9_MCDB0 (AT91C_PIO_PA9) // Multimedia Card B Data 0 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_TF0 (AT91C_PIO_PB0) // SSC Transmit Frame Sync 0 -#define AT91C_PB0_TIOB3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_TK0 (AT91C_PIO_PB1) // SSC Transmit Clock 0 -#define AT91C_PB1_CTS3 (AT91C_PIO_PB1) // USART 3 Clear To Send -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_RK1 (AT91C_PIO_PB10) // SSC Receive Clock 1 -#define AT91C_PB10_TIOA5 (AT91C_PIO_PB10) // Timer Counter 5 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_RF1 (AT91C_PIO_PB11) // SSC Receive Frame Sync 1 -#define AT91C_PB11_TIOB5 (AT91C_PIO_PB11) // Timer Counter 5 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_TF2 (AT91C_PIO_PB12) // SSC Transmit Frame Sync 2 -#define AT91C_PB12_ETX2 (AT91C_PIO_PB12) // Ethernet MAC Transmit Data 2 -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_TK2 (AT91C_PIO_PB13) // SSC Transmit Clock 2 -#define AT91C_PB13_ETX3 (AT91C_PIO_PB13) // Ethernet MAC Transmit Data 3 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_TD2 (AT91C_PIO_PB14) // SSC Transmit Data 2 -#define AT91C_PB14_ETXER (AT91C_PIO_PB14) // Ethernet MAC Transmikt Coding Error -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_RD2 (AT91C_PIO_PB15) // SSC Receive Data 2 -#define AT91C_PB15_ERX2 (AT91C_PIO_PB15) // Ethernet MAC Receive Data 2 -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_RK2 (AT91C_PIO_PB16) // SSC Receive Clock 2 -#define AT91C_PB16_ERX3 (AT91C_PIO_PB16) // Ethernet MAC Receive Data 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_RF2 (AT91C_PIO_PB17) // SSC Receive Frame Sync 2 -#define AT91C_PB17_ERXDV (AT91C_PIO_PB17) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_RI1 (AT91C_PIO_PB18) // USART 1 Ring Indicator -#define AT91C_PB18_ECOL (AT91C_PIO_PB18) // Ethernet MAC Collision Detected -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_DTR1 (AT91C_PIO_PB19) // USART 1 Data Terminal ready -#define AT91C_PB19_ERXCK (AT91C_PIO_PB19) // Ethernet MAC Receive Clock -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_TD0 (AT91C_PIO_PB2) // SSC Transmit data -#define AT91C_PB2_SCK3 (AT91C_PIO_PB2) // USART 3 Serial Clock -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_TXD1 (AT91C_PIO_PB20) // USART 1 Transmit Data -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_RXD1 (AT91C_PIO_PB21) // USART 1 Receive Data -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_SCK1 (AT91C_PIO_PB22) // USART1 Serial Clock -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_CTS1 (AT91C_PIO_PB24) // USART 1 Clear To Send -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_DSR1 (AT91C_PIO_PB25) // USART 1 Data Set ready -#define AT91C_PB25_EF100 (AT91C_PIO_PB25) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_RTS1 (AT91C_PIO_PB26) // Usart 0 Ready To Send -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_PCK0 (AT91C_PIO_PB27) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_FIQ (AT91C_PIO_PB28) // AIC Fast Interrupt Input -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_IRQ0 (AT91C_PIO_PB29) // Interrupt input 0 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_RD0 (AT91C_PIO_PB3) // SSC Receive Data -#define AT91C_PB3_MCDA1 (AT91C_PIO_PB3) // Multimedia Card A Data 1 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_RK0 (AT91C_PIO_PB4) // SSC Receive Clock -#define AT91C_PB4_MCDA2 (AT91C_PIO_PB4) // Multimedia Card A Data 2 -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_RF0 (AT91C_PIO_PB5) // SSC Receive Frame Sync 0 -#define AT91C_PB5_MCDA3 (AT91C_PIO_PB5) // Multimedia Card A Data 3 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_TF1 (AT91C_PIO_PB6) // SSC Transmit Frame Sync 1 -#define AT91C_PB6_TIOA3 (AT91C_PIO_PB6) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_TK1 (AT91C_PIO_PB7) // SSC Transmit Clock 1 -#define AT91C_PB7_TIOB3 (AT91C_PIO_PB7) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_TD1 (AT91C_PIO_PB8) // SSC Transmit Data 1 -#define AT91C_PB8_TIOA4 (AT91C_PIO_PB8) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_RD1 (AT91C_PIO_PB9) // SSC Receive Data 1 -#define AT91C_PB9_TIOB4 (AT91C_PIO_PB9) // Timer Counter 4 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 -#define AT91C_PC0_BFCK (AT91C_PIO_PC0) // Burst Flash Clock -#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 -#define AT91C_PC1_BFRDY_SMOE (AT91C_PIO_PC1) // Burst Flash Ready -#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 -#define AT91C_PC10_NCS4_CFCS (AT91C_PIO_PC10) // Compact Flash Chip Select -#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 -#define AT91C_PC11_NCS5_CFCE1 (AT91C_PIO_PC11) // Chip Select 5 / Compact Flash Chip Enable 1 -#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 -#define AT91C_PC12_NCS6_CFCE2 (AT91C_PIO_PC12) // Chip Select 6 / Compact Flash Chip Enable 2 -#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 -#define AT91C_PC13_NCS7 (AT91C_PIO_PC13) // Chip Select 7 -#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 -#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 -#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 -#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus [16] -#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 -#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus [17] -#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 -#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus [18] -#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 -#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus [19] -#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 -#define AT91C_PC2_BFAVD (AT91C_PIO_PC2) // Burst Flash Address Valid -#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 -#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus [20] -#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 -#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus [21] -#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 -#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus [22] -#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 -#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus [23] -#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24 -#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus [24] -#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25 -#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus [25] -#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26 -#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus [26] -#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27 -#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus [27] -#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28 -#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus [28] -#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29 -#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus [29] -#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 -#define AT91C_PC3_BFBAA_SMWE (AT91C_PIO_PC3) // Burst Flash Address Advance / SmartMedia Write Enable -#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30 -#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus [30] -#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31 -#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus [31] -#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 -#define AT91C_PC4_BFOE (AT91C_PIO_PC4) // Burst Flash Output Enable -#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 -#define AT91C_PC5_BFWE (AT91C_PIO_PC5) // Burst Flash Write Enable -#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 -#define AT91C_PC6_NWAIT (AT91C_PIO_PC6) // NWAIT -#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 -#define AT91C_PC7_A23 (AT91C_PIO_PC7) // Address Bus[23] -#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 -#define AT91C_PC8_A24 (AT91C_PIO_PC8) // Address Bus[24] -#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 -#define AT91C_PC9_A25_CFRNW (AT91C_PIO_PC9) // Address Bus[25] / Compact Flash Read Not Write -#define AT91C_PIO_PD0 (1 << 0) // Pin Controlled by PD0 -#define AT91C_PD0_ETX0 (AT91C_PIO_PD0) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PD1 (1 << 1) // Pin Controlled by PD1 -#define AT91C_PD1_ETX1 (AT91C_PIO_PD1) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PD10 (1 << 10) // Pin Controlled by PD10 -#define AT91C_PD10_PCK3 (AT91C_PIO_PD10) // PMC Programmable Clock Output 3 -#define AT91C_PD10_TPS1 (AT91C_PIO_PD10) // ETM ARM9 pipeline status 1 -#define AT91C_PIO_PD11 (1 << 11) // Pin Controlled by PD11 -#define AT91C_PD11_ (AT91C_PIO_PD11) // -#define AT91C_PD11_TPS2 (AT91C_PIO_PD11) // ETM ARM9 pipeline status 2 -#define AT91C_PIO_PD12 (1 << 12) // Pin Controlled by PD12 -#define AT91C_PD12_ (AT91C_PIO_PD12) // -#define AT91C_PD12_TPK0 (AT91C_PIO_PD12) // ETM Trace Packet 0 -#define AT91C_PIO_PD13 (1 << 13) // Pin Controlled by PD13 -#define AT91C_PD13_ (AT91C_PIO_PD13) // -#define AT91C_PD13_TPK1 (AT91C_PIO_PD13) // ETM Trace Packet 1 -#define AT91C_PIO_PD14 (1 << 14) // Pin Controlled by PD14 -#define AT91C_PD14_ (AT91C_PIO_PD14) // -#define AT91C_PD14_TPK2 (AT91C_PIO_PD14) // ETM Trace Packet 2 -#define AT91C_PIO_PD15 (1 << 15) // Pin Controlled by PD15 -#define AT91C_PD15_TD0 (AT91C_PIO_PD15) // SSC Transmit data -#define AT91C_PD15_TPK3 (AT91C_PIO_PD15) // ETM Trace Packet 3 -#define AT91C_PIO_PD16 (1 << 16) // Pin Controlled by PD16 -#define AT91C_PD16_TD1 (AT91C_PIO_PD16) // SSC Transmit Data 1 -#define AT91C_PD16_TPK4 (AT91C_PIO_PD16) // ETM Trace Packet 4 -#define AT91C_PIO_PD17 (1 << 17) // Pin Controlled by PD17 -#define AT91C_PD17_TD2 (AT91C_PIO_PD17) // SSC Transmit Data 2 -#define AT91C_PD17_TPK5 (AT91C_PIO_PD17) // ETM Trace Packet 5 -#define AT91C_PIO_PD18 (1 << 18) // Pin Controlled by PD18 -#define AT91C_PD18_NPCS1 (AT91C_PIO_PD18) // SPI Peripheral Chip Select 1 -#define AT91C_PD18_TPK6 (AT91C_PIO_PD18) // ETM Trace Packet 6 -#define AT91C_PIO_PD19 (1 << 19) // Pin Controlled by PD19 -#define AT91C_PD19_NPCS2 (AT91C_PIO_PD19) // SPI Peripheral Chip Select 2 -#define AT91C_PD19_TPK7 (AT91C_PIO_PD19) // ETM Trace Packet 7 -#define AT91C_PIO_PD2 (1 << 2) // Pin Controlled by PD2 -#define AT91C_PD2_ETX2 (AT91C_PIO_PD2) // Ethernet MAC Transmit Data 2 -#define AT91C_PIO_PD20 (1 << 20) // Pin Controlled by PD20 -#define AT91C_PD20_NPCS3 (AT91C_PIO_PD20) // SPI Peripheral Chip Select 3 -#define AT91C_PD20_TPK8 (AT91C_PIO_PD20) // ETM Trace Packet 8 -#define AT91C_PIO_PD21 (1 << 21) // Pin Controlled by PD21 -#define AT91C_PD21_RTS0 (AT91C_PIO_PD21) // Usart 0 Ready To Send -#define AT91C_PD21_TPK9 (AT91C_PIO_PD21) // ETM Trace Packet 9 -#define AT91C_PIO_PD22 (1 << 22) // Pin Controlled by PD22 -#define AT91C_PD22_RTS1 (AT91C_PIO_PD22) // Usart 0 Ready To Send -#define AT91C_PD22_TPK10 (AT91C_PIO_PD22) // ETM Trace Packet 10 -#define AT91C_PIO_PD23 (1 << 23) // Pin Controlled by PD23 -#define AT91C_PD23_RTS2 (AT91C_PIO_PD23) // USART 2 Ready To Send -#define AT91C_PD23_TPK11 (AT91C_PIO_PD23) // ETM Trace Packet 11 -#define AT91C_PIO_PD24 (1 << 24) // Pin Controlled by PD24 -#define AT91C_PD24_RTS3 (AT91C_PIO_PD24) // USART 3 Ready To Send -#define AT91C_PD24_TPK12 (AT91C_PIO_PD24) // ETM Trace Packet 12 -#define AT91C_PIO_PD25 (1 << 25) // Pin Controlled by PD25 -#define AT91C_PD25_DTR1 (AT91C_PIO_PD25) // USART 1 Data Terminal ready -#define AT91C_PD25_TPK13 (AT91C_PIO_PD25) // ETM Trace Packet 13 -#define AT91C_PIO_PD26 (1 << 26) // Pin Controlled by PD26 -#define AT91C_PD26_TPK14 (AT91C_PIO_PD26) // ETM Trace Packet 14 -#define AT91C_PIO_PD27 (1 << 27) // Pin Controlled by PD27 -#define AT91C_PD27_TPK15 (AT91C_PIO_PD27) // ETM Trace Packet 15 -#define AT91C_PIO_PD3 (1 << 3) // Pin Controlled by PD3 -#define AT91C_PD3_ETX3 (AT91C_PIO_PD3) // Ethernet MAC Transmit Data 3 -#define AT91C_PIO_PD4 (1 << 4) // Pin Controlled by PD4 -#define AT91C_PD4_ETXEN (AT91C_PIO_PD4) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PD5 (1 << 5) // Pin Controlled by PD5 -#define AT91C_PD5_ETXER (AT91C_PIO_PD5) // Ethernet MAC Transmikt Coding Error -#define AT91C_PIO_PD6 (1 << 6) // Pin Controlled by PD6 -#define AT91C_PD6_DTXD (AT91C_PIO_PD6) // DBGU Debug Transmit Data -#define AT91C_PIO_PD7 (1 << 7) // Pin Controlled by PD7 -#define AT91C_PD7_PCK0 (AT91C_PIO_PD7) // PMC Programmable Clock Output 0 -#define AT91C_PD7_TSYNC (AT91C_PIO_PD7) // ETM Synchronization signal -#define AT91C_PIO_PD8 (1 << 8) // Pin Controlled by PD8 -#define AT91C_PD8_PCK1 (AT91C_PIO_PD8) // PMC Programmable Clock Output 1 -#define AT91C_PD8_TCLK (AT91C_PIO_PD8) // ETM Trace Clock signal -#define AT91C_PIO_PD9 (1 << 9) // Pin Controlled by PD9 -#define AT91C_PD9_PCK2 (AT91C_PIO_PD9) // PMC Programmable Clock 2 -#define AT91C_PD9_TPS0 (AT91C_PIO_PD9) // ETM ARM9 pipeline status 0 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C -#define AT91C_ID_PIOD ( 5) // Parallel IO Controller D -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_US2 ( 8) // USART 2 -#define AT91C_ID_US3 ( 9) // USART 3 -#define AT91C_ID_MCI (10) // Multimedia Card Interface -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TWI (12) // Two-Wire Interface -#define AT91C_ID_SPI (13) // Serial Peripheral Interface -#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0 -#define AT91C_ID_SSC1 (15) // Serial Synchronous Controller 1 -#define AT91C_ID_SSC2 (16) // Serial Synchronous Controller 2 -#define AT91C_ID_TC0 (17) // Timer Counter 0 -#define AT91C_ID_TC1 (18) // Timer Counter 1 -#define AT91C_ID_TC2 (19) // Timer Counter 2 -#define AT91C_ID_TC3 (20) // Timer Counter 3 -#define AT91C_ID_TC4 (21) // Timer Counter 4 -#define AT91C_ID_TC5 (22) // Timer Counter 5 -#define AT91C_ID_UHP (23) // USB Host port -#define AT91C_ID_EMAC (24) // Ethernet MAC -#define AT91C_ID_IRQ0 (25) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (26) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ID_IRQ2 (27) // Advanced Interrupt Controller (IRQ2) -#define AT91C_ID_IRQ3 (28) // Advanced Interrupt Controller (IRQ3) -#define AT91C_ID_IRQ4 (29) // Advanced Interrupt Controller (IRQ4) -#define AT91C_ID_IRQ5 (30) // Advanced Interrupt Controller (IRQ5) -#define AT91C_ID_IRQ6 (31) // Advanced Interrupt Controller (IRQ6) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_RTC (0xFFFFFE00) // (RTC) Base Address -#define AT91C_BASE_ST (0xFFFFFD00) // (ST) Base Address -#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PIOD (0xFFFFFA00) // (PIOD) Base Address -#define AT91C_BASE_PIOC (0xFFFFF800) // (PIOC) Base Address -#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_SSC2 (0xFFFD8100) // (PDC_SSC2) Base Address -#define AT91C_BASE_SSC2 (0xFFFD8000) // (SSC2) Base Address -#define AT91C_BASE_PDC_SSC1 (0xFFFD4100) // (PDC_SSC1) Base Address -#define AT91C_BASE_SSC1 (0xFFFD4000) // (SSC1) Base Address -#define AT91C_BASE_PDC_SSC0 (0xFFFD0100) // (PDC_SSC0) Base Address -#define AT91C_BASE_SSC0 (0xFFFD0000) // (SSC0) Base Address -#define AT91C_BASE_PDC_US3 (0xFFFCC100) // (PDC_US3) Base Address -#define AT91C_BASE_US3 (0xFFFCC000) // (US3) Base Address -#define AT91C_BASE_PDC_US2 (0xFFFC8100) // (PDC_US2) Base Address -#define AT91C_BASE_US2 (0xFFFC8000) // (US2) Base Address -#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PDC_MCI (0xFFFB4100) // (PDC_MCI) Base Address -#define AT91C_BASE_MCI (0xFFFB4000) // (MCI) Base Address -#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC5 (0xFFFA4080) // (TC5) Base Address -#define AT91C_BASE_TC4 (0xFFFA4040) // (TC4) Base Address -#define AT91C_BASE_TC3 (0xFFFA4000) // (TC3) Base Address -#define AT91C_BASE_TCB1 (0xFFFA4080) // (TCB1) Base Address -#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TCB0 (0xFFFA0000) // (TCB0) Base Address -#define AT91C_BASE_UHP (0x00300000) // (UHP) Base Address -#define AT91C_BASE_EMAC (0xFFFBC000) // (EMAC) Base Address -#define AT91C_BASE_EBI (0xFFFFFF60) // (EBI) Base Address -#define AT91C_BASE_SMC2 (0xFFFFFF70) // (SMC2) Base Address -#define AT91C_BASE_SDRC (0xFFFFFF90) // (SDRC) Base Address -#define AT91C_BASE_BFC (0xFFFFFFC0) // (BFC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte) -#define AT91C_IROM (0x00100000) // Internal ROM base address -#define AT91C_IROM_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte) - - diff --git a/target/linux/at91-2.6/image/dfboot/src/include/led.h b/target/linux/at91-2.6/image/dfboot/src/include/led.h deleted file mode 100644 index 9bebd9c3cb..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/include/led.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2006 - * Atmel Nordic AB <www.atmel.com> - * Ulf Samuelsson <ulf@atmel.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - #ifndef __LED_H -#define __LED_H - -#ifndef __ASSEMBLY__ -extern void LED_init (void); -extern void LED_set(unsigned int led); -extern void red_LED_on(void); -extern void red_LED_off(void); -extern void green_LED_on(void); -extern void green_LED_off(void); -extern void yellow_LED_on(void); -extern void yellow_LED_off(void); -extern void LED_blink(unsigned int led); -#else - .extern LED_init - .extern LED_set - .extern LED_blink - .extern red_LED_on - .extern red_LED_off - .extern yellow_LED_on - .extern yellow_LED_off - .extern green_LED_on - .extern green_LED_off -#endif -#endif diff --git a/target/linux/at91-2.6/image/dfboot/src/include/lib_AT91RM9200.h b/target/linux/at91-2.6/image/dfboot/src/include/lib_AT91RM9200.h deleted file mode 100644 index c322b32a49..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/include/lib_AT91RM9200.h +++ /dev/null @@ -1,2978 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : lib_AT91RM9200.h -//* Object : AT91RM9200 inlined functions -//* Generated : AT91 SW Application Group 11/19/2003 (17:20:51) -//* -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 02 12:29:40 2002// -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_rtc_1245d.h/1.1/Fri Jan 31 12:19:12 2003// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_spi_AT91RMxxxx.h/1.2/Fri Jan 31 12:19:31 2003// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_pmc.h/1.3/Thu Nov 14 07:40:45 2002// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:53 2002// -//* CVS Reference : /lib_mci.h/1.2/Wed Nov 20 14:18:55 2002// -//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:11 2002// -//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// -//* CVS Reference : /lib_st.h/1.4/Fri Jan 31 12:20:13 2003// -//*---------------------------------------------------------------------------- - -#ifndef lib_AT91RM9200_H -#define lib_AT91RM9200_H - -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR RTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_InterruptEnable -//* \brief Enable RTC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_RTC_InterruptEnable( - AT91PS_RTC pRtc, // \arg pointer to a RTC controller - unsigned int flag) // \arg RTC interrupt to be enabled -{ - pRtc->RTC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_InterruptDisable -//* \brief Disable RTC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_RTC_InterruptDisable( - AT91PS_RTC pRtc, // \arg pointer to a RTC controller - unsigned int flag) // \arg RTC interrupt to be disabled -{ - pRtc->RTC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_GetInterruptMaskStatus -//* \brief Return RTC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_RTC_GetInterruptMaskStatus( // \return RTC Interrupt Mask Status - AT91PS_RTC pRtc) // \arg pointer to a RTC controller -{ - return pRtc->RTC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_IsInterruptMasked -//* \brief Test if RTC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_RTC_IsInterruptMasked( - AT91PS_RTC pRtc, // \arg pointer to a RTC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_RTC_GetInterruptMaskStatus(pRtc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; - else - { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Open -//* \brief Open a SPI Port -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgCs ( - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(AT91C_SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; - - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) -{ - unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -static inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) -{ - return((pSPI->SPI_RDR) & 0xFFFF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetProcessorClock -//* \brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200) -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_GetProcessorClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLLA_CLK: // PLLA clock is selected - reg = pCKGR->CKGR_PLLAR; - pllDivider = (reg & AT91C_CKGR_DIVA); - pllMultiplier = ((reg & AT91C_CKGR_MULA) >> 16) + 1; - if (reg & AT91C_CKGR_SRCA) // Source is Main clock - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - else // Source is Slow clock - return slowClock / pllDivider * pllMultiplier / prescaler; - case AT91C_PMC_CSS_PLLB_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLBR; - pllDivider = (reg & AT91C_CKGR_DIVB); - pllMultiplier = ((reg & AT91C_CKGR_MULB) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz (just for AT91RM9200) -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return AT91F_PMC_GetProcessorClock(pPMC, pCKGR, slowClock) / - (((pPMC->PMC_MCKR & AT91C_PMC_MDIV) >> 8)+1); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int ccs, // \arg clock selection: AT91C_PMC_CSS_SLOW_CLK, AT91C_PMC_CSS_MAIN_CLK, AT91C_PMC_CSS_PLLA_CLK, AT91C_PMC_CSS_PLLB_CLK - unsigned int pres) // \arg Programmable clock prescalar AT91C_PMC_PRES_CLK, AT91C_PMC_PRES_CLK_2, ..., AT91C_PMC_PRES_CLK_64 -{ - pPMC->PMC_PCKR[pck] = ccs | pres; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -static inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -static inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -static inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -static inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -static inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Define the USART mode - pUSART->US_MR = mode ; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -static inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -static inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -static inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -static inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -static inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -static inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -static inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; - - //* Reset the USART mode - pUSART->US_MR = 0 ; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_TXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_RXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -static inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) -{ - pUSART->US_THR = (character & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -static inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) -{ - return((pUSART->US_RHR) & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -static inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR MCI - ***************************************************************************** */ -//* Classic MCI Mode Register Configuration with PDC mode enabled and MCK = MCI Clock -#define AT91C_MCI_MR_PDCMODE (AT91C_MCI_CLKDIV |\ - AT91C_MCI_PWSDIV |\ - (AT91C_MCI_PWSDIV<<1) |\ - AT91C_MCI_PDCMODE) - -//* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer -#define AT91C_MCI_DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL) - -//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A -#define AT91C_MCI_MMC_SLOTA (AT91C_MCI_SCDSEL & 0x0) - -//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B -#define AT91C_MCI_MMC_SLOTB (AT91C_MCI_SCDSEL) - -//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A -#define AT91C_MCI_SDCARD_4BITS_SLOTA ( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS ) - -//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B -#define AT91C_MCI_SDCARD_4BITS_SLOTB (AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS) - - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Configure -//* \brief Configure the MCI -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_Configure ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int DTOR_register, // \arg Data Timeout Register to be programmed - unsigned int MR_register, // \arg Mode Register to be programmed - unsigned int SDCR_register) // \arg SDCard Register to be programmed -{ - //* Reset the MCI - pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN; - - //* Disable all the interrupts - pMCI->MCI_IDR = 0xFFFFFFFF; - - //* Set the Data Timeout Register - pMCI->MCI_DTOR = DTOR_register; - - //* Set the Mode Register - pMCI->MCI_MR = MR_register; - - //* Set the SDCard Register - pMCI->MCI_SDCR = SDCR_register; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_EnableIt -//* \brief Enable MCI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_EnableIt ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pMCI->MCI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_DisableIt -//* \brief Disable MCI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_DisableIt ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pMCI->MCI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Enable_Interface -//* \brief Enable the MCI Interface -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_Enable_Interface ( - AT91PS_MCI pMCI) // \arg pointer to a MCI controller -{ - //* Enable the MCI - pMCI->MCI_CR = AT91C_MCI_MCIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Disable_Interface -//* \brief Disable the MCI Interface -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_Disable_Interface ( - AT91PS_MCI pMCI) // \arg pointer to a MCI controller -{ - //* Disable the MCI - pMCI->MCI_CR = AT91C_MCI_MCIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Cfg_ModeRegister -//* \brief Configure the MCI Mode Register -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_Cfg_ModeRegister ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int mode_register) // \arg value to set in the mode register -{ - //* Configure the MCI MR - pMCI->MCI_MR = mode_register; -} -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address -{ - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg endpoints to be enabled -{ - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg endpoints to be enabled -{ - pUDP->UDP_GLBSTATE &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller -{ - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status - AT91PS_UDP pUdp) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR ST - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_SetPeriodInterval -//* \brief Set Periodic Interval Interrupt (period in ms) -//*---------------------------------------------------------------------------- -static inline void AT91F_ST_SetPeriodInterval( - AT91PS_ST pSt, - unsigned int period) -{ - volatile int status; - pSt->ST_IDR = AT91C_ST_PITS; /* Interrupt disable Register */ - - status = pSt->ST_SR; - pSt->ST_PIMR = period << 5; /* Period Interval Mode Register == timer interval = 1ms*/ -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_EnableIt -//* \brief Enable system timer interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_ST_EnableIt( - AT91PS_ST pSt, - unsigned int flag) -{ - pSt->ST_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_DisableIt -//* \brief Disable system timer interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_ST_DisableIt( - AT91PS_ST pSt, - unsigned int flag) -{ - pSt->ST_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_GetInterruptMaskStatus -//* \brief Return ST Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ST_GetInterruptMaskStatus( // \return ST Interrupt Mask Status - AT91PS_ST pSt) // \arg pointer to a ST controller -{ - return pSt->ST_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_IsInterruptMasked -//* \brief Test if ST Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_ST_IsInterruptMasked( - AT91PS_ST pSt, // \arg pointer to a ST controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ST_GetInterruptMaskStatus(pSt) & flag); -} -//*---------------------------------------------------------------------------- -//* \fn AT91F_EBI_CfgPIO -//* \brief Configure PIO controllers to drive EBI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_EBI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOC, // PIO controller base address - ((unsigned int) AT91C_PC8_A24 ) | - ((unsigned int) AT91C_PC7_A23 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA31_DTXD ) | - ((unsigned int) AT91C_PA30_DRXD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SYS_CfgPMC -//* \brief Enable Peripheral clock in PMC for SYS -//*---------------------------------------------------------------------------- -static inline void AT91F_SYS_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UHP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UHP -//*---------------------------------------------------------------------------- -static inline void AT91F_UHP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UHP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SDRC_CfgPIO -//* \brief Configure PIO controllers to drive SDRC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SDRC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOC, // PIO controller base address - ((unsigned int) AT91C_PC20_D20 ) | - ((unsigned int) AT91C_PC21_D21 ) | - ((unsigned int) AT91C_PC30_D30 ) | - ((unsigned int) AT91C_PC22_D22 ) | - ((unsigned int) AT91C_PC31_D31 ) | - ((unsigned int) AT91C_PC23_D23 ) | - ((unsigned int) AT91C_PC16_D16 ) | - ((unsigned int) AT91C_PC24_D24 ) | - ((unsigned int) AT91C_PC17_D17 ) | - ((unsigned int) AT91C_PC25_D25 ) | - ((unsigned int) AT91C_PC18_D18 ) | - ((unsigned int) AT91C_PC26_D26 ) | - ((unsigned int) AT91C_PC19_D19 ) | - ((unsigned int) AT91C_PC27_D27 ) | - ((unsigned int) AT91C_PC28_D28 ) | - ((unsigned int) AT91C_PC29_D29 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPMC -//* \brief Enable Peripheral clock in PMC for EMAC -//*---------------------------------------------------------------------------- -static inline void AT91F_EMAC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_EMAC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPIO -//* \brief Configure PIO controllers to drive EMAC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_EMAC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA14_ERXER ) | - ((unsigned int) AT91C_PA12_ERX0 ) | - ((unsigned int) AT91C_PA13_ERX1 ) | - ((unsigned int) AT91C_PA8_ETXEN ) | - ((unsigned int) AT91C_PA16_EMDIO ) | - ((unsigned int) AT91C_PA9_ETX0 ) | - ((unsigned int) AT91C_PA10_ETX1 ) | - ((unsigned int) AT91C_PA11_ECRS_ECRSDV) | - ((unsigned int) AT91C_PA15_EMDC ) | - ((unsigned int) AT91C_PA7_ETXCK_EREFCK), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RTC -//*---------------------------------------------------------------------------- -static inline void AT91F_RTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC2 -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC2_CfgPIO -//* \brief Configure PIO controllers to drive SSC2 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB12_TF2 ) | - ((unsigned int) AT91C_PB17_RF2 ) | - ((unsigned int) AT91C_PB13_TK2 ) | - ((unsigned int) AT91C_PB16_RK2 ) | - ((unsigned int) AT91C_PB14_TD2 ) | - ((unsigned int) AT91C_PB15_RD2 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC1 -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC1_CfgPIO -//* \brief Configure PIO controllers to drive SSC1 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB11_RF1 ) | - ((unsigned int) AT91C_PB10_RK1 ) | - ((unsigned int) AT91C_PB8_TD1 ) | - ((unsigned int) AT91C_PB9_RD1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC0 -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPIO -//* \brief Configure PIO controllers to drive SPI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA3_NPCS0 ) | - ((unsigned int) AT91C_PA4_NPCS1 ) | - ((unsigned int) AT91C_PA1_MOSI ) | - ((unsigned int) AT91C_PA5_NPCS2 ) | - ((unsigned int) AT91C_PA6_NPCS3 ) | - ((unsigned int) AT91C_PA0_MISO ) | - ((unsigned int) AT91C_PA2_SPCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC5_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC5 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC5_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC5)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC4_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC4 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC4_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC4)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC3_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC3 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC3_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC3)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SMC2_CfgPIO -//* \brief Configure PIO controllers to drive SMC2 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SMC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOC, // PIO controller base address - ((unsigned int) AT91C_PC10_NCS4_CFCS) | - ((unsigned int) AT91C_PC9_A25_CFRNW) | - ((unsigned int) AT91C_PC12_NCS6_CFCE2) | - ((unsigned int) AT91C_PC11_NCS5_CFCE1), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA24_PCK1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB27_PCK0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOD_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOD -//*---------------------------------------------------------------------------- -static inline void AT91F_PIOD_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOD)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOC -//*---------------------------------------------------------------------------- -static inline void AT91F_PIOC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOB_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOB -//*---------------------------------------------------------------------------- -static inline void AT91F_PIOB_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOB)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -static inline void AT91F_PIOA_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA25_TWD ) | - ((unsigned int) AT91C_PA26_TWCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US3_CfgPMC -//* \brief Enable Peripheral clock in PMC for US3 -//*---------------------------------------------------------------------------- -static inline void AT91F_US3_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US3)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US2_CfgPMC -//* \brief Enable Peripheral clock in PMC for US2 -//*---------------------------------------------------------------------------- -static inline void AT91F_US2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US2_CfgPIO -//* \brief Configure PIO controllers to drive US2 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_US2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA23_TXD2 ) | - ((unsigned int) AT91C_PA22_RXD2 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -static inline void AT91F_US1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_US1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB21_RXD1 ) | - ((unsigned int) AT91C_PB26_RTS1 ) | - ((unsigned int) AT91C_PB25_DSR1 ) | - ((unsigned int) AT91C_PB24_CTS1 ) | - ((unsigned int) AT91C_PB19_DTR1 ) | - ((unsigned int) AT91C_PB23_DCD1 ) | - ((unsigned int) AT91C_PB20_TXD1 ) | - ((unsigned int) AT91C_PB18_RI1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -static inline void AT91F_US0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_US0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA17_TXD0 ) | - ((unsigned int) AT91C_PA21_RTS0 ) | - ((unsigned int) AT91C_PA19_SCK0 ) | - ((unsigned int) AT91C_PA20_CTS0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgPMC -//* \brief Enable Peripheral clock in PMC for MCI -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_MCI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgPIO -//* \brief Configure PIO controllers to drive MCI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA28_MCCDA ) | - ((unsigned int) AT91C_PA29_MCDA0 ) | - ((unsigned int) AT91C_PA27_MCCK ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB5_MCDA3 ) | - ((unsigned int) AT91C_PB3_MCDA1 ) | - ((unsigned int) AT91C_PB4_MCDA2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_IRQ4) | - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ5) | - ((unsigned int) 1 << AT91C_ID_IRQ6) | - ((unsigned int) 1 << AT91C_ID_IRQ0) | - ((unsigned int) 1 << AT91C_ID_IRQ1) | - ((unsigned int) 1 << AT91C_ID_IRQ2) | - ((unsigned int) 1 << AT91C_ID_IRQ3)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_CfgPMC -//* \brief Enable Peripheral clock in PMC for ST -//*---------------------------------------------------------------------------- -static inline void AT91F_ST_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -#endif // lib_AT91RM9200_H diff --git a/target/linux/at91-2.6/image/dfboot/src/init.c b/target/linux/at91-2.6/image/dfboot/src/init.c deleted file mode 100644 index 4088973f7d..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/init.c +++ /dev/null @@ -1,165 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : init.c -//* Object : Low level initialisations written in C -//* Creation : HIi 10/10/2003 -//* -//*---------------------------------------------------------------------------- -#include "config.h" -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" -#include "stdio.h" - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DataAbort -//* \brief This function reports an Abort -//*---------------------------------------------------------------------------- -static void AT91F_SpuriousHandler() -{ - puts("ISI"); - while (1); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DataAbort -//* \brief This function reports an Abort -//*---------------------------------------------------------------------------- -static void AT91F_DataAbort() -{ - puts("IDA"); - while (1); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_FetchAbort -//* \brief This function reports an Abort -//*---------------------------------------------------------------------------- -static void AT91F_FetchAbort() -{ - puts("IFA"); - while (1); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UndefHandler -//* \brief This function reports that no handler have been set for current IT -//*---------------------------------------------------------------------------- -static void AT91F_UndefHandler() -{ - puts("IUD"); - while (1); -} - - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_InitSdram -//* Object : Initialize the SDRAM -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static void AT91F_InitSdram() -{ - int *pRegister; - - //* Configure PIOC as peripheral (D16/D31) - - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOC, // PIO controller base address - 0xFFFF0030, - 0 - ); - - //*Init SDRAM - pRegister = (int *)0xFFFFFF98; - *pRegister = 0x2188c155; - pRegister = (int *)0xFFFFFF90; - *pRegister = 0x2; - pRegister = (int *)0x20000000; - *pRegister = 0; - pRegister = (int *)0xFFFFFF90; - *pRegister = 0x4; - pRegister = (int *)0x20000000; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - pRegister = (int *)0xFFFFFF90; - *pRegister = 0x3; - pRegister = (int *)0x20000080; - *pRegister = 0; - - pRegister = (int *)0xFFFFFF94; - *pRegister = 0x2e0; - pRegister = (int *)0x20000000; - *pRegister = 0; - - pRegister = (int *)0xFFFFFF90; - *pRegister = 0x00; - pRegister = (int *)0x20000000; - *pRegister = 0; -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_InitFlash -//* \brief This function performs low level HW initialization -//*---------------------------------------------------------------------------- -static void AT91F_InitMemories() -{ - int *pEbi = (int *)0xFFFFFF60; - - //* Setup MEMC to support all connected memories (CS0 = FLASH; CS1=SDRAM) - pEbi = (int *)0xFFFFFF60; - *pEbi = 0x00000002; - - //* CS0 cs for flash - pEbi = (int *)0xFFFFFF70; - *pEbi = 0x00003284; - - AT91F_InitSdram(); -} - - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_LowLevelInit -//* \brief This function performs very low level HW initialization -//*---------------------------------------------------------------------------- -void AT91F_LowLevelInit(void) -{ - int i; - - // Init Interrupt Controller - AT91F_AIC_Open( - AT91C_BASE_AIC, // pointer to the AIC registers - AT91C_AIC_BRANCH_OPCODE, // IRQ exception vector - AT91F_UndefHandler, // FIQ exception vector - AT91F_UndefHandler, // AIC default handler - AT91F_SpuriousHandler, // AIC spurious handler - 0); // Protect mode - - // Perform 8 End Of Interrupt Command to make sýre AIC will not Lock out nIRQ - for(i=0; i<8; i++) - AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC); - - AT91F_AIC_SetExceptionVector((unsigned int *)0x0C, AT91F_FetchAbort); - AT91F_AIC_SetExceptionVector((unsigned int *)0x10, AT91F_DataAbort); - AT91F_AIC_SetExceptionVector((unsigned int *)0x4, AT91F_UndefHandler); - - //Initialize SDRAM and Flash - AT91F_InitMemories(); - -} - diff --git a/target/linux/at91-2.6/image/dfboot/src/jump.S b/target/linux/at91-2.6/image/dfboot/src/jump.S deleted file mode 100644 index cc69311569..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/jump.S +++ /dev/null @@ -1,4 +0,0 @@ -.global Jump - -Jump: mov pc, r0 - diff --git a/target/linux/at91-2.6/image/dfboot/src/led.c b/target/linux/at91-2.6/image/dfboot/src/led.c deleted file mode 100644 index 40d49113c7..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/led.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2006 - * Atmel Nordic AB <www.atmel.com> - * Ulf Samuelsson <ulf@atmel.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <AT91RM9200.h> - -#define GREEN_LED AT91C_PIO_PB0 -#define YELLOW_LED AT91C_PIO_PB1 -#define RED_LED AT91C_PIO_PB2 - -void LED_set(unsigned int led) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_SODR = (led ^ 0x7) & 0x7; // All 0's => Set PIO high => OFF - PIOB->PIO_CODR = led & 0x7; // All 1's => Set PIO low => ON -} - -void green_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_CODR = GREEN_LED; - PIOB->PIO_CODR = (1 << 0); -} - -void yellow_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_CODR = YELLOW_LED; - PIOB->PIO_CODR = (1 << 1); -} - -void red_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_CODR = RED_LED; - PIOB->PIO_CODR = (1 << 2); -} - -void green_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_SODR = GREEN_LED; - PIOB->PIO_SODR = (1 << 0); -} - -void yellow_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_SODR = YELLOW_LED; - PIOB->PIO_SODR = (1 << 1); -} - -void red_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_SODR = RED_LED; - PIOB->PIO_SODR = (1 << 2); -} - -void LED_blink(unsigned int led) -{ - volatile int i,j; - for(i = 0; i < 5; i++) { - LED_set((1 << led)&0x7); - for(j= 0; j < 200000; j++); - LED_set(0); - for(j= 0; j < 200000; j++); - } -} - - -void LED_init (void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - AT91PS_PMC PMC = AT91C_BASE_PMC; - PMC->PMC_PCER = (1 << AT91C_ID_PIOB); // Enable PIOB clock - // Disable peripherals on LEDs - PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; - // Enable pins as outputs - PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; - // Turn all LEDs OFF - PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; -} diff --git a/target/linux/at91-2.6/image/dfboot/src/main.c b/target/linux/at91-2.6/image/dfboot/src/main.c deleted file mode 100644 index c0705dec60..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/main.c +++ /dev/null @@ -1,811 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : main.c - * Object : - * Creation : HIi 10/10/2003 - * Modif : HIi 15/06/2004 : add crc32 to verify the download - * from dataflash - * : HIi 21/09/2004 : Set first PLLA to 180Mhz and MCK to - * 60Mhz to speed up dataflash boot (15Mhz) - * : MLC 12/04/2005 : Modify SetPLL() to avoid errata - * : USA 30/12/2005 : Change to page Size 1056 - * Change startaddress to C0008400 - * Change SPI Speed to ~4 Mhz - * Add retry on CRC Error - *---------------------------------------------------------------------------- - */ -#include "config.h" -#include "stdio.h" -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" -#include "com.h" -#include "main.h" -#include "dataflash.h" -#include "AT91C_MCI_Device.h" - -#define DEBUGOUT -#define XMODEM -#define MEMDISP - -#ifdef PAGESZ_1056 -#define PAGESIZE 1056 -#else -#define PAGESIZE 1024 -#endif - -#define AT91C_SDRAM_START 0x20000000 -#define AT91C_BOOT_ADDR 0x21F00000 -#define AT91C_BOOT_SIZE 128*PAGESIZE -#ifdef PAGESZ_1056 -#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008400 -#else -#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008000 -#endif -#define AT91C_PLLA_VALUE 0x237A3E5A // crystal= 18.432MHz - fixes BRG error at 115kbps -//#define AT91C_PLLA_VALUE 0x2026BE04 // crystal= 18.432MHz -//#define AT91C_PLLA_VALUE 0x202CBE01 // crystal= 4MHz - - - -#define DISP_LINE_LEN 16 - -// Reason for boot failure -#define IMAGE_BAD_SIZE 0 -#define IMAGE_READ_FAILURE 1 -#define IMAGE_CRC_ERROR 2 -#define IMAGE_ERROR 3 -#define SUCCESS -1 - -/* prototypes*/ -extern void AT91F_ST_ASM_HANDLER(void); -extern void Jump(unsigned int addr); - -const char *menu_dataflash[] = { -#ifdef XMODEM - "1: P DFboot\n", - "2: P U-Boot\n", -#endif - "3: P SDCard\n", -#ifdef PAGESZ_1056 - "4: R UBOOT\n", -#else - "4: R UBOOT\n", -#endif -#ifdef XMODEM - "5: P DF [addr]\n", -#endif - "6: RD DF [addr]\n", - "7: E DF\n" -}; -#ifdef XMODEM -#define MAXMENU 7 -#else -#define MAXMENU 4 -#endif - -char message[20]; -#ifdef XMODEM -volatile char XmodemComplete = 0; -#endif -unsigned int StTick = 0; - -AT91S_RomBoot const *pAT91; -#ifdef XMODEM -AT91S_SBuffer sXmBuffer; -AT91S_SvcXmodem svcXmodem; -AT91S_Pipe xmodemPipe; -#endif -AT91S_CtlTempo ctlTempo; - - -//*-------------------------------------------------------------------------------------- -//* Function Name : GetTickCount() -//* Object : Return the number of systimer tick -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -unsigned int GetTickCount(void) -{ - return StTick; -} - -#ifdef XMODEM -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91_XmodemComplete() -//* Object : Perform the remap and jump to appli in RAM -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static void AT91_XmodemComplete(AT91S_PipeStatus status, void *pVoid) -{ - /* stop the Xmodem tempo */ - svcXmodem.tempo.Stop(&(svcXmodem.tempo)); - XmodemComplete = 1; -} - - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_XmodemProtocol(AT91S_PipeStatus status, void *pVoid) -//* Object : Xmodem dispatcher -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static void XmodemProtocol(AT91S_PipeStatus status, void *pVoid) -{ - AT91PS_SBuffer pSBuffer = (AT91PS_SBuffer) xmodemPipe.pBuffer->pChild; - AT91PS_USART pUsart = svcXmodem.pUsart; - - if (pSBuffer->szRdBuffer == 0) { - /* Start a tempo to wait the Xmodem protocol complete */ - svcXmodem.tempo.Start(&(svcXmodem.tempo), 10, 0, AT91_XmodemComplete, pUsart); - } -} -#endif - -//*-------------------------------------------------------------------------------------- -//* Function Name : irq1_c_handler() -//* Object : C Interrupt handler for Interrutp source 1 -//* Input Parameters : none -//* Output Parameters : none -//*-------------------------------------------------------------------------------------- -void AT91F_ST_HANDLER(void) -{ - volatile unsigned int csr = *AT91C_DBGU_CSR; -#ifdef XMODEM - unsigned int error; -#endif - - if (AT91C_BASE_ST->ST_SR & 0x01) { - StTick++; - ctlTempo.CtlTempoTick(&ctlTempo); - return; - } - -#ifdef XMODEM - error = AT91F_US_Error((AT91PS_USART)AT91C_BASE_DBGU); - if (csr & error) { - /* Stop previous Xmodem transmition*/ - *(AT91C_DBGU_CR) = AT91C_US_RSTSTA; - AT91F_US_DisableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_ENDRX); - AT91F_US_EnableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_RXRDY); - - } - - else if (csr & (AT91C_US_TXRDY | AT91C_US_ENDTX | AT91C_US_TXEMPTY | - AT91C_US_RXRDY | AT91C_US_ENDRX | AT91C_US_TIMEOUT | - AT91C_US_RXBUFF)) { - if ( !(svcXmodem.eot) ) - svcXmodem.Handler(&svcXmodem, csr); - } -#endif -} - - -//*----------------------------------------------------------------------------- -//* Function Name : AT91F_DisplayMenu() -//* Object : -//* Input Parameters : -//* Return value : -//*----------------------------------------------------------------------------- -static int AT91F_DisplayMenu(void) -{ - int i, mci_present = 0; - printf("\nDF LOADER %s %s %s\n",AT91C_VERSION,__DATE__,__TIME__); - AT91F_DataflashPrintInfo(); - mci_present = AT91F_MCI_Init(); - for(i = 0; i < MAXMENU; i++) { - puts(menu_dataflash[i]); - } - return mci_present; -} - - -//*----------------------------------------------------------------------------- -//* Function Name : AsciiToHex() -//* Object : ascii to hexa conversion -//* Input Parameters : -//* Return value : -//*----------------------------------------------------------------------------- -static unsigned int AsciiToHex(char *s, unsigned int *val) -{ - int n; - - *val=0; - - if(s[0] == '0' && ((s[1] == 'x') || (s[1] == 'X'))) - s+=2; - n = 0; - while((n < 8) && (s[n] !=0)) - { - *val <<= 4; - if ( (s[n] >= '0') && (s[n] <='9')) - *val += (s[n] - '0'); - else - if ((s[n] >= 'a') && (s[n] <='f')) - *val += (s[n] - 0x57); - else - if ((s[n] >= 'A') && (s[n] <='F')) - *val += (s[n] - 0x37); - else - return 0; - n++; - } - - return 1; -} - - -#ifdef MEMDISP -//*----------------------------------------------------------------------------- -//* Function Name : AT91F_MemoryDisplay() -//* Object : Display the content of the dataflash -//* Input Parameters : -//* Return value : -//*----------------------------------------------------------------------------- -static int AT91F_MemoryDisplay(unsigned int addr, unsigned int length) -{ - unsigned long i, nbytes, linebytes; - char *cp; -// unsigned int *uip; -// unsigned short *usp; - unsigned char *ucp; - char linebuf[DISP_LINE_LEN]; - -// nbytes = length * size; - nbytes = length; - do - { -// uip = (unsigned int *)linebuf; -// usp = (unsigned short *)linebuf; - ucp = (unsigned char *)linebuf; - - printf("%08x:", addr); - linebytes = (nbytes > DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; - if((addr & 0xF0000000) == 0x20000000) { - for(i = 0; i < linebytes; i ++) { - linebuf[i] = *(char *)(addr+i); - } - } else { - read_dataflash(addr, linebytes, linebuf); - } - for (i=0; i<linebytes; i++) - { -/* if (size == 4) - printf(" %08x", *uip++); - else if (size == 2) - printf(" %04x", *usp++); - else -*/ - printf(" %02x", *ucp++); -// addr += size; - addr++; - } - printf(" "); - cp = linebuf; - for (i=0; i<linebytes; i++) { - if ((*cp < 0x20) || (*cp > 0x7e)) - printf("."); - else - printf("%c", *cp); - cp++; - } - printf("\n"); - nbytes -= linebytes; - } while (nbytes > 0); - return 0; -} -#endif - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_SetPLL -//* Object : Set the PLLA to 180Mhz and Master clock to 60 Mhz -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static unsigned int AT91F_SetPLL(void) -{ - AT91_REG tmp; - AT91PS_PMC pPmc = AT91C_BASE_PMC; - AT91PS_CKGR pCkgr = AT91C_BASE_CKGR; - - pPmc->PMC_IDR = 0xFFFFFFFF; - - /* -Setup the PLL A */ - pCkgr->CKGR_PLLAR = AT91C_PLLA_VALUE; - - while (!(*AT91C_PMC_SR & AT91C_PMC_LOCKA)); - - /* - Switch Master Clock from PLLB to PLLA/3 */ - tmp = pPmc->PMC_MCKR; - /* See Atmel Errata #27 and #28 */ - if (tmp & 0x0000001C) { - tmp = (tmp & ~0x0000001C); - pPmc->PMC_MCKR = tmp; - while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)); - } - if (tmp != 0x00000202) { - pPmc->PMC_MCKR = 0x00000202; - if ((tmp & 0x00000003) != 0x00000002) - while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)); - } - - return 1; -} - - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_ResetRegisters -//* Object : Restore the initial state to registers -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static unsigned int AT91F_ResetRegisters(void) -{ - volatile int i = 0; - - /* set the PIOs in input*/ - /* This disables the UART output, so dont execute for now*/ - -#ifndef DEBUGOUT - *AT91C_PIOA_ODR = 0xFFFFFFFF; /* Disables all the output pins */ - *AT91C_PIOA_PER = 0xFFFFFFFF; /* Enables the PIO to control all the pins */ -#endif - - AT91F_AIC_DisableIt (AT91C_BASE_AIC, AT91C_ID_SYS); - /* close all peripheral clocks */ - -#ifndef DEBUGOUT - AT91C_BASE_PMC->PMC_PCDR = 0xFFFFFFFC; -#endif - /* Disable core interrupts and set supervisor mode */ - __asm__ ("msr CPSR_c, #0xDF"); //* ARM_MODE_SYS(0x1F) | I_BIT(0x80) | F_BIT(0x40) - /* Clear all the interrupts */ - *AT91C_AIC_ICCR = 0xffffffff; - - /* read the AIC_IVR and AIC_FVR */ - i = *AT91C_AIC_IVR; - i = *AT91C_AIC_FVR; - - /* write the end of interrupt control register */ - *AT91C_AIC_EOICR = 0; - - return 1; -} - - -static int AT91F_LoadBoot(void) -{ -// volatile unsigned int crc1 = 0, crc2 = 0; - volatile unsigned int SizeToDownload = 0x21400; - volatile unsigned int AddressToDownload = AT91C_BOOT_ADDR; - -#if 0 - /* Read vector 6 to extract size to load */ - if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, 32, - (char *)AddressToDownload) != AT91C_DATAFLASH_OK) - { - printf("Bad Code Size\n"); - return IMAGE_BAD_SIZE; - } - /* calculate the size to download */ - SizeToDownload = *(int *)(AddressToDownload + AT91C_OFFSET_VECT6); -#endif - -// printf("\nLoad UBOOT from dataflash[%x] to SDRAM[%x]\n", -// AT91C_BOOT_DATAFLASH_ADDR, AT91C_BOOT_ADDR); - if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, SizeToDownload + 8, - (char *)AddressToDownload) != AT91C_DATAFLASH_OK) - { - printf("F DF RD\n"); - return IMAGE_READ_FAILURE; - } -#if 0 - pAT91->CRC32((const unsigned char *)AT91C_BOOT_ADDR, - (unsigned int)SizeToDownload , (unsigned int *)&crc2); - crc1 = (int)(*(char *)(AddressToDownload + SizeToDownload)) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24); - - /* Restore the value of Vector 6 */ - *(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = - *(int *)(AddressToDownload + SizeToDownload + 4); - - if (crc1 != crc2) { - printf("DF CRC bad %x != %x\n",crc1,crc2); - return IMAGE_CRC_ERROR; - } -#endif - return SUCCESS; -} - -static int AT91F_StartBoot(void) -{ - int sts; - if((sts = AT91F_LoadBoot()) != SUCCESS) return sts; -// printf("\n"); -// printf("PLLA[180MHz], MCK[60Mhz] ==> Start UBOOT\n"); - if (AT91F_ResetRegisters()) - { - printf("Jump"); - Jump(AT91C_BOOT_ADDR); -// LED_blink(0); - } - return IMAGE_ERROR; -} - -#if 0 -static void AT91F_RepeatedStartBoot(void) -{ - int i; - for(i = 0; i < CRC_RETRIES; i++) { - if(AT91F_StartBoot() != IMAGE_CRC_ERROR){ -// LED_blink(1); - return; - } - } - return; -} -#endif - -#define TRUE 1 -#define FALSE 0 -#define TRX_MAGIC 0x30524448 /* "HDR0" */ -#define TRX_VERSION 1 - -struct trx_header { - unsigned int magic; - unsigned int len; - unsigned int crc32; - unsigned int flag_version; - unsigned int offsets[3]; -}; - -#define AT91C_MCI_TIMEOUT 1000000 - -extern AT91S_MciDevice MCI_Device; -extern void AT91F_MCIDeviceWaitReady(unsigned int); -extern int AT91F_MCI_ReadBlockSwab(AT91PS_MciDevice, int, unsigned int *, int); - -int Program_From_MCI(void) -{ - int i; - unsigned int Max_Read_DataBlock_Length; - int block = 0; - int buffer = AT91C_DOWNLOAD_BASE_ADDRESS; - int bufpos = AT91C_DOWNLOAD_BASE_ADDRESS; - int NbPage = 0; - struct trx_header *p; - - p = (struct trx_header *)bufpos; - - Max_Read_DataBlock_Length = MCI_Device.pMCI_DeviceFeatures->Max_Read_DataBlock_Length; - - AT91F_MCIDeviceWaitReady(AT91C_MCI_TIMEOUT); - - AT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length); - - if (p->magic != TRX_MAGIC) { - printf("Inv IMG 0x%08x\n", p->magic); - return FALSE; - } - - printf("RDSD"); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC8 | AT91C_PIO_PC14; - for (i=0; i<(p->len/512); i++) { - AT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length); - block++; - bufpos += Max_Read_DataBlock_Length; - } - - NbPage = 0; - i = dataflash_info[0].Device.pages_number; - while(i >>= 1) - NbPage++; - i = ((p->offsets[1] - p->offsets[0])/ 512) + 1 + (NbPage << 13) + (dataflash_info[0].Device.pages_size << 17); - *(int *)(buffer + p->offsets[0] + AT91C_OFFSET_VECT6) = i; - - printf(" WDFB"); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC14; - AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8; - write_dataflash(0xc0000000, buffer + p->offsets[0], p->offsets[1] - p->offsets[0]); - printf(" WUB"); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15; - AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8 | AT91C_PIO_PC14; - write_dataflash(0xc0008000, buffer + p->offsets[1], p->offsets[2] - p->offsets[1]); - printf(" WKRFS"); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC15; - AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC14; - write_dataflash(0xc0042000, buffer + p->offsets[2], p->len - p->offsets[2]); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC14; - AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC15; - return TRUE; -} - -//*---------------------------------------------------------------------------- -//* Function Name : main -//* Object : Main function -//* Input Parameters : none -//* Output Parameters : True -//*---------------------------------------------------------------------------- -int main(void) -{ -#ifdef XMODEM - AT91PS_Buffer pXmBuffer; - AT91PS_SvcComm pSvcXmodem; -#endif - AT91S_SvcTempo svcBootTempo; // Link to a AT91S_Tempo object - unsigned int ix; - volatile unsigned int AddressToDownload, SizeToDownload; - unsigned int DeviceAddress = 0; - char command = 0; -#ifdef XMODEM - volatile int i = 0; - unsigned int crc1 = 0, crc2 = 0; - volatile int device; - int NbPage; -#endif - volatile int Nb_Device = 0; - int mci_present = 0; - - pAT91 = AT91C_ROM_BOOT_ADDRESS; - - if (!AT91F_SetPLL()) - { - printf("F SetPLL"); - while(1); - } - - at91_init_uarts(); - - /* Tempo Initialisation */ - pAT91->OpenCtlTempo(&ctlTempo, (void *) &(pAT91->SYSTIMER_DESC)); - ctlTempo.CtlTempoStart((void *) &(pAT91->SYSTIMER_DESC)); - - // Attach the tempo to a tempo controler - ctlTempo.CtlTempoCreate(&ctlTempo, &svcBootTempo); -// LED_init(); -// LED_blink(2); - -#ifdef XMODEM - /* Xmodem Initialisation */ - pXmBuffer = pAT91->OpenSBuffer(&sXmBuffer); - pSvcXmodem = pAT91->OpenSvcXmodem(&svcXmodem, - (AT91PS_USART)AT91C_BASE_DBGU, &ctlTempo); - pAT91->OpenPipe(&xmodemPipe, pSvcXmodem, pXmBuffer); -#endif - - /* System Timer initialization */ - AT91F_AIC_ConfigureIt( - AT91C_BASE_AIC, // AIC base address - AT91C_ID_SYS, // System peripheral ID - AT91C_AIC_PRIOR_HIGHEST, // Max priority - AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, // Level sensitive - AT91F_ST_ASM_HANDLER - ); - /* Enable ST interrupt */ - AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS); - -#ifndef PRODTEST - /* Start tempo to start Boot in a delay of - * AT91C_DELAY_TO_BOOT sec if no key pressed */ - svcBootTempo.Start(&svcBootTempo, AT91C_DELAY_TO_BOOT, - 0, AT91F_StartBoot, NULL); -#endif - - while(1) - { - while(command == 0) - { - AddressToDownload = AT91C_DOWNLOAD_BASE_ADDRESS; - SizeToDownload = AT91C_DOWNLOAD_MAX_SIZE; - DeviceAddress = 0; - - /* try to detect Dataflash */ - if (!Nb_Device) - Nb_Device = AT91F_DataflashInit(); - - mci_present = AT91F_DisplayMenu(); - -#ifdef PRODTEST - if (mci_present) { - if (Program_From_MCI()) - AT91F_StartBoot(); - } -#endif - - message[0] = 0; - AT91F_ReadLine ("Enter: ", message); - -#ifndef PRODTEST - /* stop tempo ==> stop autoboot */ - svcBootTempo.Stop(&svcBootTempo); -#endif - - command = message[0]; - for(ix = 1; (message[ix] == ' ') && (ix < 12); ix++); // Skip some whitespace - - if(!AsciiToHex(&message[ix], &DeviceAddress) ) - DeviceAddress = 0; // Illegal DeviceAddress - - switch(command) - { -#ifdef XMODEM - case '1': - case '2': - case '5': - if(command == '1') { - DeviceAddress = 0xC0000000; -// printf("Download DataflashBoot.bin to [0x%x]\n", DeviceAddress); - } else if(command == '2') { - DeviceAddress = AT91C_BOOT_DATAFLASH_ADDR; -// printf("Download u-boot.bin to [0x%x]\n", DeviceAddress); - } else { -// printf("Download Dataflash to [0x%x]\n", DeviceAddress); - } - switch(DeviceAddress & 0xFF000000) - { - case CFG_DATAFLASH_LOGIC_ADDR_CS0: - if (dataflash_info[0].id == 0){ - printf("No DF"); - AT91F_WaitKeyPressed(); - command = 0; - } - - device = 0; - break; - - case CFG_DATAFLASH_LOGIC_ADDR_CS3: - if (dataflash_info[1].id == 0){ - printf("No DF"); - AT91F_WaitKeyPressed(); - command = 0; - } - device = 1; - break; - - default: - command = 0; - break; - } - break; -#endif - - case '3': - if (mci_present) - Program_From_MCI(); - command = 0; - break; - - case '4': - AT91F_StartBoot(); - command = 0; - break; - -#ifdef MEMDISP - case '6': - do - { - AT91F_MemoryDisplay(DeviceAddress, 256); - AT91F_ReadLine (NULL, message); - DeviceAddress += 0x100; - } - while(message[0] == '\0'); - command = 0; - break; -#endif - - case '7': - switch(DeviceAddress & 0xFF000000) - { - case CFG_DATAFLASH_LOGIC_ADDR_CS0: - break; - case CFG_DATAFLASH_LOGIC_ADDR_CS3: - break; - default: - command = 0; - break; - } - - if (command != 0) { - AT91F_ReadLine ("RDY ERA\nSure?", - message); - if(message[0] == 'Y' || message[0] == 'y') { - erase_dataflash(DeviceAddress & 0xFF000000); -// printf("Erase complete\n\n"); - } -// else -// printf("Erase aborted\n"); - } - command = 0; - - break; - - default: - command = 0; - break; - } - } -#ifdef XMODEM - for(i = 0; i <= AT91C_DOWNLOAD_MAX_SIZE; i++) - *(unsigned char *)(AddressToDownload + i) = 0; - - xmodemPipe.Read(&xmodemPipe, (char *)AddressToDownload, - SizeToDownload, XmodemProtocol, 0); - while(XmodemComplete !=1); - SizeToDownload = (unsigned int)((svcXmodem.pData) - - (unsigned int)AddressToDownload); - - /* Modification of vector 6 */ - if ((DeviceAddress == CFG_DATAFLASH_LOGIC_ADDR_CS0)) { - // Vector 6 must be compliant to the BootRom description (ref Datasheet) - NbPage = 0; - i = dataflash_info[device].Device.pages_number; - while(i >>= 1) - NbPage++; - i = (SizeToDownload / 512)+1 + (NbPage << 13) + - (dataflash_info[device].Device.pages_size << 17); //+4 to add crc32 - SizeToDownload = 512 * (i &0xFF); - } - else - { - /* Save the contents of vector 6 ==> will be restored - * at boot time (AT91F_StartBoot) */ - *(int *)(AddressToDownload + SizeToDownload + 4) = - *(int *)(AddressToDownload + AT91C_OFFSET_VECT6); - /* Modify Vector 6 to contain the size of the - * file to copy (Dataflash -> SDRAM)*/ - i = SizeToDownload; - } - - *(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = i; -// printf("\nModification of Arm Vector 6 :%x\n", i); - -// printf("\nWrite %d bytes in DataFlash [0x%x]\n",SizeToDownload, DeviceAddress); - crc1 = 0; - pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc1); - - /* Add the crc32 at the end of the code */ - *(char *)(AddressToDownload + SizeToDownload) = (char)(crc1 & 0x000000FF); - *(char *)(AddressToDownload + SizeToDownload + 1) = (char)((crc1 & 0x0000FF00) >> 8); - *(char *)(AddressToDownload + SizeToDownload + 2) = (char)((crc1 & 0x00FF0000) >> 16); - *(char *)(AddressToDownload + SizeToDownload + 3) = (char)((crc1 & 0xFF000000) >> 24); - - /* write dataflash */ - write_dataflash (DeviceAddress, AddressToDownload, (SizeToDownload + 8)); - - /* clear the buffer before read */ - for(i=0; i <= SizeToDownload; i++) - *(unsigned char *)(AddressToDownload + i) = 0; - - /* Read dataflash to check the validity of the data */ - read_dataflash (DeviceAddress, (SizeToDownload + 4), (char *)(AddressToDownload)); - - printf("VFY: "); - crc2 = 0; - - pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc2); - crc1 = (int)(*(char *)(AddressToDownload + SizeToDownload)) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24); - - if (crc1 != crc2) - printf("ERR"); - else - printf("OK"); - - command = 0; - XmodemComplete = 0; - AT91F_WaitKeyPressed(); -#endif - } -} - diff --git a/target/linux/at91-2.6/image/dfboot/src/main.h b/target/linux/at91-2.6/image/dfboot/src/main.h deleted file mode 100644 index a8cd325ca9..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/main.h +++ /dev/null @@ -1,43 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : main.h -//* Object : -//* -//* 1.0 27/03/03 HIi : Creation -//* 1.01 03/05/04 HIi : AT9C_VERSION incremented to 1.01 -//* 1.02 15/06/04 HIi : AT9C_VERSION incremented to 1.02 ==> -//* Add crc32 to verify dataflash download -//* 1.03 18/04/05 MLC : AT91C_VERSION incremented to 1.03g -//* Repeat boot on CRC Failure -//* Change Page Size to 1056 -//* Reduce SPI speed to 4 Mbit -//* Change U-Boot boot address to a 1056 byte page boundary -//* 1.04 30/04/05 USA : AT91C_VERSION incremented to 1.04 -//* 1.05 07/08/06 USA : AT91C_VERSION incremented to 1.05 -//* Will only support loading Dataflashboot.bin and U-Boot -//*---------------------------------------------------------------------------- - -#ifndef main_h -#define main_h - -#include "embedded_services.h" - -#define AT91C_DOWNLOAD_BASE_ADDRESS 0x20000000 -#define AT91C_DOWNLOAD_MAX_SIZE 0x00040000 - -#define AT91C_OFFSET_VECT6 0x14 //* Offset for ARM vector 6 - -#define AT91C_VERSION "VER 1.05" - - -// Global variables and functions definition -extern unsigned int GetTickCount(void); -#endif - diff --git a/target/linux/at91-2.6/image/dfboot/src/mci_device.c b/target/linux/at91-2.6/image/dfboot/src/mci_device.c deleted file mode 100644 index cce74a3ae8..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/mci_device.c +++ /dev/null @@ -1,743 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : mci_device.c -//* Object : TEST DataFlash Functions -//* Creation : FB 26/11/2002 -//* -//*---------------------------------------------------------------------------- - -#include <AT91C_MCI_Device.h> -#include "stdio.h" - -#define AT91C_MCI_TIMEOUT 1000000 /* For AT91F_MCIDeviceWaitReady */ -#define BUFFER_SIZE_MCI_DEVICE 512 -#define MASTER_CLOCK 60000000 -#define FALSE 0 -#define TRUE 1 - -//* External Functions -extern void AT91F_ASM_MCI_Handler(void); -//* Global Variables -AT91S_MciDeviceFeatures MCI_Device_Features; -AT91S_MciDeviceDesc MCI_Device_Desc; -AT91S_MciDevice MCI_Device; - -#undef ENABLE_WRITE -#undef MMC - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SendCommand -//* \brief Generic function to send a command to the MMC or SDCard -//*---------------------------------------------------------------------------- -int AT91F_MCI_SendCommand ( - AT91PS_MciDevice pMCI_Device, - unsigned int Cmd, - unsigned int Arg) -{ - unsigned int error,status; - //unsigned int tick=0; - - // Send the command - AT91C_BASE_MCI->MCI_ARGR = Arg; - AT91C_BASE_MCI->MCI_CMDR = Cmd; - - // wait for CMDRDY Status flag to read the response - do - { - status = AT91C_BASE_MCI->MCI_SR; - //tick++; - } - while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) ); - - // Test error ==> if crc error and response R3 ==> don't check error - error = (AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR; - if(error != 0 ) - { - // if the command is SEND_OP_COND the CRC error flag is always present (cf : R3 response) - if ( (Cmd != AT91C_SDCARD_APP_OP_COND_CMD) && (Cmd != AT91C_MMC_SEND_OP_COND_CMD) ) - return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR); - else - { - if (error != AT91C_MCI_RCRCE) - return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR); - } - } - return AT91C_CMD_SEND_OK; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_SendAppCommand -//* \brief Specific function to send a specific command to the SDCard -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_SendAppCommand ( - AT91PS_MciDevice pMCI_Device, - unsigned int Cmd_App, - unsigned int Arg ) -{ - unsigned int status; - //unsigned int tick=0; - - // Send the CMD55 for application specific command - AT91C_BASE_MCI->MCI_ARGR = (pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address << 16 ); - AT91C_BASE_MCI->MCI_CMDR = AT91C_APP_CMD; - - // wait for CMDRDY Status flag to read the response - do - { - status = AT91C_BASE_MCI->MCI_SR; - //tick++; - } - while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) ); - - // if an error occurs - if (((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR) != 0 ) - return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR); - - // check if it is a specific command and then send the command - if ( (Cmd_App && AT91C_SDCARD_APP_ALL_CMD) == 0) - return AT91C_CMD_SEND_ERROR; - - return( AT91F_MCI_SendCommand(pMCI_Device,Cmd_App,Arg) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetStatus -//* \brief Addressed card sends its status register -//*---------------------------------------------------------------------------- -int AT91F_MCI_GetStatus(AT91PS_MciDevice pMCI_Device,unsigned int relative_card_address) -{ - if (AT91F_MCI_SendCommand(pMCI_Device, - AT91C_SEND_STATUS_CMD, - relative_card_address <<16) == AT91C_CMD_SEND_OK) - return (AT91C_BASE_MCI->MCI_RSPR[0]); - - return AT91C_CMD_SEND_ERROR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Device_Handler -//* \brief MCI C interrupt handler -//*---------------------------------------------------------------------------- -void AT91F_MCI_Device_Handler( - AT91PS_MciDevice pMCI_Device, - unsigned int status) -{ - // If End of Tx Buffer Empty interrupt occurred - if ( status & AT91C_MCI_TXBUFE ) - { - AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_TXBUFE; - AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTDIS; - - pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE; - } // End of if AT91C_MCI_TXBUFF - - // If End of Rx Buffer Full interrupt occurred - if ( status & AT91C_MCI_RXBUFF ) - { - AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_RXBUFF; - AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTDIS; - - pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE; - } // End of if AT91C_MCI_RXBUFF - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Handler -//* \brief MCI Handler -//*---------------------------------------------------------------------------- -void AT91F_MCI_Handler(void) -{ - int status; - - status = ( AT91C_BASE_MCI->MCI_SR & AT91C_BASE_MCI->MCI_IMR ); - - AT91F_MCI_Device_Handler(&MCI_Device,status); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_ReadBlock -//* \brief Read an ENTIRE block or PARTIAL block -//*---------------------------------------------------------------------------- -int AT91F_MCI_ReadBlock( - AT91PS_MciDevice pMCI_Device, - int src, - unsigned int *dataBuffer, - int sizeToRead ) -{ - //////////////////////////////////////////////////////////////////////////////////////////// - if(pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE) - return AT91C_READ_ERROR; - - if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA) - return AT91C_READ_ERROR; - - if ( (src + sizeToRead) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity ) - return AT91C_READ_ERROR; - - // If source does not fit a begin of a block - if ( (src % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 ) - return AT91C_READ_ERROR; - - // Test if the MMC supports Partial Read Block - // ALWAYS SUPPORTED IN SD Memory Card - if( (sizeToRead < pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) - && (pMCI_Device->pMCI_DeviceFeatures->Read_Partial == 0x00) ) - return AT91C_READ_ERROR; - - if( sizeToRead > pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) - return AT91C_READ_ERROR; - //////////////////////////////////////////////////////////////////////////////////////////// - - // Init Mode Register - AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length << 16) | AT91C_MCI_PDCMODE); - - if (sizeToRead %4) - sizeToRead = (sizeToRead /4)+1; - else - sizeToRead = sizeToRead/4; - - AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); - AT91C_BASE_PDC_MCI->PDC_RPR = (unsigned int)dataBuffer; - AT91C_BASE_PDC_MCI->PDC_RCR = sizeToRead; - - // Send the Read single block command - if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_READ_SINGLE_BLOCK_CMD, src) != AT91C_CMD_SEND_OK ) - return AT91C_READ_ERROR; - - pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_RX_SINGLE_BLOCK; - - // Enable AT91C_MCI_RXBUFF Interrupt - AT91C_BASE_MCI->MCI_IER = AT91C_MCI_RXBUFF; - - // (PDC) Receiver Transfer Enable - AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTEN; - - return AT91C_READ_OK; -} - - -#ifdef ENABLE_WRITE -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_WriteBlock -//* \brief Write an ENTIRE block but not always PARTIAL block !!! -//*---------------------------------------------------------------------------- -int AT91F_MCI_WriteBlock( - AT91PS_MciDevice pMCI_Device, - int dest, - unsigned int *dataBuffer, - int sizeToWrite ) -{ - //////////////////////////////////////////////////////////////////////////////////////////// - if( pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE) - return AT91C_WRITE_ERROR; - - if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA) - return AT91C_WRITE_ERROR; - - if ( (dest + sizeToWrite) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity ) - return AT91C_WRITE_ERROR; - - // If source does not fit a begin of a block - if ( (dest % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 ) - return AT91C_WRITE_ERROR; - - // Test if the MMC supports Partial Write Block - if( (sizeToWrite < pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length) - && (pMCI_Device->pMCI_DeviceFeatures->Write_Partial == 0x00) ) - return AT91C_WRITE_ERROR; - - if( sizeToWrite > pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length ) - return AT91C_WRITE_ERROR; - //////////////////////////////////////////////////////////////////////////////////////////// - - // Init Mode Register - AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length << 16) | AT91C_MCI_PDCMODE); - - if (sizeToWrite %4) - sizeToWrite = (sizeToWrite /4)+1; - else - sizeToWrite = sizeToWrite/4; - - // Init PDC for write sequence - AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); - AT91C_BASE_PDC_MCI->PDC_TPR = (unsigned int) dataBuffer; - AT91C_BASE_PDC_MCI->PDC_TCR = sizeToWrite; - - // Send the write single block command - if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_WRITE_BLOCK_CMD, dest) != AT91C_CMD_SEND_OK) - return AT91C_WRITE_ERROR; - - pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_TX_SINGLE_BLOCK; - - // Enable AT91C_MCI_TXBUFE Interrupt - AT91C_BASE_MCI->MCI_IER = AT91C_MCI_TXBUFE; - - // Enables TX for PDC transfert requests - AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTEN; - - return AT91C_WRITE_OK; -} -#endif - -#ifdef MMC -//*------------------------------------------------------------------------------------------------------------ -//* \fn AT91F_MCI_MMC_SelectCard -//* \brief Toggles a card between the Stand_by and Transfer states or between Programming and Disconnect states -//*------------------------------------------------------------------------------------------------------------ -int AT91F_MCI_MMC_SelectCard(AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address) -{ - int status; - - //* Check if the MMC card chosen is already the selected one - status = AT91F_MCI_GetStatus(pMCI_Device,relative_card_address); - - if (status < 0) - return AT91C_CARD_SELECTED_ERROR; - - if ((status & AT91C_SR_CARD_SELECTED) == AT91C_SR_CARD_SELECTED) - return AT91C_CARD_SELECTED_OK; - - //* Search for the MMC Card to be selected, status = the Corresponding Device Number - status = 0; - while( (pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address != relative_card_address) - && (status < AT91C_MAX_MCI_CARDS) ) - status++; - - if (status > AT91C_MAX_MCI_CARDS) - return AT91C_CARD_SELECTED_ERROR; - - if (AT91F_MCI_SendCommand( pMCI_Device, - AT91C_SEL_DESEL_CARD_CMD, - pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address << 16) == AT91C_CMD_SEND_OK) - return AT91C_CARD_SELECTED_OK; - return AT91C_CARD_SELECTED_ERROR; -} -#endif - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetCSD -//* \brief Asks to the specified card to send its CSD -//*---------------------------------------------------------------------------- -int AT91F_MCI_GetCSD (AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address , unsigned int * response) -{ - - if(AT91F_MCI_SendCommand(pMCI_Device, - AT91C_SEND_CSD_CMD, - (relative_card_address << 16)) != AT91C_CMD_SEND_OK) - return AT91C_CMD_SEND_ERROR; - - response[0] = AT91C_BASE_MCI->MCI_RSPR[0]; - response[1] = AT91C_BASE_MCI->MCI_RSPR[1]; - response[2] = AT91C_BASE_MCI->MCI_RSPR[2]; - response[3] = AT91C_BASE_MCI->MCI_RSPR[3]; - - return AT91C_CMD_SEND_OK; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SetBlocklength -//* \brief Select a block length for all following block commands (R/W) -//*---------------------------------------------------------------------------- -int AT91F_MCI_SetBlocklength(AT91PS_MciDevice pMCI_Device,unsigned int length) -{ - return( AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_BLOCKLEN_CMD, length) ); -} - -#ifdef MMC -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_MMC_GetAllOCR -//* \brief Asks to all cards to send their operations conditions -//*---------------------------------------------------------------------------- -int AT91F_MCI_MMC_GetAllOCR (AT91PS_MciDevice pMCI_Device) -{ - unsigned int response =0x0; - - while(1) - { - response = AT91F_MCI_SendCommand(pMCI_Device, - AT91C_MMC_SEND_OP_COND_CMD, - AT91C_MMC_HOST_VOLTAGE_RANGE); - if (response != AT91C_CMD_SEND_OK) - return AT91C_INIT_ERROR; - - response = AT91C_BASE_MCI->MCI_RSPR[0]; - - if ( (response & AT91C_CARD_POWER_UP_BUSY) == AT91C_CARD_POWER_UP_BUSY) - return(response); - } -} -#endif - -#ifdef MMC -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_MMC_GetAllCID -//* \brief Asks to the MMC on the chosen slot to send its CID -//*---------------------------------------------------------------------------- -int AT91F_MCI_MMC_GetAllCID (AT91PS_MciDevice pMCI_Device, unsigned int *response) -{ - int Nb_Cards_Found=-1; - - while(1) - { - if(AT91F_MCI_SendCommand(pMCI_Device, - AT91C_MMC_ALL_SEND_CID_CMD, - AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK) - return Nb_Cards_Found; - else - { - Nb_Cards_Found = 0; - //* Assignation of the relative address to the MMC CARD - pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Relative_Card_Address = Nb_Cards_Found + AT91C_FIRST_RCA; - //* Set the insert flag - pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Card_Inserted = AT91C_MMC_CARD_INSERTED; - - if (AT91F_MCI_SendCommand(pMCI_Device, - AT91C_MMC_SET_RELATIVE_ADDR_CMD, - (Nb_Cards_Found + AT91C_FIRST_RCA) << 16) != AT91C_CMD_SEND_OK) - return AT91C_CMD_SEND_ERROR; - - //* If no error during assignation address ==> Increment Nb_cards_Found - Nb_Cards_Found++ ; - } - } -} -#endif -#ifdef MMC -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_MMC_Init -//* \brief Return the MMC initialisation status -//*---------------------------------------------------------------------------- -int AT91F_MCI_MMC_Init (AT91PS_MciDevice pMCI_Device) -{ - unsigned int tab_response[4]; - unsigned int mult,blocknr; - unsigned int i,Nb_Cards_Found=0; - - //* Resets all MMC Cards in Idle state - AT91F_MCI_SendCommand(pMCI_Device, AT91C_MMC_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT); - - if(AT91F_MCI_MMC_GetAllOCR(pMCI_Device) == AT91C_INIT_ERROR) - return AT91C_INIT_ERROR; - - Nb_Cards_Found = AT91F_MCI_MMC_GetAllCID(pMCI_Device,tab_response); - if (Nb_Cards_Found != AT91C_CMD_SEND_ERROR) - { - //* Set the Mode Register - AT91C_BASE_MCI->MCI_MR = AT91C_MCI_MR_PDCMODE; - - for(i = 0; i < Nb_Cards_Found; i++) - { - if (AT91F_MCI_GetCSD(pMCI_Device, - pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address, - tab_response) != AT91C_CMD_SEND_OK) - pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address = 0; - else - { - pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M ); - pMCI_Device->pMCI_DeviceFeatures[i].Max_Write_DataBlock_Length = 1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M ); - pMCI_Device->pMCI_DeviceFeatures[i].Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v22_SECT_SIZE_S) & AT91C_CSD_v22_SECT_SIZE_M ); - pMCI_Device->pMCI_DeviceFeatures[i].Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M; - pMCI_Device->pMCI_DeviceFeatures[i].Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M; - - // None in MMC specification version 2.2 - pMCI_Device->pMCI_DeviceFeatures[i].Erase_Block_Enable = 0; - - pMCI_Device->pMCI_DeviceFeatures[i].Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M; - pMCI_Device->pMCI_DeviceFeatures[i].Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M; - - //// Compute Memory Capacity - // compute MULT - mult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 ); - // compute MSB of C_SIZE - blocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2; - // compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR - blocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 ); - - pMCI_Device->pMCI_DeviceFeatures[i].Memory_Capacity = pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length * blocknr; - //// End of Compute Memory Capacity - - } // end of else - } // end of for - - return AT91C_INIT_OK; - } // end of if - - return AT91C_INIT_ERROR; -} -#endif - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_GetOCR -//* \brief Asks to all cards to send their operations conditions -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_GetOCR (AT91PS_MciDevice pMCI_Device) -{ - unsigned int response =0x0; - - // The RCA to be used for CMD55 in Idle state shall be the card's default RCA=0x0000. - pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = 0x0; - - while( (response & AT91C_CARD_POWER_UP_BUSY) != AT91C_CARD_POWER_UP_BUSY ) - { - response = AT91F_MCI_SDCard_SendAppCommand(pMCI_Device, - AT91C_SDCARD_APP_OP_COND_CMD, - AT91C_MMC_HOST_VOLTAGE_RANGE); - if (response != AT91C_CMD_SEND_OK) - return AT91C_INIT_ERROR; - - response = AT91C_BASE_MCI->MCI_RSPR[0]; - } - - return(AT91C_BASE_MCI->MCI_RSPR[0]); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_GetCID -//* \brief Asks to the SDCard on the chosen slot to send its CID -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_GetCID (AT91PS_MciDevice pMCI_Device, unsigned int *response) -{ - if(AT91F_MCI_SendCommand(pMCI_Device, - AT91C_ALL_SEND_CID_CMD, - AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK) - return AT91C_CMD_SEND_ERROR; - - response[0] = AT91C_BASE_MCI->MCI_RSPR[0]; - response[1] = AT91C_BASE_MCI->MCI_RSPR[1]; - response[2] = AT91C_BASE_MCI->MCI_RSPR[2]; - response[3] = AT91C_BASE_MCI->MCI_RSPR[3]; - - return AT91C_CMD_SEND_OK; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_SetBusWidth -//* \brief Set bus width for SDCard -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_SetBusWidth(AT91PS_MciDevice pMCI_Device) -{ - volatile int ret_value; - char bus_width; - - do - { - ret_value =AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address); - } - while((ret_value > 0) && ((ret_value & AT91C_SR_READY_FOR_DATA) == 0)); - - // Select Card - AT91F_MCI_SendCommand(pMCI_Device, - AT91C_SEL_DESEL_CARD_CMD, - (pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address)<<16); - - // Set bus width for Sdcard - if(pMCI_Device->pMCI_DeviceDesc->SDCard_bus_width == AT91C_MCI_SCDBUS) - bus_width = AT91C_BUS_WIDTH_4BITS; - else bus_width = AT91C_BUS_WIDTH_1BIT; - - if (AT91F_MCI_SDCard_SendAppCommand(pMCI_Device,AT91C_SDCARD_SET_BUS_WIDTH_CMD,bus_width) != AT91C_CMD_SEND_OK) - return AT91C_CMD_SEND_ERROR; - - return AT91C_CMD_SEND_OK; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_Init -//* \brief Return the SDCard initialisation status -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_Init (AT91PS_MciDevice pMCI_Device) -{ - unsigned int tab_response[4]; - unsigned int mult,blocknr; - - AT91F_MCI_SendCommand(pMCI_Device, AT91C_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT); - - if(AT91F_MCI_SDCard_GetOCR(pMCI_Device) == AT91C_INIT_ERROR) - return AT91C_INIT_ERROR; - - if (AT91F_MCI_SDCard_GetCID(pMCI_Device,tab_response) == AT91C_CMD_SEND_OK) - { - pMCI_Device->pMCI_DeviceFeatures->Card_Inserted = AT91C_SD_CARD_INSERTED; - - if (AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_RELATIVE_ADDR_CMD, 0) == AT91C_CMD_SEND_OK) - { - pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = (AT91C_BASE_MCI->MCI_RSPR[0] >> 16); - if (AT91F_MCI_GetCSD(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address,tab_response) == AT91C_CMD_SEND_OK) - { - pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M ); - pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length = 1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M ); - pMCI_Device->pMCI_DeviceFeatures->Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v21_SECT_SIZE_S) & AT91C_CSD_v21_SECT_SIZE_M ); - pMCI_Device->pMCI_DeviceFeatures->Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M; - pMCI_Device->pMCI_DeviceFeatures->Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M; - pMCI_Device->pMCI_DeviceFeatures->Erase_Block_Enable = (tab_response[3] >> AT91C_CSD_v21_ER_BLEN_EN_S) & AT91C_CSD_v21_ER_BLEN_EN_M; - pMCI_Device->pMCI_DeviceFeatures->Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M; - pMCI_Device->pMCI_DeviceFeatures->Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M; - - //// Compute Memory Capacity - // compute MULT - mult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 ); - // compute MSB of C_SIZE - blocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2; - // compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR - blocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 ); - - pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity = pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length * blocknr; - //// End of Compute Memory Capacity - printf("SD-Card: %d Bytes\n\r", pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity); - - if( AT91F_MCI_SDCard_SetBusWidth(pMCI_Device) == AT91C_CMD_SEND_OK ) - { - if (AT91F_MCI_SetBlocklength(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) == AT91C_CMD_SEND_OK) - return AT91C_INIT_OK; - } - } - } - } - return AT91C_INIT_ERROR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CfgDevice -//* \brief This function is used to initialise MMC or SDCard Features -//*---------------------------------------------------------------------------- -void AT91F_CfgDevice(void) -{ - // Init Device Structure - - MCI_Device_Features.Relative_Card_Address = 0; - MCI_Device_Features.Card_Inserted = AT91C_CARD_REMOVED; - MCI_Device_Features.Max_Read_DataBlock_Length = 0; - MCI_Device_Features.Max_Write_DataBlock_Length = 0; - MCI_Device_Features.Read_Partial = 0; - MCI_Device_Features.Write_Partial = 0; - MCI_Device_Features.Erase_Block_Enable = 0; - MCI_Device_Features.Sector_Size = 0; - MCI_Device_Features.Memory_Capacity = 0; - - MCI_Device_Desc.state = AT91C_MCI_IDLE; - MCI_Device_Desc.SDCard_bus_width = AT91C_MCI_SCDBUS; - - // Init AT91S_DataFlash Global Structure, by default AT45DB choosen !!! - MCI_Device.pMCI_DeviceDesc = &MCI_Device_Desc; - MCI_Device.pMCI_DeviceFeatures = &MCI_Device_Features; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Init -//* \brief Initialsise Card -//*---------------------------------------------------------------------------- -int AT91F_MCI_Init(void) -{ - -/////////////////////////////////////////////////////////////////////////////////////////// -// MCI Init : common to MMC and SDCard -/////////////////////////////////////////////////////////////////////////////////////////// - - // Set up PIO SDC_TYPE to switch on MMC/SDCard and not DataFlash Card - AT91F_PIO_CfgOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7); - AT91F_PIO_SetOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7); - - // Init MCI for MMC and SDCard interface - AT91F_MCI_CfgPIO(); - AT91F_MCI_CfgPMC(); - AT91F_PDC_Open(AT91C_BASE_PDC_MCI); - - // Disable all the interrupts - AT91C_BASE_MCI->MCI_IDR = 0xFFFFFFFF; - - // Init MCI Device Structures - AT91F_CfgDevice(); - - // Configure MCI interrupt - AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, - AT91C_ID_MCI, - AT91C_AIC_PRIOR_HIGHEST, - AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, - AT91F_ASM_MCI_Handler); - - // Enable MCI interrupt - AT91F_AIC_EnableIt(AT91C_BASE_AIC,AT91C_ID_MCI); - - // Enable Receiver - AT91F_US_EnableRx((AT91PS_USART) AT91C_BASE_DBGU); - - AT91F_MCI_Configure(AT91C_BASE_MCI, - AT91C_MCI_DTOR_1MEGA_CYCLES, - AT91C_MCI_MR_PDCMODE, // 15MHz for MCK = 60MHz (CLKDIV = 1) - AT91C_MCI_SDCARD_4BITS_SLOTA); - - if(AT91F_MCI_SDCard_Init(&MCI_Device) != AT91C_INIT_OK) - return FALSE; - else - return TRUE; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCIDeviceWaitReady -//* \brief Wait for MCI Device ready -//*---------------------------------------------------------------------------- -void AT91F_MCIDeviceWaitReady(unsigned int timeout) -{ - volatile int status; - - do - { - status = AT91C_BASE_MCI->MCI_SR; - timeout--; - } - while( !(status & AT91C_MCI_NOTBUSY) && (timeout>0) ); -} - -unsigned int swab32(unsigned int data) -{ - unsigned int res = 0; - - res = (data & 0x000000ff) << 24 | - (data & 0x0000ff00) << 8 | - (data & 0x00ff0000) >> 8 | - (data & 0xff000000) >> 24; - - return res; -} - -//*-------------------------------------------------------------------- -//* \fn AT91F_MCI_ReadBlockSwab -//* \brief Read Block and swap byte order -//*-------------------------------------------------------------------- -int AT91F_MCI_ReadBlockSwab( - AT91PS_MciDevice pMCI_Device, - int src, - unsigned int *databuffer, - int sizeToRead) -{ - int i; - unsigned char *buf = (unsigned char *)databuffer; - - //* Read Block 1 - for(i=0;i<BUFFER_SIZE_MCI_DEVICE;i++) - *buf++ = 0x00; - AT91F_MCI_ReadBlock(&MCI_Device,src,databuffer,sizeToRead); - - //* Wait end of Read - AT91F_MCIDeviceWaitReady(AT91C_MCI_TIMEOUT); - - { - int index; - unsigned int *uiBuffer = databuffer; - - for(index = 0; index < 512/4; index++) - uiBuffer[index] = swab32(uiBuffer[index]); - } - return(1); -} - diff --git a/target/linux/at91-2.6/image/dfboot/src/stdio.h b/target/linux/at91-2.6/image/dfboot/src/stdio.h deleted file mode 100644 index e4e35ecf4d..0000000000 --- a/target/linux/at91-2.6/image/dfboot/src/stdio.h +++ /dev/null @@ -1,18 +0,0 @@ -#include <stdarg.h> -#include <stdbool.h> - -#ifndef NULL -#define NULL ((void *)0) -#endif - -void at91_init_uarts(void); -int puts(const char *str); -int putc(int c); -int putchar(int c); -int getc(); - -int strlen(const char *str); - -int hvfprintf(const char *fmt, va_list ap); - -int printf(const char *fmt, ...); diff --git a/target/linux/at91-2.6/image/u-boot/Makefile b/target/linux/at91-2.6/image/u-boot/Makefile deleted file mode 100644 index 6fd667de12..0000000000 --- a/target/linux/at91-2.6/image/u-boot/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -# $Id$ - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=u-boot -PKG_VERSION:=1.1.4 -PKG_RELEASE:=1 - -PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION) -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 -PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot -PKG_MD5SUM:= -PKG_CAT:=bzcat - -include $(INCLUDE_DIR)/package.mk - -UBOOT_CONFIG=$(strip $(subst ",, $(CONFIG_UBOOT_TARGET))) -LAN_IP=$(strip $(CONFIG_UBOOT_IPADDR)) -LAN_SERVERIP=$(strip $(subst ",, $(CONFIG_UBOOT_SERVERIP))) - -define Build/Compile - $(MAKE) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIG)_config - export CROSS_COMPILE=$(TARGET_CROSS); \ - export LAN_IP=$(LAN_IP); \ - export LAN_SERVERIP=$(LAN_SERVERIP); \ - $(MAKE) -C $(PKG_BUILD_DIR) - mkdir -p $(PKG_BUILD_DIR)/ubclient - $(CP) ./ubclient/* $(PKG_BUILD_DIR)/ubclient - export LAN_IP=$(LAN_IP); \ - export LAN_SERVERIP=$(LAN_SERVERIP); \ - $(MAKE) -C $(PKG_BUILD_DIR)/ubclient \ - $(TARGET_CONFIGURE_OPTS) \ - CFLAGS="$(TARGET_CFLAGS) -Dtarget_$(BOARD)=1" -endef - -define Build/InstallDev - dd if=$(PKG_BUILD_DIR)/u-boot.bin of=$(PKG_BUILD_DIR)/u-boot.block bs=232k count=1 conv=sync -# $(INSTALL_DIR) $(STAGING_DIR)/ubclient/sbin -# $(INSTALL_BIN) $(PKG_BUILD_DIR)/ubclient/ubpar $(STAGING_DIR)/ubclient/sbin/ - $(CP) $(PKG_BUILD_DIR)/ubclient/ubpar ../../base-files/default/sbin -endef - -$(eval $(call Build/DefaultTargets)) diff --git a/target/linux/at91-2.6/image/u-boot/patches/001-lowlevel-config.patch b/target/linux/at91-2.6/image/u-boot/patches/001-lowlevel-config.patch deleted file mode 100644 index 25f92e4963..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/001-lowlevel-config.patch +++ /dev/null @@ -1,91 +0,0 @@ ---- u-boot-1.1.4/cpu/arm920t/config.mk 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/cpu/arm920t/config.mk 2006-02-27 19:07:41.000000000 +0100 -@@ -30,5 +30,5 @@ - # Supply options according to compiler version - # - # ========================================================================= --PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32) - PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) ---- u-boot-1.1.4/cpu/arm920t/start.S 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/cpu/arm920t/start.S 2006-02-22 16:45:24.000000000 +0100 -@@ -237,6 +237,7 @@ - */ - - -+#ifndef CONFIG_SKIP_LOWLEVEL_INIT - cpu_init_crit: - /* - * flush v4 I/D caches -@@ -265,6 +266,7 @@ - mov lr, ip - mov pc, lr - -+#endif - - /* - ************************************************************************* ---- u-boot-1.1.4/examples/Makefile 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/examples/Makefile 2006-03-02 02:37:14.000000000 +0100 -@@ -30,7 +30,7 @@ - endif - - ifeq ($(ARCH),arm) --LOAD_ADDR = 0xc100000 -+LOAD_ADDR = 0x21000000 - endif - - ifeq ($(ARCH),mips) ---- u-boot-1.1.4/include/config.h 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.klaus/include/config.h 2006-02-27 19:04:46.000000000 +0100 -@@ -0,0 +1,2 @@ -+/* Automatically generated - do not edit */ -+#include <configs/at91rm9200dk.h> ---- u-boot-1.1.4/include/config.mk 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.klaus/include/config.mk 2006-02-27 19:04:46.000000000 +0100 -@@ -0,0 +1,4 @@ -+ARCH = arm -+CPU = arm920t -+BOARD = at91rm9200dk -+SOC = at91rm9200 ---- u-boot-1.1.4/include/configs/at91rm9200dk.h 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/include/configs/at91rm9200dk.h 2006-02-26 22:44:17.000000000 +0100 -@@ -25,6 +25,11 @@ - #ifndef __CONFIG_H - #define __CONFIG_H - -+// Added 2 defines to skip re-init lowlevel and relocate HCG HLH -+// -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SKIP_RELOCATE_UBOOT -+ - /* ARM asynchronous clock */ - #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ - #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ -@@ -165,12 +170,12 @@ - #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ - #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - --#undef CFG_ENV_IS_IN_DATAFLASH -+#define CFG_ENV_IS_IN_DATAFLASH - - #ifdef CFG_ENV_IS_IN_DATAFLASH --#define CFG_ENV_OFFSET 0x20000 -+#define CFG_ENV_OFFSET 0x21000 - #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) --#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -+#define CFG_ENV_SIZE 0x8400 /* 0x8000 */ - #else - #define CFG_ENV_IS_IN_FLASH 1 - #ifdef CONFIG_SKIP_LOWLEVEL_INIT ---- u-boot-1.1.4/Makefile 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/Makefile 2006-03-02 02:49:23.000000000 +0100 -@@ -57,7 +57,7 @@ - CROSS_COMPILE = powerpc-linux- - endif - ifeq ($(ARCH),arm) --CROSS_COMPILE = arm-linux- -+CROSS_COMPILE = ../staging_dir/bin/arm-linux- - endif - ifeq ($(ARCH),i386) - ifeq ($(HOSTARCH),i387) diff --git a/target/linux/at91-2.6/image/u-boot/patches/002-dataflash_machine.patch b/target/linux/at91-2.6/image/u-boot/patches/002-dataflash_machine.patch deleted file mode 100644 index cf7648c522..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/002-dataflash_machine.patch +++ /dev/null @@ -1,6065 +0,0 @@ -diff -Naur u-boot-1.1.4.org/board/vlink/at45.c u-boot-1.1.4.tmp/board/vlink/at45.c ---- u-boot-1.1.4.org/board/vlink/at45.c 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/at45.c 2005-12-16 17:39:27.000000000 +0100 -@@ -0,0 +1,621 @@ -+/* Driver for ATMEL DataFlash support -+ * Author : Hamid Ikdoumi (Atmel) -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ * -+ */ -+ -+#include <config.h> -+#include <common.h> -+#include <asm/hardware.h> -+ -+#ifdef CONFIG_HAS_DATAFLASH -+#include <dataflash.h> -+ -+#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to -+the Continuous Array Read function */ -+ -+/* AC Characteristics */ -+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -+#define DATAFLASH_TCSS (0xC << 16) -+#define DATAFLASH_TCHS (0x1 << 24) -+ -+#define AT91C_TIMEOUT_WRDY 200000 -+#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -+#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ -+ -+void AT91F_SpiInit(void) { -+ -+/*-------------------------------------------------------------------*/ -+/* SPI DataFlash Init */ -+/*-------------------------------------------------------------------*/ -+ /* Configure PIOs */ -+ AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | -+ AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; -+ AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | -+ AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; -+ /* Enable CLock */ -+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; -+ -+ /* Reset the SPI */ -+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; -+ -+ /* Configure SPI in Master Mode with No CS selected !!! */ -+ AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; -+ -+ /* Configure CS0 and CS3 */ -+ *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & -+ DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); -+ -+ *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & -+ DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); -+ -+} -+ -+void AT91F_SpiEnable(int cs) { -+ switch(cs) { -+ case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ -+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; -+ AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); -+ break; -+ case 3: /* Configure SPI CS3 for Serial DataFlash Card */ -+ /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ -+ AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ -+ AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ -+ /* Clear Output */ -+ AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; -+ /* Configure PCS */ -+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; -+ AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); -+ break; -+ } -+ -+ /* SPI_Enable */ -+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -+} -+ -+/*----------------------------------------------------------------------------*/ -+/* \fn AT91F_SpiWrite */ -+/* \brief Set the PDC registers for a transfert */ -+/*----------------------------------------------------------------------------*/ -+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) -+{ -+ unsigned int timeout; -+ -+ pDesc->state = BUSY; -+ -+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; -+ -+ /* Initialize the Transmit and Receive Pointer */ -+ AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; -+ AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; -+ -+ /* Intialize the Transmit and Receive Counters */ -+ AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; -+ AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; -+ -+ if ( pDesc->tx_data_size != 0 ) { -+ /* Initialize the Next Transmit and Next Receive Pointer */ -+ AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; -+ AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; -+ -+ /* Intialize the Next Transmit and Next Receive Counters */ -+ AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; -+ AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; -+ } -+ -+ /* arm simple, non interrupt dependent timer */ -+ reset_timer_masked(); -+ timeout = 0; -+ -+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; -+ while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); -+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; -+ pDesc->state = IDLE; -+ -+ if (timeout >= CFG_SPI_WRITE_TOUT){ -+ printf("Error Timeout\n\r"); -+ return DATAFLASH_ERROR; -+ } -+ -+ return DATAFLASH_OK; -+} -+ -+ -+/*----------------------------------------------------------------------*/ -+/* \fn AT91F_DataFlashSendCommand */ -+/* \brief Generic function to send a command to the dataflash */ -+/*----------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashSendCommand( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char OpCode, -+ unsigned int CmdSize, -+ unsigned int DataflashAddress) -+{ -+ unsigned int adr; -+ -+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE) -+ return DATAFLASH_BUSY; -+ -+ /* process the address to obtain page address and byte address */ -+ adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); -+ -+ /* fill the command buffer */ -+ pDataFlash->pDataFlashDesc->command[0] = OpCode; -+ if (pDataFlash->pDevice->pages_number >= 16384) { -+ pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); -+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); -+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); -+ pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); -+ } else { -+ pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); -+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); -+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; -+ pDataFlash->pDataFlashDesc->command[4] = 0; -+ } -+ pDataFlash->pDataFlashDesc->command[5] = 0; -+ pDataFlash->pDataFlashDesc->command[6] = 0; -+ pDataFlash->pDataFlashDesc->command[7] = 0; -+ -+ /* Initialize the SpiData structure for the spi write fuction */ -+ pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; -+ pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; -+ pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; -+ pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; -+ -+ /* send the command and read the data */ -+ return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); -+} -+ -+ -+/*----------------------------------------------------------------------*/ -+/* \fn AT91F_DataFlashGetStatus */ -+/* \brief Read the status register of the dataflash */ -+/*----------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -+{ -+ AT91S_DataFlashStatus status; -+ -+ /* if a transfert is in progress ==> return 0 */ -+ if( (pDesc->state) != IDLE) -+ return DATAFLASH_BUSY; -+ -+ /* first send the read status command (D7H) */ -+ pDesc->command[0] = DB_STATUS; -+ pDesc->command[1] = 0; -+ -+ pDesc->DataFlash_state = GET_STATUS; -+ pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ -+ pDesc->tx_cmd_pt = pDesc->command ; -+ pDesc->rx_cmd_pt = pDesc->command ; -+ pDesc->rx_cmd_size = 2 ; -+ pDesc->tx_cmd_size = 2 ; -+ status = AT91F_SpiWrite (pDesc); -+ -+ pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); -+ -+ return status; -+} -+ -+ -+/*----------------------------------------------------------------------*/ -+/* \fn AT91F_DataFlashWaitReady */ -+/* \brief wait for dataflash ready (bit7 of the status register == 1) */ -+/*----------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) -+{ -+ pDataFlashDesc->DataFlash_state = IDLE; -+ -+ do { -+ AT91F_DataFlashGetStatus(pDataFlashDesc); -+ timeout--; -+ } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); -+ -+ if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) -+ return DATAFLASH_ERROR; -+ -+ return DATAFLASH_OK; -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataFlashContinuousRead */ -+/* Object : Continuous stream Read */ -+/* Input Parameters : DataFlash Service */ -+/* : <src> = dataflash address */ -+/* : <*dataBuffer> = data buffer pointer */ -+/* : <sizeToRead> = data buffer size */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( -+ AT91PS_DataFlash pDataFlash, -+ int src, -+ unsigned char *dataBuffer, -+ int sizeToRead ) -+{ -+ AT91S_DataFlashStatus status; -+ /* Test the size to read in the device */ -+ if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) -+ return DATAFLASH_MEMORY_OVERFLOW; -+ -+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; -+ pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; -+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; -+ pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; -+ -+ status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); -+ /* Send the command to the dataflash */ -+ return(status); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataFlashPagePgmBuf */ -+/* Object : Main memory page program through buffer 1 or buffer 2 */ -+/* Input Parameters : DataFlash Service */ -+/* : <*src> = Source buffer */ -+/* : <dest> = dataflash destination address */ -+/* : <SizeToWrite> = data buffer size */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char *src, -+ unsigned int dest, -+ unsigned int SizeToWrite) -+{ -+ int cmdsize; -+ pDataFlash->pDataFlashDesc->tx_data_pt = src ; -+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; -+ pDataFlash->pDataFlashDesc->rx_data_pt = src; -+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; -+ -+ cmdsize = 4; -+ /* Send the command to the dataflash */ -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_MainMemoryToBufferTransfert */ -+/* Object : Read a page in the SRAM Buffer 1 or 2 */ -+/* Input Parameters : DataFlash Service */ -+/* : Page concerned */ -+/* : */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char BufferCommand, -+ unsigned int page) -+{ -+ int cmdsize; -+ /* Test if the buffer command is legal */ -+ if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) -+ return DATAFLASH_BAD_COMMAND; -+ -+ /* no data to transmit or receive */ -+ pDataFlash->pDataFlashDesc->tx_data_size = 0; -+ cmdsize = 4; -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); -+} -+ -+ -+/*----------------------------------------------------------------------------- */ -+/* Function Name : AT91F_DataFlashWriteBuffer */ -+/* Object : Write data to the internal sram buffer 1 or 2 */ -+/* Input Parameters : DataFlash Service */ -+/* : <BufferCommand> = command to write buffer1 or buffer2 */ -+/* : <*dataBuffer> = data buffer to write */ -+/* : <bufferAddress> = address in the internal buffer */ -+/* : <SizeToWrite> = data buffer size */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char BufferCommand, -+ unsigned char *dataBuffer, -+ unsigned int bufferAddress, -+ int SizeToWrite ) -+{ -+ int cmdsize; -+ /* Test if the buffer command is legal */ -+ if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) -+ return DATAFLASH_BAD_COMMAND; -+ -+ /* buffer address must be lower than page size */ -+ if (bufferAddress > pDataFlash->pDevice->pages_size) -+ return DATAFLASH_BAD_ADDRESS; -+ -+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE) -+ return DATAFLASH_BUSY; -+ -+ /* Send first Write Command */ -+ pDataFlash->pDataFlashDesc->command[0] = BufferCommand; -+ pDataFlash->pDataFlashDesc->command[1] = 0; -+ if (pDataFlash->pDevice->pages_number >= 16384) { -+ pDataFlash->pDataFlashDesc->command[2] = 0; -+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; -+ pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; -+ cmdsize = 5; -+ } else { -+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; -+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; -+ pDataFlash->pDataFlashDesc->command[4] = 0; -+ cmdsize = 4; -+ } -+ -+ pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; -+ pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; -+ pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; -+ pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; -+ -+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; -+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; -+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; -+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; -+ -+ return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -+} -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_PageErase */ -+/* Object : Erase a page */ -+/* Input Parameters : DataFlash Service */ -+/* : Page concerned */ -+/* : */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_PageErase( -+ AT91PS_DataFlash pDataFlash, -+ unsigned int page) -+{ -+ int cmdsize; -+ /* Test if the buffer command is legal */ -+ /* no data to transmit or receive */ -+ pDataFlash->pDataFlashDesc->tx_data_size = 0; -+ -+ cmdsize = 4; -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_BlockErase */ -+/* Object : Erase a Block */ -+/* Input Parameters : DataFlash Service */ -+/* : Page concerned */ -+/* : */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_BlockErase( -+ AT91PS_DataFlash pDataFlash, -+ unsigned int block) -+{ -+ int cmdsize; -+ /* Test if the buffer command is legal */ -+ /* no data to transmit or receive */ -+ pDataFlash->pDataFlashDesc->tx_data_size = 0; -+ cmdsize = 4; -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); -+} -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_WriteBufferToMain */ -+/* Object : Write buffer to the main memory */ -+/* Input Parameters : DataFlash Service */ -+/* : <BufferCommand> = command to send to buffer1 or buffer2 */ -+/* : <dest> = main memory address */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_WriteBufferToMain ( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char BufferCommand, -+ unsigned int dest ) -+{ -+ int cmdsize; -+ /* Test if the buffer command is correct */ -+ if ((BufferCommand != DB_BUF1_PAGE_PGM) && -+ (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && -+ (BufferCommand != DB_BUF2_PAGE_PGM) && -+ (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) -+ return DATAFLASH_BAD_COMMAND; -+ -+ /* no data to transmit or receive */ -+ pDataFlash->pDataFlashDesc->tx_data_size = 0; -+ -+ cmdsize = 4; -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ /* Send the command to the dataflash */ -+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_PartialPageWrite */ -+/* Object : Erase partielly a page */ -+/* Input Parameters : <page> = page number */ -+/* : <AdrInpage> = adr to begin the fading */ -+/* : <length> = Number of bytes to erase */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_PartialPageWrite ( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char *src, -+ unsigned int dest, -+ unsigned int size) -+{ -+ unsigned int page; -+ unsigned int AdrInPage; -+ -+ page = dest / (pDataFlash->pDevice->pages_size); -+ AdrInPage = dest % (pDataFlash->pDevice->pages_size); -+ -+ /* Read the contents of the page in the Sram Buffer */ -+ AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ /*Update the SRAM buffer */ -+ AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); -+ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ -+ /* Erase page if a 128 Mbits device */ -+ if (pDataFlash->pDevice->pages_number >= 16384) { -+ AT91F_PageErase(pDataFlash, page); -+ /* Rewrite the modified Sram Buffer in the main memory */ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ } -+ -+ /* Rewrite the modified Sram Buffer in the main memory */ -+ return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataFlashWrite */ -+/* Object : */ -+/* Input Parameters : <*src> = Source buffer */ -+/* : <dest> = dataflash adress */ -+/* : <size> = data buffer size */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashWrite( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char *src, -+ int dest, -+ int size ) -+{ -+ unsigned int length; -+ unsigned int page; -+ unsigned int status; -+ -+ AT91F_SpiEnable(pDataFlash->pDevice->cs); -+ -+ if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) -+ return DATAFLASH_MEMORY_OVERFLOW; -+ -+ /* If destination does not fit a page start address */ -+ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { -+ length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); -+ -+ if (size < length) -+ length = size; -+ -+ if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) -+ return DATAFLASH_ERROR; -+ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ -+ /* Update size, source and destination pointers */ -+ size -= length; -+ dest += length; -+ src += length; -+ } -+ -+ while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { -+ /* program dataflash page */ -+ page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); -+ -+ status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ -+ status = AT91F_PageErase(pDataFlash, page); -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ if (!status) -+ return DATAFLASH_ERROR; -+ -+ status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); -+ if(!status) -+ return DATAFLASH_ERROR; -+ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ -+ /* Update size, source and destination pointers */ -+ size -= pDataFlash->pDevice->pages_size ; -+ dest += pDataFlash->pDevice->pages_size ; -+ src += pDataFlash->pDevice->pages_size ; -+ } -+ -+ /* If still some bytes to read */ -+ if ( size > 0 ) { -+ /* program dataflash page */ -+ if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) -+ return DATAFLASH_ERROR; -+ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ } -+ return DATAFLASH_OK; -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataFlashRead */ -+/* Object : Read a block in dataflash */ -+/* Input Parameters : */ -+/* Return value : */ -+/*------------------------------------------------------------------------------*/ -+int AT91F_DataFlashRead( -+ AT91PS_DataFlash pDataFlash, -+ unsigned long addr, -+ unsigned long size, -+ char *buffer) -+{ -+ unsigned long SizeToRead; -+ -+ AT91F_SpiEnable(pDataFlash->pDevice->cs); -+ -+ if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) -+ return -1; -+ -+ while (size) { -+ SizeToRead = (size < 0x8000)? size:0x8000; -+ -+ if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) -+ return -1; -+ -+ if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) -+ return -1; -+ -+ size -= SizeToRead; -+ addr += SizeToRead; -+ buffer += SizeToRead; -+ } -+ -+ return DATAFLASH_OK; -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataflashProbe */ -+/* Object : */ -+/* Input Parameters : */ -+/* Return value : Dataflash status register */ -+/*------------------------------------------------------------------------------*/ -+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -+{ -+ AT91F_SpiEnable(cs); -+ AT91F_DataFlashGetStatus(pDesc); -+ return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); -+} -+ -+#endif -diff -Naur u-boot-1.1.4.org/board/vlink/config.mk u-boot-1.1.4.tmp/board/vlink/config.mk ---- u-boot-1.1.4.org/board/vlink/config.mk 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/config.mk 2005-12-16 17:39:27.000000000 +0100 -@@ -0,0 +1 @@ -+TEXT_BASE = 0x21f00000 -diff -Naur u-boot-1.1.4.org/board/vlink/flash.c u-boot-1.1.4.tmp/board/vlink/flash.c ---- u-boot-1.1.4.org/board/vlink/flash.c 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/flash.c 2006-06-05 02:44:43.000000000 +0200 -@@ -0,0 +1,504 @@ -+/* -+ * (C) Copyright 2002 -+ * Lineo, Inc. <www.lineo.com> -+ * Bernhard Kuhn <bkuhn@lineo.com> -+ * -+ * (C) Copyright 2002 -+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> -+ * Alex Zuepke <azu@sysgo.de> -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include <common.h> -+ -+ulong myflush(void); -+ -+ -+/* Flash Organization Structure */ -+typedef struct OrgDef -+{ -+ unsigned int sector_number; -+ unsigned int sector_size; -+} OrgDef; -+ -+ -+/* Flash Organizations */ -+OrgDef OrgAT49BV16x4[] = -+{ -+ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ -+ { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ -+ { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ -+}; -+ -+OrgDef OrgAT49BV16x4A[] = -+{ -+ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ -+ { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ -+}; -+ -+OrgDef OrgAT49BV6416[] = -+{ -+ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ -+ { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ -+}; -+ -+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -+ -+/* AT49BV1614A Codes */ -+#define FLASH_CODE1 0xAA -+#define FLASH_CODE2 0x55 -+#define ID_IN_CODE 0x90 -+#define ID_OUT_CODE 0xF0 -+ -+ -+#define CMD_READ_ARRAY 0x00F0 -+#define CMD_UNLOCK1 0x00AA -+#define CMD_UNLOCK2 0x0055 -+#define CMD_ERASE_SETUP 0x0080 -+#define CMD_ERASE_CONFIRM 0x0030 -+#define CMD_PROGRAM 0x00A0 -+#define CMD_UNLOCK_BYPASS 0x0020 -+#define CMD_SECTOR_UNLOCK 0x0070 -+ -+#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) -+#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) -+ -+#define BIT_ERASE_DONE 0x0080 -+#define BIT_RDY_MASK 0x0080 -+#define BIT_PROGRAM_ERROR 0x0020 -+#define BIT_TIMEOUT 0x80000000 /* our flag */ -+ -+#define READY 1 -+#define ERR 2 -+#define TMO 4 -+ -+/*----------------------------------------------------------------------- -+ */ -+void flash_identification (flash_info_t * info) -+{ -+ volatile u16 manuf_code, device_code, add_device_code; -+ -+ MEM_FLASH_ADDR1 = FLASH_CODE1; -+ MEM_FLASH_ADDR2 = FLASH_CODE2; -+ MEM_FLASH_ADDR1 = ID_IN_CODE; -+ -+ manuf_code = *(volatile u16 *) CFG_FLASH_BASE; -+ device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2); -+ add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1)); -+ -+ MEM_FLASH_ADDR1 = FLASH_CODE1; -+ MEM_FLASH_ADDR2 = FLASH_CODE2; -+ MEM_FLASH_ADDR1 = ID_OUT_CODE; -+ -+ /* Vendor type */ -+ info->flash_id = ATM_MANUFACT & FLASH_VENDMASK; -+ printf ("Atmel: "); -+ -+ if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { -+ -+ if ((add_device_code & FLASH_TYPEMASK) == -+ (ATM_ID_BV1614A & FLASH_TYPEMASK)) { -+ info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; -+ printf ("AT49BV1614A (16Mbit)\n"); -+ } else { /* AT49BV1614 Flash */ -+ info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; -+ printf ("AT49BV1614 (16Mbit)\n"); -+ } -+ -+ } else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { -+ info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; -+ printf ("AT49BV6416 (64Mbit)\n"); -+ } -+} -+ -+ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) -+{ -+ int i, nb_sectors = 0; -+ -+ for (i=0; i<nb_blocks; i++){ -+ nb_sectors += pOrgDef[i].sector_number; -+ } -+ -+ return nb_sectors; -+} -+ -+void flash_unlock_sector(flash_info_t * info, unsigned int sector) -+{ -+ volatile u16 *addr = (volatile u16 *) (info->start[sector]); -+ -+ MEM_FLASH_ADDR1 = CMD_UNLOCK1; -+ *addr = CMD_SECTOR_UNLOCK; -+} -+ -+ -+ulong flash_init (void) -+{ -+ int i, j, k; -+ unsigned int flash_nb_blocks, sector; -+ unsigned int start_address; -+ OrgDef *pOrgDef; -+ -+ ulong size = 0; -+ -+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { -+ ulong flashbase = 0; -+ -+ flash_identification (&flash_info[i]); -+ -+ if ((flash_info[i].flash_id & FLASH_TYPEMASK) == -+ (ATM_ID_BV1614 & FLASH_TYPEMASK)) { -+ -+ pOrgDef = OrgAT49BV16x4; -+ flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); -+ } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == -+ (ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */ -+ -+ pOrgDef = OrgAT49BV16x4A; -+ flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef); -+ } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == -+ (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ -+ -+ pOrgDef = OrgAT49BV6416; -+ flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); -+ } else { -+ flash_nb_blocks = 0; -+ pOrgDef = OrgAT49BV16x4; -+ } -+ -+ flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); -+ memset (flash_info[i].protect, 0, flash_info[i].sector_count); -+ -+ if (i == 0) -+ flashbase = PHYS_FLASH_1; -+ else -+ panic ("configured too many flash banks!\n"); -+ -+ sector = 0; -+ start_address = flashbase; -+ flash_info[i].size = 0; -+ -+ for (j = 0; j < flash_nb_blocks; j++) { -+ for (k = 0; k < pOrgDef[j].sector_number; k++) { -+ flash_info[i].start[sector++] = start_address; -+ start_address += pOrgDef[j].sector_size; -+ flash_info[i].size += pOrgDef[j].sector_size; -+ } -+ } -+ -+ size += flash_info[i].size; -+ -+ if ((flash_info[i].flash_id & FLASH_TYPEMASK) == -+ (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ -+ -+ /* Unlock all sectors at reset */ -+ for (j=0; j<flash_info[i].sector_count; j++){ -+ flash_unlock_sector(&flash_info[i], j); -+ } -+ } -+ } -+ -+ /* Protect binary boot image */ -+ flash_protect (FLAG_PROTECT_SET, -+ CFG_FLASH_BASE, -+ CFG_FLASH_BASE + CFG_BOOT_SIZE - 1, &flash_info[0]); -+ -+ /* Protect environment variables */ -+ flash_protect (FLAG_PROTECT_SET, -+ CFG_ENV_ADDR, -+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -+ -+ /* Protect U-Boot gzipped image */ -+ flash_protect (FLAG_PROTECT_SET, -+ CFG_U_BOOT_BASE, -+ CFG_U_BOOT_BASE + CFG_U_BOOT_SIZE - 1, &flash_info[0]); -+ -+ return size; -+} -+ -+/*----------------------------------------------------------------------- -+ */ -+void flash_print_info (flash_info_t * info) -+{ -+ int i; -+ -+ switch (info->flash_id & FLASH_VENDMASK) { -+ case (ATM_MANUFACT & FLASH_VENDMASK): -+ printf ("Atmel: "); -+ break; -+ default: -+ printf ("Unknown Vendor "); -+ break; -+ } -+ -+ switch (info->flash_id & FLASH_TYPEMASK) { -+ case (ATM_ID_BV1614 & FLASH_TYPEMASK): -+ printf ("AT49BV1614 (16Mbit)\n"); -+ break; -+ case (ATM_ID_BV1614A & FLASH_TYPEMASK): -+ printf ("AT49BV1614A (16Mbit)\n"); -+ break; -+ case (ATM_ID_BV6416 & FLASH_TYPEMASK): -+ printf ("AT49BV6416 (64Mbit)\n"); -+ break; -+ default: -+ printf ("Unknown Chip Type\n"); -+ return; -+ } -+ -+ printf (" Size: %ld MB in %d Sectors\n", -+ info->size >> 20, info->sector_count); -+ -+ printf (" Sector Start Addresses:"); -+ for (i = 0; i < info->sector_count; i++) { -+ if ((i % 5) == 0) { -+ printf ("\n "); -+ } -+ printf (" %08lX%s", info->start[i], -+ info->protect[i] ? " (RO)" : " "); -+ } -+ printf ("\n"); -+} -+ -+/*----------------------------------------------------------------------- -+ */ -+ -+int flash_erase (flash_info_t * info, int s_first, int s_last) -+{ -+ ulong result; -+ int iflag, cflag, prot, sect; -+ int rc = ERR_OK; -+ int chip1; -+ -+ /* first look for protection bits */ -+ -+ if (info->flash_id == FLASH_UNKNOWN) -+ return ERR_UNKNOWN_FLASH_TYPE; -+ -+ if ((s_first < 0) || (s_first > s_last)) { -+ return ERR_INVAL; -+ } -+ -+ if ((info->flash_id & FLASH_VENDMASK) != -+ (ATM_MANUFACT & FLASH_VENDMASK)) { -+ return ERR_UNKNOWN_FLASH_VENDOR; -+ } -+ -+ prot = 0; -+ for (sect = s_first; sect <= s_last; ++sect) { -+ if (info->protect[sect]) { -+ prot++; -+ } -+ } -+ if (prot) -+ return ERR_PROTECTED; -+ -+ /* -+ * Disable interrupts which might cause a timeout -+ * here. Remember that our exception vectors are -+ * at address 0 in the flash, and we don't want a -+ * (ticker) exception to happen while the flash -+ * chip is in programming mode. -+ */ -+ cflag = icache_status (); -+ icache_disable (); -+ iflag = disable_interrupts (); -+ -+ /* Start erase on unprotected sectors */ -+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { -+ printf ("Erasing sector %2d ... ", sect); -+ -+ /* arm simple, non interrupt dependent timer */ -+ reset_timer_masked (); -+ -+ if (info->protect[sect] == 0) { /* not protected */ -+ volatile u16 *addr = (volatile u16 *) (info->start[sect]); -+ -+ MEM_FLASH_ADDR1 = CMD_UNLOCK1; -+ MEM_FLASH_ADDR2 = CMD_UNLOCK2; -+ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; -+ -+ MEM_FLASH_ADDR1 = CMD_UNLOCK1; -+ MEM_FLASH_ADDR2 = CMD_UNLOCK2; -+ *addr = CMD_ERASE_CONFIRM; -+ -+ /* wait until flash is ready */ -+ chip1 = 0; -+ -+ do { -+ result = *addr; -+ -+ /* check timeout */ -+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { -+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; -+ chip1 = TMO; -+ break; -+ } -+ -+ if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) -+ chip1 = READY; -+ -+ } while (!chip1); -+ -+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; -+ -+ if (chip1 == ERR) { -+ rc = ERR_PROG_ERROR; -+ goto outahere; -+ } -+ if (chip1 == TMO) { -+ rc = ERR_TIMOUT; -+ goto outahere; -+ } -+ -+ printf ("ok.\n"); -+ } else { /* it was protected */ -+ printf ("protected!\n"); -+ } -+ } -+ -+ if (ctrlc ()) -+ printf ("User Interrupt!\n"); -+ -+outahere: -+ /* allow flash to settle - wait 10 ms */ -+ udelay_masked (10000); -+ -+ if (iflag) -+ enable_interrupts (); -+ -+ if (cflag) -+ icache_enable (); -+ -+ return rc; -+} -+ -+/*----------------------------------------------------------------------- -+ * Copy memory to flash -+ */ -+ -+volatile static int write_word (flash_info_t * info, ulong dest, -+ ulong data) -+{ -+ volatile u16 *addr = (volatile u16 *) dest; -+ ulong result; -+ int rc = ERR_OK; -+ int cflag, iflag; -+ int chip1; -+ -+ /* -+ * Check if Flash is (sufficiently) erased -+ */ -+ result = *addr; -+ if ((result & data) != data) -+ return ERR_NOT_ERASED; -+ -+ -+ /* -+ * Disable interrupts which might cause a timeout -+ * here. Remember that our exception vectors are -+ * at address 0 in the flash, and we don't want a -+ * (ticker) exception to happen while the flash -+ * chip is in programming mode. -+ */ -+ cflag = icache_status (); -+ icache_disable (); -+ iflag = disable_interrupts (); -+ -+ MEM_FLASH_ADDR1 = CMD_UNLOCK1; -+ MEM_FLASH_ADDR2 = CMD_UNLOCK2; -+ MEM_FLASH_ADDR1 = CMD_PROGRAM; -+ *addr = data; -+ -+ /* arm simple, non interrupt dependent timer */ -+ reset_timer_masked (); -+ -+ /* wait until flash is ready */ -+ chip1 = 0; -+ do { -+ result = *addr; -+ -+ /* check timeout */ -+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { -+ chip1 = ERR | TMO; -+ break; -+ } -+ if (!chip1 && ((result & 0x80) == (data & 0x80))) -+ chip1 = READY; -+ -+ } while (!chip1); -+ -+ *addr = CMD_READ_ARRAY; -+ -+ if (chip1 == ERR || *addr != data) -+ rc = ERR_PROG_ERROR; -+ -+ if (iflag) -+ enable_interrupts (); -+ -+ if (cflag) -+ icache_enable (); -+ -+ return rc; -+} -+ -+/*----------------------------------------------------------------------- -+ * Copy memory to flash. -+ */ -+ -+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -+{ -+ ulong wp, data; -+ int rc; -+ -+ if (addr & 1) { -+ printf ("unaligned destination not supported\n"); -+ return ERR_ALIGN; -+ }; -+ -+ if ((int) src & 1) { -+ printf ("unaligned source not supported\n"); -+ return ERR_ALIGN; -+ }; -+ -+ wp = addr; -+ -+ while (cnt >= 2) { -+ data = *((volatile u16 *) src); -+ if ((rc = write_word (info, wp, data)) != 0) { -+ return (rc); -+ } -+ src += 2; -+ wp += 2; -+ cnt -= 2; -+ } -+ -+ if (cnt == 1) { -+ data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << -+ 8); -+ if ((rc = write_word (info, wp, data)) != 0) { -+ return (rc); -+ } -+ src += 1; -+ wp += 1; -+ cnt -= 1; -+ }; -+ -+ return ERR_OK; -+} -diff -Naur u-boot-1.1.4.org/board/vlink/Makefile u-boot-1.1.4.tmp/board/vlink/Makefile ---- u-boot-1.1.4.org/board/vlink/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/Makefile 2006-06-05 02:48:33.000000000 +0200 -@@ -0,0 +1,46 @@ -+# -+# (C) Copyright 2003 -+# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -+# -+# See file CREDITS for list of people who contributed to this -+# project. -+# -+# This program is free software; you can redistribute it and/or -+# modify it under the terms of the GNU General Public License as -+# published by the Free Software Foundation; either version 2 of -+# the License, or (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+# MA 02111-1307 USA -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = lib$(BOARD).a -+ -+OBJS := vlink.o at45.o flash.o -+ -+$(LIB): $(OBJS) $(SOBJS) -+ $(AR) crv $@ $(OBJS) $(SOBJS) -+ -+clean: -+ rm -f $(SOBJS) $(OBJS) -+ -+distclean: clean -+ rm -f $(LIB) core *.bak .depend -+ -+######################################################################### -+ -+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) -+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -+ -+-include .depend -+ -+######################################################################### -diff -Naur u-boot-1.1.4.org/board/vlink/u-boot.lds u-boot-1.1.4.tmp/board/vlink/u-boot.lds ---- u-boot-1.1.4.org/board/vlink/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/u-boot.lds 2005-12-16 17:39:27.000000000 +0100 -@@ -0,0 +1,57 @@ -+/* -+ * (C) Copyright 2002 -+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -+OUTPUT_ARCH(arm) -+ENTRY(_start) -+SECTIONS -+{ -+ . = 0x00000000; -+ -+ . = ALIGN(4); -+ .text : -+ { -+ cpu/arm920t/start.o (.text) -+ *(.text) -+ } -+ -+ . = ALIGN(4); -+ .rodata : { *(.rodata) } -+ -+ . = ALIGN(4); -+ .data : { *(.data) } -+ -+ . = ALIGN(4); -+ .got : { *(.got) } -+ -+ . = .; -+ __u_boot_cmd_start = .; -+ .u_boot_cmd : { *(.u_boot_cmd) } -+ __u_boot_cmd_end = .; -+ -+ . = ALIGN(4); -+ __bss_start = .; -+ .bss : { *(.bss) } -+ _end = .; -+} -diff -Naur u-boot-1.1.4.org/board/vlink/vlink.c u-boot-1.1.4.tmp/board/vlink/vlink.c ---- u-boot-1.1.4.org/board/vlink/vlink.c 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/vlink.c 2006-06-05 03:10:22.000000000 +0200 -@@ -0,0 +1,89 @@ -+/* -+ * (C) Copyright 2002 -+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> -+ * Marius Groeger <mgroeger@sysgo.de> -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include <common.h> -+#include <asm/arch/AT91RM9200.h> -+#include <at91rm9200_net.h> -+#include <dm9161.h> -+#include <asm/mach-types.h> -+ -+/* ------------------------------------------------------------------------- */ -+/* -+ * Miscelaneous platform dependent initialisations -+ */ -+ -+int board_init (void) -+{ -+ DECLARE_GLOBAL_DATA_PTR; -+ -+ /* Enable Ctrlc */ -+ console_init_f (); -+ -+ /* Correct IRDA resistor problem */ -+ /* Set PA23_TXD in Output */ -+ (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; -+ -+ /* memory and cpu-speed are setup before relocation */ -+ /* so we do _nothing_ here */ -+ -+ /* arch number of Versalink-Board */ -+ gd->bd->bi_arch_number = MACH_TYPE_VLINK; -+ /* adress of boot parameters */ -+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -+ -+ return 0; -+} -+ -+int dram_init (void) -+{ -+ DECLARE_GLOBAL_DATA_PTR; -+ -+ gd->bd->bi_dram[0].start = PHYS_SDRAM; -+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; -+ return 0; -+} -+ -+#ifdef CONFIG_DRIVER_ETHER -+#if (CONFIG_COMMANDS & CFG_CMD_NET) -+ -+/* -+ * Name: -+ * at91rm9200_GetPhyInterface -+ * Description: -+ * Initialise the interface functions to the PHY -+ * Arguments: -+ * None -+ * Return value: -+ * None -+ */ -+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -+{ -+ p_phyops->Init = dm9161_InitPhy; -+ p_phyops->IsPhyConnected = dm9161_IsPhyConnected; -+ p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; -+ p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -+} -+ -+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ -+#endif /* CONFIG_DRIVER_ETHER */ -diff -Naur u-boot-1.1.4.org/include/asm-arm/mach-types.h u-boot-1.1.4.tmp/include/asm-arm/mach-types.h ---- u-boot-1.1.4.org/include/asm-arm/mach-types.h 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.tmp/include/asm-arm/mach-types.h 2006-06-05 01:29:25.000000000 +0200 -@@ -424,7 +424,7 @@ - #define MACH_TYPE_MPORT3S 411 - #define MACH_TYPE_RA_ALPHA 412 - #define MACH_TYPE_XCEP 413 --#define MACH_TYPE_ARCOM_MERCURY 414 -+#define MACH_TYPE_ARCOM_VULCAN 414 - #define MACH_TYPE_STARGATE 415 - #define MACH_TYPE_ARMADILLOJ 416 - #define MACH_TYPE_ELROY_JACK 417 -@@ -457,7 +457,7 @@ - #define MACH_TYPE_XM250 444 - #define MACH_TYPE_T6TC1XB 445 - #define MACH_TYPE_ESS710 446 --#define MACH_TYPE_MX3ADS 447 -+#define MACH_TYPE_MX31ADS 447 - #define MACH_TYPE_HIMALAYA 448 - #define MACH_TYPE_BOLFENK 449 - #define MACH_TYPE_AT91RM9200KR 450 -@@ -563,8 +563,8 @@ - #define MACH_TYPE_ENS_CMU 550 - #define MACH_TYPE_MM6_SDB 551 - #define MACH_TYPE_SATURN 552 --#define MACH_TYPE_ARGONPLUSEVB 553 --#define MACH_TYPE_SCMA11EVB 554 -+#define MACH_TYPE_I30030EVB 553 -+#define MACH_TYPE_MXC27530EVB 554 - #define MACH_TYPE_SMDK2800 555 - #define MACH_TYPE_MTWILSON 556 - #define MACH_TYPE_ZITI 557 -@@ -644,7 +644,7 @@ - #define MACH_TYPE_MX2JAZZ 631 - #define MACH_TYPE_MULTIIO 632 - #define MACH_TYPE_HRDISPLAY 633 --#define MACH_TYPE_SCMA11BB 634 -+#define MACH_TYPE_MXC27530ADS 634 - #define MACH_TYPE_TRIZEPS3 635 - #define MACH_TYPE_ZEFEERDZA 636 - #define MACH_TYPE_ZEFEERDZB 637 -@@ -718,7 +718,7 @@ - #define MACH_TYPE_GEM 707 - #define MACH_TYPE_I858 708 - #define MACH_TYPE_HX2750 709 --#define MACH_TYPE_ZEUSEVB 710 -+#define MACH_TYPE_MXC91131EVB 710 - #define MACH_TYPE_P700 711 - #define MACH_TYPE_CPE 712 - #define MACH_TYPE_SPITZ 713 -@@ -736,6 +736,331 @@ - #define MACH_TYPE_LN2410SBC 725 - #define MACH_TYPE_CB3RUFC 726 - #define MACH_TYPE_MP2USB 727 -+#define MACH_TYPE_NTNP425C 728 -+#define MACH_TYPE_COLIBRI 729 -+#define MACH_TYPE_PCM7220 730 -+#define MACH_TYPE_GATEWAY7001 731 -+#define MACH_TYPE_PCM027 732 -+#define MACH_TYPE_CMPXA 733 -+#define MACH_TYPE_ANUBIS 734 -+#define MACH_TYPE_ITE8152 735 -+#define MACH_TYPE_LPC3XXX 736 -+#define MACH_TYPE_PUPPETEER 737 -+#define MACH_TYPE_MACH_VADATECH 738 -+#define MACH_TYPE_E570 739 -+#define MACH_TYPE_X50 740 -+#define MACH_TYPE_RECON 741 -+#define MACH_TYPE_XBOARDGP8 742 -+#define MACH_TYPE_FPIC2 743 -+#define MACH_TYPE_AKITA 744 -+#define MACH_TYPE_A81 745 -+#define MACH_TYPE_SVM_SC25X 746 -+#define MACH_TYPE_VADATECH020 747 -+#define MACH_TYPE_TLI 748 -+#define MACH_TYPE_EDB9315LC 749 -+#define MACH_TYPE_PASSEC 750 -+#define MACH_TYPE_DS_TIGER 751 -+#define MACH_TYPE_E310 752 -+#define MACH_TYPE_E330 753 -+#define MACH_TYPE_RT3000 754 -+#define MACH_TYPE_NOKIA770 755 -+#define MACH_TYPE_PNX0106 756 -+#define MACH_TYPE_HX21XX 757 -+#define MACH_TYPE_FARADAY 758 -+#define MACH_TYPE_SBC9312 759 -+#define MACH_TYPE_BATMAN 760 -+#define MACH_TYPE_JPD201 761 -+#define MACH_TYPE_MIPSA 762 -+#define MACH_TYPE_KACOM 763 -+#define MACH_TYPE_SWARCOCPU 764 -+#define MACH_TYPE_SWARCODSL 765 -+#define MACH_TYPE_BLUEANGEL 766 -+#define MACH_TYPE_HAIRYGRAMA 767 -+#define MACH_TYPE_BANFF 768 -+#define MACH_TYPE_CARMEVA 769 -+#define MACH_TYPE_SAM255 770 -+#define MACH_TYPE_PPM10 771 -+#define MACH_TYPE_EDB9315A 772 -+#define MACH_TYPE_SUNSET 773 -+#define MACH_TYPE_STARGATE2 774 -+#define MACH_TYPE_INTELMOTE2 775 -+#define MACH_TYPE_TRIZEPS4 776 -+#define MACH_TYPE_MAINSTONE2 777 -+#define MACH_TYPE_EZ_IXP42X 778 -+#define MACH_TYPE_TAPWAVE_ZODIAC 779 -+#define MACH_TYPE_UNIVERSALMETER 780 -+#define MACH_TYPE_HICOARM9 781 -+#define MACH_TYPE_PNX4008 782 -+#define MACH_TYPE_KWS6000 783 -+#define MACH_TYPE_PORTUX920T 784 -+#define MACH_TYPE_EZ_X5 785 -+#define MACH_TYPE_OMAP_RUDOLPH 786 -+#define MACH_TYPE_CPUAT91 787 -+#define MACH_TYPE_REA9200 788 -+#define MACH_TYPE_ACTS_PUNE_SA1110 789 -+#define MACH_TYPE_IXP425 790 -+#define MACH_TYPE_I30030ADS 791 -+#define MACH_TYPE_PERCH 792 -+#define MACH_TYPE_EIS05R1 793 -+#define MACH_TYPE_PEPPERPAD 794 -+#define MACH_TYPE_SB3010 795 -+#define MACH_TYPE_RM9200 796 -+#define MACH_TYPE_DMA03 797 -+#define MACH_TYPE_ROAD_S101 798 -+#define MACH_TYPE_IQ_NEXTGEN_A 799 -+#define MACH_TYPE_IQ_NEXTGEN_B 800 -+#define MACH_TYPE_IQ_NEXTGEN_C 801 -+#define MACH_TYPE_IQ_NEXTGEN_D 802 -+#define MACH_TYPE_IQ_NEXTGEN_E 803 -+#define MACH_TYPE_MALLOW_AT91 804 -+#define MACH_TYPE_CYBERTRACKER_I 805 -+#define MACH_TYPE_GESBC931X 806 -+#define MACH_TYPE_CENTIPAD 807 -+#define MACH_TYPE_ARMSOC 808 -+#define MACH_TYPE_SE4200 809 -+#define MACH_TYPE_EMS197A 810 -+#define MACH_TYPE_MICRO9 811 -+#define MACH_TYPE_MICRO9L 812 -+#define MACH_TYPE_UC5471DSP 813 -+#define MACH_TYPE_SJ5471ENG 814 -+#define MACH_TYPE_CMPXA26X 815 -+#define MACH_TYPE_NC 816 -+#define MACH_TYPE_OMAP_PALMTE 817 -+#define MACH_TYPE_AJAX52X 818 -+#define MACH_TYPE_SIRIUSTAR 819 -+#define MACH_TYPE_IODATA_HDLG 820 -+#define MACH_TYPE_AT91RM9200UTL 821 -+#define MACH_TYPE_BIOSAFE 822 -+#define MACH_TYPE_MP1000 823 -+#define MACH_TYPE_PARSY 824 -+#define MACH_TYPE_CCXP 825 -+#define MACH_TYPE_OMAP_GSAMPLE 826 -+#define MACH_TYPE_REALVIEW_EB 827 -+#define MACH_TYPE_SAMOA 828 -+#define MACH_TYPE_T3XSCALE 829 -+#define MACH_TYPE_I878 830 -+#define MACH_TYPE_BORZOI 831 -+#define MACH_TYPE_GECKO 832 -+#define MACH_TYPE_DS101 833 -+#define MACH_TYPE_OMAP_PALMTT2 834 -+#define MACH_TYPE_XSCALE_PALMLD 835 -+#define MACH_TYPE_CC9C 836 -+#define MACH_TYPE_SBC1670 837 -+#define MACH_TYPE_IXDP28X5 838 -+#define MACH_TYPE_OMAP_PALMTT 839 -+#define MACH_TYPE_ML696K 840 -+#define MACH_TYPE_ARCOM_ZEUS 841 -+#define MACH_TYPE_OSIRIS 842 -+#define MACH_TYPE_MAESTRO 843 -+#define MACH_TYPE_TUNGE2 844 -+#define MACH_TYPE_IXBBM 845 -+#define MACH_TYPE_MX27 846 -+#define MACH_TYPE_AX8004 847 -+#define MACH_TYPE_AT91SAM9261EK 848 -+#define MACH_TYPE_LOFT 849 -+#define MACH_TYPE_MAGPIE 850 -+#define MACH_TYPE_MX21 851 -+#define MACH_TYPE_MB87M3400 852 -+#define MACH_TYPE_MGUARD_DELTA 853 -+#define MACH_TYPE_DAVINCI_DVDP 854 -+#define MACH_TYPE_HTCUNIVERSAL 855 -+#define MACH_TYPE_TPAD 856 -+#define MACH_TYPE_ROVERP3 857 -+#define MACH_TYPE_JORNADA928 858 -+#define MACH_TYPE_MV88FXX81 859 -+#define MACH_TYPE_STMP36XX 860 -+#define MACH_TYPE_SXNI79524 861 -+#define MACH_TYPE_AMS_DELTA 862 -+#define MACH_TYPE_URANIUM 863 -+#define MACH_TYPE_UCON 864 -+#define MACH_TYPE_NAS100D 865 -+#define MACH_TYPE_L083_1000 866 -+#define MACH_TYPE_EZX 867 -+#define MACH_TYPE_PNX5220 868 -+#define MACH_TYPE_BUTTE 869 -+#define MACH_TYPE_SRM2 870 -+#define MACH_TYPE_DSBR 871 -+#define MACH_TYPE_CRYSTALBALL 872 -+#define MACH_TYPE_TINYPXA27X 873 -+#define MACH_TYPE_HERBIE 874 -+#define MACH_TYPE_MAGICIAN 875 -+#define MACH_TYPE_CM4002 876 -+#define MACH_TYPE_B4 877 -+#define MACH_TYPE_MAUI 878 -+#define MACH_TYPE_CYBERTRACKER_G 879 -+#define MACH_TYPE_NXDKN 880 -+#define MACH_TYPE_MIO8390 881 -+#define MACH_TYPE_OMI_BOARD 882 -+#define MACH_TYPE_MX21CIV 883 -+#define MACH_TYPE_MAHI_CDAC 884 -+#define MACH_TYPE_XSCALE_PALMTX 885 -+#define MACH_TYPE_S3C2413 887 -+#define MACH_TYPE_SAMSYS_EP0 888 -+#define MACH_TYPE_WG302V1 889 -+#define MACH_TYPE_WG302V2 890 -+#define MACH_TYPE_EB42X 891 -+#define MACH_TYPE_IQ331ES 892 -+#define MACH_TYPE_COSYDSP 893 -+#define MACH_TYPE_UPLAT7D 894 -+#define MACH_TYPE_PTDAVINCI 895 -+#define MACH_TYPE_MBUS 896 -+#define MACH_TYPE_NADIA2VB 897 -+#define MACH_TYPE_R1000 898 -+#define MACH_TYPE_HW90250 899 -+#define MACH_TYPE_OMAP_2430SDP 900 -+#define MACH_TYPE_DAVINCI_EVM 901 -+#define MACH_TYPE_OMAP_TORNADO 902 -+#define MACH_TYPE_OLOCREEK 903 -+#define MACH_TYPE_PALMZ72 904 -+#define MACH_TYPE_NXDB500 905 -+#define MACH_TYPE_APF9328 906 -+#define MACH_TYPE_OMAP_WIPOQ 907 -+#define MACH_TYPE_OMAP_TWIP 908 -+#define MACH_TYPE_XSCALE_PALMTREO650 909 -+#define MACH_TYPE_ACUMEN 910 -+#define MACH_TYPE_XP100 911 -+#define MACH_TYPE_FS2410 912 -+#define MACH_TYPE_PXA270_CERF 913 -+#define MACH_TYPE_SQ2FTLPALM 914 -+#define MACH_TYPE_BSEMSERVER 915 -+#define MACH_TYPE_NETCLIENT 916 -+#define MACH_TYPE_XSCALE_PALMTT5 917 -+#define MACH_TYPE_OMAP_PALMTC 918 -+#define MACH_TYPE_OMAP_APOLLON 919 -+#define MACH_TYPE_MXC30030EVB 920 -+#define MACH_TYPE_REA_2D 921 -+#define MACH_TYPE_TI3E524 922 -+#define MACH_TYPE_ATEB9200 923 -+#define MACH_TYPE_AUCKLAND 924 -+#define MACH_TYPE_AK3320M 925 -+#define MACH_TYPE_DURAMAX 926 -+#define MACH_TYPE_N35 927 -+#define MACH_TYPE_PRONGHORN 928 -+#define MACH_TYPE_FUNDY 929 -+#define MACH_TYPE_LOGICPD_PXA270 930 -+#define MACH_TYPE_CPU777 931 -+#define MACH_TYPE_SIMICON9201 932 -+#define MACH_TYPE_LEAP2_HPM 933 -+#define MACH_TYPE_CM922TXA10 934 -+#define MACH_TYPE_PXA 935 -+#define MACH_TYPE_SANDGATE2 936 -+#define MACH_TYPE_SANDGATE2G 937 -+#define MACH_TYPE_SANDGATE2P 938 -+#define MACH_TYPE_FRED_JACK 939 -+#define MACH_TYPE_TTG_COLOR1 940 -+#define MACH_TYPE_NXEB500HMI 941 -+#define MACH_TYPE_NETDCU8 942 -+#define MACH_TYPE_ML675050_CPU_BOA 943 -+#define MACH_TYPE_NG_FVX538 944 -+#define MACH_TYPE_NG_FVS338 945 -+#define MACH_TYPE_PNX4103 946 -+#define MACH_TYPE_HESDB 947 -+#define MACH_TYPE_XSILO 948 -+#define MACH_TYPE_ESPRESSO 949 -+#define MACH_TYPE_EMLC 950 -+#define MACH_TYPE_SISTERON 951 -+#define MACH_TYPE_RX1950 952 -+#define MACH_TYPE_TSC_VENUS 953 -+#define MACH_TYPE_DS101J 954 -+#define MACH_TYPE_MXC30030ADS 955 -+#define MACH_TYPE_FUJITSU_WIMAXSOC 956 -+#define MACH_TYPE_DUALPCMODEM 957 -+#define MACH_TYPE_GESBC9312 958 -+#define MACH_TYPE_HTCAPACHE 959 -+#define MACH_TYPE_IXDP435 960 -+#define MACH_TYPE_CATPROVT100 961 -+#define MACH_TYPE_PICOTUX1XX 962 -+#define MACH_TYPE_PICOTUX2XX 963 -+#define MACH_TYPE_DSMG600 964 -+#define MACH_TYPE_EMPC2 965 -+#define MACH_TYPE_VENTURA 966 -+#define MACH_TYPE_PHIDGET_SBC 967 -+#define MACH_TYPE_IJ3K 968 -+#define MACH_TYPE_PISGAH 969 -+#define MACH_TYPE_OMAP_FSAMPLE 970 -+#define MACH_TYPE_SG720 971 -+#define MACH_TYPE_REDFOX 972 -+#define MACH_TYPE_MYSH_EP9315_1 973 -+#define MACH_TYPE_TPF106 974 -+#define MACH_TYPE_AT91RM9200KG 975 -+#define MACH_TYPE_SLEDB 976 -+#define MACH_TYPE_ONTRACK 977 -+#define MACH_TYPE_PM1200 978 -+#define MACH_TYPE_ESS24XXX 979 -+#define MACH_TYPE_COREMP7 980 -+#define MACH_TYPE_NEXCODER_6446 981 -+#define MACH_TYPE_STVC8380 982 -+#define MACH_TYPE_TEKLYNX 983 -+#define MACH_TYPE_CARBONADO 984 -+#define MACH_TYPE_SYSMOS_MP730 985 -+#define MACH_TYPE_SNAPPER_CL15 986 -+#define MACH_TYPE_PGIGIM 987 -+#define MACH_TYPE_PTX9160P2 988 -+#define MACH_TYPE_DCORE1 989 -+#define MACH_TYPE_VICTORPXA 990 -+#define MACH_TYPE_MX2DTB 991 -+#define MACH_TYPE_PXA_IREX_ER0100 992 -+#define MACH_TYPE_OMAP_PALMZ71 993 -+#define MACH_TYPE_BARTEC_DEG 994 -+#define MACH_TYPE_HW50251 995 -+#define MACH_TYPE_IBOX 996 -+#define MACH_TYPE_ATLASLH7A404 997 -+#define MACH_TYPE_PT2026 998 -+#define MACH_TYPE_HTCALPINE 999 -+#define MACH_TYPE_BARTEC_VTU 1000 -+#define MACH_TYPE_VCOREII 1001 -+#define MACH_TYPE_PDNB3 1002 -+#define MACH_TYPE_HTCBEETLES 1003 -+#define MACH_TYPE_S3C6400 1004 -+#define MACH_TYPE_S3C2443 1005 -+#define MACH_TYPE_OMAP_LDK 1006 -+#define MACH_TYPE_SMDK2460 1007 -+#define MACH_TYPE_SMDK2440 1008 -+#define MACH_TYPE_SMDK2412 1009 -+#define MACH_TYPE_WEBBOX 1010 -+#define MACH_TYPE_CWWNDP 1011 -+#define MACH_TYPE_DRAGON 1012 -+#define MACH_TYPE_OPENDO_CPU_BOARD 1013 -+#define MACH_TYPE_CCM2200 1014 -+#define MACH_TYPE_ETWARM 1015 -+#define MACH_TYPE_M93030 1016 -+#define MACH_TYPE_CC7U 1017 -+#define MACH_TYPE_MTT_RANGER 1018 -+#define MACH_TYPE_NEXUS 1019 -+#define MACH_TYPE_DESMAN 1020 -+#define MACH_TYPE_BKDE303 1021 -+#define MACH_TYPE_SMDK2413 1022 -+#define MACH_TYPE_AML_M7200 1023 -+#define MACH_TYPE_AML_M5900 1024 -+#define MACH_TYPE_SG640 1025 -+#define MACH_TYPE_EDG79524 1026 -+#define MACH_TYPE_AI2410 1027 -+#define MACH_TYPE_IXP465 1028 -+#define MACH_TYPE_BALLOON3 1029 -+#define MACH_TYPE_HEINS 1030 -+#define MACH_TYPE_MPLUSEVA 1031 -+#define MACH_TYPE_RT042 1032 -+#define MACH_TYPE_CWIEM 1033 -+#define MACH_TYPE_CM_X270 1034 -+#define MACH_TYPE_CM_X255 1035 -+#define MACH_TYPE_ESH_AT91 1036 -+#define MACH_TYPE_SANDGATE3 1037 -+#define MACH_TYPE_PRIMO 1038 -+#define MACH_TYPE_GEMSTONE 1039 -+#define MACH_TYPE_PRONGHORNMETRO 1040 -+#define MACH_TYPE_SIDEWINDER 1041 -+#define MACH_TYPE_PICOMOD1 1042 -+#define MACH_TYPE_SG590 1043 -+#define MACH_TYPE_AKAI9307 1044 -+#define MACH_TYPE_FONTAINE 1045 -+#define MACH_TYPE_WOMBAT 1046 -+#define MACH_TYPE_ACQ300 1047 -+#define MACH_TYPE_MOD_270 1048 -+#define MACH_TYPE_VC0820 1049 -+#define MACH_TYPE_ANI_AIM 1050 -+#define MACH_TYPE_JELLYFISH 1051 -+#define MACH_TYPE_AMANITA 1052 -+#define MACH_TYPE_VLINK 1053 - - #ifdef CONFIG_ARCH_EBSA110 - # ifdef machine_arch_type -@@ -3540,9 +3865,9 @@ - # else - # define machine_arch_type MACH_TYPE_RAMSES - # endif --# define machine_is_ramses() (machine_arch_type == MACH_TYPE_RAMSES) -+# define machine_is_mnci() (machine_arch_type == MACH_TYPE_RAMSES) - #else --# define machine_is_ramses() (0) -+# define machine_is_mnci() (0) - #endif - - #ifdef CONFIG_ARCH_S28X -@@ -4500,9 +4825,9 @@ - # else - # define machine_arch_type MACH_TYPE_M825XX - # endif --# define machine_is_m825xx() (machine_arch_type == MACH_TYPE_M825XX) -+# define machine_is_comcerto() (machine_arch_type == MACH_TYPE_M825XX) - #else --# define machine_is_m825xx() (0) -+# define machine_is_comcerto() (0) - #endif - - #ifdef CONFIG_SA1100_M7100 -@@ -5657,16 +5982,16 @@ - # define machine_is_xcep() (0) - #endif - --#ifdef CONFIG_MACH_ARCOM_MERCURY -+#ifdef CONFIG_MACH_ARCOM_VULCAN - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_ARCOM_MERCURY -+# define machine_arch_type MACH_TYPE_ARCOM_VULCAN - # endif --# define machine_is_arcom_mercury() (machine_arch_type == MACH_TYPE_ARCOM_MERCURY) -+# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN) - #else --# define machine_is_arcom_mercury() (0) -+# define machine_is_arcom_vulcan() (0) - #endif - - #ifdef CONFIG_MACH_STARGATE -@@ -6053,16 +6378,16 @@ - # define machine_is_ess710() (0) - #endif - --#ifdef CONFIG_MACH_MX3ADS -+#ifdef CONFIG_MACH_MX31ADS - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_MX3ADS -+# define machine_arch_type MACH_TYPE_MX31ADS - # endif --# define machine_is_mx3ads() (machine_arch_type == MACH_TYPE_MX3ADS) -+# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS) - #else --# define machine_is_mx3ads() (0) -+# define machine_is_mx31ads() (0) - #endif - - #ifdef CONFIG_MACH_HIMALAYA -@@ -7325,28 +7650,28 @@ - # define machine_is_saturn() (0) - #endif - --#ifdef CONFIG_MACH_ARGONPLUSEVB -+#ifdef CONFIG_MACH_I30030EVB - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_ARGONPLUSEVB -+# define machine_arch_type MACH_TYPE_I30030EVB - # endif --# define machine_is_argonplusevb() (machine_arch_type == MACH_TYPE_ARGONPLUSEVB) -+# define machine_is_i30030evb() (machine_arch_type == MACH_TYPE_I30030EVB) - #else --# define machine_is_argonplusevb() (0) -+# define machine_is_i30030evb() (0) - #endif - --#ifdef CONFIG_MACH_SCMA11EVB -+#ifdef CONFIG_MACH_MXC27530EVB - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_SCMA11EVB -+# define machine_arch_type MACH_TYPE_MXC27530EVB - # endif --# define machine_is_scma11evb() (machine_arch_type == MACH_TYPE_SCMA11EVB) -+# define machine_is_mxc27530evb() (machine_arch_type == MACH_TYPE_MXC27530EVB) - #else --# define machine_is_scma11evb() (0) -+# define machine_is_mxc27530evb() (0) - #endif - - #ifdef CONFIG_MACH_SMDK2800 -@@ -8297,16 +8622,16 @@ - # define machine_is_hrdisplay() (0) - #endif - --#ifdef CONFIG_MACH_SCMA11BB -+#ifdef CONFIG_MACH_MXC27530ADS - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_SCMA11BB -+# define machine_arch_type MACH_TYPE_MXC27530ADS - # endif --# define machine_is_scma11bb() (machine_arch_type == MACH_TYPE_SCMA11BB) -+# define machine_is_mxc27530ads() (machine_arch_type == MACH_TYPE_MXC27530ADS) - #else --# define machine_is_scma11bb() (0) -+# define machine_is_mxc27530ads() (0) - #endif - - #ifdef CONFIG_MACH_TRIZEPS3 -@@ -9185,16 +9510,16 @@ - # define machine_is_hx2750() (0) - #endif - --#ifdef CONFIG_MACH_ZEUSEVB -+#ifdef CONFIG_MACH_MXC91131EVB - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_ZEUSEVB -+# define machine_arch_type MACH_TYPE_MXC91131EVB - # endif --# define machine_is_zeusevb() (machine_arch_type == MACH_TYPE_ZEUSEVB) -+# define machine_is_mxc91131evb() (machine_arch_type == MACH_TYPE_MXC91131EVB) - #else --# define machine_is_zeusevb() (0) -+# define machine_is_mxc91131evb() (0) - #endif - - #ifdef CONFIG_MACH_P700 -@@ -9401,6 +9726,3906 @@ - # define machine_is_mp2usb() (0) - #endif - -+#ifdef CONFIG_MACH_NTNP425C -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NTNP425C -+# endif -+# define machine_is_ntnp425c() (machine_arch_type == MACH_TYPE_NTNP425C) -+#else -+# define machine_is_ntnp425c() (0) -+#endif -+ -+#ifdef CONFIG_MACH_COLIBRI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_COLIBRI -+# endif -+# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI) -+#else -+# define machine_is_colibri() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PCM7220 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PCM7220 -+# endif -+# define machine_is_pcm7220() (machine_arch_type == MACH_TYPE_PCM7220) -+#else -+# define machine_is_pcm7220() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GATEWAY7001 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GATEWAY7001 -+# endif -+# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001) -+#else -+# define machine_is_gateway7001() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PCM027 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PCM027 -+# endif -+# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027) -+#else -+# define machine_is_pcm027() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CMPXA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CMPXA -+# endif -+# define machine_is_cmpxa() (machine_arch_type == MACH_TYPE_CMPXA) -+#else -+# define machine_is_cmpxa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ANUBIS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ANUBIS -+# endif -+# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS) -+#else -+# define machine_is_anubis() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ITE8152 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ITE8152 -+# endif -+# define machine_is_ite8152() (machine_arch_type == MACH_TYPE_ITE8152) -+#else -+# define machine_is_ite8152() (0) -+#endif -+ -+#ifdef CONFIG_MACH_LPC3XXX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_LPC3XXX -+# endif -+# define machine_is_lpc3xxx() (machine_arch_type == MACH_TYPE_LPC3XXX) -+#else -+# define machine_is_lpc3xxx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PUPPETEER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PUPPETEER -+# endif -+# define machine_is_puppeteer() (machine_arch_type == MACH_TYPE_PUPPETEER) -+#else -+# define machine_is_puppeteer() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MACH_VADATECH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MACH_VADATECH -+# endif -+# define machine_is_vt001() (machine_arch_type == MACH_TYPE_MACH_VADATECH) -+#else -+# define machine_is_vt001() (0) -+#endif -+ -+#ifdef CONFIG_MACH_E570 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_E570 -+# endif -+# define machine_is_e570() (machine_arch_type == MACH_TYPE_E570) -+#else -+# define machine_is_e570() (0) -+#endif -+ -+#ifdef CONFIG_MACH_X50 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_X50 -+# endif -+# define machine_is_x50() (machine_arch_type == MACH_TYPE_X50) -+#else -+# define machine_is_x50() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RECON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RECON -+# endif -+# define machine_is_recon() (machine_arch_type == MACH_TYPE_RECON) -+#else -+# define machine_is_recon() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XBOARDGP8 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XBOARDGP8 -+# endif -+# define machine_is_xboardgp8() (machine_arch_type == MACH_TYPE_XBOARDGP8) -+#else -+# define machine_is_xboardgp8() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FPIC2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FPIC2 -+# endif -+# define machine_is_fpic2() (machine_arch_type == MACH_TYPE_FPIC2) -+#else -+# define machine_is_fpic2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AKITA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AKITA -+# endif -+# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA) -+#else -+# define machine_is_akita() (0) -+#endif -+ -+#ifdef CONFIG_MACH_A81 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_A81 -+# endif -+# define machine_is_a81() (machine_arch_type == MACH_TYPE_A81) -+#else -+# define machine_is_a81() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SVM_SC25X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SVM_SC25X -+# endif -+# define machine_is_svm_sc25x() (machine_arch_type == MACH_TYPE_SVM_SC25X) -+#else -+# define machine_is_svm_sc25x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VADATECH020 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VADATECH020 -+# endif -+# define machine_is_vt020() (machine_arch_type == MACH_TYPE_VADATECH020) -+#else -+# define machine_is_vt020() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TLI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TLI -+# endif -+# define machine_is_tli() (machine_arch_type == MACH_TYPE_TLI) -+#else -+# define machine_is_tli() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EDB9315LC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EDB9315LC -+# endif -+# define machine_is_edb9315lc() (machine_arch_type == MACH_TYPE_EDB9315LC) -+#else -+# define machine_is_edb9315lc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PASSEC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PASSEC -+# endif -+# define machine_is_passec() (machine_arch_type == MACH_TYPE_PASSEC) -+#else -+# define machine_is_passec() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DS_TIGER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DS_TIGER -+# endif -+# define machine_is_ds_tiger() (machine_arch_type == MACH_TYPE_DS_TIGER) -+#else -+# define machine_is_ds_tiger() (0) -+#endif -+ -+#ifdef CONFIG_MACH_E310 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_E310 -+# endif -+# define machine_is_e310() (machine_arch_type == MACH_TYPE_E310) -+#else -+# define machine_is_e310() (0) -+#endif -+ -+#ifdef CONFIG_MACH_E330 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_E330 -+# endif -+# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330) -+#else -+# define machine_is_e330() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RT3000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RT3000 -+# endif -+# define machine_is_rt3000() (machine_arch_type == MACH_TYPE_RT3000) -+#else -+# define machine_is_rt3000() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NOKIA770 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NOKIA770 -+# endif -+# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770) -+#else -+# define machine_is_nokia770() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PNX0106 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PNX0106 -+# endif -+# define machine_is_pnx0106() (machine_arch_type == MACH_TYPE_PNX0106) -+#else -+# define machine_is_pnx0106() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HX21XX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HX21XX -+# endif -+# define machine_is_hx21xx() (machine_arch_type == MACH_TYPE_HX21XX) -+#else -+# define machine_is_hx21xx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FARADAY -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FARADAY -+# endif -+# define machine_is_faraday() (machine_arch_type == MACH_TYPE_FARADAY) -+#else -+# define machine_is_faraday() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SBC9312 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SBC9312 -+# endif -+# define machine_is_sbc9312() (machine_arch_type == MACH_TYPE_SBC9312) -+#else -+# define machine_is_sbc9312() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BATMAN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BATMAN -+# endif -+# define machine_is_batman() (machine_arch_type == MACH_TYPE_BATMAN) -+#else -+# define machine_is_batman() (0) -+#endif -+ -+#ifdef CONFIG_MACH_JPD201 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_JPD201 -+# endif -+# define machine_is_jpd201() (machine_arch_type == MACH_TYPE_JPD201) -+#else -+# define machine_is_jpd201() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MIPSA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MIPSA -+# endif -+# define machine_is_mipsa() (machine_arch_type == MACH_TYPE_MIPSA) -+#else -+# define machine_is_mipsa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_KACOM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_KACOM -+# endif -+# define machine_is_kacom() (machine_arch_type == MACH_TYPE_KACOM) -+#else -+# define machine_is_kacom() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SWARCOCPU -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SWARCOCPU -+# endif -+# define machine_is_swarcocpu() (machine_arch_type == MACH_TYPE_SWARCOCPU) -+#else -+# define machine_is_swarcocpu() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SWARCODSL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SWARCODSL -+# endif -+# define machine_is_swarcodsl() (machine_arch_type == MACH_TYPE_SWARCODSL) -+#else -+# define machine_is_swarcodsl() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BLUEANGEL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BLUEANGEL -+# endif -+# define machine_is_blueangel() (machine_arch_type == MACH_TYPE_BLUEANGEL) -+#else -+# define machine_is_blueangel() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HAIRYGRAMA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HAIRYGRAMA -+# endif -+# define machine_is_hairygrama() (machine_arch_type == MACH_TYPE_HAIRYGRAMA) -+#else -+# define machine_is_hairygrama() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BANFF -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BANFF -+# endif -+# define machine_is_banff() (machine_arch_type == MACH_TYPE_BANFF) -+#else -+# define machine_is_banff() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CARMEVA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CARMEVA -+# endif -+# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA) -+#else -+# define machine_is_carmeva() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SAM255 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SAM255 -+# endif -+# define machine_is_sam255() (machine_arch_type == MACH_TYPE_SAM255) -+#else -+# define machine_is_sam255() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PPM10 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PPM10 -+# endif -+# define machine_is_ppm10() (machine_arch_type == MACH_TYPE_PPM10) -+#else -+# define machine_is_ppm10() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EDB9315A -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EDB9315A -+# endif -+# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A) -+#else -+# define machine_is_edb9315a() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SUNSET -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SUNSET -+# endif -+# define machine_is_sunset() (machine_arch_type == MACH_TYPE_SUNSET) -+#else -+# define machine_is_sunset() (0) -+#endif -+ -+#ifdef CONFIG_MACH_STARGATE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_STARGATE2 -+# endif -+# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2) -+#else -+# define machine_is_stargate2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_INTELMOTE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_INTELMOTE2 -+# endif -+# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2) -+#else -+# define machine_is_intelmote2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TRIZEPS4 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TRIZEPS4 -+# endif -+# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4) -+#else -+# define machine_is_trizeps4() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAINSTONE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAINSTONE2 -+# endif -+# define machine_is_mainstone2() (machine_arch_type == MACH_TYPE_MAINSTONE2) -+#else -+# define machine_is_mainstone2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EZ_IXP42X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EZ_IXP42X -+# endif -+# define machine_is_ez_ixp42x() (machine_arch_type == MACH_TYPE_EZ_IXP42X) -+#else -+# define machine_is_ez_ixp42x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TAPWAVE_ZODIAC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TAPWAVE_ZODIAC -+# endif -+# define machine_is_tapwave_zodiac() (machine_arch_type == MACH_TYPE_TAPWAVE_ZODIAC) -+#else -+# define machine_is_tapwave_zodiac() (0) -+#endif -+ -+#ifdef CONFIG_MACH_UNIVERSALMETER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_UNIVERSALMETER -+# endif -+# define machine_is_universalmeter() (machine_arch_type == MACH_TYPE_UNIVERSALMETER) -+#else -+# define machine_is_universalmeter() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HICOARM9 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HICOARM9 -+# endif -+# define machine_is_hicoarm9() (machine_arch_type == MACH_TYPE_HICOARM9) -+#else -+# define machine_is_hicoarm9() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PNX4008 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PNX4008 -+# endif -+# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008) -+#else -+# define machine_is_pnx4008() (0) -+#endif -+ -+#ifdef CONFIG_MACH_KWS6000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_KWS6000 -+# endif -+# define machine_is_kws6000() (machine_arch_type == MACH_TYPE_KWS6000) -+#else -+# define machine_is_kws6000() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PORTUX920T -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PORTUX920T -+# endif -+# define machine_is_portux920t() (machine_arch_type == MACH_TYPE_PORTUX920T) -+#else -+# define machine_is_portux920t() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EZ_X5 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EZ_X5 -+# endif -+# define machine_is_ez_x5() (machine_arch_type == MACH_TYPE_EZ_X5) -+#else -+# define machine_is_ez_x5() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_RUDOLPH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_RUDOLPH -+# endif -+# define machine_is_omap_rudolph() (machine_arch_type == MACH_TYPE_OMAP_RUDOLPH) -+#else -+# define machine_is_omap_rudolph() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CPUAT91 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CPUAT91 -+# endif -+# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) -+#else -+# define machine_is_cpuat91() (0) -+#endif -+ -+#ifdef CONFIG_MACH_REA9200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_REA9200 -+# endif -+# define machine_is_rea9200() (machine_arch_type == MACH_TYPE_REA9200) -+#else -+# define machine_is_rea9200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ACTS_PUNE_SA1110 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ACTS_PUNE_SA1110 -+# endif -+# define machine_is_acts_pune_sa1110() (machine_arch_type == MACH_TYPE_ACTS_PUNE_SA1110) -+#else -+# define machine_is_acts_pune_sa1110() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXP425 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXP425 -+# endif -+# define machine_is_ixp425() (machine_arch_type == MACH_TYPE_IXP425) -+#else -+# define machine_is_ixp425() (0) -+#endif -+ -+#ifdef CONFIG_MACH_I30030ADS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_I30030ADS -+# endif -+# define machine_is_i30030ads() (machine_arch_type == MACH_TYPE_I30030ADS) -+#else -+# define machine_is_i30030ads() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PERCH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PERCH -+# endif -+# define machine_is_perch() (machine_arch_type == MACH_TYPE_PERCH) -+#else -+# define machine_is_perch() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EIS05R1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EIS05R1 -+# endif -+# define machine_is_eis05r1() (machine_arch_type == MACH_TYPE_EIS05R1) -+#else -+# define machine_is_eis05r1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PEPPERPAD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PEPPERPAD -+# endif -+# define machine_is_pepperpad() (machine_arch_type == MACH_TYPE_PEPPERPAD) -+#else -+# define machine_is_pepperpad() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SB3010 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SB3010 -+# endif -+# define machine_is_sb3010() (machine_arch_type == MACH_TYPE_SB3010) -+#else -+# define machine_is_sb3010() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RM9200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RM9200 -+# endif -+# define machine_is_rm9200() (machine_arch_type == MACH_TYPE_RM9200) -+#else -+# define machine_is_rm9200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DMA03 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DMA03 -+# endif -+# define machine_is_dma03() (machine_arch_type == MACH_TYPE_DMA03) -+#else -+# define machine_is_dma03() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ROAD_S101 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ROAD_S101 -+# endif -+# define machine_is_road_s101() (machine_arch_type == MACH_TYPE_ROAD_S101) -+#else -+# define machine_is_road_s101() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_A -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_A -+# endif -+# define machine_is_iq_nextgen_a() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_A) -+#else -+# define machine_is_iq_nextgen_a() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_B -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_B -+# endif -+# define machine_is_iq_nextgen_b() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_B) -+#else -+# define machine_is_iq_nextgen_b() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_C -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_C -+# endif -+# define machine_is_iq_nextgen_c() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_C) -+#else -+# define machine_is_iq_nextgen_c() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_D -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_D -+# endif -+# define machine_is_iq_nextgen_d() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_D) -+#else -+# define machine_is_iq_nextgen_d() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_E -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_E -+# endif -+# define machine_is_iq_nextgen_e() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_E) -+#else -+# define machine_is_iq_nextgen_e() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MALLOW_AT91 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MALLOW_AT91 -+# endif -+# define machine_is_mallow_at91() (machine_arch_type == MACH_TYPE_MALLOW_AT91) -+#else -+# define machine_is_mallow_at91() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CYBERTRACKER_I -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CYBERTRACKER_I -+# endif -+# define machine_is_cybertracker_i() (machine_arch_type == MACH_TYPE_CYBERTRACKER_I) -+#else -+# define machine_is_cybertracker_i() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GESBC931X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GESBC931X -+# endif -+# define machine_is_gesbc931x() (machine_arch_type == MACH_TYPE_GESBC931X) -+#else -+# define machine_is_gesbc931x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CENTIPAD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CENTIPAD -+# endif -+# define machine_is_centipad() (machine_arch_type == MACH_TYPE_CENTIPAD) -+#else -+# define machine_is_centipad() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ARMSOC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ARMSOC -+# endif -+# define machine_is_armsoc() (machine_arch_type == MACH_TYPE_ARMSOC) -+#else -+# define machine_is_armsoc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SE4200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SE4200 -+# endif -+# define machine_is_se4200() (machine_arch_type == MACH_TYPE_SE4200) -+#else -+# define machine_is_se4200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EMS197A -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EMS197A -+# endif -+# define machine_is_ems197a() (machine_arch_type == MACH_TYPE_EMS197A) -+#else -+# define machine_is_ems197a() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MICRO9 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MICRO9 -+# endif -+# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9) -+#else -+# define machine_is_micro9() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MICRO9L -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MICRO9L -+# endif -+# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L) -+#else -+# define machine_is_micro9l() (0) -+#endif -+ -+#ifdef CONFIG_MACH_UC5471DSP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_UC5471DSP -+# endif -+# define machine_is_uc5471dsp() (machine_arch_type == MACH_TYPE_UC5471DSP) -+#else -+# define machine_is_uc5471dsp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SJ5471ENG -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SJ5471ENG -+# endif -+# define machine_is_sj5471eng() (machine_arch_type == MACH_TYPE_SJ5471ENG) -+#else -+# define machine_is_sj5471eng() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CMPXA26X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CMPXA26X -+# endif -+# define machine_is_none() (machine_arch_type == MACH_TYPE_CMPXA26X) -+#else -+# define machine_is_none() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NC -+# endif -+# define machine_is_nc1() (machine_arch_type == MACH_TYPE_NC) -+#else -+# define machine_is_nc1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMTE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMTE -+# endif -+# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE) -+#else -+# define machine_is_omap_palmte() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AJAX52X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AJAX52X -+# endif -+# define machine_is_ajax52x() (machine_arch_type == MACH_TYPE_AJAX52X) -+#else -+# define machine_is_ajax52x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SIRIUSTAR -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SIRIUSTAR -+# endif -+# define machine_is_siriustar() (machine_arch_type == MACH_TYPE_SIRIUSTAR) -+#else -+# define machine_is_siriustar() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IODATA_HDLG -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IODATA_HDLG -+# endif -+# define machine_is_iodata_hdlg() (machine_arch_type == MACH_TYPE_IODATA_HDLG) -+#else -+# define machine_is_iodata_hdlg() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AT91RM9200UTL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AT91RM9200UTL -+# endif -+# define machine_is_at91rm9200utl() (machine_arch_type == MACH_TYPE_AT91RM9200UTL) -+#else -+# define machine_is_at91rm9200utl() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BIOSAFE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BIOSAFE -+# endif -+# define machine_is_biosafe() (machine_arch_type == MACH_TYPE_BIOSAFE) -+#else -+# define machine_is_biosafe() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MP1000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MP1000 -+# endif -+# define machine_is_mp1000() (machine_arch_type == MACH_TYPE_MP1000) -+#else -+# define machine_is_mp1000() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PARSY -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PARSY -+# endif -+# define machine_is_parsy() (machine_arch_type == MACH_TYPE_PARSY) -+#else -+# define machine_is_parsy() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CCXP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CCXP -+# endif -+# define machine_is_ccxp270() (machine_arch_type == MACH_TYPE_CCXP) -+#else -+# define machine_is_ccxp270() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_GSAMPLE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_GSAMPLE -+# endif -+# define machine_is_omap_gsample() (machine_arch_type == MACH_TYPE_OMAP_GSAMPLE) -+#else -+# define machine_is_omap_gsample() (0) -+#endif -+ -+#ifdef CONFIG_MACH_REALVIEW_EB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_REALVIEW_EB -+# endif -+# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB) -+#else -+# define machine_is_realview_eb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SAMOA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SAMOA -+# endif -+# define machine_is_samoa() (machine_arch_type == MACH_TYPE_SAMOA) -+#else -+# define machine_is_samoa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_T3XSCALE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_T3XSCALE -+# endif -+# define machine_is_t3xscale() (machine_arch_type == MACH_TYPE_T3XSCALE) -+#else -+# define machine_is_t3xscale() (0) -+#endif -+ -+#ifdef CONFIG_MACH_I878 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_I878 -+# endif -+# define machine_is_i878() (machine_arch_type == MACH_TYPE_I878) -+#else -+# define machine_is_i878() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BORZOI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BORZOI -+# endif -+# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI) -+#else -+# define machine_is_borzoi() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GECKO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GECKO -+# endif -+# define machine_is_gecko() (machine_arch_type == MACH_TYPE_GECKO) -+#else -+# define machine_is_gecko() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DS101 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DS101 -+# endif -+# define machine_is_ds101() (machine_arch_type == MACH_TYPE_DS101) -+#else -+# define machine_is_ds101() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMTT2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMTT2 -+# endif -+# define machine_is_omap_palmtt2() (machine_arch_type == MACH_TYPE_OMAP_PALMTT2) -+#else -+# define machine_is_omap_palmtt2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSCALE_PALMLD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSCALE_PALMLD -+# endif -+# define machine_is_xscale_palmld() (machine_arch_type == MACH_TYPE_XSCALE_PALMLD) -+#else -+# define machine_is_xscale_palmld() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CC9C -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CC9C -+# endif -+# define machine_is_cc9c() (machine_arch_type == MACH_TYPE_CC9C) -+#else -+# define machine_is_cc9c() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SBC1670 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SBC1670 -+# endif -+# define machine_is_sbc1670() (machine_arch_type == MACH_TYPE_SBC1670) -+#else -+# define machine_is_sbc1670() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXDP28X5 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXDP28X5 -+# endif -+# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5) -+#else -+# define machine_is_ixdp28x5() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMTT -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMTT -+# endif -+# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT) -+#else -+# define machine_is_omap_palmtt() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ML696K -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ML696K -+# endif -+# define machine_is_ml696k() (machine_arch_type == MACH_TYPE_ML696K) -+#else -+# define machine_is_ml696k() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ARCOM_ZEUS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ARCOM_ZEUS -+# endif -+# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS) -+#else -+# define machine_is_arcom_zeus() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OSIRIS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OSIRIS -+# endif -+# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS) -+#else -+# define machine_is_osiris() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAESTRO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAESTRO -+# endif -+# define machine_is_maestro() (machine_arch_type == MACH_TYPE_MAESTRO) -+#else -+# define machine_is_maestro() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TUNGE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TUNGE2 -+# endif -+# define machine_is_tunge2() (machine_arch_type == MACH_TYPE_TUNGE2) -+#else -+# define machine_is_tunge2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXBBM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXBBM -+# endif -+# define machine_is_ixbbm() (machine_arch_type == MACH_TYPE_IXBBM) -+#else -+# define machine_is_ixbbm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MX27 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MX27 -+# endif -+# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27) -+#else -+# define machine_is_mx27ads() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AX8004 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AX8004 -+# endif -+# define machine_is_ax8004() (machine_arch_type == MACH_TYPE_AX8004) -+#else -+# define machine_is_ax8004() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AT91SAM9261EK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AT91SAM9261EK -+# endif -+# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK) -+#else -+# define machine_is_at91sam9261ek() (0) -+#endif -+ -+#ifdef CONFIG_MACH_LOFT -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_LOFT -+# endif -+# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT) -+#else -+# define machine_is_loft() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAGPIE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAGPIE -+# endif -+# define machine_is_magpie() (machine_arch_type == MACH_TYPE_MAGPIE) -+#else -+# define machine_is_magpie() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MX21 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MX21 -+# endif -+# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21) -+#else -+# define machine_is_mx21ads() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MB87M3400 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MB87M3400 -+# endif -+# define machine_is_mb87m3400() (machine_arch_type == MACH_TYPE_MB87M3400) -+#else -+# define machine_is_mb87m3400() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MGUARD_DELTA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MGUARD_DELTA -+# endif -+# define machine_is_mguard_delta() (machine_arch_type == MACH_TYPE_MGUARD_DELTA) -+#else -+# define machine_is_mguard_delta() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DAVINCI_DVDP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DAVINCI_DVDP -+# endif -+# define machine_is_davinci_dvdp() (machine_arch_type == MACH_TYPE_DAVINCI_DVDP) -+#else -+# define machine_is_davinci_dvdp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HTCUNIVERSAL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HTCUNIVERSAL -+# endif -+# define machine_is_htcuniversal() (machine_arch_type == MACH_TYPE_HTCUNIVERSAL) -+#else -+# define machine_is_htcuniversal() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TPAD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TPAD -+# endif -+# define machine_is_tpad() (machine_arch_type == MACH_TYPE_TPAD) -+#else -+# define machine_is_tpad() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ROVERP3 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ROVERP3 -+# endif -+# define machine_is_roverp3() (machine_arch_type == MACH_TYPE_ROVERP3) -+#else -+# define machine_is_roverp3() (0) -+#endif -+ -+#ifdef CONFIG_MACH_JORNADA928 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_JORNADA928 -+# endif -+# define machine_is_jornada928() (machine_arch_type == MACH_TYPE_JORNADA928) -+#else -+# define machine_is_jornada928() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MV88FXX81 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MV88FXX81 -+# endif -+# define machine_is_mv88fxx81() (machine_arch_type == MACH_TYPE_MV88FXX81) -+#else -+# define machine_is_mv88fxx81() (0) -+#endif -+ -+#ifdef CONFIG_MACH_STMP36XX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_STMP36XX -+# endif -+# define machine_is_stmp36xx() (machine_arch_type == MACH_TYPE_STMP36XX) -+#else -+# define machine_is_stmp36xx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SXNI79524 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SXNI79524 -+# endif -+# define machine_is_sxni79524() (machine_arch_type == MACH_TYPE_SXNI79524) -+#else -+# define machine_is_sxni79524() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AMS_DELTA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AMS_DELTA -+# endif -+# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA) -+#else -+# define machine_is_ams_delta() (0) -+#endif -+ -+#ifdef CONFIG_MACH_URANIUM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_URANIUM -+# endif -+# define machine_is_uranium() (machine_arch_type == MACH_TYPE_URANIUM) -+#else -+# define machine_is_uranium() (0) -+#endif -+ -+#ifdef CONFIG_MACH_UCON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_UCON -+# endif -+# define machine_is_ucon() (machine_arch_type == MACH_TYPE_UCON) -+#else -+# define machine_is_ucon() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NAS100D -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NAS100D -+# endif -+# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D) -+#else -+# define machine_is_nas100d() (0) -+#endif -+ -+#ifdef CONFIG_MACH_L083_1000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_L083_1000 -+# endif -+# define machine_is_l083() (machine_arch_type == MACH_TYPE_L083_1000) -+#else -+# define machine_is_l083() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EZX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EZX -+# endif -+# define machine_is_ezx() (machine_arch_type == MACH_TYPE_EZX) -+#else -+# define machine_is_ezx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PNX5220 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PNX5220 -+# endif -+# define machine_is_pnx5220() (machine_arch_type == MACH_TYPE_PNX5220) -+#else -+# define machine_is_pnx5220() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BUTTE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BUTTE -+# endif -+# define machine_is_butte() (machine_arch_type == MACH_TYPE_BUTTE) -+#else -+# define machine_is_butte() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SRM2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SRM2 -+# endif -+# define machine_is_srm2() (machine_arch_type == MACH_TYPE_SRM2) -+#else -+# define machine_is_srm2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DSBR -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DSBR -+# endif -+# define machine_is_dsbr() (machine_arch_type == MACH_TYPE_DSBR) -+#else -+# define machine_is_dsbr() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CRYSTALBALL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CRYSTALBALL -+# endif -+# define machine_is_crystalball() (machine_arch_type == MACH_TYPE_CRYSTALBALL) -+#else -+# define machine_is_crystalball() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TINYPXA27X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TINYPXA27X -+# endif -+# define machine_is_tinypxa27x() (machine_arch_type == MACH_TYPE_TINYPXA27X) -+#else -+# define machine_is_tinypxa27x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HERBIE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HERBIE -+# endif -+# define machine_is_herbie() (machine_arch_type == MACH_TYPE_HERBIE) -+#else -+# define machine_is_herbie() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAGICIAN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAGICIAN -+# endif -+# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN) -+#else -+# define machine_is_magician() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CM4002 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CM4002 -+# endif -+# define machine_is_cm4002() (machine_arch_type == MACH_TYPE_CM4002) -+#else -+# define machine_is_cm4002() (0) -+#endif -+ -+#ifdef CONFIG_MACH_B4 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_B4 -+# endif -+# define machine_is_b4() (machine_arch_type == MACH_TYPE_B4) -+#else -+# define machine_is_b4() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAUI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAUI -+# endif -+# define machine_is_maui() (machine_arch_type == MACH_TYPE_MAUI) -+#else -+# define machine_is_maui() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CYBERTRACKER_G -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CYBERTRACKER_G -+# endif -+# define machine_is_cybertracker_g() (machine_arch_type == MACH_TYPE_CYBERTRACKER_G) -+#else -+# define machine_is_cybertracker_g() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NXDKN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NXDKN -+# endif -+# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN) -+#else -+# define machine_is_nxdkn() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MIO8390 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MIO8390 -+# endif -+# define machine_is_mio8390() (machine_arch_type == MACH_TYPE_MIO8390) -+#else -+# define machine_is_mio8390() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMI_BOARD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMI_BOARD -+# endif -+# define machine_is_omi_board() (machine_arch_type == MACH_TYPE_OMI_BOARD) -+#else -+# define machine_is_omi_board() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MX21CIV -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MX21CIV -+# endif -+# define machine_is_mx21civ() (machine_arch_type == MACH_TYPE_MX21CIV) -+#else -+# define machine_is_mx21civ() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAHI_CDAC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAHI_CDAC -+# endif -+# define machine_is_mahi_cdac() (machine_arch_type == MACH_TYPE_MAHI_CDAC) -+#else -+# define machine_is_mahi_cdac() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSCALE_PALMTX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSCALE_PALMTX -+# endif -+# define machine_is_xscale_palmtx() (machine_arch_type == MACH_TYPE_XSCALE_PALMTX) -+#else -+# define machine_is_xscale_palmtx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_S3C2413 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_S3C2413 -+# endif -+# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413) -+#else -+# define machine_is_s3c2413() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SAMSYS_EP0 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SAMSYS_EP0 -+# endif -+# define machine_is_samsys_ep0() (machine_arch_type == MACH_TYPE_SAMSYS_EP0) -+#else -+# define machine_is_samsys_ep0() (0) -+#endif -+ -+#ifdef CONFIG_MACH_WG302V1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_WG302V1 -+# endif -+# define machine_is_wg302v1() (machine_arch_type == MACH_TYPE_WG302V1) -+#else -+# define machine_is_wg302v1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_WG302V2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_WG302V2 -+# endif -+# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2) -+#else -+# define machine_is_wg302v2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EB42X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EB42X -+# endif -+# define machine_is_eb42x() (machine_arch_type == MACH_TYPE_EB42X) -+#else -+# define machine_is_eb42x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ331ES -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ331ES -+# endif -+# define machine_is_iq331es() (machine_arch_type == MACH_TYPE_IQ331ES) -+#else -+# define machine_is_iq331es() (0) -+#endif -+ -+#ifdef CONFIG_MACH_COSYDSP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_COSYDSP -+# endif -+# define machine_is_cosydsp() (machine_arch_type == MACH_TYPE_COSYDSP) -+#else -+# define machine_is_cosydsp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_UPLAT7D -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_UPLAT7D -+# endif -+# define machine_is_uplat7d_proto() (machine_arch_type == MACH_TYPE_UPLAT7D) -+#else -+# define machine_is_uplat7d_proto() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PTDAVINCI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PTDAVINCI -+# endif -+# define machine_is_ptdavinci() (machine_arch_type == MACH_TYPE_PTDAVINCI) -+#else -+# define machine_is_ptdavinci() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MBUS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MBUS -+# endif -+# define machine_is_mbus() (machine_arch_type == MACH_TYPE_MBUS) -+#else -+# define machine_is_mbus() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NADIA2VB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NADIA2VB -+# endif -+# define machine_is_nadia2vb() (machine_arch_type == MACH_TYPE_NADIA2VB) -+#else -+# define machine_is_nadia2vb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_R1000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_R1000 -+# endif -+# define machine_is_r1000() (machine_arch_type == MACH_TYPE_R1000) -+#else -+# define machine_is_r1000() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HW90250 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HW90250 -+# endif -+# define machine_is_hw90250() (machine_arch_type == MACH_TYPE_HW90250) -+#else -+# define machine_is_hw90250() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_2430SDP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_2430SDP -+# endif -+# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP) -+#else -+# define machine_is_omap_2430sdp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DAVINCI_EVM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DAVINCI_EVM -+# endif -+# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM) -+#else -+# define machine_is_davinci_evm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_TORNADO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_TORNADO -+# endif -+# define machine_is_omap_tornado() (machine_arch_type == MACH_TYPE_OMAP_TORNADO) -+#else -+# define machine_is_omap_tornado() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OLOCREEK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OLOCREEK -+# endif -+# define machine_is_olocreek() (machine_arch_type == MACH_TYPE_OLOCREEK) -+#else -+# define machine_is_olocreek() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PALMZ72 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PALMZ72 -+# endif -+# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72) -+#else -+# define machine_is_palmz72() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NXDB500 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NXDB500 -+# endif -+# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500) -+#else -+# define machine_is_nxdb500() (0) -+#endif -+ -+#ifdef CONFIG_MACH_APF9328 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_APF9328 -+# endif -+# define machine_is_apf9328() (machine_arch_type == MACH_TYPE_APF9328) -+#else -+# define machine_is_apf9328() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_WIPOQ -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_WIPOQ -+# endif -+# define machine_is_omap_wipoq() (machine_arch_type == MACH_TYPE_OMAP_WIPOQ) -+#else -+# define machine_is_omap_wipoq() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_TWIP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_TWIP -+# endif -+# define machine_is_omap_twip() (machine_arch_type == MACH_TYPE_OMAP_TWIP) -+#else -+# define machine_is_omap_twip() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSCALE_PALMTREO650 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSCALE_PALMTREO650 -+# endif -+# define machine_is_xscale_treo650() (machine_arch_type == MACH_TYPE_XSCALE_PALMTREO650) -+#else -+# define machine_is_xscale_treo650() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ACUMEN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ACUMEN -+# endif -+# define machine_is_acumen() (machine_arch_type == MACH_TYPE_ACUMEN) -+#else -+# define machine_is_acumen() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XP100 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XP100 -+# endif -+# define machine_is_xp100() (machine_arch_type == MACH_TYPE_XP100) -+#else -+# define machine_is_xp100() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FS2410 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FS2410 -+# endif -+# define machine_is_fs2410() (machine_arch_type == MACH_TYPE_FS2410) -+#else -+# define machine_is_fs2410() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PXA270_CERF -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PXA270_CERF -+# endif -+# define machine_is_pxa270_cerf() (machine_arch_type == MACH_TYPE_PXA270_CERF) -+#else -+# define machine_is_pxa270_cerf() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SQ2FTLPALM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SQ2FTLPALM -+# endif -+# define machine_is_sq2ftlpalm() (machine_arch_type == MACH_TYPE_SQ2FTLPALM) -+#else -+# define machine_is_sq2ftlpalm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BSEMSERVER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BSEMSERVER -+# endif -+# define machine_is_bsemserver() (machine_arch_type == MACH_TYPE_BSEMSERVER) -+#else -+# define machine_is_bsemserver() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NETCLIENT -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NETCLIENT -+# endif -+# define machine_is_netclient() (machine_arch_type == MACH_TYPE_NETCLIENT) -+#else -+# define machine_is_netclient() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSCALE_PALMTT5 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSCALE_PALMTT5 -+# endif -+# define machine_is_xscale_palmtt5() (machine_arch_type == MACH_TYPE_XSCALE_PALMTT5) -+#else -+# define machine_is_xscale_palmtt5() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMTC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMTC -+# endif -+# define machine_is_xscale_palmtc() (machine_arch_type == MACH_TYPE_OMAP_PALMTC) -+#else -+# define machine_is_xscale_palmtc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_APOLLON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_APOLLON -+# endif -+# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) -+#else -+# define machine_is_omap_apollon() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MXC30030EVB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MXC30030EVB -+# endif -+# define machine_is_mxc30030evb() (machine_arch_type == MACH_TYPE_MXC30030EVB) -+#else -+# define machine_is_mxc30030evb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_REA_2D -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_REA_2D -+# endif -+# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D) -+#else -+# define machine_is_rea_2d() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TI3E524 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TI3E524 -+# endif -+# define machine_is_eti3e524() (machine_arch_type == MACH_TYPE_TI3E524) -+#else -+# define machine_is_eti3e524() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ATEB9200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ATEB9200 -+# endif -+# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200) -+#else -+# define machine_is_ateb9200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AUCKLAND -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AUCKLAND -+# endif -+# define machine_is_auckland() (machine_arch_type == MACH_TYPE_AUCKLAND) -+#else -+# define machine_is_auckland() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AK3320M -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AK3320M -+# endif -+# define machine_is_ak3220m() (machine_arch_type == MACH_TYPE_AK3320M) -+#else -+# define machine_is_ak3220m() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DURAMAX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DURAMAX -+# endif -+# define machine_is_duramax() (machine_arch_type == MACH_TYPE_DURAMAX) -+#else -+# define machine_is_duramax() (0) -+#endif -+ -+#ifdef CONFIG_MACH_N35 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_N35 -+# endif -+# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35) -+#else -+# define machine_is_n35() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PRONGHORN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PRONGHORN -+# endif -+# define machine_is_pronghorn() (machine_arch_type == MACH_TYPE_PRONGHORN) -+#else -+# define machine_is_pronghorn() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FUNDY -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FUNDY -+# endif -+# define machine_is_fundy() (machine_arch_type == MACH_TYPE_FUNDY) -+#else -+# define machine_is_fundy() (0) -+#endif -+ -+#ifdef CONFIG_MACH_LOGICPD_PXA270 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_LOGICPD_PXA270 -+# endif -+# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270) -+#else -+# define machine_is_logicpd_pxa270() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CPU777 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CPU777 -+# endif -+# define machine_is_cpu777() (machine_arch_type == MACH_TYPE_CPU777) -+#else -+# define machine_is_cpu777() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SIMICON9201 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SIMICON9201 -+# endif -+# define machine_is_simicon9201() (machine_arch_type == MACH_TYPE_SIMICON9201) -+#else -+# define machine_is_simicon9201() (0) -+#endif -+ -+#ifdef CONFIG_MACH_LEAP2_HPM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_LEAP2_HPM -+# endif -+# define machine_is_leap2_hpm() (machine_arch_type == MACH_TYPE_LEAP2_HPM) -+#else -+# define machine_is_leap2_hpm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CM922TXA10 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CM922TXA10 -+# endif -+# define machine_is_cm922txa10() (machine_arch_type == MACH_TYPE_CM922TXA10) -+#else -+# define machine_is_cm922txa10() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PXA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PXA -+# endif -+# define machine_is_sandgate() (machine_arch_type == MACH_TYPE_PXA) -+#else -+# define machine_is_sandgate() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SANDGATE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SANDGATE2 -+# endif -+# define machine_is_sandgate2() (machine_arch_type == MACH_TYPE_SANDGATE2) -+#else -+# define machine_is_sandgate2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SANDGATE2G -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SANDGATE2G -+# endif -+# define machine_is_sandgate2g() (machine_arch_type == MACH_TYPE_SANDGATE2G) -+#else -+# define machine_is_sandgate2g() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SANDGATE2P -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SANDGATE2P -+# endif -+# define machine_is_sandgate2p() (machine_arch_type == MACH_TYPE_SANDGATE2P) -+#else -+# define machine_is_sandgate2p() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FRED_JACK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FRED_JACK -+# endif -+# define machine_is_fred_jack() (machine_arch_type == MACH_TYPE_FRED_JACK) -+#else -+# define machine_is_fred_jack() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TTG_COLOR1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TTG_COLOR1 -+# endif -+# define machine_is_ttg_color1() (machine_arch_type == MACH_TYPE_TTG_COLOR1) -+#else -+# define machine_is_ttg_color1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NXEB500HMI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NXEB500HMI -+# endif -+# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI) -+#else -+# define machine_is_nxeb500hmi() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NETDCU8 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NETDCU8 -+# endif -+# define machine_is_netdcu8() (machine_arch_type == MACH_TYPE_NETDCU8) -+#else -+# define machine_is_netdcu8() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ML675050_CPU_BOA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ML675050_CPU_BOA -+# endif -+# define machine_is_ml675050_cpu_boa() (machine_arch_type == MACH_TYPE_ML675050_CPU_BOA) -+#else -+# define machine_is_ml675050_cpu_boa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NG_FVX538 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NG_FVX538 -+# endif -+# define machine_is_ng_fvx538() (machine_arch_type == MACH_TYPE_NG_FVX538) -+#else -+# define machine_is_ng_fvx538() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NG_FVS338 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NG_FVS338 -+# endif -+# define machine_is_ng_fvs338() (machine_arch_type == MACH_TYPE_NG_FVS338) -+#else -+# define machine_is_ng_fvs338() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PNX4103 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PNX4103 -+# endif -+# define machine_is_pnx4103() (machine_arch_type == MACH_TYPE_PNX4103) -+#else -+# define machine_is_pnx4103() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HESDB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HESDB -+# endif -+# define machine_is_hesdb() (machine_arch_type == MACH_TYPE_HESDB) -+#else -+# define machine_is_hesdb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSILO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSILO -+# endif -+# define machine_is_xsilo() (machine_arch_type == MACH_TYPE_XSILO) -+#else -+# define machine_is_xsilo() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ESPRESSO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ESPRESSO -+# endif -+# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO) -+#else -+# define machine_is_espresso() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EMLC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EMLC -+# endif -+# define machine_is_emlc() (machine_arch_type == MACH_TYPE_EMLC) -+#else -+# define machine_is_emlc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SISTERON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SISTERON -+# endif -+# define machine_is_sisteron() (machine_arch_type == MACH_TYPE_SISTERON) -+#else -+# define machine_is_sisteron() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RX1950 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RX1950 -+# endif -+# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950) -+#else -+# define machine_is_rx1950() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TSC_VENUS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TSC_VENUS -+# endif -+# define machine_is_tsc_venus() (machine_arch_type == MACH_TYPE_TSC_VENUS) -+#else -+# define machine_is_tsc_venus() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DS101J -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DS101J -+# endif -+# define machine_is_ds101j() (machine_arch_type == MACH_TYPE_DS101J) -+#else -+# define machine_is_ds101j() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MXC30030ADS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MXC30030ADS -+# endif -+# define machine_is_mxc30030ads() (machine_arch_type == MACH_TYPE_MXC30030ADS) -+#else -+# define machine_is_mxc30030ads() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FUJITSU_WIMAXSOC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FUJITSU_WIMAXSOC -+# endif -+# define machine_is_fujitsu_wimaxsoc() (machine_arch_type == MACH_TYPE_FUJITSU_WIMAXSOC) -+#else -+# define machine_is_fujitsu_wimaxsoc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DUALPCMODEM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DUALPCMODEM -+# endif -+# define machine_is_dualpcmodem() (machine_arch_type == MACH_TYPE_DUALPCMODEM) -+#else -+# define machine_is_dualpcmodem() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GESBC9312 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GESBC9312 -+# endif -+# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312) -+#else -+# define machine_is_gesbc9312() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HTCAPACHE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HTCAPACHE -+# endif -+# define machine_is_htcapache() (machine_arch_type == MACH_TYPE_HTCAPACHE) -+#else -+# define machine_is_htcapache() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXDP435 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXDP435 -+# endif -+# define machine_is_ixdp435() (machine_arch_type == MACH_TYPE_IXDP435) -+#else -+# define machine_is_ixdp435() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CATPROVT100 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CATPROVT100 -+# endif -+# define machine_is_catprovt100() (machine_arch_type == MACH_TYPE_CATPROVT100) -+#else -+# define machine_is_catprovt100() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PICOTUX1XX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PICOTUX1XX -+# endif -+# define machine_is_picotux1xx() (machine_arch_type == MACH_TYPE_PICOTUX1XX) -+#else -+# define machine_is_picotux1xx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PICOTUX2XX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PICOTUX2XX -+# endif -+# define machine_is_picotux2xx() (machine_arch_type == MACH_TYPE_PICOTUX2XX) -+#else -+# define machine_is_picotux2xx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DSMG600 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DSMG600 -+# endif -+# define machine_is_dsmg600() (machine_arch_type == MACH_TYPE_DSMG600) -+#else -+# define machine_is_dsmg600() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EMPC2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EMPC2 -+# endif -+# define machine_is_empc2() (machine_arch_type == MACH_TYPE_EMPC2) -+#else -+# define machine_is_empc2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VENTURA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VENTURA -+# endif -+# define machine_is_ventura() (machine_arch_type == MACH_TYPE_VENTURA) -+#else -+# define machine_is_ventura() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PHIDGET_SBC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PHIDGET_SBC -+# endif -+# define machine_is_phidget_sbc() (machine_arch_type == MACH_TYPE_PHIDGET_SBC) -+#else -+# define machine_is_phidget_sbc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IJ3K -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IJ3K -+# endif -+# define machine_is_ij3k() (machine_arch_type == MACH_TYPE_IJ3K) -+#else -+# define machine_is_ij3k() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PISGAH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PISGAH -+# endif -+# define machine_is_pisgah() (machine_arch_type == MACH_TYPE_PISGAH) -+#else -+# define machine_is_pisgah() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_FSAMPLE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_FSAMPLE -+# endif -+# define machine_is_omap_fsample() (machine_arch_type == MACH_TYPE_OMAP_FSAMPLE) -+#else -+# define machine_is_omap_fsample() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SG720 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SG720 -+# endif -+# define machine_is_sg720() (machine_arch_type == MACH_TYPE_SG720) -+#else -+# define machine_is_sg720() (0) -+#endif -+ -+#ifdef CONFIG_MACH_REDFOX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_REDFOX -+# endif -+# define machine_is_redfox() (machine_arch_type == MACH_TYPE_REDFOX) -+#else -+# define machine_is_redfox() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MYSH_EP9315_1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MYSH_EP9315_1 -+# endif -+# define machine_is_mysh_ep9315_1() (machine_arch_type == MACH_TYPE_MYSH_EP9315_1) -+#else -+# define machine_is_mysh_ep9315_1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TPF106 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TPF106 -+# endif -+# define machine_is_tpf106() (machine_arch_type == MACH_TYPE_TPF106) -+#else -+# define machine_is_tpf106() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AT91RM9200KG -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AT91RM9200KG -+# endif -+# define machine_is_at91rm9200kg() (machine_arch_type == MACH_TYPE_AT91RM9200KG) -+#else -+# define machine_is_at91rm9200kg() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SLEDB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SLEDB -+# endif -+# define machine_is_racemt2() (machine_arch_type == MACH_TYPE_SLEDB) -+#else -+# define machine_is_racemt2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ONTRACK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ONTRACK -+# endif -+# define machine_is_ontrack() (machine_arch_type == MACH_TYPE_ONTRACK) -+#else -+# define machine_is_ontrack() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PM1200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PM1200 -+# endif -+# define machine_is_pm1200() (machine_arch_type == MACH_TYPE_PM1200) -+#else -+# define machine_is_pm1200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ESS24XXX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ESS24XXX -+# endif -+# define machine_is_ess24562() (machine_arch_type == MACH_TYPE_ESS24XXX) -+#else -+# define machine_is_ess24562() (0) -+#endif -+ -+#ifdef CONFIG_MACH_COREMP7 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_COREMP7 -+# endif -+# define machine_is_coremp7() (machine_arch_type == MACH_TYPE_COREMP7) -+#else -+# define machine_is_coremp7() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NEXCODER_6446 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NEXCODER_6446 -+# endif -+# define machine_is_nexcoder_6446() (machine_arch_type == MACH_TYPE_NEXCODER_6446) -+#else -+# define machine_is_nexcoder_6446() (0) -+#endif -+ -+#ifdef CONFIG_MACH_STVC8380 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_STVC8380 -+# endif -+# define machine_is_stvc8380() (machine_arch_type == MACH_TYPE_STVC8380) -+#else -+# define machine_is_stvc8380() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TEKLYNX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TEKLYNX -+# endif -+# define machine_is_teklynx() (machine_arch_type == MACH_TYPE_TEKLYNX) -+#else -+# define machine_is_teklynx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CARBONADO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CARBONADO -+# endif -+# define machine_is_carbonado() (machine_arch_type == MACH_TYPE_CARBONADO) -+#else -+# define machine_is_carbonado() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SYSMOS_MP730 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SYSMOS_MP730 -+# endif -+# define machine_is_sysmos_mp730() (machine_arch_type == MACH_TYPE_SYSMOS_MP730) -+#else -+# define machine_is_sysmos_mp730() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SNAPPER_CL15 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SNAPPER_CL15 -+# endif -+# define machine_is_snapper_cl15() (machine_arch_type == MACH_TYPE_SNAPPER_CL15) -+#else -+# define machine_is_snapper_cl15() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PGIGIM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PGIGIM -+# endif -+# define machine_is_pgigim() (machine_arch_type == MACH_TYPE_PGIGIM) -+#else -+# define machine_is_pgigim() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PTX9160P2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PTX9160P2 -+# endif -+# define machine_is_ptx9160p2() (machine_arch_type == MACH_TYPE_PTX9160P2) -+#else -+# define machine_is_ptx9160p2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DCORE1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DCORE1 -+# endif -+# define machine_is_dcore1() (machine_arch_type == MACH_TYPE_DCORE1) -+#else -+# define machine_is_dcore1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VICTORPXA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VICTORPXA -+# endif -+# define machine_is_victorpxa() (machine_arch_type == MACH_TYPE_VICTORPXA) -+#else -+# define machine_is_victorpxa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MX2DTB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MX2DTB -+# endif -+# define machine_is_mx2dtb() (machine_arch_type == MACH_TYPE_MX2DTB) -+#else -+# define machine_is_mx2dtb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PXA_IREX_ER0100 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PXA_IREX_ER0100 -+# endif -+# define machine_is_pxa_irex_er0100() (machine_arch_type == MACH_TYPE_PXA_IREX_ER0100) -+#else -+# define machine_is_pxa_irex_er0100() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMZ71 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMZ71 -+# endif -+# define machine_is_omap_palmz71() (machine_arch_type == MACH_TYPE_OMAP_PALMZ71) -+#else -+# define machine_is_omap_palmz71() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BARTEC_DEG -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BARTEC_DEG -+# endif -+# define machine_is_bartec_deg() (machine_arch_type == MACH_TYPE_BARTEC_DEG) -+#else -+# define machine_is_bartec_deg() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HW50251 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HW50251 -+# endif -+# define machine_is_hw50251() (machine_arch_type == MACH_TYPE_HW50251) -+#else -+# define machine_is_hw50251() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IBOX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IBOX -+# endif -+# define machine_is_ibox() (machine_arch_type == MACH_TYPE_IBOX) -+#else -+# define machine_is_ibox() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ATLASLH7A404 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ATLASLH7A404 -+# endif -+# define machine_is_atlaslh7a404() (machine_arch_type == MACH_TYPE_ATLASLH7A404) -+#else -+# define machine_is_atlaslh7a404() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PT2026 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PT2026 -+# endif -+# define machine_is_pt2026() (machine_arch_type == MACH_TYPE_PT2026) -+#else -+# define machine_is_pt2026() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HTCALPINE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HTCALPINE -+# endif -+# define machine_is_htcalpine() (machine_arch_type == MACH_TYPE_HTCALPINE) -+#else -+# define machine_is_htcalpine() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BARTEC_VTU -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BARTEC_VTU -+# endif -+# define machine_is_bartec_vtu() (machine_arch_type == MACH_TYPE_BARTEC_VTU) -+#else -+# define machine_is_bartec_vtu() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VCOREII -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VCOREII -+# endif -+# define machine_is_vcoreii() (machine_arch_type == MACH_TYPE_VCOREII) -+#else -+# define machine_is_vcoreii() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PDNB3 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PDNB3 -+# endif -+# define machine_is_pdnb3() (machine_arch_type == MACH_TYPE_PDNB3) -+#else -+# define machine_is_pdnb3() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HTCBEETLES -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HTCBEETLES -+# endif -+# define machine_is_htcbeetles() (machine_arch_type == MACH_TYPE_HTCBEETLES) -+#else -+# define machine_is_htcbeetles() (0) -+#endif -+ -+#ifdef CONFIG_MACH_S3C6400 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_S3C6400 -+# endif -+# define machine_is_s3c6400() (machine_arch_type == MACH_TYPE_S3C6400) -+#else -+# define machine_is_s3c6400() (0) -+#endif -+ -+#ifdef CONFIG_MACH_S3C2443 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_S3C2443 -+# endif -+# define machine_is_s3c2443() (machine_arch_type == MACH_TYPE_S3C2443) -+#else -+# define machine_is_s3c2443() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_LDK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_LDK -+# endif -+# define machine_is_omap_ldk() (machine_arch_type == MACH_TYPE_OMAP_LDK) -+#else -+# define machine_is_omap_ldk() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SMDK2460 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SMDK2460 -+# endif -+# define machine_is_smdk2460() (machine_arch_type == MACH_TYPE_SMDK2460) -+#else -+# define machine_is_smdk2460() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SMDK2440 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SMDK2440 -+# endif -+# define machine_is_smdk2440() (machine_arch_type == MACH_TYPE_SMDK2440) -+#else -+# define machine_is_smdk2440() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SMDK2412 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SMDK2412 -+# endif -+# define machine_is_smdk2412() (machine_arch_type == MACH_TYPE_SMDK2412) -+#else -+# define machine_is_smdk2412() (0) -+#endif -+ -+#ifdef CONFIG_MACH_WEBBOX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_WEBBOX -+# endif -+# define machine_is_webbox() (machine_arch_type == MACH_TYPE_WEBBOX) -+#else -+# define machine_is_webbox() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CWWNDP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CWWNDP -+# endif -+# define machine_is_cwwndp() (machine_arch_type == MACH_TYPE_CWWNDP) -+#else -+# define machine_is_cwwndp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DRAGON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DRAGON -+# endif -+# define machine_is_dragon() (machine_arch_type == MACH_TYPE_DRAGON) -+#else -+# define machine_is_dragon() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OPENDO_CPU_BOARD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OPENDO_CPU_BOARD -+# endif -+# define machine_is_opendo_cpu_board() (machine_arch_type == MACH_TYPE_OPENDO_CPU_BOARD) -+#else -+# define machine_is_opendo_cpu_board() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CCM2200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CCM2200 -+# endif -+# define machine_is_ccm2200() (machine_arch_type == MACH_TYPE_CCM2200) -+#else -+# define machine_is_ccm2200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ETWARM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ETWARM -+# endif -+# define machine_is_etwarm() (machine_arch_type == MACH_TYPE_ETWARM) -+#else -+# define machine_is_etwarm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_M93030 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_M93030 -+# endif -+# define machine_is_m93030() (machine_arch_type == MACH_TYPE_M93030) -+#else -+# define machine_is_m93030() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CC7U -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CC7U -+# endif -+# define machine_is_cc7u() (machine_arch_type == MACH_TYPE_CC7U) -+#else -+# define machine_is_cc7u() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MTT_RANGER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MTT_RANGER -+# endif -+# define machine_is_mtt_ranger() (machine_arch_type == MACH_TYPE_MTT_RANGER) -+#else -+# define machine_is_mtt_ranger() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NEXUS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NEXUS -+# endif -+# define machine_is_nexus() (machine_arch_type == MACH_TYPE_NEXUS) -+#else -+# define machine_is_nexus() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DESMAN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DESMAN -+# endif -+# define machine_is_desman() (machine_arch_type == MACH_TYPE_DESMAN) -+#else -+# define machine_is_desman() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BKDE303 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BKDE303 -+# endif -+# define machine_is_bkde303() (machine_arch_type == MACH_TYPE_BKDE303) -+#else -+# define machine_is_bkde303() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SMDK2413 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SMDK2413 -+# endif -+# define machine_is_smdk2413() (machine_arch_type == MACH_TYPE_SMDK2413) -+#else -+# define machine_is_smdk2413() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AML_M7200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AML_M7200 -+# endif -+# define machine_is_aml_m7200() (machine_arch_type == MACH_TYPE_AML_M7200) -+#else -+# define machine_is_aml_m7200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AML_M5900 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AML_M5900 -+# endif -+# define machine_is_aml_m5900() (machine_arch_type == MACH_TYPE_AML_M5900) -+#else -+# define machine_is_aml_m5900() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SG640 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SG640 -+# endif -+# define machine_is_sg640() (machine_arch_type == MACH_TYPE_SG640) -+#else -+# define machine_is_sg640() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EDG79524 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EDG79524 -+# endif -+# define machine_is_edg79524() (machine_arch_type == MACH_TYPE_EDG79524) -+#else -+# define machine_is_edg79524() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AI2410 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AI2410 -+# endif -+# define machine_is_ai2410() (machine_arch_type == MACH_TYPE_AI2410) -+#else -+# define machine_is_ai2410() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXP465 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXP465 -+# endif -+# define machine_is_ixp465() (machine_arch_type == MACH_TYPE_IXP465) -+#else -+# define machine_is_ixp465() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BALLOON3 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BALLOON3 -+# endif -+# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3) -+#else -+# define machine_is_balloon3() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HEINS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HEINS -+# endif -+# define machine_is_heins() (machine_arch_type == MACH_TYPE_HEINS) -+#else -+# define machine_is_heins() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MPLUSEVA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MPLUSEVA -+# endif -+# define machine_is_mpluseva() (machine_arch_type == MACH_TYPE_MPLUSEVA) -+#else -+# define machine_is_mpluseva() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RT042 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RT042 -+# endif -+# define machine_is_rt042() (machine_arch_type == MACH_TYPE_RT042) -+#else -+# define machine_is_rt042() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CWIEM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CWIEM -+# endif -+# define machine_is_cwiem() (machine_arch_type == MACH_TYPE_CWIEM) -+#else -+# define machine_is_cwiem() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CM_X270 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CM_X270 -+# endif -+# define machine_is_cm_x270() (machine_arch_type == MACH_TYPE_CM_X270) -+#else -+# define machine_is_cm_x270() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CM_X255 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CM_X255 -+# endif -+# define machine_is_cm_x255() (machine_arch_type == MACH_TYPE_CM_X255) -+#else -+# define machine_is_cm_x255() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ESH_AT91 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ESH_AT91 -+# endif -+# define machine_is_esh_at91() (machine_arch_type == MACH_TYPE_ESH_AT91) -+#else -+# define machine_is_esh_at91() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SANDGATE3 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SANDGATE3 -+# endif -+# define machine_is_sandgate3() (machine_arch_type == MACH_TYPE_SANDGATE3) -+#else -+# define machine_is_sandgate3() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PRIMO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PRIMO -+# endif -+# define machine_is_primo() (machine_arch_type == MACH_TYPE_PRIMO) -+#else -+# define machine_is_primo() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GEMSTONE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GEMSTONE -+# endif -+# define machine_is_gemstone() (machine_arch_type == MACH_TYPE_GEMSTONE) -+#else -+# define machine_is_gemstone() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PRONGHORNMETRO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PRONGHORNMETRO -+# endif -+# define machine_is_pronghorn_metro() (machine_arch_type == MACH_TYPE_PRONGHORNMETRO) -+#else -+# define machine_is_pronghorn_metro() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SIDEWINDER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SIDEWINDER -+# endif -+# define machine_is_sidewinder() (machine_arch_type == MACH_TYPE_SIDEWINDER) -+#else -+# define machine_is_sidewinder() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PICOMOD1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PICOMOD1 -+# endif -+# define machine_is_picomod1() (machine_arch_type == MACH_TYPE_PICOMOD1) -+#else -+# define machine_is_picomod1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SG590 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SG590 -+# endif -+# define machine_is_sg590() (machine_arch_type == MACH_TYPE_SG590) -+#else -+# define machine_is_sg590() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AKAI9307 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AKAI9307 -+# endif -+# define machine_is_akai9307() (machine_arch_type == MACH_TYPE_AKAI9307) -+#else -+# define machine_is_akai9307() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FONTAINE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FONTAINE -+# endif -+# define machine_is_fontaine() (machine_arch_type == MACH_TYPE_FONTAINE) -+#else -+# define machine_is_fontaine() (0) -+#endif -+ -+#ifdef CONFIG_MACH_WOMBAT -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_WOMBAT -+# endif -+# define machine_is_wombat() (machine_arch_type == MACH_TYPE_WOMBAT) -+#else -+# define machine_is_wombat() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ACQ300 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ACQ300 -+# endif -+# define machine_is_acq300() (machine_arch_type == MACH_TYPE_ACQ300) -+#else -+# define machine_is_acq300() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MOD_270 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MOD_270 -+# endif -+# define machine_is_mod_270() (machine_arch_type == MACH_TYPE_MOD_270) -+#else -+# define machine_is_mod_270() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VC0820 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VC0820 -+# endif -+# define machine_is_vmc_vc0820() (machine_arch_type == MACH_TYPE_VC0820) -+#else -+# define machine_is_vmc_vc0820() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ANI_AIM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ANI_AIM -+# endif -+# define machine_is_ani_aim() (machine_arch_type == MACH_TYPE_ANI_AIM) -+#else -+# define machine_is_ani_aim() (0) -+#endif -+ -+#ifdef CONFIG_MACH_JELLYFISH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_JELLYFISH -+# endif -+# define machine_is_jellyfish() (machine_arch_type == MACH_TYPE_JELLYFISH) -+#else -+# define machine_is_jellyfish() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AMANITA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AMANITA -+# endif -+# define machine_is_amanita() (machine_arch_type == MACH_TYPE_AMANITA) -+#else -+# define machine_is_amanita() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VLINK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VLINK -+# endif -+# define machine_is_vlink() (machine_arch_type == MACH_TYPE_VLINK) -+#else -+# define machine_is_vlink() (0) -+#endif -+ - /* - * These have not yet been registered - */ -diff -Naur u-boot-1.1.4.org/include/config.h u-boot-1.1.4.tmp/include/config.h ---- u-boot-1.1.4.org/include/config.h 2006-06-05 05:04:25.000000000 +0200 -+++ u-boot-1.1.4.tmp/include/config.h 2006-06-05 05:03:47.000000000 +0200 -@@ -1,2 +1,2 @@ - /* Automatically generated - do not edit */ --#include <configs/at91rm9200dk.h> -+#include <configs/vlink.h> -diff -Naur u-boot-1.1.4.org/include/config.mk u-boot-1.1.4.tmp/include/config.mk ---- u-boot-1.1.4.org/include/config.mk 2006-06-05 05:04:25.000000000 +0200 -+++ u-boot-1.1.4.tmp/include/config.mk 2006-06-05 05:03:47.000000000 +0200 -@@ -1,4 +1,4 @@ - ARCH = arm - CPU = arm920t --BOARD = at91rm9200dk -+BOARD = vlink - SOC = at91rm9200 -diff -Naur u-boot-1.1.4.org/include/configs/vlink.h u-boot-1.1.4.tmp/include/configs/vlink.h ---- u-boot-1.1.4.org/include/configs/vlink.h 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/include/configs/vlink.h 2006-06-05 03:37:15.000000000 +0200 -@@ -0,0 +1,244 @@ -+/* -+ * Hamish Guthrie <hamish@prodigi.ch> -+ * -+ * Configuation settings for the Figment Designs Versalink board. -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+// Added 2 defines to skip re-init lowlevel and relocate HCG HLH -+// -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SKIP_RELOCATE_UBOOT -+ -+/* ARM asynchronous clock */ -+#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ -+#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ -+/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ -+ -+#define AT91_SLOW_CLOCK 32768 /* slow clock */ -+ -+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -+#define CONFIG_VLINK 1 /* on a Versalink Board */ -+#define CONFIG_IDENT_STRING " FDL Versalink" -+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -+#define USE_920T_MMU 1 -+ -+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -+#define CONFIG_SETUP_MEMORY_TAGS 1 -+#define CONFIG_INITRD_TAG 1 -+ -+#ifndef CONFIG_SKIP_LOWLEVEL_INIT -+#define CFG_USE_MAIN_OSCILLATOR 1 -+/* flash */ -+#define MC_PUIA_VAL 0x00000000 -+#define MC_PUP_VAL 0x00000000 -+#define MC_PUER_VAL 0x00000000 -+#define MC_ASR_VAL 0x00000000 -+#define MC_AASR_VAL 0x00000000 -+#define EBI_CFGR_VAL 0x00000000 -+#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ -+ -+/* clocks */ -+#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -+#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -+#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -+ -+/* sdram */ -+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -+#define PIOC_BSR_VAL 0x00000000 -+#define PIOC_PDR_VAL 0xFFFF0000 -+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -+#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -+#define SDRAM 0x20000000 /* address of the SDRAM */ -+#define SDRAM1 0x20000080 /* address of the SDRAM */ -+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -+#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -+#define SDRC_MR_VAL1 0x00000004 /* refresh */ -+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -+/* -+ * Size of malloc() pool -+ */ -+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -+ -+#define CONFIG_BAUDRATE 115200 -+ -+/* -+ * Hardware drivers -+ */ -+ -+/* define one of these to choose the DBGU, USART0 or USART1 as console */ -+#define CONFIG_DBGU -+#undef CONFIG_USART0 -+#undef CONFIG_USART1 -+ -+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ -+ -+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ -+ -+#define CONFIG_BOOTDELAY 3 -+/* #define CONFIG_ENV_OVERWRITE 1 */ -+ -+#define CONFIG_COMMANDS \ -+ ((CONFIG_CMD_DFL | CFG_CMD_MII |\ -+ CFG_CMD_DHCP ) & \ -+ ~(CFG_CMD_BDI | \ -+ CFG_CMD_IMI | \ -+ CFG_CMD_AUTOSCRIPT | \ -+ CFG_CMD_FPGA | \ -+ CFG_CMD_MISC | \ -+ CFG_CMD_LOADS )) -+ -+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -+#include <cmd_confdefs.h> -+ -+#ifndef CONFIG_VLINK -+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -+#define SECTORSIZE 512 -+ -+#define ADDR_COLUMN 1 -+#define ADDR_PAGE 2 -+#define ADDR_COLUMN_PAGE 3 -+ -+#define NAND_ChipID_UNKNOWN 0x00 -+#define NAND_MAX_FLOORS 1 -+#define NAND_MAX_CHIPS 1 -+ -+#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -+#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ -+ -+#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) -+#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) -+ -+#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) -+ -+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) -+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) -+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -+/* the following are NOP's in our implementation */ -+#define NAND_CTL_CLRALE(nandptr) -+#define NAND_CTL_SETALE(nandptr) -+#define NAND_CTL_CLRCLE(nandptr) -+#define NAND_CTL_SETCLE(nandptr) -+#endif -+ -+#define CONFIG_NR_DRAM_BANKS 1 -+#define PHYS_SDRAM 0x20000000 -+#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ -+ -+#define CFG_MEMTEST_START PHYS_SDRAM -+#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 -+ -+#define CONFIG_DRIVER_ETHER -+#define CONFIG_NET_RETRY_COUNT 20 -+#define CONFIG_AT91C_USE_RMII -+ -+#define CONFIG_HAS_DATAFLASH 1 -+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) -+#define CFG_MAX_DATAFLASH_BANKS 2 -+#define CFG_MAX_DATAFLASH_PAGES 16384 -+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -+#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ -+ -+#ifdef CONFIG_VLINK -+#define PHYS_FLASH_1 0x10000000 -+#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ -+#define CFG_FLASH_BASE PHYS_FLASH_1 -+#define CFG_MAX_FLASH_BANKS 1 -+#define CFG_MAX_FLASH_SECT 256 -+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -+#endif -+ -+#define CFG_ENV_IS_IN_DATAFLASH -+ -+#ifdef CFG_ENV_IS_IN_DATAFLASH -+#define CFG_ENV_OFFSET 0x21000 -+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) -+#define CFG_ENV_SIZE 0x8400 /* 0x8000 */ -+#else -+#define CFG_ENV_IS_IN_FLASH 1 -+#ifdef CONFIG_SKIP_LOWLEVEL_INIT -+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ -+#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ -+#else -+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ -+#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -+#endif /* CFG_ENV_IS_IN_DATAFLASH */ -+ -+ -+#define CFG_LOAD_ADDR 0x21000000 /* default load address */ -+ -+#ifdef CONFIG_SKIP_LOWLEVEL_INIT -+#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ -+#define CFG_U_BOOT_BASE PHYS_FLASH_1 -+#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */ -+#else -+#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ -+#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) -+#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ -+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -+ -+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } -+ -+#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ -+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -+#define CFG_MAXARGS 16 /* max number of command args */ -+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -+ -+#ifndef __ASSEMBLY__ -+/*----------------------------------------------------------------------- -+ * Board specific extension for bd_info -+ * -+ * This structure is embedded in the global bd_info (bd_t) structure -+ * and can be used by the board specific code (eg board/...) -+ */ -+ -+struct bd_info_ext { -+ /* helper variable for board environment handling -+ * -+ * env_crc_valid == 0 => uninitialised -+ * env_crc_valid > 0 => environment crc in flash is valid -+ * env_crc_valid < 0 => environment crc in flash is invalid -+ */ -+ int env_crc_valid; -+}; -+#endif -+ -+#define CFG_HZ 1000 -+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ -+ /* AT91C_TC_TIMER_DIV1_CLOCK */ -+ -+#define CONFIG_STACKSIZE (32*1024) /* regular stack */ -+ -+#ifdef CONFIG_USE_IRQ -+#error CONFIG_USE_IRQ not supported -+#endif -+ -+#endif -diff -Naur u-boot-1.1.4.org/MAKEALL u-boot-1.1.4.tmp/MAKEALL ---- u-boot-1.1.4.org/MAKEALL 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.tmp/MAKEALL 2006-06-05 02:44:24.000000000 +0200 -@@ -180,7 +180,7 @@ - mx1ads mx1fs2 omap1510inn omap1610h2 \ - omap1610inn omap730p2 scb9328 smdk2400 \ - smdk2410 trab VCMA9 versatile \ -- versatileab versatilepb voiceblue -+ versatileab versatilepb voiceblue vlink - " - - ######################################################################### -diff -Naur u-boot-1.1.4.org/Makefile u-boot-1.1.4.tmp/Makefile ---- u-boot-1.1.4.org/Makefile 2006-06-02 15:58:57.000000000 +0200 -+++ u-boot-1.1.4.tmp/Makefile 2006-06-05 04:40:45.000000000 +0200 -@@ -1419,6 +1419,9 @@ - mp2usb_config : unconfig - @./mkconfig $(@:_config=) arm arm920t mp2usb NULL at91rm9200 - -+vlink_config : unconfig -+ @./mkconfig $(@:_config=) arm arm920t vlink NULL at91rm9200 -+ - - ######################################################################## - ## ARM Integrator boards - see doc/README-integrator for more info. diff --git a/target/linux/at91-2.6/image/u-boot/patches/003-mac_init.patch b/target/linux/at91-2.6/image/u-boot/patches/003-mac_init.patch deleted file mode 100644 index ec5dffa0cb..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/003-mac_init.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- u-boot-1.1.4.org/lib_arm/board.c 2006-06-05 12:36:22.000000000 +0200 -+++ u-boot-1.1.4.tmp/lib_arm/board.c 2006-06-05 12:36:44.000000000 +0200 -@@ -332,6 +332,11 @@ - } - #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ - -+#ifdef CONFIG_MACH_VLINK -+ printf("Initialising MAC address\n\r"); -+ eth_init(gd->bd); -+#endif -+ - /* Initialize from environment */ - if ((s = getenv ("loadaddr")) != NULL) { - load_addr = simple_strtoul (s, NULL, 16); diff --git a/target/linux/at91-2.6/image/u-boot/patches/004-mac_config.patch b/target/linux/at91-2.6/image/u-boot/patches/004-mac_config.patch deleted file mode 100644 index 73a8260d68..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/004-mac_config.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- u-boot-1.1.4.ttt/include/configs/vlink.h 2006-06-05 15:57:37.000000000 +0200 -+++ u-boot-1.1.4/include/configs/vlink.h 2006-06-07 13:11:01.000000000 +0200 -@@ -105,9 +105,9 @@ - - #define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | CFG_CMD_MII |\ -- CFG_CMD_DHCP ) & \ -- ~(CFG_CMD_BDI | \ -- CFG_CMD_IMI | \ -+ CFG_CMD_DHCP | \ -+ CFG_CMD_BDI ) & \ -+ ~(CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ diff --git a/target/linux/at91-2.6/image/u-boot/patches/005-remove_float.patch b/target/linux/at91-2.6/image/u-boot/patches/005-remove_float.patch deleted file mode 100644 index 802c963396..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/005-remove_float.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff -urN u-boot-1.1.4.old/cpu/arm920t/config.mk u-boot-1.1.4/cpu/arm920t/config.mk ---- u-boot-1.1.4.old/cpu/arm920t/config.mk 2007-03-19 12:44:39.000000000 +0100 -+++ u-boot-1.1.4/cpu/arm920t/config.mk 2007-03-20 09:23:54.000000000 +0100 -@@ -21,8 +21,7 @@ - # MA 02111-1307 USA - # - --PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ -- -msoft-float -+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 - - PLATFORM_CPPFLAGS += -march=armv4 - # ========================================================================= diff --git a/target/linux/at91-2.6/image/u-boot/patches/006-generate_params.patch b/target/linux/at91-2.6/image/u-boot/patches/006-generate_params.patch deleted file mode 100644 index d278cfb2da..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/006-generate_params.patch +++ /dev/null @@ -1,115 +0,0 @@ ---- u-boot-1.1.4.old/tools/Makefile 2007-03-22 18:17:25.000000000 +0100 -+++ u-boot-1.1.4/tools/Makefile 2007-03-22 17:08:46.000000000 +0100 -@@ -21,9 +21,9 @@ - # MA 02111-1307 USA - # - --BINS = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) -+BINS = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) ubparams$(SFX) - --OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o -+OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o ubparams.o - - ifeq ($(ARCH),mips) - BINS += inca-swap-bytes$(SFX) -@@ -118,6 +118,9 @@ - - all: .depend $(BINS) $(LOGO_H) subdirs - -+ubparams$(SFX): ubparams.o crc32.o -+ $(CC) $(CFLAGS) -o $@ $^ -+ - envcrc$(SFX): envcrc.o crc32.o environment.o - $(CC) $(CFLAGS) -o $@ $^ - -@@ -149,6 +152,9 @@ - $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ - $(STRIP) $@ - -+ubparams.o: ubparams.c -+ $(CC) -g $(CFLAGS) -c $< -+ - envcrc.o: envcrc.c - $(CC) -g $(CFLAGS) -c $< - ---- u-boot-1.1.4.old/tools/ubparams.c 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4/tools/ubparams.c 2007-03-22 18:09:52.000000000 +0100 -@@ -0,0 +1,78 @@ -+/* -+ * ubparams.c -+ * -+ * Generate a u-boot parameter block with correct crc -+ * -+ * (C) 1007 Guthrie Consulting -+ * hamish@prodigi.ch -+ * -+ */ -+ -+#include <stdio.h> -+#include <stdlib.h> -+#include <string.h> -+ -+#ifndef __ASSEMBLY__ -+#define __ASSEMBLY__ -+#endif -+#define __ASM_STUB_PROCESSOR_H__ -+#include <config.h> -+#undef __ASSEMBLY__ -+#include "environment.h" -+ -+#define XMK_STR(x) #x -+#define MK_STR(x) XMK_STR(x) -+ -+extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); -+ -+#if !defined(ENV_CRC) -+#define ENV_CRC ~0 -+#endif -+ -+unsigned int env_size = 0x8400; -+env_t environment = { -+ ENV_CRC, -+ "bootdelay=3\0" -+ "baudrate=115200\0" -+ "stdin=serial\0" -+ "stdout=serial\0" -+ "stderr=serial\0" -+ "partitions=mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data)\0" -+ "fbargs=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/mtdblock4 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" -+ "rdba=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" -+ "rdram=run rdba; tftp 21000000 vImage; tftp 21200000 root.squashfs; bootm 21000000\0" -+ "flash=run fbargs; bootm 0xc0042000\0" -+ "bootargs=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/mtdblock4 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" -+ "bootcmd=bootm 0xc0042000\0" -+ "ethaddr=00:30:49:00:00:01\0" -+ "ipaddr=10.0.1.73\0" -+ "serverip=10.0.1.210\0" -+ "serial#=MX070205484\0" -+ "\0" -+ }; -+ -+int main(void) { -+ env_t *envptr, *source; -+ unsigned char *dataptr; -+ FILE *params; -+ -+ source = &environment; -+ envptr = (env_t *)malloc(CFG_ENV_SIZE); -+ dataptr = (unsigned char *)envptr + ENV_HEADER_SIZE; -+ -+ printf("Make u-boot params\n"); -+ printf("Params size is %d\n", CFG_ENV_SIZE); -+ -+ memset(envptr, 0, CFG_ENV_SIZE); -+ memcpy(envptr, source, sizeof(environment)); -+ -+ envptr->crc = crc32(0, envptr->data, ENV_SIZE); -+ -+ params = fopen("params", "w"); -+ fwrite(envptr, CFG_ENV_SIZE, 1, params); -+ fclose(params); -+ -+ free(envptr); -+ } -+ -+ diff --git a/target/linux/at91-2.6/image/u-boot/patches/007-ubparams_bugfix.patch b/target/linux/at91-2.6/image/u-boot/patches/007-ubparams_bugfix.patch deleted file mode 100644 index 3d069e4d39..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/007-ubparams_bugfix.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- u-boot-1.1.4.old/tools/ubparams.c 2007-03-22 18:09:52.000000000 +0100 -+++ u-boot-1.1.4/tools/ubparams.c 2007-03-22 18:29:32.000000000 +0100 -@@ -18,7 +18,7 @@ - #define __ASM_STUB_PROCESSOR_H__ - #include <config.h> - #undef __ASSEMBLY__ --#include "environment.h" -+#include <environment.h> - - #define XMK_STR(x) #x - #define MK_STR(x) XMK_STR(x) diff --git a/target/linux/at91-2.6/image/u-boot/patches/008-ubparams_bugfix.patch b/target/linux/at91-2.6/image/u-boot/patches/008-ubparams_bugfix.patch deleted file mode 100644 index 9a16e1998f..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/008-ubparams_bugfix.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- u-boot-1.1.4.old/tools/ubparams.c 2007-03-23 10:51:17.000000000 +0100 -+++ u-boot-1.1.4/tools/ubparams.c 2007-03-23 10:49:37.000000000 +0100 -@@ -73,6 +73,7 @@ - fclose(params); - - free(envptr); -+ return 0; - } - - diff --git a/target/linux/at91-2.6/image/u-boot/patches/009-mac_init_bugfix.patch b/target/linux/at91-2.6/image/u-boot/patches/009-mac_init_bugfix.patch deleted file mode 100644 index a36ebe3251..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/009-mac_init_bugfix.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -urN u-boot-1.1.4.old/lib_arm/board.c u-boot-1.1.4/lib_arm/board.c ---- u-boot-1.1.4.old/lib_arm/board.c 2007-03-23 10:53:52.000000000 +0100 -+++ u-boot-1.1.4/lib_arm/board.c 2007-03-24 13:17:12.000000000 +0100 -@@ -332,7 +332,7 @@ - } - #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ - --#ifdef CONFIG_MACH_VLINK -+#ifdef CONFIG_VLINK - printf("Initialising MAC address\n\r"); - eth_init(gd->bd); - #endif diff --git a/target/linux/at91-2.6/image/u-boot/patches/010-irda-patch-remove.patch b/target/linux/at91-2.6/image/u-boot/patches/010-irda-patch-remove.patch deleted file mode 100644 index 2f23f5b38b..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/010-irda-patch-remove.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- u-boot-1.1.4.old/board/vlink/vlink.c 2007-04-03 11:42:39.000000000 +0200 -+++ u-boot-1.1.4/board/vlink/vlink.c 2007-04-03 11:48:33.000000000 +0200 -@@ -40,10 +40,6 @@ - /* Enable Ctrlc */ - console_init_f (); - -- /* Correct IRDA resistor problem */ -- /* Set PA23_TXD in Output */ -- (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; -- - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - diff --git a/target/linux/at91-2.6/image/u-boot/patches/011-ubparams_update.patch b/target/linux/at91-2.6/image/u-boot/patches/011-ubparams_update.patch deleted file mode 100644 index 267903efe4..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/011-ubparams_update.patch +++ /dev/null @@ -1,19 +0,0 @@ -diff -urN u-boot-1.1.4.old/tools/ubparams.c u-boot-1.1.4/tools/ubparams.c ---- u-boot-1.1.4.old/tools/ubparams.c 2007-05-01 13:20:17.000000000 +0200 -+++ u-boot-1.1.4/tools/ubparams.c 2007-05-04 10:13:34.000000000 +0200 -@@ -37,12 +37,11 @@ - "stdin=serial\0" - "stdout=serial\0" - "stderr=serial\0" -- "partitions=mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data)\0" -- "fbargs=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/mtdblock4 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" -- "rdba=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" -+ "fbargs=setenv bootargs root=/dev/mtdblock3 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" -+ "rdba=setenv bootargs root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" - "rdram=run rdba; tftp 21000000 vImage; tftp 21200000 root.squashfs; bootm 21000000\0" - "flash=run fbargs; bootm 0xc0042000\0" -- "bootargs=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/mtdblock4 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" -+ "bootargs=setenv bootargs root=/dev/mtdblock3 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" - "bootcmd=bootm 0xc0042000\0" - "ethaddr=00:30:49:00:00:01\0" - "ipaddr=10.0.1.73\0" diff --git a/target/linux/at91-2.6/image/u-boot/patches/012-make_3.81.patch b/target/linux/at91-2.6/image/u-boot/patches/012-make_3.81.patch deleted file mode 100644 index 767493f901..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/012-make_3.81.patch +++ /dev/null @@ -1,16 +0,0 @@ -diff -urN u-boot-1.1.4.orig/examples/Makefile u-boot-1.1.4/examples/Makefile ---- u-boot-1.1.4.orig/examples/Makefile 2007-05-13 13:45:44.000000000 +0200 -+++ u-boot-1.1.4/examples/Makefile 2007-05-13 13:48:43.000000000 +0200 -@@ -123,10 +123,10 @@ - $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ - -o $@ -e $(<:.o=) $< $(LIB) \ - -L$(gcclibdir) -lgcc --%.srec: % -+%.srec: %.o - $(OBJCOPY) -O srec $< $@ 2>/dev/null - --%.bin: % -+%.bin: %.o - $(OBJCOPY) -O binary $< $@ 2>/dev/null - - ######################################################################### diff --git a/target/linux/at91-2.6/image/u-boot/patches/013-params-in-config.patch b/target/linux/at91-2.6/image/u-boot/patches/013-params-in-config.patch deleted file mode 100644 index 11ff2a39cb..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/013-params-in-config.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- u-boot-1.1.4.old/tools/Makefile 2007-06-13 13:35:59.000000000 +0200 -+++ u-boot-1.1.4/tools/Makefile 2007-06-14 15:33:04.000000000 +0200 -@@ -153,7 +153,7 @@ - $(STRIP) $@ - - ubparams.o: ubparams.c -- $(CC) -g $(CFLAGS) -c $< -+ $(CC) -g $(CFLAGS) -DLAN_IP=$(LAN_IP) -DLAN_SERVERIP=$(LAN_SERVERIP) -c $< - - envcrc.o: envcrc.c - $(CC) -g $(CFLAGS) -c $< ---- u-boot-1.1.4.old/tools/ubparams.c 2007-06-13 13:35:59.000000000 +0200 -+++ u-boot-1.1.4/tools/ubparams.c 2007-06-14 15:31:55.000000000 +0200 -@@ -44,8 +44,8 @@ - "bootargs=setenv bootargs root=/dev/mtdblock3 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" - "bootcmd=bootm 0xc0042000\0" - "ethaddr=00:30:49:00:00:01\0" -- "ipaddr=10.0.1.73\0" -- "serverip=10.0.1.210\0" -+ "ipaddr=" MK_STR(LAN_IP) "\0" -+ "serverip=" MK_STR(LAN_SERVERIP) "\0" - "serial#=MX070205484\0" - "\0" - }; diff --git a/target/linux/at91-2.6/image/u-boot/patches/014-ubparam-kernel.patch b/target/linux/at91-2.6/image/u-boot/patches/014-ubparam-kernel.patch deleted file mode 100644 index f6d0a1b191..0000000000 --- a/target/linux/at91-2.6/image/u-boot/patches/014-ubparam-kernel.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- u-boot-1.1.4.old/tools/ubparams.c 2007-06-19 14:24:39.000000000 +0200 -+++ u-boot-1.1.4/tools/ubparams.c 2007-06-19 14:25:05.000000000 +0200 -@@ -39,7 +39,7 @@ - "stderr=serial\0" - "fbargs=setenv bootargs root=/dev/mtdblock3 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" - "rdba=setenv bootargs root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" -- "rdram=run rdba; tftp 21000000 vImage; tftp 21200000 root.squashfs; bootm 21000000\0" -+ "rdram=run rdba; tftp 21000000 uImage; tftp 21200000 root.squashfs; bootm 21000000\0" - "flash=run fbargs; bootm 0xc0042000\0" - "bootargs=setenv bootargs root=/dev/mtdblock3 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" - "bootcmd=bootm 0xc0042000\0" diff --git a/target/linux/at91-2.6/image/u-boot/ubclient/Makefile b/target/linux/at91-2.6/image/u-boot/ubclient/Makefile deleted file mode 100644 index f8ff67cd18..0000000000 --- a/target/linux/at91-2.6/image/u-boot/ubclient/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# - -all: ubpar - -crc32.c: - ln -s ../lib_generic/crc32.c ./ - -%.o: %.c - $(CC) -I ../include $(CFLAGS) $(EXTRA_FLAGS) -DLAN_IP=$(LAN_IP) -DLAN_SERVERIP=$(LAN_SERVERIP) -c -o $@ $^ - -ubpar: ubpar.o crc32.o - $(CC) -o $@ $^ - -clean: - rm -f *.o ubpar diff --git a/target/linux/at91-2.6/image/u-boot/ubclient/ubpar.c b/target/linux/at91-2.6/image/u-boot/ubclient/ubpar.c deleted file mode 100644 index 7e8ea0eb2d..0000000000 --- a/target/linux/at91-2.6/image/u-boot/ubclient/ubpar.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * ubparams.c - * - * Generate a u-boot parameter block with correct crc - * - * (C) 1007 Guthrie Consulting - * hamish@prodigi.ch - * - */ - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ -#endif -#define __ASM_STUB_PROCESSOR_H__ -#include <config.h> -#undef __ASSEMBLY__ -#include <environment.h> - -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) - -extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); - -#if !defined(ENV_CRC) -#define ENV_CRC ~0 -#endif - -#ifdef LAN_IP - #warning LAN_IP -#else - #warning LAN_IP NOT DEFINED -#endif -#ifdef LAN_SERVERIP - #warning LAN_SERVERIP -#else - #warning LAN_SERVERIP NOT DEFINED -#endif - -static char *environment[] = { - "bootdelay=3\0" - "baudrate=115200\0" - "stdin=serial\0" - "stdout=serial\0" - "stderr=serial\0" - "fbargs=setenv bootargs root=/dev/mtdblock3 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" - "rdba=setenv bootargs root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" - "rdram=run rdba; tftp 21000000 uImage; tftp 21200000 root.squashfs; bootm 21000000\0" - "flash=run fbargs; bootm 0xc0042000\0" - "bootargs=setenv bootargs root=/dev/mtdblock3 ro init=/etc/preinit console=/dev/ttyS0,115200,mem=32M\0" - "bootcmd=bootm 0xc0042000\0" - "ipaddr=" MK_STR(LAN_IP) "\0" - "serverip=" MK_STR(LAN_SERVERIP) "\0" - "\0" - }; - -int main(int argc, char *argv[]) { - env_t *envptr; - char *src, *srcptr; - char *dataptr; - FILE *params; - int argfail = 1; - char newmac[30]; - char newser[30]; - int paramlen = 0; - int progmac = 0; - int progser = 0; - - if (argc < 3) { - printf ("Invalid arguments\n"); - return 1; - } - - switch (argc) { - case 5: - if (strcmp(argv[3], "--serial") == 0) { - argfail = 0; - sprintf(newser, "serial#=%s", argv[4]); - progser = 1; - } - case 3: - if (strcmp(argv[1], "--mac") == 0) { - argfail = 0; - sprintf(newmac, "ethaddr=%s", argv[2]); - progmac = 1; - } - else - argfail = 1; - } - - if (argfail) { - printf("Invalid arguments\n"); - return 1; - } - - - src = srcptr = *environment; - envptr = (env_t *)malloc(CFG_ENV_SIZE); - dataptr = (char *)envptr + ENV_HEADER_SIZE; - - while(*srcptr) { - //printf("%d, %s\n", strlen(srcptr), srcptr); - paramlen += strlen(srcptr) + 1; - srcptr += strlen(srcptr) + 1; - } - - printf("Make u-boot params\n"); - printf("Params size is %d\n", CFG_ENV_SIZE); - - memset(envptr, 0, CFG_ENV_SIZE); - memcpy(dataptr, src, paramlen); - dataptr += paramlen; - - if (progmac) { - memcpy(dataptr, newmac, strlen(newmac)); - dataptr += strlen(newmac) + 1; - } - - if (progser) { - memcpy(dataptr, newser, strlen(newser)); - dataptr += strlen(newser) + 1; - } - - envptr->crc = crc32(0, envptr->data, ENV_SIZE); - - params = fopen("/dev/mtd1", "w"); - fwrite(envptr, CFG_ENV_SIZE, 1, params); - fclose(params); - - free(envptr); - return 0; -} diff --git a/target/linux/at91-2.6/patches-2.6.21/000-at91patches.patch b/target/linux/at91-2.6/patches-2.6.21/000-at91patches.patch deleted file mode 100644 index 93fa2cf03c..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/000-at91patches.patch +++ /dev/null @@ -1,10312 +0,0 @@ -diff -urN -x CVS linux-2.6.21/arch/arm/boot/compressed/head-at91rm9200.S linux-2.6-stable/arch/arm/boot/compressed/head-at91rm9200.S ---- linux-2.6.21/arch/arm/boot/compressed/head-at91rm9200.S Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/boot/compressed/head-at91rm9200.S Tue May 8 12:13:30 2007 -@@ -67,6 +67,12 @@ - cmp r7, r3 - beq 99f - -+ @ Promwad Chub : 1181 -+ mov r3, #(MACH_TYPE_CHUB & 0xff) -+ orr r3, r3, #(MACH_TYPE_CHUB & 0xff00) -+ cmp r7, r3 -+ beq 99f -+ - @ Unknown board, use the AT91RM9200DK board - @ mov r7, #MACH_TYPE_AT91RM9200 - mov r7, #(MACH_TYPE_AT91RM9200DK & 0xff) -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/Kconfig linux-2.6-stable/arch/arm/mach-at91/Kconfig ---- linux-2.6.21/arch/arm/mach-at91/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/Kconfig Wed May 9 10:20:54 2007 -@@ -17,6 +17,9 @@ - config ARCH_AT91SAM9263 - bool "AT91SAM9263" - -+config ARCH_AT91SAM9RL -+ bool "AT91SAM9RL" -+ - endchoice - - # ---------------------------------------------------------- -@@ -87,6 +90,12 @@ - help - Select this if you are using Sperry-Sun's KAFA board. - -+config MACH_CHUB -+ bool "Promwad Chub board" -+ depends on ARCH_AT91RM9200 -+ help -+ Select this if you are using Promwad's Chub board. -+ - endif - - # ---------------------------------------------------------- -@@ -111,6 +120,13 @@ - Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit - <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> - -+config MACH_CAM60 -+ bool "KwikByte CAM60 board" -+ depends on ARCH_AT91SAM9260 -+ help -+ Select this if you are using KwikByte's CAM60 board based on the Atmel AT91SAM9260. -+ <http://www.kwikbyte.com> -+ - endif - - # ---------------------------------------------------------- -@@ -145,6 +161,20 @@ - - # ---------------------------------------------------------- - -+if ARCH_AT91SAM9RL -+ -+comment "AT91SAM9RL Board Type" -+ -+config MACH_AT91SAM9RLEK -+ bool "Atmel AT91SAM9RL-EK Evaluation Kit" -+ depends on ARCH_AT91SAM9RL -+ help -+ Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. -+ -+endif -+ -+# ---------------------------------------------------------- -+ - comment "AT91 Board Options" - - config MTD_AT91_DATAFLASH_CARD -@@ -160,6 +190,20 @@ - On AT91SAM926x boards both types of NAND flash can be present - (8 and 16 bit data bus width). - -+config CSB300_WAKE_SW0 -+ bool "CSB300 SW0 irq0 wakeup" -+ depends on MACH_CSB337 && PM -+ help -+ If you have a CSB300 connected to your CSB337, this lets -+ SW0 serve as a wakeup button. It uses IRQ0. -+ -+config CSB300_WAKE_SW1 -+ bool "CSB300 SW1 gpio wakeup" -+ depends on MACH_CSB337 && PM -+ help -+ If you have a CSB300 connected to your CSB337, this lets -+ SW1 serve as a wakeup button. It uses GPIO. -+ - # ---------------------------------------------------------- - - comment "AT91 Feature Selections" -@@ -170,6 +214,20 @@ - Select this if you need to program one or more of the PCK0..PCK3 - programmable clock outputs. - -+config ATMEL_TCLIB -+ bool "Timer/Counter Library" -+ help -+ Select this if you want a library to allocate the Timer/Counter -+ blocks found on many Atmel processors. This facilitates using -+ these modules despite processor differences. -+ -+config AT91_SLOW_CLOCK -+ bool "Suspend-to-RAM uses slow clock mode (EXPERIMENTAL)" -+ depends on PM && EXPERIMENTAL -+ help -+ Select this if you wish to put the CPU into slow clock mode -+ while in the "Suspend to RAM" state, to save more power. -+ - endmenu - - endif -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/Makefile linux-2.6-stable/arch/arm/mach-at91/Makefile ---- linux-2.6.21/arch/arm/mach-at91/Makefile Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/Makefile Wed May 9 12:37:19 2007 -@@ -8,12 +8,15 @@ - obj- := - - obj-$(CONFIG_PM) += pm.o -+obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o -+obj-$(CONFIG_ATMEL_TCLIB) += tclib.o - - # CPU-specific support - obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o - obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o - obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o - obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o -+obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o - - # AT91RM9200 board-specific support - obj-$(CONFIG_MACH_ONEARM) += board-1arm.o -@@ -25,9 +28,11 @@ - obj-$(CONFIG_MACH_KB9200) += board-kb9202.o - obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o - obj-$(CONFIG_MACH_KAFA) += board-kafa.o -+obj-$(CONFIG_MACH_CHUB) += board-chub.o - - # AT91SAM9260 board-specific support - obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o -+obj-$(CONFIG_MACH_CAM60) += board-cam60.o - - # AT91SAM9261 board-specific support - obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o -@@ -35,9 +40,13 @@ - # AT91SAM9263 board-specific support - obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o - -+# AT91SAM9RL board-specific support -+obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o -+ - # LEDs support - led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o - led-$(CONFIG_MACH_AT91RM9200EK) += leds.o -+led-$(CONFIG_MACH_AT91SAM9261EK)+= leds.o - led-$(CONFIG_MACH_CSB337) += leds.o - led-$(CONFIG_MACH_CSB637) += leds.o - led-$(CONFIG_MACH_KB9200) += leds.o -@@ -45,7 +54,7 @@ - obj-$(CONFIG_LEDS) += $(led-y) - - # VGA support --#obj-$(CONFIG_FB_S1D13XXX) += ics1523.o -+obj-$(CONFIG_FB_S1D13XXX) += ics1523.o - - - ifeq ($(CONFIG_PM_DEBUG),y) -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91rm9200.c linux-2.6-stable/arch/arm/mach-at91/at91rm9200.c ---- linux-2.6.21/arch/arm/mach-at91/at91rm9200.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/at91rm9200.c Tue May 8 12:13:30 2007 -@@ -117,6 +117,21 @@ - .pmc_mask = 1 << AT91RM9200_ID_PIOD, - .type = CLK_TYPE_PERIPHERAL, - }; -+static struct clk ssc0_clk = { -+ .name = "ssc0_clk", -+ .pmc_mask = 1 << AT91RM9200_ID_SSC0, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk ssc1_clk = { -+ .name = "ssc1_clk", -+ .pmc_mask = 1 << AT91RM9200_ID_SSC1, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk ssc2_clk = { -+ .name = "ssc2_clk", -+ .pmc_mask = 1 << AT91RM9200_ID_SSC2, -+ .type = CLK_TYPE_PERIPHERAL, -+}; - static struct clk tc0_clk = { - .name = "tc0_clk", - .pmc_mask = 1 << AT91RM9200_ID_TC0, -@@ -161,7 +176,9 @@ - &udc_clk, - &twi_clk, - &spi_clk, -- // ssc 0 .. ssc2 -+ &ssc0_clk, -+ &ssc1_clk, -+ &ssc2_clk, - &tc0_clk, - &tc1_clk, - &tc2_clk, -@@ -250,6 +267,33 @@ - - - /* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91rm9200_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91RM9200_BASE_TCB0, -+ .irq = { AT91RM9200_ID_TC0, AT91RM9200_ID_TC1, AT91RM9200_ID_TC2 }, -+ .clk = { &tc0_clk, &tc1_clk, &tc2_clk }, -+ }, -+ [1] = { -+ .physaddr = AT91RM9200_BASE_TCB1, -+ .irq = { AT91RM9200_ID_TC3, AT91RM9200_ID_TC4, AT91RM9200_ID_TC5 }, -+ .clk = { &tc3_clk, &tc4_clk, &tc5_clk }, -+ }, -+}; -+ -+#define at91rm9200_tc_init() atmel_tc_init(at91rm9200_tcblocks, ARRAY_SIZE(at91rm9200_tcblocks)) -+ -+#else -+#define at91rm9200_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * AT91RM9200 processor initialization - * -------------------------------------------------------------------- */ - void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks) -@@ -271,6 +315,9 @@ - - /* Initialize GPIO subsystem */ - at91_gpio_init(at91rm9200_gpio, banks); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91rm9200_tc_init(); - } - - -@@ -284,28 +331,28 @@ - static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller (FIQ) */ - 7, /* System Peripherals */ -- 0, /* Parallel IO Controller A */ -- 0, /* Parallel IO Controller B */ -- 0, /* Parallel IO Controller C */ -- 0, /* Parallel IO Controller D */ -- 6, /* USART 0 */ -- 6, /* USART 1 */ -- 6, /* USART 2 */ -- 6, /* USART 3 */ -+ 1, /* Parallel IO Controller A */ -+ 1, /* Parallel IO Controller B */ -+ 1, /* Parallel IO Controller C */ -+ 1, /* Parallel IO Controller D */ -+ 5, /* USART 0 */ -+ 5, /* USART 1 */ -+ 5, /* USART 2 */ -+ 5, /* USART 3 */ - 0, /* Multimedia Card Interface */ -- 4, /* USB Device Port */ -- 0, /* Two-Wire Interface */ -- 6, /* Serial Peripheral Interface */ -- 5, /* Serial Synchronous Controller 0 */ -- 5, /* Serial Synchronous Controller 1 */ -- 5, /* Serial Synchronous Controller 2 */ -+ 2, /* USB Device Port */ -+ 6, /* Two-Wire Interface */ -+ 5, /* Serial Peripheral Interface */ -+ 4, /* Serial Synchronous Controller 0 */ -+ 4, /* Serial Synchronous Controller 1 */ -+ 4, /* Serial Synchronous Controller 2 */ - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ - 0, /* Timer Counter 3 */ - 0, /* Timer Counter 4 */ - 0, /* Timer Counter 5 */ -- 3, /* USB Host port */ -+ 2, /* USB Host port */ - 3, /* Ethernet MAC */ - 0, /* Advanced Interrupt Controller (IRQ0) */ - 0, /* Advanced Interrupt Controller (IRQ1) */ -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91rm9200_devices.c linux-2.6-stable/arch/arm/mach-at91/at91rm9200_devices.c ---- linux-2.6.21/arch/arm/mach-at91/at91rm9200_devices.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/at91rm9200_devices.c Tue May 8 12:13:30 2007 -@@ -480,7 +480,18 @@ - * SPI - * -------------------------------------------------------------------- */ - --#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) -+#if defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) /* legacy SPI driver */ -+#define SPI_DEVNAME "at91_spi" -+ -+#elif defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) /* SPI bitbanging driver */ -+#define SPI_DEVNAME "at91_spi" -+ -+#elif defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) /* new SPI driver */ -+#define SPI_DEVNAME "atmel_spi" -+ -+#endif -+ -+#ifdef SPI_DEVNAME - static u64 spi_dmamask = 0xffffffffUL; - - static struct resource spi_resources[] = { -@@ -497,7 +508,7 @@ - }; - - static struct platform_device at91rm9200_spi_device = { -- .name = "at91_spi", -+ .name = SPI_DEVNAME, - .id = 0, - .dev = { - .dma_mask = &spi_dmamask, -@@ -606,6 +617,32 @@ - #endif - - -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ - /* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9260.c linux-2.6-stable/arch/arm/mach-at91/at91sam9260.c ---- linux-2.6.21/arch/arm/mach-at91/at91sam9260.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/at91sam9260.c Tue May 8 12:13:30 2007 -@@ -119,6 +119,11 @@ - .pmc_mask = 1 << AT91SAM9260_ID_SPI1, - .type = CLK_TYPE_PERIPHERAL, - }; -+static struct clk ssc_clk = { -+ .name = "ssc_clk", -+ .pmc_mask = 1 << AT91SAM9260_ID_SSC, -+ .type = CLK_TYPE_PERIPHERAL, -+}; - static struct clk tc0_clk = { - .name = "tc0_clk", - .pmc_mask = 1 << AT91SAM9260_ID_TC0, -@@ -193,7 +198,7 @@ - &twi_clk, - &spi0_clk, - &spi1_clk, -- // ssc -+ &ssc_clk, - &tc0_clk, - &tc1_clk, - &tc2_clk, -@@ -264,6 +269,33 @@ - - - /* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91sam9260_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91SAM9260_BASE_TCB0, -+ .irq = { AT91SAM9260_ID_TC0, AT91SAM9260_ID_TC1, AT91SAM9260_ID_TC2 }, -+ .clk = { &tc0_clk, &tc1_clk, &tc2_clk }, -+ }, -+ [1] = { -+ .physaddr = AT91SAM9260_BASE_TCB1, -+ .irq = { AT91SAM9260_ID_TC3, AT91SAM9260_ID_TC4, AT91SAM9260_ID_TC5 }, -+ .clk = { &tc3_clk, &tc4_clk, &tc5_clk }, -+ }, -+}; -+ -+#define at91sam9260_tc_init() atmel_tc_init(at91sam9260_tcblocks, ARRAY_SIZE(at91sam9260_tcblocks)) -+ -+#else -+#define at91sam9260_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * AT91SAM9260 processor initialization - * -------------------------------------------------------------------- */ - -@@ -310,6 +342,9 @@ - - /* Register GPIO subsystem */ - at91_gpio_init(at91sam9260_gpio, 3); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91sam9260_tc_init(); - } - - /* -------------------------------------------------------------------- -@@ -322,30 +357,30 @@ - static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller */ - 7, /* System Peripherals */ -- 0, /* Parallel IO Controller A */ -- 0, /* Parallel IO Controller B */ -- 0, /* Parallel IO Controller C */ -+ 1, /* Parallel IO Controller A */ -+ 1, /* Parallel IO Controller B */ -+ 1, /* Parallel IO Controller C */ - 0, /* Analog-to-Digital Converter */ -- 6, /* USART 0 */ -- 6, /* USART 1 */ -- 6, /* USART 2 */ -+ 5, /* USART 0 */ -+ 5, /* USART 1 */ -+ 5, /* USART 2 */ - 0, /* Multimedia Card Interface */ -- 4, /* USB Device Port */ -- 0, /* Two-Wire Interface */ -- 6, /* Serial Peripheral Interface 0 */ -- 6, /* Serial Peripheral Interface 1 */ -+ 2, /* USB Device Port */ -+ 6, /* Two-Wire Interface */ -+ 5, /* Serial Peripheral Interface 0 */ -+ 5, /* Serial Peripheral Interface 1 */ - 5, /* Serial Synchronous Controller */ - 0, - 0, - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ -- 3, /* USB Host port */ -+ 2, /* USB Host port */ - 3, /* Ethernet */ - 0, /* Image Sensor Interface */ -- 6, /* USART 3 */ -- 6, /* USART 4 */ -- 6, /* USART 5 */ -+ 5, /* USART 3 */ -+ 5, /* USART 4 */ -+ 5, /* USART 5 */ - 0, /* Timer Counter 3 */ - 0, /* Timer Counter 4 */ - 0, /* Timer Counter 5 */ -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9260_devices.c linux-2.6-stable/arch/arm/mach-at91/at91sam9260_devices.c ---- linux-2.6.21/arch/arm/mach-at91/at91sam9260_devices.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/at91sam9260_devices.c Tue May 8 12:13:30 2007 -@@ -527,6 +527,32 @@ - #endif - - -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ - /* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9261.c linux-2.6-stable/arch/arm/mach-at91/at91sam9261.c ---- linux-2.6.21/arch/arm/mach-at91/at91sam9261.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/at91sam9261.c Tue May 8 12:13:30 2007 -@@ -97,6 +97,21 @@ - .pmc_mask = 1 << AT91SAM9261_ID_SPI1, - .type = CLK_TYPE_PERIPHERAL, - }; -+static struct clk ssc0_clk = { -+ .name = "ssc0_clk", -+ .pmc_mask = 1 << AT91SAM9261_ID_SSC0, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk ssc1_clk = { -+ .name = "ssc1_clk", -+ .pmc_mask = 1 << AT91SAM9261_ID_SSC1, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk ssc2_clk = { -+ .name = "ssc2_clk", -+ .pmc_mask = 1 << AT91SAM9261_ID_SSC2, -+ .type = CLK_TYPE_PERIPHERAL, -+}; - static struct clk tc0_clk = { - .name = "tc0_clk", - .pmc_mask = 1 << AT91SAM9261_ID_TC0, -@@ -135,7 +150,9 @@ - &twi_clk, - &spi0_clk, - &spi1_clk, -- // ssc 0 .. ssc2 -+ &ssc0_clk, -+ &ssc1_clk, -+ &ssc2_clk, - &tc0_clk, - &tc1_clk, - &tc2_clk, -@@ -230,6 +247,28 @@ - - - /* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91sam9261_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91SAM9261_BASE_TCB0, -+ .irq = { AT91SAM9261_ID_TC0, AT91SAM9261_ID_TC1, AT91SAM9261_ID_TC2 }, -+ .clk = { &tc0_clk, &tc1_clk, &tc2_clk }, -+ } -+}; -+ -+#define at91sam9261_tc_init() atmel_tc_init(at91sam9261_tcblocks, ARRAY_SIZE(at91sam9261_tcblocks)) -+ -+#else -+#define at91sam9261_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * AT91SAM9261 processor initialization - * -------------------------------------------------------------------- */ - -@@ -250,6 +289,9 @@ - - /* Register GPIO subsystem */ - at91_gpio_init(at91sam9261_gpio, 3); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91sam9261_tc_init(); - } - - /* -------------------------------------------------------------------- -@@ -262,25 +304,25 @@ - static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller */ - 7, /* System Peripherals */ -- 0, /* Parallel IO Controller A */ -- 0, /* Parallel IO Controller B */ -- 0, /* Parallel IO Controller C */ -+ 1, /* Parallel IO Controller A */ -+ 1, /* Parallel IO Controller B */ -+ 1, /* Parallel IO Controller C */ - 0, -- 6, /* USART 0 */ -- 6, /* USART 1 */ -- 6, /* USART 2 */ -+ 5, /* USART 0 */ -+ 5, /* USART 1 */ -+ 5, /* USART 2 */ - 0, /* Multimedia Card Interface */ -- 4, /* USB Device Port */ -- 0, /* Two-Wire Interface */ -- 6, /* Serial Peripheral Interface 0 */ -- 6, /* Serial Peripheral Interface 1 */ -- 5, /* Serial Synchronous Controller 0 */ -- 5, /* Serial Synchronous Controller 1 */ -- 5, /* Serial Synchronous Controller 2 */ -+ 2, /* USB Device Port */ -+ 6, /* Two-Wire Interface */ -+ 5, /* Serial Peripheral Interface 0 */ -+ 5, /* Serial Peripheral Interface 1 */ -+ 4, /* Serial Synchronous Controller 0 */ -+ 4, /* Serial Synchronous Controller 1 */ -+ 4, /* Serial Synchronous Controller 2 */ - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ -- 3, /* USB Host port */ -+ 2, /* USB Host port */ - 3, /* LCD Controller */ - 0, - 0, -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9261_devices.c linux-2.6-stable/arch/arm/mach-at91/at91sam9261_devices.c ---- linux-2.6.21/arch/arm/mach-at91/at91sam9261_devices.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/at91sam9261_devices.c Tue May 8 12:56:33 2007 -@@ -14,6 +14,9 @@ - #include <asm/mach/map.h> - - #include <linux/platform_device.h> -+#include <linux/fb.h> -+ -+#include <video/atmel_lcdc.h> - - #include <asm/arch/board.h> - #include <asm/arch/gpio.h> -@@ -430,9 +433,9 @@ - * LCD Controller - * -------------------------------------------------------------------- */ - --#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE) -+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) - static u64 lcdc_dmamask = 0xffffffffUL; --static struct at91fb_info lcdc_data; -+static struct atmel_lcdfb_info lcdc_data; - - static struct resource lcdc_resources[] = { - [0] = { -@@ -455,7 +458,7 @@ - }; - - static struct platform_device at91_lcdc_device = { -- .name = "at91-fb", -+ .name = "atmel_lcdfb", - .id = 0, - .dev = { - .dma_mask = &lcdc_dmamask, -@@ -466,7 +469,7 @@ - .num_resources = ARRAY_SIZE(lcdc_resources), - }; - --void __init at91_add_device_lcdc(struct at91fb_info *data) -+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) - { - if (!data) { - return; -@@ -499,7 +502,7 @@ - platform_device_register(&at91_lcdc_device); - } - #else --void __init at91_add_device_lcdc(struct at91fb_info *data) {} -+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} - #endif - - -@@ -525,6 +528,32 @@ - #endif - - -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ - /* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9263.c linux-2.6-stable/arch/arm/mach-at91/at91sam9263.c ---- linux-2.6.21/arch/arm/mach-at91/at91sam9263.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/at91sam9263.c Tue May 8 12:13:30 2007 -@@ -87,6 +87,11 @@ - .pmc_mask = 1 << AT91SAM9263_ID_MCI1, - .type = CLK_TYPE_PERIPHERAL, - }; -+static struct clk can_clk = { -+ .name = "can_clk", -+ .pmc_mask = 1 << AT91SAM9263_ID_CAN, -+ .type = CLK_TYPE_PERIPHERAL, -+}; - static struct clk twi_clk = { - .name = "twi_clk", - .pmc_mask = 1 << AT91SAM9263_ID_TWI, -@@ -102,16 +107,46 @@ - .pmc_mask = 1 << AT91SAM9263_ID_SPI1, - .type = CLK_TYPE_PERIPHERAL, - }; -+static struct clk ssc0_clk = { -+ .name = "ssc0_clk", -+ .pmc_mask = 1 << AT91SAM9263_ID_SSC0, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk ssc1_clk = { -+ .name = "ssc1_clk", -+ .pmc_mask = 1 << AT91SAM9263_ID_SSC1, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk ac97_clk = { -+ .name = "ac97_clk", -+ .pmc_mask = 1 << AT91SAM9263_ID_AC97C, -+ .type = CLK_TYPE_PERIPHERAL, -+}; - static struct clk tcb_clk = { - .name = "tcb_clk", - .pmc_mask = 1 << AT91SAM9263_ID_TCB, - .type = CLK_TYPE_PERIPHERAL, - }; -+static struct clk pwmc_clk = { -+ .name = "pwmc_clk", -+ .pmc_mask = 1 << AT91SAM9263_ID_PWMC, -+ .type = CLK_TYPE_PERIPHERAL, -+}; - static struct clk macb_clk = { - .name = "macb_clk", - .pmc_mask = 1 << AT91SAM9263_ID_EMAC, - .type = CLK_TYPE_PERIPHERAL, - }; -+static struct clk dma_clk = { -+ .name = "dma_clk", -+ .pmc_mask = 1 << AT91SAM9263_ID_DMA, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk twodge_clk = { -+ .name = "2dge_clk", -+ .pmc_mask = 1 << AT91SAM9263_ID_2DGE, -+ .type = CLK_TYPE_PERIPHERAL, -+}; - static struct clk udc_clk = { - .name = "udc_clk", - .pmc_mask = 1 << AT91SAM9263_ID_UDP, -@@ -142,20 +177,21 @@ - &usart2_clk, - &mmc0_clk, - &mmc1_clk, -- // can -+ &can_clk, - &twi_clk, - &spi0_clk, - &spi1_clk, -- // ssc0 .. ssc1 -- // ac97 -+ &ssc0_clk, -+ &ssc1_clk, -+ &ac97_clk, - &tcb_clk, -- // pwmc -+ &pwmc_clk, - &macb_clk, -- // 2dge -+ &twodge_clk, - &udc_clk, - &isi_clk, - &lcdc_clk, -- // dma -+ &dma_clk, - &ohci_clk, - // irq0 .. irq1 - }; -@@ -237,6 +273,28 @@ - - - /* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91sam9263_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91SAM9263_BASE_TCB0, -+ .irq = { AT91SAM9263_ID_TCB, AT91SAM9263_ID_TCB, AT91SAM9263_ID_TCB }, -+ .clk = { &tcb_clk, &tcb_clk, &tcb_clk }, -+ } -+}; -+ -+#define at91sam9263_tc_init() atmel_tc_init(at91sam9263_tcblocks, ARRAY_SIZE(at91sam9263_tcblocks)) -+ -+#else -+#define at91sam9263_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * AT91SAM9263 processor initialization - * -------------------------------------------------------------------- */ - -@@ -256,6 +314,9 @@ - - /* Register GPIO subsystem */ - at91_gpio_init(at91sam9263_gpio, 5); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91sam9263_tc_init(); - } - - /* -------------------------------------------------------------------- -@@ -268,34 +329,34 @@ - static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller (FIQ) */ - 7, /* System Peripherals */ -- 0, /* Parallel IO Controller A */ -- 0, /* Parallel IO Controller B */ -- 0, /* Parallel IO Controller C, D and E */ -+ 1, /* Parallel IO Controller A */ -+ 1, /* Parallel IO Controller B */ -+ 1, /* Parallel IO Controller C, D and E */ - 0, - 0, -- 6, /* USART 0 */ -- 6, /* USART 1 */ -- 6, /* USART 2 */ -+ 5, /* USART 0 */ -+ 5, /* USART 1 */ -+ 5, /* USART 2 */ - 0, /* Multimedia Card Interface 0 */ - 0, /* Multimedia Card Interface 1 */ -- 4, /* CAN */ -- 0, /* Two-Wire Interface */ -- 6, /* Serial Peripheral Interface 0 */ -- 6, /* Serial Peripheral Interface 1 */ -- 5, /* Serial Synchronous Controller 0 */ -- 5, /* Serial Synchronous Controller 1 */ -- 6, /* AC97 Controller */ -+ 3, /* CAN */ -+ 6, /* Two-Wire Interface */ -+ 5, /* Serial Peripheral Interface 0 */ -+ 5, /* Serial Peripheral Interface 1 */ -+ 4, /* Serial Synchronous Controller 0 */ -+ 4, /* Serial Synchronous Controller 1 */ -+ 5, /* AC97 Controller */ - 0, /* Timer Counter 0, 1 and 2 */ - 0, /* Pulse Width Modulation Controller */ - 3, /* Ethernet */ - 0, - 0, /* 2D Graphic Engine */ -- 3, /* USB Device Port */ -+ 2, /* USB Device Port */ - 0, /* Image Sensor Interface */ - 3, /* LDC Controller */ - 0, /* DMA Controller */ - 0, -- 3, /* USB Host port */ -+ 2, /* USB Host port */ - 0, /* Advanced Interrupt Controller (IRQ0) */ - 0, /* Advanced Interrupt Controller (IRQ1) */ - }; -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9263_devices.c linux-2.6-stable/arch/arm/mach-at91/at91sam9263_devices.c ---- linux-2.6.21/arch/arm/mach-at91/at91sam9263_devices.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/at91sam9263_devices.c Thu May 10 12:23:46 2007 -@@ -13,6 +13,9 @@ - #include <asm/mach/map.h> - - #include <linux/platform_device.h> -+#include <linux/fb.h> -+ -+#include <video/atmel_lcdc.h> - - #include <asm/arch/board.h> - #include <asm/arch/gpio.h> -@@ -573,6 +576,180 @@ - - - /* -------------------------------------------------------------------- -+ * AC97 -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE) -+static u64 ac97_dmamask = 0xffffffffUL; -+static struct atmel_ac97_data ac97_data; -+ -+static struct resource ac97_resources[] = { -+ [0] = { -+ .start = AT91SAM9263_BASE_AC97C, -+ .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9263_ID_AC97C, -+ .end = AT91SAM9263_ID_AC97C, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device at91sam9263_ac97_device = { -+ .name = "ac97c", -+ .id = 1, -+ .dev = { -+ .dma_mask = &ac97_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &ac97_data, -+ }, -+ .resource = ac97_resources, -+ .num_resources = ARRAY_SIZE(ac97_resources), -+}; -+ -+void __init at91_add_device_ac97(struct atmel_ac97_data *data) -+{ -+ if (!data) -+ return; -+ -+ at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */ -+ at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */ -+ at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */ -+ at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */ -+ -+ /* reset */ -+ if (data->reset_pin) -+ at91_set_gpio_output(data->reset_pin, 0); -+ -+ ac97_data = *ek_data; -+ platform_device_register(&at91sam9263_ac97_device); -+} -+#else -+void __init at91_add_device_ac97(struct atmel_ac97_data *data) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- -+ * Image Sensor Interface -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE) -+ -+struct resource isi_resources[] = { -+ [0] = { -+ .start = AT91SAM9263_BASE_ISI, -+ .end = AT91SAM9263_BASE_ISI + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9263_ID_ISI, -+ .end = AT91SAM9263_ID_ISI, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device at91sam9263_isi_device = { -+ .name = "at91_isi", -+ .id = -1, -+ .resource = isi_resources, -+ .num_resources = ARRAY_SIZE(isi_resources), -+}; -+ -+void __init at91_add_device_isi(void) -+{ -+ at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */ -+ at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */ -+ at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */ -+ at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */ -+ at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */ -+ at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */ -+ at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */ -+ at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */ -+ at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */ -+ at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */ -+ at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */ -+ at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */ -+ at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */ -+ at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */ -+ at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */ -+ at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */ -+} -+#else -+void __init at91_add_device_isi(void) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- -+ * LCD Controller -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) -+static u64 lcdc_dmamask = 0xffffffffUL; -+static struct atmel_lcdfb_info lcdc_data; -+ -+static struct resource lcdc_resources[] = { -+ [0] = { -+ .start = AT91SAM9263_LCDC_BASE, -+ .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9263_ID_LCDC, -+ .end = AT91SAM9263_ID_LCDC, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device at91_lcdc_device = { -+ .name = "atmel_lcdfb", -+ .id = 0, -+ .dev = { -+ .dma_mask = &lcdc_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &lcdc_data, -+ }, -+ .resource = lcdc_resources, -+ .num_resources = ARRAY_SIZE(lcdc_resources), -+}; -+ -+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) -+{ -+ if (!data) -+ return; -+ -+ at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ -+ at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ -+ at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ -+ at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ -+ at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ -+ at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ -+ at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ -+ at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ -+ at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ -+ at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ -+ at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ -+ at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ -+ at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ -+ at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ -+ at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ -+ at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ -+ at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ -+ at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ -+ at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ -+ at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ -+ at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ -+ at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ -+ -+ lcdc_data = *data; -+ platform_device_register(&at91_lcdc_device); -+} -+#else -+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * LEDs - * -------------------------------------------------------------------- */ - -@@ -594,6 +771,32 @@ - #endif - - -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ - /* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9rl.c linux-2.6-stable/arch/arm/mach-at91/at91sam9rl.c ---- linux-2.6.21/arch/arm/mach-at91/at91sam9rl.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/arch/arm/mach-at91/at91sam9rl.c Fri May 11 15:48:14 2007 -@@ -0,0 +1,366 @@ -+/* -+ * arch/arm/mach-at91/at91sam9rl.c -+ * -+ * Copyright (C) 2005 SAN People -+ * Copyright (C) 2007 Atmel Corporation -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive for -+ * more details. -+ */ -+ -+#include <linux/module.h> -+ -+#include <asm/mach/arch.h> -+#include <asm/mach/map.h> -+#include <asm/arch/cpu.h> -+#include <asm/arch/at91sam9rl.h> -+#include <asm/arch/at91_pmc.h> -+#include <asm/arch/at91_rstc.h> -+ -+#include "generic.h" -+#include "clock.h" -+ -+static struct map_desc at91sam9rl_io_desc[] __initdata = { -+ { -+ .virtual = AT91_VA_BASE_SYS, -+ .pfn = __phys_to_pfn(AT91_BASE_SYS), -+ .length = SZ_16K, -+ .type = MT_DEVICE, -+ }, -+}; -+ -+static struct map_desc at91sam9rl_sram_desc[] __initdata = { -+ { -+ .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE), -+ .type = MT_DEVICE, -+ } -+}; -+ -+/* -------------------------------------------------------------------- -+ * Clocks -+ * -------------------------------------------------------------------- */ -+ -+/* -+ * The peripheral clocks. -+ */ -+static struct clk pioA_clk = { -+ .name = "pioA_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_PIOA, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk pioB_clk = { -+ .name = "pioB_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_PIOB, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk pioC_clk = { -+ .name = "pioC_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_PIOC, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk pioD_clk = { -+ .name = "pioD_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_PIOD, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk usart0_clk = { -+ .name = "usart0_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_US0, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk usart1_clk = { -+ .name = "usart1_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_US1, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk usart2_clk = { -+ .name = "usart2_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_US2, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk usart3_clk = { -+ .name = "usart3_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_US3, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk mmc_clk = { -+ .name = "mci_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_MCI, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk twi0_clk = { -+ .name = "twi0_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_TWI0, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk twi1_clk = { -+ .name = "twi1_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_TWI1, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk spi_clk = { -+ .name = "spi_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_SPI, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk ssc0_clk = { -+ .name = "ssc0_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_SSC0, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk ssc1_clk = { -+ .name = "ssc1_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_SSC1, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk tc0_clk = { -+ .name = "tc0_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_TC0, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk tc1_clk = { -+ .name = "tc1_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_TC1, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk tc2_clk = { -+ .name = "tc2_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_TC2, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk pwmc_clk = { -+ .name = "pwmc_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_PWMC, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk tsc_clk = { -+ .name = "tsc_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_TSC, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk dma_clk = { -+ .name = "dma_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_DMA, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk udphs_clk = { -+ .name = "udphs_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk lcdc_clk = { -+ .name = "lcdc_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_LCDC, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+static struct clk ac97_clk = { -+ .name = "ac97_clk", -+ .pmc_mask = 1 << AT91SAM9RL_ID_AC97C, -+ .type = CLK_TYPE_PERIPHERAL, -+}; -+ -+static struct clk *periph_clocks[] __initdata = { -+ &pioA_clk, -+ &pioB_clk, -+ &pioC_clk, -+ &pioD_clk, -+ &usart0_clk, -+ &usart1_clk, -+ &usart2_clk, -+ &usart3_clk, -+ &mmc_clk, -+ &twi0_clk, -+ &twi1_clk, -+ &spi_clk, -+ &ssc0_clk, -+ &ssc1_clk, -+ &tc0_clk, -+ &tc1_clk, -+ &tc2_clk, -+ &pwmc_clk, -+ &tsc_clk, -+ &dma_clk, -+ &udphs_clk, -+ &lcdc_clk, -+ &ac97_clk, -+ // irq0 -+}; -+ -+/* -+ * The two programmable clocks. -+ * You must configure pin multiplexing to bring these signals out. -+ */ -+static struct clk pck0 = { -+ .name = "pck0", -+ .pmc_mask = AT91_PMC_PCK0, -+ .type = CLK_TYPE_PROGRAMMABLE, -+ .id = 0, -+}; -+static struct clk pck1 = { -+ .name = "pck1", -+ .pmc_mask = AT91_PMC_PCK1, -+ .type = CLK_TYPE_PROGRAMMABLE, -+ .id = 1, -+}; -+ -+static void __init at91sam9rl_register_clocks(void) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) -+ clk_register(periph_clocks[i]); -+ -+ clk_register(&pck0); -+ clk_register(&pck1); -+} -+ -+/* -------------------------------------------------------------------- -+ * GPIO -+ * -------------------------------------------------------------------- */ -+ -+static struct at91_gpio_bank at91sam9rl_gpio[] = { -+ { -+ .id = AT91SAM9RL_ID_PIOA, -+ .offset = AT91_PIOA, -+ .clock = &pioA_clk, -+ }, { -+ .id = AT91SAM9RL_ID_PIOB, -+ .offset = AT91_PIOB, -+ .clock = &pioB_clk, -+ }, { -+ .id = AT91SAM9RL_ID_PIOC, -+ .offset = AT91_PIOC, -+ .clock = &pioC_clk, -+ }, { -+ .id = AT91SAM9RL_ID_PIOD, -+ .offset = AT91_PIOD, -+ .clock = &pioD_clk, -+ } -+}; -+ -+static void at91sam9rl_reset(void) -+{ -+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -+} -+ -+ -+/* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91sam9rl_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91SAM9RL_BASE_TCB0, -+ .irq = { AT91SAM9RL_ID_TC0, AT91SAM9RL_ID_TC1, AT91SAM9RL_ID_TC2 }, -+ .clk = { &tc0_clk, &tc1_clk, &tc2_clk }, -+ } -+}; -+ -+#define at91sam9rl_tc_init() atmel_tc_init(at91sam9rl_tcblocks, ARRAY_SIZE(at91sam9rl_tcblocks)) -+ -+#else -+#define at91sam9rl_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- -+ * AT91SAM9RL processor initialization -+ * -------------------------------------------------------------------- */ -+ -+void __init at91sam9rl_initialize(unsigned long main_clock) -+{ -+ unsigned long cidr, sram_size; -+ -+ /* Map peripherals */ -+ iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc)); -+ -+ cidr = at91_sys_read(AT91_DBGU_CIDR); -+ -+ switch (cidr & AT91_CIDR_SRAMSIZ) { -+ case AT91_CIDR_SRAMSIZ_32K: -+ sram_size = 2 * SZ_16K; -+ break; -+ case AT91_CIDR_SRAMSIZ_16K: -+ default: -+ sram_size = SZ_16K; -+ } -+ -+ at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size; -+ at91sam9rl_sram_desc->length = sram_size; -+ -+ /* Map SRAM */ -+ iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); -+ -+ at91_arch_reset = at91sam9rl_reset; -+ at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); -+ -+ /* Init clock subsystem */ -+ at91_clock_init(main_clock); -+ -+ /* Register the processor-specific clocks */ -+ at91sam9rl_register_clocks(); -+ -+ /* Register GPIO subsystem */ -+ at91_gpio_init(at91sam9rl_gpio, 4); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91sam9rl_tc_init(); -+} -+ -+/* -------------------------------------------------------------------- -+ * Interrupt initialization -+ * -------------------------------------------------------------------- */ -+ -+/* -+ * The default interrupt priority levels (0 = lowest, 7 = highest). -+ */ -+static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { -+ 7, /* Advanced Interrupt Controller */ -+ 7, /* System Peripherals */ -+ 1, /* Parallel IO Controller A */ -+ 1, /* Parallel IO Controller B */ -+ 1, /* Parallel IO Controller C */ -+ 1, /* Parallel IO Controller D */ -+ 5, /* USART 0 */ -+ 5, /* USART 1 */ -+ 5, /* USART 2 */ -+ 5, /* USART 3 */ -+ 0, /* Multimedia Card Interface */ -+ 6, /* Two-Wire Interface 0 */ -+ 6, /* Two-Wire Interface 1 */ -+ 5, /* Serial Peripheral Interface */ -+ 4, /* Serial Synchronous Controller 0 */ -+ 4, /* Serial Synchronous Controller 1 */ -+ 0, /* Timer Counter 0 */ -+ 0, /* Timer Counter 1 */ -+ 0, /* Timer Counter 2 */ -+ 0, -+ 0, /* Touch Screen Controller */ -+ 0, /* DMA Controller */ -+ 2, /* USB Device High speed port */ -+ 2, /* LCD Controller */ -+ 6, /* AC97 Controller */ -+ 0, -+ 0, -+ 0, -+ 0, -+ 0, -+ 0, -+ 0, /* Advanced Interrupt Controller */ -+}; -+ -+void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -+{ -+ if (!priority) -+ priority = at91sam9rl_default_irq_priority; -+ -+ /* Initialize the AIC interrupt controller */ -+ at91_aic_init(priority); -+ -+ /* Enable GPIO interrupts */ -+ at91_gpio_irq_setup(); -+} -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9rl_devices.c linux-2.6-stable/arch/arm/mach-at91/at91sam9rl_devices.c ---- linux-2.6.21/arch/arm/mach-at91/at91sam9rl_devices.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/arch/arm/mach-at91/at91sam9rl_devices.c Fri May 11 16:03:25 2007 -@@ -0,0 +1,660 @@ -+/* -+ * Copyright (C) 2007 Atmel Corporation -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive for -+ * more details. -+ */ -+ -+#include <asm/mach/arch.h> -+#include <asm/mach/map.h> -+ -+#include <linux/platform_device.h> -+#include <linux/fb.h> -+ -+#include <video/atmel_lcdc.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+#include <asm/arch/at91sam9rl.h> -+#include <asm/arch/at91sam9rl_matrix.h> -+#include <asm/arch/at91sam926x_mc.h> -+ -+#include "generic.h" -+ -+#define SZ_512 0x00000200 -+#define SZ_256 0x00000100 -+#define SZ_16 0x00000010 -+ -+ -+/* -------------------------------------------------------------------- -+ * MMC / SD -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) -+static u64 mmc_dmamask = 0xffffffffUL; -+static struct at91_mmc_data mmc_data; -+ -+static struct resource mmc_resources[] = { -+ [0] = { -+ .start = AT91SAM9RL_BASE_MCI, -+ .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9RL_ID_MCI, -+ .end = AT91SAM9RL_ID_MCI, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device at91sam9rl_mmc_device = { -+ .name = "at91_mci", -+ .id = -1, -+ .dev = { -+ .dma_mask = &mmc_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &mmc_data, -+ }, -+ .resource = mmc_resources, -+ .num_resources = ARRAY_SIZE(mmc_resources), -+}; -+ -+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) -+{ -+ if (!data) -+ return; -+ -+ /* input/irq */ -+ if (data->det_pin) { -+ at91_set_gpio_input(data->det_pin, 1); -+ at91_set_deglitch(data->det_pin, 1); -+ } -+ if (data->wp_pin) -+ at91_set_gpio_input(data->wp_pin, 1); -+ if (data->vcc_pin) -+ at91_set_gpio_output(data->vcc_pin, 0); -+ -+ /* CLK */ -+ at91_set_A_periph(AT91_PIN_PA2, 0); -+ -+ /* CMD */ -+ at91_set_A_periph(AT91_PIN_PA1, 1); -+ -+ /* DAT0, maybe DAT1..DAT3 */ -+ at91_set_A_periph(AT91_PIN_PA0, 1); -+ if (data->wire4) { -+ at91_set_A_periph(AT91_PIN_PA3, 1); -+ at91_set_A_periph(AT91_PIN_PA4, 1); -+ at91_set_A_periph(AT91_PIN_PA5, 1); -+ } -+ -+ mmc_data = *data; -+ platform_device_register(&at91sam9rl_mmc_device); -+} -+#else -+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- -+ * NAND / SmartMedia -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) -+static struct at91_nand_data nand_data; -+ -+#define NAND_BASE AT91_CHIPSELECT_3 -+ -+static struct resource nand_resources[] = { -+ { -+ .start = NAND_BASE, -+ .end = NAND_BASE + SZ_256M - 1, -+ .flags = IORESOURCE_MEM, -+ } -+}; -+ -+static struct platform_device at91_nand_device = { -+ .name = "at91_nand", -+ .id = -1, -+ .dev = { -+ .platform_data = &nand_data, -+ }, -+ .resource = nand_resources, -+ .num_resources = ARRAY_SIZE(nand_resources), -+}; -+ -+void __init at91_add_device_nand(struct at91_nand_data *data) -+{ -+ unsigned long csa; -+ -+ if (!data) -+ return; -+ -+ csa = at91_sys_read(AT91_MATRIX_EBICSA); -+ at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); -+ -+ /* set the bus interface characteristics */ -+ at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) -+ | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); -+ -+ at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) -+ | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); -+ -+ at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); -+ -+ at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); -+ -+ /* enable pin */ -+ if (data->enable_pin) -+ at91_set_gpio_output(data->enable_pin, 1); -+ -+ /* ready/busy pin */ -+ if (data->rdy_pin) -+ at91_set_gpio_input(data->rdy_pin, 1); -+ -+ /* card detect pin */ -+ if (data->det_pin) -+ at91_set_gpio_input(data->det_pin, 1); -+ -+ at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ -+ at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ -+ -+ nand_data = *data; -+ platform_device_register(&at91_nand_device); -+} -+ -+#else -+void __init at91_add_device_nand(struct at91_nand_data *data) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- -+ * TWI (i2c) -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) -+ -+static struct resource twi_resources[] = { -+ [0] = { -+ .start = AT91SAM9RL_BASE_TWI0, -+ .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9RL_ID_TWI0, -+ .end = AT91SAM9RL_ID_TWI0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device at91sam9rl_twi_device = { -+ .name = "at91_i2c", -+ .id = -1, -+ .resource = twi_resources, -+ .num_resources = ARRAY_SIZE(twi_resources), -+}; -+ -+void __init at91_add_device_i2c(void) -+{ -+ /* pins used for TWI interface */ -+ at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ -+ at91_set_multi_drive(AT91_PIN_PA23, 1); -+ -+ at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */ -+ at91_set_multi_drive(AT91_PIN_PA24, 1); -+ -+ platform_device_register(&at91sam9rl_twi_device); -+} -+#else -+void __init at91_add_device_i2c(void) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- -+ * SPI -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) -+static u64 spi_dmamask = 0xffffffffUL; -+ -+static struct resource spi_resources[] = { -+ [0] = { -+ .start = AT91SAM9RL_BASE_SPI, -+ .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9RL_ID_SPI, -+ .end = AT91SAM9RL_ID_SPI, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device at91sam9rl_spi_device = { -+ .name = "atmel_spi", -+ .id = 0, -+ .dev = { -+ .dma_mask = &spi_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .resource = spi_resources, -+ .num_resources = ARRAY_SIZE(spi_resources), -+}; -+ -+static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 }; -+ -+ -+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) -+{ -+ int i; -+ unsigned long cs_pin; -+ -+ at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */ -+ at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */ -+ at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */ -+ -+ /* Enable SPI chip-selects */ -+ for (i = 0; i < nr_devices; i++) { -+ if (devices[i].controller_data) -+ cs_pin = (unsigned long) devices[i].controller_data; -+ else -+ cs_pin = spi_standard_cs[devices[i].chip_select]; -+ -+ /* enable chip-select pin */ -+ at91_set_gpio_output(cs_pin, 1); -+ -+ /* pass chip-select pin to driver */ -+ devices[i].controller_data = (void *) cs_pin; -+ } -+ -+ spi_register_board_info(devices, nr_devices); -+ platform_device_register(&at91sam9rl_spi_device); -+} -+#else -+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- -+ * LCD Controller -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) -+static u64 lcdc_dmamask = 0xffffffffUL; -+static struct atmel_lcdfb_info lcdc_data; -+ -+static struct resource lcdc_resources[] = { -+ [0] = { -+ .start = AT91SAM9RL_LCDC_BASE, -+ .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9RL_ID_LCDC, -+ .end = AT91SAM9RL_ID_LCDC, -+ .flags = IORESOURCE_IRQ, -+ }, -+#if defined(CONFIG_FB_INTSRAM) -+ [2] = { -+ .start = AT91SAM9RL_SRAM_BASE, -+ .end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+#endif -+}; -+ -+static struct platform_device at91_lcdc_device = { -+ .name = "atmel_lcdfb", -+ .id = 0, -+ .dev = { -+ .dma_mask = &lcdc_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &lcdc_data, -+ }, -+ .resource = lcdc_resources, -+ .num_resources = ARRAY_SIZE(lcdc_resources), -+}; -+ -+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) -+{ -+ if (!data) { -+ return; -+ } -+ -+#warning "Check this" -+ at91_set_B_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ -+ at91_set_B_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ -+ at91_set_B_periph(AT91_PIN_PC7, 0); /* LCDDEN */ -+ at91_set_B_periph(AT91_PIN_PC3, 0); /* LCDCC */ -+ at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ -+ at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ -+ at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ -+ at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ -+ at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ -+ at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ -+ at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ -+ at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ -+ at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ -+ at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ -+ at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ -+ at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ -+ at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ -+ at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ -+ at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ -+ at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ -+ -+ lcdc_data = *data; -+ platform_device_register(&at91_lcdc_device); -+} -+#else -+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- -+ * LEDs -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_LEDS) -+u8 at91_leds_cpu; -+u8 at91_leds_timer; -+ -+void __init at91_init_leds(u8 cpu_led, u8 timer_led) -+{ -+ /* Enable GPIO to access the LEDs */ -+ at91_set_gpio_output(cpu_led, 1); -+ at91_set_gpio_output(timer_led, 1); -+ -+ at91_leds_cpu = cpu_led; -+ at91_leds_timer = timer_led; -+} -+#else -+void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} -+#endif -+ -+ -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- -+ * UART -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_SERIAL_ATMEL) -+static struct resource dbgu_resources[] = { -+ [0] = { -+ .start = AT91_VA_BASE_SYS + AT91_DBGU, -+ .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91_ID_SYS, -+ .end = AT91_ID_SYS, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct atmel_uart_data dbgu_data = { -+ .use_dma_tx = 0, -+ .use_dma_rx = 0, /* DBGU not capable of receive DMA */ -+ .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), -+}; -+ -+static struct platform_device at91sam9rl_dbgu_device = { -+ .name = "atmel_usart", -+ .id = 0, -+ .dev = { -+ .platform_data = &dbgu_data, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .resource = dbgu_resources, -+ .num_resources = ARRAY_SIZE(dbgu_resources), -+}; -+ -+static inline void configure_dbgu_pins(void) -+{ -+ at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ -+ at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ -+} -+ -+static struct resource uart0_resources[] = { -+ [0] = { -+ .start = AT91SAM9RL_BASE_US0, -+ .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9RL_ID_US0, -+ .end = AT91SAM9RL_ID_US0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct atmel_uart_data uart0_data = { -+ .use_dma_tx = 1, -+ .use_dma_rx = 1, -+}; -+ -+static struct platform_device at91sam9rl_uart0_device = { -+ .name = "atmel_usart", -+ .id = 1, -+ .dev = { -+ .platform_data = &uart0_data, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .resource = uart0_resources, -+ .num_resources = ARRAY_SIZE(uart0_resources), -+}; -+ -+static inline void configure_usart0_pins(void) -+{ -+ at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ -+ at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ -+ at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */ -+ at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */ -+} -+ -+static struct resource uart1_resources[] = { -+ [0] = { -+ .start = AT91SAM9RL_BASE_US1, -+ .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9RL_ID_US1, -+ .end = AT91SAM9RL_ID_US1, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct atmel_uart_data uart1_data = { -+ .use_dma_tx = 1, -+ .use_dma_rx = 1, -+}; -+ -+static struct platform_device at91sam9rl_uart1_device = { -+ .name = "atmel_usart", -+ .id = 2, -+ .dev = { -+ .platform_data = &uart1_data, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .resource = uart1_resources, -+ .num_resources = ARRAY_SIZE(uart1_resources), -+}; -+ -+static inline void configure_usart1_pins(void) -+{ -+ at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ -+ at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ -+} -+ -+static struct resource uart2_resources[] = { -+ [0] = { -+ .start = AT91SAM9RL_BASE_US2, -+ .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9RL_ID_US2, -+ .end = AT91SAM9RL_ID_US2, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct atmel_uart_data uart2_data = { -+ .use_dma_tx = 1, -+ .use_dma_rx = 1, -+}; -+ -+static struct platform_device at91sam9rl_uart2_device = { -+ .name = "atmel_usart", -+ .id = 3, -+ .dev = { -+ .platform_data = &uart2_data, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .resource = uart2_resources, -+ .num_resources = ARRAY_SIZE(uart2_resources), -+}; -+ -+static inline void configure_usart2_pins(void) -+{ -+ at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ -+ at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ -+} -+ -+static struct resource uart3_resources[] = { -+ [0] = { -+ .start = AT91SAM9RL_BASE_US3, -+ .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9RL_ID_US3, -+ .end = AT91SAM9RL_ID_US3, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct atmel_uart_data uart3_data = { -+ .use_dma_tx = 1, -+ .use_dma_rx = 1, -+}; -+ -+static struct platform_device at91sam9rl_uart3_device = { -+ .name = "atmel_usart", -+ .id = 4, -+ .dev = { -+ .platform_data = &uart3_data, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .resource = uart3_resources, -+ .num_resources = ARRAY_SIZE(uart3_resources), -+}; -+ -+static inline void configure_usart3_pins(void) -+{ -+ at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */ -+ at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */ -+} -+ -+struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ -+struct platform_device *atmel_default_console_device; /* the serial console device */ -+ -+void __init at91_init_serial(struct at91_uart_config *config) -+{ -+ int i; -+ -+ /* Fill in list of supported UARTs */ -+ for (i = 0; i < config->nr_tty; i++) { -+ switch (config->tty_map[i]) { -+ case 0: -+ configure_usart0_pins(); -+ at91_uarts[i] = &at91sam9rl_uart0_device; -+ at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart"); -+ break; -+ case 1: -+ configure_usart1_pins(); -+ at91_uarts[i] = &at91sam9rl_uart1_device; -+ at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart"); -+ break; -+ case 2: -+ configure_usart2_pins(); -+ at91_uarts[i] = &at91sam9rl_uart2_device; -+ at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart"); -+ break; -+ case 3: -+ configure_usart3_pins(); -+ at91_uarts[i] = &at91sam9rl_uart3_device; -+ at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart"); -+ break; -+ case 4: -+ configure_dbgu_pins(); -+ at91_uarts[i] = &at91sam9rl_dbgu_device; -+ at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart"); -+ break; -+ default: -+ continue; -+ } -+ at91_uarts[i]->id = i; /* update ID number to mapped ID */ -+ } -+ -+ /* Set serial console device */ -+ if (config->console_tty < ATMEL_MAX_UART) -+ atmel_default_console_device = at91_uarts[config->console_tty]; -+ if (!atmel_default_console_device) -+ printk(KERN_INFO "AT91: No default serial console defined.\n"); -+} -+ -+void __init at91_add_device_serial(void) -+{ -+ int i; -+ -+ for (i = 0; i < ATMEL_MAX_UART; i++) { -+ if (at91_uarts[i]) -+ platform_device_register(at91_uarts[i]); -+ } -+} -+#else -+void __init at91_init_serial(struct at91_uart_config *config) {} -+void __init at91_add_device_serial(void) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- */ -+ -+/* -+ * These devices are always present and don't need any board-specific -+ * setup. -+ */ -+static int __init at91_add_standard_devices(void) -+{ -+ return 0; -+} -+ -+arch_initcall(at91_add_standard_devices); -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-cam60.c linux-2.6-stable/arch/arm/mach-at91/board-cam60.c ---- linux-2.6.21/arch/arm/mach-at91/board-cam60.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/arch/arm/mach-at91/board-cam60.c Tue May 8 12:13:30 2007 -@@ -0,0 +1,148 @@ -+/* -+ * KwikByte CAM60 -+ * -+ * based on board-sam9260ek.c -+ * Copyright (C) 2005 SAN People -+ * Copyright (C) 2006 Atmel -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/types.h> -+#include <linux/init.h> -+#include <linux/mm.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+#include <linux/spi/spi.h> -+#include <linux/spi/flash.h> -+ -+#include <asm/hardware.h> -+#include <asm/setup.h> -+#include <asm/mach-types.h> -+#include <asm/irq.h> -+ -+#include <asm/mach/arch.h> -+#include <asm/mach/map.h> -+#include <asm/mach/irq.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+#include <asm/arch/at91sam926x_mc.h> -+ -+#include "generic.h" -+ -+ -+/* -+ * Serial port configuration. -+ * 0 .. 5 = USART0 .. USART5 -+ * 6 = DBGU -+ */ -+static struct at91_uart_config __initdata cam60_uart_config = { -+ .console_tty = 0, /* ttyS0 */ -+ .nr_tty = 1, -+ .tty_map = { 6, -1, -1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */ -+}; -+ -+static void __init cam60_map_io(void) -+{ -+ /* Initialize processor: 10 MHz crystal */ -+ at91sam9260_initialize(10000000); -+ -+ /* Setup the serial ports and console */ -+ at91_init_serial(&cam60_uart_config); -+} -+ -+static void __init cam60_init_irq(void) -+{ -+ at91sam9260_init_interrupts(NULL); -+} -+ -+ -+/* -+ * SPI devices. -+ */ -+#if defined(CONFIG_MTD_DATAFLASH) -+static struct mtd_partition __initdata cam60_spi_partitions[] = { -+ { -+ .name = "BOOT1", -+ .offset = 0, -+ .size = 4 * 1056, -+ }, -+ { -+ .name = "BOOT2", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 256 * 1056, -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 2222 * 1056, -+ }, -+ { -+ .name = "file system", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static struct flash_platform_data __initdata cam60_spi_flash_platform_data = { -+ .name = "spi_flash", -+ .parts = cam60_spi_partitions, -+ .nr_parts = ARRAY_SIZE(cam60_spi_partitions) -+}; -+#endif -+ -+static struct spi_board_info cam60_spi_devices[] = { -+#if defined(CONFIG_MTD_DATAFLASH) -+ { /* DataFlash chip */ -+ .modalias = "mtd_dataflash", -+ .chip_select = 0, -+ .max_speed_hz = 15 * 1000 * 1000, -+ .bus_num = 0, -+ .platform_data = &cam60_spi_flash_platform_data -+ }, -+#endif -+}; -+ -+ -+/* -+ * MACB Ethernet device -+ */ -+static struct __initdata at91_eth_data cam60_macb_data = { -+ .phy_irq_pin = AT91_PIN_PB5, -+ .is_rmii = 0, -+}; -+ -+ -+static void __init cam60_board_init(void) -+{ -+ /* Serial */ -+ at91_add_device_serial(); -+ /* SPI */ -+ at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices)); -+ /* Ethernet */ -+ at91_add_device_eth(&cam60_macb_data); -+} -+ -+MACHINE_START(CAM60, "KwikByte CAM60") -+ /* Maintainer: KwikByte */ -+ .phys_io = AT91_BASE_SYS, -+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, -+ .boot_params = AT91_SDRAM_BASE + 0x100, -+ .timer = &at91sam926x_timer, -+ .map_io = cam60_map_io, -+ .init_irq = cam60_init_irq, -+ .init_machine = cam60_board_init, -+MACHINE_END -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-chub.c linux-2.6-stable/arch/arm/mach-at91/board-chub.c ---- linux-2.6.21/arch/arm/mach-at91/board-chub.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/arch/arm/mach-at91/board-chub.c Tue May 8 12:13:30 2007 -@@ -0,0 +1,132 @@ -+/* -+ * linux/arch/arm/mach-at91/board-chub.c -+ * -+ * Copyright (C) 2005 SAN People, adapted for Promwad Chub board -+ * by Kuten Ivan -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/types.h> -+#include <linux/init.h> -+#include <linux/mm.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+ -+#include <asm/hardware.h> -+#include <asm/setup.h> -+#include <asm/mach-types.h> -+#include <asm/irq.h> -+ -+#include <asm/mach/arch.h> -+#include <asm/mach/map.h> -+#include <asm/mach/irq.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+ -+#include "generic.h" -+ -+/* -+ * Serial port configuration. -+ * 0 .. 3 = USART0 .. USART3 -+ * 4 = DBGU -+ */ -+static struct at91_uart_config __initdata chub_uart_config = { -+ .console_tty = 0, /* ttyS0 */ -+ .nr_tty = 5, -+ .tty_map = { 4, 0, 1, 2, 3 } /* ttyS0, ..., ttyS4 */ -+}; -+ -+static void __init chub_init_irq(void) -+{ -+ at91rm9200_init_interrupts(NULL); -+} -+ -+static void __init chub_map_io(void) -+{ -+ /* Initialize clocks: 18.432 MHz crystal */ -+ at91rm9200_initialize(18432000, AT91RM9200_PQFP); -+ -+ /* Setup the serial ports and console */ -+ at91_init_serial(&chub_uart_config); -+} -+ -+static struct at91_eth_data __initdata chub_eth_data = { -+ .phy_irq_pin = AT91_PIN_PB29, -+ .is_rmii = 0, -+}; -+ -+static struct mtd_partition __initdata chub_nand_partition[] = { -+ { -+ .name = "NAND Partition 1", -+ .offset = 0, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static struct mtd_partition *nand_partitions(int size, int *num_partitions) -+{ -+ *num_partitions = ARRAY_SIZE(chub_nand_partition); -+ return chub_nand_partition; -+} -+ -+static struct at91_nand_data __initdata chub_nand_data = { -+ .ale = 22, -+ .cle = 21, -+ .enable_pin = AT91_PIN_PA27, -+ .partition_info = nand_partitions, -+}; -+ -+static struct spi_board_info chub_spi_devices[] = { -+ { /* DataFlash chip */ -+ .modalias = "mtd_dataflash", -+ .chip_select = 0, -+ .max_speed_hz = 15 * 1000 * 1000, -+ }, -+}; -+ -+static void __init chub_board_init(void) -+{ -+ /* Serial */ -+ at91_add_device_serial(); -+ /* I2C */ -+ at91_add_device_i2c(); -+ /* Ethernet */ -+ at91_add_device_eth(&chub_eth_data); -+ /* SPI */ -+ at91_add_device_spi(chub_spi_devices, ARRAY_SIZE(chub_spi_devices)); -+ /* NAND Flash */ -+ at91_add_device_nand(&chub_nand_data); -+ /* Disable write protect for NAND */ -+ at91_set_gpio_output(AT91_PIN_PB7, 1); -+ /* Power enable for 3x RS-232 and 1x RS-485 */ -+ at91_set_gpio_output(AT91_PIN_PB9, 1); -+ /* Disable write protect for FRAM */ -+ at91_set_gpio_output(AT91_PIN_PA21, 1); -+ /* Disable write protect for Dataflash */ -+ at91_set_gpio_output(AT91_PIN_PA19, 1); -+} -+ -+MACHINE_START(CHUB, "Promwad Chub") -+ /* Maintainer: Ivan Kuten AT Promwad DOT com */ -+ .phys_io = AT91_BASE_SYS, -+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, -+ .boot_params = AT91_SDRAM_BASE + 0x100, -+ .timer = &at91rm9200_timer, -+ .map_io = chub_map_io, -+ .init_irq = chub_init_irq, -+ .init_machine = chub_board_init, -+MACHINE_END -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-csb337.c linux-2.6-stable/arch/arm/mach-at91/board-csb337.c ---- linux-2.6.21/arch/arm/mach-at91/board-csb337.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/board-csb337.c Tue May 8 12:13:30 2007 -@@ -24,6 +24,7 @@ - #include <linux/module.h> - #include <linux/platform_device.h> - #include <linux/spi/spi.h> -+#include <linux/interrupt.h> - #include <linux/mtd/physmap.h> - - #include <asm/hardware.h> -@@ -59,6 +60,7 @@ - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); -+ at91_set_gpio_output(AT91_PIN_PB2, 1); /* third (unused) LED */ - - /* Setup the serial ports and console */ - at91_init_serial(&csb337_uart_config); -@@ -149,6 +151,55 @@ - .num_resources = ARRAY_SIZE(csb_flash_resources), - }; - -+static struct at91_gpio_led csb337_leds[] = { -+ { -+ .name = "led0", -+ .gpio = AT91_PIN_PB0, -+ .trigger = "heartbeat", -+ }, -+ { -+ .name = "led1", -+ .gpio = AT91_PIN_PB1, -+ .trigger = "timer", -+ }, -+ { -+ .name = "led2", -+ .gpio = AT91_PIN_PB2, -+ } -+}; -+ -+#if defined(CONFIG_CSB300_WAKE_SW0) || defined(CONFIG_CSB300_WAKE_SW1) -+static irqreturn_t switch_irq_handler(int irq, void *context) -+{ -+ return IRQ_HANDLED; -+} -+ -+static inline void __init switch_irq_setup(int irq, char *name, unsigned long mode) -+{ -+ int res; -+ -+ res = request_irq(irq, switch_irq_handler, IRQF_SAMPLE_RANDOM | mode, name, NULL); -+ if (res == 0) -+ enable_irq_wake(irq); -+} -+ -+static void __init csb300_switches(void) -+{ -+#ifdef CONFIG_CSB300_WAKE_SW0 -+ at91_set_A_periph(AT91_PIN_PB29, 1); /* IRQ0 */ -+ switch_irq_setup(AT91RM9200_ID_IRQ0, "csb300_sw0", IRQF_TRIGGER_FALLING); -+#endif -+#ifdef CONFIG_CSB300_WAKE_SW1 -+ at91_set_gpio_input(AT91_PIN_PB28, 1); -+ at91_set_deglitch(AT91_PIN_PB28, 1); -+ switch_irq_setup(AT91_PIN_PB28, "csb300_sw1", IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING); -+#endif -+ /* there's also SW2 at PA21, GPIO or TIOA2 */ -+} -+#else -+static void __init csb300_switches(void) {} -+#endif -+ - static void __init csb337_board_init(void) - { - /* Serial */ -@@ -168,8 +219,12 @@ - at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices)); - /* MMC */ - at91_add_device_mmc(0, &csb337_mmc_data); -+ /* LEDS */ -+ at91_gpio_leds(csb337_leds, ARRAY_SIZE(csb337_leds)); - /* NOR flash */ - platform_device_register(&csb_flash); -+ /* Switches on CSB300 */ -+ csb300_switches(); - } - - MACHINE_START(CSB337, "Cogent CSB337") -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-dk.c linux-2.6-stable/arch/arm/mach-at91/board-dk.c ---- linux-2.6.21/arch/arm/mach-at91/board-dk.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/board-dk.c Tue May 8 14:29:12 2007 -@@ -73,6 +73,185 @@ - at91rm9200_init_interrupts(NULL); - } - -+#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE) -+#include <video/s1d13xxxfb.h> -+#include <asm/arch/ics1523.h> -+ -+/* EPSON S1D13806 FB */ -+#define AT91_FB_REG_BASE 0x30000000L -+#define AT91_FB_REG_SIZE 0x200 -+#define AT91_FB_VMEM_BASE 0x30200000L -+#define AT91_FB_VMEM_SIZE 0x140000L -+ -+static void __init dk_init_video(void) -+{ -+ /* NWAIT Signal */ -+ at91_set_A_periph(AT91_PIN_PC6, 0); -+ -+ /* Initialization of the Static Memory Controller for Chip Select 2 */ -+ at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */ -+ | AT91_SMC_WSEN | AT91_SMC_NWS_(4) /* wait states */ -+ | AT91_SMC_TDF_(1) /* float time */ -+ ); -+ -+ at91_ics1523_init(); -+} -+ -+/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz) -+ Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */ -+static const struct s1d13xxxfb_regval dk_s1dfb_initregs[] = { -+ {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */ -+ {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */ -+ {S1DREG_GPIO_CNF0, 0x00}, -+ {S1DREG_GPIO_CNF1, 0x00}, -+ {S1DREG_GPIO_CTL0, 0x08}, -+ {S1DREG_GPIO_CTL1, 0x00}, -+ {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/ -+ {S1DREG_LCD_CLK_CNF, 0x00}, -+ {S1DREG_CRT_CLK_CNF, 0x00}, -+ {S1DREG_MPLUG_CLK_CNF, 0x00}, -+ {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */ -+ {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */ -+ {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */ -+ {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */ -+ {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */ -+ {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */ -+ {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */ -+ {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */ -+ {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */ -+ {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */ -+ {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */ -+ {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, -+ {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */ -+ {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */ -+ {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */ -+ {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */ -+ {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */ -+ {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */ -+ {S1DREG_LCD_DISP_START0, 0x00}, -+ {S1DREG_LCD_DISP_START1, 0xC8}, -+ {S1DREG_LCD_DISP_START2, 0x00}, -+ {S1DREG_LCD_MEM_OFF0, 0x80}, -+ {S1DREG_LCD_MEM_OFF1, 0x02}, -+ {S1DREG_LCD_PIX_PAN, 0x00}, -+ {S1DREG_LCD_DISP_FIFO_HTC, 0x3B}, -+ {S1DREG_LCD_DISP_FIFO_LTC, 0x3C}, -+ {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */ -+ {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */ -+ {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */ -+ {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */ -+ {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, -+ {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */ -+ {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */ -+ {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */ -+ {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */ -+ {S1DREG_TV_OUT_CTL, 0x10}, -+ {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */ -+ {S1DREG_CRT_DISP_START0, 0x00}, -+ {S1DREG_CRT_DISP_START1, 0x00}, -+ {S1DREG_CRT_DISP_START2, 0x00}, -+ {S1DREG_CRT_MEM_OFF0, 0x80}, -+ {S1DREG_CRT_MEM_OFF1, 0x02}, -+ {S1DREG_CRT_PIX_PAN, 0x00}, -+ {S1DREG_CRT_DISP_FIFO_HTC, 0x3B}, -+ {S1DREG_CRT_DISP_FIFO_LTC, 0x3C}, -+ {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */ -+ {S1DREG_LCD_CUR_START, 0x01}, -+ {S1DREG_LCD_CUR_XPOS0, 0x00}, -+ {S1DREG_LCD_CUR_XPOS1, 0x00}, -+ {S1DREG_LCD_CUR_YPOS0, 0x00}, -+ {S1DREG_LCD_CUR_YPOS1, 0x00}, -+ {S1DREG_LCD_CUR_BCTL0, 0x00}, -+ {S1DREG_LCD_CUR_GCTL0, 0x00}, -+ {S1DREG_LCD_CUR_RCTL0, 0x00}, -+ {S1DREG_LCD_CUR_BCTL1, 0x1F}, -+ {S1DREG_LCD_CUR_GCTL1, 0x3F}, -+ {S1DREG_LCD_CUR_RCTL1, 0x1F}, -+ {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, -+ {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */ -+ {S1DREG_CRT_CUR_START, 0x01}, -+ {S1DREG_CRT_CUR_XPOS0, 0x00}, -+ {S1DREG_CRT_CUR_XPOS1, 0x00}, -+ {S1DREG_CRT_CUR_YPOS0, 0x00}, -+ {S1DREG_CRT_CUR_YPOS1, 0x00}, -+ {S1DREG_CRT_CUR_BCTL0, 0x00}, -+ {S1DREG_CRT_CUR_GCTL0, 0x00}, -+ {S1DREG_CRT_CUR_RCTL0, 0x00}, -+ {S1DREG_CRT_CUR_BCTL1, 0x1F}, -+ {S1DREG_CRT_CUR_GCTL1, 0x3F}, -+ {S1DREG_CRT_CUR_RCTL1, 0x1F}, -+ {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, -+ {S1DREG_BBLT_CTL0, 0x00}, -+ {S1DREG_BBLT_CTL0, 0x00}, -+ {S1DREG_BBLT_CC_EXP, 0x00}, -+ {S1DREG_BBLT_OP, 0x00}, -+ {S1DREG_BBLT_SRC_START0, 0x00}, -+ {S1DREG_BBLT_SRC_START1, 0x00}, -+ {S1DREG_BBLT_SRC_START2, 0x00}, -+ {S1DREG_BBLT_DST_START0, 0x00}, -+ {S1DREG_BBLT_DST_START1, 0x00}, -+ {S1DREG_BBLT_DST_START2, 0x00}, -+ {S1DREG_BBLT_MEM_OFF0, 0x00}, -+ {S1DREG_BBLT_MEM_OFF1, 0x00}, -+ {S1DREG_BBLT_WIDTH0, 0x00}, -+ {S1DREG_BBLT_WIDTH1, 0x00}, -+ {S1DREG_BBLT_HEIGHT0, 0x00}, -+ {S1DREG_BBLT_HEIGHT1, 0x00}, -+ {S1DREG_BBLT_BGC0, 0x00}, -+ {S1DREG_BBLT_BGC1, 0x00}, -+ {S1DREG_BBLT_FGC0, 0x00}, -+ {S1DREG_BBLT_FGC1, 0x00}, -+ {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */ -+ {S1DREG_LKUP_ADDR, 0x00}, -+ {S1DREG_PS_CNF, 0x00}, /* Power Save disable */ -+ {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */ -+ {S1DREG_CPU2MEM_WDOGT, 0x00}, -+ {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */ -+}; -+ -+static struct s1d13xxxfb_pdata dk_s1dfb_pdata = { -+ .initregs = dk_s1dfb_initregs, -+ .initregssize = ARRAY_SIZE(dk_s1dfb_initregs), -+ .platform_init_video = dk_init_video, -+}; -+ -+static u64 s1dfb_dmamask = 0xffffffffUL; -+ -+static struct resource dk_s1dfb_resource[] = { -+ [0] = { /* video mem */ -+ .name = "s1d13806 memory", -+ .start = AT91_FB_VMEM_BASE, -+ .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { /* video registers */ -+ .name = "s1d13806 registers", -+ .start = AT91_FB_REG_BASE, -+ .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device dk_s1dfb_device = { -+ .name = "s1d13806fb", -+ .id = -1, -+ .dev = { -+ .dma_mask = &s1dfb_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &dk_s1dfb_pdata, -+ }, -+ .resource = dk_s1dfb_resource, -+ .num_resources = ARRAY_SIZE(dk_s1dfb_resource), -+}; -+ -+static void __init dk_add_device_video(void) -+{ -+ platform_device_register(&dk_s1dfb_device); -+} -+#else -+static void __init dk_add_device_video(void) {} -+#endif -+ - static struct at91_eth_data __initdata dk_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -@@ -151,7 +330,7 @@ - #define DK_FLASH_SIZE 0x200000 - - static struct physmap_flash_data dk_flash_data = { -- .width = 2, -+ .width = 2, - }; - - static struct resource dk_flash_resource = { -@@ -170,6 +349,13 @@ - .num_resources = 1, - }; - -+static struct at91_gpio_led dk_leds[] = { -+ { -+ .name = "led0", -+ .gpio = AT91_PIN_PB2, -+ .trigger = "timer", -+ } -+}; - - static void __init dk_board_init(void) - { -@@ -200,8 +386,10 @@ - at91_add_device_nand(&dk_nand_data); - /* NOR Flash */ - platform_device_register(&dk_flash); -+ /* LEDs */ -+ at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds)); - /* VGA */ --// dk_add_device_video(); -+ dk_add_device_video(); - } - - MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-ek.c linux-2.6-stable/arch/arm/mach-at91/board-ek.c ---- linux-2.6.21/arch/arm/mach-at91/board-ek.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/board-ek.c Tue May 8 14:29:22 2007 -@@ -73,6 +73,187 @@ - at91rm9200_init_interrupts(NULL); - } - -+#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE) -+#include <video/s1d13xxxfb.h> -+#include <asm/arch/ics1523.h> -+ -+/* EPSON S1D13806 FB */ -+#define AT91_FB_REG_BASE 0x40000000L -+#define AT91_FB_REG_SIZE 0x200 -+#define AT91_FB_VMEM_BASE 0x40200000L -+#define AT91_FB_VMEM_SIZE 0x140000L -+ -+static void __init ek_init_video(void) -+{ -+ /* NWAIT Signal */ -+ at91_set_A_periph(AT91_PIN_PC6, 0); -+ -+ /* Initialization of the Static Memory Controller for Chip Select 3 */ -+ at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16 /* 16 bit */ -+ | AT91_SMC_WSEN | AT91_SMC_NWS_(5) /* wait states */ -+ | AT91_SMC_TDF_(1) /* float time */ -+ ); -+ -+ at91_ics1523_init(); -+} -+ -+/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz) -+ Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */ -+static const struct s1d13xxxfb_regval ek_s1dfb_initregs[] = { -+ {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */ -+ {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */ -+ {S1DREG_GPIO_CNF0, 0xFF}, // 0x00 -+ {S1DREG_GPIO_CNF1, 0x1F}, // 0x08 -+ {S1DREG_GPIO_CTL0, 0x00}, -+ {S1DREG_GPIO_CTL1, 0x00}, -+ {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/ -+ {S1DREG_LCD_CLK_CNF, 0x00}, -+ {S1DREG_CRT_CLK_CNF, 0x00}, -+ {S1DREG_MPLUG_CLK_CNF, 0x00}, -+ {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */ -+ {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */ -+ {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */ -+ {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */ -+ {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */ -+ {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */ -+ {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */ -+ {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */ -+ {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */ -+ {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */ -+ {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */ -+ {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, -+ {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */ -+ {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */ -+ {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */ -+ {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */ -+ {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */ -+ {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */ -+ {S1DREG_LCD_DISP_START0, 0x00}, -+ {S1DREG_LCD_DISP_START1, 0xC8}, -+ {S1DREG_LCD_DISP_START2, 0x00}, -+ {S1DREG_LCD_MEM_OFF0, 0x80}, -+ {S1DREG_LCD_MEM_OFF1, 0x02}, -+ {S1DREG_LCD_PIX_PAN, 0x00}, -+ {S1DREG_LCD_DISP_FIFO_HTC, 0x3B}, -+ {S1DREG_LCD_DISP_FIFO_LTC, 0x3C}, -+ {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */ -+ {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */ -+ {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */ -+ {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */ -+ {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, -+ {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */ -+ {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */ -+ {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */ -+ {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */ -+ {S1DREG_TV_OUT_CTL, 0x10}, -+ {0x005E, 0x9F}, -+ {0x005F, 0x00}, -+ {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */ -+ {S1DREG_CRT_DISP_START0, 0x00}, -+ {S1DREG_CRT_DISP_START1, 0x00}, -+ {S1DREG_CRT_DISP_START2, 0x00}, -+ {S1DREG_CRT_MEM_OFF0, 0x80}, -+ {S1DREG_CRT_MEM_OFF1, 0x02}, -+ {S1DREG_CRT_PIX_PAN, 0x00}, -+ {S1DREG_CRT_DISP_FIFO_HTC, 0x3B}, -+ {S1DREG_CRT_DISP_FIFO_LTC, 0x3C}, -+ {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */ -+ {S1DREG_LCD_CUR_START, 0x01}, -+ {S1DREG_LCD_CUR_XPOS0, 0x00}, -+ {S1DREG_LCD_CUR_XPOS1, 0x00}, -+ {S1DREG_LCD_CUR_YPOS0, 0x00}, -+ {S1DREG_LCD_CUR_YPOS1, 0x00}, -+ {S1DREG_LCD_CUR_BCTL0, 0x00}, -+ {S1DREG_LCD_CUR_GCTL0, 0x00}, -+ {S1DREG_LCD_CUR_RCTL0, 0x00}, -+ {S1DREG_LCD_CUR_BCTL1, 0x1F}, -+ {S1DREG_LCD_CUR_GCTL1, 0x3F}, -+ {S1DREG_LCD_CUR_RCTL1, 0x1F}, -+ {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, -+ {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */ -+ {S1DREG_CRT_CUR_START, 0x01}, -+ {S1DREG_CRT_CUR_XPOS0, 0x00}, -+ {S1DREG_CRT_CUR_XPOS1, 0x00}, -+ {S1DREG_CRT_CUR_YPOS0, 0x00}, -+ {S1DREG_CRT_CUR_YPOS1, 0x00}, -+ {S1DREG_CRT_CUR_BCTL0, 0x00}, -+ {S1DREG_CRT_CUR_GCTL0, 0x00}, -+ {S1DREG_CRT_CUR_RCTL0, 0x00}, -+ {S1DREG_CRT_CUR_BCTL1, 0x1F}, -+ {S1DREG_CRT_CUR_GCTL1, 0x3F}, -+ {S1DREG_CRT_CUR_RCTL1, 0x1F}, -+ {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, -+ {S1DREG_BBLT_CTL0, 0x00}, -+ {S1DREG_BBLT_CTL0, 0x00}, -+ {S1DREG_BBLT_CC_EXP, 0x00}, -+ {S1DREG_BBLT_OP, 0x00}, -+ {S1DREG_BBLT_SRC_START0, 0x00}, -+ {S1DREG_BBLT_SRC_START1, 0x00}, -+ {S1DREG_BBLT_SRC_START2, 0x00}, -+ {S1DREG_BBLT_DST_START0, 0x00}, -+ {S1DREG_BBLT_DST_START1, 0x00}, -+ {S1DREG_BBLT_DST_START2, 0x00}, -+ {S1DREG_BBLT_MEM_OFF0, 0x00}, -+ {S1DREG_BBLT_MEM_OFF1, 0x00}, -+ {S1DREG_BBLT_WIDTH0, 0x00}, -+ {S1DREG_BBLT_WIDTH1, 0x00}, -+ {S1DREG_BBLT_HEIGHT0, 0x00}, -+ {S1DREG_BBLT_HEIGHT1, 0x00}, -+ {S1DREG_BBLT_BGC0, 0x00}, -+ {S1DREG_BBLT_BGC1, 0x00}, -+ {S1DREG_BBLT_FGC0, 0x00}, -+ {S1DREG_BBLT_FGC1, 0x00}, -+ {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */ -+ {S1DREG_LKUP_ADDR, 0x00}, -+ {S1DREG_PS_CNF, 0x10}, /* Power Save disable */ -+ {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */ -+ {S1DREG_CPU2MEM_WDOGT, 0x00}, -+ {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */ -+}; -+ -+static struct s1d13xxxfb_pdata ek_s1dfb_pdata = { -+ .initregs = ek_s1dfb_initregs, -+ .initregssize = ARRAY_SIZE(ek_s1dfb_initregs), -+ .platform_init_video = ek_init_video, -+}; -+ -+static u64 s1dfb_dmamask = 0xffffffffUL; -+ -+static struct resource ek_s1dfb_resource[] = { -+ [0] = { /* video mem */ -+ .name = "s1d13806 memory", -+ .start = AT91_FB_VMEM_BASE, -+ .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { /* video registers */ -+ .name = "s1d13806 registers", -+ .start = AT91_FB_REG_BASE, -+ .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ek_s1dfb_device = { -+ .name = "s1d13806fb", -+ .id = -1, -+ .dev = { -+ .dma_mask = &s1dfb_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &ek_s1dfb_pdata, -+ }, -+ .resource = ek_s1dfb_resource, -+ .num_resources = ARRAY_SIZE(ek_s1dfb_resource), -+}; -+ -+static void __init ek_add_device_video(void) -+{ -+ platform_device_register(&ek_s1dfb_device); -+} -+#else -+static void __init ek_add_device_video(void) {} -+#endif -+ - static struct at91_eth_data __initdata ek_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -@@ -113,7 +294,7 @@ - #define EK_FLASH_SIZE 0x200000 - - static struct physmap_flash_data ek_flash_data = { -- .width = 2, -+ .width = 2, - }; - - static struct resource ek_flash_resource = { -@@ -132,6 +313,18 @@ - .num_resources = 1, - }; - -+static struct at91_gpio_led ek_leds[] = { -+ { -+ .name = "led0", -+ .gpio = AT91_PIN_PB1, -+ .trigger = "heartbeat", -+ }, -+ { -+ .name = "led1", -+ .gpio = AT91_PIN_PB2, -+ .trigger = "timer", -+ } -+}; - - static void __init ek_board_init(void) - { -@@ -158,8 +351,10 @@ - #endif - /* NOR Flash */ - platform_device_register(&ek_flash); -+ /* LEDs */ -+ at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); - /* VGA */ --// ek_add_device_video(); -+ ek_add_device_video(); - } - - MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-kb9202.c linux-2.6-stable/arch/arm/mach-at91/board-kb9202.c ---- linux-2.6.21/arch/arm/mach-at91/board-kb9202.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/board-kb9202.c Tue May 8 12:21:31 2007 -@@ -37,6 +37,8 @@ - #include <asm/arch/board.h> - #include <asm/arch/gpio.h> - -+#include <asm/arch/at91rm9200_mc.h> -+ - #include "generic.h" - - -@@ -111,6 +113,48 @@ - .partition_info = nand_partitions, - }; - -+ -+#if defined(CONFIG_FB_S1D15605) -+#warning "Rather pass reset pin via platform_data" -+static struct resource kb9202_lcd_resources[] = { -+ [0] = { -+ .start = AT91_CHIPSELECT_2, -+ .end = AT91_CHIPSELECT_2 + 0x200FF, -+ .flags = IORESOURCE_MEM -+ }, -+ [1] = { /* reset pin */ -+ .start = AT91_PIN_PC22, -+ .end = AT91_PIN_PC22, -+ .flags = IORESOURCE_MEM -+ }, -+}; -+ -+static struct platform_device kb9202_lcd_device = { -+ .name = "s1d15605fb", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(kb9202_lcd_resources), -+ .resource = kb9202_lcd_resources, -+}; -+ -+static void __init kb9202_add_device_lcd(void) -+{ -+ /* In case the boot loader did not set the chip select mode and timing */ -+ at91_sys_write(AT91_SMC_CSR(2), -+ AT91_SMC_WSEN | AT91_SMC_NWS_(18) | AT91_SMC_TDF_(1) | AT91_SMC_DBW_8 | -+ AT91_SMC_RWSETUP_(1) | AT91_SMC_RWHOLD_(1)); -+ -+ /* Backlight pin = output, off */ -+ at91_set_gpio_output(AT91_PIN_PC23, 0); -+ -+ /* Reset pin = output, in reset */ -+ at91_set_gpio_output(AT91_PIN_PC22, 0); -+ -+ platform_device_register(&kb9202_lcd_device); -+} -+#else -+static void __init kb9202_add_device_lcd(void) {} -+#endif -+ - static void __init kb9202_board_init(void) - { - /* Serial */ -@@ -129,6 +173,8 @@ - at91_add_device_spi(NULL, 0); - /* NAND */ - at91_add_device_nand(&kb9202_nand_data); -+ /* LCD */ -+ kb9202_add_device_lcd(); - } - - MACHINE_START(KB9200, "KB920x") -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-sam9260ek.c linux-2.6-stable/arch/arm/mach-at91/board-sam9260ek.c ---- linux-2.6.21/arch/arm/mach-at91/board-sam9260ek.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/board-sam9260ek.c Tue May 8 12:13:30 2007 -@@ -104,9 +104,9 @@ - }, - #endif - #endif --#if defined(CONFIG_SND_AT73C213) -+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) - { /* AT73C213 DAC */ -- .modalias = "snd_at73c213", -+ .modalias = "at73c213", - .chip_select = 0, - .max_speed_hz = 10 * 1000 * 1000, - .bus_num = 1, -@@ -118,7 +118,7 @@ - /* - * MACB Ethernet device - */ --static struct __initdata at91_eth_data ek_macb_data = { -+static struct at91_eth_data __initdata ek_macb_data = { - .phy_irq_pin = AT91_PIN_PA7, - .is_rmii = 1, - }; -@@ -188,6 +188,8 @@ - at91_add_device_eth(&ek_macb_data); - /* MMC */ - at91_add_device_mmc(0, &ek_mmc_data); -+ /* I2C */ -+ at91_add_device_i2c(); - } - - MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-sam9261ek.c linux-2.6-stable/arch/arm/mach-at91/board-sam9261ek.c ---- linux-2.6.21/arch/arm/mach-at91/board-sam9261ek.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/board-sam9261ek.c Wed May 9 12:37:19 2007 -@@ -25,7 +25,11 @@ - #include <linux/module.h> - #include <linux/platform_device.h> - #include <linux/spi/spi.h> -+#include <linux/spi/ads7846.h> - #include <linux/dm9000.h> -+#include <linux/fb.h> -+ -+#include <video/atmel_lcdc.h> - - #include <asm/hardware.h> - #include <asm/setup.h> -@@ -59,6 +63,9 @@ - /* Initialize processor: 18.432 MHz crystal */ - at91sam9261_initialize(18432000); - -+ /* Setup the LEDs */ -+ at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); -+ - /* Setup the serial ports and console */ - at91_init_serial(&ek_uart_config); - } -@@ -195,6 +202,41 @@ - }; - - /* -+ * ADS7846 Touchscreen -+ */ -+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -+ -+static int ads7843_pendown_state(void) -+{ -+ return !at91_get_gpio_value(AT91_PIN_PC2); /* Touchscreen PENIRQ */ -+} -+ -+static struct ads7846_platform_data ads_info = { -+ .model = 7843, -+ .x_min = 150, -+ .x_max = 3830, -+ .y_min = 190, -+ .y_max = 3830, -+ .vref_delay_usecs = 100, -+ .x_plate_ohms = 450, -+ .y_plate_ohms = 250, -+ .pressure_max = 15000, -+ .debounce_max = 1, -+ .debounce_rep = 0, -+ .debounce_tol = (~0), -+ .get_pendown_state = ads7843_pendown_state, -+}; -+ -+static void __init ek_add_device_ts(void) -+{ -+ at91_set_B_periph(AT91_PIN_PC2, 1); /* External IRQ0, with pullup */ -+ at91_set_gpio_input(AT91_PIN_PA11, 1); /* Touchscreen BUSY signal */ -+} -+#else -+static void __init ek_add_device_ts(void) {} -+#endif -+ -+/* - * SPI devices - */ - static struct spi_board_info ek_spi_devices[] = { -@@ -204,6 +246,17 @@ - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - }, -+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -+ { -+ .modalias = "ads7846", -+ .chip_select = 2, -+ .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */ -+ .bus_num = 0, -+ .platform_data = &ads_info, -+ .irq = AT91SAM9261_ID_IRQ0, -+ .controller_data = AT91_PIN_PA28, /* CS pin */ -+ }, -+#endif - #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) - { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */ - .modalias = "mtd_dataflash", -@@ -211,9 +264,9 @@ - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - }, --#elif defined(CONFIG_SND_AT73C213) -+#elif defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) - { /* AT73C213 DAC */ -- .modalias = "snd_at73c213", -+ .modalias = "at73c213", - .chip_select = 3, - .max_speed_hz = 10 * 1000 * 1000, - .bus_num = 0, -@@ -222,6 +275,65 @@ - }; - - -+/* -+ * LCD Controller -+ */ -+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) -+static struct fb_videomode at91_tft_vga_modes[] = { -+ { -+ .name = "TX09D50VM1CCA @ 60", -+ .refresh = 60, -+ .xres = 240, .yres = 320, -+ .pixclock = KHZ2PICOS(4965), -+ -+ .left_margin = 1, .right_margin = 33, -+ .upper_margin = 1, .lower_margin = 0, -+ .hsync_len = 5, .vsync_len = 1, -+ -+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ .vmode = FB_VMODE_NONINTERLACED, -+ }, -+}; -+ -+static struct fb_monspecs at91fb_default_monspecs = { -+ .manufacturer = "HIT", -+ .monitor = "TX09D50VM1CCA", -+ -+ .modedb = at91_tft_vga_modes, -+ .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), -+ .hfmin = 15000, -+ .hfmax = 64000, -+ .vfmin = 50, -+ .vfmax = 150, -+}; -+ -+#define AT91SAM9261_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ -+ | ATMEL_LCDC_DISTYPE_TFT \ -+ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -+ -+static void at91_lcdc_power_control(int on) -+{ -+ if (on) -+ at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ -+ else -+ at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ -+} -+ -+/* Driver datas */ -+static struct atmel_lcdfb_info __initdata ek_lcdc_data = { -+ .default_bpp = 16, -+ .default_dmacon = ATMEL_LCDC_DMAEN, -+ .default_lcdcon2 = AT91SAM9261_DEFAULT_LCDCON2, -+ .default_monspecs = &at91fb_default_monspecs, -+ .atmel_lcdfb_power_control = at91_lcdc_power_control, -+ .guard_time = 1, -+}; -+ -+#else -+static struct atmel_lcdfb_info __initdata ek_lcdc_data; -+#endif -+ -+ - static void __init ek_board_init(void) - { - /* Serial */ -@@ -241,10 +353,14 @@ - #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) - /* SPI */ - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); -+ /* Touchscreen */ -+ ek_add_device_ts(); - #else - /* MMC */ - at91_add_device_mmc(0, &ek_mmc_data); - #endif -+ /* LCD Controller */ -+ at91_add_device_lcdc(&ek_lcdc_data); - } - - MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-sam9263ek.c linux-2.6-stable/arch/arm/mach-at91/board-sam9263ek.c ---- linux-2.6.21/arch/arm/mach-at91/board-sam9263ek.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/board-sam9263ek.c Tue May 8 12:56:33 2007 -@@ -25,6 +25,10 @@ - #include <linux/module.h> - #include <linux/platform_device.h> - #include <linux/spi/spi.h> -+#include <linux/spi/ads7846.h> -+#include <linux/fb.h> -+ -+#include <video/atmel_lcdc.h> - - #include <asm/hardware.h> - #include <asm/setup.h> -@@ -86,6 +90,40 @@ - - - /* -+ * ADS7846 Touchscreen -+ */ -+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -+static int ads7843_pendown_state(void) -+{ -+ return !at91_get_gpio_value(AT91_PIN_PA15); /* Touchscreen PENIRQ */ -+} -+ -+static struct ads7846_platform_data ads_info = { -+ .model = 7843, -+ .x_min = 150, -+ .x_max = 3830, -+ .y_min = 190, -+ .y_max = 3830, -+ .vref_delay_usecs = 100, -+ .x_plate_ohms = 450, -+ .y_plate_ohms = 250, -+ .pressure_max = 15000, -+ .debounce_max = 1, -+ .debounce_rep = 0, -+ .debounce_tol = (~0), -+ .get_pendown_state = ads7843_pendown_state, -+}; -+ -+static void __init ek_add_device_ts(void) -+{ -+ at91_set_B_periph(AT91_PIN_PA15, 1); /* External IRQ1, with pullup */ -+ at91_set_gpio_input(AT91_PIN_PA31, 1); /* Touchscreen BUSY signal */ -+} -+#else -+static void __init ek_add_device_ts(void) {} -+#endif -+ -+/* - * SPI devices. - */ - static struct spi_board_info ek_spi_devices[] = { -@@ -97,6 +135,16 @@ - .bus_num = 0, - }, - #endif -+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -+ { -+ .modalias = "ads7846", -+ .chip_select = 3, -+ .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */ -+ .bus_num = 0, -+ .platform_data = &ads_info, -+ .irq = AT91SAM9263_ID_IRQ1, -+ }, -+#endif - }; - - -@@ -112,6 +160,14 @@ - - - /* -+ * MACB Ethernet device -+ */ -+static struct at91_eth_data __initdata ek_macb_data = { -+ .is_rmii = 1, -+}; -+ -+ -+/* - * NAND flash - */ - static struct mtd_partition __initdata ek_nand_partition[] = { -@@ -148,6 +204,73 @@ - }; - - -+/* -+ * LCD Controller -+ */ -+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) -+static struct fb_videomode at91_tft_vga_modes[] = { -+ { -+ .name = "TX09D50VM1CCA @ 60", -+ .refresh = 60, -+ .xres = 240, .yres = 320, -+ .pixclock = KHZ2PICOS(4965), -+ -+ .left_margin = 1, .right_margin = 33, -+ .upper_margin = 1, .lower_margin = 0, -+ .hsync_len = 5, .vsync_len = 1, -+ -+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ .vmode = FB_VMODE_NONINTERLACED, -+ }, -+}; -+ -+static struct fb_monspecs at91fb_default_monspecs = { -+ .manufacturer = "HIT", -+ .monitor = "TX09D70VM1CCA", -+ -+ .modedb = at91_tft_vga_modes, -+ .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), -+ .hfmin = 15000, -+ .hfmax = 64000, -+ .vfmin = 50, -+ .vfmax = 150, -+}; -+ -+#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ -+ | ATMEL_LCDC_DISTYPE_TFT \ -+ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -+ -+static void at91_lcdc_power_control(int on) -+{ -+ if (on) -+ at91_set_gpio_value(AT91_PIN_PD12, 0); /* power up */ -+ else -+ at91_set_gpio_value(AT91_PIN_PD12, 1); /* power down */ -+} -+ -+/* Driver datas */ -+static struct atmel_lcdfb_info __initdata ek_lcdc_data = { -+ .default_bpp = 16, -+ .default_dmacon = ATMEL_LCDC_DMAEN, -+ .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2, -+ .default_monspecs = &at91fb_default_monspecs, -+ .atmel_lcdfb_power_control = at91_lcdc_power_control, -+ .guard_time = 1, -+}; -+ -+#else -+static struct atmel_lcdfb_info __initdata ek_lcdc_data; -+#endif -+ -+ -+/* -+ * AC97 -+ */ -+static struct atmel_ac97_data ek_ac97_data = { -+ .reset_pin = AT91_PIN_PA13, -+}; -+ -+ - static void __init ek_board_init(void) - { - /* Serial */ -@@ -157,11 +280,22 @@ - /* USB Device */ - at91_add_device_udc(&ek_udc_data); - /* SPI */ -+ at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */ - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); -+ /* Touchscreen */ -+ ek_add_device_ts(); - /* MMC */ - at91_add_device_mmc(1, &ek_mmc_data); -+ /* Ethernet */ -+ at91_add_device_eth(&ek_macb_data); - /* NAND */ - at91_add_device_nand(&ek_nand_data); -+ /* I2C */ -+ at91_add_device_i2c(); -+ /* LCD Controller */ -+ at91_add_device_lcdc(&ek_lcdc_data); -+ /* AC97 */ -+ at91_add_device_ac97(&ek_ac97_data); - } - - MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK") -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-sam9rlek.c linux-2.6-stable/arch/arm/mach-at91/board-sam9rlek.c ---- linux-2.6.21/arch/arm/mach-at91/board-sam9rlek.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/arch/arm/mach-at91/board-sam9rlek.c Wed May 9 10:58:34 2007 -@@ -0,0 +1,204 @@ -+/* -+ * Copyright (C) 2005 SAN People -+ * Copyright (C) 2007 Atmel Corporation -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive for -+ * more details. -+ */ -+ -+#include <linux/types.h> -+#include <linux/init.h> -+#include <linux/mm.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+#include <linux/spi/spi.h> -+#include <linux/fb.h> -+#include <linux/clk.h> -+ -+#include <video/atmel_lcdc.h> -+ -+#include <asm/hardware.h> -+#include <asm/setup.h> -+#include <asm/mach-types.h> -+#include <asm/irq.h> -+ -+#include <asm/mach/arch.h> -+#include <asm/mach/map.h> -+#include <asm/mach/irq.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+#include <asm/arch/at91sam926x_mc.h> -+ -+#include "generic.h" -+ -+ -+/* -+ * Serial port configuration. -+ * 0 .. 3 = USART0 .. USART3 -+ * 4 = DBGU -+ */ -+static struct at91_uart_config __initdata ek_uart_config = { -+ .console_tty = 0, /* ttyS0 */ -+ .nr_tty = 2, -+ .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ -+}; -+ -+static void __init ek_map_io(void) -+{ -+ /* Initialize processor: 12.000 MHz crystal */ -+ at91sam9rl_initialize(12000000); -+ -+ /* Setup the serial ports and console */ -+ at91_init_serial(&ek_uart_config); -+} -+ -+static void __init ek_init_irq(void) -+{ -+ at91sam9rl_init_interrupts(NULL); -+} -+ -+ -+/* -+ * MCI (SD/MMC) -+ */ -+static struct at91_mmc_data __initdata ek_mmc_data = { -+ .wire4 = 1, -+ .det_pin = AT91_PIN_PA15, -+// .wp_pin = ... not connected -+// .vcc_pin = ... not connected -+}; -+ -+ -+/* -+ * NAND flash -+ */ -+static struct mtd_partition __initdata ek_nand_partition[] = { -+ { -+ .name = "Partition 1", -+ .offset = 0, -+ .size = 256 * 1024, -+ }, -+ { -+ .name = "Partition 2", -+ .offset = 256 * 1024 , -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static struct mtd_partition *nand_partitions(int size, int *num_partitions) -+{ -+ *num_partitions = ARRAY_SIZE(ek_nand_partition); -+ return ek_nand_partition; -+} -+ -+static struct at91_nand_data __initdata ek_nand_data = { -+ .ale = 21, -+ .cle = 22, -+// .det_pin = ... not connected -+ .rdy_pin = AT91_PIN_PD17, -+ .enable_pin = AT91_PIN_PB6, -+ .partition_info = nand_partitions, -+ .bus_width_16 = 0, -+}; -+ -+ -+/* -+ * SPI devices -+ */ -+static struct spi_board_info ek_spi_devices[] = { -+ { /* DataFlash chip */ -+ .modalias = "mtd_dataflash", -+ .chip_select = 0, -+ .max_speed_hz = 15 * 1000 * 1000, -+ .bus_num = 0, -+ }, -+}; -+ -+ -+/* -+ * LCD Controller -+ */ -+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) -+static struct fb_videomode at91_tft_vga_modes[] = { -+ { -+ .name = "TX09D50VM1CCA @ 60", -+ .refresh = 60, -+ .xres = 240, .yres = 320, -+ .pixclock = KHZ2PICOS(4965), -+ -+ .left_margin = 1, .right_margin = 33, -+ .upper_margin = 1, .lower_margin = 0, -+ .hsync_len = 5, .vsync_len = 1, -+ -+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ .vmode = FB_VMODE_NONINTERLACED, -+ }, -+}; -+ -+static struct fb_monspecs at91fb_default_monspecs = { -+ .manufacturer = "HIT", -+ .monitor = "TX09D50VM1CCA", -+ -+ .modedb = at91_tft_vga_modes, -+ .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), -+ .hfmin = 15000, -+ .hfmax = 64000, -+ .vfmin = 50, -+ .vfmax = 150, -+}; -+ -+#define AT91SAM9RL_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ -+ | ATMEL_LCDC_DISTYPE_TFT \ -+ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -+ -+static void at91_lcdc_power_control(int on) -+{ -+ if (on) -+ at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ -+ else -+ at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ -+} -+ -+/* Driver datas */ -+static struct atmel_lcdfb_info __initdata ek_lcdc_data = { -+ .default_bpp = 16, -+ .default_dmacon = ATMEL_LCDC_DMAEN, -+ .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2, -+ .default_monspecs = &at91fb_default_monspecs, -+ .atmel_lcdfb_power_control = at91_lcdc_power_control, -+ .guard_time = 1, -+}; -+ -+#else -+static struct atmel_lcdfb_info __initdata ek_lcdc_data; -+#endif -+ -+ -+static void __init ek_board_init(void) -+{ -+ /* Serial */ -+ at91_add_device_serial(); -+ /* I2C */ -+ at91_add_device_i2c(); -+ /* NAND */ -+ at91_add_device_nand(&ek_nand_data); -+ /* SPI */ -+ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); -+ /* MMC */ -+ at91_add_device_mmc(0, &ek_mmc_data); -+ /* LCD Controller */ -+ at91_add_device_lcdc(&ek_lcdc_data); -+} -+ -+MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") -+ /* Maintainer: Atmel */ -+ .phys_io = AT91_BASE_SYS, -+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, -+ .boot_params = AT91_SDRAM_BASE + 0x100, -+ .timer = &at91sam926x_timer, -+ .map_io = ek_map_io, -+ .init_irq = ek_init_irq, -+ .init_machine = ek_board_init, -+MACHINE_END -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/clock.c linux-2.6-stable/arch/arm/mach-at91/clock.c ---- linux-2.6.21/arch/arm/mach-at91/clock.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/clock.c Tue May 8 12:13:30 2007 -@@ -32,6 +32,7 @@ - #include <asm/arch/cpu.h> - - #include "clock.h" -+#include "generic.h" - - - /* -@@ -254,6 +255,23 @@ - - /*------------------------------------------------------------------------*/ - -+#ifdef CONFIG_PM -+ -+int clk_must_disable(struct clk *clk) -+{ -+ if (!at91_suspend_entering_slow_clock()) -+ return 0; -+ -+ while (clk->parent) -+ clk = clk->parent; -+ return clk != &clk32k; -+} -+EXPORT_SYMBOL(clk_must_disable); -+ -+#endif -+ -+/*------------------------------------------------------------------------*/ -+ - #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS - - /* -@@ -375,6 +393,7 @@ - seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); - - seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); -+#warning "Hard-coded PCK" - for (i = 0; i < 4; i++) - seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i))); - seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/generic.h linux-2.6-stable/arch/arm/mach-at91/generic.h ---- linux-2.6.21/arch/arm/mach-at91/generic.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/generic.h Wed May 9 10:20:54 2007 -@@ -13,12 +13,14 @@ - extern void __init at91sam9260_initialize(unsigned long main_clock); - extern void __init at91sam9261_initialize(unsigned long main_clock); - extern void __init at91sam9263_initialize(unsigned long main_clock); -+extern void __init at91sam9rl_initialize(unsigned long main_clock); - - /* Interrupts */ - extern void __init at91rm9200_init_interrupts(unsigned int priority[]); - extern void __init at91sam9260_init_interrupts(unsigned int priority[]); - extern void __init at91sam9261_init_interrupts(unsigned int priority[]); - extern void __init at91sam9263_init_interrupts(unsigned int priority[]); -+extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); - extern void __init at91_aic_init(unsigned int priority[]); - - /* Timer */ -@@ -34,6 +36,7 @@ - /* Power Management */ - extern void at91_irq_suspend(void); - extern void at91_irq_resume(void); -+extern int at91_suspend_entering_slow_clock(void); - - /* GPIO */ - #define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/ics1523.c linux-2.6-stable/arch/arm/mach-at91/ics1523.c ---- linux-2.6.21/arch/arm/mach-at91/ics1523.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/arch/arm/mach-at91/ics1523.c Tue May 8 12:13:30 2007 -@@ -0,0 +1,207 @@ -+/* -+ * arch/arm/mach-at91rm9200/ics1523.c -+ * -+ * Copyright (C) 2003 ATMEL Rousset -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <asm/hardware.h> -+#include <asm/io.h> -+ -+#include <linux/clk.h> -+#include <linux/delay.h> -+#include <linux/err.h> -+#include <linux/init.h> -+ -+#include <asm/arch/ics1523.h> -+#include <asm/arch/at91_twi.h> -+#include <asm/arch/gpio.h> -+ -+/* TWI Errors */ -+#define AT91_TWI_ERROR (AT91_TWI_NACK | AT91_TWI_UNRE | AT91_TWI_OVRE) -+ -+ -+static void __iomem *twi_base; -+ -+#define at91_twi_read(reg) __raw_readl(twi_base + (reg)) -+#define at91_twi_write(reg, val) __raw_writel((val), twi_base + (reg)) -+ -+ -+/* ----------------------------------------------------------------------------- -+ * Initialization of TWI CLOCK -+ * ----------------------------------------------------------------------------- */ -+ -+static void at91_ics1523_SetTwiClock(unsigned int mck_khz) -+{ -+ int sclock; -+ -+ /* Here, CKDIV = 1 and CHDIV = CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */ -+ sclock = (10*mck_khz / ICS_TRANSFER_RATE); -+ if (sclock % 10 >= 5) -+ sclock = (sclock /10) - 5; -+ else -+ sclock = (sclock /10)- 6; -+ sclock = (sclock + (4 - sclock %4)) >> 2; /* div 4 */ -+ -+ at91_twi_write(AT91_TWI_CWGR, 0x00010000 | sclock | (sclock << 8)); -+} -+ -+/* ----------------------------------------------------------------------------- -+ * Read a byte with TWI Interface from the Clock Generator ICS1523 -+ * ----------------------------------------------------------------------------- */ -+ -+static int at91_ics1523_ReadByte(unsigned char reg_address, unsigned char *data_in) -+{ -+ int Status, nb_trial; -+ -+ at91_twi_write(AT91_TWI_MMR, AT91_TWI_MREAD | AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR)); -+ at91_twi_write(AT91_TWI_IADR, reg_address); -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP); -+ -+ /* Program temporizing period (300us) */ -+ udelay(300); -+ -+ /* Wait TXcomplete ... */ -+ nb_trial = 0; -+ Status = at91_twi_read(AT91_TWI_SR); -+ while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) { -+ nb_trial++; -+ Status = at91_twi_read(AT91_TWI_SR); -+ } -+ -+ if (Status & AT91_TWI_TXCOMP) { -+ *data_in = (unsigned char) at91_twi_read(AT91_TWI_RHR); -+ return ICS1523_ACCESS_OK; -+ } -+ else -+ return ICS1523_ACCESS_ERROR; -+} -+ -+/* ----------------------------------------------------------------------------- -+ * Write a byte with TWI Interface to the Clock Generator ICS1523 -+ * ----------------------------------------------------------------------------- */ -+ -+static int at91_ics1523_WriteByte(unsigned char reg_address, unsigned char data_out) -+{ -+ int Status, nb_trial; -+ -+ at91_twi_write(AT91_TWI_MMR, AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR)); -+ at91_twi_write(AT91_TWI_IADR, reg_address); -+ at91_twi_write(AT91_TWI_THR, data_out); -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP); -+ -+ /* Program temporizing period (300us) */ -+ udelay(300); -+ -+ nb_trial = 0; -+ Status = at91_twi_read(AT91_TWI_SR); -+ while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) { -+ nb_trial++; -+ if (Status & AT91_TWI_ERROR) { -+ /* If Underrun OR NACK - Start again */ -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP); -+ -+ /* Program temporizing period (300us) */ -+ udelay(300); -+ } -+ Status = at91_twi_read(AT91_TWI_SR); -+ }; -+ -+ if (Status & AT91_TWI_TXCOMP) -+ return ICS1523_ACCESS_OK; -+ else -+ return ICS1523_ACCESS_ERROR; -+} -+ -+/* ----------------------------------------------------------------------------- -+ * Initialization of the Clock Generator ICS1523 -+ * ----------------------------------------------------------------------------- */ -+ -+int at91_ics1523_init(void) -+{ -+ int nb_trial; -+ int ack = ICS1523_ACCESS_OK; -+ unsigned int status = 0xffffffff; -+ struct clk *twi_clk; -+ -+ /* Map in TWI peripheral */ -+ twi_base = ioremap(AT91RM9200_BASE_TWI, SZ_16K); -+ if (!twi_base) -+ return -ENOMEM; -+ -+ /* pins used for TWI interface */ -+ at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */ -+ at91_set_multi_drive(AT91_PIN_PA25, 1); -+ at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */ -+ at91_set_multi_drive(AT91_PIN_PA26, 1); -+ -+ /* Enable the TWI clock */ -+ twi_clk = clk_get(NULL, "twi_clk"); -+ if (IS_ERR(twi_clk)) -+ return ICS1523_ACCESS_ERROR; -+ clk_enable(twi_clk); -+ -+ /* Disable interrupts */ -+ at91_twi_write(AT91_TWI_IDR, -1); -+ -+ /* Reset peripheral */ -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST); -+ -+ /* Set Master mode */ -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN); -+ -+ /* Set TWI Clock Waveform Generator Register */ -+ at91_ics1523_SetTwiClock(60000); /* MCK in KHz = 60000 KHz */ -+ -+ /* ICS1523 Initialisation */ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) 0); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OE, (unsigned char) (ICS_OEF | ICS_OET2 | ICS_OETCK)); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OD, (unsigned char) (ICS_INSEL | 0x7F)); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0); -+ -+ nb_trial = 0; -+ do { -+ nb_trial++; -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) (ICS_ENDLS | ICS_ENPLS | ICS_PDEN /*| ICS_FUNCSEL*/)); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_LCR, (unsigned char) (ICS_PSD | ICS_PFD)); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD0, (unsigned char) 0x39) ; /* 0x7A */ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD1, (unsigned char) 0x00); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_PLLR)); -+ -+ /* Program 1ms temporizing period */ -+ mdelay(1); -+ -+ at91_ics1523_ReadByte ((unsigned char) ICS_SR, (char *)&status); -+ } while (!((unsigned int) status & (unsigned int) ICS_PLLLOCK) && (nb_trial < 10)); -+ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAC, (unsigned char) 0x03) ; /* 0x01 */ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_DPAR)); -+ -+ /* Program 1ms temporizing period */ -+ mdelay(1); -+ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0x00); -+ -+ /* Program 1ms temporizing period */ -+ mdelay(1); -+ -+ /* All done - cleanup */ -+ iounmap(twi_base); -+ clk_disable(twi_clk); -+ clk_put(twi_clk); -+ -+ return ack; -+} -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/pm.c linux-2.6-stable/arch/arm/mach-at91/pm.c ---- linux-2.6.21/arch/arm/mach-at91/pm.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mach-at91/pm.c Tue May 8 12:13:31 2007 -@@ -63,6 +63,7 @@ - * Verify that all the clocks are correct before entering - * slow-clock mode. - */ -+#warning "SAM9260 only has 3 programmable clocks." - static int at91_pm_verify_clocks(void) - { - unsigned long scsr; -@@ -104,20 +105,15 @@ - } - - /* -- * Call this from platform driver suspend() to see how deeply to suspend. -+ * This is called from clk_must_disable(), to see how deeply to suspend. - * For example, some controllers (like OHCI) need one of the PLL clocks - * in order to act as a wakeup source, and those are not available when - * going into slow clock mode. -- * -- * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have -- * the very same problem (but not using at91 main_clk), and it'd be better -- * to add one generic API rather than lots of platform-specific ones. - */ - int at91_suspend_entering_slow_clock(void) - { - return (target_state == PM_SUSPEND_MEM); - } --EXPORT_SYMBOL(at91_suspend_entering_slow_clock); - - - static void (*slow_clock)(void); -@@ -207,16 +203,23 @@ - .enter = at91_pm_enter, - }; - -+#ifdef CONFIG_AT91_SLOW_CLOCK -+extern void at91rm9200_slow_clock(void); -+extern u32 at91rm9200_slow_clock_sz; -+#endif -+ - static int __init at91_pm_init(void) - { -- printk("AT91: Power Management\n"); -- --#ifdef CONFIG_AT91_PM_SLOW_CLOCK -- /* REVISIT allocations of SRAM should be dynamically managed. -+#ifdef CONFIG_AT91_SLOW_CLOCK -+ /* -+ * REVISIT allocations of SRAM should be dynamically managed. - * FIQ handlers and other components will want SRAM/TCM too... - */ -- slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K)); -+ slow_clock = (void *) (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE + (3 * SZ_4K)); - memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz); -+ printk("AT91: Power Management (with slow clock mode)\n"); -+#else -+ printk("AT91: Power Management\n"); - #endif - - /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */ -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/pm_slowclock.S linux-2.6-stable/arch/arm/mach-at91/pm_slowclock.S ---- linux-2.6.21/arch/arm/mach-at91/pm_slowclock.S Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/arch/arm/mach-at91/pm_slowclock.S Tue May 8 12:13:31 2007 -@@ -0,0 +1,172 @@ -+/* -+ * arch/arm/mach-at91/pm_slow_clock.S -+ * -+ * Copyright (C) 2006 Savin Zlobec -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include <linux/linkage.h> -+#include <asm/hardware.h> -+#include <asm/arch/at91_pmc.h> -+#include <asm/arch/at91rm9200_mc.h> -+ -+#define MCKRDY_TIMEOUT 1000 -+#define MOSCRDY_TIMEOUT 1000 -+#define PLLALOCK_TIMEOUT 1000 -+ -+ .macro wait_mckrdy -+ mov r2, #MCKRDY_TIMEOUT -+1: sub r2, r2, #1 -+ cmp r2, #0 -+ beq 2f -+ ldr r3, [r1, #AT91_PMC_SR] -+ tst r3, #AT91_PMC_MCKRDY -+ beq 1b -+2: -+ .endm -+ -+ .macro wait_moscrdy -+ mov r2, #MOSCRDY_TIMEOUT -+1: sub r2, r2, #1 -+ cmp r2, #0 -+ beq 2f -+ ldr r3, [r1, #AT91_PMC_SR] -+ tst r3, #AT91_PMC_MOSCS -+ beq 1b -+2: -+ .endm -+ -+ .macro wait_pllalock -+ mov r2, #PLLALOCK_TIMEOUT -+1: sub r2, r2, #1 -+ cmp r2, #0 -+ beq 2f -+ ldr r3, [r1, #AT91_PMC_SR] -+ tst r3, #AT91_PMC_LOCKA -+ beq 1b -+2: -+ .endm -+ -+ .macro wait_plladis -+ mov r2, #PLLALOCK_TIMEOUT -+1: sub r2, r2, #1 -+ cmp r2, #0 -+ beq 2f -+ ldr r3, [r1, #AT91_PMC_SR] -+ tst r3, #AT91_PMC_LOCKA -+ bne 1b -+2: -+ .endm -+ -+ .text -+ -+ENTRY(at91rm9200_slow_clock) -+ -+ ldr r1, .at91_va_base_sys -+ -+ /* Put SDRAM in self refresh mode */ -+ -+ b 1f -+ .align 5 -+1: mcr p15, 0, r0, c7, c10, 4 -+ mov r2, #1 -+ str r2, [r1, #AT91_SDRAMC_SRR] -+ -+ /* Save Master clock setting */ -+ -+ ldr r2, [r1, #AT91_PMC_MCKR] -+ str r2, .saved_mckr -+ -+ /* -+ * Set the Master clock source to slow clock -+ * -+ * First set the CSS field, wait for MCKRDY -+ * and than set the PRES and MDIV fields. -+ * -+ * See eratta #2[78] for details. -+ */ -+ -+ bic r2, r2, #3 -+ str r2, [r1, #AT91_PMC_MCKR] -+ -+ wait_mckrdy -+ -+ mov r2, #0 -+ str r2, [r1, #AT91_PMC_MCKR] -+ -+ /* Save PLLA setting and disable it */ -+ -+ ldr r2, [r1, #AT91_CKGR_PLLAR] -+ str r2, .saved_pllar -+ -+ mov r2, #0 -+ str r2, [r1, #AT91_CKGR_PLLAR] -+ -+ wait_plladis -+ -+ /* Turn off the main oscillator */ -+ -+ ldr r2, [r1, #AT91_CKGR_MOR] -+ bic r2, r2, #AT91_PMC_MOSCEN -+ str r2, [r1, #AT91_CKGR_MOR] -+ -+ /* Wait for interrupt */ -+ -+ mcr p15, 0, r0, c7, c0, 4 -+ -+ /* Turn on the main oscillator */ -+ -+ ldr r2, [r1, #AT91_CKGR_MOR] -+ orr r2, r2, #AT91_PMC_MOSCEN -+ str r2, [r1, #AT91_CKGR_MOR] -+ -+ wait_moscrdy -+ -+ /* Restore PLLA setting */ -+ -+ ldr r2, .saved_pllar -+ str r2, [r1, #AT91_CKGR_PLLAR] -+ -+ wait_pllalock -+ -+ /* -+ * Restore master clock setting -+ * -+ * First set PRES if it was not 0, -+ * than set CSS and MDIV fields. -+ * After every change wait for -+ * MCKRDY. -+ * -+ * See eratta #2[78] for details. -+ */ -+ -+ ldr r2, .saved_mckr -+ tst r2, #0x1C -+ beq 2f -+ and r2, r2, #0x1C -+ str r2, [r1, #AT91_PMC_MCKR] -+ -+ wait_mckrdy -+ -+2: ldr r2, .saved_mckr -+ str r2, [r1, #AT91_PMC_MCKR] -+ -+ wait_mckrdy -+ -+ mov pc, lr -+ -+.saved_mckr: -+ .word 0 -+ -+.saved_pllar: -+ .word 0 -+ -+.at91_va_base_sys: -+ .word AT91_VA_BASE_SYS -+ -+ENTRY(at91rm9200_slow_clock_sz) -+ .word .-at91rm9200_slow_clock -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/tclib.c linux-2.6-stable/arch/arm/mach-at91/tclib.c ---- linux-2.6.21/arch/arm/mach-at91/tclib.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/arch/arm/mach-at91/tclib.c Tue May 8 12:13:31 2007 -@@ -0,0 +1,17 @@ -+#include <linux/clk.h> -+#include <linux/kernel.h> -+#include <linux/module.h> -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock *blocks; -+static int nblocks; -+ -+/* -+ * Called from the processor-specific init to register the TC Blocks. -+ */ -+void __init atmel_tc_init(struct atmel_tcblock *tcblocks, int n) -+{ -+ blocks = tcblocks; -+ nblocks = n; -+} -diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/tclib.h linux-2.6-stable/arch/arm/mach-at91/tclib.h ---- linux-2.6.21/arch/arm/mach-at91/tclib.h Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/arch/arm/mach-at91/tclib.h Tue May 8 12:13:31 2007 -@@ -0,0 +1,11 @@ -+ -+#define TC_PER_TCB 3 -+ -+struct atmel_tcblock { -+ u32 physaddr; -+ void __iomem *ioaddr; -+ struct clk *clk[TC_PER_TCB]; -+ int irq[TC_PER_TCB]; -+}; -+ -+extern void __init atmel_tc_init(struct atmel_tcblock *tcblocks, int n); -diff -urN -x CVS linux-2.6.21/arch/arm/mm/Kconfig linux-2.6-stable/arch/arm/mm/Kconfig ---- linux-2.6.21/arch/arm/mm/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/mm/Kconfig Wed May 9 10:20:54 2007 -@@ -171,8 +171,8 @@ - # ARM926T - config CPU_ARM926T - bool "Support ARM926T processor" -- depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX -- default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX -+ depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX -+ default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX - select CPU_32v5 - select CPU_ABRT_EV5TJ - select CPU_CACHE_VIVT -diff -urN -x CVS linux-2.6.21/arch/arm/tools/mach-types linux-2.6-stable/arch/arm/tools/mach-types ---- linux-2.6.21/arch/arm/tools/mach-types Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/arch/arm/tools/mach-types Tue May 8 12:13:31 2007 -@@ -1335,3 +1335,32 @@ - comtech_router MACH_COMTECH_ROUTER COMTECH_ROUTER 1327 - sbc2410x MACH_SBC2410X SBC2410X 1328 - at4x0bd MACH_AT4X0BD AT4X0BD 1329 -+cbifr MACH_CBIFR CBIFR 1330 -+arcom_quantum MACH_ARCOM_QUANTUM ARCOM_QUANTUM 1331 -+matrix520 MACH_MATRIX520 MATRIX520 1332 -+matrix510 MACH_MATRIX510 MATRIX510 1333 -+matrix500 MACH_MATRIX500 MATRIX500 1334 -+m501 MACH_M501 M501 1335 -+aaeon1270 MACH_AAEON1270 AAEON1270 1336 -+matrix500ev MACH_MATRIX500EV MATRIX500EV 1337 -+pac500 MACH_PAC500 PAC500 1338 -+pnx8181 MACH_PNX8181 PNX8181 1339 -+colibri320 MACH_COLIBRI320 COLIBRI320 1340 -+aztoolbb MACH_AZTOOLBB AZTOOLBB 1341 -+aztoolg2 MACH_AZTOOLG2 AZTOOLG2 1342 -+dvlhost MACH_DVLHOST DVLHOST 1343 -+zir9200 MACH_ZIR9200 ZIR9200 1344 -+zir9260 MACH_ZIR9260 ZIR9260 1345 -+cocopah MACH_COCOPAH COCOPAH 1346 -+nds MACH_NDS NDS 1347 -+rosencrantz MACH_ROSENCRANTZ ROSENCRANTZ 1348 -+fttx_odsc MACH_FTTX_ODSC FTTX_ODSC 1349 -+classe_r6904 MACH_CLASSE_R6904 CLASSE_R6904 1350 -+cam60 MACH_CAM60 CAM60 1351 -+mxc30031ads MACH_MXC30031ADS MXC30031ADS 1352 -+datacall MACH_DATACALL DATACALL 1353 -+at91eb01 MACH_AT91EB01 AT91EB01 1354 -+rty MACH_RTY RTY 1355 -+dwl2100 MACH_DWL2100 DWL2100 1356 -+vinsi MACH_VINSI VINSI 1357 -+db88f5281 MACH_DB88F5281 DB88F5281 1358 -diff -urN -x CVS linux-2.6.21/drivers/char/Kconfig linux-2.6-stable/drivers/char/Kconfig ---- linux-2.6.21/drivers/char/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/char/Kconfig Tue May 8 14:31:24 2007 -@@ -1071,5 +1071,21 @@ - /sys/devices/platform/telco_clock, with a number of files for - controlling the behavior of this hardware. - -+config AT91_SPI -+ bool "SPI driver (legacy) for AT91RM9200 processors" -+ depends on ARCH_AT91RM9200 -+ default y -+ help -+ The SPI driver gives access to this serial bus on the AT91RM9200 -+ processor. -+ -+config AT91_SPIDEV -+ bool "SPI device interface (legacy) for AT91RM9200 processors" -+ depends on ARCH_AT91RM9200 && AT91_SPI -+ default n -+ help -+ The SPI driver gives user mode access to this serial -+ bus on the AT91RM9200 processor. -+ - endmenu - -diff -urN -x CVS linux-2.6.21/drivers/char/Makefile linux-2.6-stable/drivers/char/Makefile ---- linux-2.6.21/drivers/char/Makefile Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/char/Makefile Tue May 8 14:31:24 2007 -@@ -93,6 +93,8 @@ - obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o - obj-$(CONFIG_TANBAC_TB0219) += tb0219.o - obj-$(CONFIG_TELCLOCK) += tlclk.o -+obj-$(CONFIG_AT91_SPI) += at91_spi.o -+obj-$(CONFIG_AT91_SPIDEV) += at91_spidev.o - - obj-$(CONFIG_WATCHDOG) += watchdog/ - obj-$(CONFIG_MWAVE) += mwave/ -diff -urN -x CVS linux-2.6.21/drivers/char/at91_spi.c linux-2.6-stable/drivers/char/at91_spi.c ---- linux-2.6.21/drivers/char/at91_spi.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/drivers/char/at91_spi.c Tue May 8 14:31:24 2007 -@@ -0,0 +1,336 @@ -+/* -+ * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 (Thunder) -+ * -+ * Copyright (C) SAN People (Pty) Ltd -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include <linux/init.h> -+#include <linux/dma-mapping.h> -+#include <linux/module.h> -+#include <linux/sched.h> -+#include <linux/completion.h> -+#include <linux/interrupt.h> -+#include <linux/clk.h> -+#include <linux/platform_device.h> -+#include <linux/atmel_pdc.h> -+#include <asm/io.h> -+#include <asm/semaphore.h> -+ -+#include <asm/arch/at91_spi.h> -+#include <asm/arch/board.h> -+#include <asm/arch/spi.h> -+ -+#undef DEBUG_SPI -+ -+static struct spi_local spi_dev[NR_SPI_DEVICES]; /* state of the SPI devices */ -+static int spi_enabled = 0; -+static struct semaphore spi_lock; /* protect access to SPI bus */ -+static int current_device = -1; /* currently selected SPI device */ -+static struct clk *spi_clk; /* SPI clock */ -+static void __iomem *spi_base; /* SPI peripheral base-address */ -+ -+DECLARE_COMPLETION(transfer_complete); -+ -+ -+#define at91_spi_read(reg) __raw_readl(spi_base + (reg)) -+#define at91_spi_write(reg, val) __raw_writel((val), spi_base + (reg)) -+ -+ -+/* ......................................................................... */ -+ -+/* -+ * Access and enable the SPI bus. -+ * This MUST be called before any transfers are performed. -+ */ -+void spi_access_bus(short device) -+{ -+ /* Ensure that requested device is valid */ -+ if ((device < 0) || (device >= NR_SPI_DEVICES)) -+ panic("at91_spi: spi_access_bus called with invalid device"); -+ -+ if (spi_enabled == 0) { -+ clk_enable(spi_clk); /* Enable Peripheral clock */ -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */ -+#ifdef DEBUG_SPI -+ printk("SPI on\n"); -+#endif -+ } -+ spi_enabled++; -+ -+ /* Lock the SPI bus */ -+ down(&spi_lock); -+ current_device = device; -+ -+ /* Configure SPI bus for device */ -+ at91_spi_write(AT91_SPI_MR, AT91_SPI_MSTR | AT91_SPI_MODFDIS | (spi_dev[device].pcs << 16)); -+} -+ -+/* -+ * Relinquish control of the SPI bus. -+ */ -+void spi_release_bus(short device) -+{ -+ if (device != current_device) -+ panic("at91_spi: spi_release called with invalid device"); -+ -+ /* Release the SPI bus */ -+ current_device = -1; -+ up(&spi_lock); -+ -+ spi_enabled--; -+ if (spi_enabled == 0) { -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */ -+ clk_disable(spi_clk); /* Disable Peripheral clock */ -+#ifdef DEBUG_SPI -+ printk("SPI off\n"); -+#endif -+ } -+} -+ -+/* -+ * Perform a data transfer over the SPI bus -+ */ -+int spi_transfer(struct spi_transfer_list* list) -+{ -+ struct spi_local *device = (struct spi_local *) &spi_dev[current_device]; -+ int tx_size; -+ -+ if (!list) -+ panic("at91_spi: spi_transfer called with NULL transfer list"); -+ if (current_device == -1) -+ panic("at91_spi: spi_transfer called without acquiring bus"); -+ -+#ifdef DEBUG_SPI -+ printk("SPI transfer start [%i]\n", list->nr_transfers); -+#endif -+ -+ /* If we are in 16-bit mode, we need to modify what we pass to the PDC */ -+ tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1; -+ -+ /* Store transfer list */ -+ device->xfers = list; -+ list->curr = 0; -+ -+ /* Assume there must be at least one transfer */ -+ device->tx = dma_map_single(NULL, list->tx[0], list->txlen[0], DMA_TO_DEVICE); -+ device->rx = dma_map_single(NULL, list->rx[0], list->rxlen[0], DMA_FROM_DEVICE); -+ -+ /* Program PDC registers */ -+ at91_spi_write(ATMEL_PDC_TPR, device->tx); -+ at91_spi_write(ATMEL_PDC_RPR, device->rx); -+ at91_spi_write(ATMEL_PDC_TCR, list->txlen[0] / tx_size); -+ at91_spi_write(ATMEL_PDC_RCR, list->rxlen[0] / tx_size); -+ -+ /* Is there a second transfer? */ -+ if (list->nr_transfers > 1) { -+ device->txnext = dma_map_single(NULL, list->tx[1], list->txlen[1], DMA_TO_DEVICE); -+ device->rxnext = dma_map_single(NULL, list->rx[1], list->rxlen[1], DMA_FROM_DEVICE); -+ -+ /* Program Next PDC registers */ -+ at91_spi_write(ATMEL_PDC_TNPR, device->txnext); -+ at91_spi_write(ATMEL_PDC_RNPR, device->rxnext); -+ at91_spi_write(ATMEL_PDC_TNCR, list->txlen[1] / tx_size); -+ at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[1] / tx_size); -+ } -+ else { -+ device->txnext = 0; -+ device->rxnext = 0; -+ at91_spi_write(ATMEL_PDC_TNCR, 0); -+ at91_spi_write(ATMEL_PDC_RNCR, 0); -+ } -+ -+ // TODO: If we are doing consecutive transfers (at high speed, or -+ // small buffers), then it might be worth modifying the 'Delay between -+ // Consecutive Transfers' in the CSR registers. -+ // This is an issue if we cannot chain the next buffer fast enough -+ // in the interrupt handler. -+ -+ /* Enable transmitter and receiver */ -+ at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN | ATMEL_PDC_TXTEN); -+ -+ at91_spi_write(AT91_SPI_IER, AT91_SPI_ENDRX); /* enable buffer complete interrupt */ -+ wait_for_completion(&transfer_complete); -+ -+#ifdef DEBUG_SPI -+ printk("SPI transfer end\n"); -+#endif -+ -+ return 0; -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Handle interrupts from the SPI controller. -+ */ -+static irqreturn_t at91spi_interrupt(int irq, void *dev_id) -+{ -+ unsigned int status; -+ struct spi_local *device = (struct spi_local *) &spi_dev[current_device]; -+ struct spi_transfer_list *list = device->xfers; -+ -+#ifdef DEBUG_SPI -+ printk("SPI interrupt %i\n", current_device); -+#endif -+ -+ if (!list) -+ panic("at91_spi: spi_interrupt with a NULL transfer list"); -+ -+ status = at91_spi_read(AT91_SPI_SR) & at91_spi_read(AT91_SPI_IMR); /* read status */ -+ -+ dma_unmap_single(NULL, device->tx, list->txlen[list->curr], DMA_TO_DEVICE); -+ dma_unmap_single(NULL, device->rx, list->rxlen[list->curr], DMA_FROM_DEVICE); -+ -+ device->tx = device->txnext; /* move next transfer to current transfer */ -+ device->rx = device->rxnext; -+ -+ list->curr = list->curr + 1; -+ if (list->curr == list->nr_transfers) { /* all transfers complete */ -+ at91_spi_write(AT91_SPI_IDR, AT91_SPI_ENDRX); /* disable interrupt */ -+ -+ /* Disable transmitter and receiver */ -+ at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); -+ -+ device->xfers = NULL; -+ complete(&transfer_complete); -+ } -+ else if (list->curr+1 == list->nr_transfers) { /* no more next transfers */ -+ device->txnext = 0; -+ device->rxnext = 0; -+ at91_spi_write(ATMEL_PDC_TNCR, 0); -+ at91_spi_write(ATMEL_PDC_RNCR, 0); -+ } -+ else { -+ int i = (list->curr)+1; -+ -+ /* If we are in 16-bit mode, we need to modify what we pass to the PDC */ -+ int tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1; -+ -+ device->txnext = dma_map_single(NULL, list->tx[i], list->txlen[i], DMA_TO_DEVICE); -+ device->rxnext = dma_map_single(NULL, list->rx[i], list->rxlen[i], DMA_FROM_DEVICE); -+ at91_spi_write(ATMEL_PDC_TNPR, device->txnext); -+ at91_spi_write(ATMEL_PDC_RNPR, device->rxnext); -+ at91_spi_write(ATMEL_PDC_TNCR, list->txlen[i] / tx_size); -+ at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[i] / tx_size); -+ } -+ return IRQ_HANDLED; -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Initialize the SPI controller -+ */ -+static int __init at91spi_probe(struct platform_device *pdev) -+{ -+ int i; -+ unsigned long scbr; -+ struct resource *res; -+ -+ init_MUTEX(&spi_lock); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -ENXIO; -+ -+ if (!request_mem_region(res->start, res->end - res->start + 1, "at91_spi")) -+ return -EBUSY; -+ -+ spi_base = ioremap(res->start, res->end - res->start + 1); -+ if (!spi_base) { -+ release_mem_region(res->start, res->end - res->start + 1); -+ return -ENOMEM; -+ } -+ -+ spi_clk = clk_get(NULL, "spi_clk"); -+ if (IS_ERR(spi_clk)) { -+ printk(KERN_ERR "at91_spi: no clock defined\n"); -+ iounmap(spi_base); -+ release_mem_region(res->start, res->end - res->start + 1); -+ return -ENODEV; -+ } -+ -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SWRST); /* software reset of SPI controller */ -+ -+ /* -+ * Calculate the correct SPI baud-rate divisor. -+ */ -+ scbr = clk_get_rate(spi_clk) / (2 * DEFAULT_SPI_CLK); -+ scbr = scbr + 1; /* round up */ -+ -+ printk(KERN_INFO "at91_spi: Baud rate set to %ld\n", clk_get_rate(spi_clk) / (2 * scbr)); -+ -+ /* Set Chip Select registers to good defaults */ -+ for (i = 0; i < 4; i++) { -+ at91_spi_write(AT91_SPI_CSR(i), AT91_SPI_CPOL | AT91_SPI_BITS_8 | (16 << 16) | (scbr << 8)); -+ } -+ -+ at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); -+ -+ memset(&spi_dev, 0, sizeof(spi_dev)); -+ spi_dev[0].pcs = 0xE; -+ spi_dev[1].pcs = 0xD; -+ spi_dev[2].pcs = 0xB; -+ spi_dev[3].pcs = 0x7; -+ -+ if (request_irq(AT91RM9200_ID_SPI, at91spi_interrupt, 0, "spi", NULL)) { -+ clk_put(spi_clk); -+ iounmap(spi_base); -+ release_mem_region(res->start, res->end - res->start + 1); -+ return -EBUSY; -+ } -+ -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */ -+ -+ return 0; -+} -+ -+static int __devexit at91spi_remove(struct platform_device *pdev) -+{ -+ struct resource *res; -+ -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */ -+ clk_put(spi_clk); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ iounmap(spi_base); -+ release_mem_region(res->start, res->end - res->start + 1); -+ -+ free_irq(AT91RM9200_ID_SPI, 0); -+ return 0; -+} -+ -+static struct platform_driver at91spi_driver = { -+ .probe = at91spi_probe, -+ .remove = __devexit_p(at91spi_remove), -+ .driver = { -+ .name = "at91_spi", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init at91spi_init(void) -+{ -+ return platform_driver_register(&at91spi_driver); -+} -+ -+static void __exit at91spi_exit(void) -+{ -+ platform_driver_unregister(&at91spi_driver); -+} -+ -+EXPORT_SYMBOL(spi_access_bus); -+EXPORT_SYMBOL(spi_release_bus); -+EXPORT_SYMBOL(spi_transfer); -+ -+module_init(at91spi_init); -+module_exit(at91spi_exit); -+ -+MODULE_LICENSE("GPL") -+MODULE_AUTHOR("Andrew Victor") -+MODULE_DESCRIPTION("SPI driver for Atmel AT91RM9200") -diff -urN -x CVS linux-2.6.21/drivers/char/at91_spidev.c linux-2.6-stable/drivers/char/at91_spidev.c ---- linux-2.6.21/drivers/char/at91_spidev.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/drivers/char/at91_spidev.c Tue May 8 14:31:24 2007 -@@ -0,0 +1,236 @@ -+/* -+ * User-space interface to the SPI bus on Atmel AT91RM9200 -+ * -+ * Copyright (C) 2003 SAN People (Pty) Ltd -+ * -+ * Based on SPI driver by Rick Bronson -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/slab.h> -+#include <linux/highmem.h> -+#include <linux/pagemap.h> -+#include <asm/arch/spi.h> -+ -+#ifdef CONFIG_DEVFS_FS -+#include <linux/devfs_fs_kernel.h> -+#endif -+ -+ -+#undef DEBUG_SPIDEV -+ -+/* ......................................................................... */ -+ -+/* -+ * Read or Write to SPI bus. -+ */ -+static ssize_t spidev_rd_wr(struct file *file, char *buf, size_t count, loff_t *offset) -+{ -+ unsigned int spi_device = (unsigned int) file->private_data; -+ -+ struct mm_struct * mm; -+ struct page ** maplist; -+ struct spi_transfer_list* list; -+ int pgcount; -+ -+ unsigned int ofs, pagelen; -+ int res, i, err; -+ -+ if (!count) { -+ return 0; -+ } -+ -+ list = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL); -+ if (!list) { -+ return -ENOMEM; -+ } -+ -+ mm = current->mm; -+ -+ pgcount = ((unsigned long)buf+count+PAGE_SIZE-1)/PAGE_SIZE - (unsigned long)buf/PAGE_SIZE; -+ -+ if (pgcount >= MAX_SPI_TRANSFERS) { -+ kfree(list); -+ return -EFBIG; -+ } -+ -+ maplist = kmalloc (pgcount * sizeof (struct page *), GFP_KERNEL); -+ -+ if (!maplist) { -+ kfree(list); -+ return -ENOMEM; -+ } -+ flush_cache_all(); -+ down_read(&mm->mmap_sem); -+ err= get_user_pages(current, mm, (unsigned long)buf, pgcount, 1, 0, maplist, NULL); -+ up_read(&mm->mmap_sem); -+ -+ if (err < 0) { -+ kfree(list); -+ kfree(maplist); -+ return err; -+ } -+ pgcount = err; -+ -+#ifdef DEBUG_SPIDEV -+ printk("spidev_rd_rw: %i %i\n", count, pgcount); -+#endif -+ -+ /* Set default return value = transfer length */ -+ res = count; -+ -+ /* -+ * At this point, the virtual area buf[0] .. buf[count-1] will have -+ * corresponding pages mapped in the physical memory and locked until -+ * we unmap the kiobuf. The pages cannot be swapped out or moved -+ * around. -+ */ -+ ofs = (unsigned long) buf & (PAGE_SIZE -1); -+ pagelen = PAGE_SIZE - ofs; -+ if (count < pagelen) -+ pagelen = count; -+ -+ for (i = 0; i < pgcount; i++) { -+ flush_dcache_page(maplist[i]); -+ -+ list->tx[i] = list->rx[i] = page_address(maplist[i]) + ofs; -+ list->txlen[i] = list->rxlen[i] = pagelen; -+ -+#ifdef DEBUG_SPIDEV -+ printk(" %i: %x (%i)\n", i, list->tx[i], list->txlen[i]); -+#endif -+ -+ ofs = 0; /* all subsequent transfers start at beginning of a page */ -+ count = count - pagelen; -+ pagelen = (count < PAGE_SIZE) ? count : PAGE_SIZE; -+ } -+ list->nr_transfers = pgcount; -+ -+ /* Perform transfer on SPI bus */ -+ spi_access_bus(spi_device); -+ spi_transfer(list); -+ spi_release_bus(spi_device); -+ -+ while (pgcount--) { -+ page_cache_release (maplist[pgcount]); -+ } -+ flush_cache_all(); -+ -+ kfree(maplist); -+ kfree(list); -+ -+ return res; -+} -+ -+static int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int spi_device = MINOR(inode->i_rdev); -+ -+ if (spi_device >= NR_SPI_DEVICES) -+ return -ENODEV; -+ -+ // TODO: This interface can be used to configure the SPI bus. -+ // Configurable options could include: Speed, Clock Polarity, Clock Phase -+ -+ switch(cmd) { -+ default: -+ return -ENOIOCTLCMD; -+ } -+} -+ -+/* -+ * Open the SPI device -+ */ -+static int spidev_open(struct inode *inode, struct file *file) -+{ -+ unsigned int spi_device = MINOR(inode->i_rdev); -+ -+ if (spi_device >= NR_SPI_DEVICES) -+ return -ENODEV; -+ -+ /* -+ * 'private_data' is actually a pointer, but we overload it with the -+ * value we want to store. -+ */ -+ file->private_data = (void *)spi_device; -+ -+ return 0; -+} -+ -+/* -+ * Close the SPI device -+ */ -+static int spidev_close(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+/* ......................................................................... */ -+ -+static struct file_operations spidev_fops = { -+ .owner = THIS_MODULE, -+ .llseek = no_llseek, -+ .read = spidev_rd_wr, -+ .write = (int (*) (struct file *file, const char *buf, size_t count, loff_t *offset))spidev_rd_wr, -+ .ioctl = spidev_ioctl, -+ .open = spidev_open, -+ .release = spidev_close, -+}; -+ -+/* -+ * Install the SPI /dev interface driver -+ */ -+static int __init at91_spidev_init(void) -+{ -+#ifdef CONFIG_DEVFS_FS -+ int i; -+#endif -+ -+ if (register_chrdev(SPI_MAJOR, "spi", &spidev_fops)) { -+ printk(KERN_ERR "at91_spidev: Unable to get major %d for SPI bus\n", SPI_MAJOR); -+ return -EIO; -+ } -+ -+#ifdef CONFIG_DEVFS_FS -+ devfs_mk_dir("spi"); -+ for (i = 0; i < NR_SPI_DEVICES; i++) { -+ devfs_mk_cdev(MKDEV(SPI_MAJOR, i), S_IFCHR | S_IRUSR | S_IWUSR, "spi/%d",i); -+ } -+#endif -+ printk(KERN_INFO "AT91 SPI driver loaded\n"); -+ -+ return 0; -+} -+ -+/* -+ * Remove the SPI /dev interface driver -+ */ -+static void __exit at91_spidev_exit(void) -+{ -+#ifdef CONFIG_DEVFS_FS -+ int i; -+ for (i = 0; i < NR_SPI_DEVICES; i++) { -+ devfs_remove("spi/%d", i); -+ } -+ -+ devfs_remove("spi"); -+#endif -+ -+ if (unregister_chrdev(SPI_MAJOR, "spi")) { -+ printk(KERN_ERR "at91_spidev: Unable to release major %d for SPI bus\n", SPI_MAJOR); -+ return; -+ } -+} -+ -+module_init(at91_spidev_init); -+module_exit(at91_spidev_exit); -+ -+MODULE_LICENSE("GPL") -+MODULE_AUTHOR("Andrew Victor") -+MODULE_DESCRIPTION("SPI /dev interface for Atmel AT91RM9200") -diff -urN -x CVS linux-2.6.21/drivers/i2c/busses/Kconfig linux-2.6-stable/drivers/i2c/busses/Kconfig ---- linux-2.6.21/drivers/i2c/busses/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/i2c/busses/Kconfig Tue May 8 12:13:31 2007 -@@ -81,6 +81,14 @@ - This supports the use of the I2C interface on Atmel AT91 - processors. - -+config I2C_AT91_CLOCKRATE -+ prompt "Atmel AT91 I2C/TWI clock-rate" -+ depends on I2C_AT91 -+ int -+ default 100000 -+ help -+ Set the AT91 I2C/TWI clock-rate. -+ - config I2C_AU1550 - tristate "Au1550/Au1200 SMBus interface" - depends on I2C && (SOC_AU1550 || SOC_AU1200) -@@ -545,6 +553,14 @@ - This driver can also be built as a module. If so, the module - will be called i2c-voodoo3. - -+config I2C_PCA -+ tristate "PCA9564" -+ depends on I2C -+ select I2C_ALGOPCA -+ help -+ This driver support the Philips PCA 9564 Parallel bus to I2C -+ bus controller. -+ - config I2C_PCA_ISA - tristate "PCA9564 on an ISA bus" - depends on I2C -diff -urN -x CVS linux-2.6.21/drivers/i2c/busses/Makefile linux-2.6-stable/drivers/i2c/busses/Makefile ---- linux-2.6.21/drivers/i2c/busses/Makefile Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/i2c/busses/Makefile Tue May 8 12:13:31 2007 -@@ -28,6 +28,7 @@ - obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o - obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o - obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o -+obj-$(CONFIG_I2C_PCA) += i2c-pca.o - obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o - obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o - obj-$(CONFIG_I2C_PNX) += i2c-pnx.o -diff -urN -x CVS linux-2.6.21/drivers/i2c/busses/i2c-at91.c linux-2.6-stable/drivers/i2c/busses/i2c-at91.c ---- linux-2.6.21/drivers/i2c/busses/i2c-at91.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/i2c/busses/i2c-at91.c Tue May 8 12:13:31 2007 -@@ -31,8 +31,11 @@ - #include <asm/arch/board.h> - #include <asm/arch/cpu.h> - --#define TWI_CLOCK 100000 /* Hz. max 400 Kbits/sec */ - -+/* Clockrate is configurable - max 400 Kbits/sec */ -+static unsigned int clockrate = CONFIG_I2C_AT91_CLOCKRATE; -+module_param(clockrate, uint, 0); -+MODULE_PARM_DESC(clockrate, "The TWI clockrate"); - - static struct clk *twi_clk; - static void __iomem *twi_base; -@@ -53,7 +56,7 @@ - at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN); /* Set Master mode */ - - /* Calcuate clock dividers */ -- cdiv = (clk_get_rate(twi_clk) / (2 * TWI_CLOCK)) - 3; -+ cdiv = (clk_get_rate(twi_clk) / (2 * clockrate)) - 3; - cdiv = cdiv + 1; /* round up */ - ckdiv = 0; - while (cdiv > 255) { -@@ -61,11 +64,12 @@ - cdiv = cdiv >> 1; - } - -- if (cpu_is_at91rm9200()) { /* AT91RM9200 Errata #22 */ -- if (ckdiv > 5) { -- printk(KERN_ERR "AT91 I2C: Invalid TWI_CLOCK value!\n"); -- ckdiv = 5; -- } -+ if (cpu_is_at91rm9200() && (ckdiv > 5)) { /* AT91RM9200 Errata #22 */ -+ printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n"); -+ ckdiv = 5; -+ } else if (ckdiv > 7) { -+ printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n"); -+ ckdiv = 7; - } - - at91_twi_write(AT91_TWI_CWGR, (ckdiv << 16) | (cdiv << 8) | cdiv); -diff -urN -x CVS linux-2.6.21/drivers/i2c/busses/i2c-pca.c linux-2.6-stable/drivers/i2c/busses/i2c-pca.c ---- linux-2.6.21/drivers/i2c/busses/i2c-pca.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/drivers/i2c/busses/i2c-pca.c Tue May 8 12:13:31 2007 -@@ -0,0 +1,213 @@ -+/* -+ * Platform driver for PCA9564 I2C bus controller. -+ * -+ * (C) 2006 Andrew Victor -+ * -+ * Based on i2c-pca-isa.c driver for PCA9564 on ISA boards -+ * Copyright (C) 2004 Arcom Control Systems -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/moduleparam.h> -+#include <linux/delay.h> -+#include <linux/init.h> -+#include <linux/interrupt.h> -+#include <linux/wait.h> -+#include <linux/platform_device.h> -+ -+#include <linux/i2c.h> -+#include <linux/i2c-algo-pca.h> -+ -+#include <asm/io.h> -+ -+#include "../algos/i2c-algo-pca.h" -+ -+#define PCA_OWN_ADDRESS 0x55 /* our address for slave mode */ -+#define PCA_CLOCK I2C_PCA_CON_59kHz -+ -+//#define REG_SHIFT 2 -+#define REG_SHIFT 0 -+ -+//#define DEBUG_IO -+ -+#define PCA_IO_SIZE 4 -+ -+static void __iomem *base_addr; -+static int irq; -+static wait_queue_head_t pca_wait; -+ -+static int pca_getown(struct i2c_algo_pca_data *adap) -+{ -+ return PCA_OWN_ADDRESS; -+} -+ -+static int pca_getclock(struct i2c_algo_pca_data *adap) -+{ -+ return PCA_CLOCK; -+} -+ -+static void pca_writebyte(struct i2c_algo_pca_data *adap, int reg, int val) -+{ -+#ifdef DEBUG_IO -+ static char *names[] = { "T/O", "DAT", "ADR", "CON" }; -+ printk("*** write %s at %#lx <= %#04x\n", names[reg], (unsigned long) base_addr+reg, val); -+#endif -+ udelay(1); -+ outb(val, base_addr + (reg << REG_SHIFT)); -+} -+ -+static int pca_readbyte(struct i2c_algo_pca_data *adap, int reg) -+{ -+ int res; -+ -+ udelay(1); -+ res = inb(base_addr + (reg << REG_SHIFT)); -+#ifdef DEBUG_IO -+ { -+ static char *names[] = { "STA", "DAT", "ADR", "CON" }; -+ printk("*** read %s => %#04x\n", names[reg], res); -+ } -+#endif -+ return res; -+} -+ -+static int pca_waitforinterrupt(struct i2c_algo_pca_data *adap) -+{ -+ int ret = 0; -+ -+ if (irq > -1) { -+ ret = wait_event_interruptible(pca_wait, -+ pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI); -+ } else { -+ while ((pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0) -+ udelay(100); -+ } -+ return ret; -+} -+ -+static irqreturn_t pca_handler(int this_irq, void *dev_id) -+{ -+ wake_up_interruptible(&pca_wait); -+ return IRQ_HANDLED; -+} -+ -+static struct i2c_algo_pca_data pca_i2c_data = { -+ .get_own = pca_getown, -+ .get_clock = pca_getclock, -+ .write_byte = pca_writebyte, -+ .read_byte = pca_readbyte, -+ .wait_for_interrupt = pca_waitforinterrupt, -+}; -+ -+static struct i2c_adapter pca_i2c_ops = { -+ .owner = THIS_MODULE, -+ .id = I2C_HW_A_PLAT, -+ .algo_data = &pca_i2c_data, -+ .name = "PCA9564", -+ .class = I2C_CLASS_HWMON, -+}; -+ -+static int __devinit pca_i2c_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ -+ init_waitqueue_head(&pca_wait); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -ENODEV; -+ -+ if (!request_mem_region(res->start, PCA_IO_SIZE, "PCA9564")) -+ return -ENXIO; -+ -+ base_addr = ioremap(res->start, PCA_IO_SIZE); -+ if (base_addr == NULL) -+ goto out_region; -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq > -1) { -+ if (request_irq(irq, pca_handler, 0, "pca9564", NULL) < 0) { -+ printk(KERN_ERR "i2c-pca: Request irq%d failed\n", irq); -+ goto out_remap; -+ } -+ } -+ -+ /* set up the driverfs linkage to our parent device */ -+ pca_i2c_ops.dev.parent = &pdev->dev; -+ -+ if (i2c_pca_add_bus(&pca_i2c_ops) < 0) { -+ printk(KERN_ERR "i2c-pca: Failed to add i2c bus\n"); -+ goto out_irq; -+ } -+ -+ return 0; -+ -+ out_irq: -+ if (irq > -1) -+ free_irq(irq, &pca_i2c_ops); -+ -+ out_remap: -+ iounmap(base_addr); -+ -+ out_region: -+ release_mem_region(res->start, PCA_IO_SIZE); -+ return -ENODEV; -+} -+ -+static int __devexit pca_i2c_remove(struct platform_device *pdev) -+{ -+ struct resource *res; -+ -+ i2c_del_adapter(&pca_i2c_ops); -+ -+ if (irq > 0) -+ free_irq(irq, NULL); -+ -+ iounmap(base_addr); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ release_mem_region(res->start, PCA_IO_SIZE); -+ -+ return 0; -+} -+ -+static struct platform_driver pca_i2c_driver = { -+ .probe = pca_i2c_probe, -+ .remove = __devexit_p(pca_i2c_remove), -+ .driver = { -+ .name = "pca9564", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init pca_i2c_init(void) -+{ -+ return platform_driver_register(&pca_i2c_driver); -+} -+ -+static void __exit pca_i2c_exit(void) -+{ -+ platform_driver_unregister(&pca_i2c_driver); -+} -+ -+module_init(pca_i2c_init); -+module_exit(pca_i2c_exit); -+ -+MODULE_AUTHOR("Andrew Victor"); -+MODULE_DESCRIPTION("PCA9564 platform driver"); -+MODULE_LICENSE("GPL"); -diff -urN -x CVS linux-2.6.21/drivers/input/touchscreen/ads7846.c linux-2.6-stable/drivers/input/touchscreen/ads7846.c ---- linux-2.6.21/drivers/input/touchscreen/ads7846.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/input/touchscreen/ads7846.c Tue May 8 12:56:33 2007 -@@ -39,7 +39,8 @@ - /* - * This code has been heavily tested on a Nokia 770, and lightly - * tested on other ads7846 devices (OSK/Mistral, Lubbock). -- * Support for ads7843 and ads7845 has only been stubbed in. -+ * Support for ads7843 tested on Atmel at91sam926x-EK. -+ * Support for ads7845 has only been stubbed in. - * - * IRQ handling needs a workaround because of a shortcoming in handling - * edge triggered IRQs on some platforms like the OMAP1/2. These -@@ -246,18 +247,16 @@ - - /* REVISIT: take a few more samples, and compare ... */ - -- /* maybe off internal vREF */ -- if (use_internal) { -- req->ref_off = REF_OFF; -- req->xfer[4].tx_buf = &req->ref_off; -- req->xfer[4].len = 1; -- spi_message_add_tail(&req->xfer[4], &req->msg); -- -- req->xfer[5].rx_buf = &req->scratch; -- req->xfer[5].len = 2; -- CS_CHANGE(req->xfer[5]); -- spi_message_add_tail(&req->xfer[5], &req->msg); -- } -+ /* converter in low power mode & enable PENIRQ */ -+ req->ref_off = PWRDOWN; -+ req->xfer[4].tx_buf = &req->ref_off; -+ req->xfer[4].len = 1; -+ spi_message_add_tail(&req->xfer[4], &req->msg); -+ -+ req->xfer[5].rx_buf = &req->scratch; -+ req->xfer[5].len = 2; -+ CS_CHANGE(req->xfer[5]); -+ spi_message_add_tail(&req->xfer[5], &req->msg); - - ts->irq_disabled = 1; - disable_irq(spi->irq); -@@ -536,6 +535,9 @@ - } else - Rt = 0; - -+ if (ts->model == 7843) -+ Rt = ts->pressure_max / 2; -+ - /* Sample found inconsistent by debouncing or pressure is beyond - * the maximum. Don't report it to user space, repeat at least - * once more the measurement -diff -urN -x CVS linux-2.6.21/drivers/leds/Kconfig linux-2.6-stable/drivers/leds/Kconfig ---- linux-2.6.21/drivers/leds/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/leds/Kconfig Tue May 8 12:13:31 2007 -@@ -76,6 +76,13 @@ - This option enables support for the Soekris net4801 and net4826 error - LED. - -+config LEDS_AT91 -+ tristate "LED support using AT91 GPIOs" -+ depends on LEDS_CLASS && ARCH_AT91 && !LEDS -+ help -+ This option enables support for LEDs connected to GPIO lines -+ on AT91-based boards. -+ - config LEDS_WRAP - tristate "LED Support for the WRAP series LEDs" - depends on LEDS_CLASS && SCx200_GPIO -diff -urN -x CVS linux-2.6.21/drivers/leds/Makefile linux-2.6-stable/drivers/leds/Makefile ---- linux-2.6.21/drivers/leds/Makefile Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/leds/Makefile Tue May 8 12:13:31 2007 -@@ -16,6 +16,7 @@ - obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o - obj-$(CONFIG_LEDS_H1940) += leds-h1940.o - obj-$(CONFIG_LEDS_COBALT) += leds-cobalt.o -+obj-$(CONFIG_LEDS_AT91) += leds-at91.o - - # LED Triggers - obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o -diff -urN -x CVS linux-2.6.21/drivers/leds/leds-at91.c linux-2.6-stable/drivers/leds/leds-at91.c ---- linux-2.6.21/drivers/leds/leds-at91.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/drivers/leds/leds-at91.c Tue May 8 12:13:31 2007 -@@ -0,0 +1,140 @@ -+/* -+ * AT91 GPIO based LED driver -+ * -+ * Copyright (C) 2006 David Brownell -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/init.h> -+#include <linux/platform_device.h> -+#include <linux/leds.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+ -+static LIST_HEAD(at91_led_list); /* list of AT91 LEDs */ -+ -+struct at91_led { -+ struct led_classdev cdev; -+ struct list_head list; -+ struct at91_gpio_led *led_data; -+}; -+ -+/* -+ * Change the state of the LED. -+ */ -+static void at91_led_set(struct led_classdev *cdev, enum led_brightness value) -+{ -+ struct at91_led *led = container_of(cdev, struct at91_led, cdev); -+ short active = (value == LED_OFF); -+ -+ if (led->led_data->flags & 1) /* active high/low? */ -+ active = !active; -+ at91_set_gpio_value(led->led_data->gpio, active); -+} -+ -+static int __devexit at91_led_remove(struct platform_device *pdev) -+{ -+ struct at91_led *led; -+ -+ list_for_each_entry (led, &at91_led_list, list) -+ led_classdev_unregister(&led->cdev); -+ -+#warning "Free allocated memory" -+ // TODO: Free memory. kfree(led); -+ -+ return 0; -+} -+ -+static int __init at91_led_probe(struct platform_device *pdev) -+{ -+ int status = 0; -+ struct at91_gpio_led *pdata = pdev->dev.platform_data; -+ unsigned nr_leds; -+ struct at91_led *led; -+ -+ if (!pdata) -+ return -ENODEV; -+ -+ nr_leds = pdata->index; /* first index stores number of LEDs */ -+ -+ while (nr_leds--) { -+ led = kzalloc(sizeof(struct at91_led), GFP_KERNEL); -+ if (!led) { -+ dev_err(&pdev->dev, "No memory for device\n"); -+ status = -ENOMEM; -+ goto cleanup; -+ } -+ led->led_data = pdata; -+ led->cdev.name = pdata->name; -+ led->cdev.brightness_set = at91_led_set, -+ led->cdev.default_trigger = pdata->trigger; -+ -+ status = led_classdev_register(&pdev->dev, &led->cdev); -+ if (status < 0) { -+ dev_err(&pdev->dev, "led_classdev_register failed - %d\n", status); -+cleanup: -+ at91_led_remove(pdev); -+ break; -+ } -+ list_add(&led->list, &at91_led_list); -+ pdata++; -+ } -+ return status; -+} -+ -+#ifdef CONFIG_PM -+static int at91_led_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ struct at91_led *led; -+ -+ list_for_each_entry (led, &at91_led_list, list) -+ led_classdev_suspend(&led->cdev); -+ -+ return 0; -+} -+ -+static int at91_led_resume(struct platform_device *dev) -+{ -+ struct at91_led *led; -+ -+ list_for_each_entry (led, &at91_led_list, list) -+ led_classdev_resume(&led->cdev); -+ -+ return 0; -+} -+#else -+#define at91_led_suspend NULL -+#define at91_led_resume NULL -+#endif -+ -+static struct platform_driver at91_led_driver = { -+ .probe = at91_led_probe, -+ .remove = __devexit_p(at91_led_remove), -+ .suspend = at91_led_suspend, -+ .resume = at91_led_resume, -+ .driver = { -+ .name = "at91_leds", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init at91_led_init(void) -+{ -+ return platform_driver_register(&at91_led_driver); -+} -+module_init(at91_led_init); -+ -+static void __exit at91_led_exit(void) -+{ -+ platform_driver_unregister(&at91_led_driver); -+} -+module_exit(at91_led_exit); -+ -+MODULE_DESCRIPTION("AT91 GPIO LED driver"); -+MODULE_AUTHOR("David Brownell"); -+MODULE_LICENSE("GPL"); -diff -urN -x CVS linux-2.6.21/drivers/mmc/at91_mci.c linux-2.6-stable/drivers/mmc/at91_mci.c ---- linux-2.6.21/drivers/mmc/at91_mci.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/mmc/at91_mci.c Fri May 11 17:13:13 2007 -@@ -86,7 +86,7 @@ - - #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ - | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ -- | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) -+ | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) - - #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) - #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) -@@ -561,9 +561,7 @@ - pr_debug("Status = %08X [%08X %08X %08X %08X]\n", - status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - -- if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE | -- AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE | -- AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) { -+ if (status & AT91_MCI_ERRORS) { - if ((status & AT91_MCI_RCRCE) && - ((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) { - cmd->error = MMC_ERR_NONE; -@@ -665,15 +663,15 @@ - - int_status = at91_mci_read(host, AT91_MCI_SR); - int_mask = at91_mci_read(host, AT91_MCI_IMR); -- -+ - pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, - int_status & int_mask); -- -+ - int_status = int_status & int_mask; - - if (int_status & AT91_MCI_ERRORS) { - completed = 1; -- -+ - if (int_status & AT91_MCI_UNRE) - pr_debug("MMC: Underrun error\n"); - if (int_status & AT91_MCI_OVRE) -@@ -821,7 +819,7 @@ - mmc->f_min = 375000; - mmc->f_max = 25000000; - mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; -- mmc->caps = MMC_CAP_BYTEBLOCK; -+ mmc->caps = MMC_CAP_BYTEBLOCK | MMC_CAP_MULTIWRITE; - - mmc->max_blk_size = 4095; - mmc->max_blk_count = mmc->max_req_size; -@@ -895,6 +893,8 @@ - - mmc_add_host(mmc); - -+ device_init_wakeup(&pdev->dev, 1); -+ - /* - * monitor card insertion/removal if we can - */ -@@ -924,6 +924,8 @@ - - host = mmc_priv(mmc); - -+ device_init_wakeup(&pdev->dev, 0); -+ - if (host->present != -1) { - free_irq(host->board->det_pin, host); - cancel_delayed_work(&host->mmc->detect); -@@ -951,8 +953,12 @@ - static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) - { - struct mmc_host *mmc = platform_get_drvdata(pdev); -+ struct at91mci_host *host = mmc_priv(mmc); - int ret = 0; - -+ if (device_may_wakeup(&pdev->dev)) -+ enable_irq_wake(host->board->det_pin); -+ - if (mmc) - ret = mmc_suspend_host(mmc, state); - -@@ -962,8 +968,12 @@ - static int at91_mci_resume(struct platform_device *pdev) - { - struct mmc_host *mmc = platform_get_drvdata(pdev); -+ struct at91mci_host *host = mmc_priv(mmc); - int ret = 0; - -+ if (device_may_wakeup(&pdev->dev)) -+ disable_irq_wake(host->board->det_pin); -+ - if (mmc) - ret = mmc_resume_host(mmc); - -diff -urN -x CVS linux-2.6.21/drivers/mtd/devices/Kconfig linux-2.6-stable/drivers/mtd/devices/Kconfig ---- linux-2.6.21/drivers/mtd/devices/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/mtd/devices/Kconfig Tue May 8 14:31:24 2007 -@@ -267,5 +267,11 @@ - LinuxBIOS or if you need to recover a DiskOnChip Millennium on which - you have managed to wipe the first block. - --endmenu -+config MTD_AT91_DATAFLASH -+ tristate "AT91RM9200 DataFlash AT45DBxxx (legacy driver)" -+ depends on MTD && ARCH_AT91RM9200 && AT91_SPI -+ help -+ This enables access to the DataFlash (AT45DBxxx) on the AT91RM9200. -+ If you have such a board, say 'Y'. - -+endmenu -diff -urN -x CVS linux-2.6.21/drivers/mtd/devices/Makefile linux-2.6-stable/drivers/mtd/devices/Makefile ---- linux-2.6.21/drivers/mtd/devices/Makefile Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/mtd/devices/Makefile Tue May 8 14:31:24 2007 -@@ -17,3 +17,4 @@ - obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o - obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o - obj-$(CONFIG_MTD_M25P80) += m25p80.o -+obj-$(CONFIG_MTD_AT91_DATAFLASH)+= at91_dataflash.o -diff -urN -x CVS linux-2.6.21/drivers/mtd/devices/at91_dataflash.c linux-2.6-stable/drivers/mtd/devices/at91_dataflash.c ---- linux-2.6.21/drivers/mtd/devices/at91_dataflash.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/drivers/mtd/devices/at91_dataflash.c Tue May 8 14:31:24 2007 -@@ -0,0 +1,667 @@ -+/* -+ * Atmel DataFlash driver for Atmel AT91RM9200 (Thunder) -+ * -+ * Copyright (C) SAN People (Pty) Ltd -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+*/ -+ -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/slab.h> -+#include <linux/pci.h> -+#include <linux/mtd/mtd.h> -+#include <linux/mtd/partitions.h> -+ -+#include <asm/arch/spi.h> -+ -+#undef DEBUG_DATAFLASH -+ -+#define DATAFLASH_MAX_DEVICES 4 /* max number of dataflash devices */ -+#undef DATAFLASH_ALWAYS_ADD_DEVICE /* always add whole device when using partitions? */ -+ -+#define OP_READ_CONTINUOUS 0xE8 -+#define OP_READ_PAGE 0xD2 -+#define OP_READ_BUFFER1 0xD4 -+#define OP_READ_BUFFER2 0xD6 -+#define OP_READ_STATUS 0xD7 -+ -+#define OP_ERASE_PAGE 0x81 -+#define OP_ERASE_BLOCK 0x50 -+ -+#define OP_TRANSFER_BUF1 0x53 -+#define OP_TRANSFER_BUF2 0x55 -+#define OP_COMPARE_BUF1 0x60 -+#define OP_COMPARE_BUF2 0x61 -+ -+#define OP_PROGRAM_VIA_BUF1 0x82 -+#define OP_PROGRAM_VIA_BUF2 0x85 -+ -+struct dataflash_local -+{ -+ int spi; /* SPI chip-select number */ -+ -+ unsigned int page_size; /* number of bytes per page */ -+ unsigned short page_offset; /* page offset in flash address */ -+}; -+ -+ -+/* Detected DataFlash devices */ -+static struct mtd_info* mtd_devices[DATAFLASH_MAX_DEVICES]; -+static int nr_devices = 0; -+ -+/* ......................................................................... */ -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ -+static struct mtd_partition static_partitions_2M[] = -+{ -+ { -+ .name = "bootloader", -+ .offset = 0, -+ .size = 1 * 32 * 8 * 528, /* 1st sector = 32 blocks * 8 pages * 528 bytes */ -+ .mask_flags = MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 6 * 32 * 8 * 528, /* 6 sectors */ -+ }, -+ { -+ .name = "filesystem", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, /* rest = 9 sectors */ -+ } -+}; -+ -+static struct mtd_partition static_partitions_4M[] = -+{ -+ { -+ .name = "bootloader", -+ .offset = 0, -+ .size = 1 * 64 * 8 * 528, /* 1st sector = 64 blocks * 8 pages * 528 bytes */ -+ .mask_flags = MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 4 * 64 * 8 * 528, /* 4 sectors */ -+ }, -+ { -+ .name = "filesystem", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, /* rest = 11 sectors */ -+ } -+}; -+ -+#if defined(CONFIG_MACH_KAFA) -+static struct mtd_partition static_partitions_8M[] = -+{ -+ { -+ name: "romboot", -+ offset: 0, -+ size: 16 * 1056, /* 160 Kb */ -+ mask_flags: MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ name: "uboot", -+ offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */ -+ size: 128 * 1056, /* 1 MB */ -+ }, -+ { -+ name: "kernel", -+ offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */ -+ size: 1024 * 1056, /* 1 MB */ -+ }, -+ { -+ name: "filesystem", -+ offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */ -+ size: MTDPART_SIZ_FULL, -+ } -+}; -+ -+#elif defined(CONFIG_MACH_MULTMDP) -+ -+static struct mtd_partition static_partitions_8M[] = -+{ -+ { -+ .name = "bootloader", -+ .offset = 0, -+ .size = 12 * 1056, /* 1st sector = 32 blocks * 8 pages * 1056 bytes */ -+ .mask_flags = MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ .name = "configuration", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 20 * 1056, -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 1520 * 1056, -+ }, -+ { -+ .name = "filesystem", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ } -+}; -+ -+#else -+ -+static struct mtd_partition static_partitions_8M[] = -+{ -+ { -+ .name = "bootloader", -+ .offset = 0, -+ .size = 1 * 32 * 8 * 1056, /* 1st sector = 32 blocks * 8 pages * 1056 bytes */ -+ .mask_flags = MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 5 * 32 * 8 * 1056, /* 5 sectors */ -+ }, -+ { -+ .name = "filesystem", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, /* rest = 26 sectors */ -+ } -+}; -+#endif -+ -+static const char *part_probes[] = { "cmdlinepart", NULL, }; -+ -+#endif -+ -+/* ......................................................................... */ -+ -+/* Allocate a single SPI transfer descriptor. We're assuming that if multiple -+ SPI transfers occur at the same time, spi_access_bus() will serialize them. -+ If this is not valid, then either (i) each dataflash 'priv' structure -+ needs it's own transfer descriptor, (ii) we lock this one, or (iii) use -+ another mechanism. */ -+static struct spi_transfer_list* spi_transfer_desc; -+ -+/* -+ * Perform a SPI transfer to access the DataFlash device. -+ */ -+static int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len, -+ char* txnext, int txnext_len, char* rxnext, int rxnext_len) -+{ -+ struct spi_transfer_list* list = spi_transfer_desc; -+ -+ list->tx[0] = tx; list->txlen[0] = tx_len; -+ list->rx[0] = rx; list->rxlen[0] = rx_len; -+ -+ list->tx[1] = txnext; list->txlen[1] = txnext_len; -+ list->rx[1] = rxnext; list->rxlen[1] = rxnext_len; -+ -+ list->nr_transfers = nr; -+ -+ return spi_transfer(list); -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Poll the DataFlash device until it is READY. -+ */ -+static void at91_dataflash_waitready(void) -+{ -+ char* command = kmalloc(2, GFP_KERNEL); -+ -+ if (!command) -+ return; -+ -+ do { -+ command[0] = OP_READ_STATUS; -+ command[1] = 0; -+ -+ do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0); -+ } while ((command[1] & 0x80) == 0); -+ -+ kfree(command); -+} -+ -+/* -+ * Return the status of the DataFlash device. -+ */ -+static unsigned short at91_dataflash_status(void) -+{ -+ unsigned short status; -+ char* command = kmalloc(2, GFP_KERNEL); -+ -+ if (!command) -+ return 0; -+ -+ command[0] = OP_READ_STATUS; -+ command[1] = 0; -+ -+ do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0); -+ status = command[1]; -+ -+ kfree(command); -+ return status; -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Erase blocks of flash. -+ */ -+static int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) -+{ -+ struct dataflash_local *priv = (struct dataflash_local *) mtd->priv; -+ unsigned int pageaddr; -+ char* command; -+ -+#ifdef DEBUG_DATAFLASH -+ printk("dataflash_erase: addr=%i len=%i\n", instr->addr, instr->len); -+#endif -+ -+ /* Sanity checks */ -+ if (instr->addr + instr->len > mtd->size) -+ return -EINVAL; -+ if ((instr->len % mtd->erasesize != 0) || (instr->len % priv->page_size != 0)) -+ return -EINVAL; -+ if ((instr->addr % priv->page_size) != 0) -+ return -EINVAL; -+ -+ command = kmalloc(4, GFP_KERNEL); -+ if (!command) -+ return -ENOMEM; -+ -+ while (instr->len > 0) { -+ /* Calculate flash page address */ -+ pageaddr = (instr->addr / priv->page_size) << priv->page_offset; -+ -+ command[0] = OP_ERASE_PAGE; -+ command[1] = (pageaddr & 0x00FF0000) >> 16; -+ command[2] = (pageaddr & 0x0000FF00) >> 8; -+ command[3] = 0; -+#ifdef DEBUG_DATAFLASH -+ printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr); -+#endif -+ -+ /* Send command to SPI device */ -+ spi_access_bus(priv->spi); -+ do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0); -+ -+ at91_dataflash_waitready(); /* poll status until ready */ -+ spi_release_bus(priv->spi); -+ -+ instr->addr += priv->page_size; /* next page */ -+ instr->len -= priv->page_size; -+ } -+ -+ kfree(command); -+ -+ /* Inform MTD subsystem that erase is complete */ -+ instr->state = MTD_ERASE_DONE; -+ if (instr->callback) -+ instr->callback(instr); -+ -+ return 0; -+} -+ -+/* -+ * Read from the DataFlash device. -+ * from : Start offset in flash device -+ * len : Amount to read -+ * retlen : About of data actually read -+ * buf : Buffer containing the data -+ */ -+static int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) -+{ -+ struct dataflash_local *priv = (struct dataflash_local *) mtd->priv; -+ unsigned int addr; -+ char* command; -+ -+#ifdef DEBUG_DATAFLASH -+ printk("dataflash_read: %lli .. %lli\n", from, from+len); -+#endif -+ -+ *retlen = 0; -+ -+ /* Sanity checks */ -+ if (!len) -+ return 0; -+ if (from + len > mtd->size) -+ return -EINVAL; -+ -+ /* Calculate flash page/byte address */ -+ addr = (((unsigned)from / priv->page_size) << priv->page_offset) + ((unsigned)from % priv->page_size); -+ -+ command = kmalloc(8, GFP_KERNEL); -+ if (!command) -+ return -ENOMEM; -+ -+ command[0] = OP_READ_CONTINUOUS; -+ command[1] = (addr & 0x00FF0000) >> 16; -+ command[2] = (addr & 0x0000FF00) >> 8; -+ command[3] = (addr & 0x000000FF); -+#ifdef DEBUG_DATAFLASH -+ printk("READ: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); -+#endif -+ -+ /* Send command to SPI device */ -+ spi_access_bus(priv->spi); -+ do_spi_transfer(2, command, 8, command, 8, buf, len, buf, len); -+ spi_release_bus(priv->spi); -+ -+ *retlen = len; -+ kfree(command); -+ return 0; -+} -+ -+/* -+ * Write to the DataFlash device. -+ * to : Start offset in flash device -+ * len : Amount to write -+ * retlen : Amount of data actually written -+ * buf : Buffer containing the data -+ */ -+static int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) -+{ -+ struct dataflash_local *priv = (struct dataflash_local *) mtd->priv; -+ unsigned int pageaddr, addr, offset, writelen; -+ size_t remaining; -+ u_char *writebuf; -+ unsigned short status; -+ int res = 0; -+ char* command; -+ char* tmpbuf = NULL; -+ -+#ifdef DEBUG_DATAFLASH -+ printk("dataflash_write: %lli .. %lli\n", to, to+len); -+#endif -+ -+ *retlen = 0; -+ -+ /* Sanity checks */ -+ if (!len) -+ return 0; -+ if (to + len > mtd->size) -+ return -EINVAL; -+ -+ command = kmalloc(4, GFP_KERNEL); -+ if (!command) -+ return -ENOMEM; -+ -+ pageaddr = ((unsigned)to / priv->page_size); -+ offset = ((unsigned)to % priv->page_size); -+ if (offset + len > priv->page_size) -+ writelen = priv->page_size - offset; -+ else -+ writelen = len; -+ writebuf = (u_char *)buf; -+ remaining = len; -+ -+ /* Allocate temporary buffer */ -+ tmpbuf = kmalloc(priv->page_size, GFP_KERNEL); -+ if (!tmpbuf) { -+ kfree(command); -+ return -ENOMEM; -+ } -+ -+ /* Gain access to the SPI bus */ -+ spi_access_bus(priv->spi); -+ -+ while (remaining > 0) { -+#ifdef DEBUG_DATAFLASH -+ printk("write @ %i:%i len=%i\n", pageaddr, offset, writelen); -+#endif -+ -+ /* (1) Transfer to Buffer1 */ -+ if (writelen != priv->page_size) { -+ addr = pageaddr << priv->page_offset; -+ command[0] = OP_TRANSFER_BUF1; -+ command[1] = (addr & 0x00FF0000) >> 16; -+ command[2] = (addr & 0x0000FF00) >> 8; -+ command[3] = 0; -+#ifdef DEBUG_DATAFLASH -+ printk("TRANSFER: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); -+#endif -+ do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0); -+ at91_dataflash_waitready(); -+ } -+ -+ /* (2) Program via Buffer1 */ -+ addr = (pageaddr << priv->page_offset) + offset; -+ command[0] = OP_PROGRAM_VIA_BUF1; -+ command[1] = (addr & 0x00FF0000) >> 16; -+ command[2] = (addr & 0x0000FF00) >> 8; -+ command[3] = (addr & 0x000000FF); -+#ifdef DEBUG_DATAFLASH -+ printk("PROGRAM: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); -+#endif -+ do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, tmpbuf, writelen); -+ at91_dataflash_waitready(); -+ -+ /* (3) Compare to Buffer1 */ -+ addr = pageaddr << priv->page_offset; -+ command[0] = OP_COMPARE_BUF1; -+ command[1] = (addr & 0x00FF0000) >> 16; -+ command[2] = (addr & 0x0000FF00) >> 8; -+ command[3] = 0; -+#ifdef DEBUG_DATAFLASH -+ printk("COMPARE: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); -+#endif -+ do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0); -+ at91_dataflash_waitready(); -+ -+ /* Get result of the compare operation */ -+ status = at91_dataflash_status(); -+ if ((status & 0x40) == 1) { -+ printk("at91_dataflash: Write error on page %i\n", pageaddr); -+ remaining = 0; -+ res = -EIO; -+ } -+ -+ remaining = remaining - writelen; -+ pageaddr++; -+ offset = 0; -+ writebuf += writelen; -+ *retlen += writelen; -+ -+ if (remaining > priv->page_size) -+ writelen = priv->page_size; -+ else -+ writelen = remaining; -+ } -+ -+ /* Release SPI bus */ -+ spi_release_bus(priv->spi); -+ -+ kfree(tmpbuf); -+ kfree(command); -+ return res; -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Initialize and register DataFlash device with MTD subsystem. -+ */ -+static int __init add_dataflash(int channel, char *name, int IDsize, -+ int nr_pages, int pagesize, int pageoffset) -+{ -+ struct mtd_info *device; -+ struct dataflash_local *priv; -+#ifdef CONFIG_MTD_PARTITIONS -+ struct mtd_partition *mtd_parts = 0; -+ int mtd_parts_nr = 0; -+#endif -+ -+ if (nr_devices >= DATAFLASH_MAX_DEVICES) { -+ printk(KERN_ERR "at91_dataflash: Too many devices detected\n"); -+ return 0; -+ } -+ -+ device = kmalloc(sizeof(struct mtd_info) + strlen(name) + 8, GFP_KERNEL); -+ if (!device) -+ return -ENOMEM; -+ memset(device, 0, sizeof(struct mtd_info)); -+ -+ device->name = (char *)&device[1]; -+ sprintf(device->name, "%s.spi%d", name, channel); -+ device->size = nr_pages * pagesize; -+ device->erasesize = pagesize; -+ device->writesize = pagesize; -+ device->owner = THIS_MODULE; -+ device->type = MTD_DATAFLASH; -+ device->flags = MTD_WRITEABLE; -+ device->erase = at91_dataflash_erase; -+ device->read = at91_dataflash_read; -+ device->write = at91_dataflash_write; -+ -+ priv = (struct dataflash_local *) kmalloc(sizeof(struct dataflash_local), GFP_KERNEL); -+ if (!priv) { -+ kfree(device); -+ return -ENOMEM; -+ } -+ memset(priv, 0, sizeof(struct dataflash_local)); -+ -+ priv->spi = channel; -+ priv->page_size = pagesize; -+ priv->page_offset = pageoffset; -+ device->priv = priv; -+ -+ mtd_devices[nr_devices] = device; -+ nr_devices++; -+ printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, device->size); -+ -+#ifdef CONFIG_MTD_PARTITIONS -+#ifdef CONFIG_MTD_CMDLINE_PARTS -+ mtd_parts_nr = parse_mtd_partitions(device, part_probes, &mtd_parts, 0); -+#endif -+ if (mtd_parts_nr <= 0) { -+ switch (IDsize) { -+ case SZ_2M: -+ mtd_parts = static_partitions_2M; -+ mtd_parts_nr = ARRAY_SIZE(static_partitions_2M); -+ break; -+ case SZ_4M: -+ mtd_parts = static_partitions_4M; -+ mtd_parts_nr = ARRAY_SIZE(static_partitions_4M); -+ break; -+ case SZ_8M: -+ mtd_parts = static_partitions_8M; -+ mtd_parts_nr = ARRAY_SIZE(static_partitions_8M); -+ break; -+ } -+ } -+ -+ if (mtd_parts_nr > 0) { -+#ifdef DATAFLASH_ALWAYS_ADD_DEVICE -+ add_mtd_device(device); -+#endif -+ return add_mtd_partitions(device, mtd_parts, mtd_parts_nr); -+ } -+#endif -+ return add_mtd_device(device); /* add whole device */ -+} -+ -+/* -+ * Detect and initialize DataFlash device connected to specified SPI channel. -+ * -+ * Device Density ID code Nr Pages Page Size Page offset -+ * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9 -+ * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1025 264 9 -+ * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9 -+ * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9 -+ * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10 -+ * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10 -+ * AT45DB0642 64Mbit (8M) xx1111xx (0x3c) 8192 1056 11 -+ * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11 -+ */ -+static int __init at91_dataflash_detect(int channel) -+{ -+ int res = 0; -+ unsigned short status; -+ -+ spi_access_bus(channel); -+ status = at91_dataflash_status(); -+ spi_release_bus(channel); -+ if (status != 0xff) { /* no dataflash device there */ -+ switch (status & 0x3c) { -+ case 0x0c: /* 0 0 1 1 */ -+ res = add_dataflash(channel, "AT45DB011B", SZ_128K, 512, 264, 9); -+ break; -+ case 0x14: /* 0 1 0 1 */ -+ res = add_dataflash(channel, "AT45DB021B", SZ_256K, 1025, 264, 9); -+ break; -+ case 0x1c: /* 0 1 1 1 */ -+ res = add_dataflash(channel, "AT45DB041B", SZ_512K, 2048, 264, 9); -+ break; -+ case 0x24: /* 1 0 0 1 */ -+ res = add_dataflash(channel, "AT45DB081B", SZ_1M, 4096, 264, 9); -+ break; -+ case 0x2c: /* 1 0 1 1 */ -+ res = add_dataflash(channel, "AT45DB161B", SZ_2M, 4096, 528, 10); -+ break; -+ case 0x34: /* 1 1 0 1 */ -+ res = add_dataflash(channel, "AT45DB321B", SZ_4M, 8192, 528, 10); -+ break; -+ case 0x3c: /* 1 1 1 1 */ -+ res = add_dataflash(channel, "AT45DB642", SZ_8M, 8192, 1056, 11); -+ break; -+// Currently unsupported since Atmel removed the "Main Memory Program via Buffer" commands. -+// case 0x10: /* 0 1 0 0 */ -+// res = add_dataflash(channel, "AT45DB1282", SZ_16M, 16384, 1056, 11); -+// break; -+ default: -+ printk(KERN_ERR "at91_dataflash: Unknown device (%x)\n", status & 0x3c); -+ } -+ } -+ -+ return res; -+} -+ -+static int __init at91_dataflash_init(void) -+{ -+ spi_transfer_desc = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL); -+ if (!spi_transfer_desc) -+ return -ENOMEM; -+ -+ /* DataFlash (SPI chip select 0) */ -+ at91_dataflash_detect(0); -+ -+#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD -+ /* DataFlash card (SPI chip select 3) */ -+ at91_dataflash_detect(3); -+#endif -+ -+ return 0; -+} -+ -+static void __exit at91_dataflash_exit(void) -+{ -+ int i; -+ -+ for (i = 0; i < DATAFLASH_MAX_DEVICES; i++) { -+ if (mtd_devices[i]) { -+#ifdef CONFIG_MTD_PARTITIONS -+ del_mtd_partitions(mtd_devices[i]); -+#else -+ del_mtd_device(mtd_devices[i]); -+#endif -+ kfree(mtd_devices[i]->priv); -+ kfree(mtd_devices[i]); -+ } -+ } -+ nr_devices = 0; -+ kfree(spi_transfer_desc); -+} -+ -+ -+module_init(at91_dataflash_init); -+module_exit(at91_dataflash_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Andrew Victor"); -+MODULE_DESCRIPTION("DataFlash driver for Atmel AT91RM9200"); -diff -urN -x CVS linux-2.6.21/drivers/mtd/nand/at91_nand.c linux-2.6-stable/drivers/mtd/nand/at91_nand.c ---- linux-2.6.21/drivers/mtd/nand/at91_nand.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/mtd/nand/at91_nand.c Tue May 8 12:13:31 2007 -@@ -82,6 +82,10 @@ - at91_set_gpio_value(host->board->enable_pin, 1); - } - -+#ifdef CONFIG_MTD_PARTITIONS -+const char *part_probes[] = { "cmdlinepart", NULL }; -+#endif -+ - /* - * Probe for the NAND device. - */ -@@ -151,6 +155,12 @@ - #ifdef CONFIG_MTD_PARTITIONS - if (host->board->partition_info) - partitions = host->board->partition_info(mtd->size, &num_partitions); -+#ifdef CONFIG_MTD_CMDLINE_PARTS -+ else { -+ mtd->name = "at91_nand"; -+ num_partitions = parse_mtd_partitions(mtd, part_probes, &partitions, 0); -+ } -+#endif - - if ((!partitions) || (num_partitions == 0)) { - printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n"); -diff -urN -x CVS linux-2.6.21/drivers/net/arm/at91_ether.c linux-2.6-stable/drivers/net/arm/at91_ether.c ---- linux-2.6.21/drivers/net/arm/at91_ether.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/net/arm/at91_ether.c Tue May 8 12:13:31 2007 -@@ -225,6 +225,16 @@ - if (!(phy & ((1 << 2) | 1))) - goto done; - } -+ else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */ -+ read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy); -+ if (!(phy & ((1 << 2) | 1))) -+ goto done; -+ } -+ else if (lp->phy_type == MII_DP83848_ID) { -+ read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */ -+ if (!(phy & (1 << 7))) -+ goto done; -+ } - - update_linkspeed(dev, 0); - -@@ -280,6 +290,19 @@ - dsintr = (1 << 10) | ( 1 << 8); - write_phy(lp->phy_address, MII_TPISTATUS, dsintr); - } -+ else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ -+ read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); -+ dsintr = dsintr | 0x500; /* set bits 8, 10 */ -+ write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); -+ } -+ else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ -+ read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); -+ dsintr = dsintr | 0x3c; /* set bits 2..5 */ -+ write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); -+ read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); -+ dsintr = dsintr | 0x3; /* set bits 0,1 */ -+ write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); -+ } - - disable_mdi(); - spin_unlock_irq(&lp->lock); -@@ -323,6 +346,19 @@ - dsintr = ~((1 << 10) | (1 << 8)); - write_phy(lp->phy_address, MII_TPISTATUS, dsintr); - } -+ else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ -+ read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); -+ dsintr = dsintr & ~0x500; /* clear bits 8, 10 */ -+ write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); -+ } -+ else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ -+ read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); -+ dsintr = dsintr & ~0x3; /* clear bits 0, 1 */ -+ write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); -+ read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); -+ dsintr = dsintr & ~0x3c; /* clear bits 2..5 */ -+ write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); -+ } - - disable_mdi(); - spin_unlock_irq(&lp->lock); -@@ -535,8 +571,8 @@ - mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); - } - -- at91_emac_write(AT91_EMAC_HSH, mc_filter[0]); -- at91_emac_write(AT91_EMAC_HSL, mc_filter[1]); -+ at91_emac_write(AT91_EMAC_HSL, mc_filter[0]); -+ at91_emac_write(AT91_EMAC_HSH, mc_filter[1]); - } - - /* -@@ -943,14 +979,22 @@ - struct net_device *dev; - struct at91_private *lp; - unsigned int val; -- int res; -+ struct resource *res; -+ int ret; - - dev = alloc_etherdev(sizeof(struct at91_private)); - if (!dev) - return -ENOMEM; - -- dev->base_addr = AT91_VA_BASE_EMAC; -- dev->irq = AT91RM9200_ID_EMAC; -+ /* Get I/O base address and IRQ */ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ free_netdev(dev); -+ return -ENODEV; -+ } -+ dev->base_addr = res->start; -+ dev->irq = platform_get_irq(pdev, 0); -+ - SET_MODULE_OWNER(dev); - - /* Install the interrupt handler */ -@@ -1023,12 +1067,12 @@ - lp->phy_address = phy_address; /* MDI address of PHY */ - - /* Register the network interface */ -- res = register_netdev(dev); -- if (res) { -+ ret = register_netdev(dev); -+ if (ret) { - free_irq(dev->irq, dev); - free_netdev(dev); - dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); -- return res; -+ return ret; - } - - /* Determine current link speed */ -@@ -1063,10 +1107,16 @@ - printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name); - else if (phy_type == MII_DP83847_ID) - printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name); -+ else if (phy_type == MII_DP83848_ID) -+ printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name); - else if (phy_type == MII_AC101L_ID) - printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name); - else if (phy_type == MII_KS8721_ID) - printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name); -+ else if (phy_type == MII_T78Q21x3_ID) -+ printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name); -+ else if (phy_type == MII_LAN83C185_ID) -+ printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name); - - return 0; - } -@@ -1104,8 +1154,11 @@ - case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ - case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ - case MII_DP83847_ID: /* National Semiconductor DP83847: */ -+ case MII_DP83848_ID: /* National Semiconductor DP83848: */ - case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ - case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ -+ case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */ -+ case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */ - detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk); - break; - } -diff -urN -x CVS linux-2.6.21/drivers/net/arm/at91_ether.h linux-2.6-stable/drivers/net/arm/at91_ether.h ---- linux-2.6.21/drivers/net/arm/at91_ether.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/net/arm/at91_ether.h Tue May 8 12:13:31 2007 -@@ -17,39 +17,46 @@ - - - /* Davicom 9161 PHY */ --#define MII_DM9161_ID 0x0181b880 --#define MII_DM9161A_ID 0x0181b8a0 -- --/* Davicom specific registers */ --#define MII_DSCR_REG 16 --#define MII_DSCSR_REG 17 --#define MII_DSINTR_REG 21 -+#define MII_DM9161_ID 0x0181b880 -+#define MII_DM9161A_ID 0x0181b8a0 -+#define MII_DSCR_REG 16 -+#define MII_DSCSR_REG 17 -+#define MII_DSINTR_REG 21 - - /* Intel LXT971A PHY */ --#define MII_LXT971A_ID 0x001378E0 -- --/* Intel specific registers */ --#define MII_ISINTE_REG 18 --#define MII_ISINTS_REG 19 --#define MII_LEDCTRL_REG 20 -+#define MII_LXT971A_ID 0x001378E0 -+#define MII_ISINTE_REG 18 -+#define MII_ISINTS_REG 19 -+#define MII_LEDCTRL_REG 20 - - /* Realtek RTL8201 PHY */ --#define MII_RTL8201_ID 0x00008200 -+#define MII_RTL8201_ID 0x00008200 - - /* Broadcom BCM5221 PHY */ --#define MII_BCM5221_ID 0x004061e0 -- --/* Broadcom specific registers */ --#define MII_BCMINTR_REG 26 -+#define MII_BCM5221_ID 0x004061e0 -+#define MII_BCMINTR_REG 26 - - /* National Semiconductor DP83847 */ --#define MII_DP83847_ID 0x20005c30 -+#define MII_DP83847_ID 0x20005c30 -+ -+/* National Semiconductor DP83848 */ -+#define MII_DP83848_ID 0x20005c90 -+#define MII_DPPHYSTS_REG 16 -+#define MII_DPMICR_REG 17 -+#define MII_DPMISR_REG 18 - - /* Altima AC101L PHY */ --#define MII_AC101L_ID 0x00225520 -+#define MII_AC101L_ID 0x00225520 - - /* Micrel KS8721 PHY */ --#define MII_KS8721_ID 0x00221610 -+#define MII_KS8721_ID 0x00221610 -+ -+/* Teridian 78Q2123/78Q2133 */ -+#define MII_T78Q21x3_ID 0x000e7230 -+#define MII_T78Q21INT_REG 17 -+ -+/* SMSC LAN83C185 */ -+#define MII_LAN83C185_ID 0x0007C0A0 - - /* ........................................................................ */ - -diff -urN -x CVS linux-2.6.21/drivers/pcmcia/at91_cf.c linux-2.6-stable/drivers/pcmcia/at91_cf.c ---- linux-2.6.21/drivers/pcmcia/at91_cf.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/pcmcia/at91_cf.c Tue May 8 12:13:31 2007 -@@ -332,20 +332,27 @@ - struct at91_cf_data *board = cf->board; - - pcmcia_socket_dev_suspend(&pdev->dev, mesg); -+ - if (device_may_wakeup(&pdev->dev)) { - enable_irq_wake(board->det_pin); - if (board->irq_pin) - enable_irq_wake(board->irq_pin); -- } else { -- disable_irq_wake(board->det_pin); -- if (board->irq_pin) -- disable_irq_wake(board->irq_pin); - } -+ - return 0; - } - - static int at91_cf_resume(struct platform_device *pdev) - { -+ struct at91_cf_socket *cf = platform_get_drvdata(pdev); -+ struct at91_cf_data *board = cf->board; -+ -+ if (device_may_wakeup(&pdev->dev)) { -+ disable_irq_wake(board->det_pin); -+ if (board->irq_pin) -+ disable_irq_wake(board->irq_pin); -+ } -+ - pcmcia_socket_dev_resume(&pdev->dev); - return 0; - } -@@ -360,7 +367,6 @@ - .name = (char *) driver_name, - .owner = THIS_MODULE, - }, -- .probe = at91_cf_probe, - .remove = __exit_p(at91_cf_remove), - .suspend = at91_cf_suspend, - .resume = at91_cf_resume, -@@ -370,7 +376,7 @@ - - static int __init at91_cf_init(void) - { -- return platform_driver_register(&at91_cf_driver); -+ return platform_driver_probe(&at91_cf_driver, at91_cf_probe); - } - module_init(at91_cf_init); - -diff -urN -x CVS linux-2.6.21/drivers/serial/atmel_serial.c linux-2.6-stable/drivers/serial/atmel_serial.c ---- linux-2.6.21/drivers/serial/atmel_serial.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/serial/atmel_serial.c Tue May 8 12:13:31 2007 -@@ -7,6 +7,8 @@ - * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. - * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. - * -+ * DMA support added by Chip Coldwell. -+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or -@@ -33,6 +35,7 @@ - #include <linux/sysrq.h> - #include <linux/tty_flip.h> - #include <linux/platform_device.h> -+#include <linux/dma-mapping.h> - #include <linux/atmel_pdc.h> - - #include <asm/io.h> -@@ -47,6 +50,11 @@ - - #include "atmel_serial.h" - -+#define SUPPORT_PDC -+#define PDC_BUFFER_SIZE (L1_CACHE_BYTES << 3) -+#warning "Revisit" -+#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ -+ - #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) - #define SUPPORT_SYSRQ - #endif -@@ -107,6 +115,13 @@ - static int (*atmel_open_hook)(struct uart_port *); - static void (*atmel_close_hook)(struct uart_port *); - -+struct atmel_dma_buffer { -+ unsigned char *buf; -+ dma_addr_t dma_addr; -+ size_t dma_size; -+ unsigned int ofs; -+}; -+ - /* - * We wrap our port structure around the generic uart_port. - */ -@@ -114,10 +129,20 @@ - struct uart_port uart; /* uart */ - struct clk *clk; /* uart clock */ - unsigned short suspended; /* is port suspended? */ -+ -+ short use_dma_rx; /* enable PDC receiver */ -+ short pdc_rx_idx; /* current PDC RX buffer */ -+ struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ -+ -+ short use_dma_tx; /* enable PDC transmitter */ -+ struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ - }; - - static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; - -+#define PDC_RX_BUF(port) &(port)->pdc_rx[(port)->pdc_rx_idx] -+#define PDC_RX_SWITCH(port) (port)->pdc_rx_idx = !(port)->pdc_rx_idx -+ - #ifdef SUPPORT_SYSRQ - static struct console atmel_console; - #endif -@@ -205,7 +230,12 @@ - { - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - -- UART_PUT_IDR(port, ATMEL_US_TXRDY); -+ if (atmel_port->use_dma_tx) { -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); /* disable PDC transmit */ -+ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); -+ } -+ else -+ UART_PUT_IDR(port, ATMEL_US_TXRDY); - } - - /* -@@ -215,7 +245,17 @@ - { - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - -- UART_PUT_IER(port, ATMEL_US_TXRDY); -+ if (atmel_port->use_dma_tx) { -+ if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) -+ /* The transmitter is already running. Yes, we -+ really need this.*/ -+ return; -+ -+ UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); /* re-enable PDC transmit */ -+ } -+ else -+ UART_PUT_IER(port, ATMEL_US_TXRDY); - } - - /* -@@ -225,7 +265,12 @@ - { - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - -- UART_PUT_IDR(port, ATMEL_US_RXRDY); -+ if (atmel_port->use_dma_rx) { -+ UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); /* disable PDC receive */ -+ UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); -+ } -+ else -+ UART_PUT_IDR(port, ATMEL_US_RXRDY); - } - - /* -@@ -248,6 +293,134 @@ - } - - /* -+ * Receive data via the PDC. A buffer has been fulled. -+ */ -+static void atmel_pdc_endrx(struct uart_port *port) -+{ -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; -+ struct tty_struct *tty = port->info->tty; -+ struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port); -+ unsigned int count; -+ -+ count = pdc->dma_size - pdc->ofs; -+ if (likely(count > 0)) { -+ dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE); -+ tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count); -+ tty_flip_buffer_push(tty); -+ -+ port->icount.rx += count; -+ } -+ -+ /* Set this buffer as the next receive buffer */ -+ pdc->ofs = 0; -+ UART_PUT_RNPR(port, pdc->dma_addr); -+ UART_PUT_RNCR(port, pdc->dma_size); -+ -+ /* Switch to next buffer */ -+ PDC_RX_SWITCH(atmel_port); /* next PDC buffer */ -+} -+ -+/* -+ * Receive data via the PDC. At least one byte was received, but the -+ * buffer was not full when the inter-character timeout expired. -+ */ -+static void atmel_pdc_timeout(struct uart_port *port) -+{ -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; -+ struct tty_struct *tty = port->info->tty; -+ struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port); -+ /* unsigned */ int ofs, count; -+ -+ ofs = UART_GET_RPR(port) - pdc->dma_addr; /* current DMA adress */ -+ count = ofs - pdc->ofs; -+ -+ if (likely(count > 0)) { -+ dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE); -+ tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count); -+ tty_flip_buffer_push(tty); -+ -+ pdc->ofs = ofs; -+ port->icount.rx += count; -+ } -+ -+ /* reset the UART timeout */ -+ UART_PUT_CR(port, ATMEL_US_STTTO); -+} -+ -+/* -+ * Deal with parity, framing and overrun errors. -+ */ -+static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) -+{ -+ /* clear error */ -+ UART_PUT_CR(port, ATMEL_US_RSTSTA); -+ -+ if (status & ATMEL_US_RXBRK) { -+ status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */ -+ port->icount.brk++; -+ } -+ if (status & ATMEL_US_PARE) -+ port->icount.parity++; -+ if (status & ATMEL_US_FRAME) -+ port->icount.frame++; -+ if (status & ATMEL_US_OVRE) -+ port->icount.overrun++; -+} -+ -+/* -+ * A transmission via the PDC is complete. -+ */ -+static void atmel_pdc_endtx(struct uart_port *port) -+{ -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; -+ struct circ_buf *xmit = &port->info->xmit; -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; -+ -+ xmit->tail += pdc->ofs; -+ if (xmit->tail >= SERIAL_XMIT_SIZE) -+ xmit->tail -= SERIAL_XMIT_SIZE; -+ -+ port->icount.tx += pdc->ofs; -+ pdc->ofs = 0; -+ -+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) -+ uart_write_wakeup(port); -+} -+ -+/* -+ * The PDC transmitter is idle, so either start the next transfer or -+ * disable the transmitter. -+ */ -+static void atmel_pdc_txbufe(struct uart_port *port) -+{ -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; -+ struct circ_buf *xmit = &port->info->xmit; -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; -+ int count; -+ -+ if (!uart_circ_empty(xmit)) { -+ /* more to transmit - setup next transfer */ -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); /* disable PDC transmit */ -+ dma_sync_single_for_device(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE); -+ -+ if (xmit->tail < xmit->head) -+ count = xmit->head - xmit->tail; -+ else -+ count = SERIAL_XMIT_SIZE - xmit->tail; -+ pdc->ofs = count; -+ -+ UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); -+ UART_PUT_TCR(port, count); -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); /* re-enable PDC transmit */ -+ } -+ else { -+ /* nothing left to transmit - disable the transmitter */ -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); /* disable PDC transmit */ -+ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); -+ } -+} -+ -+/* - * Characters received (called from interrupt handler) - */ - static void atmel_rx_chars(struct uart_port *port) -@@ -349,6 +522,14 @@ - status = UART_GET_CSR(port); - pending = status & UART_GET_IMR(port); - while (pending) { -+ /* PDC receive */ -+ if (pending & ATMEL_US_ENDRX) -+ atmel_pdc_endrx(port); -+ if (pending & ATMEL_US_TIMEOUT) -+ atmel_pdc_timeout(port); -+ if (atmel_port->use_dma_rx && pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | ATMEL_US_FRAME | ATMEL_US_PARE)) -+ atmel_pdc_rxerr(port, pending); -+ - /* Interrupt receive */ - if (pending & ATMEL_US_RXRDY) - atmel_rx_chars(port); -@@ -363,6 +544,12 @@ - if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC)) - wake_up_interruptible(&port->info->delta_msr_wait); - -+ /* PDC transmit */ -+ if (pending & ATMEL_US_ENDTX) -+ atmel_pdc_endtx(port); -+ if (pending & ATMEL_US_TXBUFE) -+ atmel_pdc_txbufe(port); -+ - /* Interrupt transmit */ - if (pending & ATMEL_US_TXRDY) - atmel_tx_chars(port); -@@ -401,6 +588,47 @@ - } - - /* -+ * Initialize DMA (if necessary) -+ */ -+ if (atmel_port->use_dma_rx) { -+ int i; -+ -+ for (i = 0; i < 2; i++) { -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; -+ -+ pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); -+ if (pdc->buf == NULL) { -+ if (i != 0) { -+ dma_unmap_single(port->dev, atmel_port->pdc_rx[0].dma_addr, PDC_BUFFER_SIZE, DMA_FROM_DEVICE); -+ kfree(atmel_port->pdc_rx[0].buf); -+ } -+ free_irq(port->irq, port); -+ return -ENOMEM; -+ } -+ pdc->dma_addr = dma_map_single(port->dev, pdc->buf, PDC_BUFFER_SIZE, DMA_FROM_DEVICE); -+ pdc->dma_size = PDC_BUFFER_SIZE; -+ pdc->ofs = 0; -+ } -+ -+ atmel_port->pdc_rx_idx = 0; -+ -+ UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); -+ UART_PUT_RCR(port, PDC_BUFFER_SIZE); -+ -+ UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); -+ UART_PUT_RNCR(port, PDC_BUFFER_SIZE); -+ } -+ if (atmel_port->use_dma_tx) { -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; -+ struct circ_buf *xmit = &port->info->xmit; -+ -+ pdc->buf = xmit->buf; -+ pdc->dma_addr = dma_map_single(port->dev, pdc->buf, SERIAL_XMIT_SIZE, DMA_TO_DEVICE); -+ pdc->dma_size = SERIAL_XMIT_SIZE; -+ pdc->ofs = 0; -+ } -+ -+ /* - * If there is a specific "open" function (to register - * control line interrupts) - */ -@@ -418,7 +646,15 @@ - UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); - UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */ - -- UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */ -+ if (atmel_port->use_dma_rx) { -+ UART_PUT_RTOR(port, PDC_RX_TIMEOUT); /* set UART timeout */ -+ UART_PUT_CR(port, ATMEL_US_STTTO); -+ -+ UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); -+ UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); /* enable PDC controller */ -+ } -+ else -+ UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */ - - return 0; - } -@@ -431,6 +667,31 @@ - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - - /* -+ * Ensure everything is stopped. -+ */ -+ atmel_stop_rx(port); -+ atmel_stop_tx(port); -+ -+ /* -+ * Shut-down the DMA. -+ */ -+ if (atmel_port->use_dma_rx) { -+ int i; -+ -+ for (i = 0; i < 2; i++) { -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; -+ -+ dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE); -+ kfree(pdc->buf); -+ } -+ } -+ if (atmel_port->use_dma_tx) { -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; -+ -+ dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE); -+ } -+ -+ /* - * Disable all interrupts, port and break condition. - */ - UART_PUT_CR(port, ATMEL_US_RSTSTA); -@@ -481,14 +742,20 @@ - */ - static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old) - { -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - unsigned long flags; - unsigned int mode, imr, quot, baud; - -+ /* Get current mode register */ -+ mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR); -+ - baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); - quot = uart_get_divisor(port, baud); - -- /* Get current mode register */ -- mode = UART_GET_MR(port) & ~(ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR); -+ if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ -+ quot /= 8; -+ mode |= ATMEL_US_USCLKS_MCK_DIV8; -+ } - - /* byte size */ - switch (termios->c_cflag & CSIZE) { -@@ -534,6 +801,9 @@ - if (termios->c_iflag & (BRKINT | PARMRK)) - port->read_status_mask |= ATMEL_US_RXBRK; - -+ if (atmel_port->use_dma_rx) /* need to enable error interrupts */ -+ UART_PUT_IER(port, port->read_status_mask); -+ - /* - * Characters to ignore - */ -@@ -712,6 +982,13 @@ - clk_enable(atmel_port->clk); - port->uartclk = clk_get_rate(atmel_port->clk); - } -+ -+#ifdef SUPPORT_PDC -+ atmel_port->use_dma_rx = data->use_dma_rx; -+ atmel_port->use_dma_tx = data->use_dma_tx; -+ if (atmel_port->use_dma_tx) -+ port->fifosize = PDC_BUFFER_SIZE; -+#endif - } - - /* -@@ -888,7 +1165,8 @@ - struct uart_port *port = platform_get_drvdata(pdev); - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - -- if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock()) -+ if (device_may_wakeup(&pdev->dev) -+ && !clk_must_disable(atmel_port->clk)) - enable_irq_wake(port->irq); - else { - uart_suspend_port(&atmel_uart, port); -diff -urN -x CVS linux-2.6.21/drivers/serial/atmel_serial.h linux-2.6-stable/drivers/serial/atmel_serial.h ---- linux-2.6.21/drivers/serial/atmel_serial.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/serial/atmel_serial.h Tue May 8 12:13:31 2007 -@@ -46,6 +46,9 @@ - #define ATMEL_US_USMODE_ISO7816_T1 6 - #define ATMEL_US_USMODE_IRDA 8 - #define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */ -+#define ATMEL_US_USCLKS_MCK (0 << 4) -+#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) -+#define ATMEL_US_USCLKS_SCK (3 << 4) - #define ATMEL_US_CHRL (3 << 6) /* Character Length */ - #define ATMEL_US_CHRL_5 (0 << 6) - #define ATMEL_US_CHRL_6 (1 << 6) -diff -urN -x CVS linux-2.6.21/drivers/spi/Kconfig linux-2.6-stable/drivers/spi/Kconfig ---- linux-2.6.21/drivers/spi/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/spi/Kconfig Tue May 8 14:31:24 2007 -@@ -54,6 +54,7 @@ - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) && SPI_MASTER -+ select SPI_AT91_MANUAL_CS if ARCH_AT91RM9200 - help - This selects a driver for the Atmel SPI Controller, present on - many AT32 (AVR32) and AT91 (ARM) chips. -@@ -82,6 +83,24 @@ - inexpensive battery powered microcontroller evaluation board. - This same cable can be used to flash new firmware. - -+config SPI_AT91 -+ tristate "AT91RM9200 Bitbang SPI Master" -+ depends on SPI_MASTER && ARCH_AT91RM9200 && !SPI_ATMEL && EXPERIMENTAL -+ select SPI_BITBANG -+ select SPI_AT91_MANUAL_CS -+ help -+ This is dumb PIO bitbanging driver for the Atmel AT91RM9200. -+ The SPI_ATMEL driver will be its replacement, using the native -+ SPI hardware and its DMA controller. -+ -+config SPI_AT91_MANUAL_CS -+ bool -+ depends on ARCH_AT91RM9200 -+ help -+ Works around an AT91RM9200 problem whereby the SPI chip-select -+ will be wrongly disabled. The workaround uses those pins as -+ GPIOs instead of letting the SPI controller manage them. -+ - config SPI_IMX - tristate "Freescale iMX SPI controller" - depends on SPI_MASTER && ARCH_IMX && EXPERIMENTAL -diff -urN -x CVS linux-2.6.21/drivers/spi/Makefile linux-2.6-stable/drivers/spi/Makefile ---- linux-2.6.21/drivers/spi/Makefile Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/spi/Makefile Tue May 8 14:31:24 2007 -@@ -20,6 +20,7 @@ - obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o - obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o - obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o -+obj-$(CONFIG_SPI_AT91) += spi_at91_bitbang.o - # ... add above this line ... - - # SPI protocol drivers (device/link on bus) -diff -urN -x CVS linux-2.6.21/drivers/spi/spi_at91_bitbang.c linux-2.6-stable/drivers/spi/spi_at91_bitbang.c ---- linux-2.6.21/drivers/spi/spi_at91_bitbang.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/drivers/spi/spi_at91_bitbang.c Tue May 8 14:31:24 2007 -@@ -0,0 +1,207 @@ -+/* -+ * at91_spi.c - at91 SPI driver (BOOTSTRAP/BITBANG VERSION) -+ * -+ * Copyright (C) 2006 David Brownell -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+#include <linux/kernel.h> -+#include <linux/init.h> -+#include <linux/platform_device.h> -+ -+#include <linux/spi/spi.h> -+#include <linux/spi/spi_bitbang.h> -+ -+#include <asm/arch/gpio.h> -+ -+ -+/* -+ * FIXME this bitbanging version is just to help bootstrap systems until -+ * there's a native SPI+IRQ+DMA controller driver ... such a driver should -+ * be a drop-in replacement for this one, and much faster. -+ * -+ * remember: -+ * -+ * - other at91 parts (like at91sam9) have multiple controllers -+ * and different pin muxing; this version is at91rm9200 specfic. -+ * -+ * - at91sam9261 SPI0 pins are directly muxed with MMC/SD pins. -+ * -+ * - rm9200 spi chipselects drop wrongly, so the native driver -+ * will need to use gpios much like this does. -+ * -+ * - real hardware only allows 8..16 bits per word, while this -+ * bitbanger allows 1..32 (incompatible superset). -+ * -+ * - this disregards clock parameters. with inlined gpio calls, -+ * gcc 3.4.4 produces about 1.5 mbit/sec, more than 2x faster -+ * than using the subroutined veresion from txrx_word(). -+ * -+ * - suspend/resume and <linux/clk.h> support is missing ... -+ */ -+ -+#define spi_miso_bit AT91_PIN_PA0 -+#define spi_mosi_bit AT91_PIN_PA1 -+#define spi_sck_bit AT91_PIN_PA2 -+ -+struct at91_spi { -+ struct spi_bitbang bitbang; -+ struct platform_device *pdev; -+}; -+ -+/*----------------------------------------------------------------------*/ -+ -+static inline void setsck(struct spi_device *spi, int is_on) -+{ -+ at91_set_gpio_value(spi_sck_bit, is_on); -+} -+ -+static inline void setmosi(struct spi_device *spi, int is_on) -+{ -+ at91_set_gpio_value(spi_mosi_bit, is_on); -+} -+ -+static inline int getmiso(struct spi_device *spi) -+{ -+ return at91_get_gpio_value(spi_miso_bit); -+} -+ -+static void at91_spi_chipselect(struct spi_device *spi, int is_active) -+{ -+ unsigned long cs = (unsigned long) spi->controller_data; -+ -+ /* set default clock polarity */ -+ if (is_active) -+ setsck(spi, spi->mode & SPI_CPOL); -+ -+ /* only support active-low (default) */ -+ at91_set_gpio_value(cs, !is_active); -+} -+ -+/* -+ * NOTE: this is "as fast as we can"; it should be a function of -+ * the device clock ... -+ */ -+#define spidelay(X) do{} while(0) -+ -+#define EXPAND_BITBANG_TXRX -+#include <linux/spi/spi_bitbang.h> -+ -+static u32 at91_spi_txrx_word_mode0(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, 8); -+} -+ -+static u32 at91_spi_txrx_word_mode1(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, 8); -+} -+ -+static u32 at91_spi_txrx_word_mode2(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, 8); -+} -+ -+static u32 at91_spi_txrx_word_mode3(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, 8); -+} -+ -+/*----------------------------------------------------------------------*/ -+ -+static int __init at91_spi_probe(struct platform_device *pdev) -+{ -+ int status; -+ struct spi_master *master; -+ struct at91_spi *at91_spi; -+ -+ if (pdev->id != 0) /* SPI0 bus */ -+ return -EINVAL; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof *at91_spi); -+ if (!master) -+ return -ENOMEM; -+ -+ at91_spi = spi_master_get_devdata(master); -+ at91_spi->pdev = pdev; -+ platform_set_drvdata(pdev, at91_spi); -+ -+ /* SPI and bitbang hookup */ -+ master->bus_num = 0; -+ master->num_chipselect = 4; -+ -+ at91_spi->bitbang.master = spi_master_get(master); -+ at91_spi->bitbang.chipselect = at91_spi_chipselect; -+ at91_spi->bitbang.txrx_word[SPI_MODE_0] = at91_spi_txrx_word_mode0; -+ at91_spi->bitbang.txrx_word[SPI_MODE_1] = at91_spi_txrx_word_mode1; -+ at91_spi->bitbang.txrx_word[SPI_MODE_2] = at91_spi_txrx_word_mode2; -+ at91_spi->bitbang.txrx_word[SPI_MODE_3] = at91_spi_txrx_word_mode3; -+ -+ status = spi_bitbang_start(&at91_spi->bitbang); -+ if (status < 0) -+ (void) spi_master_put(at91_spi->bitbang.master); -+ -+ return status; -+} -+ -+static int __exit at91_spi_remove(struct platform_device *pdev) -+{ -+ struct at91_spi *at91_spi = platform_get_drvdata(pdev); -+ int status; -+ -+ /* stop() unregisters child devices too */ -+ status = spi_bitbang_stop(&at91_spi->bitbang); -+ (void) spi_master_put(at91_spi->bitbang.master); -+ -+ platform_set_drvdata(pdev, NULL); -+ return status; -+} -+ -+static struct platform_driver at91_spi_driver = { -+ .probe = at91_spi_probe, -+ .remove = __exit_p(at91_spi_remove), -+ .driver = { -+ .name = "at91_spi", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init at91_spi_init(void) -+{ -+ at91_set_gpio_output(spi_sck_bit, 0); -+ at91_set_gpio_output(spi_mosi_bit, 0); -+ at91_set_gpio_input(spi_miso_bit, 1 /* pullup */); -+ -+ /* register driver */ -+ return platform_driver_register(&at91_spi_driver); -+} -+ -+static void __exit at91_spi_exit(void) -+{ -+ platform_driver_unregister(&at91_spi_driver); -+} -+ -+device_initcall(at91_spi_init); -+module_exit(at91_spi_exit); -+ -+MODULE_ALIAS("at91_spi.0"); -+ -+MODULE_DESCRIPTION("AT91 SPI support (BOOTSTRAP/BITBANG VERSION)"); -+MODULE_AUTHOR("David Brownell"); -+MODULE_LICENSE("GPL"); -diff -urN -x CVS linux-2.6.21/drivers/usb/gadget/Kconfig linux-2.6-stable/drivers/usb/gadget/Kconfig ---- linux-2.6.21/drivers/usb/gadget/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/usb/gadget/Kconfig Wed May 9 10:20:54 2007 -@@ -189,7 +189,7 @@ - - config USB_GADGET_AT91 - boolean "AT91 USB Device Port" -- depends on ARCH_AT91 -+ depends on ARCH_AT91 && !ARCH_AT91SAM9RL - select USB_GADGET_SELECTED - help - Many Atmel AT91 processors (such as the AT91RM2000) have a -diff -urN -x CVS linux-2.6.21/drivers/usb/gadget/at91_udc.c linux-2.6-stable/drivers/usb/gadget/at91_udc.c ---- linux-2.6.21/drivers/usb/gadget/at91_udc.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/usb/gadget/at91_udc.c Tue May 8 12:13:31 2007 -@@ -1804,7 +1804,7 @@ - */ - if ((!udc->suspended && udc->addr) - || !wake -- || at91_suspend_entering_slow_clock()) { -+ || clk_must_disable(udc->fclk)) { - pullup(udc, 0); - wake = 0; - } else -diff -urN -x CVS linux-2.6.21/drivers/usb/host/ohci-at91.c linux-2.6-stable/drivers/usb/host/ohci-at91.c ---- linux-2.6.21/drivers/usb/host/ohci-at91.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/usb/host/ohci-at91.c Tue May 8 12:13:31 2007 -@@ -299,7 +299,7 @@ - * - * REVISIT: some boards will be able to turn VBUS off... - */ -- if (at91_suspend_entering_slow_clock()) { -+ if (clk_must_disable(fclk)) { - ohci_usb_reset (ohci); - at91_stop_clock(); - } -diff -urN -x CVS linux-2.6.21/drivers/video/Kconfig linux-2.6-stable/drivers/video/Kconfig ---- linux-2.6.21/drivers/video/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/video/Kconfig Thu May 10 12:34:41 2007 -@@ -663,6 +663,17 @@ - framebuffer. Product specs at - <http://www.erd.epson.com/vdc/html/products.htm>. - -+config FB_S1D15605 -+ tristate "Epson S1D15605 framebuffer support" -+ depends on FB -+ default m if MACH_KB9200 -+ select FB_CFB_FILLRECT -+ select FB_CFB_COPYAREA -+ select FB_CFB_IMAGEBLIT -+ help -+ Build in support for the S1D15605 Epson Research 128x64 -+ LCD controller as a framebuffer. -+ - config FB_S1D13XXX - tristate "Epson S1D13XXX framebuffer support" - depends on FB -@@ -674,6 +685,22 @@ - working with S1D13806). Product specs at - <http://www.erd.epson.com/vdc/html/legacy_13xxx.htm> - -+config FB_ATMEL -+ tristate "AT91/AT32 LCD Controller support" -+ depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || AVR32) -+ select FB_CFB_FILLRECT -+ select FB_CFB_COPYAREA -+ select FB_CFB_IMAGEBLIT -+ help -+ This enables support for the AT91/AT32 LCD Controller. -+ -+config FB_INTSRAM -+ bool "Frame Buffer in internal SRAM" -+ depends on FB_ATMEL && ARCH_AT91SAM9261 -+ help -+ Say Y if you want to map Frame Buffer in internal SRAM. Say N if you want -+ to let frame buffer in external SDRAM. -+ - config FB_NVIDIA - tristate "nVidia Framebuffer Support" - depends on FB && PCI -diff -urN -x CVS linux-2.6.21/drivers/video/Makefile linux-2.6-stable/drivers/video/Makefile ---- linux-2.6.21/drivers/video/Makefile Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/video/Makefile Thu May 10 12:34:01 2007 -@@ -75,6 +75,8 @@ - obj-$(CONFIG_FB_SA1100) += sa1100fb.o - obj-$(CONFIG_FB_HIT) += hitfb.o - obj-$(CONFIG_FB_EPSON1355) += epson1355fb.o -+obj-$(CONFIG_FB_S1D15605) += s1d15605fb.o -+obj-$(CONFIG_FB_ATMEL) += atmel_lcdfb.o - obj-$(CONFIG_FB_PVR2) += pvr2fb.o - obj-$(CONFIG_FB_VOODOO1) += sstfb.o - obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o -diff -urN -x CVS linux-2.6.21/drivers/video/atmel_lcdfb.c linux-2.6-stable/drivers/video/atmel_lcdfb.c ---- linux-2.6.21/drivers/video/atmel_lcdfb.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/drivers/video/atmel_lcdfb.c Thu May 10 12:34:01 2007 -@@ -0,0 +1,752 @@ -+/* -+ * Driver for AT91/AT32 LCD Controller -+ * -+ * Copyright (C) 2007 Atmel Corporation -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive for -+ * more details. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/platform_device.h> -+#include <linux/dma-mapping.h> -+#include <linux/interrupt.h> -+#include <linux/clk.h> -+#include <linux/fb.h> -+#include <linux/init.h> -+#include <linux/delay.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/cpu.h> -+#include <asm/arch/gpio.h> -+ -+#include <video/atmel_lcdc.h> -+ -+#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg)) -+#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg)) -+ -+/* configurable parameters */ -+#define ATMEL_LCDC_CVAL_DEFAULT 0xc8 -+#define ATMEL_LCDC_DMA_BURST_LEN 8 -+ -+#if defined(CONFIG_ARCH_AT91SAM9263) -+#define ATMEL_LCDC_FIFO_SIZE 2048 -+#else -+#define ATMEL_LCDC_FIFO_SIZE 512 -+#endif -+ -+#if defined(CONFIG_ARCH_AT91) -+#define ATMEL_LCDFB_FBINFO_DEFAULT FBINFO_DEFAULT -+ -+static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo, -+ struct fb_var_screeninfo *var) -+{ -+ -+} -+#elif defined(CONFIG_AVR32) -+#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \ -+ | FBINFO_PARTIAL_PAN_OK \ -+ | FBINFO_HWACCEL_XPAN \ -+ | FBINFO_HWACCEL_YPAN) -+ -+static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo, -+ struct fb_var_screeninfo *var) -+{ -+ u32 dma2dcfg; -+ u32 pixeloff; -+ -+ pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f; -+ -+ dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8; -+ dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET; -+ lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg); -+ -+ /* Update configuration */ -+ lcdc_writel(sinfo, ATMEL_LCDC_DMACON, -+ lcdc_readl(sinfo, ATMEL_LCDC_DMACON) -+ | ATMEL_LCDC_DMAUPDT); -+} -+#endif -+ -+ -+static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = { -+ .type = FB_TYPE_PACKED_PIXELS, -+ .visual = FB_VISUAL_TRUECOLOR, -+ .xpanstep = 0, -+ .ypanstep = 0, -+ .ywrapstep = 0, -+ .accel = FB_ACCEL_NONE, -+}; -+ -+ -+static void atmel_lcdfb_update_dma(struct fb_info *info, -+ struct fb_var_screeninfo *var) -+{ -+ struct atmel_lcdfb_info *sinfo = info->par; -+ struct fb_fix_screeninfo *fix = &info->fix; -+ unsigned long dma_addr; -+ -+ dma_addr = (fix->smem_start + var->yoffset * fix->line_length -+ + var->xoffset * var->bits_per_pixel / 8); -+ -+ dma_addr &= ~3UL; -+ -+ /* Set framebuffer DMA base address and pixel offset */ -+ lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr); -+ -+ atmel_lcdfb_update_dma2d(sinfo, var); -+} -+ -+static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo) -+{ -+ struct fb_info *info = sinfo->info; -+ -+ dma_free_writecombine(info->device, info->fix.smem_len, -+ info->screen_base, info->fix.smem_start); -+} -+ -+/** -+ * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory -+ * @sinfo: the frame buffer to allocate memory for -+ */ -+static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo) -+{ -+ struct fb_info *info = sinfo->info; -+ struct fb_var_screeninfo *var = &info->var; -+ -+ info->fix.smem_len = (var->xres_virtual * var->yres_virtual -+ * ((var->bits_per_pixel + 7) / 8)); -+ -+ info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len, -+ (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL); -+ -+ if (!info->screen_base) { -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+/** -+ * atmel_lcdfb_check_var - Validates a var passed in. -+ * @var: frame buffer variable screen structure -+ * @info: frame buffer structure that represents a single frame buffer -+ * -+ * Checks to see if the hardware supports the state requested by -+ * var passed in. This function does not alter the hardware -+ * state!!! This means the data stored in struct fb_info and -+ * struct atmel_lcdfb_info do not change. This includes the var -+ * inside of struct fb_info. Do NOT change these. This function -+ * can be called on its own if we intent to only test a mode and -+ * not actually set it. The stuff in modedb.c is a example of -+ * this. If the var passed in is slightly off by what the -+ * hardware can support then we alter the var PASSED in to what -+ * we can do. If the hardware doesn't support mode change a -+ * -EINVAL will be returned by the upper layers. You don't need -+ * to implement this function then. If you hardware doesn't -+ * support changing the resolution then this function is not -+ * needed. In this case the driver would just provide a var that -+ * represents the static state the screen is in. -+ * -+ * Returns negative errno on error, or zero on success. -+ */ -+static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, -+ struct fb_info *info) -+{ -+ struct device *dev = info->device; -+ struct atmel_lcdfb_info *sinfo = info->par; -+ unsigned long clk_value_khz; -+ -+ clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; -+ -+ dev_dbg(dev, "%s:\n", __func__); -+ dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres); -+ dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock)); -+ dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel); -+ dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz); -+ -+ if ((PICOS2KHZ(var->pixclock) * var->bits_per_pixel / 8) > clk_value_khz) { -+ dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock)); -+ return -EINVAL; -+ } -+ -+ /* Force same alignment for each line */ -+ var->xres = (var->xres + 3) & ~3UL; -+ var->xres_virtual = (var->xres_virtual + 3) & ~3UL; -+ -+ var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0; -+ var->transp.msb_right = 0; -+ var->transp.offset = var->transp.length = 0; -+ var->xoffset = var->yoffset = 0; -+ -+ switch (var->bits_per_pixel) { -+ case 2: -+ case 4: -+ case 8: -+ var->red.offset = var->green.offset = var->blue.offset = 0; -+ var->red.length = var->green.length = var->blue.length -+ = var->bits_per_pixel; -+ break; -+ case 15: -+ case 16: -+ var->red.offset = 0; -+ var->green.offset = 5; -+ var->blue.offset = 10; -+ var->red.length = var->green.length = var->blue.length = 5; -+ break; -+ case 24: -+ case 32: -+ var->red.offset = 0; -+ var->green.offset = 8; -+ var->blue.offset = 16; -+ var->red.length = var->green.length = var->blue.length = 8; -+ break; -+ default: -+ dev_err(dev, "color depth %d not supported\n", -+ var->bits_per_pixel); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/** -+ * atmel_lcdfb_set_par - Alters the hardware state. -+ * @info: frame buffer structure that represents a single frame buffer -+ * -+ * Using the fb_var_screeninfo in fb_info we set the resolution -+ * of the this particular framebuffer. This function alters the -+ * par AND the fb_fix_screeninfo stored in fb_info. It doesn't -+ * not alter var in fb_info since we are using that data. This -+ * means we depend on the data in var inside fb_info to be -+ * supported by the hardware. atmel_lcdfb_check_var is always called -+ * before atmel_lcdfb_set_par to ensure this. Again if you can't -+ * change the resolution you don't need this function. -+ * -+ */ -+static int atmel_lcdfb_set_par(struct fb_info *info) -+{ -+ struct atmel_lcdfb_info *sinfo = info->par; -+ unsigned long value; -+ unsigned long clk_value_khz; -+ -+ dev_dbg(info->device, "%s:\n", __func__); -+ dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n", -+ info->var.xres, info->var.yres, -+ info->var.xres_virtual, info->var.yres_virtual); -+ -+ /* Turn off the LCD controller and the DMA controller */ -+ lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET); -+ -+ lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0); -+ -+ if (info->var.bits_per_pixel <= 8) -+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR; -+ else -+ info->fix.visual = FB_VISUAL_TRUECOLOR; -+ -+ info->fix.line_length = info->var.xres_virtual * (info->var.bits_per_pixel / 8); -+ -+ /* Re-initialize the DMA engine... */ -+ dev_dbg(info->device, " * update DMA engine\n"); -+ atmel_lcdfb_update_dma(info, &info->var); -+ -+ /* ...set frame size and burst length = 8 words (?) */ -+ value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32; -+ value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET); -+ lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value); -+ -+ /* Now, the LCDC core... */ -+ -+ /* Set pixel clock */ -+ clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; -+ -+ value = clk_value_khz / PICOS2KHZ(info->var.pixclock); -+ -+ if (clk_value_khz % PICOS2KHZ(info->var.pixclock)) -+ value++; -+ -+ value = (value / 2) - 1; -+ -+ if (value <= 0) { -+ dev_notice(info->device, "Bypassing pixel clock divider\n"); -+ lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); -+ } else -+ lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET); -+ -+ /* Initialize control register 2 */ -+ value = sinfo->default_lcdcon2; -+ -+ if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) -+ value |= ATMEL_LCDC_INVLINE_INVERTED; -+ if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) -+ value |= ATMEL_LCDC_INVFRAME_INVERTED; -+ -+ switch (info->var.bits_per_pixel) { -+ case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break; -+ case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break; -+ case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break; -+ case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break; -+ case 15: /* fall through */ -+ case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break; -+ case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break; -+ case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break; -+ default: BUG(); break; -+ } -+ dev_dbg(info->device, " * LCDCON2 = %08lx\n", value); -+ lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value); -+ -+ /* Vertical timing */ -+ value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET; -+ value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET; -+ value |= info->var.lower_margin; -+ dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value); -+ lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value); -+ -+ /* Horizontal timing */ -+ value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET; -+ value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET; -+ value |= (info->var.left_margin - 1); -+ dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value); -+ lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value); -+ -+ /* Display size */ -+ value = (info->var.xres - 1) << ATMEL_LCDC_HOZVAL_OFFSET; -+ value |= info->var.yres - 1; -+ lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value); -+ -+ /* FIFO Threshold: Use formula from data sheet */ -+ value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3); -+ lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value); -+ -+ /* Toggle LCD_MODE every frame */ -+ lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0); -+ -+ /* Disable all interrupts */ -+ lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL); -+ -+ /* Set contrast */ -+ value = ATMEL_LCDC_PS_DIV8 | ATMEL_LCDC_POL_POSITIVE | ATMEL_LCDC_ENA_PWMENABLE; -+ lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value); -+ lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); -+ /* ...wait for DMA engine to become idle... */ -+ while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY) -+ msleep(10); -+ -+ dev_dbg(info->device, " * re-enable DMA engine\n"); -+ /* ...and enable it with updated configuration */ -+ lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon); -+ -+ dev_dbg(info->device, " * re-enable LCDC core\n"); -+ lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, -+ (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); -+ -+ dev_dbg(info->device, " * DONE\n"); -+ -+ return 0; -+} -+ -+static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf) -+{ -+ chan &= 0xffff; -+ chan >>= 16 - bf->length; -+ return chan << bf->offset; -+} -+ -+/** -+ * atmel_lcdfb_setcolreg - Optional function. Sets a color register. -+ * @regno: Which register in the CLUT we are programming -+ * @red: The red value which can be up to 16 bits wide -+ * @green: The green value which can be up to 16 bits wide -+ * @blue: The blue value which can be up to 16 bits wide. -+ * @transp: If supported the alpha value which can be up to 16 bits wide. -+ * @info: frame buffer info structure -+ * -+ * Set a single color register. The values supplied have a 16 bit -+ * magnitude which needs to be scaled in this function for the hardware. -+ * Things to take into consideration are how many color registers, if -+ * any, are supported with the current color visual. With truecolor mode -+ * no color palettes are supported. Here a psuedo palette is created -+ * which we store the value in pseudo_palette in struct fb_info. For -+ * pseudocolor mode we have a limited color palette. To deal with this -+ * we can program what color is displayed for a particular pixel value. -+ * DirectColor is similar in that we can program each color field. If -+ * we have a static colormap we don't need to implement this function. -+ * -+ * Returns negative errno on error, or zero on success. In an -+ * ideal world, this would have been the case, but as it turns -+ * out, the other drivers return 1 on failure, so that's what -+ * we're going to do. -+ */ -+static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red, -+ unsigned int green, unsigned int blue, -+ unsigned int transp, struct fb_info *info) -+{ -+ struct atmel_lcdfb_info *sinfo = info->par; -+ unsigned int val; -+ u32 *pal; -+ int ret = 1; -+ -+ if (info->var.grayscale) -+ red = green = blue = (19595 * red + 38470 * green -+ + 7471 * blue) >> 16; -+ -+ switch (info->fix.visual) { -+ case FB_VISUAL_TRUECOLOR: -+ if (regno < 16) { -+ pal = info->pseudo_palette; -+ -+ val = chan_to_field(red, &info->var.red); -+ val |= chan_to_field(green, &info->var.green); -+ val |= chan_to_field(blue, &info->var.blue); -+ -+ pal[regno] = val; -+ ret = 0; -+ } -+ break; -+ -+ case FB_VISUAL_PSEUDOCOLOR: -+ if (regno < 256) { -+ val = ((red >> 11) & 0x001f); -+ val |= ((green >> 6) & 0x03e0); -+ val |= ((blue >> 1) & 0x7c00); -+ -+ /* -+ * TODO: intensity bit. Maybe something like -+ * ~(red[10] ^ green[10] ^ blue[10]) & 1 -+ */ -+ -+ lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val); -+ ret = 0; -+ } -+ break; -+ } -+ -+ return ret; -+} -+ -+static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var, -+ struct fb_info *info) -+{ -+ dev_dbg(info->device, "%s\n", __func__); -+ -+ atmel_lcdfb_update_dma(info, var); -+ -+ return 0; -+} -+ -+static struct fb_ops atmel_lcdfb_ops = { -+ .owner = THIS_MODULE, -+ .fb_check_var = atmel_lcdfb_check_var, -+ .fb_set_par = atmel_lcdfb_set_par, -+ .fb_setcolreg = atmel_lcdfb_setcolreg, -+ .fb_pan_display = atmel_lcdfb_pan_display, -+ .fb_fillrect = cfb_fillrect, -+ .fb_copyarea = cfb_copyarea, -+ .fb_imageblit = cfb_imageblit, -+}; -+ -+static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id) -+{ -+ struct fb_info *info = dev_id; -+ struct atmel_lcdfb_info *sinfo = info->par; -+ u32 status; -+ -+ status = lcdc_readl(sinfo, ATMEL_LCDC_ISR); -+ lcdc_writel(sinfo, ATMEL_LCDC_IDR, status); -+ return IRQ_HANDLED; -+} -+ -+static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo) -+{ -+ struct fb_info *info = sinfo->info; -+ int ret = 0; -+ -+ memset_io(info->screen_base, 0, info->fix.smem_len); -+ info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW; -+ -+ dev_info(info->device, -+ "%luKiB frame buffer at %08lx (mapped at %p)\n", -+ (unsigned long)info->fix.smem_len / 1024, -+ (unsigned long)info->fix.smem_start, -+ info->screen_base); -+ -+ /* Allocate colormap */ -+ ret = fb_alloc_cmap(&info->cmap, 256, 0); -+ if (ret < 0) -+ dev_err(info->device, "Alloc color map failed\n"); -+ -+ return ret; -+} -+ -+static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo) -+{ -+ if (sinfo->bus_clk) -+ clk_enable(sinfo->bus_clk); -+ clk_enable(sinfo->lcdc_clk); -+} -+ -+static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo) -+{ -+ if (sinfo->bus_clk) -+ clk_disable(sinfo->bus_clk); -+ clk_disable(sinfo->lcdc_clk); -+} -+ -+ -+static int __init atmel_lcdfb_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct fb_info *info; -+ struct atmel_lcdfb_info *sinfo; -+ struct atmel_lcdfb_info *pdata_sinfo; -+ struct resource *regs = NULL; -+ struct resource *map = NULL; -+ int ret; -+ -+ dev_dbg(dev, "%s BEGIN\n", __func__); -+ -+ ret = -ENOMEM; -+ info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev); -+ if (!info) { -+ dev_err(dev, "cannot allocate memory\n"); -+ goto out; -+ } -+ -+ sinfo = info->par; -+ -+ if (dev->platform_data) { -+ pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data; -+ sinfo->default_bpp = pdata_sinfo->default_bpp; -+ sinfo->default_dmacon = pdata_sinfo->default_dmacon; -+ sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2; -+ sinfo->default_monspecs = pdata_sinfo->default_monspecs; -+ sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control; -+ sinfo->guard_time = pdata_sinfo->guard_time; -+ } else { -+ dev_err(dev, "cannot get default configuration\n"); -+ goto free_info; -+ } -+ sinfo->info = info; -+ sinfo->pdev = pdev; -+ -+ strcpy(info->fix.id, sinfo->pdev->name); -+ info->flags = ATMEL_LCDFB_FBINFO_DEFAULT; -+ info->pseudo_palette = sinfo->pseudo_palette; -+ info->fbops = &atmel_lcdfb_ops; -+ -+ memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs)); -+ info->fix = atmel_lcdfb_fix; -+ -+ /* Enable LCDC Clocks */ -+ if (cpu_is_at91sam9261()) { -+ sinfo->bus_clk = clk_get(dev, "hck1"); -+ if (IS_ERR(sinfo->bus_clk)) { -+ ret = PTR_ERR(sinfo->bus_clk); -+ goto free_info; -+ } -+ } -+ sinfo->lcdc_clk = clk_get(dev, "lcdc_clk"); -+ if (IS_ERR(sinfo->lcdc_clk)) { -+ ret = PTR_ERR(sinfo->lcdc_clk); -+ goto put_bus_clk; -+ } -+ atmel_lcdfb_start_clock(sinfo); -+ -+ ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb, -+ info->monspecs.modedb_len, info->monspecs.modedb, -+ sinfo->default_bpp); -+ if (!ret) { -+ dev_err(dev, "no suitable video mode found\n"); -+ goto stop_clk; -+ } -+ -+ -+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!regs) { -+ dev_err(dev, "resources unusable\n"); -+ ret = -ENXIO; -+ goto stop_clk; -+ } -+ -+ sinfo->irq_base = platform_get_irq(pdev, 0); -+ if (sinfo->irq_base < 0) { -+ dev_err(dev, "unable to get irq\n"); -+ ret = sinfo->irq_base; -+ goto stop_clk; -+ } -+ -+ /* Initialize video memory */ -+ map = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ if (map) { -+ /* use a pre-allocated memory buffer */ -+ info->fix.smem_start = map->start; -+ info->fix.smem_len = map->end - map->start + 1; -+ if (!request_mem_region(info->fix.smem_start, -+ info->fix.smem_len, pdev->name)) { -+ ret = -EBUSY; -+ goto stop_clk; -+ } -+ -+ info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); -+ if (!info->screen_base) -+ goto release_intmem; -+ } else { -+ /* alocate memory buffer */ -+ ret = atmel_lcdfb_alloc_video_memory(sinfo); -+ if (ret < 0) { -+ dev_err(dev, "cannot allocate framebuffer: %d\n", ret); -+ goto stop_clk; -+ } -+ } -+ -+ /* LCDC registers */ -+ info->fix.mmio_start = regs->start; -+ info->fix.mmio_len = regs->end - regs->start + 1; -+ -+ if (!request_mem_region(info->fix.mmio_start, -+ info->fix.mmio_len, pdev->name)) { -+ ret = -EBUSY; -+ goto free_fb; -+ } -+ -+ sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len); -+ if (!sinfo->mmio) { -+ dev_err(dev, "cannot map LCDC registers\n"); -+ goto release_mem; -+ } -+ -+ /* interrupt */ -+ ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info); -+ if (ret) { -+ dev_err(dev, "request_irq failed: %d\n", ret); -+ goto unmap_mmio; -+ } -+ -+ ret = atmel_lcdfb_init_fbinfo(sinfo); -+ if (ret < 0) { -+ dev_err(dev, "init fbinfo failed: %d\n", ret); -+ goto unregister_irqs; -+ } -+ -+ /* -+ * This makes sure that our colour bitfield -+ * descriptors are correctly initialised. -+ */ -+ atmel_lcdfb_check_var(&info->var, info); -+ -+ ret = fb_set_var(info, &info->var); -+ if (ret) { -+ dev_warn(dev, "unable to set display parameters\n"); -+ goto free_cmap; -+ } -+ -+ dev_set_drvdata(dev, info); -+ -+ /* -+ * Tell the world that we're ready to go -+ */ -+ ret = register_framebuffer(info); -+ if (ret < 0) { -+ dev_err(dev, "failed to register framebuffer device: %d\n", ret); -+ goto free_cmap; -+ } -+ -+ /* Power up the LCDC screen */ -+ if (sinfo->atmel_lcdfb_power_control) -+ sinfo->atmel_lcdfb_power_control(1); -+ -+ dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %lu\n", -+ info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base); -+ -+ return 0; -+ -+ -+free_cmap: -+ fb_dealloc_cmap(&info->cmap); -+unregister_irqs: -+ free_irq(sinfo->irq_base, info); -+unmap_mmio: -+ iounmap(sinfo->mmio); -+release_mem: -+ release_mem_region(info->fix.mmio_start, info->fix.mmio_len); -+free_fb: -+ if (map) -+ iounmap(info->screen_base); -+ else -+ atmel_lcdfb_free_video_memory(sinfo); -+ -+release_intmem: -+ if (map) -+ release_mem_region(info->fix.smem_start, info->fix.smem_len); -+stop_clk: -+ atmel_lcdfb_stop_clock(sinfo); -+ clk_put(sinfo->lcdc_clk); -+put_bus_clk: -+ if (sinfo->bus_clk) -+ clk_put(sinfo->bus_clk); -+free_info: -+ framebuffer_release(info); -+out: -+ dev_dbg(dev, "%s FAILED\n", __func__); -+ return ret; -+} -+ -+static int __exit atmel_lcdfb_remove(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct fb_info *info = dev_get_drvdata(dev); -+ struct atmel_lcdfb_info *sinfo = info->par; -+ -+ if (!sinfo) -+ return 0; -+ -+ if (sinfo->atmel_lcdfb_power_control) -+ sinfo->atmel_lcdfb_power_control(0); -+ unregister_framebuffer(info); -+ atmel_lcdfb_stop_clock(sinfo); -+ clk_put(sinfo->lcdc_clk); -+ if (sinfo->bus_clk) -+ clk_put(sinfo->bus_clk); -+ fb_dealloc_cmap(&info->cmap); -+ free_irq(sinfo->irq_base, info); -+ iounmap(sinfo->mmio); -+ release_mem_region(info->fix.mmio_start, info->fix.mmio_len); -+ if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) { -+ iounmap(info->screen_base); -+ release_mem_region(info->fix.smem_start, info->fix.smem_len); -+ } else { -+ atmel_lcdfb_free_video_memory(sinfo); -+ } -+ -+ dev_set_drvdata(dev, NULL); -+ framebuffer_release(info); -+ -+ return 0; -+} -+ -+static struct platform_driver atmel_lcdfb_driver = { -+ .remove = __exit_p(atmel_lcdfb_remove), -+ .driver = { -+ .name = "atmel_lcdfb", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init atmel_lcdfb_init(void) -+{ -+ return platform_driver_probe(&atmel_lcdfb_driver, atmel_lcdfb_probe); -+} -+ -+static void __exit atmel_lcdfb_exit(void) -+{ -+ platform_driver_unregister(&atmel_lcdfb_driver); -+} -+ -+module_init(atmel_lcdfb_init); -+module_exit(atmel_lcdfb_exit); -+ -+MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver"); -+MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@rfo.atmel.com>"); -+MODULE_LICENSE("GPL"); -diff -urN -x CVS linux-2.6.21/drivers/video/backlight/Kconfig linux-2.6-stable/drivers/video/backlight/Kconfig ---- linux-2.6.21/drivers/video/backlight/Kconfig Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/video/backlight/Kconfig Tue May 8 12:13:31 2007 -@@ -63,3 +63,11 @@ - help - If you have a Frontpath ProGear say Y to enable the - backlight driver. -+ -+config BACKLIGHT_KB920x -+ tristate "KwikByte KB9202 Backlight Driver" -+ depends on BACKLIGHT_CLASS_DEVICE && MACH_KB9200 -+ default y -+ help -+ If you have a KwikByte KB9202 board, say Y to enable the -+ backlight driver. -diff -urN -x CVS linux-2.6.21/drivers/video/backlight/Makefile linux-2.6-stable/drivers/video/backlight/Makefile ---- linux-2.6.21/drivers/video/backlight/Makefile Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/drivers/video/backlight/Makefile Tue May 8 12:13:31 2007 -@@ -6,3 +6,4 @@ - obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o - obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o - obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o -+obj-$(CONFIG_BACKLIGHT_KB920x) += kb920x_bl.o -diff -urN -x CVS linux-2.6.21/drivers/video/backlight/kb920x_bl.c linux-2.6-stable/drivers/video/backlight/kb920x_bl.c ---- linux-2.6.21/drivers/video/backlight/kb920x_bl.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/drivers/video/backlight/kb920x_bl.c Tue May 8 12:13:31 2007 -@@ -0,0 +1,164 @@ -+/* -+ * Backlight Driver for KB9202 -+ * -+ * Copyright (c) 2006 KwikByte -+ * -+ * Based on Sharp's Corgi Backlight Driver -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ */ -+ -+#include <linux/module.h> -+#include <linux/kernel.h> -+#include <linux/init.h> -+#include <linux/platform_device.h> -+#include <linux/spinlock.h> -+#include <linux/fb.h> -+#include <linux/backlight.h> -+ -+#include <asm/arch/gpio.h> -+ -+/* The backlight is on(1)/off(0) */ -+#define KB9202_DEFAULT_INTENSITY 1 -+#define KB9202_MAX_INTENSITY 1 -+ -+static int kb9202bl_suspended; -+static int current_intensity = 0; -+static DEFINE_SPINLOCK(bl_lock); -+ -+static int kb9202bl_set_intensity(struct backlight_device *bd) -+{ -+ unsigned long flags; -+ int intensity = bd->props.brightness; -+ -+ if (bd->props.power != FB_BLANK_UNBLANK) -+ intensity = 0; -+ if (bd->props.fb_blank != FB_BLANK_UNBLANK) -+ intensity = 0; -+ if (kb9202bl_suspended) -+ intensity = 0; -+ -+ if ((!current_intensity) && (bd->props.power == FB_BLANK_UNBLANK)) -+ intensity = 1; -+ -+ spin_lock_irqsave(&bl_lock, flags); -+ if (intensity) -+ gpio_set_value(AT91_PIN_PC23, 1); -+ else -+ gpio_set_value(AT91_PIN_PC23, 0); -+ spin_unlock_irqrestore(&bl_lock, flags); -+ -+ current_intensity = intensity; -+ -+ return 0; -+} -+ -+static int kb9202bl_get_intensity(struct backlight_device *bd) -+{ -+ return current_intensity; -+} -+ -+static struct backlight_ops kb9202bl_ops = { -+ .get_brightness = kb9202bl_get_intensity, -+ .update_status = kb9202bl_set_intensity, -+}; -+ -+static int __init kb9202bl_probe(struct platform_device *pdev) -+{ -+ struct backlight_device *bd; -+ -+ bd = backlight_device_register ("kb9202-bl", &pdev->dev, NULL, &kb9202bl_ops); -+ if (IS_ERR(bd)) -+ return PTR_ERR(bd); -+ -+ platform_set_drvdata(pdev, bd); -+ -+ bd->props.max_brightness = KB9202_MAX_INTENSITY; -+ bd->props.brightness = KB9202_DEFAULT_INTENSITY; -+ (void) kb9202bl_set_intensity(bd); -+ -+ return 0; -+} -+ -+static int kb9202bl_remove(struct platform_device *pdev) -+{ -+ struct backlight_device *bd = platform_get_drvdata(pdev); -+ -+ bd->props.brightness = 0; -+ bd->props.power = 0; -+ (void) kb9202bl_set_intensity(bd); -+ -+ backlight_device_unregister(bd); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static int kb9202bl_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ struct backlight_device *bd = platform_get_drvdata(pdev); -+ -+ kb9202bl_suspended = 1; -+ (void) kb9202bl_set_intensity(bd); -+ return 0; -+} -+ -+static int kb9202bl_resume(struct platform_device *dev) -+{ -+ struct backlight_device *bd = platform_get_drvdata(pdev); -+ -+ kb9202bl_suspended = 0; -+ (void) kb9202bl_set_intensity(bd); -+ return 0; -+} -+#else -+#define kb9202bl_suspend NULL -+#define kb9202bl_resume NULL -+#endif -+ -+static struct platform_driver kb9202bl_driver = { -+ .probe = kb9202bl_probe, -+ .remove = kb9202bl_remove, -+ .suspend = kb9202bl_suspend, -+ .resume = kb9202bl_resume, -+ .driver = { -+ .name = "kb9202-bl", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static struct platform_device *kb9202bl_device; -+ -+static int __init kb9202bl_init(void) -+{ -+ int ret; -+ -+ ret = platform_driver_register(&kb9202bl_driver); -+ if (!ret) { -+ kb9202bl_device = platform_device_alloc("kb9202-bl", -1); -+ if (!kb9202bl_device) -+ return -ENOMEM; -+ -+ ret = platform_device_add(kb9202bl_device); -+ if (ret) { -+ platform_device_put(kb9202bl_device); -+ platform_driver_unregister(&kb9202bl_driver); -+ } -+ } -+ return ret; -+} -+ -+static void __exit kb9202bl_exit(void) -+{ -+ platform_device_unregister(kb9202bl_device); -+ platform_driver_unregister(&kb9202bl_driver); -+} -+ -+module_init(kb9202bl_init); -+module_exit(kb9202bl_exit); -+ -+MODULE_AUTHOR("KwikByte <kb9200_dev@kwikbyte.com>"); -+MODULE_DESCRIPTION("KB9202 Backlight Driver"); -+MODULE_LICENSE("GPL"); -diff -urN -x CVS linux-2.6.21/drivers/video/s1d15605fb.c linux-2.6-stable/drivers/video/s1d15605fb.c ---- linux-2.6.21/drivers/video/s1d15605fb.c Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/drivers/video/s1d15605fb.c Tue May 8 12:13:31 2007 -@@ -0,0 +1,659 @@ -+/* -+ * drivers/video/s1d15605.c -+ * -+ * Adapted from several sources including: -+ * 1) Driver for AT91 LCD Controller -+ * Copyright (C) 2006 Atmel -+ * -+ * 2) Copyright (C) 2005 S. Kevin Hester -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive for -+ * more details. -+ * -+ * This is a basic framebuffer driver for the Optrex F-51320 128x64 mono LCD -+ * display. This display uses a clone of the common Epson SED 1531 display -+ * controller. -+ * -+ * I've heavily borrowed code from the vfb.c driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifdef DEBUG -+#define MSG(string, args...) printk("s1d15605fb:" string, ##args) -+#else -+#define MSG(string, args...) -+#endif -+ -+#include <linux/kernel.h> -+#include <linux/platform_device.h> -+#include <linux/dma-mapping.h> -+#include <linux/interrupt.h> -+#include <linux/clk.h> -+#include <linux/fb.h> -+#include <linux/init.h> -+#include <linux/delay.h> -+ -+#include <asm/uaccess.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+ -+#ifdef CONFIG_PMAC_BACKLIGHT -+#include <asm/backlight.h> -+#endif -+ -+#define VIDEOWIDTH 128 -+#define VIDEOHEIGHT 64 -+#define VIDEODEPTH 1 /* bits/pixel */ -+#define VIDEOWIDTH_BYTES ((VIDEOWIDTH * VIDEODEPTH) / 8) -+ -+/* The number of bytes that actually go to the device */ -+#define ACTUALVIDEOMEMSIZE (VIDEOWIDTH_BYTES * VIDEOHEIGHT) -+#define VIDEOMEMSIZE PAGE_SIZE -+ -+static struct fb_var_screeninfo s1d15605_default __initdata = { -+ .xres = VIDEOWIDTH, -+ .yres = VIDEOHEIGHT, -+ .xres_virtual = VIDEOWIDTH, -+ .yres_virtual = VIDEOHEIGHT, -+ .bits_per_pixel = VIDEODEPTH, -+ .red = { 0, 1, 0 }, -+ .green = { 0, 1, 0 }, -+ .blue = { 0, 1, 0 }, -+ .activate = FB_ACTIVATE_NOW, -+ .pixclock = 20000, -+ .vmode = FB_VMODE_NONINTERLACED, -+}; -+ -+static struct fb_fix_screeninfo s1d15605_fix __initdata = { -+ .id = "s1d15605", -+ .type = FB_TYPE_PACKED_PIXELS, -+ .visual = FB_VISUAL_MONO10, -+ .xpanstep = 0, -+ .ypanstep = 0, -+ .ywrapstep = 0, -+ .accel = FB_ACCEL_NONE, -+}; -+ -+struct s1d15605fb_info { -+ struct fb_info *info; -+ char *mmio; -+ unsigned long reset_pin; -+ struct platform_device *pdev; -+}; -+ -+/* -+ * LCD device interface -+ */ -+#define RESET_DISPLAY 0xE2 -+#define LCD_BIAS_1_9 0xA2 -+#define ADC_SELECT_REVERSE 0xA1 -+#define COMMON_OUTPUT_NORMAL 0xC0 -+#define V5_RESISTOR_RATIO 0x26 -+#define ELECTRONIC_VOLUME_SET 0x81 -+#define ELECTRONIC_VOLUME_INIT 0x20 -+#define POWER_CONTROL_SET 0x28 -+#define VOLTAGE_REGULATOR 0x02 -+#define VOLTAGE_FOLLOWER 0x01 -+#define BOOSTER_CIRCUIT 0x04 -+#define DISPLAY_ON 0xAF -+#define START_LINE_SET 0x40 -+#define PAGE_ADDRESS_SET 0xB0 -+#define COLUMN_ADDRESS_HIGH 0x10 -+#define COLUMN_ADDRESS_LOW 0x00 -+#define RESISTOR_RATIO_START 0x20 -+ -+#define NUM_OF_PAGES 8 -+#define NUM_OF_COLUMNS 128 -+ -+#define WRITE_COMMAND(x) __raw_writeb((x), (sinfo)->mmio) -+#define READ_COMMAND __raw_readb((sinfo)->mmio) -+#define WRITE_DATA(x) __raw_writeb((x), (sinfo)->mmio + (0x10000)) -+#define READ_DATA __raw_readb((sinfo)->mmio + (0x10000)) -+ -+ -+/* -+ * s1d15605fb_resize_framebuffer -+ * -+ * Free allocated space if different. Allocate on new of changed. -+ * Returns -ENOMEM if the new framebuffer can not be allocated, -+ * zero on success. -+ */ -+static int s1d15605fb_resize_framebuffer(struct s1d15605fb_info *sinfo) -+{ -+ struct fb_info *info = sinfo->info; -+ struct fb_fix_screeninfo *fix = &info->fix; -+ struct fb_var_screeninfo *var = &info->var; -+ unsigned int new_size; -+ void *new_vaddr; -+ -+ new_size = ((var->xres_virtual * var->yres_virtual * var->bits_per_pixel) / 8); -+ -+ MSG("%s: x (%d) y (%d) bpp (%d): new size 0x%08x\n", __FUNCTION__, -+ var->xres_virtual, var->yres_virtual, var->bits_per_pixel, new_size); -+ -+ if (new_size == fix->smem_len) -+ return 0; -+ -+ if (fix->smem_len) { -+ kfree(info->screen_base); -+ } -+ -+ new_vaddr = kmalloc(new_size, GFP_KERNEL); -+ -+ if (!new_vaddr) { -+ fix->smem_len = 0; -+ return -ENOMEM; -+ } -+ -+ info->screen_base = new_vaddr; -+ fix->smem_start = (unsigned)new_vaddr; -+ fix->smem_len = new_size; -+ fix->line_length = (var->xres_virtual * var->bits_per_pixel) / 8; -+ -+ dev_info(info->device, -+ "%luKiB frame buffer at %08lx (mapped at %p)\n", -+ (unsigned long)info->fix.smem_len / 1024, -+ (unsigned long)info->fix.smem_start, -+ info->screen_base); -+ -+ return 0; -+} -+ -+ -+/* -+ * The s1d15605 seems to be divided into eight 128 pixel wide pages (from top to -+ * bottom) each page seems to be eight pixels high, where these eight pixels are -+ * one byte -+ */ -+static void s1d15605_update(struct fb_info *info) -+{ -+ struct s1d15605fb_info *sinfo = info->par; -+ int page, i, row, colmask; -+ u8 retVal, *rowPtr; -+ -+ WRITE_COMMAND(START_LINE_SET); -+ for (page = 0; page < NUM_OF_PAGES; ++page) { -+ WRITE_COMMAND(PAGE_ADDRESS_SET + page); -+ WRITE_COMMAND(COLUMN_ADDRESS_HIGH); -+ WRITE_COMMAND(COLUMN_ADDRESS_LOW); -+ -+ for (i = 0; i < NUM_OF_COLUMNS; ++i) -+ { -+ /* point of opportunity: optimization */ -+ colmask = (1 << (i & 0x7)); -+ rowPtr = (u8*)(info->screen_base); -+ rowPtr += (VIDEOWIDTH_BYTES * 8 * page); -+ rowPtr += (i >> 3); -+ retVal = 0; -+ for (row = 0; row < 8; ++row) -+ { -+ retVal = (retVal >> 1) | (((*rowPtr) & colmask) ? 0x80 : 0); -+ rowPtr += VIDEOWIDTH_BYTES; -+ } -+ WRITE_DATA(retVal); -+ } -+ } -+ -+ WRITE_COMMAND(DISPLAY_ON); -+} -+ -+ -+/* -+ * Setting the video mode has been split into two parts. -+ * First part, xxxfb_check_var, must not write anything -+ * to hardware, it should only verify and adjust var. -+ * This means it doesn't alter par but it does use hardware -+ * data from it to check this var. -+ */ -+static int s1d15605_check_var(struct fb_var_screeninfo *var, struct fb_info *info) -+{ -+ /* -+ * Some very basic checks -+ */ -+ if (!var->xres) -+ var->xres = 1; -+ if (!var->yres) -+ var->yres = 1; -+ if (var->xres > var->xres_virtual) -+ var->xres_virtual = var->xres; -+ if (var->yres > var->yres_virtual) -+ var->yres_virtual = var->yres; -+ -+ if(var->bits_per_pixel > VIDEODEPTH) -+ return -EINVAL; -+ -+ /* -+ * Memory limit -+ */ -+ if (((var->yres_virtual * var->bits_per_pixel * var->yres_virtual) >> 3) > -+ ACTUALVIDEOMEMSIZE) -+ return -ENOMEM; -+ -+ /* -+ * Now that we checked it we alter var. The reason being is that the video -+ * mode passed in might not work but slight changes to it might make it -+ * work. This way we let the user know what is acceptable. -+ */ -+ switch (var->bits_per_pixel) { -+ case 1: -+ var->red.offset = var->green.offset = var->blue.offset = 0; -+ var->red.length = var->green.length = var->blue.length -+ = var->bits_per_pixel; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ var->xoffset = var->yoffset = 0; -+ var->red.msb_right = var->green.msb_right = var->blue.msb_right = -+ var->transp.msb_right = 0; -+ -+ return 0; -+} -+ -+ -+/* -+ * This routine actually sets the video mode. It's in here where we -+ * the hardware state info->par and fix which can be affected by the -+ * change in par. For this driver it doesn't do much. -+ */ -+static int s1d15605_set_par(struct fb_info *info) -+{ -+ int ret; -+ -+ MSG("%s:\n", __func__); -+ MSG(" * resolution: %ux%u (%ux%u virtual)\n", -+ info->var.xres, info->var.yres, -+ info->var.xres_virtual, info->var.yres_virtual); -+ -+ ret = s1d15605fb_resize_framebuffer(info->par); -+ -+ info->fix.visual = FB_VISUAL_MONO10; -+ return ret; -+} -+ -+ -+/* -+ * Set a single color register. The values supplied are already -+ * rounded down to the hardware's capabilities (according to the -+ * entries in the var structure). Return != 0 for invalid regno. -+ */ -+static int s1d15605_setcolreg(u_int regno, u_int red, u_int green, u_int blue, -+ u_int transp, struct fb_info *info) -+{ -+ if (regno > 1) /* no. of hw registers - we only do mono now */ -+ return 1; -+ -+ return 0; -+} -+ -+ -+/* -+ * Currently, the routine will simply shut-off the backlight and prevent -+ * updates/refreshes. Modify according to application. -+ * -+ * 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off -+ */ -+static int s1d15605_blank(int blank, struct fb_info *info) -+{ -+#ifdef CONFIG_PMAC_BACKLIGHT -+ if (blank) -+ pmac_backlight->props.power = FB_BLANK_POWERDOWN; -+ else -+ pmac_backlight->props.power = FB_BLANK_UNBLANK; -+ backlight_update_status(pmac_backlight); -+#endif -+ return 1; -+} -+ -+ -+/* -+ * Pan or Wrap the Display -+ * -+ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag -+ */ -+/* -+static int s1d15605_pan_display(struct fb_var_screeninfo *var, -+ struct fb_info *info) -+{ -+ if (var->vmode & FB_VMODE_YWRAP) { -+ if (var->yoffset < 0 -+ || var->yoffset >= info->var.yres_virtual -+ || var->xoffset) -+ return -EINVAL; -+ } else { -+ if (var->xoffset + var->xres > info->var.xres_virtual || -+ var->yoffset + var->yres > info->var.yres_virtual) -+ return -EINVAL; -+ } -+ info->var.xoffset = var->xoffset; -+ info->var.yoffset = var->yoffset; -+ if (var->vmode & FB_VMODE_YWRAP) -+ info->var.vmode |= FB_VMODE_YWRAP; -+ else -+ info->var.vmode &= ~FB_VMODE_YWRAP; -+ return 0; -+} -+*/ -+ -+ -+static void s1d15605_copyarea(struct fb_info *info, const struct fb_copyarea *region) -+{ -+ cfb_copyarea(info, region); -+ s1d15605_update(info); -+} -+ -+ -+static void s1d15605_fillrect (struct fb_info *info, const struct fb_fillrect *rect) -+{ -+ cfb_fillrect(info, rect); -+ s1d15605_update(info); -+} -+ -+ -+static void s1d15605_imageblit(struct fb_info *p, const struct fb_image *image) -+{ -+ cfb_imageblit(p, image); -+ s1d15605_update(p); -+} -+ -+ -+/* -+ * Write the users data to our framebuffer, and then trigger a psuedo DMA -+ */ -+static ssize_t s1d15605_write(struct file *file, const char *buf, -+ size_t count, loff_t *ppos) -+{ -+ unsigned long p = *ppos; -+ struct inode *inode = file->f_dentry->d_inode; -+ int fbidx = iminor(inode); -+ struct fb_info *info = registered_fb[fbidx]; -+ int err; -+ -+ if (p > info->fix.smem_len) -+ return -ENOSPC; -+ if (count >= info->fix.smem_len) -+ count = info->fix.smem_len; -+ err = 0; -+ if (count + p > info->fix.smem_len) { -+ count = info->fix.smem_len - p; -+ err = -ENOSPC; -+ } -+ if (count) { -+ char *base_addr; -+ -+ base_addr = info->screen_base; -+ count -= copy_from_user(base_addr+p, buf, count); -+ *ppos += count; -+ err = -EFAULT; -+ } -+ -+ s1d15605_update(info); -+ -+ if (count) -+ return count; -+ -+ return err; -+} -+ -+#ifdef USE_PRIVATE_VMA_FXS -+static void s1d15605_vma_open(struct vm_area_struct *vma) -+{ -+ // FIXME - store stats in the device data via vm_private_data -+} -+ -+ -+static void s1d15605_vma_close(struct vm_area_struct *vma) -+{ -+ // FIXME - store stats in the device data via vm_private_data -+} -+ -+ -+static struct page *s1d15605_vma_nopage(struct vm_area_struct *vma, -+ unsigned long address, int *type) -+{ -+ struct page *page; -+ struct fb_info *info = vma->vm_private_data; -+ -+ page = virt_to_page(info->screen_base); -+ get_page(page); -+ -+ // FIXME - now someone has a link to our page, start periodically blitting -+ // latest updates to the actual device. -+ -+ return page; -+} -+ -+ -+static struct vm_operations_struct s1d15605_vm_ops = { -+ .open = s1d15605_vma_open, -+ .close = s1d15605_vma_close, -+ .nopage = s1d15605_vma_nopage -+}; -+ -+ -+/* We don't do much here - because we have special vm_ops */ -+static int s1d15605_mmap(struct fb_info *info, struct vm_area_struct *vma) -+{ -+ vma->vm_ops = &s1d15605_vm_ops; -+ vma->vm_flags |= VM_RESERVED; -+ vma->vm_private_data = info; -+ s1d15605_vma_open(vma); -+ -+ return 0; -+} -+#endif /* USE_PRIVATE_VMA_FXS */ -+ -+ -+static struct fb_ops s1d15605fb_ops = { -+ .owner = THIS_MODULE, -+ .fb_check_var = s1d15605_check_var, -+ .fb_set_par = s1d15605_set_par, -+ .fb_setcolreg = s1d15605_setcolreg, -+ .fb_blank = s1d15605_blank, -+// .fb_pan_display = s1d15605_pan_display, -+ .fb_fillrect = s1d15605_fillrect, -+ .fb_copyarea = s1d15605_copyarea, -+ .fb_imageblit = s1d15605_imageblit, -+ .fb_write = s1d15605_write, -+#ifdef USE_PRIVATE_VMA_FXS -+ .fb_mmap = s1d15605_mmap, -+#endif -+}; -+ -+ -+static void s1d15605_device_init(struct s1d15605fb_info *sinfo) { -+ -+ char value; -+ -+ /* release the reset line by reading the device - proto hardware */ -+ value = READ_COMMAND; -+ value = READ_COMMAND; -+ -+#ifdef CONFIG_MACH_KB9200 -+ /* new boards have dedicated reset line */ -+ gpio_set_value(sinfo->reset_pin, 1); -+#endif -+ -+ /* initialize the device within 5ms */ -+ WRITE_COMMAND(RESET_DISPLAY); -+ WRITE_COMMAND(LCD_BIAS_1_9); -+ WRITE_COMMAND(ADC_SELECT_REVERSE); -+ WRITE_COMMAND(COMMON_OUTPUT_NORMAL); -+ WRITE_COMMAND(V5_RESISTOR_RATIO); -+ WRITE_COMMAND(ELECTRONIC_VOLUME_SET); -+ WRITE_COMMAND(ELECTRONIC_VOLUME_INIT); -+ WRITE_COMMAND(POWER_CONTROL_SET | VOLTAGE_REGULATOR | VOLTAGE_FOLLOWER | BOOSTER_CIRCUIT); -+ WRITE_COMMAND(DISPLAY_ON); -+ -+ WRITE_COMMAND(RESISTOR_RATIO_START + 4); -+ WRITE_COMMAND(ELECTRONIC_VOLUME_SET); -+ WRITE_COMMAND(0x33); -+} -+ -+ -+static int s1d15605fb_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct fb_info *info; -+ struct s1d15605fb_info *sinfo; -+ int ret; -+ -+ MSG("%s\n", __func__); -+ -+ if (!(info = framebuffer_alloc(sizeof(struct s1d15605fb_info), dev))) { -+ dev_err(dev, "Cannot allocate framebuffer struct\n"); -+ return -ENOMEM; -+ } -+ -+ sinfo = info->par; -+ sinfo->info = info; -+ sinfo->pdev = pdev; -+ -+ if (pdev->num_resources < 2) { -+ dev_err(dev, "Resources unusable\n"); -+ ret = -ENODEV; -+ goto free_info; -+ } -+ -+ info->fbops = &s1d15605fb_ops; -+ strcpy(info->fix.id, pdev->name); -+ -+ info->fix.mmio_start = pdev->resource[0].start; -+ info->fix.mmio_len = pdev->resource[0].end - pdev->resource[0].start + 1; -+ sinfo->reset_pin = pdev->resource[1].start; -+ -+ ret = s1d15605fb_resize_framebuffer(sinfo); -+ if (ret < 0) { -+ dev_err(dev, "Cannot resize framebuffer: %d\n", ret); -+ goto free_fb; -+ } -+ -+ if (!request_mem_region(info->fix.mmio_start, -+ info->fix.mmio_len, pdev->name)) { -+ ret = -EBUSY; -+ goto free_fb; -+ } -+ -+ sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len); -+ if (!sinfo->mmio) { -+ dev_err(dev, "Cannot map LCD memory region\n"); -+ goto release_mem; -+ } -+ -+ s1d15605_device_init(sinfo); -+ -+ ret = fb_find_mode(&info->var, info, NULL, NULL, 0, NULL, 1); -+ -+ if (!ret || (ret == 4)) -+ info->var = s1d15605_default; -+ -+ info->fix = s1d15605_fix; -+ info->flags = FBINFO_FLAG_DEFAULT | -+/* FBINFO_HWACCEL_YPAN | */ -+ FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA; -+ -+ ret = register_framebuffer(info); -+ if (ret < 0) { -+ dev_err(dev, "Failed to register framebuffer device: %d\n", ret); -+ goto unmap_mmio; -+ } -+ -+ dev_set_drvdata(dev, info); -+ -+ memset(info->screen_base, 0, info->fix.smem_len); -+ info->var.activate |= FB_ACTIVATE_NOW; -+ ret = fb_set_var(info, &info->var); -+ if (ret) { -+ dev_warn(dev, "Unable to set display parameters\n"); -+ } -+ -+ info->var.activate &= ~(FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW); -+ -+ dev_dbg(dev, "%s SUCCESS\n", __func__); -+ -+ dev_info(dev, "Driver $Revision: 1.1 $\n"); -+ -+ return 0; -+ -+unmap_mmio: -+ iounmap(sinfo->mmio); -+release_mem: -+ release_mem_region(info->fix.mmio_start, info->fix.mmio_len); -+free_fb: -+ kfree(info->screen_base); -+ -+free_info: -+ framebuffer_release(info); -+ -+ dev_dbg(dev, "%s FAILED\n", __func__); -+ return ret; -+} -+ -+ -+static int s1d15605fb_remove(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct fb_info *info = dev_get_drvdata(dev); -+ struct s1d15605fb_info *sinfo = info->par; -+ -+ if (!sinfo) -+ return 0; -+ -+ unregister_framebuffer(info); -+ -+ iounmap(sinfo->mmio); -+ release_mem_region(info->fix.mmio_start, info->fix.mmio_len); -+ -+ kfree(info->screen_base); -+ -+ dev_set_drvdata(dev, NULL); -+ framebuffer_release(info); -+ return 0; -+} -+ -+ -+static struct platform_driver s1d15605fb_driver = { -+ .probe = s1d15605fb_probe, -+ .remove = s1d15605fb_remove, -+ .driver = { -+ .name = "s1d15605fb", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+ -+static int __init s1d15605fb_init(void) -+{ -+ return platform_driver_register(&s1d15605fb_driver); -+} -+ -+ -+static void __exit s1d15605fb_exit(void) -+{ -+ platform_driver_unregister(&s1d15605fb_driver); -+} -+ -+ -+module_init(s1d15605fb_init); -+module_exit(s1d15605fb_exit); -+ -+ -+MODULE_AUTHOR("KwikByte"); -+MODULE_DESCRIPTION("Epson S1D15605 LCD Controller framebuffer driver"); -+MODULE_LICENSE("GPL"); -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91_adc.h linux-2.6-stable/include/asm-arm/arch-at91/at91_adc.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91_adc.h Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91_adc.h Tue May 8 12:13:31 2007 -@@ -0,0 +1,61 @@ -+/* -+ * include/asm-arm/arch-at91/at91_adc.h -+ * -+ * Copyright (C) SAN People -+ * -+ * Analog-to-Digital Converter (ADC) registers. -+ * Based on AT91SAM9260 datasheet revision D. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#ifndef AT91_ADC_H -+#define AT91_ADC_H -+ -+#define AT91_ADC_CR 0x00 /* Control Register */ -+#define AT91_ADC_SWRST (1 << 0) /* Software Reset */ -+#define AT91_ADC_START (1 << 1) /* Start Conversion */ -+ -+#define AT91_ADC_MR 0x04 /* Mode Register */ -+#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ -+#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ -+#define AT91_ADC_TRGSEL_TC0 (0 << 1) -+#define AT91_ADC_TRGSEL_TC1 (1 << 1) -+#define AT91_ADC_TRGSEL_TC2 (2 << 1) -+#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) -+#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ -+#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ -+#define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ -+#define AT91_ADC_PRESCAL_(x) ((x) << 8) -+#define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */ -+#define AT91_ADC_STARTUP_(x) ((x) << 16) -+#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ -+#define AT91_ADC_SHTIM_(x) ((x) << 24) -+ -+#define AT91_ADC_CHER 0x10 /* Channel Enable Register */ -+#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ -+#define AT91_ADC_CHSR 0x18 /* Channel Status Register */ -+#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ -+ -+#define AT91_ADC_SR 0x1C /* Status Register */ -+#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ -+#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ -+#define AT91_ADC_DRDY (1 << 16) /* Data Ready */ -+#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ -+#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ -+#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ -+ -+#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ -+#define AT91_ADC_LDATA (0x3ff) -+ -+#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ -+#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ -+#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ -+ -+#define AT91_ADC_CHR(n) (0x30 + ((n) * 4) /* Channel Data Register N */ -+#define AT91_ADC_DATA (0x3ff) -+ -+#endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91_mci.h linux-2.6-stable/include/asm-arm/arch-at91/at91_mci.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91_mci.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91_mci.h Tue May 8 12:13:31 2007 -@@ -26,6 +26,9 @@ - #define AT91_MCI_MR 0x04 /* Mode Register */ - #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ - #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -+#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ -+#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ -+#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ - #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ - #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ - #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91_pmc.h linux-2.6-stable/include/asm-arm/arch-at91/at91_pmc.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91_pmc.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91_pmc.h Fri May 11 16:45:00 2007 -@@ -37,7 +37,9 @@ - #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ - #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ - --#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ -+#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL only] */ -+ -+#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ - #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ - #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ - #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91rm9200.h linux-2.6-stable/include/asm-arm/arch-at91/at91rm9200.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91rm9200.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91rm9200.h Tue May 8 12:56:33 2007 -@@ -107,185 +107,4 @@ - #define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ - - --#if 0 --/* -- * PIO pin definitions (peripheral A/B multiplexing). -- */ --#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */ --#define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */ --#define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */ --#define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */ --#define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */ --#define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */ --#define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */ --#define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */ --#define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */ --#define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */ --#define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */ --#define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */ --#define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */ --#define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */ --#define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */ --#define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */ --#define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */ --#define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */ --#define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */ --#define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */ --#define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */ --#define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */ --#define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */ --#define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */ --#define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */ --#define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */ --#define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */ --#define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */ --#define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */ --#define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */ --#define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */ --#define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */ --#define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */ --#define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */ --#define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */ --#define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */ --#define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */ --#define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */ --#define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */ --#define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */ --#define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */ --#define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */ --#define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ --#define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */ --#define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */ --#define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */ --#define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */ --#define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */ --#define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */ --#define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */ --#define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */ --#define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */ --#define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */ --#define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */ --#define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */ --#define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */ --#define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */ --#define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */ --#define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */ --#define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */ --#define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */ --#define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */ --#define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */ --#define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */ -- --#define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */ --#define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */ --#define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */ --#define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */ --#define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */ --#define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */ --#define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */ --#define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */ --#define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */ --#define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */ --#define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */ --#define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */ --#define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */ --#define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */ --#define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */ --#define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */ --#define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */ --#define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */ --#define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */ --#define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */ --#define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */ --#define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */ --#define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */ --#define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */ --#define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */ --#define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */ --#define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */ --#define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */ --#define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */ --#define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */ --#define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */ --#define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */ --#define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */ --#define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */ --#define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */ --#define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */ --#define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */ --#define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */ --#define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */ --#define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */ --#define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */ --#define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */ --#define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */ --#define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */ --#define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */ --#define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */ --#define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */ --#define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */ --#define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */ --#define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */ --#define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */ -- --#define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */ --#define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */ --#define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */ --#define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */ --#define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */ --#define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */ --#define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */ --#define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */ --#define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */ --#define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */ --#define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */ --#define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */ --#define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */ --#define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */ -- --#define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */ --#define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */ --#define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */ --#define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */ --#define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */ --#define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */ --#define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */ --#define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */ --#define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */ --#define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */ --#define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */ --#define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */ --#define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */ --#define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */ --#define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */ --#define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */ --#define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */ --#define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */ --#define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */ --#define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */ --#define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */ --#define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */ --#define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */ --#define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */ --#define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */ --#define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */ --#define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */ --#define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */ --#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */ --#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */ --#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */ --#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ --#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */ --#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */ --#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */ --#define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */ --#define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */ --#define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */ --#define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */ --#define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */ --#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */ --#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */ --#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */ --#endif -- - #endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9260.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91sam9260.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260.h Tue May 8 12:56:33 2007 -@@ -117,13 +117,4 @@ - #define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ - - --#if 0 --/* -- * PIO pin definitions (peripheral A/B multiplexing). -- */ -- --// TODO: Add -- --#endif -- - #endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9260_matrix.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260_matrix.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91sam9260_matrix.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260_matrix.h Fri May 11 16:20:33 2007 -@@ -67,7 +67,7 @@ - #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ - #define AT91_MATRIX_CS4A_SMC (0 << 4) - #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) --#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ -+#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ - #define AT91_MATRIX_CS5A_SMC (0 << 5) - #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) - #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9261.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9261.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91sam9261.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9261.h Tue May 8 12:56:33 2007 -@@ -98,195 +98,4 @@ - #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ - - --#if 0 --/* -- * PIO pin definitions (peripheral A/B multiplexing). -- */ --#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */ --#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */ --#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */ --#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */ --#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */ --#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */ --#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */ --#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */ --#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */ --#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */ --#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */ --#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */ --#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */ --#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */ --#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */ --#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */ --#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */ --#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */ --#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */ --#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */ --#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */ --#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */ --#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */ --#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */ --#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */ --#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */ --#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */ --#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */ --#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */ --#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */ --#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */ --#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */ --#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */ --#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */ --#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */ --#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */ --#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */ --#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */ --#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */ --#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */ --#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */ --#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */ --#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */ --#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */ --#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */ --#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */ --#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */ --#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */ --#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */ --#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */ --#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */ --#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */ --#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */ --#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */ --#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */ --#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */ --#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */ --#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */ --#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */ --#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */ --#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */ --#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */ --#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */ -- --#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */ --#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */ --#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */ --#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */ --#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */ --#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */ --#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */ --#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */ --#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */ --#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */ --#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */ --#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */ --#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */ --#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */ --#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */ --#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */ --#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */ --#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */ --#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */ --#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */ --#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */ --#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */ --#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */ --#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */ --#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */ --#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */ --#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */ --#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */ --#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */ --#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */ --#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */ --#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */ --#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */ --#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */ --#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */ --#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */ --#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */ --#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */ --#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */ --#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */ --#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */ --#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */ --#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */ --#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */ --#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */ --#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */ --#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */ --#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */ --#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */ --#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */ --#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */ --#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */ --#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */ --#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */ --#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */ --#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */ --#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */ --#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */ --#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */ --#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */ --#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */ -- --#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */ --#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */ --#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */ --#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */ --#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */ --#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */ --#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */ --#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */ --#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */ --#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */ --#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */ --#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */ --#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */ --#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */ --#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */ --#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */ --#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */ --#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */ --#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */ --#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */ --#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */ --#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */ --#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */ --#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */ --#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */ --#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */ --#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */ --#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */ --#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */ --#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */ --#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */ --#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */ --#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */ --#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */ --#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */ --#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */ --#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */ --#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */ --#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */ --#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */ --#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */ --#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */ --#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */ --#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */ --#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */ --#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */ --#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */ --#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */ --#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */ --#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */ --#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */ --#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */ --#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */ --#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */ --#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */ --#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */ --#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */ --#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */ --#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */ --#endif -- - #endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9263.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9263.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91sam9263.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9263.h Tue May 8 12:56:33 2007 -@@ -119,13 +119,5 @@ - #define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ - #define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ - --#if 0 --/* -- * PIO pin definitions (peripheral A/B multiplexing). -- */ -- --// TODO: Add -- --#endif - - #endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9rl.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9rl.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91sam9rl.h Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9rl.h Fri May 11 14:53:48 2007 -@@ -0,0 +1,110 @@ -+/* -+ * include/asm-arm/arch-at91/at91sam9260.h -+ * -+ * Copyright (C) 2007 Atmel Corporation -+ * -+ * Common definitions. -+ * Based on AT91SAM9RL datasheet revision A. (Preliminary) -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive for -+ * more details. -+ */ -+ -+#ifndef AT91SAM9RL_H -+#define AT91SAM9RL_H -+ -+/* -+ * Peripheral identifiers/interrupts. -+ */ -+#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -+#define AT91_ID_SYS 1 /* System Controller */ -+#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ -+#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ -+#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ -+#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ -+#define AT91SAM9RL_ID_US0 6 /* USART 0 */ -+#define AT91SAM9RL_ID_US1 7 /* USART 1 */ -+#define AT91SAM9RL_ID_US2 8 /* USART 2 */ -+#define AT91SAM9RL_ID_US3 9 /* USART 3 */ -+#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ -+#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ -+#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ -+#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ -+#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -+#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -+#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ -+#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ -+#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ -+#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ -+#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ -+#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ -+#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ -+#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ -+#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ -+#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ -+ -+ -+/* -+ * User Peripheral physical base addresses. -+ */ -+#define AT91SAM9RL_BASE_TCB0 0xfffa0000 -+#define AT91SAM9RL_BASE_TC0 0xfffa0000 -+#define AT91SAM9RL_BASE_TC1 0xfffa0040 -+#define AT91SAM9RL_BASE_TC2 0xfffa0080 -+#define AT91SAM9RL_BASE_MCI 0xfffa4000 -+#define AT91SAM9RL_BASE_TWI0 0xfffa8000 -+#define AT91SAM9RL_BASE_TWI1 0xfffac000 -+#define AT91SAM9RL_BASE_US0 0xfffb0000 -+#define AT91SAM9RL_BASE_US1 0xfffb4000 -+#define AT91SAM9RL_BASE_US2 0xfffb8000 -+#define AT91SAM9RL_BASE_US3 0xfffbc000 -+#define AT91SAM9RL_BASE_SSC0 0xfffc0000 -+#define AT91SAM9RL_BASE_SSC1 0xfffc4000 -+#define AT91SAM9RL_BASE_PWMC 0xfffc8000 -+#define AT91SAM9RL_BASE_SPI 0xfffcc000 -+#define AT91SAM9RL_BASE_TSC 0xfffd0000 -+#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 -+#define AT91SAM9RL_BASE_AC97C 0xfffd8000 -+#define AT91_BASE_SYS 0xffffc000 -+ -+ -+/* -+ * System Peripherals (offset from AT91_BASE_SYS) -+ */ -+#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) -+#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -+#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -+#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -+#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -+#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -+#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -+#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -+#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -+#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -+#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -+#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) -+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -+#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -+#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -+#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -+#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -+#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -+#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) -+#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -+#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) -+ -+ -+/* -+ * Internal Memory. -+ */ -+#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -+#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ -+ -+#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ -+#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ -+ -+#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ -+#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ -+ -+#endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9rl_matrix.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9rl_matrix.h ---- linux-2.6.21/include/asm-arm/arch-at91/at91sam9rl_matrix.h Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9rl_matrix.h Fri May 11 16:18:45 2007 -@@ -0,0 +1,96 @@ -+/* -+ * include/asm-arm/arch-at91/at91sam9rl_matrix.h -+ * -+ * Copyright (C) 2007 Atmel Corporation -+ * -+ * Memory Controllers (MATRIX, EBI) - System peripherals registers. -+ * Based on AT91SAM9RL datasheet revision A. (Preliminary) -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive for -+ * more details. -+ */ -+ -+#ifndef AT91SAM9RL_MATRIX_H -+#define AT91SAM9RL_MATRIX_H -+ -+#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -+#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -+#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -+#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -+#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -+#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -+#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -+#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -+#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -+#define AT91_MATRIX_ULBT_FOUR (2 << 0) -+#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -+ -+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -+#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -+#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -+#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) -+ -+#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -+#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -+#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -+#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -+#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -+#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -+#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -+#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -+#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -+#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -+#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -+#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -+ -+#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -+#define AT91_MATRIX_RCB2 (1 << 2) -+#define AT91_MATRIX_RCB3 (1 << 3) -+#define AT91_MATRIX_RCB4 (1 << 4) -+#define AT91_MATRIX_RCB5 (1 << 5) -+ -+#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ -+#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -+#define AT91_MATRIX_ITCM_0 (0 << 0) -+#define AT91_MATRIX_ITCM_16 (5 << 0) -+#define AT91_MATRIX_ITCM_32 (6 << 0) -+#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -+#define AT91_MATRIX_DTCM_0 (0 << 4) -+#define AT91_MATRIX_DTCM_16 (5 << 4) -+#define AT91_MATRIX_DTCM_32 (6 << 4) -+ -+#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ -+#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -+#define AT91_MATRIX_CS1A_SMC (0 << 1) -+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -+#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -+#define AT91_MATRIX_CS3A_SMC (0 << 3) -+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -+#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -+#define AT91_MATRIX_CS4A_SMC (0 << 4) -+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -+#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -+#define AT91_MATRIX_CS5A_SMC (0 << 5) -+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -+#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -+#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) -+ -+ -+#endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/board.h linux-2.6-stable/include/asm-arm/arch-at91/board.h ---- linux-2.6.21/include/asm-arm/arch-at91/board.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/board.h Thu May 10 12:21:10 2007 -@@ -62,7 +62,7 @@ - }; - extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); - -- /* Ethernet */ -+ /* Ethernet (EMAC & MACB) */ - struct at91_eth_data { - u8 phy_irq_pin; /* PHY IRQ */ - u8 is_rmii; /* using RMII interface? */ -@@ -114,9 +114,31 @@ - }; - extern void __init at91_add_device_serial(void); - -+ /* LCD Controller */ -+struct atmel_lcdfb_info; -+extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); -+ -+ /* AC97 */ -+struct atmel_ac97_data { -+ u8 reset_pin; /* reset */ -+}; -+extern void __init at91_add_device_ac97(struct atmel_ac97_data *data); -+ -+ /* ISI */ -+extern void __init at91_add_device_isi(void); -+ - /* LEDs */ - extern u8 at91_leds_cpu; - extern u8 at91_leds_timer; - extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); - -+struct at91_gpio_led { -+ u8 index; /* index of LED */ -+ char* name; /* name of LED */ -+ u8 gpio; /* AT91_PIN_xx */ -+ u8 flags; /* 1=active-high */ -+ char* trigger; /* default trigger */ -+}; -+extern void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr); -+ - #endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/cpu.h linux-2.6-stable/include/asm-arm/arch-at91/cpu.h ---- linux-2.6.21/include/asm-arm/arch-at91/cpu.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/cpu.h Wed May 9 10:20:54 2007 -@@ -26,6 +26,8 @@ - #define ARCH_ID_AT91SAM9XE256 0x329a93a0 - #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 - -+#define ARCH_ID_AT91SAM9RL64 0x019b03a0 -+ - static inline unsigned long at91_cpu_identify(void) - { - return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); -@@ -68,4 +70,10 @@ - #define cpu_is_at91sam9263() (0) - #endif - -+#ifdef CONFIG_ARCH_AT91SAM9RL -+#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) -+#else -+#define cpu_is_at91sam9rl() (0) -+#endif -+ - #endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/hardware.h linux-2.6-stable/include/asm-arm/arch-at91/hardware.h ---- linux-2.6.21/include/asm-arm/arch-at91/hardware.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/hardware.h Fri May 11 14:45:12 2007 -@@ -24,6 +24,8 @@ - #include <asm/arch/at91sam9261.h> - #elif defined(CONFIG_ARCH_AT91SAM9263) - #include <asm/arch/at91sam9263.h> -+#elif defined(CONFIG_ARCH_AT91SAM9RL) -+#include <asm/arch/at91sam9rl.h> - #else - #error "Unsupported AT91 processor" - #endif -@@ -69,22 +71,5 @@ - /* Clocks */ - #define AT91_SLOW_CLOCK 32768 /* slow clock */ - --#ifndef __ASSEMBLY__ --#include <asm/io.h> -- --static inline unsigned int at91_sys_read(unsigned int reg_offset) --{ -- void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; -- -- return __raw_readl(addr + reg_offset); --} -- --static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) --{ -- void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; -- -- __raw_writel(value, addr + reg_offset); --} --#endif - - #endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/ics1523.h linux-2.6-stable/include/asm-arm/arch-at91/ics1523.h ---- linux-2.6.21/include/asm-arm/arch-at91/ics1523.h Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/include/asm-arm/arch-at91/ics1523.h Tue May 8 12:13:31 2007 -@@ -0,0 +1,154 @@ -+//*---------------------------------------------------------------------------- -+//* ATMEL Microcontroller Software Support - ROUSSET - -+//*---------------------------------------------------------------------------- -+//* The software is delivered "AS IS" without warranty or condition of any -+//* kind, either express, implied or statutory. This includes without -+//* limitation any warranty or condition with respect to merchantability or -+//* fitness for any particular purpose, or against the infringements of -+//* intellectual property rights of others. -+//*---------------------------------------------------------------------------- -+//* File Name : ics1523.h -+//* Object : Clock Generator Prototyping File. -+//* -+//* 1.0 08/28/02 ED : Creation -+//* 1.2 13/01/03 FB : Update on lib V3 -+//*---------------------------------------------------------------------------- -+ -+#ifndef ics1523_h -+#define ics1523_h -+ -+/*-------------------------------------------*/ -+/* ICS1523 TWI Serial Clock Definition */ -+/*-------------------------------------------*/ -+ -+#define ICS_MIN_CLOCK 100 /* Min Frequency Access Clock KHz */ -+#define ICS_MAX_CLOCK 400 /* Max Frequency Access Clock KHz */ -+#define ICS_TRANSFER_RATE ICS_MAX_CLOCK /* Transfer speed to apply */ -+ -+#define ICS_WRITE_CLK_PNB 30 /* TWCK Clock Periods required to write */ -+#define ICS_READ_CLK_PNB 40 /* TWCK Clock Periods required to read */ -+ -+/*-------------------------------------------*/ -+/* ICS1523 Write Operation Definition */ -+/*-------------------------------------------*/ -+ -+#define ICS1523_ACCESS_OK 0 /* OK */ -+#define ICS1523_ACCESS_ERROR -1 /* NOK */ -+ -+/*-------------------------------------------*/ -+/* ICS1523 Device Addresses Definition */ -+/*-------------------------------------------*/ -+ -+#define ICS_ADDR 0x26 /* Device Address */ -+ -+/*--------------------------------------------------*/ -+/* ICS1523 Registers Internal Addresses Definition */ -+/*--------------------------------------------------*/ -+ -+#define ICS_ICR 0x0 /* Input Control Register */ -+#define ICS_LCR 0x1 /* Loop Control Register */ -+#define ICS_FD0 0x2 /* PLL FeedBack Divider LSBs */ -+#define ICS_FD1 0x3 /* PLL FeedBack Divider MSBs */ -+#define ICS_DPAO 0x4 /* Dynamic Phase Aligner Offset */ -+#define ICS_DPAC 0x5 /* Dynamic Phase Aligner Resolution */ -+#define ICS_OE 0x6 /* Output Enables Register */ -+#define ICS_OD 0x7 /* Osc Divider Register */ -+#define ICS_SWRST 0x8 /* DPA & PLL Reset Register */ -+#define ICS_VID 0x10 /* Chip Version Register */ -+#define ICS_RID 0x11 /* Chip Revision Register */ -+#define ICS_SR 0x12 /* Status Register */ -+ -+/*------------------------------------------------------*/ -+/* ICS1523 Input Control Register Bits Definition */ -+/*------------------------------------------------------*/ -+ -+#define ICS_PDEN 0x1 /* Phase Detector Enable */ -+#define ICS_PDPOL 0x2 /* Phase Detector Enable Polarity */ -+#define ICS_REFPOL 0x4 /* External Reference Polarity */ -+#define ICS_FBKPOL 0x8 /* External Feedback Polarity */ -+#define ICS_FBKSEL 0x10 /* External Feedback Select */ -+#define ICS_FUNCSEL 0x20 /* Function Out Select */ -+#define ICS_ENPLS 0x40 /* Enable PLL Lock/Ref Status Output */ -+#define ICS_ENDLS 0x80 /* Enable DPA Lock/Ref Status Output */ -+ -+/*-----------------------------------------------------*/ -+/* ICS1523 Loop Control Register Bits Definition */ -+/*-----------------------------------------------------*/ -+ -+#define ICS_PFD 0x7 /* Phase Detector Gain */ -+#define ICS_PSD 0x30 /* Post-Scaler Divider */ -+ -+/*----------------------------------------------------*/ -+/* ICS1523 PLL FeedBack Divider LSBs Definition */ -+/*----------------------------------------------------*/ -+ -+#define ICS_FBDL 0xFF /* PLL FeedBack Divider LSBs */ -+ -+/*----------------------------------------------------*/ -+/* ICS1523 PLL FeedBack Divider MSBs Definition */ -+/*----------------------------------------------------*/ -+ -+#define ICS_FBDM 0xF /* PLL FeedBack Divider MSBs */ -+ -+/*------------------------------------------------------------*/ -+/* ICS1523 Dynamic Phase Aligner Offset Bits Definition */ -+/*------------------------------------------------------------*/ -+ -+#define ICS_DPAOS 0x2F /* Dynamic Phase Aligner Offset */ -+#define ICS_FILSEL 0x80 /* Loop Filter Select */ -+ -+/*----------------------------------------------------------------*/ -+/* ICS1523 Dynamic Phase Aligner Resolution Bits Definition */ -+/*----------------------------------------------------------------*/ -+ -+#define ICS_DPARES 0x3 /* Dynamic Phase Aligner Resolution */ -+#define ICS_MMREV 0xFC /* Metal Mask Revision Number */ -+ -+/*-------------------------------------------------------*/ -+/* ICS1523 Output Enables Register Bits Definition */ -+/*-------------------------------------------------------*/ -+ -+#define ICS_OEPCK 0x1 /* Output Enable for PECL PCLK Outputs */ -+#define ICS_OETCK 0x2 /* Output Enable for STTL CLK Output */ -+#define ICS_OEP2 0x4 /* Output Enable for PECL CLK/2 Outputs */ -+#define ICS_OET2 0x8 /* Output Enable for STTL CLK/2 Output */ -+#define ICS_OEF 0x10 /* Output Enable for STTL FUNC Output */ -+#define ICS_CLK2INV 0x20 /* CLK/2 Invert */ -+#define ICS_OSCL 0xC0 /* SSTL Clock Scaler */ -+ -+/*----------------------------------------------------*/ -+/* ICS1523 Osc Divider Register Bits Definition */ -+/*----------------------------------------------------*/ -+ -+#define ICS_OSCDIV 0x7F /* Oscillator Divider Modulus */ -+#define ICS_INSEL 0x80 /* Input Select */ -+ -+/*---------------------------------------------------*/ -+/* ICS1523 DPA & PLL Reset Register Definition */ -+/*---------------------------------------------------*/ -+ -+#define ICS_DPAR 0x0A /* DPA Reset Command */ -+#define ICS_PLLR 0x50 /* PLL Reset Command */ -+ -+/*------------------------------------------------*/ -+/* ICS1523 Chip Version Register Definition */ -+/*------------------------------------------------*/ -+ -+#define ICS_CHIPV 0xFF /* Chip Version */ -+ -+/*-------------------------------------------------*/ -+/* ICS1523 Chip Revision Register Definition */ -+/*-------------------------------------------------*/ -+ -+#define ICS_CHIPR 0xFF /* Chip Revision */ -+ -+/*------------------------------------------*/ -+/* ICS1523 Status Register Definition */ -+/*------------------------------------------*/ -+ -+#define ICS_DPALOCK 0x1 /* DPA Lock Status */ -+#define ICS_PLLLOCK 0x2 /* PLL Lock Status */ -+ -+int at91_ics1523_init(void); -+ -+#endif /* ics1523_h */ -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/io.h linux-2.6-stable/include/asm-arm/arch-at91/io.h ---- linux-2.6.21/include/asm-arm/arch-at91/io.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/io.h Fri May 11 14:45:12 2007 -@@ -29,4 +29,22 @@ - #define __mem_pci(a) (a) - - -+#ifndef __ASSEMBLY__ -+ -+static inline unsigned int at91_sys_read(unsigned int reg_offset) -+{ -+ void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; -+ -+ return __raw_readl(addr + reg_offset); -+} -+ -+static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -+{ -+ void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; -+ -+ __raw_writel(value, addr + reg_offset); -+} -+ -+#endif -+ - #endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/irqs.h linux-2.6-stable/include/asm-arm/arch-at91/irqs.h ---- linux-2.6.21/include/asm-arm/arch-at91/irqs.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/irqs.h Fri May 11 14:45:12 2007 -@@ -21,6 +21,7 @@ - #ifndef __ASM_ARCH_IRQS_H - #define __ASM_ARCH_IRQS_H - -+#include <asm/io.h> - #include <asm/arch/at91_aic.h> - - #define NR_AIC_IRQS 32 -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/spi.h linux-2.6-stable/include/asm-arm/arch-at91/spi.h ---- linux-2.6.21/include/asm-arm/arch-at91/spi.h Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/include/asm-arm/arch-at91/spi.h Tue May 8 14:31:24 2007 -@@ -0,0 +1,54 @@ -+/* -+ * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 -+ * -+ * (c) SAN People (Pty) Ltd -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#ifndef AT91_LEGACY_SPI_H -+#define AT91_LEGACY_SPI_H -+ -+#define SPI_MAJOR 153 /* registered device number */ -+ -+#define DEFAULT_SPI_CLK 6000000 -+ -+ -+/* Maximum number of buffers in a single SPI transfer. -+ * DataFlash uses maximum of 2 -+ * spidev interface supports up to 8. -+ */ -+#define MAX_SPI_TRANSFERS 8 -+#define NR_SPI_DEVICES 4 /* number of devices on SPI bus */ -+ -+/* -+ * Describes the buffers for a SPI transfer. -+ * A transmit & receive buffer must be specified for each transfer -+ */ -+struct spi_transfer_list { -+ void* tx[MAX_SPI_TRANSFERS]; /* transmit */ -+ int txlen[MAX_SPI_TRANSFERS]; -+ void* rx[MAX_SPI_TRANSFERS]; /* receive */ -+ int rxlen[MAX_SPI_TRANSFERS]; -+ int nr_transfers; /* number of transfers */ -+ int curr; /* current transfer */ -+}; -+ -+struct spi_local { -+ unsigned int pcs; /* Peripheral Chip Select value */ -+ -+ struct spi_transfer_list *xfers; /* current transfer list */ -+ dma_addr_t tx, rx; /* DMA address for current transfer */ -+ dma_addr_t txnext, rxnext; /* DMA address for next transfer */ -+}; -+ -+ -+/* Exported functions */ -+extern void spi_access_bus(short device); -+extern void spi_release_bus(short device); -+extern int spi_transfer(struct spi_transfer_list* list); -+ -+#endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/timex.h linux-2.6-stable/include/asm-arm/arch-at91/timex.h ---- linux-2.6.21/include/asm-arm/arch-at91/timex.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/timex.h Wed May 9 10:20:53 2007 -@@ -37,6 +37,11 @@ - #define AT91SAM9_MASTER_CLOCK 99959500 - #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) - -+#elif defined(CONFIG_ARCH_AT91SAM9RL) -+ -+#define AT91SAM9_MASTER_CLOCK 100000000 -+#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) -+ - #endif - - #endif -diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/uncompress.h linux-2.6-stable/include/asm-arm/arch-at91/uncompress.h ---- linux-2.6.21/include/asm-arm/arch-at91/uncompress.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/uncompress.h Fri May 11 14:45:12 2007 -@@ -21,7 +21,7 @@ - #ifndef __ASM_ARCH_UNCOMPRESS_H - #define __ASM_ARCH_UNCOMPRESS_H - --#include <asm/hardware.h> -+#include <asm/io.h> - #include <asm/arch/at91_dbgu.h> - - /* -diff -urN -x CVS linux-2.6.21/include/linux/clk.h linux-2.6-stable/include/linux/clk.h ---- linux-2.6.21/include/linux/clk.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/linux/clk.h Tue May 8 12:13:31 2007 -@@ -121,4 +121,24 @@ - */ - struct clk *clk_get_parent(struct clk *clk); - -+/** -+ * clk_must_disable - report whether a clock's users must disable it -+ * @clk: one node in the clock tree -+ * -+ * This routine returns true only if the upcoming system state requires -+ * disabling the specified clock. -+ * -+ * It's common for platform power states to constrain certain clocks (and -+ * their descendants) to be unavailable, while other states allow that -+ * clock to be active. A platform's power states often include an "all on" -+ * mode; system wide sleep states like "standby" or "suspend-to-RAM"; and -+ * operating states which sacrifice functionality for lower power usage. -+ * -+ * The constraint value is commonly tested in device driver suspend(), to -+ * leave clocks active if they are needed for features like wakeup events. -+ * On platforms that support reduced functionality operating states, the -+ * constraint may also need to be tested during resume() and probe() calls. -+ */ -+int clk_must_disable(struct clk *clk); -+ - #endif -diff -urN -x CVS linux-2.6.21/include/linux/i2c-id.h linux-2.6-stable/include/linux/i2c-id.h ---- linux-2.6.21/include/linux/i2c-id.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/linux/i2c-id.h Tue May 8 12:13:31 2007 -@@ -202,6 +202,7 @@ - - /* --- PCA 9564 based algorithms */ - #define I2C_HW_A_ISA 0x1a0000 /* generic ISA Bus interface card */ -+#define I2C_HW_A_PLAT 0x1a0001 /* generic platform_bus interface */ - - /* --- ACPI Embedded controller algorithms */ - #define I2C_HW_ACPI_EC 0x1f0000 -diff -urN -x CVS linux-2.6.21/include/video/atmel_lcdc.h linux-2.6-stable/include/video/atmel_lcdc.h ---- linux-2.6.21/include/video/atmel_lcdc.h Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/include/video/atmel_lcdc.h Thu May 10 12:34:01 2007 -@@ -0,0 +1,196 @@ -+/* -+ * Header file for AT91/AT32 LCD Controller -+ * -+ * Data structure and register user interface -+ * -+ * Copyright (C) 2007 Atmel Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ATMEL_LCDC_H__ -+#define __ATMEL_LCDC_H__ -+ -+ /* LCD Controller info data structure */ -+struct atmel_lcdfb_info { -+ spinlock_t lock; -+ struct fb_info *info; -+ void __iomem *mmio; -+ unsigned long irq_base; -+ -+ unsigned int guard_time; -+ struct platform_device *pdev; -+ struct clk *bus_clk; -+ struct clk *lcdc_clk; -+ unsigned int default_bpp; -+ unsigned int default_lcdcon2; -+ unsigned int default_dmacon; -+ void (*atmel_lcdfb_power_control)(int on); -+ struct fb_monspecs *default_monspecs; -+ u32 pseudo_palette[16]; -+}; -+ -+#define ATMEL_LCDC_DMABADDR1 0x00 -+#define ATMEL_LCDC_DMABADDR2 0x04 -+#define ATMEL_LCDC_DMAFRMPT1 0x08 -+#define ATMEL_LCDC_DMAFRMPT2 0x0c -+#define ATMEL_LCDC_DMAFRMADD1 0x10 -+#define ATMEL_LCDC_DMAFRMADD2 0x14 -+ -+#define ATMEL_LCDC_DMAFRMCFG 0x18 -+#define ATMEL_LCDC_FRSIZE (0x7fffff << 0) -+#define ATMEL_LCDC_BLENGTH_OFFSET 24 -+#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET) -+ -+#define ATMEL_LCDC_DMACON 0x1c -+#define ATMEL_LCDC_DMAEN (0x1 << 0) -+#define ATMEL_LCDC_DMARST (0x1 << 1) -+#define ATMEL_LCDC_DMABUSY (0x1 << 2) -+#define ATMEL_LCDC_DMAUPDT (0x1 << 3) -+#define ATMEL_LCDC_DMA2DEN (0x1 << 4) -+ -+#define ATMEL_LCDC_DMA2DCFG 0x20 -+#define ATMEL_LCDC_ADDRINC_OFFSET 0 -+#define ATMEL_LCDC_ADDRINC (0xffff) -+#define ATMEL_LCDC_PIXELOFF_OFFSET 24 -+#define ATMEL_LCDC_PIXELOFF (0x1f << 24) -+ -+#define ATMEL_LCDC_LCDCON1 0x0800 -+#define ATMEL_LCDC_BYPASS (1 << 0) -+#define ATMEL_LCDC_CLKVAL_OFFSET 12 -+#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) -+#define ATMEL_LCDC_LINCNT (0x7ff << 21) -+ -+#define ATMEL_LCDC_LCDCON2 0x0804 -+#define ATMEL_LCDC_DISTYPE (3 << 0) -+#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) -+#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) -+#define ATMEL_LCDC_DISTYPE_TFT (2 << 0) -+#define ATMEL_LCDC_SCANMOD (1 << 2) -+#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) -+#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) -+#define ATMEL_LCDC_IFWIDTH (3 << 3) -+#define ATMEL_LCDC_IFWIDTH_4 (0 << 3) -+#define ATMEL_LCDC_IFWIDTH_8 (1 << 3) -+#define ATMEL_LCDC_IFWIDTH_16 (2 << 3) -+#define ATMEL_LCDC_PIXELSIZE (7 << 5) -+#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) -+#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) -+#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) -+#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) -+#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) -+#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) -+#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) -+#define ATMEL_LCDC_INVVD (1 << 8) -+#define ATMEL_LCDC_INVVD_NORMAL (0 << 8) -+#define ATMEL_LCDC_INVVD_INVERTED (1 << 8) -+#define ATMEL_LCDC_INVFRAME (1 << 9 ) -+#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) -+#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) -+#define ATMEL_LCDC_INVLINE (1 << 10) -+#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) -+#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) -+#define ATMEL_LCDC_INVCLK (1 << 11) -+#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) -+#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) -+#define ATMEL_LCDC_INVDVAL (1 << 12) -+#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) -+#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) -+#define ATMEL_LCDC_CLKMOD (1 << 15) -+#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) -+#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) -+#define ATMEL_LCDC_MEMOR (1 << 31) -+#define ATMEL_LCDC_MEMOR_BIG (0 << 31) -+#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) -+ -+#define ATMEL_LCDC_TIM1 0x0808 -+#define ATMEL_LCDC_VFP (0xff << 0) -+#define ATMEL_LCDC_VBP_OFFSET 8 -+#define ATMEL_LCDC_VBP (0xff << ATMEL_LCDC_VBP_OFFSET) -+#define ATMEL_LCDC_VPW_OFFSET 16 -+#define ATMEL_LCDC_VPW (0x3f << ATMEL_LCDC_VPW_OFFSET) -+#define ATMEL_LCDC_VHDLY_OFFSET 24 -+#define ATMEL_LCDC_VHDLY (0xf << ATMEL_LCDC_VHDLY_OFFSET) -+ -+#define ATMEL_LCDC_TIM2 0x080c -+#define ATMEL_LCDC_HBP (0xff << 0) -+#define ATMEL_LCDC_HPW_OFFSET 8 -+#define ATMEL_LCDC_HPW (0x3f << ATMEL_LCDC_HPW_OFFSET) -+#define ATMEL_LCDC_HFP_OFFSET 21 -+#define ATMEL_LCDC_HFP (0x7ff << ATMEL_LCDC_HFP_OFFSET) -+ -+#define ATMEL_LCDC_LCDFRMCFG 0x0810 -+#define ATMEL_LCDC_LINEVAL (0x7ff << 0) -+#define ATMEL_LCDC_HOZVAL_OFFSET 21 -+#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) -+ -+#define ATMEL_LCDC_FIFO 0x0814 -+#define ATMEL_LCDC_FIFOTH (0xffff) -+ -+#define ATMEL_LCDC_MVAL 0x0818 -+ -+#define ATMEL_LCDC_DP1_2 0x081c -+#define ATMEL_LCDC_DP4_7 0x0820 -+#define ATMEL_LCDC_DP3_5 0x0824 -+#define ATMEL_LCDC_DP2_3 0x0828 -+#define ATMEL_LCDC_DP5_7 0x082c -+#define ATMEL_LCDC_DP3_4 0x0830 -+#define ATMEL_LCDC_DP4_5 0x0834 -+#define ATMEL_LCDC_DP6_7 0x0838 -+#define ATMEL_LCDC_DP1_2_VAL (0xff) -+#define ATMEL_LCDC_DP4_7_VAL (0xfffffff) -+#define ATMEL_LCDC_DP3_5_VAL (0xfffff) -+#define ATMEL_LCDC_DP2_3_VAL (0xfff) -+#define ATMEL_LCDC_DP5_7_VAL (0xfffffff) -+#define ATMEL_LCDC_DP3_4_VAL (0xffff) -+#define ATMEL_LCDC_DP4_5_VAL (0xfffff) -+#define ATMEL_LCDC_DP6_7_VAL (0xfffffff) -+ -+#define ATMEL_LCDC_PWRCON 0x083c -+#define ATMEL_LCDC_PWR (1 << 0) -+#define ATMEL_LCDC_GUARDT_OFFSET 1 -+#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET) -+#define ATMEL_LCDC_BUSY (1 << 31) -+ -+#define ATMEL_LCDC_CONTRAST_CTR 0x0840 -+#define ATMEL_LCDC_PS (3 << 0) -+#define ATMEL_LCDC_PS_DIV1 (0 << 0) -+#define ATMEL_LCDC_PS_DIV2 (1 << 0) -+#define ATMEL_LCDC_PS_DIV4 (2 << 0) -+#define ATMEL_LCDC_PS_DIV8 (3 << 0) -+#define ATMEL_LCDC_POL (1 << 2) -+#define ATMEL_LCDC_POL_NEGATIVE (0 << 2) -+#define ATMEL_LCDC_POL_POSITIVE (1 << 2) -+#define ATMEL_LCDC_ENA (1 << 3) -+#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) -+#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) -+ -+#define ATMEL_LCDC_CONTRAST_VAL 0x0844 -+#define ATMEL_LCDC_CVAL (0xff) -+ -+#define ATMEL_LCDC_IER 0x0848 -+#define ATMEL_LCDC_IDR 0x084c -+#define ATMEL_LCDC_IMR 0x0850 -+#define ATMEL_LCDC_ISR 0x0854 -+#define ATMEL_LCDC_ICR 0x0858 -+#define ATMEL_LCDC_LNI (1 << 0) -+#define ATMEL_LCDC_LSTLNI (1 << 1) -+#define ATMEL_LCDC_EOFI (1 << 2) -+#define ATMEL_LCDC_UFLWI (1 << 4) -+#define ATMEL_LCDC_OWRI (1 << 5) -+#define ATMEL_LCDC_MERI (1 << 6) -+ -+#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) -+ -+#endif /* __ATMEL_LCDC_H__ */ -diff -urN -x CVS linux-2.6.21/sound/soc/at91/eti_b1_wm8731.c linux-2.6-stable/sound/soc/at91/eti_b1_wm8731.c ---- linux-2.6.21/sound/soc/at91/eti_b1_wm8731.c Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/sound/soc/at91/eti_b1_wm8731.c Tue May 8 12:13:58 2007 -@@ -34,8 +34,7 @@ - #include <sound/soc.h> - #include <sound/soc-dapm.h> - --#include <asm/arch/hardware.h> --#include <asm/arch/at91_pio.h> -+#include <asm/hardware.h> - #include <asm/arch/gpio.h> - - #include "../codecs/wm8731.h" -@@ -48,13 +47,6 @@ - #define DBG(x...) - #endif - --#define AT91_PIO_TF1 (1 << (AT91_PIN_PB6 - PIN_BASE) % 32) --#define AT91_PIO_TK1 (1 << (AT91_PIN_PB7 - PIN_BASE) % 32) --#define AT91_PIO_TD1 (1 << (AT91_PIN_PB8 - PIN_BASE) % 32) --#define AT91_PIO_RD1 (1 << (AT91_PIN_PB9 - PIN_BASE) % 32) --#define AT91_PIO_RK1 (1 << (AT91_PIN_PB10 - PIN_BASE) % 32) --#define AT91_PIO_RF1 (1 << (AT91_PIN_PB11 - PIN_BASE) % 32) -- - static struct clk *pck1_clk; - static struct clk *pllb_clk; - -@@ -277,7 +269,6 @@ - static int __init eti_b1_init(void) - { - int ret; -- u32 ssc_pio_lines; - struct at91_ssc_periph *ssc = eti_b1_dai.cpu_dai->private_data; - - if (!request_mem_region(AT91RM9200_BASE_SSC1, SZ_16K, "soc-audio")) { -@@ -311,19 +302,12 @@ - goto fail_io_unmap; - } - -- ssc_pio_lines = AT91_PIO_TF1 | AT91_PIO_TK1 | AT91_PIO_TD1 -- | AT91_PIO_RD1 /* | AT91_PIO_RK1 */ | AT91_PIO_RF1; -- -- /* Reset all PIO registers and assign lines to peripheral A */ -- at91_sys_write(AT91_PIOB + PIO_PDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_ODR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_IFDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_CODR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_IDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_MDDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_PUDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_ASR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_OWDR, ssc_pio_lines); -+ at91_set_A_periph(AT91_PIN_PB6, 0); /* TF1 */ -+ at91_set_A_periph(AT91_PIN_PB7, 0); /* TK1 */ -+ at91_set_A_periph(AT91_PIN_PB8, 0); /* TD1 */ -+ at91_set_A_periph(AT91_PIN_PB9, 0); /* RD1 */ -+/* at91_set_A_periph(AT91_PIN_PB10, 0);*/ /* RK1 */ -+ at91_set_A_periph(AT91_PIN_PB11, 0); /* RF1 */ - - /* - * Set PCK1 parent to PLLB and its rate to 12 Mhz. diff --git a/target/linux/at91-2.6/patches-2.6.21/001-vlink-machine.patch b/target/linux/at91-2.6/patches-2.6.21/001-vlink-machine.patch deleted file mode 100644 index 1c12db3553..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/001-vlink-machine.patch +++ /dev/null @@ -1,211 +0,0 @@ ---- linux-2.6.21.1.orig/arch/arm/boot/compressed/head-at91rm9200.S 2007-05-28 12:22:29.000000000 +0200 -+++ linux-2.6.21.1/arch/arm/boot/compressed/head-at91rm9200.S 2007-05-28 12:52:16.000000000 +0200 -@@ -61,6 +61,12 @@ - cmp r7, r3 - beq 99f - -+ @ FDL Versalink : 1053 -+ mov r3, #(MACH_TYPE_VLINK & 0xff) -+ orr r3, r3, #(MACH_TYPE_VLINK & 0xff00) -+ cmp r7, r3 -+ beq 99f -+ - @ Ajeco 1ARM : 1075 - mov r3, #(MACH_TYPE_ONEARM & 0xff) - orr r3, r3, #(MACH_TYPE_ONEARM & 0xff00) ---- linux-2.6.21.1.orig/arch/arm/mach-at91/board-vlink.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.21.1/arch/arm/mach-at91/board-vlink.c 2007-05-28 13:09:54.000000000 +0200 -@@ -0,0 +1,160 @@ -+/* -+ * linux/arch/arm/mach-at91/board-vlink.c -+ * -+ * Copyright (C) 2005 SAN People -+ * Copyright (C) 2006,2007 Guthrie Consulting -+ * -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/types.h> -+#include <linux/init.h> -+#include <linux/mm.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+#include <linux/spi/spi.h> -+#include <linux/mtd/physmap.h> -+ -+#include <asm/hardware.h> -+#include <asm/setup.h> -+#include <asm/mach-types.h> -+#include <asm/irq.h> -+ -+#include <asm/mach/arch.h> -+#include <asm/mach/map.h> -+#include <asm/mach/irq.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+#include <asm/arch/at91rm9200_mc.h> -+ -+#include "generic.h" -+ -+ -+/* -+ * Serial port configuration. -+ * 0 .. 3 = USART0 .. USART3 -+ * 4 = DBGU -+ */ -+static struct at91_uart_config __initdata vlink_uart_config = { -+ .console_tty = 0, /* ttyS0 */ -+ .nr_tty = 5, -+ .tty_map = { 4, 1, 0, 3, 2 } /* ttyS0, ..., ttyS4 */ -+}; -+ -+static void __init vlink_map_io(void) -+{ -+ /* Initialize processor: 18.432 MHz crystal */ -+ at91rm9200_initialize(18432000, AT91RM9200_PQFP); -+ -+ /* Setup the LEDs */ -+// at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); -+ -+ /* Setup the serial ports and console */ -+ at91_init_serial(&vlink_uart_config); -+} -+ -+static void __init vlink_init_irq(void) -+{ -+ at91rm9200_init_interrupts(NULL); -+} -+ -+static struct at91_eth_data __initdata vlink_eth_data = { -+ .phy_irq_pin = AT91_PIN_PC4, -+ .is_rmii = 1, -+}; -+ -+static struct at91_usbh_data __initdata vlink_usbh_data = { -+ .ports = 1, -+}; -+ -+static struct at91_udc_data __initdata vlink_udc_data = { -+ .vbus_pin = AT91_PIN_PD4, -+ .pullup_pin = AT91_PIN_PD5, -+}; -+ -+static struct at91_mmc_data __initdata vlink_mmc_data = { -+// .det_pin = AT91_PIN_PB27, -+ .slot_b = 0, -+ .wire4 = 1, -+// .wp_pin = AT91_PIN_PA17, -+}; -+ -+static struct spi_board_info vlink_spi_devices[] = { -+ { /* DataFlash chip */ -+ .modalias = "mtd_dataflash", -+ .chip_select = 0, -+ .max_speed_hz = 15 * 1000 * 1000, -+ }, -+#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD -+ { /* DataFlash card */ -+ .modalias = "mtd_dataflash", -+ .chip_select = 3, -+ .max_speed_hz = 15 * 1000 * 1000, -+ }, -+#endif -+}; -+ -+static struct at91_gpio_led vlink_leds[] = { -+ { -+ .name = "led0", -+ .gpio = AT91_PIN_PB1, -+ .trigger = "heartbeat", -+ }, -+ { -+ .name = "led1", -+ .gpio = AT91_PIN_PB2, -+ .trigger = "timer", -+ } -+}; -+ -+static void __init vlink_board_init(void) -+{ -+ /* Serial */ -+ at91_add_device_serial(); -+ /* Ethernet */ -+ at91_add_device_eth(&vlink_eth_data); -+ /* USB Host */ -+ at91_add_device_usbh(&vlink_usbh_data); -+ /* USB Device */ -+ at91_add_device_udc(&vlink_udc_data); -+ at91_set_multi_drive(vlink_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ -+ /* I2C */ -+ at91_add_device_i2c(); -+ /* SPI */ -+ at91_add_device_spi(vlink_spi_devices, ARRAY_SIZE(vlink_spi_devices)); -+#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD -+ /* DataFlash card */ -+// at91_set_gpio_output(AT91_PIN_PB22, 0); -+#else -+ /* MMC */ -+// at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ -+ at91_add_device_mmc(0, &vlink_mmc_data); -+#endif -+ /* LEDs */ -+ at91_gpio_leds(vlink_leds, ARRAY_SIZE(vlink_leds)); -+} -+ -+MACHINE_START(VLINK, "FDL VersaLink") -+ /* Maintainer: Guthrie Consulting */ -+ .phys_io = AT91_BASE_SYS, -+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, -+ .boot_params = AT91_SDRAM_BASE + 0x100, -+ .timer = &at91rm9200_timer, -+ .map_io = vlink_map_io, -+ .init_irq = vlink_init_irq, -+ .init_machine = vlink_board_init, -+MACHINE_END ---- linux-2.6.21.1.orig/arch/arm/mach-at91/Kconfig 2007-05-28 12:22:29.000000000 +0200 -+++ linux-2.6.21.1/arch/arm/mach-at91/Kconfig 2007-05-28 13:11:45.000000000 +0200 -@@ -96,6 +96,12 @@ - help - Select this if you are using Promwad's Chub board. - -+config MACH_VLINK -+ bool "Figment Design Labs VersaLink" -+ depends on ARCH_AT91RM9200 -+ help -+ Select this if you are using FDL's VersaLink board -+ - endif - - # ---------------------------------------------------------- ---- linux-2.6.21.1.orig/arch/arm/mach-at91/Makefile 2007-05-28 12:22:29.000000000 +0200 -+++ linux-2.6.21.1/arch/arm/mach-at91/Makefile 2007-05-28 13:13:15.000000000 +0200 -@@ -29,6 +29,7 @@ - obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o - obj-$(CONFIG_MACH_KAFA) += board-kafa.o - obj-$(CONFIG_MACH_CHUB) += board-chub.o -+obj-$(CONFIG_MACH_VLINK) += board-vlink.o - - # AT91SAM9260 board-specific support - obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o -@@ -51,6 +52,7 @@ - led-$(CONFIG_MACH_CSB637) += leds.o - led-$(CONFIG_MACH_KB9200) += leds.o - led-$(CONFIG_MACH_KAFA) += leds.o -+led-$(CONFIG_MACH_VLINK) += leds.o - obj-$(CONFIG_LEDS) += $(led-y) - - # VGA support diff --git a/target/linux/at91-2.6/patches-2.6.21/002-led-driver.patch b/target/linux/at91-2.6/patches-2.6.21/002-led-driver.patch deleted file mode 100644 index e78ed443c0..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/002-led-driver.patch +++ /dev/null @@ -1,189 +0,0 @@ -diff -urN linux-2.6.21.1.orig/arch/arm/mach-at91/board-vlink.c linux-2.6.21.1/arch/arm/mach-at91/board-vlink.c ---- linux-2.6.21.1.orig/arch/arm/mach-at91/board-vlink.c 2007-05-28 13:33:41.000000000 +0200 -+++ linux-2.6.21.1/arch/arm/mach-at91/board-vlink.c 2007-05-28 14:43:28.000000000 +0200 -@@ -61,7 +61,7 @@ - at91rm9200_initialize(18432000, AT91RM9200_PQFP); - - /* Setup the LEDs */ --// at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); -+ at91_init_leds(AT91_PIN_PC14, AT91_PIN_PC15); - - /* Setup the serial ports and console */ - at91_init_serial(&vlink_uart_config); -@@ -81,10 +81,12 @@ - .ports = 1, - }; - -+/* - static struct at91_udc_data __initdata vlink_udc_data = { - .vbus_pin = AT91_PIN_PD4, - .pullup_pin = AT91_PIN_PD5, - }; -+*/ - - static struct at91_mmc_data __initdata vlink_mmc_data = { - // .det_pin = AT91_PIN_PB27, -@@ -108,18 +110,19 @@ - #endif - }; - --static struct at91_gpio_led vlink_leds[] = { -+/*static struct at91_gpio_led vlink_leds[] = { - { - .name = "led0", -- .gpio = AT91_PIN_PB1, -+ .gpio = AT91_PIN_PC14, - .trigger = "heartbeat", - }, - { - .name = "led1", -- .gpio = AT91_PIN_PB2, -+ .gpio = AT91_PIN_PC15, - .trigger = "timer", - } - }; -+*/ - - static void __init vlink_board_init(void) - { -@@ -130,8 +133,8 @@ - /* USB Host */ - at91_add_device_usbh(&vlink_usbh_data); - /* USB Device */ -- at91_add_device_udc(&vlink_udc_data); -- at91_set_multi_drive(vlink_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ -+// at91_add_device_udc(&vlink_udc_data); -+// at91_set_multi_drive(vlink_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ - /* I2C */ - at91_add_device_i2c(); - /* SPI */ -@@ -145,7 +148,7 @@ - at91_add_device_mmc(0, &vlink_mmc_data); - #endif - /* LEDs */ -- at91_gpio_leds(vlink_leds, ARRAY_SIZE(vlink_leds)); -+// at91_gpio_leds(vlink_leds, ARRAY_SIZE(vlink_leds)); - } - - MACHINE_START(VLINK, "FDL VersaLink") -diff -urN linux-2.6.21.1.orig/arch/arm/mach-at91/Makefile linux-2.6.21.1/arch/arm/mach-at91/Makefile ---- linux-2.6.21.1.orig/arch/arm/mach-at91/Makefile 2007-05-28 13:13:15.000000000 +0200 -+++ linux-2.6.21.1/arch/arm/mach-at91/Makefile 2007-05-28 14:19:06.000000000 +0200 -@@ -52,7 +52,7 @@ - led-$(CONFIG_MACH_CSB637) += leds.o - led-$(CONFIG_MACH_KB9200) += leds.o - led-$(CONFIG_MACH_KAFA) += leds.o --led-$(CONFIG_MACH_VLINK) += leds.o -+led-$(CONFIG_MACH_VLINK) += vlink_leds.o - obj-$(CONFIG_LEDS) += $(led-y) - - # VGA support -diff -urN linux-2.6.21.1.orig/arch/arm/mach-at91/vlink_leds.c linux-2.6.21.1/arch/arm/mach-at91/vlink_leds.c ---- linux-2.6.21.1.orig/arch/arm/mach-at91/vlink_leds.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.21.1/arch/arm/mach-at91/vlink_leds.c 2007-05-28 14:41:03.000000000 +0200 -@@ -0,0 +1,105 @@ -+/* -+ * LED driver for Atmel AT91-based boards. -+ * -+ * Copyright (C) SAN People (Pty) Ltd -+ * Modified for FDL VersaLink Copyright (C) Guthrie Consulting -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+*/ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/init.h> -+ -+#include <asm/mach-types.h> -+#include <asm/leds.h> -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+ -+ -+static inline void at91_led_on(unsigned int led) -+{ -+ at91_set_gpio_value(led, 0); -+} -+ -+static inline void at91_led_off(unsigned int led) -+{ -+ at91_set_gpio_value(led, 1); -+} -+ -+static inline void at91_led_toggle(unsigned int led) -+{ -+ unsigned long is_off = at91_get_gpio_value(led); -+ if (is_off) { -+ at91_led_on(led); -+ at91_led_off(at91_leds_cpu); -+ } -+ else { -+ at91_led_on(at91_leds_cpu); -+ at91_led_off(led); -+ } -+} -+ -+ -+/* -+ * Handle LED events. -+ */ -+ -+/* -+ * VersaLink has a single bi-coloured LED which changes colour when the -+ * polarity is reversed -+ */ -+static void at91_leds_event(led_event_t evt) -+{ -+ unsigned long flags; -+ -+ local_irq_save(flags); -+ -+ switch(evt) { -+ case led_start: /* System startup */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+ -+ case led_stop: /* System stop / suspend */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+ -+#ifdef CONFIG_LEDS_TIMER -+ case led_timer: /* Every 50 timer ticks */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+#endif -+ -+#ifdef CONFIG_LEDS_CPU -+ case led_idle_start: /* Entering idle state */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+ -+ case led_idle_end: /* Exit idle state */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+#endif -+ -+ default: -+ break; -+ } -+ -+ local_irq_restore(flags); -+} -+ -+ -+static int __init leds_init(void) -+{ -+ if (!at91_leds_timer || !at91_leds_cpu) -+ return -ENODEV; -+ -+ leds_event = at91_leds_event; -+ -+ leds_event(led_start); -+ return 0; -+} -+ -+__initcall(leds_init); diff --git a/target/linux/at91-2.6/patches-2.6.21/003-gpio-driver.patch b/target/linux/at91-2.6/patches-2.6.21/003-gpio-driver.patch deleted file mode 100644 index aa5a2e32e1..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/003-gpio-driver.patch +++ /dev/null @@ -1,355 +0,0 @@ ---- linux-2.6.21.1.orig/arch/arm/mach-at91/gpio.c 2007-04-27 23:49:26.000000000 +0200 -+++ linux-2.6.21.1/arch/arm/mach-at91/gpio.c 2007-05-28 15:30:48.000000000 +0200 -@@ -27,6 +27,7 @@ - - static struct at91_gpio_bank *gpio; - static int gpio_banks; -+static u32 pio_gpio_pin[4] = { 0, 0, 0, 0 }; - - - static inline void __iomem *pin_to_controller(unsigned pin) -@@ -71,9 +72,13 @@ - { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); -+ int bank = (pin - PIN_BASE) / 32; - - if (!pio) - return -EINVAL; -+ -+ pio_gpio_pin[bank] |= mask; -+ - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_PER); -@@ -130,10 +135,13 @@ - { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); -+ int bank = (pin - PIN_BASE) / 32; - - if (!pio) - return -EINVAL; - -+ pio_gpio_pin[bank] |= mask; -+ - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_ODR); -@@ -151,10 +159,13 @@ - { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); -+ int bank = (pin - PIN_BASE) / 32; - - if (!pio) - return -EINVAL; - -+ pio_gpio_pin[bank] |= mask; -+ - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + PIO_PUDR); - __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); -@@ -262,6 +273,18 @@ - } - EXPORT_SYMBOL(at91_get_gpio_value); - -+int at91_is_pin_gpio(unsigned pin) -+{ -+ void __iomem *pio = pin_to_controller(pin); -+ unsigned mask = pin_to_mask(pin); -+ int bank = (pin - PIN_BASE) / 32; -+ -+ if (!pio) -+ return -EINVAL; -+ return (pio_gpio_pin[bank] & mask) != 0; -+} -+EXPORT_SYMBOL(at91_is_pin_gpio); -+ - /*--------------------------------------------------------------------------*/ - - #ifdef CONFIG_PM ---- linux-2.6.21.1.orig/drivers/char/Kconfig 2007-05-28 12:22:29.000000000 +0200 -+++ linux-2.6.21.1/drivers/char/Kconfig 2007-05-28 15:37:43.000000000 +0200 -@@ -1087,5 +1087,12 @@ - The SPI driver gives user mode access to this serial - bus on the AT91RM9200 processor. - -+config AT91_VLIO -+ tristate "Versalink LED and GPIO interface" -+ depends on ARCH_AT91RM9200 && MACH_VLINK -+ default n -+ help -+ Provides a handler GPIO's in userspace -+ - endmenu - ---- linux-2.6.21.1.orig/drivers/char/Makefile 2007-05-28 12:22:29.000000000 +0200 -+++ linux-2.6.21.1/drivers/char/Makefile 2007-05-28 15:38:11.000000000 +0200 -@@ -95,6 +95,7 @@ - obj-$(CONFIG_TELCLOCK) += tlclk.o - obj-$(CONFIG_AT91_SPI) += at91_spi.o - obj-$(CONFIG_AT91_SPIDEV) += at91_spidev.o -+obj-$(CONFIG_AT91_VLIO) += vlink_giu.o - - obj-$(CONFIG_WATCHDOG) += watchdog/ - obj-$(CONFIG_MWAVE) += mwave/ ---- linux-2.6.21.1.orig/drivers/char/vlink_giu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.21.1/drivers/char/vlink_giu.c 2007-05-28 15:39:47.000000000 +0200 -@@ -0,0 +1,256 @@ -+/* -+ * Driver for FDL Versalink GPIO -+ * -+ * Copyright (C) 2005 Guthrie Consulting -+ * Author: Hamish Guthrie <hamish@prodigi.ch> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/module.h> -+#include <linux/moduleparam.h> -+#include <linux/init.h> -+#include <linux/platform_device.h> -+ -+#include <linux/kernel.h> -+#include <linux/slab.h> -+#include <linux/fs.h> -+#include <linux/errno.h> -+#include <linux/init.h> -+#include <linux/types.h> -+#include <linux/proc_fs.h> -+#include <linux/fcntl.h> -+#include <linux/seq_file.h> -+#include <linux/cdev.h> -+#include <asm/arch/gpio.h> -+#include <asm/uaccess.h> -+ -+static int major; /* default is dynamic major device number */ -+module_param(major, int, 0); -+MODULE_PARM_DESC(major, "Major device number"); -+ -+#define VIO_NR_DEVS 96 -+ -+struct vio_dev { -+ struct cdev cdev; -+}; -+ -+struct vio_dev *vio_devices; -+static struct class *vio_class; -+ -+static ssize_t gpio_read(struct file *file, char __user *buf, size_t len, -+ loff_t *ppos) -+{ -+ unsigned int pin; -+ int retval; -+ char value = '0'; -+ -+ pin = iminor(file->f_dentry->d_inode); -+ -+ retval = at91_get_gpio_value(PIN_BASE + pin); -+ if (retval < 0) -+ return -EFAULT; -+ -+ value = retval + 0x30; -+ if (put_user(value, buf)) -+ return -EFAULT; -+ -+ return 1; -+} -+ -+static ssize_t gpio_write(struct file *file, const char __user *data, -+ size_t len, loff_t *ppos) -+{ -+ unsigned int pin; -+ size_t i; -+ char c; -+ int retval = 0; -+ -+ pin = iminor(file->f_dentry->d_inode); -+ -+ for (i = 0; i < len; i++) { -+ if (get_user(c, data + i)) -+ return -EFAULT; -+ -+ switch (c) { -+ case '0': -+ case '1': -+ retval = at91_set_gpio_value(PIN_BASE + pin, (int)c - 0x30); -+ if (retval < 0) -+ return -EFAULT; -+ break; -+ default: -+ break; -+ } -+ -+ if (retval < 0) -+ break; -+ } -+ -+ return i; -+} -+ -+static int gpio_open(struct inode *inode, struct file *file) -+{ -+ return nonseekable_open(inode, file); -+} -+ -+static int gpio_release(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+static struct file_operations vio_fops = { -+ .owner = THIS_MODULE, -+ .read = gpio_read, -+ .write = gpio_write, -+ .open = gpio_open, -+ .release = gpio_release, -+}; -+ -+static void vio_setup_cdev(struct vio_dev *dev, int index) -+{ -+ int err, devno = MKDEV(major, index); -+ -+ cdev_init(&dev->cdev, &vio_fops); -+ dev->cdev.owner = THIS_MODULE; -+ dev->cdev.ops = &vio_fops; -+ err = cdev_add (&dev->cdev, devno, 1); -+ if (err) -+ printk(KERN_NOTICE "vio: Error %d adding vio%d", err, index); -+} -+ -+static int vio_remove(struct platform_device *dev) -+{ -+ int i; -+ dev_t devno = MKDEV(major, 0); -+ -+ if (vio_devices) { -+ for(i=0; i<VIO_NR_DEVS; i++) { -+ int iodev = at91_is_pin_gpio(PIN_BASE + i); -+ if (iodev) { -+ cdev_del(&vio_devices[i].cdev); -+ class_device_destroy(vio_class, MKDEV(major, i)); -+ } -+ } -+ kfree(vio_devices); -+ } -+ -+ class_destroy(vio_class); -+ unregister_chrdev_region(devno, VIO_NR_DEVS); -+ -+ platform_set_drvdata(dev, NULL); -+ -+ return 0; -+} -+ -+static int vio_probe(struct platform_device *dev) -+{ -+ int retval, i, j; -+ dev_t vdev = 0; -+ -+ if (major) { -+ vdev = MKDEV(major, 0); -+ retval = register_chrdev_region(vdev, VIO_NR_DEVS, "vio"); -+ } else { -+ retval = alloc_chrdev_region(&vdev, 0, VIO_NR_DEVS, "vio"); -+ major = MAJOR(vdev); -+ } -+ if (retval < 0) { -+ printk(KERN_WARNING "vio: can't get major %d\n", major); -+ return retval; -+ } -+ -+ if (major == 0) { -+ major = retval; -+ printk(KERN_INFO "vio: major number %d\n", major); -+ } -+ -+ vio_class = class_create(THIS_MODULE, "vio"); -+ -+ if (IS_ERR(vio_class)) { -+ printk(KERN_ERR "vio: Error creating vio class\n"); -+ vio_remove(dev); -+ return PTR_ERR(vio_class); -+ } -+ -+ vio_devices = kmalloc(VIO_NR_DEVS * sizeof(struct vio_dev), GFP_KERNEL); -+ if (!vio_devices) { -+ retval = -ENOMEM; -+ goto fail; -+ } -+ memset(vio_devices, 0, VIO_NR_DEVS * sizeof(struct vio_dev)); -+ -+ for (i=0; i<VIO_NR_DEVS/32; i++) -+ for(j=0; j<32; j++) { -+ int iodev = at91_is_pin_gpio(PIN_BASE + i*32 + j); -+ if (iodev) { -+ vio_setup_cdev(&vio_devices[i*32 + j], i*32 + j); -+ class_device_create(vio_class, NULL, MKDEV(major, i*32 + j), NULL, -+ "vio%c%d", i + 'A', j); -+ } -+ } -+ -+ platform_set_drvdata(dev, vio_devices); -+ -+ return 0; -+ -+fail: -+ vio_remove(dev); -+ return retval; -+} -+ -+static struct platform_device *vio_platform_device; -+ -+static struct platform_driver vio_driver = { -+ .probe = vio_probe, -+ .remove = vio_remove, -+ .driver = { -+ .name = "vio", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init vio_init(void) -+{ -+ int retval; -+ -+ vio_platform_device = platform_device_register_simple("vio", -1, NULL, 0); -+ if (IS_ERR(vio_platform_device)) { -+ printk(KERN_WARNING "vio: device registration failed\n"); -+ return PTR_ERR(vio_platform_device); -+ } -+ -+ retval = platform_driver_register(&vio_driver); -+ if (retval < 0) { -+ printk(KERN_WARNING "vio: driver registration failed\n"); -+ platform_device_unregister(vio_platform_device); -+ } -+ -+ return retval; -+} -+ -+static void __exit vio_exit(void) -+{ -+ platform_driver_unregister(&vio_driver); -+ platform_device_unregister(vio_platform_device); -+} -+ -+module_init(vio_init); -+module_exit(vio_exit); -+ -+MODULE_AUTHOR("Hamish Guthrie <hamish@prodigi.ch>"); -+MODULE_DESCRIPTION("FDL Versalink GPIO Driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/at91-2.6/patches-2.6.21/006-change-gpios.patch b/target/linux/at91-2.6/patches-2.6.21/006-change-gpios.patch deleted file mode 100644 index 97a4a8d2f5..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/006-change-gpios.patch +++ /dev/null @@ -1,36 +0,0 @@ ---- linux-2.6.21.1.orig/arch/arm/mach-at91/board-vlink.c 2007-05-28 15:53:31.000000000 +0200 -+++ linux-2.6.21.1/arch/arm/mach-at91/board-vlink.c 2007-05-28 15:58:46.000000000 +0200 -@@ -149,6 +149,33 @@ - #endif - /* LEDs */ - // at91_gpio_leds(vlink_leds, ARRAY_SIZE(vlink_leds)); -+ -+/* Other LED's */ -+ at91_set_gpio_output(AT91_PIN_PC7, 1); // LED FRONT AP1 -+ at91_set_gpio_output(AT91_PIN_PC8, 1); // LED FRONT BP1 -+ at91_set_gpio_output(AT91_PIN_PB14, 1); // LED BACK AP1 -+ at91_set_gpio_output(AT91_PIN_PB15, 1); // LED BACK BP1 -+ at91_set_gpio_output(AT91_PIN_PB16, 1); // LED BACK AP2 -+ at91_set_gpio_output(AT91_PIN_PB17, 1); // LED BACK BP2 -+ -+/* SIM Cards */ -+ at91_set_gpio_output(AT91_PIN_PB9, 1); // ENBSC3 -+ at91_set_gpio_output(AT91_PIN_PB10, 1); // ENBSC2 -+ at91_set_gpio_output(AT91_PIN_PB11, 1); // ENBSC1 -+ -+/* GSM Module Control */ -+ at91_set_gpio_output(AT91_PIN_PB12, 1); // GSMONOFF -+ -+/* Test jig presence detection */ -+ at91_set_gpio_input(AT91_PIN_PB8, 1); // JIGPRESENT -+ -+/* Power indicator */ -+ at91_set_gpio_input(AT91_PIN_PB22, 1); // PWR_IND -+ -+/* USB Device control */ -+ at91_set_gpio_input(AT91_PIN_PB27, 1); // UDB_CNX -+ at91_set_gpio_output(AT91_PIN_PB28, 1); // UDB_PUP -+ - } - - MACHINE_START(VLINK, "FDL VersaLink") diff --git a/target/linux/at91-2.6/patches-2.6.21/007-mtd-partition.patch b/target/linux/at91-2.6/patches-2.6.21/007-mtd-partition.patch deleted file mode 100644 index 98bec0dad8..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/007-mtd-partition.patch +++ /dev/null @@ -1,36 +0,0 @@ ---- linux-2.6.21.1.orig/drivers/mtd/devices/at91_dataflash.c 2007-05-28 12:22:29.000000000 +0200 -+++ linux-2.6.21.1/drivers/mtd/devices/at91_dataflash.c 2007-05-28 16:10:21.000000000 +0200 -@@ -173,7 +173,7 @@ - }; - #endif - --static const char *part_probes[] = { "cmdlinepart", NULL, }; -+static const char *part_probes[] = { "cmdlinepart", "at91part", NULL, }; - - #endif - ---- linux-2.6.21.1.orig/drivers/mtd/Kconfig 2007-05-28 12:22:09.000000000 +0200 -+++ linux-2.6.21.1/drivers/mtd/Kconfig 2007-05-28 16:09:16.000000000 +0200 -@@ -157,6 +157,12 @@ - for your particular device. It won't happen automatically. The - 'armflash' map driver (CONFIG_MTD_ARMFLASH) does this, for example. - -+config MTD_AT91_PARTS -+ tristate "Atmel AT91 partitioning support" -+ depends on MTD_PARTITIONS && ARCH_AT91RM9200 && AT91_SPI -+ ---help--- -+ Atmel AT91 partitioning support -+ - comment "User Modules And Translation Layers" - depends on MTD - ---- linux-2.6.21.1.orig/drivers/mtd/Makefile 2007-04-27 23:49:26.000000000 +0200 -+++ linux-2.6.21.1/drivers/mtd/Makefile 2007-05-28 16:09:55.000000000 +0200 -@@ -12,6 +12,7 @@ - obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o - obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o - obj-$(CONFIG_MTD_AFS_PARTS) += afs.o -+obj-$(CONFIG_MTD_AT91_PARTS) += at91part.o - - # 'Users' - code which presents functionality to userspace. - obj-$(CONFIG_MTD_CHAR) += mtdchar.o diff --git a/target/linux/at91-2.6/patches-2.6.21/008-fdl-serial.patch b/target/linux/at91-2.6/patches-2.6.21/008-fdl-serial.patch deleted file mode 100644 index 42589197be..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/008-fdl-serial.patch +++ /dev/null @@ -1,160 +0,0 @@ ---- linux-2.6.21.1.orig/drivers/serial/atmel_serial.c 2007-05-28 12:22:29.000000000 +0200 -+++ linux-2.6.21.1/drivers/serial/atmel_serial.c 2007-05-28 16:39:09.000000000 +0200 -@@ -174,7 +174,35 @@ - at91_set_gpio_value(AT91_PIN_PA21, 0); - else - at91_set_gpio_value(AT91_PIN_PA21, 1); -+ -+ /* -+ * FDL VersaLink adds GPIOS to provide full modem control on -+ * USART 0 - Drive DTR and RI pins manually -+ */ -+ if (mctrl & TIOCM_DTR) -+ at91_set_gpio_value(AT91_PIN_PB6, 0); -+ else -+ at91_set_gpio_value(AT91_PIN_PB6, 1); -+ if (mctrl & TIOCM_RI) -+ at91_set_gpio_value(AT91_PIN_PB7, 0); -+ else -+ at91_set_gpio_value(AT91_PIN_PB7, 1); - } -+ -+ /* -+ * FDL VersaLink adds GPIOS to provide full modem control on -+ * USART 3 - Drive DTR and RI pins manually -+ */ -+ if (port->mapbase == AT91RM9200_BASE_US3) { -+ if (mctrl & TIOCM_DTR) -+ at91_set_gpio_value(AT91_PIN_PB29, 0); -+ else -+ at91_set_gpio_value(AT91_PIN_PB29, 1); -+ if (mctrl & TIOCM_RI) -+ at91_set_gpio_value(AT91_PIN_PB2, 0); -+ else -+ at91_set_gpio_value(AT91_PIN_PB2, 1); -+ } - } - #endif - -@@ -211,8 +239,10 @@ - /* - * The control signals are active low. - */ -- if (!(status & ATMEL_US_DCD)) -- ret |= TIOCM_CD; -+ -+ if (!(port->mapbase == AT91RM9200_BASE_US0 || port->mapbase == AT91RM9200_BASE_US3)) -+ if (!(status & ATMEL_US_DCD)) -+ ret |= TIOCM_CD; - if (!(status & ATMEL_US_CTS)) - ret |= TIOCM_CTS; - if (!(status & ATMEL_US_DSR)) -@@ -220,6 +250,16 @@ - if (!(status & ATMEL_US_RI)) - ret |= TIOCM_RI; - -+ /* -+ * Read the GPIO's for the FDL VersaLink special case -+ */ -+ if (port->mapbase == AT91RM9200_BASE_US0) -+ if (!(at91_get_gpio_value(AT91_PIN_PA19))) -+ ret |= TIOCM_CD; -+ if (port->mapbase == AT91RM9200_BASE_US3) -+ if (!(at91_get_gpio_value(AT91_PIN_PA24))) -+ ret |= TIOCM_CD; -+ - return ret; - } - -@@ -511,6 +551,34 @@ - } - - /* -+ * USART0 DCD Interrupt handler -+ */ -+ -+static irqreturn_t atmel_u0_DCD_interrupt(int irq, void *dev_id) -+{ -+ struct uart_port *port = dev_id; -+ int status = at91_get_gpio_value(irq); -+ -+ uart_handle_dcd_change(port, !(status)); -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * USART3 DCD Interrupt handler -+ */ -+ -+static irqreturn_t atmel_u3_DCD_interrupt(int irq, void *dev_id) -+{ -+ struct uart_port *port = dev_id; -+ int status = at91_get_gpio_value(irq); -+ -+ uart_handle_dcd_change(port, !(status)); -+ -+ return IRQ_HANDLED; -+} -+ -+/* - * Interrupt handler - */ - static irqreturn_t atmel_interrupt(int irq, void *dev_id) -@@ -587,6 +655,23 @@ - return retval; - } - -+ if (port->mapbase == AT91RM9200_BASE_US0) { -+ retval = request_irq(AT91_PIN_PA19, atmel_u0_DCD_interrupt, 0, "atmel_serial", port); -+ if (retval) { -+ printk("atmel_serial: atmel_startup - Can't get u0DCD irq\n"); -+ free_irq(port->irq, port); -+ return retval; -+ } -+ } -+ if (port->mapbase == AT91RM9200_BASE_US3) { -+ retval = request_irq(AT91_PIN_PA24, atmel_u3_DCD_interrupt, 0, "atmel_serial", port); -+ if (retval) { -+ printk("atmel_serial: atmel_startup - Can't get u3DCD irq\n"); -+ free_irq(port->irq, port); -+ return retval; -+ } -+ } -+ - /* - * Initialize DMA (if necessary) - */ -@@ -603,6 +688,10 @@ - kfree(atmel_port->pdc_rx[0].buf); - } - free_irq(port->irq, port); -+ if (port->mapbase == AT91RM9200_BASE_US0) -+ free_irq(AT91_PIN_PA19, port); -+ if (port->mapbase == AT91RM9200_BASE_US3) -+ free_irq(AT91_PIN_PA24, port); - return -ENOMEM; - } - pdc->dma_addr = dma_map_single(port->dev, pdc->buf, PDC_BUFFER_SIZE, DMA_FROM_DEVICE); -@@ -636,6 +725,10 @@ - retval = atmel_open_hook(port); - if (retval) { - free_irq(port->irq, port); -+ if (port->mapbase == AT91RM9200_BASE_US0) -+ free_irq(AT91_PIN_PA19, port); -+ if (port->mapbase == AT91RM9200_BASE_US3) -+ free_irq(AT91_PIN_PA24, port); - return retval; - } - } -@@ -701,6 +794,10 @@ - * Free the interrupt - */ - free_irq(port->irq, port); -+ if (port->mapbase == AT91RM9200_BASE_US0) -+ free_irq(AT91_PIN_PA19, port); -+ if (port->mapbase == AT91RM9200_BASE_US3) -+ free_irq(AT91_PIN_PA24, port); - - /* - * If there is a specific "close" function (to unregister diff --git a/target/linux/at91-2.6/patches-2.6.21/009-fdl-uartinit.patch b/target/linux/at91-2.6/patches-2.6.21/009-fdl-uartinit.patch deleted file mode 100644 index f2491f3496..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/009-fdl-uartinit.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- linux-2.6.21.1.orig/arch/arm/mach-at91/at91rm9200_devices.c 2007-05-28 12:22:29.000000000 +0200 -+++ linux-2.6.21.1/arch/arm/mach-at91/at91rm9200_devices.c 2007-05-28 16:44:36.000000000 +0200 -@@ -618,7 +618,6 @@ - - - #if defined(CONFIG_NEW_LEDS) -- - static struct platform_device at91_leds = { - .name = "at91_leds", - .id = -1, -@@ -724,6 +723,10 @@ - * We need to drive the pin manually. Default is off (RTS is active low). - */ - at91_set_gpio_output(AT91_PIN_PA21, 1); -+ at91_set_gpio_output(AT91_PIN_PB6, 1); /* DTR0 */ -+ at91_set_gpio_output(AT91_PIN_PB7, 1); /* RI0 */ -+ at91_set_gpio_input(AT91_PIN_PA19, 1); /* DCD0 */ -+ at91_set_deglitch(AT91_PIN_PA19, 1); - } - - static struct resource uart1_resources[] = { -@@ -835,6 +838,12 @@ - { - at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */ - at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */ -+ at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */ -+ at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */ -+ at91_set_gpio_output(AT91_PIN_PB29, 1); /* DTR0 */ -+ at91_set_gpio_output(AT91_PIN_PB2, 1); /* RI0 */ -+ at91_set_gpio_input(AT91_PIN_PA24, 1); /* DCD0 */ -+ at91_set_deglitch(AT91_PIN_PA24, 1); - } - - struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ diff --git a/target/linux/at91-2.6/patches-2.6.21/010-dm9161a-phyfix.patch b/target/linux/at91-2.6/patches-2.6.21/010-dm9161a-phyfix.patch deleted file mode 100644 index 9ad8c42530..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/010-dm9161a-phyfix.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- linux-2.6.21.1/drivers/net/arm/at91_ether.c.old 2007-06-04 18:15:49.000000000 +0200 -+++ linux-2.6.21.1/drivers/net/arm/at91_ether.c 2007-06-04 18:10:36.000000000 +0200 -@@ -146,6 +146,7 @@ - struct at91_private *lp = netdev_priv(dev); - unsigned int bmsr, bmcr, lpa, mac_cfg; - unsigned int speed, duplex; -+ unsigned long timeout = jiffies + HZ; - - if (!mii_link_ok(&lp->mii)) { /* no link */ - netif_carrier_off(dev); -@@ -158,8 +159,15 @@ - read_phy(lp->phy_address, MII_BMSR, &bmsr); - read_phy(lp->phy_address, MII_BMCR, &bmcr); - if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ -- if (!(bmsr & BMSR_ANEGCOMPLETE)) -- return; /* Do nothing - another interrupt generated when negotiation complete */ -+ while (!(bmsr & BMSR_ANEGCOMPLETE)) { -+ if (time_after(jiffies, timeout)) { -+ printk("at91_ether: Auto-negotiate timeout\n"); -+ return; -+ } -+ read_phy(lp->phy_address, MII_BMSR, &bmsr); -+ read_phy(lp->phy_address, MII_BMCR, &bmcr); -+ cpu_relax(); -+ } - - read_phy(lp->phy_address, MII_LPA, &lpa); - if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; diff --git a/target/linux/at91-2.6/patches-2.6.21/011-vlink-resetfix.patch b/target/linux/at91-2.6/patches-2.6.21/011-vlink-resetfix.patch deleted file mode 100644 index 78ff38481e..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/011-vlink-resetfix.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- linux-2.6.21.1.old/arch/arm/mach-at91/board-vlink.c 2007-06-04 15:45:19.000000000 +0200 -+++ linux-2.6.21.1/arch/arm/mach-at91/board-vlink.c 2007-06-05 05:27:19.000000000 +0200 -@@ -175,6 +175,7 @@ - /* USB Device control */ - at91_set_gpio_input(AT91_PIN_PB27, 1); // UDB_CNX - at91_set_gpio_output(AT91_PIN_PB28, 1); // UDB_PUP -+ at91_set_multi_drive(AT91_PIN_PB28, 1); // Set to multi-drive - - } - diff --git a/target/linux/at91-2.6/patches-2.6.21/012-at91-mmcfix.patch b/target/linux/at91-2.6/patches-2.6.21/012-at91-mmcfix.patch deleted file mode 100644 index e8991ae614..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/012-at91-mmcfix.patch +++ /dev/null @@ -1,424 +0,0 @@ ---- linux-2.6.21.1.old/drivers/mmc/at91_mci.c 2007-06-05 09:08:57.000000000 +0200 -+++ linux-2.6.21.1/drivers/mmc/at91_mci.c 2007-06-05 10:59:11.000000000 +0200 -@@ -79,7 +79,8 @@ - - #define DRIVER_NAME "at91_mci" - --#undef SUPPORT_4WIRE -+//#undef SUPPORT_4WIRE -+#define SUPPORT_4WIRE - - #define FL_SENT_COMMAND (1 << 0) - #define FL_SENT_STOP (1 << 1) -@@ -132,7 +133,7 @@ - /* - * Copy from sg to a dma block - used for transfers - */ --static inline void at91mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) -+static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) - { - unsigned int len, i, size; - unsigned *dmabuf = host->buffer; -@@ -181,7 +182,7 @@ - /* - * Prepare a dma read - */ --static void at91mci_pre_dma_read(struct at91mci_host *host) -+static void at91_mci_pre_dma_read(struct at91mci_host *host) - { - int i; - struct scatterlist *sg; -@@ -249,23 +250,24 @@ - /* - * Handle after a dma read - */ --static void at91mci_post_dma_read(struct at91mci_host *host) -+static int at91_mci_post_dma_read(struct at91mci_host *host) - { - struct mmc_command *cmd; - struct mmc_data *data; -+ int completed = 0; - - pr_debug("post dma read\n"); - - cmd = host->cmd; - if (!cmd) { - pr_debug("no command\n"); -- return; -+ return 1; - } - - data = cmd->data; - if (!data) { - pr_debug("no data\n"); -- return; -+ return 1; - } - - while (host->in_use_index < host->transfer_index) { -@@ -300,39 +302,14 @@ - - /* Is there another transfer to trigger? */ - if (host->transfer_index < data->sg_len) -- at91mci_pre_dma_read(host); -+ at91_mci_pre_dma_read(host); - else { -+ at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); - at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); -- at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); - } - - pr_debug("post dma read done\n"); --} -- --/* -- * Handle transmitted data -- */ --static void at91_mci_handle_transmitted(struct at91mci_host *host) --{ -- struct mmc_command *cmd; -- struct mmc_data *data; -- -- pr_debug("Handling the transmit\n"); -- -- /* Disable the transfer */ -- at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); -- -- /* Now wait for cmd ready */ -- at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); -- at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); -- -- cmd = host->cmd; -- if (!cmd) return; -- -- data = cmd->data; -- if (!data) return; -- -- data->bytes_xfered = host->total_length; -+ return completed; - } - - /* -@@ -340,10 +317,17 @@ - */ - static void at91_mci_enable(struct at91mci_host *host) - { -+ unsigned int mr; -+ - at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); - at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); - at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); -- at91_mci_write(host, AT91_MCI_MR, AT91_MCI_PDCMODE | 0x34a); -+ mr = AT91_MCI_PDCMODE | 0x34a; -+ -+ if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) -+ mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; -+ -+ at91_mci_write(host, AT91_MCI_MR, mr); - - /* use Slot A or B (only one at same time) */ - at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); -@@ -359,9 +343,8 @@ - - /* - * Send a command -- * return the interrupts to enable - */ --static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) -+static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) - { - unsigned int cmdr, mr; - unsigned int block_length; -@@ -372,8 +355,7 @@ - - host->cmd = cmd; - -- /* Not sure if this is needed */ --#if 0 -+ /* Needed for leaving busy state before CMD1 */ - if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { - pr_debug("Clearing timeout\n"); - at91_mci_write(host, AT91_MCI_ARGR, 0); -@@ -383,7 +365,7 @@ - pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR)); - } - } --#endif -+ - cmdr = cmd->opcode; - - if (mmc_resp_type(cmd) == MMC_RSP_NONE) -@@ -440,50 +422,48 @@ - at91_mci_write(host, ATMEL_PDC_TCR, 0); - at91_mci_write(host, ATMEL_PDC_TNPR, 0); - at91_mci_write(host, ATMEL_PDC_TNCR, 0); -+ ier = AT91_MCI_CMDRDY; -+ } else { -+ /* zero block length in PDC mode */ -+ mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; -+ at91_mci_write(host, AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE); -+ -+ /* -+ * Disable the PDC controller -+ */ -+ at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); - -- at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); -- at91_mci_write(host, AT91_MCI_CMDR, cmdr); -- return AT91_MCI_CMDRDY; -- } -- -- mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; /* zero block length and PDC mode */ -- at91_mci_write(host, AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE); -- -- /* -- * Disable the PDC controller -- */ -- at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); -- -- if (cmdr & AT91_MCI_TRCMD_START) { -- data->bytes_xfered = 0; -- host->transfer_index = 0; -- host->in_use_index = 0; -- if (cmdr & AT91_MCI_TRDIR) { -- /* -- * Handle a read -- */ -- host->buffer = NULL; -- host->total_length = 0; -+ if (cmdr & AT91_MCI_TRCMD_START) { -+ data->bytes_xfered = 0; -+ host->transfer_index = 0; -+ host->in_use_index = 0; -+ if (cmdr & AT91_MCI_TRDIR) { -+ /* -+ * Handle a read -+ */ -+ host->buffer = NULL; -+ host->total_length = 0; - -- at91mci_pre_dma_read(host); -- ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; -- } -- else { -- /* -- * Handle a write -- */ -- host->total_length = block_length * blocks; -- host->buffer = dma_alloc_coherent(NULL, -- host->total_length, -- &host->physical_address, GFP_KERNEL); -- -- at91mci_sg_to_dma(host, data); -- -- pr_debug("Transmitting %d bytes\n", host->total_length); -- -- at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); -- at91_mci_write(host, ATMEL_PDC_TCR, host->total_length / 4); -- ier = AT91_MCI_TXBUFE; -+ at91_mci_pre_dma_read(host); -+ ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; -+ } -+ else { -+ /* -+ * Handle a write -+ */ -+ host->total_length = block_length * blocks; -+ host->buffer = dma_alloc_coherent(NULL, -+ host->total_length, -+ &host->physical_address, GFP_KERNEL); -+ -+ at91_mci_sg_to_dma(host, data); -+ -+ pr_debug("Transmitting %d bytes\n", host->total_length); -+ -+ at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); -+ at91_mci_write(host, ATMEL_PDC_TCR, host->total_length / 4); -+ ier = AT91_MCI_CMDRDY; -+ } - } - } - -@@ -498,39 +478,24 @@ - if (cmdr & AT91_MCI_TRCMD_START) { - if (cmdr & AT91_MCI_TRDIR) - at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); -- else -- at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); - } -- return ier; --} - --/* -- * Wait for a command to complete -- */ --static void at91mci_process_command(struct at91mci_host *host, struct mmc_command *cmd) --{ -- unsigned int ier; -- -- ier = at91_mci_send_command(host, cmd); -- -- pr_debug("setting ier to %08X\n", ier); -- -- /* Stop on errors or the required value */ -+ /* Enable selected interrupts */ - at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); - } - - /* - * Process the next step in the request - */ --static void at91mci_process_next(struct at91mci_host *host) -+static void at91_mci_process_next(struct at91mci_host *host) - { - if (!(host->flags & FL_SENT_COMMAND)) { - host->flags |= FL_SENT_COMMAND; -- at91mci_process_command(host, host->request->cmd); -+ at91_mci_send_command(host, host->request->cmd); - } - else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { - host->flags |= FL_SENT_STOP; -- at91mci_process_command(host, host->request->stop); -+ at91_mci_send_command(host, host->request->stop); - } - else - mmc_request_done(host->mmc, host->request); -@@ -539,7 +504,7 @@ - /* - * Handle a command that has been completed - */ --static void at91mci_completed_command(struct at91mci_host *host) -+static void at91_mci_completed_command(struct at91mci_host *host) - { - struct mmc_command *cmd = host->cmd; - unsigned int status; -@@ -583,7 +548,7 @@ - else - cmd->error = MMC_ERR_NONE; - -- at91mci_process_next(host); -+ at91_mci_process_next(host); - } - - /* -@@ -595,7 +560,60 @@ - host->request = mrq; - host->flags = 0; - -- at91mci_process_next(host); -+ at91_mci_process_next(host); -+} -+ -+/* -+ * Handle transmitted data -+ */ -+static void at91_mci_handle_transmitted(struct at91mci_host *host) -+{ -+ struct mmc_command *cmd; -+ struct mmc_data *data; -+ -+ pr_debug("Handling the transmit\n"); -+ -+ /* Disable the transfer */ -+ at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); -+ -+ /* Now wait for cmd ready */ -+ at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); -+ -+ cmd = host->cmd; -+ if (!cmd) return; -+ -+ data = cmd->data; -+ if (!data) return; -+ -+ if (cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) { -+ pr_debug("multiple write : wait for BLKE...\n"); -+ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); -+ } else -+ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); -+ -+ data->bytes_xfered = host->total_length; -+} -+ -+ -+/*Handle after command sent ready*/ -+static int at91_mci_handle_cmdrdy(struct at91mci_host *host) -+{ -+ if (!host->cmd) -+ return 1; -+ else if (!host->cmd->data) { -+ if (host->flags & FL_SENT_STOP) { -+ /*After multi block write, we mus wait for NOTBUSY*/ -+ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); -+ } else return 1; -+ } else if (host->cmd->data->flags & MMC_DATA_WRITE) { -+ /*After sending multi-block-write command, start DMA transfer*/ -+ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE); -+ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); -+ at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); -+ } -+ -+ /* command not completed, have to wait */ -+ return 0; - } - - /* -@@ -698,29 +716,33 @@ - at91_mci_handle_transmitted(host); - } - -+ if (int_status & AT91_MCI_ENDRX) { -+ pr_debug("ENDRX\n"); -+ at91_mci_post_dma_read(host); -+ } -+ - if (int_status & AT91_MCI_RXBUFF) { - pr_debug("RX buffer full\n"); -- at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY); -+ at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); -+ at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); -+ completed = 1; - } - - if (int_status & AT91_MCI_ENDTX) - pr_debug("Transmit has ended\n"); - -- if (int_status & AT91_MCI_ENDRX) { -- pr_debug("Receive has ended\n"); -- at91mci_post_dma_read(host); -- } -- - if (int_status & AT91_MCI_NOTBUSY) { - pr_debug("Card is ready\n"); -- at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY); -+ completed = 1; - } - - if (int_status & AT91_MCI_DTIP) - pr_debug("Data transfer in progress\n"); - -- if (int_status & AT91_MCI_BLKE) -+ if (int_status & AT91_MCI_BLKE) { - pr_debug("Block transfer has ended\n"); -+ completed = 1; -+ } - - if (int_status & AT91_MCI_TXRDY) - pr_debug("Ready to transmit\n"); -@@ -730,14 +752,14 @@ - - if (int_status & AT91_MCI_CMDRDY) { - pr_debug("Command ready\n"); -- completed = 1; -+ completed = at91_mci_handle_cmdrdy(host); - } - } - - if (completed) { - pr_debug("Completed command\n"); - at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); -- at91mci_completed_command(host); -+ at91_mci_completed_command(host); - } else - at91_mci_write(host, AT91_MCI_IDR, int_status); - diff --git a/target/linux/at91-2.6/patches-2.6.21/013-at91-mmc1wire.patch b/target/linux/at91-2.6/patches-2.6.21/013-at91-mmc1wire.patch deleted file mode 100644 index 31b1e96776..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/013-at91-mmc1wire.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- linux-2.6.21.1.old/drivers/mmc/at91_mci.c 2007-06-05 11:08:39.000000000 +0200 -+++ linux-2.6.21.1/drivers/mmc/at91_mci.c 2007-06-05 11:28:40.000000000 +0200 -@@ -79,8 +79,7 @@ - - #define DRIVER_NAME "at91_mci" - --//#undef SUPPORT_4WIRE --#define SUPPORT_4WIRE -+#undef SUPPORT_4WIRE - - #define FL_SENT_COMMAND (1 << 0) - #define FL_SENT_STOP (1 << 1) diff --git a/target/linux/at91-2.6/patches-2.6.21/014-initpartition.patch b/target/linux/at91-2.6/patches-2.6.21/014-initpartition.patch deleted file mode 100644 index 7e78e6487a..0000000000 --- a/target/linux/at91-2.6/patches-2.6.21/014-initpartition.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- linux-2.6.21.5.old/drivers/mtd/devices/at91_dataflash.c 2007-06-13 13:31:24.000000000 +0200 -+++ linux-2.6.21.5/drivers/mtd/devices/at91_dataflash.c 2007-06-19 12:49:48.000000000 +0200 -@@ -161,12 +161,12 @@ - .mask_flags = MTD_WRITEABLE, /* read-only */ - }, - { -- .name = "kernel", -+ .name = "knlroot", - .offset = MTDPART_OFS_NXTBLK, -- .size = 5 * 32 * 8 * 1056, /* 5 sectors */ -+ .size = 0x320400, /* 5 sectors */ - }, - { -- .name = "filesystem", -+ .name = "jffs2", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL, /* rest = 26 sectors */ - } diff --git a/target/linux/at91-2.6/patches-2.6.22/000-at91.patch b/target/linux/at91-2.6/patches-2.6.22/000-at91.patch deleted file mode 100644 index 16ab784881..0000000000 --- a/target/linux/at91-2.6/patches-2.6.22/000-at91.patch +++ /dev/null @@ -1,9932 +0,0 @@ -diff -urN linux-2.6.22-rc5/arch/arm/boot/compressed/head-at91rm9200.S linux-2.6.22-rc5.new/arch/arm/boot/compressed/head-at91rm9200.S ---- linux-2.6.22-rc5/arch/arm/boot/compressed/head-at91rm9200.S 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/boot/compressed/head-at91rm9200.S 2007-07-29 05:23:04.000000000 +0200 -@@ -73,6 +73,12 @@ - cmp r7, r3 - beq 99f - -+ @ Promwad Chub : 1181 -+ mov r3, #(MACH_TYPE_CHUB & 0xff) -+ orr r3, r3, #(MACH_TYPE_CHUB & 0xff00) -+ cmp r7, r3 -+ beq 99f -+ - @ Unknown board, use the AT91RM9200DK board - @ mov r7, #MACH_TYPE_AT91RM9200 - mov r7, #(MACH_TYPE_AT91RM9200DK & 0xff) -diff -urN linux-2.6.22-rc5/arch/arm/configs/at91sam9260ek_defconfig linux-2.6.22-rc5.new/arch/arm/configs/at91sam9260ek_defconfig ---- linux-2.6.22-rc5/arch/arm/configs/at91sam9260ek_defconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/configs/at91sam9260ek_defconfig 2007-07-29 05:23:04.000000000 +0200 -@@ -1,18 +1,24 @@ - # - # Automatically generated make config: don't edit --# Linux kernel version: 2.6.19-rc6 --# Fri Nov 17 18:42:21 2006 -+# Linux kernel version: 2.6.21 -+# Mon May 7 11:42:02 2007 - # - CONFIG_ARM=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+CONFIG_GENERIC_GPIO=y - # CONFIG_GENERIC_TIME is not set - CONFIG_MMU=y -+# CONFIG_NO_IOPORT is not set - CONFIG_GENERIC_HARDIRQS=y - CONFIG_TRACE_IRQFLAGS_SUPPORT=y - CONFIG_HARDIRQS_SW_RESEND=y - CONFIG_GENERIC_IRQ_PROBE=y - CONFIG_RWSEM_GENERIC_SPINLOCK=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set - CONFIG_GENERIC_HWEIGHT=y - CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ZONE_DMA=y - CONFIG_VECTORS_BASE=0xffff0000 - CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -@@ -31,13 +37,16 @@ - # CONFIG_SWAP is not set - CONFIG_SYSVIPC=y - # CONFIG_IPC_NS is not set -+CONFIG_SYSVIPC_SYSCTL=y - # CONFIG_POSIX_MQUEUE is not set - # CONFIG_BSD_PROCESS_ACCT is not set - # CONFIG_TASKSTATS is not set - # CONFIG_UTS_NS is not set - # CONFIG_AUDIT is not set - # CONFIG_IKCONFIG is not set -+CONFIG_SYSFS_DEPRECATED=y - # CONFIG_RELAY is not set -+CONFIG_BLK_DEV_INITRD=y - CONFIG_INITRAMFS_SOURCE="" - CONFIG_CC_OPTIMIZE_FOR_SIZE=y - CONFIG_SYSCTL=y -@@ -76,7 +85,9 @@ - # Block layer - # - CONFIG_BLOCK=y -+# CONFIG_LBD is not set - # CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set - - # - # IO Schedulers -@@ -110,10 +121,12 @@ - # CONFIG_ARCH_IMX is not set - # CONFIG_ARCH_IOP32X is not set - # CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IOP13XX is not set - # CONFIG_ARCH_IXP4XX is not set - # CONFIG_ARCH_IXP2000 is not set - # CONFIG_ARCH_IXP23XX is not set - # CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_NS9XXX is not set - # CONFIG_ARCH_PNX4008 is not set - # CONFIG_ARCH_PXA is not set - # CONFIG_ARCH_RPC is not set -@@ -129,21 +142,29 @@ - # CONFIG_ARCH_AT91RM9200 is not set - CONFIG_ARCH_AT91SAM9260=y - # CONFIG_ARCH_AT91SAM9261 is not set -+# CONFIG_ARCH_AT91SAM9263 is not set -+ -+# -+# AT91SAM9260 Variants -+# -+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set - - # --# AT91SAM9260 Board Type -+# AT91SAM9260 / AT91SAM9XE Board Type - # - CONFIG_MACH_AT91SAM9260EK=y - - # - # AT91 Board Options - # -+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set - # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set - - # - # AT91 Feature Selections - # - # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set -+# CONFIG_ATMEL_TCLIB is not set - - # - # Processor Type -@@ -166,6 +187,7 @@ - # CONFIG_CPU_DCACHE_DISABLE is not set - # CONFIG_CPU_DCACHE_WRITETHROUGH is not set - # CONFIG_CPU_CACHE_ROUND_ROBIN is not set -+# CONFIG_OUTER_CACHE is not set - - # - # Bus support -@@ -193,6 +215,7 @@ - # CONFIG_SPARSEMEM_STATIC is not set - CONFIG_SPLIT_PTLOCK_CPUS=4096 - # CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 - # CONFIG_LEDS is not set - CONFIG_ALIGNMENT_TRAP=y - -@@ -203,6 +226,7 @@ - CONFIG_ZBOOT_ROM_BSS=0x0 - CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" - # CONFIG_XIP_KERNEL is not set -+# CONFIG_KEXEC is not set - - # - # Floating point emulation -@@ -228,7 +252,6 @@ - # Power management options - # - # CONFIG_PM is not set --# CONFIG_APM is not set - - # - # Networking -@@ -242,9 +265,6 @@ - CONFIG_PACKET=y - # CONFIG_PACKET_MMAP is not set - CONFIG_UNIX=y --CONFIG_XFRM=y --# CONFIG_XFRM_USER is not set --# CONFIG_XFRM_SUB_POLICY is not set - # CONFIG_NET_KEY is not set - CONFIG_INET=y - # CONFIG_IP_MULTICAST is not set -@@ -263,14 +283,15 @@ - # CONFIG_INET_IPCOMP is not set - # CONFIG_INET_XFRM_TUNNEL is not set - # CONFIG_INET_TUNNEL is not set --CONFIG_INET_XFRM_MODE_TRANSPORT=y --CONFIG_INET_XFRM_MODE_TUNNEL=y --CONFIG_INET_XFRM_MODE_BEET=y -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set - CONFIG_INET_DIAG=y - CONFIG_INET_TCP_DIAG=y - # CONFIG_TCP_CONG_ADVANCED is not set - CONFIG_TCP_CONG_CUBIC=y - CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set - # CONFIG_IPV6 is not set - # CONFIG_INET6_XFRM_TUNNEL is not set - # CONFIG_INET6_TUNNEL is not set -@@ -328,6 +349,7 @@ - CONFIG_PREVENT_FIRMWARE_BUILD=y - # CONFIG_FW_LOADER is not set - # CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set - # CONFIG_SYS_HYPERVISOR is not set - - # -@@ -348,6 +370,7 @@ - # - # Plug and Play support - # -+# CONFIG_PNPACPI is not set - - # - # Block devices -@@ -360,7 +383,6 @@ - CONFIG_BLK_DEV_RAM_COUNT=16 - CONFIG_BLK_DEV_RAM_SIZE=8192 - CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 --CONFIG_BLK_DEV_INITRD=y - # CONFIG_CDROM_PKTCDVD is not set - # CONFIG_ATA_OVER_ETH is not set - -@@ -369,6 +391,7 @@ - # - # CONFIG_RAID_ATTRS is not set - CONFIG_SCSI=y -+# CONFIG_SCSI_TGT is not set - # CONFIG_SCSI_NETLINK is not set - CONFIG_SCSI_PROC_FS=y - -@@ -388,6 +411,7 @@ - CONFIG_SCSI_MULTI_LUN=y - # CONFIG_SCSI_CONSTANTS is not set - # CONFIG_SCSI_LOGGING is not set -+# CONFIG_SCSI_SCAN_ASYNC is not set - - # - # SCSI Transports -@@ -405,6 +429,11 @@ - # CONFIG_SCSI_DEBUG is not set - - # -+# Serial ATA (prod) and Parallel ATA (experimental) drivers -+# -+# CONFIG_ATA is not set -+ -+# - # Multi-device support (RAID and LVM) - # - # CONFIG_MD is not set -@@ -425,7 +454,51 @@ - # - # Network device support - # --# CONFIG_NETDEVICES is not set -+CONFIG_NETDEVICES=y -+# CONFIG_DUMMY is not set -+# CONFIG_BONDING is not set -+# CONFIG_EQUALIZER is not set -+# CONFIG_TUN is not set -+ -+# -+# PHY device support -+# -+# CONFIG_PHYLIB is not set -+ -+# -+# Ethernet (10 or 100Mbit) -+# -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=y -+CONFIG_MACB=y -+# CONFIG_SMC91X is not set -+# CONFIG_DM9000 is not set -+ -+# -+# Ethernet (1000 Mbit) -+# -+ -+# -+# Ethernet (10000 Mbit) -+# -+ -+# -+# Token Ring devices -+# -+ -+# -+# Wireless LAN (non-hamradio) -+# -+# CONFIG_NET_RADIO is not set -+ -+# -+# Wan interfaces -+# -+# CONFIG_WAN is not set -+# CONFIG_PPP is not set -+# CONFIG_SLIP is not set -+# CONFIG_SHAPER is not set -+# CONFIG_NETCONSOLE is not set - # CONFIG_NETPOLL is not set - # CONFIG_NET_POLL_CONTROLLER is not set - -@@ -517,10 +590,6 @@ - # CONFIG_NVRAM is not set - # CONFIG_DTLK is not set - # CONFIG_R3964 is not set -- --# --# Ftape, the floppy tape device driver --# - # CONFIG_RAW_DRIVER is not set - - # -@@ -553,7 +622,11 @@ - # - # Misc devices - # --# CONFIG_TIFM_CORE is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set - - # - # LED devices -@@ -582,7 +655,7 @@ - # - # Graphics support - # --# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - # CONFIG_FB is not set - - # -@@ -590,7 +663,6 @@ - # - # CONFIG_VGA_CONSOLE is not set - CONFIG_DUMMY_CONSOLE=y --# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - - # - # Sound -@@ -598,6 +670,12 @@ - # CONFIG_SOUND is not set - - # -+# HID Devices -+# -+CONFIG_HID=y -+# CONFIG_HID_DEBUG is not set -+ -+# - # USB support - # - CONFIG_USB_ARCH_HAS_HCD=y -@@ -610,7 +688,6 @@ - # Miscellaneous USB options - # - CONFIG_USB_DEVICEFS=y --# CONFIG_USB_BANDWIDTH is not set - # CONFIG_USB_DYNAMIC_MINORS is not set - # CONFIG_USB_OTG is not set - -@@ -619,7 +696,8 @@ - # - # CONFIG_USB_ISP116X_HCD is not set - CONFIG_USB_OHCI_HCD=y --# CONFIG_USB_OHCI_BIG_ENDIAN is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set - CONFIG_USB_OHCI_LITTLE_ENDIAN=y - # CONFIG_USB_SL811_HCD is not set - -@@ -671,6 +749,7 @@ - # CONFIG_USB_ATI_REMOTE2 is not set - # CONFIG_USB_KEYSPAN_REMOTE is not set - # CONFIG_USB_APPLETOUCH is not set -+# CONFIG_USB_GTCO is not set - - # - # USB Imaging devices -@@ -708,6 +787,7 @@ - # CONFIG_USB_RIO500 is not set - # CONFIG_USB_LEGOTOWER is not set - # CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set - # CONFIG_USB_LED is not set - # CONFIG_USB_CYPRESS_CY7C63 is not set - # CONFIG_USB_CYTHERM is not set -@@ -717,6 +797,7 @@ - # CONFIG_USB_APPLEDISPLAY is not set - # CONFIG_USB_LD is not set - # CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set - # CONFIG_USB_TEST is not set - - # -@@ -889,6 +970,11 @@ - # CONFIG_NLS_UTF8 is not set - - # -+# Distributed Lock Manager -+# -+# CONFIG_DLM is not set -+ -+# - # Profiling support - # - # CONFIG_PROFILING is not set -@@ -900,28 +986,30 @@ - CONFIG_ENABLE_MUST_CHECK=y - # CONFIG_MAGIC_SYSRQ is not set - # CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_DEBUG_FS is not set -+# CONFIG_HEADERS_CHECK is not set - CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set - CONFIG_LOG_BUF_SHIFT=14 - CONFIG_DETECT_SOFTLOCKUP=y - # CONFIG_SCHEDSTATS is not set -+# CONFIG_TIMER_STATS is not set - # CONFIG_DEBUG_SLAB is not set - # CONFIG_DEBUG_RT_MUTEXES is not set - # CONFIG_RT_MUTEX_TESTER is not set - # CONFIG_DEBUG_SPINLOCK is not set - # CONFIG_DEBUG_MUTEXES is not set --# CONFIG_DEBUG_RWSEMS is not set - # CONFIG_DEBUG_SPINLOCK_SLEEP is not set - # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set - # CONFIG_DEBUG_KOBJECT is not set - CONFIG_DEBUG_BUGVERBOSE=y - # CONFIG_DEBUG_INFO is not set --# CONFIG_DEBUG_FS is not set - # CONFIG_DEBUG_VM is not set - # CONFIG_DEBUG_LIST is not set - CONFIG_FRAME_POINTER=y - CONFIG_FORCED_INLINING=y --# CONFIG_HEADERS_CHECK is not set - # CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_FAULT_INJECTION is not set - CONFIG_DEBUG_USER=y - # CONFIG_DEBUG_ERRORS is not set - CONFIG_DEBUG_LL=y -@@ -941,9 +1029,12 @@ - # - # Library routines - # -+CONFIG_BITREVERSE=y - # CONFIG_CRC_CCITT is not set - # CONFIG_CRC16 is not set - CONFIG_CRC32=y - # CONFIG_LIBCRC32C is not set - CONFIG_ZLIB_INFLATE=y - CONFIG_PLIST=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -diff -urN linux-2.6.22-rc5/arch/arm/configs/at91sam9261ek_defconfig linux-2.6.22-rc5.new/arch/arm/configs/at91sam9261ek_defconfig ---- linux-2.6.22-rc5/arch/arm/configs/at91sam9261ek_defconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/configs/at91sam9261ek_defconfig 2007-07-29 05:23:04.000000000 +0200 -@@ -1,18 +1,24 @@ - # - # Automatically generated make config: don't edit --# Linux kernel version: 2.6.19-rc6 --# Fri Nov 17 18:00:38 2006 -+# Linux kernel version: 2.6.21 -+# Mon May 7 11:42:30 2007 - # - CONFIG_ARM=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+CONFIG_GENERIC_GPIO=y - # CONFIG_GENERIC_TIME is not set - CONFIG_MMU=y -+# CONFIG_NO_IOPORT is not set - CONFIG_GENERIC_HARDIRQS=y - CONFIG_TRACE_IRQFLAGS_SUPPORT=y - CONFIG_HARDIRQS_SW_RESEND=y - CONFIG_GENERIC_IRQ_PROBE=y - CONFIG_RWSEM_GENERIC_SPINLOCK=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set - CONFIG_GENERIC_HWEIGHT=y - CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ZONE_DMA=y - CONFIG_VECTORS_BASE=0xffff0000 - CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -@@ -31,13 +37,16 @@ - # CONFIG_SWAP is not set - CONFIG_SYSVIPC=y - # CONFIG_IPC_NS is not set -+CONFIG_SYSVIPC_SYSCTL=y - # CONFIG_POSIX_MQUEUE is not set - # CONFIG_BSD_PROCESS_ACCT is not set - # CONFIG_TASKSTATS is not set - # CONFIG_UTS_NS is not set - # CONFIG_AUDIT is not set - # CONFIG_IKCONFIG is not set -+CONFIG_SYSFS_DEPRECATED=y - # CONFIG_RELAY is not set -+CONFIG_BLK_DEV_INITRD=y - CONFIG_INITRAMFS_SOURCE="" - CONFIG_CC_OPTIMIZE_FOR_SIZE=y - CONFIG_SYSCTL=y -@@ -76,7 +85,9 @@ - # Block layer - # - CONFIG_BLOCK=y -+# CONFIG_LBD is not set - # CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set - - # - # IO Schedulers -@@ -110,10 +121,12 @@ - # CONFIG_ARCH_IMX is not set - # CONFIG_ARCH_IOP32X is not set - # CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IOP13XX is not set - # CONFIG_ARCH_IXP4XX is not set - # CONFIG_ARCH_IXP2000 is not set - # CONFIG_ARCH_IXP23XX is not set - # CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_NS9XXX is not set - # CONFIG_ARCH_PNX4008 is not set - # CONFIG_ARCH_PXA is not set - # CONFIG_ARCH_RPC is not set -@@ -129,6 +142,7 @@ - # CONFIG_ARCH_AT91RM9200 is not set - # CONFIG_ARCH_AT91SAM9260 is not set - CONFIG_ARCH_AT91SAM9261=y -+# CONFIG_ARCH_AT91SAM9263 is not set - - # - # AT91SAM9261 Board Type -@@ -138,12 +152,14 @@ - # - # AT91 Board Options - # -+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set - # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set - - # - # AT91 Feature Selections - # - # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set -+# CONFIG_ATMEL_TCLIB is not set - - # - # Processor Type -@@ -166,6 +182,7 @@ - # CONFIG_CPU_DCACHE_DISABLE is not set - # CONFIG_CPU_DCACHE_WRITETHROUGH is not set - # CONFIG_CPU_CACHE_ROUND_ROBIN is not set -+# CONFIG_OUTER_CACHE is not set - - # - # Bus support -@@ -193,6 +210,7 @@ - # CONFIG_SPARSEMEM_STATIC is not set - CONFIG_SPLIT_PTLOCK_CPUS=4096 - # CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 - # CONFIG_LEDS is not set - CONFIG_ALIGNMENT_TRAP=y - -@@ -203,6 +221,7 @@ - CONFIG_ZBOOT_ROM_BSS=0x0 - CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" - # CONFIG_XIP_KERNEL is not set -+# CONFIG_KEXEC is not set - - # - # Floating point emulation -@@ -228,7 +247,6 @@ - # Power management options - # - # CONFIG_PM is not set --# CONFIG_APM is not set - - # - # Networking -@@ -245,6 +263,7 @@ - CONFIG_XFRM=y - # CONFIG_XFRM_USER is not set - # CONFIG_XFRM_SUB_POLICY is not set -+# CONFIG_XFRM_MIGRATE is not set - # CONFIG_NET_KEY is not set - CONFIG_INET=y - # CONFIG_IP_MULTICAST is not set -@@ -271,6 +290,7 @@ - # CONFIG_TCP_CONG_ADVANCED is not set - CONFIG_TCP_CONG_CUBIC=y - CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set - # CONFIG_IPV6 is not set - # CONFIG_INET6_XFRM_TUNNEL is not set - # CONFIG_INET6_TUNNEL is not set -@@ -328,6 +348,7 @@ - CONFIG_PREVENT_FIRMWARE_BUILD=y - # CONFIG_FW_LOADER is not set - # CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set - # CONFIG_SYS_HYPERVISOR is not set - - # -@@ -350,6 +371,7 @@ - # User Modules And Translation Layers - # - # CONFIG_MTD_CHAR is not set -+CONFIG_MTD_BLKDEVS=y - CONFIG_MTD_BLOCK=y - # CONFIG_FTL is not set - # CONFIG_NFTL is not set -@@ -386,6 +408,8 @@ - # - # Self-contained MTD device drivers - # -+# CONFIG_MTD_DATAFLASH is not set -+# CONFIG_MTD_M25P80 is not set - # CONFIG_MTD_SLRAM is not set - # CONFIG_MTD_PHRAM is not set - # CONFIG_MTD_MTDRAM is not set -@@ -422,6 +446,7 @@ - # - # Plug and Play support - # -+# CONFIG_PNPACPI is not set - - # - # Block devices -@@ -434,7 +459,6 @@ - CONFIG_BLK_DEV_RAM_COUNT=16 - CONFIG_BLK_DEV_RAM_SIZE=8192 - CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 --CONFIG_BLK_DEV_INITRD=y - # CONFIG_CDROM_PKTCDVD is not set - # CONFIG_ATA_OVER_ETH is not set - -@@ -443,6 +467,7 @@ - # - # CONFIG_RAID_ATTRS is not set - CONFIG_SCSI=y -+# CONFIG_SCSI_TGT is not set - # CONFIG_SCSI_NETLINK is not set - CONFIG_SCSI_PROC_FS=y - -@@ -462,6 +487,7 @@ - CONFIG_SCSI_MULTI_LUN=y - # CONFIG_SCSI_CONSTANTS is not set - # CONFIG_SCSI_LOGGING is not set -+# CONFIG_SCSI_SCAN_ASYNC is not set - - # - # SCSI Transports -@@ -479,6 +505,11 @@ - # CONFIG_SCSI_DEBUG is not set - - # -+# Serial ATA (prod) and Parallel ATA (experimental) drivers -+# -+# CONFIG_ATA is not set -+ -+# - # Multi-device support (RAID and LVM) - # - # CONFIG_MD is not set -@@ -575,7 +606,16 @@ - # CONFIG_INPUT_KEYBOARD is not set - # CONFIG_INPUT_MOUSE is not set - # CONFIG_INPUT_JOYSTICK is not set --# CONFIG_INPUT_TOUCHSCREEN is not set -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_ADS7846=y -+# CONFIG_TOUCHSCREEN_GUNZE is not set -+# CONFIG_TOUCHSCREEN_ELO is not set -+# CONFIG_TOUCHSCREEN_MTOUCH is not set -+# CONFIG_TOUCHSCREEN_MK712 is not set -+# CONFIG_TOUCHSCREEN_PENMOUNT is not set -+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -+# CONFIG_TOUCHSCREEN_UCB1400 is not set - # CONFIG_INPUT_MISC is not set - - # -@@ -634,10 +674,6 @@ - # CONFIG_NVRAM is not set - # CONFIG_DTLK is not set - # CONFIG_R3964 is not set -- --# --# Ftape, the floppy tape device driver --# - # CONFIG_RAW_DRIVER is not set - - # -@@ -662,6 +698,7 @@ - # I2C Hardware Bus support - # - CONFIG_I2C_AT91=y -+CONFIG_I2C_AT91_CLOCKRATE=100000 - # CONFIG_I2C_OCORES is not set - # CONFIG_I2C_PARPORT_LIGHT is not set - # CONFIG_I2C_STUB is not set -@@ -686,8 +723,20 @@ - # - # SPI support - # --# CONFIG_SPI is not set --# CONFIG_SPI_MASTER is not set -+CONFIG_SPI=y -+# CONFIG_SPI_DEBUG is not set -+CONFIG_SPI_MASTER=y -+ -+# -+# SPI Master Controller Drivers -+# -+CONFIG_SPI_ATMEL=y -+# CONFIG_SPI_BITBANG is not set -+ -+# -+# SPI Protocol Masters -+# -+# CONFIG_SPI_AT25 is not set - - # - # Dallas's 1-wire bus -@@ -703,7 +752,11 @@ - # - # Misc devices - # --# CONFIG_TIFM_CORE is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set - - # - # LED devices -@@ -732,7 +785,7 @@ - # - # Graphics support - # --# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - # CONFIG_FB is not set - - # -@@ -740,7 +793,6 @@ - # - # CONFIG_VGA_CONSOLE is not set - CONFIG_DUMMY_CONSOLE=y --# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - - # - # Sound -@@ -748,6 +800,12 @@ - # CONFIG_SOUND is not set - - # -+# HID Devices -+# -+CONFIG_HID=y -+# CONFIG_HID_DEBUG is not set -+ -+# - # USB support - # - CONFIG_USB_ARCH_HAS_HCD=y -@@ -760,7 +818,6 @@ - # Miscellaneous USB options - # - CONFIG_USB_DEVICEFS=y --# CONFIG_USB_BANDWIDTH is not set - # CONFIG_USB_DYNAMIC_MINORS is not set - # CONFIG_USB_OTG is not set - -@@ -769,7 +826,8 @@ - # - # CONFIG_USB_ISP116X_HCD is not set - CONFIG_USB_OHCI_HCD=y --# CONFIG_USB_OHCI_BIG_ENDIAN is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set - CONFIG_USB_OHCI_LITTLE_ENDIAN=y - # CONFIG_USB_SL811_HCD is not set - -@@ -821,6 +879,7 @@ - # CONFIG_USB_ATI_REMOTE2 is not set - # CONFIG_USB_KEYSPAN_REMOTE is not set - # CONFIG_USB_APPLETOUCH is not set -+# CONFIG_USB_GTCO is not set - - # - # USB Imaging devices -@@ -858,6 +917,7 @@ - # CONFIG_USB_RIO500 is not set - # CONFIG_USB_LEGOTOWER is not set - # CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set - # CONFIG_USB_LED is not set - # CONFIG_USB_CYPRESS_CY7C63 is not set - # CONFIG_USB_CYTHERM is not set -@@ -867,6 +927,7 @@ - # CONFIG_USB_APPLEDISPLAY is not set - # CONFIG_USB_LD is not set - # CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set - # CONFIG_USB_TEST is not set - - # -@@ -903,7 +964,6 @@ - # CONFIG_MMC_DEBUG is not set - CONFIG_MMC_BLOCK=y - CONFIG_MMC_AT91=m --# CONFIG_MMC_TIFM_SD is not set - - # - # Real Time Clock -@@ -973,7 +1033,6 @@ - # CONFIG_BEFS_FS is not set - # CONFIG_BFS_FS is not set - # CONFIG_EFS_FS is not set --# CONFIG_JFFS_FS is not set - # CONFIG_JFFS2_FS is not set - CONFIG_CRAMFS=y - # CONFIG_VXFS_FS is not set -@@ -1045,6 +1104,11 @@ - # CONFIG_NLS_UTF8 is not set - - # -+# Distributed Lock Manager -+# -+# CONFIG_DLM is not set -+ -+# - # Profiling support - # - # CONFIG_PROFILING is not set -@@ -1056,28 +1120,30 @@ - CONFIG_ENABLE_MUST_CHECK=y - # CONFIG_MAGIC_SYSRQ is not set - # CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_DEBUG_FS is not set -+# CONFIG_HEADERS_CHECK is not set - CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set - CONFIG_LOG_BUF_SHIFT=14 - CONFIG_DETECT_SOFTLOCKUP=y - # CONFIG_SCHEDSTATS is not set -+# CONFIG_TIMER_STATS is not set - # CONFIG_DEBUG_SLAB is not set - # CONFIG_DEBUG_RT_MUTEXES is not set - # CONFIG_RT_MUTEX_TESTER is not set - # CONFIG_DEBUG_SPINLOCK is not set - # CONFIG_DEBUG_MUTEXES is not set --# CONFIG_DEBUG_RWSEMS is not set - # CONFIG_DEBUG_SPINLOCK_SLEEP is not set - # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set - # CONFIG_DEBUG_KOBJECT is not set - CONFIG_DEBUG_BUGVERBOSE=y - # CONFIG_DEBUG_INFO is not set --# CONFIG_DEBUG_FS is not set - # CONFIG_DEBUG_VM is not set - # CONFIG_DEBUG_LIST is not set - CONFIG_FRAME_POINTER=y - CONFIG_FORCED_INLINING=y --# CONFIG_HEADERS_CHECK is not set - # CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_FAULT_INJECTION is not set - CONFIG_DEBUG_USER=y - # CONFIG_DEBUG_ERRORS is not set - CONFIG_DEBUG_LL=y -@@ -1097,9 +1163,12 @@ - # - # Library routines - # -+CONFIG_BITREVERSE=y - # CONFIG_CRC_CCITT is not set - # CONFIG_CRC16 is not set - CONFIG_CRC32=y - # CONFIG_LIBCRC32C is not set - CONFIG_ZLIB_INFLATE=y - CONFIG_PLIST=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -diff -urN linux-2.6.22-rc5/arch/arm/configs/at91sam9263ek_defconfig linux-2.6.22-rc5.new/arch/arm/configs/at91sam9263ek_defconfig ---- linux-2.6.22-rc5/arch/arm/configs/at91sam9263ek_defconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/configs/at91sam9263ek_defconfig 2007-07-29 05:23:04.000000000 +0200 -@@ -1,11 +1,14 @@ - # - # Automatically generated make config: don't edit --# Linux kernel version: 2.6.20-rc1 --# Mon Jan 8 16:06:54 2007 -+# Linux kernel version: 2.6.21 -+# Mon May 7 11:42:49 2007 - # - CONFIG_ARM=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+CONFIG_GENERIC_GPIO=y - # CONFIG_GENERIC_TIME is not set - CONFIG_MMU=y -+# CONFIG_NO_IOPORT is not set - CONFIG_GENERIC_HARDIRQS=y - CONFIG_TRACE_IRQFLAGS_SUPPORT=y - CONFIG_HARDIRQS_SW_RESEND=y -@@ -15,6 +18,7 @@ - # CONFIG_ARCH_HAS_ILOG2_U64 is not set - CONFIG_GENERIC_HWEIGHT=y - CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ZONE_DMA=y - CONFIG_VECTORS_BASE=0xffff0000 - CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -@@ -33,6 +37,7 @@ - # CONFIG_SWAP is not set - CONFIG_SYSVIPC=y - # CONFIG_IPC_NS is not set -+CONFIG_SYSVIPC_SYSCTL=y - # CONFIG_POSIX_MQUEUE is not set - # CONFIG_BSD_PROCESS_ACCT is not set - # CONFIG_TASKSTATS is not set -@@ -41,6 +46,7 @@ - # CONFIG_IKCONFIG is not set - CONFIG_SYSFS_DEPRECATED=y - # CONFIG_RELAY is not set -+CONFIG_BLK_DEV_INITRD=y - CONFIG_INITRAMFS_SOURCE="" - CONFIG_CC_OPTIMIZE_FOR_SIZE=y - CONFIG_SYSCTL=y -@@ -120,6 +126,7 @@ - # CONFIG_ARCH_IXP2000 is not set - # CONFIG_ARCH_IXP23XX is not set - # CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_NS9XXX is not set - # CONFIG_ARCH_PNX4008 is not set - # CONFIG_ARCH_PXA is not set - # CONFIG_ARCH_RPC is not set -@@ -152,6 +159,7 @@ - # AT91 Feature Selections - # - # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set -+# CONFIG_ATMEL_TCLIB is not set - - # - # Processor Type -@@ -174,6 +182,7 @@ - # CONFIG_CPU_DCACHE_DISABLE is not set - # CONFIG_CPU_DCACHE_WRITETHROUGH is not set - # CONFIG_CPU_CACHE_ROUND_ROBIN is not set -+# CONFIG_OUTER_CACHE is not set - - # - # Bus support -@@ -201,6 +210,7 @@ - # CONFIG_SPARSEMEM_STATIC is not set - CONFIG_SPLIT_PTLOCK_CPUS=4096 - # CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 - # CONFIG_LEDS is not set - CONFIG_ALIGNMENT_TRAP=y - -@@ -211,6 +221,7 @@ - CONFIG_ZBOOT_ROM_BSS=0x0 - CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" - # CONFIG_XIP_KERNEL is not set -+# CONFIG_KEXEC is not set - - # - # Floating point emulation -@@ -236,7 +247,6 @@ - # Power management options - # - # CONFIG_PM is not set --# CONFIG_APM is not set - - # - # Networking -@@ -333,6 +343,7 @@ - CONFIG_PREVENT_FIRMWARE_BUILD=y - # CONFIG_FW_LOADER is not set - # CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set - # CONFIG_SYS_HYPERVISOR is not set - - # -@@ -430,6 +441,7 @@ - # - # Plug and Play support - # -+# CONFIG_PNPACPI is not set - - # - # Block devices -@@ -443,7 +455,6 @@ - CONFIG_BLK_DEV_RAM_COUNT=16 - CONFIG_BLK_DEV_RAM_SIZE=8192 - CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 --CONFIG_BLK_DEV_INITRD=y - # CONFIG_CDROM_PKTCDVD is not set - # CONFIG_ATA_OVER_ETH is not set - -@@ -531,6 +542,7 @@ - # - CONFIG_NET_ETHERNET=y - CONFIG_MII=y -+CONFIG_MACB=y - # CONFIG_SMC91X is not set - # CONFIG_DM9000 is not set - -@@ -685,6 +697,7 @@ - # I2C Hardware Bus support - # - CONFIG_I2C_AT91=y -+CONFIG_I2C_AT91_CLOCKRATE=100000 - # CONFIG_I2C_OCORES is not set - # CONFIG_I2C_PARPORT_LIGHT is not set - # CONFIG_I2C_STUB is not set -@@ -722,6 +735,7 @@ - # - # SPI Protocol Masters - # -+# CONFIG_SPI_AT25 is not set - - # - # Dallas's 1-wire bus -@@ -737,7 +751,11 @@ - # - # Misc devices - # --# CONFIG_TIFM_CORE is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set - - # - # LED devices -@@ -766,15 +784,23 @@ - # - # Graphics support - # --# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - CONFIG_FB=y -+# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_FB_DDC is not set - # CONFIG_FB_CFB_FILLRECT is not set - # CONFIG_FB_CFB_COPYAREA is not set - # CONFIG_FB_CFB_IMAGEBLIT is not set -+# CONFIG_FB_SVGALIB is not set - # CONFIG_FB_MACMODES is not set - # CONFIG_FB_BACKLIGHT is not set - # CONFIG_FB_MODE_HELPERS is not set - # CONFIG_FB_TILEBLITTING is not set -+ -+# -+# Frame buffer hardware drivers -+# -+# CONFIG_FB_S1D15605 is not set - # CONFIG_FB_S1D13XXX is not set - # CONFIG_FB_VIRTUAL is not set - -@@ -789,7 +815,6 @@ - # Logo configuration - # - # CONFIG_LOGO is not set --# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - - # - # Sound -@@ -800,6 +825,7 @@ - # HID Devices - # - CONFIG_HID=y -+# CONFIG_HID_DEBUG is not set - - # - # USB support -@@ -814,9 +840,7 @@ - # Miscellaneous USB options - # - CONFIG_USB_DEVICEFS=y --# CONFIG_USB_BANDWIDTH is not set - # CONFIG_USB_DYNAMIC_MINORS is not set --# CONFIG_USB_MULTITHREAD_PROBE is not set - # CONFIG_USB_OTG is not set - - # -@@ -824,7 +848,8 @@ - # - # CONFIG_USB_ISP116X_HCD is not set - CONFIG_USB_OHCI_HCD=y --# CONFIG_USB_OHCI_BIG_ENDIAN is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set - CONFIG_USB_OHCI_LITTLE_ENDIAN=y - # CONFIG_USB_SL811_HCD is not set - -@@ -877,6 +902,7 @@ - # CONFIG_USB_ATI_REMOTE2 is not set - # CONFIG_USB_KEYSPAN_REMOTE is not set - # CONFIG_USB_APPLETOUCH is not set -+# CONFIG_USB_GTCO is not set - - # - # USB Imaging devices -@@ -914,6 +940,7 @@ - # CONFIG_USB_RIO500 is not set - # CONFIG_USB_LEGOTOWER is not set - # CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set - # CONFIG_USB_LED is not set - # CONFIG_USB_CYPRESS_CY7C63 is not set - # CONFIG_USB_CYTHERM is not set -@@ -923,6 +950,7 @@ - # CONFIG_USB_APPLEDISPLAY is not set - # CONFIG_USB_LD is not set - # CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set - # CONFIG_USB_TEST is not set - - # -@@ -959,7 +987,6 @@ - # CONFIG_MMC_DEBUG is not set - CONFIG_MMC_BLOCK=y - CONFIG_MMC_AT91=m --# CONFIG_MMC_TIFM_SD is not set - - # - # Real Time Clock -@@ -1136,15 +1163,16 @@ - # CONFIG_DEBUG_FS is not set - # CONFIG_HEADERS_CHECK is not set - CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set - CONFIG_LOG_BUF_SHIFT=14 - CONFIG_DETECT_SOFTLOCKUP=y - # CONFIG_SCHEDSTATS is not set -+# CONFIG_TIMER_STATS is not set - # CONFIG_DEBUG_SLAB is not set - # CONFIG_DEBUG_RT_MUTEXES is not set - # CONFIG_RT_MUTEX_TESTER is not set - # CONFIG_DEBUG_SPINLOCK is not set - # CONFIG_DEBUG_MUTEXES is not set --# CONFIG_DEBUG_RWSEMS is not set - # CONFIG_DEBUG_SPINLOCK_SLEEP is not set - # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set - # CONFIG_DEBUG_KOBJECT is not set -@@ -1155,6 +1183,7 @@ - CONFIG_FRAME_POINTER=y - CONFIG_FORCED_INLINING=y - # CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_FAULT_INJECTION is not set - CONFIG_DEBUG_USER=y - # CONFIG_DEBUG_ERRORS is not set - CONFIG_DEBUG_LL=y -@@ -1180,5 +1209,7 @@ - CONFIG_CRC32=y - # CONFIG_LIBCRC32C is not set - CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y - CONFIG_PLIST=y --CONFIG_IOMAP_COPY=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -diff -urN linux-2.6.22-rc5/arch/arm/configs/cam60_defconfig linux-2.6.22-rc5.new/arch/arm/configs/cam60_defconfig ---- linux-2.6.22-rc5/arch/arm/configs/cam60_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/arch/arm/configs/cam60_defconfig 2007-07-29 05:23:04.000000000 +0200 -@@ -0,0 +1,954 @@ -+# -+# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.20 -+# Tue May 1 21:06:33 2007 -+# -+CONFIG_ARM=y -+# CONFIG_GENERIC_TIME is not set -+CONFIG_MMU=y -+CONFIG_GENERIC_HARDIRQS=y -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_HARDIRQS_SW_RESEND=y -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_RWSEM_GENERIC_SPINLOCK=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_VECTORS_BASE=0xffff0000 -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+ -+# -+# Code maturity level options -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_BROKEN_ON_SMP=y -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+ -+# -+# General setup -+# -+CONFIG_LOCALVERSION="" -+# CONFIG_LOCALVERSION_AUTO is not set -+# CONFIG_SWAP is not set -+CONFIG_SYSVIPC=y -+# CONFIG_IPC_NS is not set -+# CONFIG_POSIX_MQUEUE is not set -+# CONFIG_BSD_PROCESS_ACCT is not set -+# CONFIG_TASKSTATS is not set -+# CONFIG_UTS_NS is not set -+# CONFIG_AUDIT is not set -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_SYSFS_DEPRECATED=y -+# CONFIG_RELAY is not set -+CONFIG_INITRAMFS_SOURCE="" -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_SYSCTL=y -+# CONFIG_EMBEDDED is not set -+CONFIG_UID16=y -+CONFIG_SYSCTL_SYSCALL=y -+CONFIG_KALLSYMS=y -+# CONFIG_KALLSYMS_ALL is not set -+# CONFIG_KALLSYMS_EXTRA_PASS is not set -+CONFIG_HOTPLUG=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+CONFIG_BASE_FULL=y -+CONFIG_FUTEX=y -+CONFIG_EPOLL=y -+CONFIG_SHMEM=y -+CONFIG_SLAB=y -+CONFIG_VM_EVENT_COUNTERS=y -+CONFIG_RT_MUTEXES=y -+# CONFIG_TINY_SHMEM is not set -+CONFIG_BASE_SMALL=0 -+# CONFIG_SLOB is not set -+ -+# -+# Loadable module support -+# -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODULE_FORCE_UNLOAD=y -+# CONFIG_MODVERSIONS is not set -+# CONFIG_MODULE_SRCVERSION_ALL is not set -+# CONFIG_KMOD is not set -+ -+# -+# Block layer -+# -+CONFIG_BLOCK=y -+# CONFIG_LBD is not set -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_AS=y -+# CONFIG_IOSCHED_DEADLINE is not set -+# CONFIG_IOSCHED_CFQ is not set -+CONFIG_DEFAULT_AS=y -+# CONFIG_DEFAULT_DEADLINE is not set -+# CONFIG_DEFAULT_CFQ is not set -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="anticipatory" -+ -+# -+# System Type -+# -+# CONFIG_ARCH_AAEC2000 is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_REALVIEW is not set -+# CONFIG_ARCH_VERSATILE is not set -+CONFIG_ARCH_AT91=y -+# CONFIG_ARCH_CLPS7500 is not set -+# CONFIG_ARCH_CLPS711X is not set -+# CONFIG_ARCH_CO285 is not set -+# CONFIG_ARCH_EBSA110 is not set -+# CONFIG_ARCH_EP93XX is not set -+# CONFIG_ARCH_FOOTBRIDGE is not set -+# CONFIG_ARCH_NETX is not set -+# CONFIG_ARCH_H720X is not set -+# CONFIG_ARCH_IMX is not set -+# CONFIG_ARCH_IOP32X is not set -+# CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IOP13XX is not set -+# CONFIG_ARCH_IXP4XX is not set -+# CONFIG_ARCH_IXP2000 is not set -+# CONFIG_ARCH_IXP23XX is not set -+# CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_PNX4008 is not set -+# CONFIG_ARCH_PXA is not set -+# CONFIG_ARCH_RPC is not set -+# CONFIG_ARCH_SA1100 is not set -+# CONFIG_ARCH_S3C2410 is not set -+# CONFIG_ARCH_SHARK is not set -+# CONFIG_ARCH_LH7A40X is not set -+# CONFIG_ARCH_OMAP is not set -+ -+# -+# Atmel AT91 System-on-Chip -+# -+# CONFIG_ARCH_AT91RM9200 is not set -+CONFIG_ARCH_AT91SAM9260=y -+# CONFIG_ARCH_AT91SAM9261 is not set -+# CONFIG_ARCH_AT91SAM9263 is not set -+ -+# -+# AT91SAM9260 Board Type -+# -+# CONFIG_MACH_AT91SAM9260EK is not set -+CONFIG_MACH_CAM60=y -+ -+# -+# AT91 Board Options -+# -+ -+# -+# AT91 Feature Selections -+# -+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set -+ -+# -+# Processor Type -+# -+CONFIG_CPU_32=y -+CONFIG_CPU_ARM926T=y -+CONFIG_CPU_32v5=y -+CONFIG_CPU_ABRT_EV5TJ=y -+CONFIG_CPU_CACHE_VIVT=y -+CONFIG_CPU_COPY_V4WB=y -+CONFIG_CPU_TLB_V4WBI=y -+CONFIG_CPU_CP15=y -+CONFIG_CPU_CP15_MMU=y -+ -+# -+# Processor Features -+# -+# CONFIG_ARM_THUMB is not set -+# CONFIG_CPU_ICACHE_DISABLE is not set -+# CONFIG_CPU_DCACHE_DISABLE is not set -+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -+ -+# -+# Bus support -+# -+ -+# -+# PCCARD (PCMCIA/CardBus) support -+# -+# CONFIG_PCCARD is not set -+ -+# -+# Kernel Features -+# -+# CONFIG_PREEMPT is not set -+# CONFIG_NO_IDLE_HZ is not set -+CONFIG_HZ=100 -+# CONFIG_AEABI is not set -+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+# CONFIG_SPARSEMEM_STATIC is not set -+CONFIG_SPLIT_PTLOCK_CPUS=4096 -+# CONFIG_RESOURCES_64BIT is not set -+# CONFIG_LEDS is not set -+CONFIG_ALIGNMENT_TRAP=y -+ -+# -+# Boot options -+# -+CONFIG_ZBOOT_ROM_TEXT=0x22000000 -+CONFIG_ZBOOT_ROM_BSS=0x20004000 -+# CONFIG_ZBOOT_ROM is not set -+CONFIG_CMDLINE="console=ttyS0,115200 noinitrd root=/dev/mtdblock3 rootfstype=jffs2 mem=64M" -+# CONFIG_XIP_KERNEL is not set -+ -+# -+# Floating point emulation -+# -+ -+# -+# At least one emulation must be selected -+# -+CONFIG_FPE_NWFPE=y -+# CONFIG_FPE_NWFPE_XP is not set -+# CONFIG_FPE_FASTFPE is not set -+# CONFIG_VFP is not set -+ -+# -+# Userspace binary formats -+# -+CONFIG_BINFMT_ELF=y -+# CONFIG_BINFMT_AOUT is not set -+# CONFIG_BINFMT_MISC is not set -+# CONFIG_ARTHUR is not set -+ -+# -+# Power management options -+# -+# CONFIG_PM is not set -+# CONFIG_APM is not set -+ -+# -+# Networking -+# -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+# CONFIG_NETDEBUG is not set -+CONFIG_PACKET=y -+# CONFIG_PACKET_MMAP is not set -+CONFIG_UNIX=y -+CONFIG_XFRM=y -+# CONFIG_XFRM_USER is not set -+# CONFIG_XFRM_SUB_POLICY is not set -+# CONFIG_NET_KEY is not set -+CONFIG_INET=y -+# CONFIG_IP_MULTICAST is not set -+# CONFIG_IP_ADVANCED_ROUTER is not set -+CONFIG_IP_FIB_HASH=y -+CONFIG_IP_PNP=y -+# CONFIG_IP_PNP_DHCP is not set -+CONFIG_IP_PNP_BOOTP=y -+# CONFIG_IP_PNP_RARP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_ARPD is not set -+# CONFIG_SYN_COOKIES is not set -+# CONFIG_INET_AH is not set -+# CONFIG_INET_ESP is not set -+# CONFIG_INET_IPCOMP is not set -+# CONFIG_INET_XFRM_TUNNEL is not set -+# CONFIG_INET_TUNNEL is not set -+CONFIG_INET_XFRM_MODE_TRANSPORT=y -+CONFIG_INET_XFRM_MODE_TUNNEL=y -+CONFIG_INET_XFRM_MODE_BEET=y -+CONFIG_INET_DIAG=y -+CONFIG_INET_TCP_DIAG=y -+# CONFIG_TCP_CONG_ADVANCED is not set -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set -+# CONFIG_IPV6 is not set -+# CONFIG_INET6_XFRM_TUNNEL is not set -+# CONFIG_INET6_TUNNEL is not set -+# CONFIG_NETWORK_SECMARK is not set -+# CONFIG_NETFILTER is not set -+ -+# -+# DCCP Configuration (EXPERIMENTAL) -+# -+# CONFIG_IP_DCCP is not set -+ -+# -+# SCTP Configuration (EXPERIMENTAL) -+# -+# CONFIG_IP_SCTP is not set -+ -+# -+# TIPC Configuration (EXPERIMENTAL) -+# -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+ -+# -+# QoS and/or fair queueing -+# -+# CONFIG_NET_SCHED is not set -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_HAMRADIO is not set -+# CONFIG_IRDA is not set -+# CONFIG_BT is not set -+# CONFIG_IEEE80211 is not set -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+# CONFIG_FW_LOADER is not set -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_SYS_HYPERVISOR is not set -+ -+# -+# Connector - unified userspace <-> kernelspace linker -+# -+# CONFIG_CONNECTOR is not set -+ -+# -+# Memory Technology Devices (MTD) -+# -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+CONFIG_MTD_CONCAT=y -+CONFIG_MTD_PARTITIONS=y -+# CONFIG_MTD_REDBOOT_PARTS is not set -+CONFIG_MTD_CMDLINE_PARTS=y -+# CONFIG_MTD_AFS_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLKDEVS=y -+CONFIG_MTD_BLOCK=y -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+CONFIG_MTD_CFI=y -+# CONFIG_MTD_JEDECPROBE is not set -+CONFIG_MTD_GEN_PROBE=y -+# CONFIG_MTD_CFI_ADV_OPTIONS is not set -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+# CONFIG_MTD_CFI_INTELEXT is not set -+# CONFIG_MTD_CFI_AMDSTD is not set -+# CONFIG_MTD_CFI_STAA is not set -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+# CONFIG_MTD_OBSOLETE_CHIPS is not set -+ -+# -+# Mapping drivers for chip access -+# -+CONFIG_MTD_COMPLEX_MAPPINGS=y -+# CONFIG_MTD_PHYSMAP is not set -+# CONFIG_MTD_ARM_INTEGRATOR is not set -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+CONFIG_MTD_DATAFLASH=y -+# CONFIG_MTD_M25P80 is not set -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+ -+# -+# NAND Flash Device Drivers -+# -+# CONFIG_MTD_NAND is not set -+ -+# -+# OneNAND Flash Device Drivers -+# -+# CONFIG_MTD_ONENAND is not set -+ -+# -+# Parallel port support -+# -+# CONFIG_PARPORT is not set -+ -+# -+# Plug and Play support -+# -+ -+# -+# Block devices -+# -+# CONFIG_BLK_DEV_COW_COMMON is not set -+# CONFIG_BLK_DEV_LOOP is not set -+# CONFIG_BLK_DEV_NBD is not set -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=16 -+CONFIG_BLK_DEV_RAM_SIZE=8192 -+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -+CONFIG_BLK_DEV_INITRD=y -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+ -+# -+# SCSI device support -+# -+# CONFIG_RAID_ATTRS is not set -+# CONFIG_SCSI is not set -+# CONFIG_SCSI_NETLINK is not set -+ -+# -+# Serial ATA (prod) and Parallel ATA (experimental) drivers -+# -+# CONFIG_ATA is not set -+ -+# -+# Multi-device support (RAID and LVM) -+# -+# CONFIG_MD is not set -+ -+# -+# Fusion MPT device support -+# -+# CONFIG_FUSION is not set -+ -+# -+# IEEE 1394 (FireWire) support -+# -+ -+# -+# I2O device support -+# -+ -+# -+# Network device support -+# -+CONFIG_NETDEVICES=y -+# CONFIG_DUMMY is not set -+# CONFIG_BONDING is not set -+# CONFIG_EQUALIZER is not set -+# CONFIG_TUN is not set -+ -+# -+# PHY device support -+# -+# CONFIG_PHYLIB is not set -+ -+# -+# Ethernet (10 or 100Mbit) -+# -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=y -+CONFIG_MACB=y -+# CONFIG_SMC91X is not set -+# CONFIG_DM9000 is not set -+ -+# -+# Ethernet (1000 Mbit) -+# -+ -+# -+# Ethernet (10000 Mbit) -+# -+ -+# -+# Token Ring devices -+# -+ -+# -+# Wireless LAN (non-hamradio) -+# -+# CONFIG_NET_RADIO is not set -+ -+# -+# Wan interfaces -+# -+# CONFIG_WAN is not set -+# CONFIG_PPP is not set -+# CONFIG_SLIP is not set -+# CONFIG_SHAPER is not set -+# CONFIG_NETCONSOLE is not set -+# CONFIG_NETPOLL is not set -+# CONFIG_NET_POLL_CONTROLLER is not set -+ -+# -+# ISDN subsystem -+# -+# CONFIG_ISDN is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+# CONFIG_INPUT_FF_MEMLESS is not set -+ -+# -+# Userland interfaces -+# -+CONFIG_INPUT_MOUSEDEV=y -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+# CONFIG_INPUT_JOYDEV is not set -+# CONFIG_INPUT_TSDEV is not set -+# CONFIG_INPUT_EVDEV is not set -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+# CONFIG_INPUT_KEYBOARD is not set -+# CONFIG_INPUT_MOUSE is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+# CONFIG_INPUT_MISC is not set -+ -+# -+# Hardware I/O ports -+# -+# CONFIG_SERIO is not set -+# CONFIG_GAMEPORT is not set -+ -+# -+# Character devices -+# -+CONFIG_VT=y -+CONFIG_VT_CONSOLE=y -+CONFIG_HW_CONSOLE=y -+# CONFIG_VT_HW_CONSOLE_BINDING is not set -+# CONFIG_SERIAL_NONSTANDARD is not set -+ -+# -+# Serial drivers -+# -+# CONFIG_SERIAL_8250 is not set -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_ATMEL=y -+CONFIG_SERIAL_ATMEL_CONSOLE=y -+# CONFIG_SERIAL_ATMEL_TTYAT is not set -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+CONFIG_UNIX98_PTYS=y -+CONFIG_LEGACY_PTYS=y -+CONFIG_LEGACY_PTY_COUNT=256 -+ -+# -+# IPMI -+# -+# CONFIG_IPMI_HANDLER is not set -+ -+# -+# Watchdog Cards -+# -+# CONFIG_WATCHDOG is not set -+# CONFIG_HW_RANDOM is not set -+# CONFIG_NVRAM is not set -+# CONFIG_DTLK is not set -+# CONFIG_R3964 is not set -+# CONFIG_RAW_DRIVER is not set -+ -+# -+# TPM devices -+# -+# CONFIG_TCG_TPM is not set -+ -+# -+# I2C support -+# -+# CONFIG_I2C is not set -+ -+# -+# SPI support -+# -+CONFIG_SPI=y -+# CONFIG_SPI_DEBUG is not set -+CONFIG_SPI_MASTER=y -+ -+# -+# SPI Master Controller Drivers -+# -+CONFIG_SPI_ATMEL=y -+# CONFIG_SPI_BITBANG is not set -+ -+# -+# SPI Protocol Masters -+# -+ -+# -+# Dallas's 1-wire bus -+# -+# CONFIG_W1 is not set -+ -+# -+# Hardware Monitoring support -+# -+# CONFIG_HWMON is not set -+# CONFIG_HWMON_VID is not set -+ -+# -+# Misc devices -+# -+# CONFIG_TIFM_CORE is not set -+ -+# -+# LED devices -+# -+# CONFIG_NEW_LEDS is not set -+ -+# -+# LED drivers -+# -+ -+# -+# LED Triggers -+# -+ -+# -+# Multimedia devices -+# -+# CONFIG_VIDEO_DEV is not set -+ -+# -+# Digital Video Broadcasting Devices -+# -+# CONFIG_DVB is not set -+ -+# -+# Graphics support -+# -+# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_FB is not set -+ -+# -+# Console display driver support -+# -+# CONFIG_VGA_CONSOLE is not set -+CONFIG_DUMMY_CONSOLE=y -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -+ -+# -+# Sound -+# -+# CONFIG_SOUND is not set -+ -+# -+# HID Devices -+# -+# CONFIG_HID is not set -+ -+# -+# USB support -+# -+CONFIG_USB_ARCH_HAS_HCD=y -+CONFIG_USB_ARCH_HAS_OHCI=y -+# CONFIG_USB_ARCH_HAS_EHCI is not set -+# CONFIG_USB is not set -+ -+# -+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -+# -+ -+# -+# USB Gadget Support -+# -+# CONFIG_USB_GADGET is not set -+ -+# -+# MMC/SD Card support -+# -+# CONFIG_MMC is not set -+ -+# -+# Real Time Clock -+# -+CONFIG_RTC_LIB=y -+# CONFIG_RTC_CLASS is not set -+ -+# -+# File systems -+# -+CONFIG_EXT2_FS=y -+# CONFIG_EXT2_FS_XATTR is not set -+# CONFIG_EXT2_FS_XIP is not set -+CONFIG_EXT3_FS=y -+CONFIG_EXT3_FS_XATTR=y -+# CONFIG_EXT3_FS_POSIX_ACL is not set -+# CONFIG_EXT3_FS_SECURITY is not set -+# CONFIG_EXT4DEV_FS is not set -+CONFIG_JBD=y -+# CONFIG_JBD_DEBUG is not set -+CONFIG_FS_MBCACHE=y -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+# CONFIG_FS_POSIX_ACL is not set -+# CONFIG_XFS_FS is not set -+# CONFIG_GFS2_FS is not set -+# CONFIG_OCFS2_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_ROMFS_FS is not set -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+# CONFIG_QUOTA is not set -+CONFIG_DNOTIFY=y -+# CONFIG_AUTOFS_FS is not set -+CONFIG_AUTOFS4_FS=y -+# CONFIG_FUSE_FS is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+# CONFIG_ISO9660_FS is not set -+# CONFIG_UDF_FS is not set -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=y -+# CONFIG_MSDOS_FS is not set -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+# CONFIG_NTFS_FS is not set -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_SYSCTL=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+# CONFIG_TMPFS_POSIX_ACL is not set -+# CONFIG_HUGETLB_PAGE is not set -+CONFIG_RAMFS=y -+# CONFIG_CONFIGFS_FS is not set -+ -+# -+# Miscellaneous filesystems -+# -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+# CONFIG_JFFS2_SUMMARY is not set -+# CONFIG_JFFS2_FS_XATTR is not set -+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_ZLIB=y -+CONFIG_JFFS2_RTIME=y -+# CONFIG_JFFS2_RUBIN is not set -+CONFIG_CRAMFS=y -+# CONFIG_VXFS_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+ -+# -+# Network File Systems -+# -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3=y -+# CONFIG_NFS_V3_ACL is not set -+# CONFIG_NFS_V4 is not set -+# CONFIG_NFS_DIRECTIO is not set -+# CONFIG_NFSD is not set -+CONFIG_ROOT_NFS=y -+CONFIG_LOCKD=y -+CONFIG_LOCKD_V4=y -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=y -+# CONFIG_RPCSEC_GSS_KRB5 is not set -+# CONFIG_RPCSEC_GSS_SPKM3 is not set -+# CONFIG_SMB_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_NCP_FS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+# CONFIG_9P_FS is not set -+ -+# -+# Partition Types -+# -+# CONFIG_PARTITION_ADVANCED is not set -+CONFIG_MSDOS_PARTITION=y -+ -+# -+# Native Language Support -+# -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="iso8859-1" -+CONFIG_NLS_CODEPAGE_437=y -+# CONFIG_NLS_CODEPAGE_737 is not set -+# CONFIG_NLS_CODEPAGE_775 is not set -+CONFIG_NLS_CODEPAGE_850=y -+# CONFIG_NLS_CODEPAGE_852 is not set -+# CONFIG_NLS_CODEPAGE_855 is not set -+# CONFIG_NLS_CODEPAGE_857 is not set -+# CONFIG_NLS_CODEPAGE_860 is not set -+# CONFIG_NLS_CODEPAGE_861 is not set -+# CONFIG_NLS_CODEPAGE_862 is not set -+# CONFIG_NLS_CODEPAGE_863 is not set -+# CONFIG_NLS_CODEPAGE_864 is not set -+# CONFIG_NLS_CODEPAGE_865 is not set -+# CONFIG_NLS_CODEPAGE_866 is not set -+# CONFIG_NLS_CODEPAGE_869 is not set -+# CONFIG_NLS_CODEPAGE_936 is not set -+# CONFIG_NLS_CODEPAGE_950 is not set -+# CONFIG_NLS_CODEPAGE_932 is not set -+# CONFIG_NLS_CODEPAGE_949 is not set -+# CONFIG_NLS_CODEPAGE_874 is not set -+# CONFIG_NLS_ISO8859_8 is not set -+# CONFIG_NLS_CODEPAGE_1250 is not set -+# CONFIG_NLS_CODEPAGE_1251 is not set -+# CONFIG_NLS_ASCII is not set -+CONFIG_NLS_ISO8859_1=y -+# CONFIG_NLS_ISO8859_2 is not set -+# CONFIG_NLS_ISO8859_3 is not set -+# CONFIG_NLS_ISO8859_4 is not set -+# CONFIG_NLS_ISO8859_5 is not set -+# CONFIG_NLS_ISO8859_6 is not set -+# CONFIG_NLS_ISO8859_7 is not set -+# CONFIG_NLS_ISO8859_9 is not set -+# CONFIG_NLS_ISO8859_13 is not set -+# CONFIG_NLS_ISO8859_14 is not set -+# CONFIG_NLS_ISO8859_15 is not set -+# CONFIG_NLS_KOI8_R is not set -+# CONFIG_NLS_KOI8_U is not set -+# CONFIG_NLS_UTF8 is not set -+ -+# -+# Distributed Lock Manager -+# -+# CONFIG_DLM is not set -+ -+# -+# Profiling support -+# -+# CONFIG_PROFILING is not set -+ -+# -+# Kernel hacking -+# -+# CONFIG_PRINTK_TIME is not set -+CONFIG_ENABLE_MUST_CHECK=y -+# CONFIG_MAGIC_SYSRQ is not set -+# CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_DEBUG_FS is not set -+# CONFIG_HEADERS_CHECK is not set -+CONFIG_DEBUG_KERNEL=y -+CONFIG_LOG_BUF_SHIFT=14 -+CONFIG_DETECT_SOFTLOCKUP=y -+# CONFIG_SCHEDSTATS is not set -+# CONFIG_DEBUG_SLAB is not set -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+# CONFIG_DEBUG_SPINLOCK is not set -+# CONFIG_DEBUG_MUTEXES is not set -+# CONFIG_DEBUG_RWSEMS is not set -+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_DEBUG_KOBJECT is not set -+CONFIG_DEBUG_BUGVERBOSE=y -+# CONFIG_DEBUG_INFO is not set -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_LIST is not set -+CONFIG_FRAME_POINTER=y -+CONFIG_FORCED_INLINING=y -+# CONFIG_RCU_TORTURE_TEST is not set -+CONFIG_DEBUG_USER=y -+# CONFIG_DEBUG_ERRORS is not set -+CONFIG_DEBUG_LL=y -+# CONFIG_DEBUG_ICEDCC is not set -+ -+# -+# Security options -+# -+# CONFIG_KEYS is not set -+# CONFIG_SECURITY is not set -+ -+# -+# Cryptographic options -+# -+# CONFIG_CRYPTO is not set -+ -+# -+# Library routines -+# -+CONFIG_BITREVERSE=y -+# CONFIG_CRC_CCITT is not set -+# CONFIG_CRC16 is not set -+CONFIG_CRC32=y -+# CONFIG_LIBCRC32C is not set -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_PLIST=y -+CONFIG_IOMAP_COPY=y -diff -urN linux-2.6.22-rc5/arch/arm/configs/kb9202_defconfig linux-2.6.22-rc5.new/arch/arm/configs/kb9202_defconfig ---- linux-2.6.22-rc5/arch/arm/configs/kb9202_defconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/configs/kb9202_defconfig 2007-07-29 05:23:04.000000000 +0200 -@@ -1,19 +1,31 @@ - # - # Automatically generated make config: don't edit --# Linux kernel version: 2.6.13-rc2 --# Sun Aug 14 19:26:59 2005 -+# Linux kernel version: 2.6.21 -+# Mon May 7 11:43:14 2007 - # - CONFIG_ARM=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+CONFIG_GENERIC_GPIO=y -+# CONFIG_GENERIC_TIME is not set - CONFIG_MMU=y --CONFIG_UID16=y -+# CONFIG_NO_IOPORT is not set -+CONFIG_GENERIC_HARDIRQS=y -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_HARDIRQS_SW_RESEND=y -+CONFIG_GENERIC_IRQ_PROBE=y - CONFIG_RWSEM_GENERIC_SPINLOCK=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set -+CONFIG_GENERIC_HWEIGHT=y - CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ZONE_DMA=y -+CONFIG_VECTORS_BASE=0xffff0000 -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - - # - # Code maturity level options - # --# CONFIG_EXPERIMENTAL is not set --CONFIG_CLEAN_COMPILE=y -+CONFIG_EXPERIMENTAL=y - CONFIG_BROKEN_ON_SMP=y - CONFIG_INIT_ENV_ARG_LIMIT=32 - -@@ -21,54 +33,103 @@ - # General setup - # - CONFIG_LOCALVERSION="" --# CONFIG_SWAP is not set --# CONFIG_SYSVIPC is not set --# CONFIG_BSD_PROCESS_ACCT is not set -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+# CONFIG_IPC_NS is not set -+CONFIG_SYSVIPC_SYSCTL=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_BSD_PROCESS_ACCT=y -+# CONFIG_BSD_PROCESS_ACCT_V3 is not set -+# CONFIG_TASKSTATS is not set -+# CONFIG_UTS_NS is not set -+CONFIG_AUDIT=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_SYSFS_DEPRECATED=y -+# CONFIG_RELAY is not set -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="" -+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - CONFIG_SYSCTL=y --# CONFIG_AUDIT is not set --CONFIG_HOTPLUG=y --# CONFIG_KOBJECT_UEVENT is not set --# CONFIG_IKCONFIG is not set - # CONFIG_EMBEDDED is not set -+CONFIG_UID16=y -+CONFIG_SYSCTL_SYSCALL=y - CONFIG_KALLSYMS=y - # CONFIG_KALLSYMS_ALL is not set --# CONFIG_KALLSYMS_EXTRA_PASS is not set -+CONFIG_KALLSYMS_EXTRA_PASS=y -+CONFIG_HOTPLUG=y - CONFIG_PRINTK=y - CONFIG_BUG=y -+CONFIG_ELF_CORE=y - CONFIG_BASE_FULL=y - CONFIG_FUTEX=y - CONFIG_EPOLL=y --CONFIG_CC_OPTIMIZE_FOR_SIZE=y - CONFIG_SHMEM=y --CONFIG_CC_ALIGN_FUNCTIONS=0 --CONFIG_CC_ALIGN_LABELS=0 --CONFIG_CC_ALIGN_LOOPS=0 --CONFIG_CC_ALIGN_JUMPS=0 -+CONFIG_SLAB=y -+CONFIG_VM_EVENT_COUNTERS=y -+CONFIG_RT_MUTEXES=y - # CONFIG_TINY_SHMEM is not set - CONFIG_BASE_SMALL=0 -+# CONFIG_SLOB is not set - - # - # Loadable module support - # - CONFIG_MODULES=y - CONFIG_MODULE_UNLOAD=y --CONFIG_OBSOLETE_MODPARM=y --# CONFIG_MODULE_SRCVERSION_ALL is not set -+# CONFIG_MODULE_FORCE_UNLOAD is not set -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y - CONFIG_KMOD=y - - # -+# Block layer -+# -+CONFIG_BLOCK=y -+CONFIG_LBD=y -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_AS=y -+CONFIG_IOSCHED_DEADLINE=y -+CONFIG_IOSCHED_CFQ=y -+# CONFIG_DEFAULT_AS is not set -+# CONFIG_DEFAULT_DEADLINE is not set -+CONFIG_DEFAULT_CFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="cfq" -+ -+# - # System Type - # -+# CONFIG_ARCH_AAEC2000 is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_REALVIEW is not set -+# CONFIG_ARCH_VERSATILE is not set -+CONFIG_ARCH_AT91=y - # CONFIG_ARCH_CLPS7500 is not set - # CONFIG_ARCH_CLPS711X is not set - # CONFIG_ARCH_CO285 is not set - # CONFIG_ARCH_EBSA110 is not set -+# CONFIG_ARCH_EP93XX is not set - # CONFIG_ARCH_FOOTBRIDGE is not set --# CONFIG_ARCH_INTEGRATOR is not set --# CONFIG_ARCH_IOP3XX is not set -+# CONFIG_ARCH_NETX is not set -+# CONFIG_ARCH_H720X is not set -+# CONFIG_ARCH_IMX is not set -+# CONFIG_ARCH_IOP32X is not set -+# CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IOP13XX is not set - # CONFIG_ARCH_IXP4XX is not set - # CONFIG_ARCH_IXP2000 is not set -+# CONFIG_ARCH_IXP23XX is not set - # CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_NS9XXX is not set -+# CONFIG_ARCH_PNX4008 is not set - # CONFIG_ARCH_PXA is not set - # CONFIG_ARCH_RPC is not set - # CONFIG_ARCH_SA1100 is not set -@@ -76,34 +137,52 @@ - # CONFIG_ARCH_SHARK is not set - # CONFIG_ARCH_LH7A40X is not set - # CONFIG_ARCH_OMAP is not set --# CONFIG_ARCH_VERSATILE is not set --# CONFIG_ARCH_IMX is not set --# CONFIG_ARCH_H720X is not set --# CONFIG_ARCH_AAEC2000 is not set --CONFIG_ARCH_AT91=y -+ -+# -+# Atmel AT91 System-on-Chip -+# - CONFIG_ARCH_AT91RM9200=y -+# CONFIG_ARCH_AT91SAM9260 is not set -+# CONFIG_ARCH_AT91SAM9261 is not set -+# CONFIG_ARCH_AT91SAM9263 is not set - - # --# AT91RM9200 Implementations -+# AT91RM9200 Board Type - # -+# CONFIG_MACH_ONEARM is not set - # CONFIG_ARCH_AT91RM9200DK is not set - # CONFIG_MACH_AT91RM9200EK is not set - # CONFIG_MACH_CSB337 is not set - # CONFIG_MACH_CSB637 is not set - # CONFIG_MACH_CARMEVA is not set -+# CONFIG_MACH_ATEB9200 is not set - CONFIG_MACH_KB9200=y -+# CONFIG_MACH_KAFA is not set -+# CONFIG_MACH_CHUB is not set -+ -+# -+# AT91 Board Options -+# -+ -+# -+# AT91 Feature Selections -+# -+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set -+# CONFIG_ATMEL_TCLIB is not set - - # - # Processor Type - # - CONFIG_CPU_32=y - CONFIG_CPU_ARM920T=y --CONFIG_CPU_32v4=y -+CONFIG_CPU_32v4T=y - CONFIG_CPU_ABRT_EV4T=y - CONFIG_CPU_CACHE_V4WT=y - CONFIG_CPU_CACHE_VIVT=y - CONFIG_CPU_COPY_V4WB=y - CONFIG_CPU_TLB_V4WBI=y -+CONFIG_CPU_CP15=y -+CONFIG_CPU_CP15_MMU=y - - # - # Processor Features -@@ -112,24 +191,44 @@ - # CONFIG_CPU_ICACHE_DISABLE is not set - # CONFIG_CPU_DCACHE_DISABLE is not set - # CONFIG_CPU_DCACHE_WRITETHROUGH is not set -+# CONFIG_OUTER_CACHE is not set - - # - # Bus support - # --CONFIG_ISA_DMA_API=y - - # - # PCCARD (PCMCIA/CardBus) support - # --# CONFIG_PCCARD is not set -+CONFIG_PCCARD=m -+# CONFIG_PCMCIA_DEBUG is not set -+CONFIG_PCMCIA=m -+CONFIG_PCMCIA_LOAD_CIS=y -+CONFIG_PCMCIA_IOCTL=y -+ -+# -+# PC-card bridges -+# -+# CONFIG_AT91_CF is not set - - # - # Kernel Features - # -+# CONFIG_PREEMPT is not set - # CONFIG_NO_IDLE_HZ is not set -+CONFIG_HZ=100 -+# CONFIG_AEABI is not set - # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set - CONFIG_FLATMEM=y - CONFIG_FLAT_NODE_MEM_MAP=y -+# CONFIG_SPARSEMEM_STATIC is not set -+CONFIG_SPLIT_PTLOCK_CPUS=4096 -+# CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 - # CONFIG_LEDS is not set - CONFIG_ALIGNMENT_TRAP=y - -@@ -138,8 +237,10 @@ - # - CONFIG_ZBOOT_ROM_TEXT=0x10000000 - CONFIG_ZBOOT_ROM_BSS=0x20040000 --CONFIG_ZBOOT_ROM=y --CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram rw initrd=0x20210000,654933" -+# CONFIG_ZBOOT_ROM is not set -+CONFIG_CMDLINE="noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M" -+# CONFIG_XIP_KERNEL is not set -+# CONFIG_KEXEC is not set - - # - # Floating point emulation -@@ -150,6 +251,7 @@ - # - CONFIG_FPE_NWFPE=y - # CONFIG_FPE_NWFPE_XP is not set -+# CONFIG_FPE_FASTFPE is not set - - # - # Userspace binary formats -@@ -165,6 +267,96 @@ - # CONFIG_PM is not set - - # -+# Networking -+# -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+# CONFIG_NETDEBUG is not set -+CONFIG_PACKET=y -+# CONFIG_PACKET_MMAP is not set -+CONFIG_UNIX=y -+# CONFIG_NET_KEY is not set -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+# CONFIG_IP_ADVANCED_ROUTER is not set -+CONFIG_IP_FIB_HASH=y -+CONFIG_IP_PNP=y -+# CONFIG_IP_PNP_DHCP is not set -+# CONFIG_IP_PNP_BOOTP is not set -+# CONFIG_IP_PNP_RARP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_IP_MROUTE is not set -+# CONFIG_ARPD is not set -+# CONFIG_SYN_COOKIES is not set -+# CONFIG_INET_AH is not set -+# CONFIG_INET_ESP is not set -+# CONFIG_INET_IPCOMP is not set -+# CONFIG_INET_XFRM_TUNNEL is not set -+# CONFIG_INET_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set -+# CONFIG_INET_DIAG is not set -+# CONFIG_TCP_CONG_ADVANCED is not set -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set -+# CONFIG_IPV6 is not set -+# CONFIG_INET6_XFRM_TUNNEL is not set -+# CONFIG_INET6_TUNNEL is not set -+# CONFIG_NETWORK_SECMARK is not set -+# CONFIG_NETFILTER is not set -+ -+# -+# DCCP Configuration (EXPERIMENTAL) -+# -+# CONFIG_IP_DCCP is not set -+ -+# -+# SCTP Configuration (EXPERIMENTAL) -+# -+CONFIG_IP_SCTP=m -+# CONFIG_SCTP_DBG_MSG is not set -+# CONFIG_SCTP_DBG_OBJCNT is not set -+# CONFIG_SCTP_HMAC_NONE is not set -+# CONFIG_SCTP_HMAC_SHA1 is not set -+CONFIG_SCTP_HMAC_MD5=y -+ -+# -+# TIPC Configuration (EXPERIMENTAL) -+# -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+ -+# -+# QoS and/or fair queueing -+# -+# CONFIG_NET_SCHED is not set -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_HAMRADIO is not set -+# CONFIG_IRDA is not set -+# CONFIG_BT is not set -+# CONFIG_IEEE80211 is not set -+ -+# - # Device Drivers - # - -@@ -173,13 +365,95 @@ - # - CONFIG_STANDALONE=y - CONFIG_PREVENT_FIRMWARE_BUILD=y --# CONFIG_FW_LOADER is not set --CONFIG_DEBUG_DRIVER=y -+CONFIG_FW_LOADER=y -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set -+# CONFIG_SYS_HYPERVISOR is not set -+ -+# -+# Connector - unified userspace <-> kernelspace linker -+# -+# CONFIG_CONNECTOR is not set - - # - # Memory Technology Devices (MTD) - # --# CONFIG_MTD is not set -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+CONFIG_MTD_CONCAT=y -+CONFIG_MTD_PARTITIONS=y -+# CONFIG_MTD_REDBOOT_PARTS is not set -+CONFIG_MTD_CMDLINE_PARTS=y -+# CONFIG_MTD_AFS_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLKDEVS=y -+CONFIG_MTD_BLOCK=y -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+# CONFIG_MTD_CFI is not set -+# CONFIG_MTD_JEDECPROBE is not set -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+# CONFIG_MTD_OBSOLETE_CHIPS is not set -+ -+# -+# Mapping drivers for chip access -+# -+CONFIG_MTD_COMPLEX_MAPPINGS=y -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+ -+# -+# NAND Flash Device Drivers -+# -+CONFIG_MTD_NAND=y -+# CONFIG_MTD_NAND_VERIFY_WRITE is not set -+# CONFIG_MTD_NAND_ECC_SMC is not set -+CONFIG_MTD_NAND_IDS=y -+# CONFIG_MTD_NAND_DISKONCHIP is not set -+CONFIG_MTD_NAND_AT91=y -+# CONFIG_MTD_NAND_NANDSIM is not set -+ -+# -+# OneNAND Flash Device Drivers -+# -+# CONFIG_MTD_ONENAND is not set - - # - # Parallel port support -@@ -189,6 +463,7 @@ - # - # Plug and Play support - # -+# CONFIG_PNPACPI is not set - - # - # Block devices -@@ -196,28 +471,27 @@ - # CONFIG_BLK_DEV_COW_COMMON is not set - CONFIG_BLK_DEV_LOOP=y - # CONFIG_BLK_DEV_CRYPTOLOOP is not set --CONFIG_BLK_DEV_NBD=y -+# CONFIG_BLK_DEV_NBD is not set - # CONFIG_BLK_DEV_UB is not set - CONFIG_BLK_DEV_RAM=y - CONFIG_BLK_DEV_RAM_COUNT=16 --CONFIG_BLK_DEV_RAM_SIZE=4096 --CONFIG_BLK_DEV_INITRD=y --CONFIG_INITRAMFS_SOURCE="" -+CONFIG_BLK_DEV_RAM_SIZE=16384 -+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 - # CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set - - # --# IO Schedulers -+# ATA/ATAPI/MFM/RLL support - # --CONFIG_IOSCHED_NOOP=y --CONFIG_IOSCHED_AS=y --CONFIG_IOSCHED_DEADLINE=y --CONFIG_IOSCHED_CFQ=y --# CONFIG_ATA_OVER_ETH is not set -+# CONFIG_IDE is not set - - # - # SCSI device support - # -+# CONFIG_RAID_ATTRS is not set - CONFIG_SCSI=y -+# CONFIG_SCSI_TGT is not set -+# CONFIG_SCSI_NETLINK is not set - CONFIG_SCSI_PROC_FS=y - - # -@@ -233,97 +507,61 @@ - # - # Some SCSI devices (e.g. CD jukebox) support multiple LUNs - # --# CONFIG_SCSI_MULTI_LUN is not set --# CONFIG_SCSI_CONSTANTS is not set --# CONFIG_SCSI_LOGGING is not set -+CONFIG_SCSI_MULTI_LUN=y -+CONFIG_SCSI_CONSTANTS=y -+CONFIG_SCSI_LOGGING=y -+# CONFIG_SCSI_SCAN_ASYNC is not set - - # --# SCSI Transport Attributes -+# SCSI Transports - # --# CONFIG_SCSI_SPI_ATTRS is not set -+CONFIG_SCSI_SPI_ATTRS=m - # CONFIG_SCSI_FC_ATTRS is not set - # CONFIG_SCSI_ISCSI_ATTRS is not set -+# CONFIG_SCSI_SAS_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set - - # - # SCSI low-level drivers - # --# CONFIG_SCSI_SATA is not set -+# CONFIG_ISCSI_TCP is not set - # CONFIG_SCSI_DEBUG is not set - - # --# Multi-device support (RAID and LVM) --# --# CONFIG_MD is not set -- --# --# Fusion MPT device support -+# PCMCIA SCSI adapter support - # --# CONFIG_FUSION is not set -+# CONFIG_PCMCIA_AHA152X is not set -+# CONFIG_PCMCIA_FDOMAIN is not set -+# CONFIG_PCMCIA_NINJA_SCSI is not set -+# CONFIG_PCMCIA_QLOGIC is not set -+# CONFIG_PCMCIA_SYM53C500 is not set - - # --# IEEE 1394 (FireWire) support -+# Serial ATA (prod) and Parallel ATA (experimental) drivers - # -+# CONFIG_ATA is not set - - # --# I2O device support -+# Multi-device support (RAID and LVM) - # -+# CONFIG_MD is not set - - # --# Networking support -+# Fusion MPT device support - # --CONFIG_NET=y -+# CONFIG_FUSION is not set - - # --# Networking options -+# IEEE 1394 (FireWire) support - # --CONFIG_PACKET=y --# CONFIG_PACKET_MMAP is not set --CONFIG_UNIX=y --# CONFIG_NET_KEY is not set --CONFIG_INET=y --CONFIG_IP_MULTICAST=y --# CONFIG_IP_ADVANCED_ROUTER is not set --CONFIG_IP_FIB_HASH=y --CONFIG_IP_PNP=y --CONFIG_IP_PNP_DHCP=y --# CONFIG_IP_PNP_BOOTP is not set --# CONFIG_IP_PNP_RARP is not set --# CONFIG_NET_IPIP is not set --# CONFIG_NET_IPGRE is not set --# CONFIG_IP_MROUTE is not set --# CONFIG_SYN_COOKIES is not set --# CONFIG_INET_AH is not set --# CONFIG_INET_ESP is not set --# CONFIG_INET_IPCOMP is not set --# CONFIG_INET_TUNNEL is not set --# CONFIG_IP_TCPDIAG is not set --# CONFIG_IP_TCPDIAG_IPV6 is not set --# CONFIG_TCP_CONG_ADVANCED is not set --CONFIG_TCP_CONG_BIC=y --# CONFIG_IPV6 is not set --# CONFIG_NETFILTER is not set --# CONFIG_BRIDGE is not set --# CONFIG_VLAN_8021Q is not set --# CONFIG_DECNET is not set --# CONFIG_LLC2 is not set --# CONFIG_IPX is not set --# CONFIG_ATALK is not set - - # --# QoS and/or fair queueing -+# I2O device support - # --# CONFIG_NET_SCHED is not set --# CONFIG_NET_CLS_ROUTE is not set - - # --# Network testing -+# Network device support - # --# CONFIG_NET_PKTGEN is not set --# CONFIG_NETPOLL is not set --# CONFIG_NET_POLL_CONTROLLER is not set --# CONFIG_HAMRADIO is not set --# CONFIG_IRDA is not set --# CONFIG_BT is not set - CONFIG_NETDEVICES=y - # CONFIG_DUMMY is not set - # CONFIG_BONDING is not set -@@ -331,6 +569,11 @@ - # CONFIG_TUN is not set - - # -+# PHY device support -+# -+# CONFIG_PHYLIB is not set -+ -+# - # Ethernet (10 or 100Mbit) - # - CONFIG_NET_ETHERNET=y -@@ -357,11 +600,20 @@ - # CONFIG_NET_RADIO is not set - - # -+# PCMCIA network device support -+# -+# CONFIG_NET_PCMCIA is not set -+ -+# - # Wan interfaces - # - # CONFIG_WAN is not set - # CONFIG_PPP is not set - # CONFIG_SLIP is not set -+# CONFIG_SHAPER is not set -+# CONFIG_NETCONSOLE is not set -+# CONFIG_NETPOLL is not set -+# CONFIG_NET_POLL_CONTROLLER is not set - - # - # ISDN subsystem -@@ -372,6 +624,7 @@ - # Input device support - # - CONFIG_INPUT=y -+# CONFIG_INPUT_FF_MEMLESS is not set - - # - # Userland interfaces -@@ -397,9 +650,7 @@ - # - # Hardware I/O ports - # --CONFIG_SERIO=y --# CONFIG_SERIO_SERPORT is not set --# CONFIG_SERIO_RAW is not set -+# CONFIG_SERIO is not set - # CONFIG_GAMEPORT is not set - - # -@@ -408,6 +659,7 @@ - CONFIG_VT=y - CONFIG_VT_CONSOLE=y - CONFIG_HW_CONSOLE=y -+# CONFIG_VT_HW_CONSOLE_BINDING is not set - # CONFIG_SERIAL_NONSTANDARD is not set - - # -@@ -420,11 +672,11 @@ - # - CONFIG_SERIAL_ATMEL=y - CONFIG_SERIAL_ATMEL_CONSOLE=y -+# CONFIG_SERIAL_ATMEL_TTYAT is not set - CONFIG_SERIAL_CORE=y - CONFIG_SERIAL_CORE_CONSOLE=y - CONFIG_UNIX98_PTYS=y --CONFIG_LEGACY_PTYS=y --CONFIG_LEGACY_PTY_COUNT=256 -+# CONFIG_LEGACY_PTYS is not set - - # - # IPMI -@@ -435,21 +687,23 @@ - # Watchdog Cards - # - # CONFIG_WATCHDOG is not set -+# CONFIG_HW_RANDOM is not set - # CONFIG_NVRAM is not set --# CONFIG_RTC is not set --# CONFIG_AT91RM9200_RTC is not set - # CONFIG_DTLK is not set - # CONFIG_R3964 is not set - - # --# Ftape, the floppy tape device driver -+# PCMCIA character devices - # -+# CONFIG_SYNCLINK_CS is not set -+# CONFIG_CARDMAN_4000 is not set -+# CONFIG_CARDMAN_4040 is not set - # CONFIG_RAW_DRIVER is not set - - # - # TPM devices - # --# CONFIG_AT91_SPI is not set -+# CONFIG_TCG_TPM is not set - - # - # I2C support -@@ -457,10 +711,50 @@ - # CONFIG_I2C is not set - - # -+# SPI support -+# -+# CONFIG_SPI is not set -+# CONFIG_SPI_MASTER is not set -+ -+# -+# Dallas's 1-wire bus -+# -+# CONFIG_W1 is not set -+ -+# -+# Hardware Monitoring support -+# -+CONFIG_HWMON=y -+# CONFIG_HWMON_VID is not set -+# CONFIG_SENSORS_ABITUGURU is not set -+# CONFIG_SENSORS_F71805F is not set -+# CONFIG_SENSORS_PC87427 is not set -+# CONFIG_SENSORS_VT1211 is not set -+CONFIG_HWMON_DEBUG_CHIP=y -+ -+# - # Misc devices - # - - # -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set -+ -+# -+# LED devices -+# -+# CONFIG_NEW_LEDS is not set -+ -+# -+# LED drivers -+# -+ -+# -+# LED Triggers -+# -+ -+# - # Multimedia devices - # - # CONFIG_VIDEO_DEV is not set -@@ -469,17 +763,57 @@ - # Digital Video Broadcasting Devices - # - # CONFIG_DVB is not set -+# CONFIG_USB_DABUSB is not set - - # - # Graphics support - # --# CONFIG_FB is not set -+CONFIG_BACKLIGHT_LCD_SUPPORT=y -+CONFIG_BACKLIGHT_CLASS_DEVICE=y -+# CONFIG_LCD_CLASS_DEVICE is not set -+CONFIG_BACKLIGHT_KB920x=y -+CONFIG_FB=y -+# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_FB_DDC is not set -+CONFIG_FB_CFB_FILLRECT=y -+CONFIG_FB_CFB_COPYAREA=y -+CONFIG_FB_CFB_IMAGEBLIT=y -+# CONFIG_FB_SVGALIB is not set -+# CONFIG_FB_MACMODES is not set -+# CONFIG_FB_BACKLIGHT is not set -+CONFIG_FB_MODE_HELPERS=y -+CONFIG_FB_TILEBLITTING=y -+ -+# -+# Frame buffer hardware drivers -+# -+CONFIG_FB_S1D15605=y -+# CONFIG_FB_S1D13XXX is not set -+# CONFIG_FB_VIRTUAL is not set - - # - # Console display driver support - # - # CONFIG_VGA_CONSOLE is not set - CONFIG_DUMMY_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -+CONFIG_FONTS=y -+# CONFIG_FONT_8x8 is not set -+# CONFIG_FONT_8x16 is not set -+# CONFIG_FONT_6x11 is not set -+# CONFIG_FONT_7x14 is not set -+# CONFIG_FONT_PEARL_8x8 is not set -+# CONFIG_FONT_ACORN_8x8 is not set -+CONFIG_FONT_MINI_4x6=y -+# CONFIG_FONT_SUN8x16 is not set -+# CONFIG_FONT_SUN12x22 is not set -+# CONFIG_FONT_10x18 is not set -+ -+# -+# Logo configuration -+# -+# CONFIG_LOGO is not set - - # - # Sound -@@ -487,82 +821,98 @@ - # CONFIG_SOUND is not set - - # -+# HID Devices -+# -+CONFIG_HID=y -+# CONFIG_HID_DEBUG is not set -+ -+# - # USB support - # - CONFIG_USB_ARCH_HAS_HCD=y - CONFIG_USB_ARCH_HAS_OHCI=y -+# CONFIG_USB_ARCH_HAS_EHCI is not set - CONFIG_USB=y --CONFIG_USB_DEBUG=y -+# CONFIG_USB_DEBUG is not set - - # - # Miscellaneous USB options - # - CONFIG_USB_DEVICEFS=y -+# CONFIG_USB_DYNAMIC_MINORS is not set -+# CONFIG_USB_OTG is not set - - # - # USB Host Controller Drivers - # - # CONFIG_USB_ISP116X_HCD is not set - CONFIG_USB_OHCI_HCD=y --# CONFIG_USB_OHCI_BIG_ENDIAN is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set - CONFIG_USB_OHCI_LITTLE_ENDIAN=y - # CONFIG_USB_SL811_HCD is not set - - # - # USB Device Class drivers - # --# CONFIG_USB_BLUETOOTH_TTY is not set - # CONFIG_USB_ACM is not set - # CONFIG_USB_PRINTER is not set - - # --# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -+# -+ -+# -+# may also be needed; see USB_STORAGE Help for more information - # - CONFIG_USB_STORAGE=y --CONFIG_USB_STORAGE_DEBUG=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+# CONFIG_USB_STORAGE_DATAFAB is not set - # CONFIG_USB_STORAGE_FREECOM is not set - # CONFIG_USB_STORAGE_DPCM is not set -+# CONFIG_USB_STORAGE_USBAT is not set -+# CONFIG_USB_STORAGE_SDDR09 is not set -+# CONFIG_USB_STORAGE_SDDR55 is not set -+# CONFIG_USB_STORAGE_JUMPSHOT is not set -+# CONFIG_USB_STORAGE_ALAUDA is not set -+# CONFIG_USB_STORAGE_KARMA is not set -+CONFIG_USB_LIBUSUAL=y - - # - # USB Input Devices - # --# CONFIG_USB_HID is not set -- --# --# USB HID Boot Protocol drivers --# --# CONFIG_USB_KBD is not set --# CONFIG_USB_MOUSE is not set -+CONFIG_USB_HID=y -+# CONFIG_USB_HIDINPUT_POWERBOOK is not set -+# CONFIG_HID_FF is not set -+# CONFIG_USB_HIDDEV is not set - # CONFIG_USB_AIPTEK is not set - # CONFIG_USB_WACOM is not set - # CONFIG_USB_ACECAD is not set - # CONFIG_USB_KBTAB is not set - # CONFIG_USB_POWERMATE is not set --# CONFIG_USB_MTOUCH is not set --# CONFIG_USB_ITMTOUCH is not set --# CONFIG_USB_EGALAX is not set -+# CONFIG_USB_TOUCHSCREEN is not set -+# CONFIG_USB_YEALINK is not set - # CONFIG_USB_XPAD is not set - # CONFIG_USB_ATI_REMOTE is not set -+# CONFIG_USB_ATI_REMOTE2 is not set -+# CONFIG_USB_KEYSPAN_REMOTE is not set -+# CONFIG_USB_APPLETOUCH is not set -+# CONFIG_USB_GTCO is not set - - # - # USB Imaging devices - # -+# CONFIG_USB_MDC800 is not set - # CONFIG_USB_MICROTEK is not set - - # --# USB Multimedia devices --# --# CONFIG_USB_DABUSB is not set -- --# --# Video4Linux support is needed for USB Multimedia device support --# -- --# - # USB Network Adapters - # -+# CONFIG_USB_CATC is not set - # CONFIG_USB_KAWETH is not set - # CONFIG_USB_PEGASUS is not set -+# CONFIG_USB_RTL8150 is not set -+# CONFIG_USB_USBNET_MII is not set - # CONFIG_USB_USBNET is not set - # CONFIG_USB_MON is not set - -@@ -580,12 +930,23 @@ - # - # CONFIG_USB_EMI62 is not set - # CONFIG_USB_EMI26 is not set -+# CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_AUERSWALD is not set -+# CONFIG_USB_RIO500 is not set -+# CONFIG_USB_LEGOTOWER is not set - # CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set - # CONFIG_USB_LED is not set -+# CONFIG_USB_CYPRESS_CY7C63 is not set - # CONFIG_USB_CYTHERM is not set --# CONFIG_USB_PHIDGETKIT is not set --# CONFIG_USB_PHIDGETSERVO is not set -+# CONFIG_USB_PHIDGET is not set - # CONFIG_USB_IDMOUSE is not set -+# CONFIG_USB_FTDI_ELAN is not set -+# CONFIG_USB_APPLEDISPLAY is not set -+# CONFIG_USB_LD is not set -+# CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set -+# CONFIG_USB_TEST is not set - - # - # USB DSL modem support -@@ -599,36 +960,51 @@ - # - # MMC/SD Card support - # --# CONFIG_MMC is not set -+CONFIG_MMC=y -+# CONFIG_MMC_DEBUG is not set -+CONFIG_MMC_BLOCK=y -+CONFIG_MMC_AT91=y -+ -+# -+# Real Time Clock -+# -+CONFIG_RTC_LIB=y -+# CONFIG_RTC_CLASS is not set - - # - # File systems - # - CONFIG_EXT2_FS=y - CONFIG_EXT2_FS_XATTR=y --# CONFIG_EXT2_FS_POSIX_ACL is not set --# CONFIG_EXT2_FS_SECURITY is not set -+CONFIG_EXT2_FS_POSIX_ACL=y -+CONFIG_EXT2_FS_SECURITY=y - # CONFIG_EXT2_FS_XIP is not set - CONFIG_EXT3_FS=y - CONFIG_EXT3_FS_XATTR=y --# CONFIG_EXT3_FS_POSIX_ACL is not set --# CONFIG_EXT3_FS_SECURITY is not set -+CONFIG_EXT3_FS_POSIX_ACL=y -+CONFIG_EXT3_FS_SECURITY=y -+# CONFIG_EXT4DEV_FS is not set - CONFIG_JBD=y - # CONFIG_JBD_DEBUG is not set - CONFIG_FS_MBCACHE=y - # CONFIG_REISERFS_FS is not set - # CONFIG_JFS_FS is not set -- --# --# XFS support --# -+CONFIG_FS_POSIX_ACL=y - # CONFIG_XFS_FS is not set -+# CONFIG_GFS2_FS is not set -+# CONFIG_OCFS2_FS is not set - # CONFIG_MINIX_FS is not set - # CONFIG_ROMFS_FS is not set --# CONFIG_QUOTA is not set -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+CONFIG_QUOTA=y -+# CONFIG_QFMT_V1 is not set -+CONFIG_QFMT_V2=y -+CONFIG_QUOTACTL=y - CONFIG_DNOTIFY=y --CONFIG_AUTOFS_FS=y -+# CONFIG_AUTOFS_FS is not set - CONFIG_AUTOFS4_FS=y -+# CONFIG_FUSE_FS is not set - - # - # CD-ROM/DVD Filesystems -@@ -643,25 +1019,40 @@ - CONFIG_MSDOS_FS=y - CONFIG_VFAT_FS=y - CONFIG_FAT_DEFAULT_CODEPAGE=437 --CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" - # CONFIG_NTFS_FS is not set - - # - # Pseudo filesystems - # - CONFIG_PROC_FS=y -+CONFIG_PROC_SYSCTL=y - CONFIG_SYSFS=y --CONFIG_DEVPTS_FS_XATTR=y --# CONFIG_DEVPTS_FS_SECURITY is not set - CONFIG_TMPFS=y --# CONFIG_TMPFS_XATTR is not set -+# CONFIG_TMPFS_POSIX_ACL is not set - # CONFIG_HUGETLB_PAGE is not set - CONFIG_RAMFS=y -+CONFIG_CONFIGFS_FS=y - - # - # Miscellaneous filesystems - # -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_HFS_FS is not set - # CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+# CONFIG_JFFS2_SUMMARY is not set -+# CONFIG_JFFS2_FS_XATTR is not set -+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_ZLIB=y -+CONFIG_JFFS2_RTIME=y -+# CONFIG_JFFS2_RUBIN is not set - # CONFIG_CRAMFS is not set - # CONFIG_VXFS_FS is not set - # CONFIG_HPFS_FS is not set -@@ -675,16 +1066,23 @@ - CONFIG_NFS_FS=y - CONFIG_NFS_V3=y - # CONFIG_NFS_V3_ACL is not set -+CONFIG_NFS_V4=y -+# CONFIG_NFS_DIRECTIO is not set - # CONFIG_NFSD is not set - CONFIG_ROOT_NFS=y - CONFIG_LOCKD=y - CONFIG_LOCKD_V4=y - CONFIG_NFS_COMMON=y - CONFIG_SUNRPC=y -+CONFIG_SUNRPC_GSS=y -+CONFIG_RPCSEC_GSS_KRB5=y -+# CONFIG_RPCSEC_GSS_SPKM3 is not set - # CONFIG_SMB_FS is not set - # CONFIG_CIFS is not set - # CONFIG_NCP_FS is not set - # CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+# CONFIG_9P_FS is not set - - # - # Partition Types -@@ -734,26 +1132,51 @@ - # CONFIG_NLS_ISO8859_15 is not set - # CONFIG_NLS_KOI8_R is not set - # CONFIG_NLS_KOI8_U is not set --# CONFIG_NLS_UTF8 is not set -+CONFIG_NLS_UTF8=y -+ -+# -+# Distributed Lock Manager -+# -+# CONFIG_DLM is not set -+ -+# -+# Profiling support -+# -+# CONFIG_PROFILING is not set - - # - # Kernel hacking - # - # CONFIG_PRINTK_TIME is not set -+CONFIG_ENABLE_MUST_CHECK=y -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_DEBUG_FS is not set -+# CONFIG_HEADERS_CHECK is not set - CONFIG_DEBUG_KERNEL=y --# CONFIG_MAGIC_SYSRQ is not set --CONFIG_LOG_BUF_SHIFT=14 -+# CONFIG_DEBUG_SHIRQ is not set -+CONFIG_LOG_BUF_SHIFT=17 -+CONFIG_DETECT_SOFTLOCKUP=y - # CONFIG_SCHEDSTATS is not set -+# CONFIG_TIMER_STATS is not set - # CONFIG_DEBUG_SLAB is not set --# CONFIG_DEBUG_SPINLOCK is not set --# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+CONFIG_DEBUG_SPINLOCK=y -+# CONFIG_DEBUG_MUTEXES is not set -+CONFIG_DEBUG_SPINLOCK_SLEEP=y -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set - # CONFIG_DEBUG_KOBJECT is not set - CONFIG_DEBUG_BUGVERBOSE=y - # CONFIG_DEBUG_INFO is not set --# CONFIG_DEBUG_FS is not set -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_LIST is not set - CONFIG_FRAME_POINTER=y --CONFIG_DEBUG_USER=y --CONFIG_DEBUG_ERRORS=y -+CONFIG_FORCED_INLINING=y -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_FAULT_INJECTION is not set -+# CONFIG_DEBUG_USER is not set -+# CONFIG_DEBUG_ERRORS is not set - CONFIG_DEBUG_LL=y - # CONFIG_DEBUG_ICEDCC is not set - -@@ -766,7 +1189,43 @@ - # - # Cryptographic options - # --# CONFIG_CRYPTO is not set -+CONFIG_CRYPTO=y -+CONFIG_CRYPTO_ALGAPI=y -+CONFIG_CRYPTO_BLKCIPHER=y -+CONFIG_CRYPTO_HASH=m -+CONFIG_CRYPTO_MANAGER=y -+CONFIG_CRYPTO_HMAC=m -+# CONFIG_CRYPTO_XCBC is not set -+# CONFIG_CRYPTO_NULL is not set -+# CONFIG_CRYPTO_MD4 is not set -+CONFIG_CRYPTO_MD5=y -+# CONFIG_CRYPTO_SHA1 is not set -+# CONFIG_CRYPTO_SHA256 is not set -+# CONFIG_CRYPTO_SHA512 is not set -+# CONFIG_CRYPTO_WP512 is not set -+# CONFIG_CRYPTO_TGR192 is not set -+# CONFIG_CRYPTO_GF128MUL is not set -+# CONFIG_CRYPTO_ECB is not set -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_PCBC=m -+# CONFIG_CRYPTO_LRW is not set -+CONFIG_CRYPTO_DES=y -+# CONFIG_CRYPTO_FCRYPT is not set -+# CONFIG_CRYPTO_BLOWFISH is not set -+# CONFIG_CRYPTO_TWOFISH is not set -+# CONFIG_CRYPTO_SERPENT is not set -+# CONFIG_CRYPTO_AES is not set -+# CONFIG_CRYPTO_CAST5 is not set -+# CONFIG_CRYPTO_CAST6 is not set -+# CONFIG_CRYPTO_TEA is not set -+# CONFIG_CRYPTO_ARC4 is not set -+# CONFIG_CRYPTO_KHAZAD is not set -+# CONFIG_CRYPTO_ANUBIS is not set -+# CONFIG_CRYPTO_DEFLATE is not set -+# CONFIG_CRYPTO_MICHAEL_MIC is not set -+# CONFIG_CRYPTO_CRC32C is not set -+# CONFIG_CRYPTO_CAMELLIA is not set -+# CONFIG_CRYPTO_TEST is not set - - # - # Hardware crypto devices -@@ -775,6 +1234,14 @@ - # - # Library routines - # -+CONFIG_BITREVERSE=y - # CONFIG_CRC_CCITT is not set -+# CONFIG_CRC16 is not set - CONFIG_CRC32=y - # CONFIG_LIBCRC32C is not set -+CONFIG_AUDIT_GENERIC=y -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_PLIST=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91rm9200.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91rm9200.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91rm9200.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91rm9200.c 2007-07-29 05:23:04.000000000 +0200 -@@ -267,6 +267,33 @@ - - - /* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91rm9200_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91RM9200_BASE_TCB0, -+ .irq = { AT91RM9200_ID_TC0, AT91RM9200_ID_TC1, AT91RM9200_ID_TC2 }, -+ .clk = { &tc0_clk, &tc1_clk, &tc2_clk }, -+ }, -+ [1] = { -+ .physaddr = AT91RM9200_BASE_TCB1, -+ .irq = { AT91RM9200_ID_TC3, AT91RM9200_ID_TC4, AT91RM9200_ID_TC5 }, -+ .clk = { &tc3_clk, &tc4_clk, &tc5_clk }, -+ }, -+}; -+ -+#define at91rm9200_tc_init() atmel_tc_init(at91rm9200_tcblocks, ARRAY_SIZE(at91rm9200_tcblocks)) -+ -+#else -+#define at91rm9200_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * AT91RM9200 processor initialization - * -------------------------------------------------------------------- */ - void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks) -@@ -288,6 +315,9 @@ - - /* Initialize GPIO subsystem */ - at91_gpio_init(at91rm9200_gpio, banks); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91rm9200_tc_init(); - } - - -@@ -301,28 +331,28 @@ - static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller (FIQ) */ - 7, /* System Peripherals */ -- 0, /* Parallel IO Controller A */ -- 0, /* Parallel IO Controller B */ -- 0, /* Parallel IO Controller C */ -- 0, /* Parallel IO Controller D */ -- 6, /* USART 0 */ -- 6, /* USART 1 */ -- 6, /* USART 2 */ -- 6, /* USART 3 */ -+ 1, /* Parallel IO Controller A */ -+ 1, /* Parallel IO Controller B */ -+ 1, /* Parallel IO Controller C */ -+ 1, /* Parallel IO Controller D */ -+ 5, /* USART 0 */ -+ 5, /* USART 1 */ -+ 5, /* USART 2 */ -+ 5, /* USART 3 */ - 0, /* Multimedia Card Interface */ -- 4, /* USB Device Port */ -- 0, /* Two-Wire Interface */ -- 6, /* Serial Peripheral Interface */ -- 5, /* Serial Synchronous Controller 0 */ -- 5, /* Serial Synchronous Controller 1 */ -- 5, /* Serial Synchronous Controller 2 */ -+ 2, /* USB Device Port */ -+ 6, /* Two-Wire Interface */ -+ 5, /* Serial Peripheral Interface */ -+ 4, /* Serial Synchronous Controller 0 */ -+ 4, /* Serial Synchronous Controller 1 */ -+ 4, /* Serial Synchronous Controller 2 */ - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ - 0, /* Timer Counter 3 */ - 0, /* Timer Counter 4 */ - 0, /* Timer Counter 5 */ -- 3, /* USB Host port */ -+ 2, /* USB Host port */ - 3, /* Ethernet MAC */ - 0, /* Advanced Interrupt Controller (IRQ0) */ - 0, /* Advanced Interrupt Controller (IRQ1) */ -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91rm9200_devices.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91rm9200_devices.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91rm9200_devices.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91rm9200_devices.c 2007-07-29 05:23:04.000000000 +0200 -@@ -477,7 +477,18 @@ - * SPI - * -------------------------------------------------------------------- */ - --#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) -+#if defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) /* legacy SPI driver */ -+#define SPI_DEVNAME "at91_spi" -+ -+#elif defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) /* SPI bitbanging driver */ -+#define SPI_DEVNAME "at91_spi" -+ -+#elif defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) /* new SPI driver */ -+#define SPI_DEVNAME "atmel_spi" -+ -+#endif -+ -+#ifdef SPI_DEVNAME - static u64 spi_dmamask = 0xffffffffUL; - - static struct resource spi_resources[] = { -@@ -494,7 +505,7 @@ - }; - - static struct platform_device at91rm9200_spi_device = { -- .name = "at91_spi", -+ .name = SPI_DEVNAME, - .id = 0, - .dev = { - .dma_mask = &spi_dmamask, -@@ -603,6 +614,32 @@ - #endif - - -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ - /* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9260.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9260.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9260.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9260.c 2007-07-29 05:23:04.000000000 +0200 -@@ -269,6 +269,33 @@ - - - /* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91sam9260_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91SAM9260_BASE_TCB0, -+ .irq = { AT91SAM9260_ID_TC0, AT91SAM9260_ID_TC1, AT91SAM9260_ID_TC2 }, -+ .clk = { &tc0_clk, &tc1_clk, &tc2_clk }, -+ }, -+ [1] = { -+ .physaddr = AT91SAM9260_BASE_TCB1, -+ .irq = { AT91SAM9260_ID_TC3, AT91SAM9260_ID_TC4, AT91SAM9260_ID_TC5 }, -+ .clk = { &tc3_clk, &tc4_clk, &tc5_clk }, -+ }, -+}; -+ -+#define at91sam9260_tc_init() atmel_tc_init(at91sam9260_tcblocks, ARRAY_SIZE(at91sam9260_tcblocks)) -+ -+#else -+#define at91sam9260_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * AT91SAM9260 processor initialization - * -------------------------------------------------------------------- */ - -@@ -315,6 +342,9 @@ - - /* Register GPIO subsystem */ - at91_gpio_init(at91sam9260_gpio, 3); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91sam9260_tc_init(); - } - - /* -------------------------------------------------------------------- -@@ -327,30 +357,30 @@ - static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller */ - 7, /* System Peripherals */ -- 0, /* Parallel IO Controller A */ -- 0, /* Parallel IO Controller B */ -- 0, /* Parallel IO Controller C */ -+ 1, /* Parallel IO Controller A */ -+ 1, /* Parallel IO Controller B */ -+ 1, /* Parallel IO Controller C */ - 0, /* Analog-to-Digital Converter */ -- 6, /* USART 0 */ -- 6, /* USART 1 */ -- 6, /* USART 2 */ -+ 5, /* USART 0 */ -+ 5, /* USART 1 */ -+ 5, /* USART 2 */ - 0, /* Multimedia Card Interface */ -- 4, /* USB Device Port */ -- 0, /* Two-Wire Interface */ -- 6, /* Serial Peripheral Interface 0 */ -- 6, /* Serial Peripheral Interface 1 */ -+ 2, /* USB Device Port */ -+ 6, /* Two-Wire Interface */ -+ 5, /* Serial Peripheral Interface 0 */ -+ 5, /* Serial Peripheral Interface 1 */ - 5, /* Serial Synchronous Controller */ - 0, - 0, - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ -- 3, /* USB Host port */ -+ 2, /* USB Host port */ - 3, /* Ethernet */ - 0, /* Image Sensor Interface */ -- 6, /* USART 3 */ -- 6, /* USART 4 */ -- 6, /* USART 5 */ -+ 5, /* USART 3 */ -+ 5, /* USART 4 */ -+ 5, /* USART 5 */ - 0, /* Timer Counter 3 */ - 0, /* Timer Counter 4 */ - 0, /* Timer Counter 5 */ -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9260_devices.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9260_devices.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9260_devices.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9260_devices.c 2007-07-29 05:23:04.000000000 +0200 -@@ -524,6 +524,32 @@ - #endif - - -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ - /* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9261.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9261.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9261.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9261.c 2007-07-29 05:23:04.000000000 +0200 -@@ -247,6 +247,28 @@ - - - /* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91sam9261_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91SAM9261_BASE_TCB0, -+ .irq = { AT91SAM9261_ID_TC0, AT91SAM9261_ID_TC1, AT91SAM9261_ID_TC2 }, -+ .clk = { &tc0_clk, &tc1_clk, &tc2_clk }, -+ } -+}; -+ -+#define at91sam9261_tc_init() atmel_tc_init(at91sam9261_tcblocks, ARRAY_SIZE(at91sam9261_tcblocks)) -+ -+#else -+#define at91sam9261_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * AT91SAM9261 processor initialization - * -------------------------------------------------------------------- */ - -@@ -267,6 +289,9 @@ - - /* Register GPIO subsystem */ - at91_gpio_init(at91sam9261_gpio, 3); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91sam9261_tc_init(); - } - - /* -------------------------------------------------------------------- -@@ -279,25 +304,25 @@ - static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller */ - 7, /* System Peripherals */ -- 0, /* Parallel IO Controller A */ -- 0, /* Parallel IO Controller B */ -- 0, /* Parallel IO Controller C */ -- 0, -- 6, /* USART 0 */ -- 6, /* USART 1 */ -- 6, /* USART 2 */ -+ 1, /* Parallel IO Controller A */ -+ 1, /* Parallel IO Controller B */ -+ 1, /* Parallel IO Controller C */ -+ 0, -+ 5, /* USART 0 */ -+ 5, /* USART 1 */ -+ 5, /* USART 2 */ - 0, /* Multimedia Card Interface */ -- 4, /* USB Device Port */ -- 0, /* Two-Wire Interface */ -- 6, /* Serial Peripheral Interface 0 */ -- 6, /* Serial Peripheral Interface 1 */ -- 5, /* Serial Synchronous Controller 0 */ -- 5, /* Serial Synchronous Controller 1 */ -- 5, /* Serial Synchronous Controller 2 */ -+ 2, /* USB Device Port */ -+ 6, /* Two-Wire Interface */ -+ 5, /* Serial Peripheral Interface 0 */ -+ 5, /* Serial Peripheral Interface 1 */ -+ 4, /* Serial Synchronous Controller 0 */ -+ 4, /* Serial Synchronous Controller 1 */ -+ 4, /* Serial Synchronous Controller 2 */ - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ -- 3, /* USB Host port */ -+ 2, /* USB Host port */ - 3, /* LCD Controller */ - 0, - 0, -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9261_devices.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9261_devices.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9261_devices.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9261_devices.c 2007-07-29 05:23:04.000000000 +0200 -@@ -14,6 +14,9 @@ - #include <asm/mach/map.h> - - #include <linux/platform_device.h> -+#include <linux/fb.h> -+ -+#include <video/atmel_lcdc.h> - - #include <asm/arch/board.h> - #include <asm/arch/gpio.h> -@@ -522,6 +525,32 @@ - #endif - - -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ - /* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9263.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9263.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9263.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9263.c 2007-07-29 05:23:04.000000000 +0200 -@@ -273,6 +273,28 @@ - - - /* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91sam9263_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91SAM9263_BASE_TCB0, -+ .irq = { AT91SAM9263_ID_TCB, AT91SAM9263_ID_TCB, AT91SAM9263_ID_TCB }, -+ .clk = { &tcb_clk, &tcb_clk, &tcb_clk }, -+ } -+}; -+ -+#define at91sam9263_tc_init() atmel_tc_init(at91sam9263_tcblocks, ARRAY_SIZE(at91sam9263_tcblocks)) -+ -+#else -+#define at91sam9263_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * AT91SAM9263 processor initialization - * -------------------------------------------------------------------- */ - -@@ -292,6 +314,9 @@ - - /* Register GPIO subsystem */ - at91_gpio_init(at91sam9263_gpio, 5); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91sam9263_tc_init(); - } - - /* -------------------------------------------------------------------- -@@ -304,34 +329,34 @@ - static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller (FIQ) */ - 7, /* System Peripherals */ -- 0, /* Parallel IO Controller A */ -- 0, /* Parallel IO Controller B */ -- 0, /* Parallel IO Controller C, D and E */ -+ 1, /* Parallel IO Controller A */ -+ 1, /* Parallel IO Controller B */ -+ 1, /* Parallel IO Controller C, D and E */ - 0, - 0, -- 6, /* USART 0 */ -- 6, /* USART 1 */ -- 6, /* USART 2 */ -+ 5, /* USART 0 */ -+ 5, /* USART 1 */ -+ 5, /* USART 2 */ - 0, /* Multimedia Card Interface 0 */ - 0, /* Multimedia Card Interface 1 */ -- 4, /* CAN */ -- 0, /* Two-Wire Interface */ -- 6, /* Serial Peripheral Interface 0 */ -- 6, /* Serial Peripheral Interface 1 */ -- 5, /* Serial Synchronous Controller 0 */ -- 5, /* Serial Synchronous Controller 1 */ -- 6, /* AC97 Controller */ -+ 3, /* CAN */ -+ 6, /* Two-Wire Interface */ -+ 5, /* Serial Peripheral Interface 0 */ -+ 5, /* Serial Peripheral Interface 1 */ -+ 4, /* Serial Synchronous Controller 0 */ -+ 4, /* Serial Synchronous Controller 1 */ -+ 5, /* AC97 Controller */ - 0, /* Timer Counter 0, 1 and 2 */ - 0, /* Pulse Width Modulation Controller */ - 3, /* Ethernet */ - 0, - 0, /* 2D Graphic Engine */ -- 3, /* USB Device Port */ -+ 2, /* USB Device Port */ - 0, /* Image Sensor Interface */ - 3, /* LDC Controller */ - 0, /* DMA Controller */ - 0, -- 3, /* USB Host port */ -+ 2, /* USB Host port */ - 0, /* Advanced Interrupt Controller (IRQ0) */ - 0, /* Advanced Interrupt Controller (IRQ1) */ - }; -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9263_devices.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9263_devices.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9263_devices.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9263_devices.c 2007-07-29 05:23:04.000000000 +0200 -@@ -13,6 +13,9 @@ - #include <asm/mach/map.h> - - #include <linux/platform_device.h> -+#include <linux/fb.h> -+ -+#include <video/atmel_lcdc.h> - - #include <asm/arch/board.h> - #include <asm/arch/gpio.h> -@@ -625,6 +628,56 @@ - - - /* -------------------------------------------------------------------- -+ * Image Sensor Interface -+ * -------------------------------------------------------------------- */ -+ -+#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE) -+ -+struct resource isi_resources[] = { -+ [0] = { -+ .start = AT91SAM9263_BASE_ISI, -+ .end = AT91SAM9263_BASE_ISI + SZ_16K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AT91SAM9263_ID_ISI, -+ .end = AT91SAM9263_ID_ISI, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device at91sam9263_isi_device = { -+ .name = "at91_isi", -+ .id = -1, -+ .resource = isi_resources, -+ .num_resources = ARRAY_SIZE(isi_resources), -+}; -+ -+void __init at91_add_device_isi(void) -+{ -+ at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */ -+ at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */ -+ at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */ -+ at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */ -+ at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */ -+ at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */ -+ at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */ -+ at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */ -+ at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */ -+ at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */ -+ at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */ -+ at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */ -+ at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */ -+ at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */ -+ at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */ -+ at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */ -+} -+#else -+void __init at91_add_device_isi(void) {} -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * LCD Controller - * -------------------------------------------------------------------- */ - -@@ -715,6 +768,32 @@ - #endif - - -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ - /* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9rl.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9rl.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9rl.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9rl.c 2007-07-29 05:23:04.000000000 +0200 -@@ -246,6 +246,28 @@ - - - /* -------------------------------------------------------------------- -+ * Timer/Counter library initialization -+ * -------------------------------------------------------------------- */ -+#ifdef CONFIG_ATMEL_TCLIB -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock at91sam9rl_tcblocks[] = { -+ [0] = { -+ .physaddr = AT91SAM9RL_BASE_TCB0, -+ .irq = { AT91SAM9RL_ID_TC0, AT91SAM9RL_ID_TC1, AT91SAM9RL_ID_TC2 }, -+ .clk = { &tc0_clk, &tc1_clk, &tc2_clk }, -+ } -+}; -+ -+#define at91sam9rl_tc_init() atmel_tc_init(at91sam9rl_tcblocks, ARRAY_SIZE(at91sam9rl_tcblocks)) -+ -+#else -+#define at91sam9rl_tc_init() do {} while(0) -+#endif -+ -+ -+/* -------------------------------------------------------------------- - * AT91SAM9RL processor initialization - * -------------------------------------------------------------------- */ - -@@ -284,6 +306,9 @@ - - /* Register GPIO subsystem */ - at91_gpio_init(at91sam9rl_gpio, 4); -+ -+ /* Initialize the Timer/Counter blocks */ -+ at91sam9rl_tc_init(); - } - - /* -------------------------------------------------------------------- -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9rl_devices.c linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9rl_devices.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/at91sam9rl_devices.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/at91sam9rl_devices.c 2007-07-29 05:23:04.000000000 +0200 -@@ -370,6 +370,32 @@ - #endif - - -+#if defined(CONFIG_NEW_LEDS) -+ -+static struct platform_device at91_leds = { -+ .name = "at91_leds", -+ .id = -1, -+}; -+ -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) -+{ -+ if (!nr) -+ return; -+ -+ at91_leds.dev.platform_data = leds; -+ -+ for ( ; nr; nr--, leds++) { -+ leds->index = nr; /* first record stores number of leds */ -+ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0); -+ } -+ -+ platform_device_register(&at91_leds); -+} -+#else -+void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {} -+#endif -+ -+ - /* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/board-cam60.c linux-2.6.22-rc5.new/arch/arm/mach-at91/board-cam60.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/board-cam60.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/board-cam60.c 2007-07-29 05:23:04.000000000 +0200 -@@ -0,0 +1,148 @@ -+/* -+ * KwikByte CAM60 -+ * -+ * based on board-sam9260ek.c -+ * Copyright (C) 2005 SAN People -+ * Copyright (C) 2006 Atmel -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/types.h> -+#include <linux/init.h> -+#include <linux/mm.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+#include <linux/spi/spi.h> -+#include <linux/spi/flash.h> -+ -+#include <asm/hardware.h> -+#include <asm/setup.h> -+#include <asm/mach-types.h> -+#include <asm/irq.h> -+ -+#include <asm/mach/arch.h> -+#include <asm/mach/map.h> -+#include <asm/mach/irq.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+#include <asm/arch/at91sam926x_mc.h> -+ -+#include "generic.h" -+ -+ -+/* -+ * Serial port configuration. -+ * 0 .. 5 = USART0 .. USART5 -+ * 6 = DBGU -+ */ -+static struct at91_uart_config __initdata cam60_uart_config = { -+ .console_tty = 0, /* ttyS0 */ -+ .nr_tty = 1, -+ .tty_map = { 6, -1, -1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */ -+}; -+ -+static void __init cam60_map_io(void) -+{ -+ /* Initialize processor: 10 MHz crystal */ -+ at91sam9260_initialize(10000000); -+ -+ /* Setup the serial ports and console */ -+ at91_init_serial(&cam60_uart_config); -+} -+ -+static void __init cam60_init_irq(void) -+{ -+ at91sam9260_init_interrupts(NULL); -+} -+ -+ -+/* -+ * SPI devices. -+ */ -+#if defined(CONFIG_MTD_DATAFLASH) -+static struct mtd_partition __initdata cam60_spi_partitions[] = { -+ { -+ .name = "BOOT1", -+ .offset = 0, -+ .size = 4 * 1056, -+ }, -+ { -+ .name = "BOOT2", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 256 * 1056, -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 2222 * 1056, -+ }, -+ { -+ .name = "file system", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static struct flash_platform_data __initdata cam60_spi_flash_platform_data = { -+ .name = "spi_flash", -+ .parts = cam60_spi_partitions, -+ .nr_parts = ARRAY_SIZE(cam60_spi_partitions) -+}; -+#endif -+ -+static struct spi_board_info cam60_spi_devices[] = { -+#if defined(CONFIG_MTD_DATAFLASH) -+ { /* DataFlash chip */ -+ .modalias = "mtd_dataflash", -+ .chip_select = 0, -+ .max_speed_hz = 15 * 1000 * 1000, -+ .bus_num = 0, -+ .platform_data = &cam60_spi_flash_platform_data -+ }, -+#endif -+}; -+ -+ -+/* -+ * MACB Ethernet device -+ */ -+static struct __initdata at91_eth_data cam60_macb_data = { -+ .phy_irq_pin = AT91_PIN_PB5, -+ .is_rmii = 0, -+}; -+ -+ -+static void __init cam60_board_init(void) -+{ -+ /* Serial */ -+ at91_add_device_serial(); -+ /* SPI */ -+ at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices)); -+ /* Ethernet */ -+ at91_add_device_eth(&cam60_macb_data); -+} -+ -+MACHINE_START(CAM60, "KwikByte CAM60") -+ /* Maintainer: KwikByte */ -+ .phys_io = AT91_BASE_SYS, -+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, -+ .boot_params = AT91_SDRAM_BASE + 0x100, -+ .timer = &at91sam926x_timer, -+ .map_io = cam60_map_io, -+ .init_irq = cam60_init_irq, -+ .init_machine = cam60_board_init, -+MACHINE_END -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/board-chub.c linux-2.6.22-rc5.new/arch/arm/mach-at91/board-chub.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/board-chub.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/board-chub.c 2007-07-29 05:23:04.000000000 +0200 -@@ -0,0 +1,132 @@ -+/* -+ * linux/arch/arm/mach-at91/board-chub.c -+ * -+ * Copyright (C) 2005 SAN People, adapted for Promwad Chub board -+ * by Kuten Ivan -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/types.h> -+#include <linux/init.h> -+#include <linux/mm.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+ -+#include <asm/hardware.h> -+#include <asm/setup.h> -+#include <asm/mach-types.h> -+#include <asm/irq.h> -+ -+#include <asm/mach/arch.h> -+#include <asm/mach/map.h> -+#include <asm/mach/irq.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+ -+#include "generic.h" -+ -+/* -+ * Serial port configuration. -+ * 0 .. 3 = USART0 .. USART3 -+ * 4 = DBGU -+ */ -+static struct at91_uart_config __initdata chub_uart_config = { -+ .console_tty = 0, /* ttyS0 */ -+ .nr_tty = 5, -+ .tty_map = { 4, 0, 1, 2, 3 } /* ttyS0, ..., ttyS4 */ -+}; -+ -+static void __init chub_init_irq(void) -+{ -+ at91rm9200_init_interrupts(NULL); -+} -+ -+static void __init chub_map_io(void) -+{ -+ /* Initialize clocks: 18.432 MHz crystal */ -+ at91rm9200_initialize(18432000, AT91RM9200_PQFP); -+ -+ /* Setup the serial ports and console */ -+ at91_init_serial(&chub_uart_config); -+} -+ -+static struct at91_eth_data __initdata chub_eth_data = { -+ .phy_irq_pin = AT91_PIN_PB29, -+ .is_rmii = 0, -+}; -+ -+static struct mtd_partition __initdata chub_nand_partition[] = { -+ { -+ .name = "NAND Partition 1", -+ .offset = 0, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) -+{ -+ *num_partitions = ARRAY_SIZE(chub_nand_partition); -+ return chub_nand_partition; -+} -+ -+static struct at91_nand_data __initdata chub_nand_data = { -+ .ale = 22, -+ .cle = 21, -+ .enable_pin = AT91_PIN_PA27, -+ .partition_info = nand_partitions, -+}; -+ -+static struct spi_board_info chub_spi_devices[] = { -+ { /* DataFlash chip */ -+ .modalias = "mtd_dataflash", -+ .chip_select = 0, -+ .max_speed_hz = 15 * 1000 * 1000, -+ }, -+}; -+ -+static void __init chub_board_init(void) -+{ -+ /* Serial */ -+ at91_add_device_serial(); -+ /* I2C */ -+ at91_add_device_i2c(); -+ /* Ethernet */ -+ at91_add_device_eth(&chub_eth_data); -+ /* SPI */ -+ at91_add_device_spi(chub_spi_devices, ARRAY_SIZE(chub_spi_devices)); -+ /* NAND Flash */ -+ at91_add_device_nand(&chub_nand_data); -+ /* Disable write protect for NAND */ -+ at91_set_gpio_output(AT91_PIN_PB7, 1); -+ /* Power enable for 3x RS-232 and 1x RS-485 */ -+ at91_set_gpio_output(AT91_PIN_PB9, 1); -+ /* Disable write protect for FRAM */ -+ at91_set_gpio_output(AT91_PIN_PA21, 1); -+ /* Disable write protect for Dataflash */ -+ at91_set_gpio_output(AT91_PIN_PA19, 1); -+} -+ -+MACHINE_START(CHUB, "Promwad Chub") -+ /* Maintainer: Ivan Kuten AT Promwad DOT com */ -+ .phys_io = AT91_BASE_SYS, -+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, -+ .boot_params = AT91_SDRAM_BASE + 0x100, -+ .timer = &at91rm9200_timer, -+ .map_io = chub_map_io, -+ .init_irq = chub_init_irq, -+ .init_machine = chub_board_init, -+MACHINE_END -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/board-csb337.c linux-2.6.22-rc5.new/arch/arm/mach-at91/board-csb337.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/board-csb337.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/board-csb337.c 2007-07-29 05:23:04.000000000 +0200 -@@ -24,6 +24,7 @@ - #include <linux/module.h> - #include <linux/platform_device.h> - #include <linux/spi/spi.h> -+#include <linux/interrupt.h> - #include <linux/mtd/physmap.h> - - #include <asm/hardware.h> -@@ -59,6 +60,7 @@ - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); -+ at91_set_gpio_output(AT91_PIN_PB2, 1); /* third (unused) LED */ - - /* Setup the serial ports and console */ - at91_init_serial(&csb337_uart_config); -@@ -149,6 +151,55 @@ - .num_resources = ARRAY_SIZE(csb_flash_resources), - }; - -+static struct at91_gpio_led csb337_leds[] = { -+ { -+ .name = "led0", -+ .gpio = AT91_PIN_PB0, -+ .trigger = "heartbeat", -+ }, -+ { -+ .name = "led1", -+ .gpio = AT91_PIN_PB1, -+ .trigger = "timer", -+ }, -+ { -+ .name = "led2", -+ .gpio = AT91_PIN_PB2, -+ } -+}; -+ -+#if defined(CONFIG_CSB300_WAKE_SW0) || defined(CONFIG_CSB300_WAKE_SW1) -+static irqreturn_t switch_irq_handler(int irq, void *context) -+{ -+ return IRQ_HANDLED; -+} -+ -+static inline void __init switch_irq_setup(int irq, char *name, unsigned long mode) -+{ -+ int res; -+ -+ res = request_irq(irq, switch_irq_handler, IRQF_SAMPLE_RANDOM | mode, name, NULL); -+ if (res == 0) -+ enable_irq_wake(irq); -+} -+ -+static void __init csb300_switches(void) -+{ -+#ifdef CONFIG_CSB300_WAKE_SW0 -+ at91_set_A_periph(AT91_PIN_PB29, 1); /* IRQ0 */ -+ switch_irq_setup(AT91RM9200_ID_IRQ0, "csb300_sw0", IRQF_TRIGGER_FALLING); -+#endif -+#ifdef CONFIG_CSB300_WAKE_SW1 -+ at91_set_gpio_input(AT91_PIN_PB28, 1); -+ at91_set_deglitch(AT91_PIN_PB28, 1); -+ switch_irq_setup(AT91_PIN_PB28, "csb300_sw1", IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING); -+#endif -+ /* there's also SW2 at PA21, GPIO or TIOA2 */ -+} -+#else -+static void __init csb300_switches(void) {} -+#endif -+ - static void __init csb337_board_init(void) - { - /* Serial */ -@@ -168,8 +219,12 @@ - at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices)); - /* MMC */ - at91_add_device_mmc(0, &csb337_mmc_data); -+ /* LEDS */ -+ at91_gpio_leds(csb337_leds, ARRAY_SIZE(csb337_leds)); - /* NOR flash */ - platform_device_register(&csb_flash); -+ /* Switches on CSB300 */ -+ csb300_switches(); - } - - MACHINE_START(CSB337, "Cogent CSB337") -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/board-dk.c linux-2.6.22-rc5.new/arch/arm/mach-at91/board-dk.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/board-dk.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/board-dk.c 2007-07-29 05:23:04.000000000 +0200 -@@ -73,6 +73,185 @@ - at91rm9200_init_interrupts(NULL); - } - -+#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE) -+#include <video/s1d13xxxfb.h> -+#include <asm/arch/ics1523.h> -+ -+/* EPSON S1D13806 FB */ -+#define AT91_FB_REG_BASE 0x30000000L -+#define AT91_FB_REG_SIZE 0x200 -+#define AT91_FB_VMEM_BASE 0x30200000L -+#define AT91_FB_VMEM_SIZE 0x140000L -+ -+static void __init dk_init_video(void) -+{ -+ /* NWAIT Signal */ -+ at91_set_A_periph(AT91_PIN_PC6, 0); -+ -+ /* Initialization of the Static Memory Controller for Chip Select 2 */ -+ at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */ -+ | AT91_SMC_WSEN | AT91_SMC_NWS_(4) /* wait states */ -+ | AT91_SMC_TDF_(1) /* float time */ -+ ); -+ -+ at91_ics1523_init(); -+} -+ -+/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz) -+ Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */ -+static const struct s1d13xxxfb_regval dk_s1dfb_initregs[] = { -+ {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */ -+ {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */ -+ {S1DREG_GPIO_CNF0, 0x00}, -+ {S1DREG_GPIO_CNF1, 0x00}, -+ {S1DREG_GPIO_CTL0, 0x08}, -+ {S1DREG_GPIO_CTL1, 0x00}, -+ {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/ -+ {S1DREG_LCD_CLK_CNF, 0x00}, -+ {S1DREG_CRT_CLK_CNF, 0x00}, -+ {S1DREG_MPLUG_CLK_CNF, 0x00}, -+ {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */ -+ {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */ -+ {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */ -+ {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */ -+ {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */ -+ {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */ -+ {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */ -+ {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */ -+ {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */ -+ {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */ -+ {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */ -+ {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, -+ {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */ -+ {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */ -+ {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */ -+ {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */ -+ {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */ -+ {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */ -+ {S1DREG_LCD_DISP_START0, 0x00}, -+ {S1DREG_LCD_DISP_START1, 0xC8}, -+ {S1DREG_LCD_DISP_START2, 0x00}, -+ {S1DREG_LCD_MEM_OFF0, 0x80}, -+ {S1DREG_LCD_MEM_OFF1, 0x02}, -+ {S1DREG_LCD_PIX_PAN, 0x00}, -+ {S1DREG_LCD_DISP_FIFO_HTC, 0x3B}, -+ {S1DREG_LCD_DISP_FIFO_LTC, 0x3C}, -+ {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */ -+ {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */ -+ {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */ -+ {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */ -+ {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, -+ {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */ -+ {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */ -+ {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */ -+ {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */ -+ {S1DREG_TV_OUT_CTL, 0x10}, -+ {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */ -+ {S1DREG_CRT_DISP_START0, 0x00}, -+ {S1DREG_CRT_DISP_START1, 0x00}, -+ {S1DREG_CRT_DISP_START2, 0x00}, -+ {S1DREG_CRT_MEM_OFF0, 0x80}, -+ {S1DREG_CRT_MEM_OFF1, 0x02}, -+ {S1DREG_CRT_PIX_PAN, 0x00}, -+ {S1DREG_CRT_DISP_FIFO_HTC, 0x3B}, -+ {S1DREG_CRT_DISP_FIFO_LTC, 0x3C}, -+ {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */ -+ {S1DREG_LCD_CUR_START, 0x01}, -+ {S1DREG_LCD_CUR_XPOS0, 0x00}, -+ {S1DREG_LCD_CUR_XPOS1, 0x00}, -+ {S1DREG_LCD_CUR_YPOS0, 0x00}, -+ {S1DREG_LCD_CUR_YPOS1, 0x00}, -+ {S1DREG_LCD_CUR_BCTL0, 0x00}, -+ {S1DREG_LCD_CUR_GCTL0, 0x00}, -+ {S1DREG_LCD_CUR_RCTL0, 0x00}, -+ {S1DREG_LCD_CUR_BCTL1, 0x1F}, -+ {S1DREG_LCD_CUR_GCTL1, 0x3F}, -+ {S1DREG_LCD_CUR_RCTL1, 0x1F}, -+ {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, -+ {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */ -+ {S1DREG_CRT_CUR_START, 0x01}, -+ {S1DREG_CRT_CUR_XPOS0, 0x00}, -+ {S1DREG_CRT_CUR_XPOS1, 0x00}, -+ {S1DREG_CRT_CUR_YPOS0, 0x00}, -+ {S1DREG_CRT_CUR_YPOS1, 0x00}, -+ {S1DREG_CRT_CUR_BCTL0, 0x00}, -+ {S1DREG_CRT_CUR_GCTL0, 0x00}, -+ {S1DREG_CRT_CUR_RCTL0, 0x00}, -+ {S1DREG_CRT_CUR_BCTL1, 0x1F}, -+ {S1DREG_CRT_CUR_GCTL1, 0x3F}, -+ {S1DREG_CRT_CUR_RCTL1, 0x1F}, -+ {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, -+ {S1DREG_BBLT_CTL0, 0x00}, -+ {S1DREG_BBLT_CTL0, 0x00}, -+ {S1DREG_BBLT_CC_EXP, 0x00}, -+ {S1DREG_BBLT_OP, 0x00}, -+ {S1DREG_BBLT_SRC_START0, 0x00}, -+ {S1DREG_BBLT_SRC_START1, 0x00}, -+ {S1DREG_BBLT_SRC_START2, 0x00}, -+ {S1DREG_BBLT_DST_START0, 0x00}, -+ {S1DREG_BBLT_DST_START1, 0x00}, -+ {S1DREG_BBLT_DST_START2, 0x00}, -+ {S1DREG_BBLT_MEM_OFF0, 0x00}, -+ {S1DREG_BBLT_MEM_OFF1, 0x00}, -+ {S1DREG_BBLT_WIDTH0, 0x00}, -+ {S1DREG_BBLT_WIDTH1, 0x00}, -+ {S1DREG_BBLT_HEIGHT0, 0x00}, -+ {S1DREG_BBLT_HEIGHT1, 0x00}, -+ {S1DREG_BBLT_BGC0, 0x00}, -+ {S1DREG_BBLT_BGC1, 0x00}, -+ {S1DREG_BBLT_FGC0, 0x00}, -+ {S1DREG_BBLT_FGC1, 0x00}, -+ {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */ -+ {S1DREG_LKUP_ADDR, 0x00}, -+ {S1DREG_PS_CNF, 0x00}, /* Power Save disable */ -+ {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */ -+ {S1DREG_CPU2MEM_WDOGT, 0x00}, -+ {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */ -+}; -+ -+static struct s1d13xxxfb_pdata dk_s1dfb_pdata = { -+ .initregs = dk_s1dfb_initregs, -+ .initregssize = ARRAY_SIZE(dk_s1dfb_initregs), -+ .platform_init_video = dk_init_video, -+}; -+ -+static u64 s1dfb_dmamask = 0xffffffffUL; -+ -+static struct resource dk_s1dfb_resource[] = { -+ [0] = { /* video mem */ -+ .name = "s1d13806 memory", -+ .start = AT91_FB_VMEM_BASE, -+ .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { /* video registers */ -+ .name = "s1d13806 registers", -+ .start = AT91_FB_REG_BASE, -+ .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device dk_s1dfb_device = { -+ .name = "s1d13806fb", -+ .id = -1, -+ .dev = { -+ .dma_mask = &s1dfb_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &dk_s1dfb_pdata, -+ }, -+ .resource = dk_s1dfb_resource, -+ .num_resources = ARRAY_SIZE(dk_s1dfb_resource), -+}; -+ -+static void __init dk_add_device_video(void) -+{ -+ platform_device_register(&dk_s1dfb_device); -+} -+#else -+static void __init dk_add_device_video(void) {} -+#endif -+ - static struct at91_eth_data __initdata dk_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -@@ -151,7 +330,7 @@ - #define DK_FLASH_SIZE 0x200000 - - static struct physmap_flash_data dk_flash_data = { -- .width = 2, -+ .width = 2, - }; - - static struct resource dk_flash_resource = { -@@ -170,6 +349,13 @@ - .num_resources = 1, - }; - -+static struct at91_gpio_led dk_leds[] = { -+ { -+ .name = "led0", -+ .gpio = AT91_PIN_PB2, -+ .trigger = "timer", -+ } -+}; - - static void __init dk_board_init(void) - { -@@ -200,8 +386,10 @@ - at91_add_device_nand(&dk_nand_data); - /* NOR Flash */ - platform_device_register(&dk_flash); -+ /* LEDs */ -+ at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds)); - /* VGA */ --// dk_add_device_video(); -+ dk_add_device_video(); - } - - MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/board-ek.c linux-2.6.22-rc5.new/arch/arm/mach-at91/board-ek.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/board-ek.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/board-ek.c 2007-07-29 05:23:04.000000000 +0200 -@@ -73,6 +73,187 @@ - at91rm9200_init_interrupts(NULL); - } - -+#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE) -+#include <video/s1d13xxxfb.h> -+#include <asm/arch/ics1523.h> -+ -+/* EPSON S1D13806 FB */ -+#define AT91_FB_REG_BASE 0x40000000L -+#define AT91_FB_REG_SIZE 0x200 -+#define AT91_FB_VMEM_BASE 0x40200000L -+#define AT91_FB_VMEM_SIZE 0x140000L -+ -+static void __init ek_init_video(void) -+{ -+ /* NWAIT Signal */ -+ at91_set_A_periph(AT91_PIN_PC6, 0); -+ -+ /* Initialization of the Static Memory Controller for Chip Select 3 */ -+ at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16 /* 16 bit */ -+ | AT91_SMC_WSEN | AT91_SMC_NWS_(5) /* wait states */ -+ | AT91_SMC_TDF_(1) /* float time */ -+ ); -+ -+ at91_ics1523_init(); -+} -+ -+/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz) -+ Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */ -+static const struct s1d13xxxfb_regval ek_s1dfb_initregs[] = { -+ {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */ -+ {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */ -+ {S1DREG_GPIO_CNF0, 0xFF}, // 0x00 -+ {S1DREG_GPIO_CNF1, 0x1F}, // 0x08 -+ {S1DREG_GPIO_CTL0, 0x00}, -+ {S1DREG_GPIO_CTL1, 0x00}, -+ {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/ -+ {S1DREG_LCD_CLK_CNF, 0x00}, -+ {S1DREG_CRT_CLK_CNF, 0x00}, -+ {S1DREG_MPLUG_CLK_CNF, 0x00}, -+ {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */ -+ {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */ -+ {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */ -+ {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */ -+ {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */ -+ {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */ -+ {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */ -+ {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */ -+ {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */ -+ {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */ -+ {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */ -+ {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, -+ {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */ -+ {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */ -+ {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */ -+ {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */ -+ {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */ -+ {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */ -+ {S1DREG_LCD_DISP_START0, 0x00}, -+ {S1DREG_LCD_DISP_START1, 0xC8}, -+ {S1DREG_LCD_DISP_START2, 0x00}, -+ {S1DREG_LCD_MEM_OFF0, 0x80}, -+ {S1DREG_LCD_MEM_OFF1, 0x02}, -+ {S1DREG_LCD_PIX_PAN, 0x00}, -+ {S1DREG_LCD_DISP_FIFO_HTC, 0x3B}, -+ {S1DREG_LCD_DISP_FIFO_LTC, 0x3C}, -+ {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */ -+ {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */ -+ {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */ -+ {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */ -+ {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, -+ {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */ -+ {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */ -+ {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */ -+ {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */ -+ {S1DREG_TV_OUT_CTL, 0x10}, -+ {0x005E, 0x9F}, -+ {0x005F, 0x00}, -+ {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */ -+ {S1DREG_CRT_DISP_START0, 0x00}, -+ {S1DREG_CRT_DISP_START1, 0x00}, -+ {S1DREG_CRT_DISP_START2, 0x00}, -+ {S1DREG_CRT_MEM_OFF0, 0x80}, -+ {S1DREG_CRT_MEM_OFF1, 0x02}, -+ {S1DREG_CRT_PIX_PAN, 0x00}, -+ {S1DREG_CRT_DISP_FIFO_HTC, 0x3B}, -+ {S1DREG_CRT_DISP_FIFO_LTC, 0x3C}, -+ {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */ -+ {S1DREG_LCD_CUR_START, 0x01}, -+ {S1DREG_LCD_CUR_XPOS0, 0x00}, -+ {S1DREG_LCD_CUR_XPOS1, 0x00}, -+ {S1DREG_LCD_CUR_YPOS0, 0x00}, -+ {S1DREG_LCD_CUR_YPOS1, 0x00}, -+ {S1DREG_LCD_CUR_BCTL0, 0x00}, -+ {S1DREG_LCD_CUR_GCTL0, 0x00}, -+ {S1DREG_LCD_CUR_RCTL0, 0x00}, -+ {S1DREG_LCD_CUR_BCTL1, 0x1F}, -+ {S1DREG_LCD_CUR_GCTL1, 0x3F}, -+ {S1DREG_LCD_CUR_RCTL1, 0x1F}, -+ {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, -+ {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */ -+ {S1DREG_CRT_CUR_START, 0x01}, -+ {S1DREG_CRT_CUR_XPOS0, 0x00}, -+ {S1DREG_CRT_CUR_XPOS1, 0x00}, -+ {S1DREG_CRT_CUR_YPOS0, 0x00}, -+ {S1DREG_CRT_CUR_YPOS1, 0x00}, -+ {S1DREG_CRT_CUR_BCTL0, 0x00}, -+ {S1DREG_CRT_CUR_GCTL0, 0x00}, -+ {S1DREG_CRT_CUR_RCTL0, 0x00}, -+ {S1DREG_CRT_CUR_BCTL1, 0x1F}, -+ {S1DREG_CRT_CUR_GCTL1, 0x3F}, -+ {S1DREG_CRT_CUR_RCTL1, 0x1F}, -+ {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, -+ {S1DREG_BBLT_CTL0, 0x00}, -+ {S1DREG_BBLT_CTL0, 0x00}, -+ {S1DREG_BBLT_CC_EXP, 0x00}, -+ {S1DREG_BBLT_OP, 0x00}, -+ {S1DREG_BBLT_SRC_START0, 0x00}, -+ {S1DREG_BBLT_SRC_START1, 0x00}, -+ {S1DREG_BBLT_SRC_START2, 0x00}, -+ {S1DREG_BBLT_DST_START0, 0x00}, -+ {S1DREG_BBLT_DST_START1, 0x00}, -+ {S1DREG_BBLT_DST_START2, 0x00}, -+ {S1DREG_BBLT_MEM_OFF0, 0x00}, -+ {S1DREG_BBLT_MEM_OFF1, 0x00}, -+ {S1DREG_BBLT_WIDTH0, 0x00}, -+ {S1DREG_BBLT_WIDTH1, 0x00}, -+ {S1DREG_BBLT_HEIGHT0, 0x00}, -+ {S1DREG_BBLT_HEIGHT1, 0x00}, -+ {S1DREG_BBLT_BGC0, 0x00}, -+ {S1DREG_BBLT_BGC1, 0x00}, -+ {S1DREG_BBLT_FGC0, 0x00}, -+ {S1DREG_BBLT_FGC1, 0x00}, -+ {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */ -+ {S1DREG_LKUP_ADDR, 0x00}, -+ {S1DREG_PS_CNF, 0x10}, /* Power Save disable */ -+ {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */ -+ {S1DREG_CPU2MEM_WDOGT, 0x00}, -+ {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */ -+}; -+ -+static struct s1d13xxxfb_pdata ek_s1dfb_pdata = { -+ .initregs = ek_s1dfb_initregs, -+ .initregssize = ARRAY_SIZE(ek_s1dfb_initregs), -+ .platform_init_video = ek_init_video, -+}; -+ -+static u64 s1dfb_dmamask = 0xffffffffUL; -+ -+static struct resource ek_s1dfb_resource[] = { -+ [0] = { /* video mem */ -+ .name = "s1d13806 memory", -+ .start = AT91_FB_VMEM_BASE, -+ .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { /* video registers */ -+ .name = "s1d13806 registers", -+ .start = AT91_FB_REG_BASE, -+ .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ek_s1dfb_device = { -+ .name = "s1d13806fb", -+ .id = -1, -+ .dev = { -+ .dma_mask = &s1dfb_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &ek_s1dfb_pdata, -+ }, -+ .resource = ek_s1dfb_resource, -+ .num_resources = ARRAY_SIZE(ek_s1dfb_resource), -+}; -+ -+static void __init ek_add_device_video(void) -+{ -+ platform_device_register(&ek_s1dfb_device); -+} -+#else -+static void __init ek_add_device_video(void) {} -+#endif -+ - static struct at91_eth_data __initdata ek_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -@@ -113,7 +294,7 @@ - #define EK_FLASH_SIZE 0x200000 - - static struct physmap_flash_data ek_flash_data = { -- .width = 2, -+ .width = 2, - }; - - static struct resource ek_flash_resource = { -@@ -132,6 +313,18 @@ - .num_resources = 1, - }; - -+static struct at91_gpio_led ek_leds[] = { -+ { -+ .name = "led0", -+ .gpio = AT91_PIN_PB1, -+ .trigger = "heartbeat", -+ }, -+ { -+ .name = "led1", -+ .gpio = AT91_PIN_PB2, -+ .trigger = "timer", -+ } -+}; - - static void __init ek_board_init(void) - { -@@ -158,8 +351,10 @@ - #endif - /* NOR Flash */ - platform_device_register(&ek_flash); -+ /* LEDs */ -+ at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); - /* VGA */ --// ek_add_device_video(); -+ ek_add_device_video(); - } - - MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/board-kb9202.c linux-2.6.22-rc5.new/arch/arm/mach-at91/board-kb9202.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/board-kb9202.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/board-kb9202.c 2007-07-29 05:23:04.000000000 +0200 -@@ -37,6 +37,8 @@ - #include <asm/arch/board.h> - #include <asm/arch/gpio.h> - -+#include <asm/arch/at91rm9200_mc.h> -+ - #include "generic.h" - - -@@ -111,6 +113,48 @@ - .partition_info = nand_partitions, - }; - -+ -+#if defined(CONFIG_FB_S1D15605) -+#warning "Rather pass reset pin via platform_data" -+static struct resource kb9202_lcd_resources[] = { -+ [0] = { -+ .start = AT91_CHIPSELECT_2, -+ .end = AT91_CHIPSELECT_2 + 0x200FF, -+ .flags = IORESOURCE_MEM -+ }, -+ [1] = { /* reset pin */ -+ .start = AT91_PIN_PC22, -+ .end = AT91_PIN_PC22, -+ .flags = IORESOURCE_MEM -+ }, -+}; -+ -+static struct platform_device kb9202_lcd_device = { -+ .name = "s1d15605fb", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(kb9202_lcd_resources), -+ .resource = kb9202_lcd_resources, -+}; -+ -+static void __init kb9202_add_device_lcd(void) -+{ -+ /* In case the boot loader did not set the chip select mode and timing */ -+ at91_sys_write(AT91_SMC_CSR(2), -+ AT91_SMC_WSEN | AT91_SMC_NWS_(18) | AT91_SMC_TDF_(1) | AT91_SMC_DBW_8 | -+ AT91_SMC_RWSETUP_(1) | AT91_SMC_RWHOLD_(1)); -+ -+ /* Backlight pin = output, off */ -+ at91_set_gpio_output(AT91_PIN_PC23, 0); -+ -+ /* Reset pin = output, in reset */ -+ at91_set_gpio_output(AT91_PIN_PC22, 0); -+ -+ platform_device_register(&kb9202_lcd_device); -+} -+#else -+static void __init kb9202_add_device_lcd(void) {} -+#endif -+ - static void __init kb9202_board_init(void) - { - /* Serial */ -@@ -129,6 +173,8 @@ - at91_add_device_spi(NULL, 0); - /* NAND */ - at91_add_device_nand(&kb9202_nand_data); -+ /* LCD */ -+ kb9202_add_device_lcd(); - } - - MACHINE_START(KB9200, "KB920x") -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/board-sam9261ek.c linux-2.6.22-rc5.new/arch/arm/mach-at91/board-sam9261ek.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/board-sam9261ek.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/board-sam9261ek.c 2007-07-29 05:23:04.000000000 +0200 -@@ -27,6 +27,9 @@ - #include <linux/spi/spi.h> - #include <linux/spi/ads7846.h> - #include <linux/dm9000.h> -+#include <linux/fb.h> -+ -+#include <video/atmel_lcdc.h> - - #include <asm/hardware.h> - #include <asm/setup.h> -@@ -251,6 +254,7 @@ - .bus_num = 0, - .platform_data = &ads_info, - .irq = AT91SAM9261_ID_IRQ0, -+ .controller_data = AT91_PIN_PA28, /* CS pin */ - }, - #endif - #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) -@@ -271,6 +275,65 @@ - }; - - -+/* -+ * LCD Controller -+ */ -+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) -+static struct fb_videomode at91_tft_vga_modes[] = { -+ { -+ .name = "TX09D50VM1CCA @ 60", -+ .refresh = 60, -+ .xres = 240, .yres = 320, -+ .pixclock = KHZ2PICOS(4965), -+ -+ .left_margin = 1, .right_margin = 33, -+ .upper_margin = 1, .lower_margin = 0, -+ .hsync_len = 5, .vsync_len = 1, -+ -+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ .vmode = FB_VMODE_NONINTERLACED, -+ }, -+}; -+ -+static struct fb_monspecs at91fb_default_monspecs = { -+ .manufacturer = "HIT", -+ .monitor = "TX09D50VM1CCA", -+ -+ .modedb = at91_tft_vga_modes, -+ .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), -+ .hfmin = 15000, -+ .hfmax = 64000, -+ .vfmin = 50, -+ .vfmax = 150, -+}; -+ -+#define AT91SAM9261_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ -+ | ATMEL_LCDC_DISTYPE_TFT \ -+ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -+ -+static void at91_lcdc_power_control(int on) -+{ -+ if (on) -+ at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ -+ else -+ at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ -+} -+ -+/* Driver datas */ -+static struct atmel_lcdfb_info __initdata ek_lcdc_data = { -+ .default_bpp = 16, -+ .default_dmacon = ATMEL_LCDC_DMAEN, -+ .default_lcdcon2 = AT91SAM9261_DEFAULT_LCDCON2, -+ .default_monspecs = &at91fb_default_monspecs, -+ .atmel_lcdfb_power_control = at91_lcdc_power_control, -+ .guard_time = 1, -+}; -+ -+#else -+static struct atmel_lcdfb_info __initdata ek_lcdc_data; -+#endif -+ -+ - static void __init ek_board_init(void) - { - /* Serial */ -@@ -296,6 +359,8 @@ - /* MMC */ - at91_add_device_mmc(0, &ek_mmc_data); - #endif -+ /* LCD Controller */ -+ at91_add_device_lcdc(&ek_lcdc_data); - } - - MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/board-sam9263ek.c linux-2.6.22-rc5.new/arch/arm/mach-at91/board-sam9263ek.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/board-sam9263ek.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/board-sam9263ek.c 2007-07-29 05:23:04.000000000 +0200 -@@ -26,6 +26,9 @@ - #include <linux/platform_device.h> - #include <linux/spi/spi.h> - #include <linux/spi/ads7846.h> -+#include <linux/fb.h> -+ -+#include <video/atmel_lcdc.h> - - #include <asm/hardware.h> - #include <asm/setup.h> -@@ -202,6 +205,65 @@ - - - /* -+ * LCD Controller -+ */ -+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) -+static struct fb_videomode at91_tft_vga_modes[] = { -+ { -+ .name = "TX09D50VM1CCA @ 60", -+ .refresh = 60, -+ .xres = 240, .yres = 320, -+ .pixclock = KHZ2PICOS(4965), -+ -+ .left_margin = 1, .right_margin = 33, -+ .upper_margin = 1, .lower_margin = 0, -+ .hsync_len = 5, .vsync_len = 1, -+ -+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ .vmode = FB_VMODE_NONINTERLACED, -+ }, -+}; -+ -+static struct fb_monspecs at91fb_default_monspecs = { -+ .manufacturer = "HIT", -+ .monitor = "TX09D70VM1CCA", -+ -+ .modedb = at91_tft_vga_modes, -+ .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), -+ .hfmin = 15000, -+ .hfmax = 64000, -+ .vfmin = 50, -+ .vfmax = 150, -+}; -+ -+#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ -+ | ATMEL_LCDC_DISTYPE_TFT \ -+ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -+ -+static void at91_lcdc_power_control(int on) -+{ -+ if (on) -+ at91_set_gpio_value(AT91_PIN_PD12, 0); /* power up */ -+ else -+ at91_set_gpio_value(AT91_PIN_PD12, 1); /* power down */ -+} -+ -+/* Driver datas */ -+static struct atmel_lcdfb_info __initdata ek_lcdc_data = { -+ .default_bpp = 16, -+ .default_dmacon = ATMEL_LCDC_DMAEN, -+ .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2, -+ .default_monspecs = &at91fb_default_monspecs, -+ .atmel_lcdfb_power_control = at91_lcdc_power_control, -+ .guard_time = 1, -+}; -+ -+#else -+static struct atmel_lcdfb_info __initdata ek_lcdc_data; -+#endif -+ -+ -+/* - * AC97 - */ - static struct atmel_ac97_data ek_ac97_data = { -@@ -230,6 +292,8 @@ - at91_add_device_nand(&ek_nand_data); - /* I2C */ - at91_add_device_i2c(); -+ /* LCD Controller */ -+ at91_add_device_lcdc(&ek_lcdc_data); - /* AC97 */ - at91_add_device_ac97(&ek_ac97_data); - } -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/clock.c linux-2.6.22-rc5.new/arch/arm/mach-at91/clock.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/clock.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/clock.c 2007-07-29 05:23:04.000000000 +0200 -@@ -32,6 +32,7 @@ - #include <asm/arch/cpu.h> - - #include "clock.h" -+#include "generic.h" - - - /* -@@ -254,6 +255,23 @@ - - /*------------------------------------------------------------------------*/ - -+#ifdef CONFIG_PM -+ -+int clk_must_disable(struct clk *clk) -+{ -+ if (!at91_suspend_entering_slow_clock()) -+ return 0; -+ -+ while (clk->parent) -+ clk = clk->parent; -+ return clk != &clk32k; -+} -+EXPORT_SYMBOL(clk_must_disable); -+ -+#endif -+ -+/*------------------------------------------------------------------------*/ -+ - #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS - - /* -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/generic.h linux-2.6.22-rc5.new/arch/arm/mach-at91/generic.h ---- linux-2.6.22-rc5/arch/arm/mach-at91/generic.h 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/generic.h 2007-07-29 05:23:04.000000000 +0200 -@@ -36,6 +36,7 @@ - /* Power Management */ - extern void at91_irq_suspend(void); - extern void at91_irq_resume(void); -+extern int at91_suspend_entering_slow_clock(void); - - /* GPIO */ - #define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/ics1523.c linux-2.6.22-rc5.new/arch/arm/mach-at91/ics1523.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/ics1523.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/ics1523.c 2007-07-29 05:23:04.000000000 +0200 -@@ -0,0 +1,207 @@ -+/* -+ * arch/arm/mach-at91rm9200/ics1523.c -+ * -+ * Copyright (C) 2003 ATMEL Rousset -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <asm/hardware.h> -+#include <asm/io.h> -+ -+#include <linux/clk.h> -+#include <linux/delay.h> -+#include <linux/err.h> -+#include <linux/init.h> -+ -+#include <asm/arch/ics1523.h> -+#include <asm/arch/at91_twi.h> -+#include <asm/arch/gpio.h> -+ -+/* TWI Errors */ -+#define AT91_TWI_ERROR (AT91_TWI_NACK | AT91_TWI_UNRE | AT91_TWI_OVRE) -+ -+ -+static void __iomem *twi_base; -+ -+#define at91_twi_read(reg) __raw_readl(twi_base + (reg)) -+#define at91_twi_write(reg, val) __raw_writel((val), twi_base + (reg)) -+ -+ -+/* ----------------------------------------------------------------------------- -+ * Initialization of TWI CLOCK -+ * ----------------------------------------------------------------------------- */ -+ -+static void at91_ics1523_SetTwiClock(unsigned int mck_khz) -+{ -+ int sclock; -+ -+ /* Here, CKDIV = 1 and CHDIV = CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */ -+ sclock = (10*mck_khz / ICS_TRANSFER_RATE); -+ if (sclock % 10 >= 5) -+ sclock = (sclock /10) - 5; -+ else -+ sclock = (sclock /10)- 6; -+ sclock = (sclock + (4 - sclock %4)) >> 2; /* div 4 */ -+ -+ at91_twi_write(AT91_TWI_CWGR, 0x00010000 | sclock | (sclock << 8)); -+} -+ -+/* ----------------------------------------------------------------------------- -+ * Read a byte with TWI Interface from the Clock Generator ICS1523 -+ * ----------------------------------------------------------------------------- */ -+ -+static int at91_ics1523_ReadByte(unsigned char reg_address, unsigned char *data_in) -+{ -+ int Status, nb_trial; -+ -+ at91_twi_write(AT91_TWI_MMR, AT91_TWI_MREAD | AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR)); -+ at91_twi_write(AT91_TWI_IADR, reg_address); -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP); -+ -+ /* Program temporizing period (300us) */ -+ udelay(300); -+ -+ /* Wait TXcomplete ... */ -+ nb_trial = 0; -+ Status = at91_twi_read(AT91_TWI_SR); -+ while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) { -+ nb_trial++; -+ Status = at91_twi_read(AT91_TWI_SR); -+ } -+ -+ if (Status & AT91_TWI_TXCOMP) { -+ *data_in = (unsigned char) at91_twi_read(AT91_TWI_RHR); -+ return ICS1523_ACCESS_OK; -+ } -+ else -+ return ICS1523_ACCESS_ERROR; -+} -+ -+/* ----------------------------------------------------------------------------- -+ * Write a byte with TWI Interface to the Clock Generator ICS1523 -+ * ----------------------------------------------------------------------------- */ -+ -+static int at91_ics1523_WriteByte(unsigned char reg_address, unsigned char data_out) -+{ -+ int Status, nb_trial; -+ -+ at91_twi_write(AT91_TWI_MMR, AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR)); -+ at91_twi_write(AT91_TWI_IADR, reg_address); -+ at91_twi_write(AT91_TWI_THR, data_out); -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP); -+ -+ /* Program temporizing period (300us) */ -+ udelay(300); -+ -+ nb_trial = 0; -+ Status = at91_twi_read(AT91_TWI_SR); -+ while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) { -+ nb_trial++; -+ if (Status & AT91_TWI_ERROR) { -+ /* If Underrun OR NACK - Start again */ -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP); -+ -+ /* Program temporizing period (300us) */ -+ udelay(300); -+ } -+ Status = at91_twi_read(AT91_TWI_SR); -+ }; -+ -+ if (Status & AT91_TWI_TXCOMP) -+ return ICS1523_ACCESS_OK; -+ else -+ return ICS1523_ACCESS_ERROR; -+} -+ -+/* ----------------------------------------------------------------------------- -+ * Initialization of the Clock Generator ICS1523 -+ * ----------------------------------------------------------------------------- */ -+ -+int at91_ics1523_init(void) -+{ -+ int nb_trial; -+ int ack = ICS1523_ACCESS_OK; -+ unsigned int status = 0xffffffff; -+ struct clk *twi_clk; -+ -+ /* Map in TWI peripheral */ -+ twi_base = ioremap(AT91RM9200_BASE_TWI, SZ_16K); -+ if (!twi_base) -+ return -ENOMEM; -+ -+ /* pins used for TWI interface */ -+ at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */ -+ at91_set_multi_drive(AT91_PIN_PA25, 1); -+ at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */ -+ at91_set_multi_drive(AT91_PIN_PA26, 1); -+ -+ /* Enable the TWI clock */ -+ twi_clk = clk_get(NULL, "twi_clk"); -+ if (IS_ERR(twi_clk)) -+ return ICS1523_ACCESS_ERROR; -+ clk_enable(twi_clk); -+ -+ /* Disable interrupts */ -+ at91_twi_write(AT91_TWI_IDR, -1); -+ -+ /* Reset peripheral */ -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST); -+ -+ /* Set Master mode */ -+ at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN); -+ -+ /* Set TWI Clock Waveform Generator Register */ -+ at91_ics1523_SetTwiClock(60000); /* MCK in KHz = 60000 KHz */ -+ -+ /* ICS1523 Initialisation */ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) 0); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OE, (unsigned char) (ICS_OEF | ICS_OET2 | ICS_OETCK)); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OD, (unsigned char) (ICS_INSEL | 0x7F)); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0); -+ -+ nb_trial = 0; -+ do { -+ nb_trial++; -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) (ICS_ENDLS | ICS_ENPLS | ICS_PDEN /*| ICS_FUNCSEL*/)); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_LCR, (unsigned char) (ICS_PSD | ICS_PFD)); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD0, (unsigned char) 0x39) ; /* 0x7A */ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD1, (unsigned char) 0x00); -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_PLLR)); -+ -+ /* Program 1ms temporizing period */ -+ mdelay(1); -+ -+ at91_ics1523_ReadByte ((unsigned char) ICS_SR, (char *)&status); -+ } while (!((unsigned int) status & (unsigned int) ICS_PLLLOCK) && (nb_trial < 10)); -+ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAC, (unsigned char) 0x03) ; /* 0x01 */ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_DPAR)); -+ -+ /* Program 1ms temporizing period */ -+ mdelay(1); -+ -+ ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0x00); -+ -+ /* Program 1ms temporizing period */ -+ mdelay(1); -+ -+ /* All done - cleanup */ -+ iounmap(twi_base); -+ clk_disable(twi_clk); -+ clk_put(twi_clk); -+ -+ return ack; -+} -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/Kconfig linux-2.6.22-rc5.new/arch/arm/mach-at91/Kconfig ---- linux-2.6.22-rc5/arch/arm/mach-at91/Kconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/Kconfig 2007-07-29 05:23:04.000000000 +0200 -@@ -97,6 +97,12 @@ - help - Select this if you are using Sperry-Sun's KAFA board. - -+config MACH_CHUB -+ bool "Promwad Chub board" -+ depends on ARCH_AT91RM9200 -+ help -+ Select this if you are using Promwad's Chub board. -+ - endif - - # ---------------------------------------------------------- -@@ -121,6 +127,13 @@ - Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit - <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> - -+config MACH_CAM60 -+ bool "KwikByte CAM60 board" -+ depends on ARCH_AT91SAM9260 -+ help -+ Select this if you are using KwikByte's CAM60 board based on the Atmel AT91SAM9260. -+ <http://www.kwikbyte.com> -+ - endif - - # ---------------------------------------------------------- -@@ -184,6 +197,20 @@ - On AT91SAM926x boards both types of NAND flash can be present - (8 and 16 bit data bus width). - -+config CSB300_WAKE_SW0 -+ bool "CSB300 SW0 irq0 wakeup" -+ depends on MACH_CSB337 && PM -+ help -+ If you have a CSB300 connected to your CSB337, this lets -+ SW0 serve as a wakeup button. It uses IRQ0. -+ -+config CSB300_WAKE_SW1 -+ bool "CSB300 SW1 gpio wakeup" -+ depends on MACH_CSB337 && PM -+ help -+ If you have a CSB300 connected to your CSB337, this lets -+ SW1 serve as a wakeup button. It uses GPIO. -+ - # ---------------------------------------------------------- - - comment "AT91 Feature Selections" -@@ -194,6 +221,20 @@ - Select this if you need to program one or more of the PCK0..PCK3 - programmable clock outputs. - -+config ATMEL_TCLIB -+ bool "Timer/Counter Library" -+ help -+ Select this if you want a library to allocate the Timer/Counter -+ blocks found on many Atmel processors. This facilitates using -+ these modules despite processor differences. -+ -+config AT91_SLOW_CLOCK -+ bool "Suspend-to-RAM uses slow clock mode (EXPERIMENTAL)" -+ depends on PM && EXPERIMENTAL -+ help -+ Select this if you wish to put the CPU into slow clock mode -+ while in the "Suspend to RAM" state, to save more power. -+ - endmenu - - endif -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/Makefile linux-2.6.22-rc5.new/arch/arm/mach-at91/Makefile ---- linux-2.6.22-rc5/arch/arm/mach-at91/Makefile 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/Makefile 2007-07-29 05:23:04.000000000 +0200 -@@ -8,6 +8,8 @@ - obj- := - - obj-$(CONFIG_PM) += pm.o -+obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o -+obj-$(CONFIG_ATMEL_TCLIB) += tclib.o - - # CPU-specific support - obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -@@ -26,10 +28,12 @@ - obj-$(CONFIG_MACH_KB9200) += board-kb9202.o - obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o - obj-$(CONFIG_MACH_KAFA) += board-kafa.o -+obj-$(CONFIG_MACH_CHUB) += board-chub.o - obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o - - # AT91SAM9260 board-specific support - obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o -+obj-$(CONFIG_MACH_CAM60) += board-cam60.o - - # AT91SAM9261 board-specific support - obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o -@@ -51,7 +55,7 @@ - obj-$(CONFIG_LEDS) += $(led-y) - - # VGA support --#obj-$(CONFIG_FB_S1D13XXX) += ics1523.o -+obj-$(CONFIG_FB_S1D13XXX) += ics1523.o - - - ifeq ($(CONFIG_PM_DEBUG),y) -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/pm.c linux-2.6.22-rc5.new/arch/arm/mach-at91/pm.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/pm.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/pm.c 2007-07-29 05:23:04.000000000 +0200 -@@ -63,6 +63,7 @@ - * Verify that all the clocks are correct before entering - * slow-clock mode. - */ -+#warning "SAM9260 only has 3 programmable clocks." - static int at91_pm_verify_clocks(void) - { - unsigned long scsr; -@@ -103,20 +104,15 @@ - } - - /* -- * Call this from platform driver suspend() to see how deeply to suspend. -+ * This is called from clk_must_disable(), to see how deeply to suspend. - * For example, some controllers (like OHCI) need one of the PLL clocks - * in order to act as a wakeup source, and those are not available when - * going into slow clock mode. -- * -- * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have -- * the very same problem (but not using at91 main_clk), and it'd be better -- * to add one generic API rather than lots of platform-specific ones. - */ - int at91_suspend_entering_slow_clock(void) - { - return (target_state == PM_SUSPEND_MEM); - } --EXPORT_SYMBOL(at91_suspend_entering_slow_clock); - - - static void (*slow_clock)(void); -@@ -205,16 +201,23 @@ - .enter = at91_pm_enter, - }; - -+#ifdef CONFIG_AT91_SLOW_CLOCK -+extern void at91rm9200_slow_clock(void); -+extern u32 at91rm9200_slow_clock_sz; -+#endif -+ - static int __init at91_pm_init(void) - { -- printk("AT91: Power Management\n"); -- --#ifdef CONFIG_AT91_PM_SLOW_CLOCK -- /* REVISIT allocations of SRAM should be dynamically managed. -+#ifdef CONFIG_AT91_SLOW_CLOCK -+ /* -+ * REVISIT allocations of SRAM should be dynamically managed. - * FIQ handlers and other components will want SRAM/TCM too... - */ -- slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K)); -+ slow_clock = (void *) (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE + (3 * SZ_4K)); - memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz); -+ printk("AT91: Power Management (with slow clock mode)\n"); -+#else -+ printk("AT91: Power Management\n"); - #endif - - /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */ -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/pm.c.orig linux-2.6.22-rc5.new/arch/arm/mach-at91/pm.c.orig ---- linux-2.6.22-rc5/arch/arm/mach-at91/pm.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/pm.c.orig 2007-06-17 04:09:12.000000000 +0200 -@@ -0,0 +1,227 @@ -+/* -+ * arch/arm/mach-at91/pm.c -+ * AT91 Power Management -+ * -+ * Copyright (C) 2005 David Brownell -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include <linux/pm.h> -+#include <linux/sched.h> -+#include <linux/proc_fs.h> -+#include <linux/pm.h> -+#include <linux/interrupt.h> -+#include <linux/sysfs.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+ -+#include <asm/io.h> -+#include <asm/irq.h> -+#include <asm/atomic.h> -+#include <asm/mach/time.h> -+#include <asm/mach/irq.h> -+#include <asm/mach-types.h> -+ -+#include <asm/arch/at91_pmc.h> -+#include <asm/arch/at91rm9200_mc.h> -+#include <asm/arch/gpio.h> -+#include <asm/arch/cpu.h> -+ -+#include "generic.h" -+ -+ -+static int at91_pm_valid_state(suspend_state_t state) -+{ -+ switch (state) { -+ case PM_SUSPEND_ON: -+ case PM_SUSPEND_STANDBY: -+ case PM_SUSPEND_MEM: -+ return 1; -+ -+ default: -+ return 0; -+ } -+} -+ -+ -+static suspend_state_t target_state; -+ -+/* -+ * Called after processes are frozen, but before we shutdown devices. -+ */ -+static int at91_pm_prepare(suspend_state_t state) -+{ -+ target_state = state; -+ return 0; -+} -+ -+/* -+ * Verify that all the clocks are correct before entering -+ * slow-clock mode. -+ */ -+static int at91_pm_verify_clocks(void) -+{ -+ unsigned long scsr; -+ int i; -+ -+ scsr = at91_sys_read(AT91_PMC_SCSR); -+ -+ /* USB must not be using PLLB */ -+ if (cpu_is_at91rm9200()) { -+ if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) { -+ pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n"); -+ return 0; -+ } -+ } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) { -+ if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) { -+ pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n"); -+ return 0; -+ } -+ } -+ -+#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS -+ /* PCK0..PCK3 must be disabled, or configured to use clk32k */ -+ for (i = 0; i < 4; i++) { -+ u32 css; -+ -+ if ((scsr & (AT91_PMC_PCK0 << i)) == 0) -+ continue; -+ -+ css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; -+ if (css != AT91_PMC_CSS_SLOW) { -+ pr_debug("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); -+ return 0; -+ } -+ } -+#endif -+ -+ return 1; -+} -+ -+/* -+ * Call this from platform driver suspend() to see how deeply to suspend. -+ * For example, some controllers (like OHCI) need one of the PLL clocks -+ * in order to act as a wakeup source, and those are not available when -+ * going into slow clock mode. -+ * -+ * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have -+ * the very same problem (but not using at91 main_clk), and it'd be better -+ * to add one generic API rather than lots of platform-specific ones. -+ */ -+int at91_suspend_entering_slow_clock(void) -+{ -+ return (target_state == PM_SUSPEND_MEM); -+} -+EXPORT_SYMBOL(at91_suspend_entering_slow_clock); -+ -+ -+static void (*slow_clock)(void); -+ -+ -+static int at91_pm_enter(suspend_state_t state) -+{ -+ at91_gpio_suspend(); -+ at91_irq_suspend(); -+ -+ pr_debug("AT91: PM - wake mask %08x, pm state %d\n", -+ /* remember all the always-wake irqs */ -+ (at91_sys_read(AT91_PMC_PCSR) -+ | (1 << AT91_ID_FIQ) -+ | (1 << AT91_ID_SYS) -+ | (at91_extern_irq)) -+ & at91_sys_read(AT91_AIC_IMR), -+ state); -+ -+ switch (state) { -+ /* -+ * Suspend-to-RAM is like STANDBY plus slow clock mode, so -+ * drivers must suspend more deeply: only the master clock -+ * controller may be using the main oscillator. -+ */ -+ case PM_SUSPEND_MEM: -+ /* -+ * Ensure that clocks are in a valid state. -+ */ -+ if (!at91_pm_verify_clocks()) -+ goto error; -+ -+ /* -+ * Enter slow clock mode by switching over to clk32k and -+ * turning off the main oscillator; reverse on wakeup. -+ */ -+ if (slow_clock) { -+ slow_clock(); -+ break; -+ } else { -+ /* DEVELOPMENT ONLY */ -+ pr_info("AT91: PM - no slow clock mode yet ...\n"); -+ /* FALLTHROUGH leaving master clock alone */ -+ } -+ -+ /* -+ * STANDBY mode has *all* drivers suspended; ignores irqs not -+ * marked as 'wakeup' event sources; and reduces DRAM power. -+ * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and -+ * nothing fancy done with main or cpu clocks. -+ */ -+ case PM_SUSPEND_STANDBY: -+ /* -+ * NOTE: the Wait-for-Interrupt instruction needs to be -+ * in icache so the SDRAM stays in self-refresh mode until -+ * the wakeup IRQ occurs. -+ */ -+ asm("b 1f; .align 5; 1:"); -+ asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ -+ at91_sys_write(AT91_SDRAMC_SRR, 1); /* self-refresh mode */ -+ /* fall though to next state */ -+ -+ case PM_SUSPEND_ON: -+ asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ -+ break; -+ -+ default: -+ pr_debug("AT91: PM - bogus suspend state %d\n", state); -+ goto error; -+ } -+ -+ pr_debug("AT91: PM - wakeup %08x\n", -+ at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR)); -+ -+error: -+ target_state = PM_SUSPEND_ON; -+ at91_irq_resume(); -+ at91_gpio_resume(); -+ return 0; -+} -+ -+ -+static struct pm_ops at91_pm_ops ={ -+ .valid = at91_pm_valid_state, -+ .prepare = at91_pm_prepare, -+ .enter = at91_pm_enter, -+}; -+ -+static int __init at91_pm_init(void) -+{ -+ printk("AT91: Power Management\n"); -+ -+#ifdef CONFIG_AT91_PM_SLOW_CLOCK -+ /* REVISIT allocations of SRAM should be dynamically managed. -+ * FIQ handlers and other components will want SRAM/TCM too... -+ */ -+ slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K)); -+ memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz); -+#endif -+ -+ /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */ -+ at91_sys_write(AT91_SDRAMC_LPR, 0); -+ -+ pm_set_ops(&at91_pm_ops); -+ -+ return 0; -+} -+arch_initcall(at91_pm_init); -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/pm_slowclock.S linux-2.6.22-rc5.new/arch/arm/mach-at91/pm_slowclock.S ---- linux-2.6.22-rc5/arch/arm/mach-at91/pm_slowclock.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/pm_slowclock.S 2007-07-29 05:23:04.000000000 +0200 -@@ -0,0 +1,172 @@ -+/* -+ * arch/arm/mach-at91/pm_slow_clock.S -+ * -+ * Copyright (C) 2006 Savin Zlobec -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include <linux/linkage.h> -+#include <asm/hardware.h> -+#include <asm/arch/at91_pmc.h> -+#include <asm/arch/at91rm9200_mc.h> -+ -+#define MCKRDY_TIMEOUT 1000 -+#define MOSCRDY_TIMEOUT 1000 -+#define PLLALOCK_TIMEOUT 1000 -+ -+ .macro wait_mckrdy -+ mov r2, #MCKRDY_TIMEOUT -+1: sub r2, r2, #1 -+ cmp r2, #0 -+ beq 2f -+ ldr r3, [r1, #AT91_PMC_SR] -+ tst r3, #AT91_PMC_MCKRDY -+ beq 1b -+2: -+ .endm -+ -+ .macro wait_moscrdy -+ mov r2, #MOSCRDY_TIMEOUT -+1: sub r2, r2, #1 -+ cmp r2, #0 -+ beq 2f -+ ldr r3, [r1, #AT91_PMC_SR] -+ tst r3, #AT91_PMC_MOSCS -+ beq 1b -+2: -+ .endm -+ -+ .macro wait_pllalock -+ mov r2, #PLLALOCK_TIMEOUT -+1: sub r2, r2, #1 -+ cmp r2, #0 -+ beq 2f -+ ldr r3, [r1, #AT91_PMC_SR] -+ tst r3, #AT91_PMC_LOCKA -+ beq 1b -+2: -+ .endm -+ -+ .macro wait_plladis -+ mov r2, #PLLALOCK_TIMEOUT -+1: sub r2, r2, #1 -+ cmp r2, #0 -+ beq 2f -+ ldr r3, [r1, #AT91_PMC_SR] -+ tst r3, #AT91_PMC_LOCKA -+ bne 1b -+2: -+ .endm -+ -+ .text -+ -+ENTRY(at91rm9200_slow_clock) -+ -+ ldr r1, .at91_va_base_sys -+ -+ /* Put SDRAM in self refresh mode */ -+ -+ b 1f -+ .align 5 -+1: mcr p15, 0, r0, c7, c10, 4 -+ mov r2, #1 -+ str r2, [r1, #AT91_SDRAMC_SRR] -+ -+ /* Save Master clock setting */ -+ -+ ldr r2, [r1, #AT91_PMC_MCKR] -+ str r2, .saved_mckr -+ -+ /* -+ * Set the Master clock source to slow clock -+ * -+ * First set the CSS field, wait for MCKRDY -+ * and than set the PRES and MDIV fields. -+ * -+ * See eratta #2[78] for details. -+ */ -+ -+ bic r2, r2, #3 -+ str r2, [r1, #AT91_PMC_MCKR] -+ -+ wait_mckrdy -+ -+ mov r2, #0 -+ str r2, [r1, #AT91_PMC_MCKR] -+ -+ /* Save PLLA setting and disable it */ -+ -+ ldr r2, [r1, #AT91_CKGR_PLLAR] -+ str r2, .saved_pllar -+ -+ mov r2, #0 -+ str r2, [r1, #AT91_CKGR_PLLAR] -+ -+ wait_plladis -+ -+ /* Turn off the main oscillator */ -+ -+ ldr r2, [r1, #AT91_CKGR_MOR] -+ bic r2, r2, #AT91_PMC_MOSCEN -+ str r2, [r1, #AT91_CKGR_MOR] -+ -+ /* Wait for interrupt */ -+ -+ mcr p15, 0, r0, c7, c0, 4 -+ -+ /* Turn on the main oscillator */ -+ -+ ldr r2, [r1, #AT91_CKGR_MOR] -+ orr r2, r2, #AT91_PMC_MOSCEN -+ str r2, [r1, #AT91_CKGR_MOR] -+ -+ wait_moscrdy -+ -+ /* Restore PLLA setting */ -+ -+ ldr r2, .saved_pllar -+ str r2, [r1, #AT91_CKGR_PLLAR] -+ -+ wait_pllalock -+ -+ /* -+ * Restore master clock setting -+ * -+ * First set PRES if it was not 0, -+ * than set CSS and MDIV fields. -+ * After every change wait for -+ * MCKRDY. -+ * -+ * See eratta #2[78] for details. -+ */ -+ -+ ldr r2, .saved_mckr -+ tst r2, #0x1C -+ beq 2f -+ and r2, r2, #0x1C -+ str r2, [r1, #AT91_PMC_MCKR] -+ -+ wait_mckrdy -+ -+2: ldr r2, .saved_mckr -+ str r2, [r1, #AT91_PMC_MCKR] -+ -+ wait_mckrdy -+ -+ mov pc, lr -+ -+.saved_mckr: -+ .word 0 -+ -+.saved_pllar: -+ .word 0 -+ -+.at91_va_base_sys: -+ .word AT91_VA_BASE_SYS -+ -+ENTRY(at91rm9200_slow_clock_sz) -+ .word .-at91rm9200_slow_clock -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/tclib.c linux-2.6.22-rc5.new/arch/arm/mach-at91/tclib.c ---- linux-2.6.22-rc5/arch/arm/mach-at91/tclib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/tclib.c 2007-07-29 05:23:04.000000000 +0200 -@@ -0,0 +1,17 @@ -+#include <linux/clk.h> -+#include <linux/kernel.h> -+#include <linux/module.h> -+ -+#include "tclib.h" -+ -+static struct atmel_tcblock *blocks; -+static int nblocks; -+ -+/* -+ * Called from the processor-specific init to register the TC Blocks. -+ */ -+void __init atmel_tc_init(struct atmel_tcblock *tcblocks, int n) -+{ -+ blocks = tcblocks; -+ nblocks = n; -+} -diff -urN linux-2.6.22-rc5/arch/arm/mach-at91/tclib.h linux-2.6.22-rc5.new/arch/arm/mach-at91/tclib.h ---- linux-2.6.22-rc5/arch/arm/mach-at91/tclib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/arch/arm/mach-at91/tclib.h 2007-07-29 05:23:04.000000000 +0200 -@@ -0,0 +1,11 @@ -+ -+#define TC_PER_TCB 3 -+ -+struct atmel_tcblock { -+ u32 physaddr; -+ void __iomem *ioaddr; -+ struct clk *clk[TC_PER_TCB]; -+ int irq[TC_PER_TCB]; -+}; -+ -+extern void __init atmel_tc_init(struct atmel_tcblock *tcblocks, int n); -diff -urN -x CVS linux-2.6.22-rc1/include/asm-arm/arch-at91/at91_mci.h linux-2.6-stable/include/asm-arm/arch-at91/at91_mci.h ---- linux-2.6.22-rc1/include/asm-arm/arch-at91/at91_mci.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91_mci.h Tue May 8 12:13:31 2007 -@@ -26,6 +26,9 @@ - #define AT91_MCI_MR 0x04 /* Mode Register */ - #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ - #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -+#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ -+#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ -+#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ - #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ - #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ - #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ -diff -urN -x CVS linux-2.6.22-rc1/include/asm-arm/arch-at91/at91_pmc.h linux-2.6-stable/include/asm-arm/arch-at91/at91_pmc.h ---- linux-2.6.22-rc1/include/asm-arm/arch-at91/at91_pmc.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91_pmc.h Fri May 11 16:45:00 2007 -@@ -37,7 +37,9 @@ - #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ - #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ - --#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ -+#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL only] */ -+ -+#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ - #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ - #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ - #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -diff -urN -x CVS linux-2.6.22-rc1/include/asm-arm/arch-at91/at91sam9260_matrix.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260_matrix.h ---- linux-2.6.22-rc1/include/asm-arm/arch-at91/at91sam9260_matrix.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260_matrix.h Fri May 11 16:20:33 2007 -@@ -67,7 +67,7 @@ - #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ - #define AT91_MATRIX_CS4A_SMC (0 << 4) - #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) --#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ -+#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ - #define AT91_MATRIX_CS5A_SMC (0 << 5) - #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) - #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -diff -urN -x CVS linux-2.6.22-rc1/include/asm-arm/arch-at91/board.h linux-2.6-stable/include/asm-arm/arch-at91/board.h ---- linux-2.6.22-rc1/include/asm-arm/arch-at91/board.h Thu May 17 12:13:17 2007 -+++ linux-2.6-stable/include/asm-arm/arch-at91/board.h Thu May 10 12:21:10 2007 -@@ -124,9 +124,21 @@ - }; - extern void __init at91_add_device_ac97(struct atmel_ac97_data *data); - -+ /* ISI */ -+extern void __init at91_add_device_isi(void); -+ - /* LEDs */ - extern u8 at91_leds_cpu; - extern u8 at91_leds_timer; - extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); - -+struct at91_gpio_led { -+ u8 index; /* index of LED */ -+ char* name; /* name of LED */ -+ u8 gpio; /* AT91_PIN_xx */ -+ u8 flags; /* 1=active-high */ -+ char* trigger; /* default trigger */ -+}; -+extern void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr); -+ - #endif -diff -urN -x CVS linux-2.6.22-rc1/include/asm-arm/arch-at91/ics1523.h linux-2.6-stable/include/asm-arm/arch-at91/ics1523.h ---- linux-2.6.22-rc1/include/asm-arm/arch-at91/ics1523.h Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/include/asm-arm/arch-at91/ics1523.h Mon May 14 13:49:47 2007 -@@ -0,0 +1,154 @@ -+//*---------------------------------------------------------------------------- -+//* ATMEL Microcontroller Software Support - ROUSSET - -+//*---------------------------------------------------------------------------- -+//* The software is delivered "AS IS" without warranty or condition of any -+//* kind, either express, implied or statutory. This includes without -+//* limitation any warranty or condition with respect to merchantability or -+//* fitness for any particular purpose, or against the infringements of -+//* intellectual property rights of others. -+//*---------------------------------------------------------------------------- -+//* File Name : ics1523.h -+//* Object : Clock Generator Prototyping File. -+//* -+//* 1.0 08/28/02 ED : Creation -+//* 1.2 13/01/03 FB : Update on lib V3 -+//*---------------------------------------------------------------------------- -+ -+#ifndef ics1523_h -+#define ics1523_h -+ -+/*-------------------------------------------*/ -+/* ICS1523 TWI Serial Clock Definition */ -+/*-------------------------------------------*/ -+ -+#define ICS_MIN_CLOCK 100 /* Min Frequency Access Clock KHz */ -+#define ICS_MAX_CLOCK 400 /* Max Frequency Access Clock KHz */ -+#define ICS_TRANSFER_RATE ICS_MAX_CLOCK /* Transfer speed to apply */ -+ -+#define ICS_WRITE_CLK_PNB 30 /* TWCK Clock Periods required to write */ -+#define ICS_READ_CLK_PNB 40 /* TWCK Clock Periods required to read */ -+ -+/*-------------------------------------------*/ -+/* ICS1523 Write Operation Definition */ -+/*-------------------------------------------*/ -+ -+#define ICS1523_ACCESS_OK 0 /* OK */ -+#define ICS1523_ACCESS_ERROR -1 /* NOK */ -+ -+/*-------------------------------------------*/ -+/* ICS1523 Device Addresses Definition */ -+/*-------------------------------------------*/ -+ -+#define ICS_ADDR 0x26 /* Device Address */ -+ -+/*--------------------------------------------------*/ -+/* ICS1523 Registers Internal Addresses Definition */ -+/*--------------------------------------------------*/ -+ -+#define ICS_ICR 0x0 /* Input Control Register */ -+#define ICS_LCR 0x1 /* Loop Control Register */ -+#define ICS_FD0 0x2 /* PLL FeedBack Divider LSBs */ -+#define ICS_FD1 0x3 /* PLL FeedBack Divider MSBs */ -+#define ICS_DPAO 0x4 /* Dynamic Phase Aligner Offset */ -+#define ICS_DPAC 0x5 /* Dynamic Phase Aligner Resolution */ -+#define ICS_OE 0x6 /* Output Enables Register */ -+#define ICS_OD 0x7 /* Osc Divider Register */ -+#define ICS_SWRST 0x8 /* DPA & PLL Reset Register */ -+#define ICS_VID 0x10 /* Chip Version Register */ -+#define ICS_RID 0x11 /* Chip Revision Register */ -+#define ICS_SR 0x12 /* Status Register */ -+ -+/*------------------------------------------------------*/ -+/* ICS1523 Input Control Register Bits Definition */ -+/*------------------------------------------------------*/ -+ -+#define ICS_PDEN 0x1 /* Phase Detector Enable */ -+#define ICS_PDPOL 0x2 /* Phase Detector Enable Polarity */ -+#define ICS_REFPOL 0x4 /* External Reference Polarity */ -+#define ICS_FBKPOL 0x8 /* External Feedback Polarity */ -+#define ICS_FBKSEL 0x10 /* External Feedback Select */ -+#define ICS_FUNCSEL 0x20 /* Function Out Select */ -+#define ICS_ENPLS 0x40 /* Enable PLL Lock/Ref Status Output */ -+#define ICS_ENDLS 0x80 /* Enable DPA Lock/Ref Status Output */ -+ -+/*-----------------------------------------------------*/ -+/* ICS1523 Loop Control Register Bits Definition */ -+/*-----------------------------------------------------*/ -+ -+#define ICS_PFD 0x7 /* Phase Detector Gain */ -+#define ICS_PSD 0x30 /* Post-Scaler Divider */ -+ -+/*----------------------------------------------------*/ -+/* ICS1523 PLL FeedBack Divider LSBs Definition */ -+/*----------------------------------------------------*/ -+ -+#define ICS_FBDL 0xFF /* PLL FeedBack Divider LSBs */ -+ -+/*----------------------------------------------------*/ -+/* ICS1523 PLL FeedBack Divider MSBs Definition */ -+/*----------------------------------------------------*/ -+ -+#define ICS_FBDM 0xF /* PLL FeedBack Divider MSBs */ -+ -+/*------------------------------------------------------------*/ -+/* ICS1523 Dynamic Phase Aligner Offset Bits Definition */ -+/*------------------------------------------------------------*/ -+ -+#define ICS_DPAOS 0x2F /* Dynamic Phase Aligner Offset */ -+#define ICS_FILSEL 0x80 /* Loop Filter Select */ -+ -+/*----------------------------------------------------------------*/ -+/* ICS1523 Dynamic Phase Aligner Resolution Bits Definition */ -+/*----------------------------------------------------------------*/ -+ -+#define ICS_DPARES 0x3 /* Dynamic Phase Aligner Resolution */ -+#define ICS_MMREV 0xFC /* Metal Mask Revision Number */ -+ -+/*-------------------------------------------------------*/ -+/* ICS1523 Output Enables Register Bits Definition */ -+/*-------------------------------------------------------*/ -+ -+#define ICS_OEPCK 0x1 /* Output Enable for PECL PCLK Outputs */ -+#define ICS_OETCK 0x2 /* Output Enable for STTL CLK Output */ -+#define ICS_OEP2 0x4 /* Output Enable for PECL CLK/2 Outputs */ -+#define ICS_OET2 0x8 /* Output Enable for STTL CLK/2 Output */ -+#define ICS_OEF 0x10 /* Output Enable for STTL FUNC Output */ -+#define ICS_CLK2INV 0x20 /* CLK/2 Invert */ -+#define ICS_OSCL 0xC0 /* SSTL Clock Scaler */ -+ -+/*----------------------------------------------------*/ -+/* ICS1523 Osc Divider Register Bits Definition */ -+/*----------------------------------------------------*/ -+ -+#define ICS_OSCDIV 0x7F /* Oscillator Divider Modulus */ -+#define ICS_INSEL 0x80 /* Input Select */ -+ -+/*---------------------------------------------------*/ -+/* ICS1523 DPA & PLL Reset Register Definition */ -+/*---------------------------------------------------*/ -+ -+#define ICS_DPAR 0x0A /* DPA Reset Command */ -+#define ICS_PLLR 0x50 /* PLL Reset Command */ -+ -+/*------------------------------------------------*/ -+/* ICS1523 Chip Version Register Definition */ -+/*------------------------------------------------*/ -+ -+#define ICS_CHIPV 0xFF /* Chip Version */ -+ -+/*-------------------------------------------------*/ -+/* ICS1523 Chip Revision Register Definition */ -+/*-------------------------------------------------*/ -+ -+#define ICS_CHIPR 0xFF /* Chip Revision */ -+ -+/*------------------------------------------*/ -+/* ICS1523 Status Register Definition */ -+/*------------------------------------------*/ -+ -+#define ICS_DPALOCK 0x1 /* DPA Lock Status */ -+#define ICS_PLLLOCK 0x2 /* PLL Lock Status */ -+ -+int at91_ics1523_init(void); -+ -+#endif /* ics1523_h */ -diff -urN -x CVS linux-2.6.22-rc1/include/asm-arm/arch-at91/spi.h linux-2.6-stable/include/asm-arm/arch-at91/spi.h ---- linux-2.6.22-rc1/include/asm-arm/arch-at91/spi.h Thu Jan 1 02:00:00 1970 -+++ linux-2.6-stable/include/asm-arm/arch-at91/spi.h Mon May 14 13:49:47 2007 -@@ -0,0 +1,54 @@ -+/* -+ * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 -+ * -+ * (c) SAN People (Pty) Ltd -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#ifndef AT91_LEGACY_SPI_H -+#define AT91_LEGACY_SPI_H -+ -+#define SPI_MAJOR 153 /* registered device number */ -+ -+#define DEFAULT_SPI_CLK 6000000 -+ -+ -+/* Maximum number of buffers in a single SPI transfer. -+ * DataFlash uses maximum of 2 -+ * spidev interface supports up to 8. -+ */ -+#define MAX_SPI_TRANSFERS 8 -+#define NR_SPI_DEVICES 4 /* number of devices on SPI bus */ -+ -+/* -+ * Describes the buffers for a SPI transfer. -+ * A transmit & receive buffer must be specified for each transfer -+ */ -+struct spi_transfer_list { -+ void* tx[MAX_SPI_TRANSFERS]; /* transmit */ -+ int txlen[MAX_SPI_TRANSFERS]; -+ void* rx[MAX_SPI_TRANSFERS]; /* receive */ -+ int rxlen[MAX_SPI_TRANSFERS]; -+ int nr_transfers; /* number of transfers */ -+ int curr; /* current transfer */ -+}; -+ -+struct spi_local { -+ unsigned int pcs; /* Peripheral Chip Select value */ -+ -+ struct spi_transfer_list *xfers; /* current transfer list */ -+ dma_addr_t tx, rx; /* DMA address for current transfer */ -+ dma_addr_t txnext, rxnext; /* DMA address for next transfer */ -+}; -+ -+ -+/* Exported functions */ -+extern void spi_access_bus(short device); -+extern void spi_release_bus(short device); -+extern int spi_transfer(struct spi_transfer_list* list); -+ -+#endif -diff -urN -x CVS linux-2.6.22-rc1/include/linux/clk.h linux-2.6-stable/include/linux/clk.h ---- linux-2.6.22-rc1/include/linux/clk.h Thu Apr 26 05:08:32 2007 -+++ linux-2.6-stable/include/linux/clk.h Tue May 8 12:13:31 2007 -@@ -121,4 +121,24 @@ - */ - struct clk *clk_get_parent(struct clk *clk); - -+/** -+ * clk_must_disable - report whether a clock's users must disable it -+ * @clk: one node in the clock tree -+ * -+ * This routine returns true only if the upcoming system state requires -+ * disabling the specified clock. -+ * -+ * It's common for platform power states to constrain certain clocks (and -+ * their descendants) to be unavailable, while other states allow that -+ * clock to be active. A platform's power states often include an "all on" -+ * mode; system wide sleep states like "standby" or "suspend-to-RAM"; and -+ * operating states which sacrifice functionality for lower power usage. -+ * -+ * The constraint value is commonly tested in device driver suspend(), to -+ * leave clocks active if they are needed for features like wakeup events. -+ * On platforms that support reduced functionality operating states, the -+ * constraint may also need to be tested during resume() and probe() calls. -+ */ -+int clk_must_disable(struct clk *clk); -+ - #endif -diff -urN -x CVS linux-2.6.22-rc1/include/linux/i2c-id.h linux-2.6-stable/include/linux/i2c-id.h ---- linux-2.6.22-rc1/include/linux/i2c-id.h Thu May 17 12:13:23 2007 -+++ linux-2.6-stable/include/linux/i2c-id.h Mon May 14 10:18:35 2007 -@@ -203,6 +203,7 @@ - - /* --- PCA 9564 based algorithms */ - #define I2C_HW_A_ISA 0x1a0000 /* generic ISA Bus interface card */ -+#define I2C_HW_A_PLAT 0x1a0001 /* generic platform_bus interface */ - - /* --- ACPI Embedded controller algorithms */ - #define I2C_HW_ACPI_EC 0x1f0000 -diff -urN -x CVS linux-2.6.22-rc1/sound/soc/at91/eti_b1_wm8731.c linux-2.6-stable/sound/soc/at91/eti_b1_wm8731.c ---- linux-2.6.22-rc1/sound/soc/at91/eti_b1_wm8731.c Thu May 17 12:13:36 2007 -+++ linux-2.6-stable/sound/soc/at91/eti_b1_wm8731.c Mon May 14 10:19:04 2007 -@@ -34,8 +34,7 @@ - #include <sound/soc.h> - #include <sound/soc-dapm.h> - --#include <asm/arch/hardware.h> --#include <asm/arch/at91_pio.h> -+#include <asm/hardware.h> - #include <asm/arch/gpio.h> - - #include "../codecs/wm8731.h" -@@ -48,13 +47,6 @@ - #define DBG(x...) - #endif - --#define AT91_PIO_TF1 (1 << (AT91_PIN_PB6 - PIN_BASE) % 32) --#define AT91_PIO_TK1 (1 << (AT91_PIN_PB7 - PIN_BASE) % 32) --#define AT91_PIO_TD1 (1 << (AT91_PIN_PB8 - PIN_BASE) % 32) --#define AT91_PIO_RD1 (1 << (AT91_PIN_PB9 - PIN_BASE) % 32) --#define AT91_PIO_RK1 (1 << (AT91_PIN_PB10 - PIN_BASE) % 32) --#define AT91_PIO_RF1 (1 << (AT91_PIN_PB11 - PIN_BASE) % 32) -- - static struct clk *pck1_clk; - static struct clk *pllb_clk; - -@@ -277,7 +269,6 @@ - static int __init eti_b1_init(void) - { - int ret; -- u32 ssc_pio_lines; - struct at91_ssc_periph *ssc = eti_b1_dai.cpu_dai->private_data; - - if (!request_mem_region(AT91RM9200_BASE_SSC1, SZ_16K, "soc-audio")) { -@@ -311,19 +302,12 @@ - goto fail_io_unmap; - } - -- ssc_pio_lines = AT91_PIO_TF1 | AT91_PIO_TK1 | AT91_PIO_TD1 -- | AT91_PIO_RD1 /* | AT91_PIO_RK1 */ | AT91_PIO_RF1; -- -- /* Reset all PIO registers and assign lines to peripheral A */ -- at91_sys_write(AT91_PIOB + PIO_PDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_ODR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_IFDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_CODR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_IDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_MDDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_PUDR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_ASR, ssc_pio_lines); -- at91_sys_write(AT91_PIOB + PIO_OWDR, ssc_pio_lines); -+ at91_set_A_periph(AT91_PIN_PB6, 0); /* TF1 */ -+ at91_set_A_periph(AT91_PIN_PB7, 0); /* TK1 */ -+ at91_set_A_periph(AT91_PIN_PB8, 0); /* TD1 */ -+ at91_set_A_periph(AT91_PIN_PB9, 0); /* RD1 */ -+/* at91_set_A_periph(AT91_PIN_PB10, 0);*/ /* RK1 */ -+ at91_set_A_periph(AT91_PIN_PB11, 0); /* RF1 */ - - /* - * Set PCK1 parent to PLLB and its rate to 12 Mhz. -diff -urN linux-2.6.22-rc5/drivers/char/at91_spi.c linux-2.6.22-rc5.new/drivers/char/at91_spi.c ---- linux-2.6.22-rc5/drivers/char/at91_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/drivers/char/at91_spi.c 2007-07-29 05:55:39.000000000 +0200 -@@ -0,0 +1,336 @@ -+/* -+ * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 (Thunder) -+ * -+ * Copyright (C) SAN People (Pty) Ltd -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include <linux/init.h> -+#include <linux/dma-mapping.h> -+#include <linux/module.h> -+#include <linux/sched.h> -+#include <linux/completion.h> -+#include <linux/interrupt.h> -+#include <linux/clk.h> -+#include <linux/platform_device.h> -+#include <linux/atmel_pdc.h> -+#include <asm/io.h> -+#include <asm/semaphore.h> -+ -+#include <asm/arch/at91_spi.h> -+#include <asm/arch/board.h> -+#include <asm/arch/spi.h> -+ -+#undef DEBUG_SPI -+ -+static struct spi_local spi_dev[NR_SPI_DEVICES]; /* state of the SPI devices */ -+static int spi_enabled = 0; -+static struct semaphore spi_lock; /* protect access to SPI bus */ -+static int current_device = -1; /* currently selected SPI device */ -+static struct clk *spi_clk; /* SPI clock */ -+static void __iomem *spi_base; /* SPI peripheral base-address */ -+ -+DECLARE_COMPLETION(transfer_complete); -+ -+ -+#define at91_spi_read(reg) __raw_readl(spi_base + (reg)) -+#define at91_spi_write(reg, val) __raw_writel((val), spi_base + (reg)) -+ -+ -+/* ......................................................................... */ -+ -+/* -+ * Access and enable the SPI bus. -+ * This MUST be called before any transfers are performed. -+ */ -+void spi_access_bus(short device) -+{ -+ /* Ensure that requested device is valid */ -+ if ((device < 0) || (device >= NR_SPI_DEVICES)) -+ panic("at91_spi: spi_access_bus called with invalid device"); -+ -+ if (spi_enabled == 0) { -+ clk_enable(spi_clk); /* Enable Peripheral clock */ -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */ -+#ifdef DEBUG_SPI -+ printk("SPI on\n"); -+#endif -+ } -+ spi_enabled++; -+ -+ /* Lock the SPI bus */ -+ down(&spi_lock); -+ current_device = device; -+ -+ /* Configure SPI bus for device */ -+ at91_spi_write(AT91_SPI_MR, AT91_SPI_MSTR | AT91_SPI_MODFDIS | (spi_dev[device].pcs << 16)); -+} -+ -+/* -+ * Relinquish control of the SPI bus. -+ */ -+void spi_release_bus(short device) -+{ -+ if (device != current_device) -+ panic("at91_spi: spi_release called with invalid device"); -+ -+ /* Release the SPI bus */ -+ current_device = -1; -+ up(&spi_lock); -+ -+ spi_enabled--; -+ if (spi_enabled == 0) { -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */ -+ clk_disable(spi_clk); /* Disable Peripheral clock */ -+#ifdef DEBUG_SPI -+ printk("SPI off\n"); -+#endif -+ } -+} -+ -+/* -+ * Perform a data transfer over the SPI bus -+ */ -+int spi_transfer(struct spi_transfer_list* list) -+{ -+ struct spi_local *device = (struct spi_local *) &spi_dev[current_device]; -+ int tx_size; -+ -+ if (!list) -+ panic("at91_spi: spi_transfer called with NULL transfer list"); -+ if (current_device == -1) -+ panic("at91_spi: spi_transfer called without acquiring bus"); -+ -+#ifdef DEBUG_SPI -+ printk("SPI transfer start [%i]\n", list->nr_transfers); -+#endif -+ -+ /* If we are in 16-bit mode, we need to modify what we pass to the PDC */ -+ tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1; -+ -+ /* Store transfer list */ -+ device->xfers = list; -+ list->curr = 0; -+ -+ /* Assume there must be at least one transfer */ -+ device->tx = dma_map_single(NULL, list->tx[0], list->txlen[0], DMA_TO_DEVICE); -+ device->rx = dma_map_single(NULL, list->rx[0], list->rxlen[0], DMA_FROM_DEVICE); -+ -+ /* Program PDC registers */ -+ at91_spi_write(ATMEL_PDC_TPR, device->tx); -+ at91_spi_write(ATMEL_PDC_RPR, device->rx); -+ at91_spi_write(ATMEL_PDC_TCR, list->txlen[0] / tx_size); -+ at91_spi_write(ATMEL_PDC_RCR, list->rxlen[0] / tx_size); -+ -+ /* Is there a second transfer? */ -+ if (list->nr_transfers > 1) { -+ device->txnext = dma_map_single(NULL, list->tx[1], list->txlen[1], DMA_TO_DEVICE); -+ device->rxnext = dma_map_single(NULL, list->rx[1], list->rxlen[1], DMA_FROM_DEVICE); -+ -+ /* Program Next PDC registers */ -+ at91_spi_write(ATMEL_PDC_TNPR, device->txnext); -+ at91_spi_write(ATMEL_PDC_RNPR, device->rxnext); -+ at91_spi_write(ATMEL_PDC_TNCR, list->txlen[1] / tx_size); -+ at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[1] / tx_size); -+ } -+ else { -+ device->txnext = 0; -+ device->rxnext = 0; -+ at91_spi_write(ATMEL_PDC_TNCR, 0); -+ at91_spi_write(ATMEL_PDC_RNCR, 0); -+ } -+ -+ // TODO: If we are doing consecutive transfers (at high speed, or -+ // small buffers), then it might be worth modifying the 'Delay between -+ // Consecutive Transfers' in the CSR registers. -+ // This is an issue if we cannot chain the next buffer fast enough -+ // in the interrupt handler. -+ -+ /* Enable transmitter and receiver */ -+ at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN | ATMEL_PDC_TXTEN); -+ -+ at91_spi_write(AT91_SPI_IER, AT91_SPI_ENDRX); /* enable buffer complete interrupt */ -+ wait_for_completion(&transfer_complete); -+ -+#ifdef DEBUG_SPI -+ printk("SPI transfer end\n"); -+#endif -+ -+ return 0; -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Handle interrupts from the SPI controller. -+ */ -+static irqreturn_t at91spi_interrupt(int irq, void *dev_id) -+{ -+ unsigned int status; -+ struct spi_local *device = (struct spi_local *) &spi_dev[current_device]; -+ struct spi_transfer_list *list = device->xfers; -+ -+#ifdef DEBUG_SPI -+ printk("SPI interrupt %i\n", current_device); -+#endif -+ -+ if (!list) -+ panic("at91_spi: spi_interrupt with a NULL transfer list"); -+ -+ status = at91_spi_read(AT91_SPI_SR) & at91_spi_read(AT91_SPI_IMR); /* read status */ -+ -+ dma_unmap_single(NULL, device->tx, list->txlen[list->curr], DMA_TO_DEVICE); -+ dma_unmap_single(NULL, device->rx, list->rxlen[list->curr], DMA_FROM_DEVICE); -+ -+ device->tx = device->txnext; /* move next transfer to current transfer */ -+ device->rx = device->rxnext; -+ -+ list->curr = list->curr + 1; -+ if (list->curr == list->nr_transfers) { /* all transfers complete */ -+ at91_spi_write(AT91_SPI_IDR, AT91_SPI_ENDRX); /* disable interrupt */ -+ -+ /* Disable transmitter and receiver */ -+ at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); -+ -+ device->xfers = NULL; -+ complete(&transfer_complete); -+ } -+ else if (list->curr+1 == list->nr_transfers) { /* no more next transfers */ -+ device->txnext = 0; -+ device->rxnext = 0; -+ at91_spi_write(ATMEL_PDC_TNCR, 0); -+ at91_spi_write(ATMEL_PDC_RNCR, 0); -+ } -+ else { -+ int i = (list->curr)+1; -+ -+ /* If we are in 16-bit mode, we need to modify what we pass to the PDC */ -+ int tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1; -+ -+ device->txnext = dma_map_single(NULL, list->tx[i], list->txlen[i], DMA_TO_DEVICE); -+ device->rxnext = dma_map_single(NULL, list->rx[i], list->rxlen[i], DMA_FROM_DEVICE); -+ at91_spi_write(ATMEL_PDC_TNPR, device->txnext); -+ at91_spi_write(ATMEL_PDC_RNPR, device->rxnext); -+ at91_spi_write(ATMEL_PDC_TNCR, list->txlen[i] / tx_size); -+ at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[i] / tx_size); -+ } -+ return IRQ_HANDLED; -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Initialize the SPI controller -+ */ -+static int __init at91spi_probe(struct platform_device *pdev) -+{ -+ int i; -+ unsigned long scbr; -+ struct resource *res; -+ -+ init_MUTEX(&spi_lock); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -ENXIO; -+ -+ if (!request_mem_region(res->start, res->end - res->start + 1, "at91_spi")) -+ return -EBUSY; -+ -+ spi_base = ioremap(res->start, res->end - res->start + 1); -+ if (!spi_base) { -+ release_mem_region(res->start, res->end - res->start + 1); -+ return -ENOMEM; -+ } -+ -+ spi_clk = clk_get(NULL, "spi_clk"); -+ if (IS_ERR(spi_clk)) { -+ printk(KERN_ERR "at91_spi: no clock defined\n"); -+ iounmap(spi_base); -+ release_mem_region(res->start, res->end - res->start + 1); -+ return -ENODEV; -+ } -+ -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SWRST); /* software reset of SPI controller */ -+ -+ /* -+ * Calculate the correct SPI baud-rate divisor. -+ */ -+ scbr = clk_get_rate(spi_clk) / (2 * DEFAULT_SPI_CLK); -+ scbr = scbr + 1; /* round up */ -+ -+ printk(KERN_INFO "at91_spi: Baud rate set to %ld\n", clk_get_rate(spi_clk) / (2 * scbr)); -+ -+ /* Set Chip Select registers to good defaults */ -+ for (i = 0; i < 4; i++) { -+ at91_spi_write(AT91_SPI_CSR(i), AT91_SPI_CPOL | AT91_SPI_BITS_8 | (16 << 16) | (scbr << 8)); -+ } -+ -+ at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); -+ -+ memset(&spi_dev, 0, sizeof(spi_dev)); -+ spi_dev[0].pcs = 0xE; -+ spi_dev[1].pcs = 0xD; -+ spi_dev[2].pcs = 0xB; -+ spi_dev[3].pcs = 0x7; -+ -+ if (request_irq(AT91RM9200_ID_SPI, at91spi_interrupt, 0, "spi", NULL)) { -+ clk_put(spi_clk); -+ iounmap(spi_base); -+ release_mem_region(res->start, res->end - res->start + 1); -+ return -EBUSY; -+ } -+ -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */ -+ -+ return 0; -+} -+ -+static int __devexit at91spi_remove(struct platform_device *pdev) -+{ -+ struct resource *res; -+ -+ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */ -+ clk_put(spi_clk); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ iounmap(spi_base); -+ release_mem_region(res->start, res->end - res->start + 1); -+ -+ free_irq(AT91RM9200_ID_SPI, 0); -+ return 0; -+} -+ -+static struct platform_driver at91spi_driver = { -+ .probe = at91spi_probe, -+ .remove = __devexit_p(at91spi_remove), -+ .driver = { -+ .name = "at91_spi", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init at91spi_init(void) -+{ -+ return platform_driver_register(&at91spi_driver); -+} -+ -+static void __exit at91spi_exit(void) -+{ -+ platform_driver_unregister(&at91spi_driver); -+} -+ -+EXPORT_SYMBOL(spi_access_bus); -+EXPORT_SYMBOL(spi_release_bus); -+EXPORT_SYMBOL(spi_transfer); -+ -+module_init(at91spi_init); -+module_exit(at91spi_exit); -+ -+MODULE_LICENSE("GPL") -+MODULE_AUTHOR("Andrew Victor") -+MODULE_DESCRIPTION("SPI driver for Atmel AT91RM9200") -diff -urN linux-2.6.22-rc5/drivers/char/at91_spidev.c linux-2.6.22-rc5.new/drivers/char/at91_spidev.c ---- linux-2.6.22-rc5/drivers/char/at91_spidev.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/drivers/char/at91_spidev.c 2007-07-29 05:55:39.000000000 +0200 -@@ -0,0 +1,236 @@ -+/* -+ * User-space interface to the SPI bus on Atmel AT91RM9200 -+ * -+ * Copyright (C) 2003 SAN People (Pty) Ltd -+ * -+ * Based on SPI driver by Rick Bronson -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/slab.h> -+#include <linux/highmem.h> -+#include <linux/pagemap.h> -+#include <asm/arch/spi.h> -+ -+#ifdef CONFIG_DEVFS_FS -+#include <linux/devfs_fs_kernel.h> -+#endif -+ -+ -+#undef DEBUG_SPIDEV -+ -+/* ......................................................................... */ -+ -+/* -+ * Read or Write to SPI bus. -+ */ -+static ssize_t spidev_rd_wr(struct file *file, char *buf, size_t count, loff_t *offset) -+{ -+ unsigned int spi_device = (unsigned int) file->private_data; -+ -+ struct mm_struct * mm; -+ struct page ** maplist; -+ struct spi_transfer_list* list; -+ int pgcount; -+ -+ unsigned int ofs, pagelen; -+ int res, i, err; -+ -+ if (!count) { -+ return 0; -+ } -+ -+ list = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL); -+ if (!list) { -+ return -ENOMEM; -+ } -+ -+ mm = current->mm; -+ -+ pgcount = ((unsigned long)buf+count+PAGE_SIZE-1)/PAGE_SIZE - (unsigned long)buf/PAGE_SIZE; -+ -+ if (pgcount >= MAX_SPI_TRANSFERS) { -+ kfree(list); -+ return -EFBIG; -+ } -+ -+ maplist = kmalloc (pgcount * sizeof (struct page *), GFP_KERNEL); -+ -+ if (!maplist) { -+ kfree(list); -+ return -ENOMEM; -+ } -+ flush_cache_all(); -+ down_read(&mm->mmap_sem); -+ err= get_user_pages(current, mm, (unsigned long)buf, pgcount, 1, 0, maplist, NULL); -+ up_read(&mm->mmap_sem); -+ -+ if (err < 0) { -+ kfree(list); -+ kfree(maplist); -+ return err; -+ } -+ pgcount = err; -+ -+#ifdef DEBUG_SPIDEV -+ printk("spidev_rd_rw: %i %i\n", count, pgcount); -+#endif -+ -+ /* Set default return value = transfer length */ -+ res = count; -+ -+ /* -+ * At this point, the virtual area buf[0] .. buf[count-1] will have -+ * corresponding pages mapped in the physical memory and locked until -+ * we unmap the kiobuf. The pages cannot be swapped out or moved -+ * around. -+ */ -+ ofs = (unsigned long) buf & (PAGE_SIZE -1); -+ pagelen = PAGE_SIZE - ofs; -+ if (count < pagelen) -+ pagelen = count; -+ -+ for (i = 0; i < pgcount; i++) { -+ flush_dcache_page(maplist[i]); -+ -+ list->tx[i] = list->rx[i] = page_address(maplist[i]) + ofs; -+ list->txlen[i] = list->rxlen[i] = pagelen; -+ -+#ifdef DEBUG_SPIDEV -+ printk(" %i: %x (%i)\n", i, list->tx[i], list->txlen[i]); -+#endif -+ -+ ofs = 0; /* all subsequent transfers start at beginning of a page */ -+ count = count - pagelen; -+ pagelen = (count < PAGE_SIZE) ? count : PAGE_SIZE; -+ } -+ list->nr_transfers = pgcount; -+ -+ /* Perform transfer on SPI bus */ -+ spi_access_bus(spi_device); -+ spi_transfer(list); -+ spi_release_bus(spi_device); -+ -+ while (pgcount--) { -+ page_cache_release (maplist[pgcount]); -+ } -+ flush_cache_all(); -+ -+ kfree(maplist); -+ kfree(list); -+ -+ return res; -+} -+ -+static int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int spi_device = MINOR(inode->i_rdev); -+ -+ if (spi_device >= NR_SPI_DEVICES) -+ return -ENODEV; -+ -+ // TODO: This interface can be used to configure the SPI bus. -+ // Configurable options could include: Speed, Clock Polarity, Clock Phase -+ -+ switch(cmd) { -+ default: -+ return -ENOIOCTLCMD; -+ } -+} -+ -+/* -+ * Open the SPI device -+ */ -+static int spidev_open(struct inode *inode, struct file *file) -+{ -+ unsigned int spi_device = MINOR(inode->i_rdev); -+ -+ if (spi_device >= NR_SPI_DEVICES) -+ return -ENODEV; -+ -+ /* -+ * 'private_data' is actually a pointer, but we overload it with the -+ * value we want to store. -+ */ -+ file->private_data = (void *)spi_device; -+ -+ return 0; -+} -+ -+/* -+ * Close the SPI device -+ */ -+static int spidev_close(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+/* ......................................................................... */ -+ -+static struct file_operations spidev_fops = { -+ .owner = THIS_MODULE, -+ .llseek = no_llseek, -+ .read = spidev_rd_wr, -+ .write = (int (*) (struct file *file, const char *buf, size_t count, loff_t *offset))spidev_rd_wr, -+ .ioctl = spidev_ioctl, -+ .open = spidev_open, -+ .release = spidev_close, -+}; -+ -+/* -+ * Install the SPI /dev interface driver -+ */ -+static int __init at91_spidev_init(void) -+{ -+#ifdef CONFIG_DEVFS_FS -+ int i; -+#endif -+ -+ if (register_chrdev(SPI_MAJOR, "spi", &spidev_fops)) { -+ printk(KERN_ERR "at91_spidev: Unable to get major %d for SPI bus\n", SPI_MAJOR); -+ return -EIO; -+ } -+ -+#ifdef CONFIG_DEVFS_FS -+ devfs_mk_dir("spi"); -+ for (i = 0; i < NR_SPI_DEVICES; i++) { -+ devfs_mk_cdev(MKDEV(SPI_MAJOR, i), S_IFCHR | S_IRUSR | S_IWUSR, "spi/%d",i); -+ } -+#endif -+ printk(KERN_INFO "AT91 SPI driver loaded\n"); -+ -+ return 0; -+} -+ -+/* -+ * Remove the SPI /dev interface driver -+ */ -+static void __exit at91_spidev_exit(void) -+{ -+#ifdef CONFIG_DEVFS_FS -+ int i; -+ for (i = 0; i < NR_SPI_DEVICES; i++) { -+ devfs_remove("spi/%d", i); -+ } -+ -+ devfs_remove("spi"); -+#endif -+ -+ if (unregister_chrdev(SPI_MAJOR, "spi")) { -+ printk(KERN_ERR "at91_spidev: Unable to release major %d for SPI bus\n", SPI_MAJOR); -+ return; -+ } -+} -+ -+module_init(at91_spidev_init); -+module_exit(at91_spidev_exit); -+ -+MODULE_LICENSE("GPL") -+MODULE_AUTHOR("Andrew Victor") -+MODULE_DESCRIPTION("SPI /dev interface for Atmel AT91RM9200") -diff -urN linux-2.6.22-rc5/drivers/char/Kconfig linux-2.6.22-rc5.new/drivers/char/Kconfig ---- linux-2.6.22-rc5/drivers/char/Kconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/char/Kconfig 2007-07-29 05:55:39.000000000 +0200 -@@ -1083,5 +1083,21 @@ - - source "drivers/s390/char/Kconfig" - -+config AT91_SPI -+ bool "SPI driver (legacy) for AT91RM9200 processors" -+ depends on ARCH_AT91RM9200 -+ default y -+ help -+ The SPI driver gives access to this serial bus on the AT91RM9200 -+ processor. -+ -+config AT91_SPIDEV -+ bool "SPI device interface (legacy) for AT91RM9200 processors" -+ depends on ARCH_AT91RM9200 && AT91_SPI -+ default n -+ help -+ The SPI driver gives user mode access to this serial -+ bus on the AT91RM9200 processor. -+ - endmenu - -diff -urN linux-2.6.22-rc5/drivers/char/Makefile linux-2.6.22-rc5.new/drivers/char/Makefile ---- linux-2.6.22-rc5/drivers/char/Makefile 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/char/Makefile 2007-07-29 05:55:39.000000000 +0200 -@@ -93,6 +93,8 @@ - obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o - obj-$(CONFIG_GPIO_TB0219) += tb0219.o - obj-$(CONFIG_TELCLOCK) += tlclk.o -+obj-$(CONFIG_AT91_SPI) += at91_spi.o -+obj-$(CONFIG_AT91_SPIDEV) += at91_spidev.o - - obj-$(CONFIG_WATCHDOG) += watchdog/ - obj-$(CONFIG_MWAVE) += mwave/ -diff -urN linux-2.6.22-rc5/drivers/i2c/busses/i2c-at91.c linux-2.6.22-rc5.new/drivers/i2c/busses/i2c-at91.c ---- linux-2.6.22-rc5/drivers/i2c/busses/i2c-at91.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/i2c/busses/i2c-at91.c 2007-07-29 05:55:39.000000000 +0200 -@@ -31,8 +31,11 @@ - #include <asm/arch/board.h> - #include <asm/arch/cpu.h> - --#define TWI_CLOCK 100000 /* Hz. max 400 Kbits/sec */ - -+/* Clockrate is configurable - max 400 Kbits/sec */ -+static unsigned int clockrate = CONFIG_I2C_AT91_CLOCKRATE; -+module_param(clockrate, uint, 0); -+MODULE_PARM_DESC(clockrate, "The TWI clockrate"); - - static struct clk *twi_clk; - static void __iomem *twi_base; -@@ -53,7 +56,7 @@ - at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN); /* Set Master mode */ - - /* Calcuate clock dividers */ -- cdiv = (clk_get_rate(twi_clk) / (2 * TWI_CLOCK)) - 3; -+ cdiv = (clk_get_rate(twi_clk) / (2 * clockrate)) - 3; - cdiv = cdiv + 1; /* round up */ - ckdiv = 0; - while (cdiv > 255) { -@@ -61,11 +64,12 @@ - cdiv = cdiv >> 1; - } - -- if (cpu_is_at91rm9200()) { /* AT91RM9200 Errata #22 */ -- if (ckdiv > 5) { -- printk(KERN_ERR "AT91 I2C: Invalid TWI_CLOCK value!\n"); -- ckdiv = 5; -- } -+ if (cpu_is_at91rm9200() && (ckdiv > 5)) { /* AT91RM9200 Errata #22 */ -+ printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n"); -+ ckdiv = 5; -+ } else if (ckdiv > 7) { -+ printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n"); -+ ckdiv = 7; - } - - at91_twi_write(AT91_TWI_CWGR, (ckdiv << 16) | (cdiv << 8) | cdiv); -diff -urN linux-2.6.22-rc5/drivers/i2c/busses/i2c-pca.c linux-2.6.22-rc5.new/drivers/i2c/busses/i2c-pca.c ---- linux-2.6.22-rc5/drivers/i2c/busses/i2c-pca.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/drivers/i2c/busses/i2c-pca.c 2007-07-29 05:55:39.000000000 +0200 -@@ -0,0 +1,213 @@ -+/* -+ * Platform driver for PCA9564 I2C bus controller. -+ * -+ * (C) 2006 Andrew Victor -+ * -+ * Based on i2c-pca-isa.c driver for PCA9564 on ISA boards -+ * Copyright (C) 2004 Arcom Control Systems -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/moduleparam.h> -+#include <linux/delay.h> -+#include <linux/init.h> -+#include <linux/interrupt.h> -+#include <linux/wait.h> -+#include <linux/platform_device.h> -+ -+#include <linux/i2c.h> -+#include <linux/i2c-algo-pca.h> -+ -+#include <asm/io.h> -+ -+#include "../algos/i2c-algo-pca.h" -+ -+#define PCA_OWN_ADDRESS 0x55 /* our address for slave mode */ -+#define PCA_CLOCK I2C_PCA_CON_59kHz -+ -+//#define REG_SHIFT 2 -+#define REG_SHIFT 0 -+ -+//#define DEBUG_IO -+ -+#define PCA_IO_SIZE 4 -+ -+static void __iomem *base_addr; -+static int irq; -+static wait_queue_head_t pca_wait; -+ -+static int pca_getown(struct i2c_algo_pca_data *adap) -+{ -+ return PCA_OWN_ADDRESS; -+} -+ -+static int pca_getclock(struct i2c_algo_pca_data *adap) -+{ -+ return PCA_CLOCK; -+} -+ -+static void pca_writebyte(struct i2c_algo_pca_data *adap, int reg, int val) -+{ -+#ifdef DEBUG_IO -+ static char *names[] = { "T/O", "DAT", "ADR", "CON" }; -+ printk("*** write %s at %#lx <= %#04x\n", names[reg], (unsigned long) base_addr+reg, val); -+#endif -+ udelay(1); -+ outb(val, base_addr + (reg << REG_SHIFT)); -+} -+ -+static int pca_readbyte(struct i2c_algo_pca_data *adap, int reg) -+{ -+ int res; -+ -+ udelay(1); -+ res = inb(base_addr + (reg << REG_SHIFT)); -+#ifdef DEBUG_IO -+ { -+ static char *names[] = { "STA", "DAT", "ADR", "CON" }; -+ printk("*** read %s => %#04x\n", names[reg], res); -+ } -+#endif -+ return res; -+} -+ -+static int pca_waitforinterrupt(struct i2c_algo_pca_data *adap) -+{ -+ int ret = 0; -+ -+ if (irq > -1) { -+ ret = wait_event_interruptible(pca_wait, -+ pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI); -+ } else { -+ while ((pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0) -+ udelay(100); -+ } -+ return ret; -+} -+ -+static irqreturn_t pca_handler(int this_irq, void *dev_id) -+{ -+ wake_up_interruptible(&pca_wait); -+ return IRQ_HANDLED; -+} -+ -+static struct i2c_algo_pca_data pca_i2c_data = { -+ .get_own = pca_getown, -+ .get_clock = pca_getclock, -+ .write_byte = pca_writebyte, -+ .read_byte = pca_readbyte, -+ .wait_for_interrupt = pca_waitforinterrupt, -+}; -+ -+static struct i2c_adapter pca_i2c_ops = { -+ .owner = THIS_MODULE, -+ .id = I2C_HW_A_PLAT, -+ .algo_data = &pca_i2c_data, -+ .name = "PCA9564", -+ .class = I2C_CLASS_HWMON, -+}; -+ -+static int __devinit pca_i2c_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ -+ init_waitqueue_head(&pca_wait); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -ENODEV; -+ -+ if (!request_mem_region(res->start, PCA_IO_SIZE, "PCA9564")) -+ return -ENXIO; -+ -+ base_addr = ioremap(res->start, PCA_IO_SIZE); -+ if (base_addr == NULL) -+ goto out_region; -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq > -1) { -+ if (request_irq(irq, pca_handler, 0, "pca9564", NULL) < 0) { -+ printk(KERN_ERR "i2c-pca: Request irq%d failed\n", irq); -+ goto out_remap; -+ } -+ } -+ -+ /* set up the driverfs linkage to our parent device */ -+ pca_i2c_ops.dev.parent = &pdev->dev; -+ -+ if (i2c_pca_add_bus(&pca_i2c_ops) < 0) { -+ printk(KERN_ERR "i2c-pca: Failed to add i2c bus\n"); -+ goto out_irq; -+ } -+ -+ return 0; -+ -+ out_irq: -+ if (irq > -1) -+ free_irq(irq, &pca_i2c_ops); -+ -+ out_remap: -+ iounmap(base_addr); -+ -+ out_region: -+ release_mem_region(res->start, PCA_IO_SIZE); -+ return -ENODEV; -+} -+ -+static int __devexit pca_i2c_remove(struct platform_device *pdev) -+{ -+ struct resource *res; -+ -+ i2c_del_adapter(&pca_i2c_ops); -+ -+ if (irq > 0) -+ free_irq(irq, NULL); -+ -+ iounmap(base_addr); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ release_mem_region(res->start, PCA_IO_SIZE); -+ -+ return 0; -+} -+ -+static struct platform_driver pca_i2c_driver = { -+ .probe = pca_i2c_probe, -+ .remove = __devexit_p(pca_i2c_remove), -+ .driver = { -+ .name = "pca9564", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init pca_i2c_init(void) -+{ -+ return platform_driver_register(&pca_i2c_driver); -+} -+ -+static void __exit pca_i2c_exit(void) -+{ -+ platform_driver_unregister(&pca_i2c_driver); -+} -+ -+module_init(pca_i2c_init); -+module_exit(pca_i2c_exit); -+ -+MODULE_AUTHOR("Andrew Victor"); -+MODULE_DESCRIPTION("PCA9564 platform driver"); -+MODULE_LICENSE("GPL"); -diff -urN linux-2.6.22-rc5/drivers/i2c/busses/Kconfig linux-2.6.22-rc5.new/drivers/i2c/busses/Kconfig ---- linux-2.6.22-rc5/drivers/i2c/busses/Kconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/i2c/busses/Kconfig 2007-07-29 05:55:39.000000000 +0200 -@@ -80,6 +80,14 @@ - This supports the use of the I2C interface on Atmel AT91 - processors. - -+config I2C_AT91_CLOCKRATE -+ prompt "Atmel AT91 I2C/TWI clock-rate" -+ depends on I2C_AT91 -+ int -+ default 100000 -+ help -+ Set the AT91 I2C/TWI clock-rate. -+ - config I2C_AU1550 - tristate "Au1550/Au1200 SMBus interface" - depends on SOC_AU1550 || SOC_AU1200 -@@ -598,6 +606,14 @@ - This driver can also be built as a module. If so, the module - will be called i2c-voodoo3. - -+config I2C_PCA -+ tristate "PCA9564" -+ depends on I2C -+ select I2C_ALGOPCA -+ help -+ This driver support the Philips PCA 9564 Parallel bus to I2C -+ bus controller. -+ - config I2C_PCA_ISA - tristate "PCA9564 on an ISA bus" - depends on ISA -diff -urN linux-2.6.22-rc5/drivers/i2c/busses/Makefile linux-2.6.22-rc5.new/drivers/i2c/busses/Makefile ---- linux-2.6.22-rc5/drivers/i2c/busses/Makefile 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/i2c/busses/Makefile 2007-07-29 05:55:39.000000000 +0200 -@@ -30,6 +30,7 @@ - obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o - obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o - obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o -+obj-$(CONFIG_I2C_PCA) += i2c-pca.o - obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o - obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o - obj-$(CONFIG_I2C_PNX) += i2c-pnx.o -diff -urN linux-2.6.22-rc5/drivers/leds/Kconfig linux-2.6.22-rc5.new/drivers/leds/Kconfig ---- linux-2.6.22-rc5/drivers/leds/Kconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/leds/Kconfig 2007-07-29 05:55:39.000000000 +0200 -@@ -77,6 +77,13 @@ - This option enables support for the Soekris net4801 and net4826 error - LED. - -+config LEDS_AT91 -+ tristate "LED support using AT91 GPIOs" -+ depends on LEDS_CLASS && ARCH_AT91 && !LEDS -+ help -+ This option enables support for LEDs connected to GPIO lines -+ on AT91-based boards. -+ - config LEDS_WRAP - tristate "LED Support for the WRAP series LEDs" - depends on LEDS_CLASS && SCx200_GPIO -diff -urN linux-2.6.22-rc5/drivers/leds/leds-at91.c linux-2.6.22-rc5.new/drivers/leds/leds-at91.c ---- linux-2.6.22-rc5/drivers/leds/leds-at91.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/drivers/leds/leds-at91.c 2007-07-29 05:55:39.000000000 +0200 -@@ -0,0 +1,140 @@ -+/* -+ * AT91 GPIO based LED driver -+ * -+ * Copyright (C) 2006 David Brownell -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/init.h> -+#include <linux/platform_device.h> -+#include <linux/leds.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+ -+static LIST_HEAD(at91_led_list); /* list of AT91 LEDs */ -+ -+struct at91_led { -+ struct led_classdev cdev; -+ struct list_head list; -+ struct at91_gpio_led *led_data; -+}; -+ -+/* -+ * Change the state of the LED. -+ */ -+static void at91_led_set(struct led_classdev *cdev, enum led_brightness value) -+{ -+ struct at91_led *led = container_of(cdev, struct at91_led, cdev); -+ short active = (value == LED_OFF); -+ -+ if (led->led_data->flags & 1) /* active high/low? */ -+ active = !active; -+ at91_set_gpio_value(led->led_data->gpio, active); -+} -+ -+static int __devexit at91_led_remove(struct platform_device *pdev) -+{ -+ struct at91_led *led; -+ -+ list_for_each_entry (led, &at91_led_list, list) -+ led_classdev_unregister(&led->cdev); -+ -+#warning "Free allocated memory" -+ // TODO: Free memory. kfree(led); -+ -+ return 0; -+} -+ -+static int __init at91_led_probe(struct platform_device *pdev) -+{ -+ int status = 0; -+ struct at91_gpio_led *pdata = pdev->dev.platform_data; -+ unsigned nr_leds; -+ struct at91_led *led; -+ -+ if (!pdata) -+ return -ENODEV; -+ -+ nr_leds = pdata->index; /* first index stores number of LEDs */ -+ -+ while (nr_leds--) { -+ led = kzalloc(sizeof(struct at91_led), GFP_KERNEL); -+ if (!led) { -+ dev_err(&pdev->dev, "No memory for device\n"); -+ status = -ENOMEM; -+ goto cleanup; -+ } -+ led->led_data = pdata; -+ led->cdev.name = pdata->name; -+ led->cdev.brightness_set = at91_led_set, -+ led->cdev.default_trigger = pdata->trigger; -+ -+ status = led_classdev_register(&pdev->dev, &led->cdev); -+ if (status < 0) { -+ dev_err(&pdev->dev, "led_classdev_register failed - %d\n", status); -+cleanup: -+ at91_led_remove(pdev); -+ break; -+ } -+ list_add(&led->list, &at91_led_list); -+ pdata++; -+ } -+ return status; -+} -+ -+#ifdef CONFIG_PM -+static int at91_led_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ struct at91_led *led; -+ -+ list_for_each_entry (led, &at91_led_list, list) -+ led_classdev_suspend(&led->cdev); -+ -+ return 0; -+} -+ -+static int at91_led_resume(struct platform_device *dev) -+{ -+ struct at91_led *led; -+ -+ list_for_each_entry (led, &at91_led_list, list) -+ led_classdev_resume(&led->cdev); -+ -+ return 0; -+} -+#else -+#define at91_led_suspend NULL -+#define at91_led_resume NULL -+#endif -+ -+static struct platform_driver at91_led_driver = { -+ .probe = at91_led_probe, -+ .remove = __devexit_p(at91_led_remove), -+ .suspend = at91_led_suspend, -+ .resume = at91_led_resume, -+ .driver = { -+ .name = "at91_leds", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init at91_led_init(void) -+{ -+ return platform_driver_register(&at91_led_driver); -+} -+module_init(at91_led_init); -+ -+static void __exit at91_led_exit(void) -+{ -+ platform_driver_unregister(&at91_led_driver); -+} -+module_exit(at91_led_exit); -+ -+MODULE_DESCRIPTION("AT91 GPIO LED driver"); -+MODULE_AUTHOR("David Brownell"); -+MODULE_LICENSE("GPL"); -diff -urN linux-2.6.22-rc5/drivers/leds/Makefile linux-2.6.22-rc5.new/drivers/leds/Makefile ---- linux-2.6.22-rc5/drivers/leds/Makefile 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/leds/Makefile 2007-07-29 05:55:39.000000000 +0200 -@@ -16,6 +16,7 @@ - obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o - obj-$(CONFIG_LEDS_H1940) += leds-h1940.o - obj-$(CONFIG_LEDS_COBALT) += leds-cobalt.o -+obj-$(CONFIG_LEDS_AT91) += leds-at91.o - - # LED Triggers - obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o -diff -urN linux-2.6.22-rc5/drivers/mmc/host/at91_mci.c linux-2.6.22-rc5.new/drivers/mmc/host/at91_mci.c ---- linux-2.6.22-rc5/drivers/mmc/host/at91_mci.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/mmc/host/at91_mci.c 2007-07-29 05:57:56.000000000 +0200 -@@ -85,7 +85,7 @@ - - #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ - | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ -- | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) -+ | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) - - #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) - #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) -@@ -560,9 +560,7 @@ - pr_debug("Status = %08X [%08X %08X %08X %08X]\n", - status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - -- if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE | -- AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE | -- AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) { -+ if (status & AT91_MCI_ERRORS) { - if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { - cmd->error = MMC_ERR_NONE; - } -@@ -663,15 +661,15 @@ - - int_status = at91_mci_read(host, AT91_MCI_SR); - int_mask = at91_mci_read(host, AT91_MCI_IMR); -- -+ - pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, - int_status & int_mask); -- -+ - int_status = int_status & int_mask; - - if (int_status & AT91_MCI_ERRORS) { - completed = 1; -- -+ - if (int_status & AT91_MCI_UNRE) - pr_debug("MMC: Underrun error\n"); - if (int_status & AT91_MCI_OVRE) -@@ -819,7 +817,7 @@ - mmc->f_min = 375000; - mmc->f_max = 25000000; - mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; -- mmc->caps = MMC_CAP_BYTEBLOCK; -+ mmc->caps = MMC_CAP_BYTEBLOCK | MMC_CAP_MULTIWRITE; - - mmc->max_blk_size = 4095; - mmc->max_blk_count = mmc->max_req_size; -@@ -893,6 +891,8 @@ - - mmc_add_host(mmc); - -+ device_init_wakeup(&pdev->dev, 1); -+ - /* - * monitor card insertion/removal if we can - */ -@@ -922,6 +922,8 @@ - - host = mmc_priv(mmc); - -+ device_init_wakeup(&pdev->dev, 0); -+ - if (host->present != -1) { - free_irq(host->board->det_pin, host); - cancel_delayed_work(&host->mmc->detect); -@@ -949,8 +951,12 @@ - static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) - { - struct mmc_host *mmc = platform_get_drvdata(pdev); -+ struct at91mci_host *host = mmc_priv(mmc); - int ret = 0; - -+ if (device_may_wakeup(&pdev->dev)) -+ enable_irq_wake(host->board->det_pin); -+ - if (mmc) - ret = mmc_suspend_host(mmc, state); - -@@ -960,8 +966,12 @@ - static int at91_mci_resume(struct platform_device *pdev) - { - struct mmc_host *mmc = platform_get_drvdata(pdev); -+ struct at91mci_host *host = mmc_priv(mmc); - int ret = 0; - -+ if (device_may_wakeup(&pdev->dev)) -+ disable_irq_wake(host->board->det_pin); -+ - if (mmc) - ret = mmc_resume_host(mmc); - -diff -urN linux-2.6.22-rc5/drivers/mtd/devices/at91_dataflash.c linux-2.6.22-rc5.new/drivers/mtd/devices/at91_dataflash.c ---- linux-2.6.22-rc5/drivers/mtd/devices/at91_dataflash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/drivers/mtd/devices/at91_dataflash.c 2007-07-29 05:55:39.000000000 +0200 -@@ -0,0 +1,667 @@ -+/* -+ * Atmel DataFlash driver for Atmel AT91RM9200 (Thunder) -+ * -+ * Copyright (C) SAN People (Pty) Ltd -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+*/ -+ -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/slab.h> -+#include <linux/pci.h> -+#include <linux/mtd/mtd.h> -+#include <linux/mtd/partitions.h> -+ -+#include <asm/arch/spi.h> -+ -+#undef DEBUG_DATAFLASH -+ -+#define DATAFLASH_MAX_DEVICES 4 /* max number of dataflash devices */ -+#undef DATAFLASH_ALWAYS_ADD_DEVICE /* always add whole device when using partitions? */ -+ -+#define OP_READ_CONTINUOUS 0xE8 -+#define OP_READ_PAGE 0xD2 -+#define OP_READ_BUFFER1 0xD4 -+#define OP_READ_BUFFER2 0xD6 -+#define OP_READ_STATUS 0xD7 -+ -+#define OP_ERASE_PAGE 0x81 -+#define OP_ERASE_BLOCK 0x50 -+ -+#define OP_TRANSFER_BUF1 0x53 -+#define OP_TRANSFER_BUF2 0x55 -+#define OP_COMPARE_BUF1 0x60 -+#define OP_COMPARE_BUF2 0x61 -+ -+#define OP_PROGRAM_VIA_BUF1 0x82 -+#define OP_PROGRAM_VIA_BUF2 0x85 -+ -+struct dataflash_local -+{ -+ int spi; /* SPI chip-select number */ -+ -+ unsigned int page_size; /* number of bytes per page */ -+ unsigned short page_offset; /* page offset in flash address */ -+}; -+ -+ -+/* Detected DataFlash devices */ -+static struct mtd_info* mtd_devices[DATAFLASH_MAX_DEVICES]; -+static int nr_devices = 0; -+ -+/* ......................................................................... */ -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ -+static struct mtd_partition static_partitions_2M[] = -+{ -+ { -+ .name = "bootloader", -+ .offset = 0, -+ .size = 1 * 32 * 8 * 528, /* 1st sector = 32 blocks * 8 pages * 528 bytes */ -+ .mask_flags = MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 6 * 32 * 8 * 528, /* 6 sectors */ -+ }, -+ { -+ .name = "filesystem", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, /* rest = 9 sectors */ -+ } -+}; -+ -+static struct mtd_partition static_partitions_4M[] = -+{ -+ { -+ .name = "bootloader", -+ .offset = 0, -+ .size = 1 * 64 * 8 * 528, /* 1st sector = 64 blocks * 8 pages * 528 bytes */ -+ .mask_flags = MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 4 * 64 * 8 * 528, /* 4 sectors */ -+ }, -+ { -+ .name = "filesystem", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, /* rest = 11 sectors */ -+ } -+}; -+ -+#if defined(CONFIG_MACH_KAFA) -+static struct mtd_partition static_partitions_8M[] = -+{ -+ { -+ name: "romboot", -+ offset: 0, -+ size: 16 * 1056, /* 160 Kb */ -+ mask_flags: MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ name: "uboot", -+ offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */ -+ size: 128 * 1056, /* 1 MB */ -+ }, -+ { -+ name: "kernel", -+ offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */ -+ size: 1024 * 1056, /* 1 MB */ -+ }, -+ { -+ name: "filesystem", -+ offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */ -+ size: MTDPART_SIZ_FULL, -+ } -+}; -+ -+#elif defined(CONFIG_MACH_MULTMDP) -+ -+static struct mtd_partition static_partitions_8M[] = -+{ -+ { -+ .name = "bootloader", -+ .offset = 0, -+ .size = 12 * 1056, /* 1st sector = 32 blocks * 8 pages * 1056 bytes */ -+ .mask_flags = MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ .name = "configuration", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 20 * 1056, -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 1520 * 1056, -+ }, -+ { -+ .name = "filesystem", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ } -+}; -+ -+#else -+ -+static struct mtd_partition static_partitions_8M[] = -+{ -+ { -+ .name = "bootloader", -+ .offset = 0, -+ .size = 1 * 32 * 8 * 1056, /* 1st sector = 32 blocks * 8 pages * 1056 bytes */ -+ .mask_flags = MTD_WRITEABLE, /* read-only */ -+ }, -+ { -+ .name = "kernel", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 5 * 32 * 8 * 1056, /* 5 sectors */ -+ }, -+ { -+ .name = "filesystem", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, /* rest = 26 sectors */ -+ } -+}; -+#endif -+ -+static const char *part_probes[] = { "cmdlinepart", NULL, }; -+ -+#endif -+ -+/* ......................................................................... */ -+ -+/* Allocate a single SPI transfer descriptor. We're assuming that if multiple -+ SPI transfers occur at the same time, spi_access_bus() will serialize them. -+ If this is not valid, then either (i) each dataflash 'priv' structure -+ needs it's own transfer descriptor, (ii) we lock this one, or (iii) use -+ another mechanism. */ -+static struct spi_transfer_list* spi_transfer_desc; -+ -+/* -+ * Perform a SPI transfer to access the DataFlash device. -+ */ -+static int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len, -+ char* txnext, int txnext_len, char* rxnext, int rxnext_len) -+{ -+ struct spi_transfer_list* list = spi_transfer_desc; -+ -+ list->tx[0] = tx; list->txlen[0] = tx_len; -+ list->rx[0] = rx; list->rxlen[0] = rx_len; -+ -+ list->tx[1] = txnext; list->txlen[1] = txnext_len; -+ list->rx[1] = rxnext; list->rxlen[1] = rxnext_len; -+ -+ list->nr_transfers = nr; -+ -+ return spi_transfer(list); -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Poll the DataFlash device until it is READY. -+ */ -+static void at91_dataflash_waitready(void) -+{ -+ char* command = kmalloc(2, GFP_KERNEL); -+ -+ if (!command) -+ return; -+ -+ do { -+ command[0] = OP_READ_STATUS; -+ command[1] = 0; -+ -+ do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0); -+ } while ((command[1] & 0x80) == 0); -+ -+ kfree(command); -+} -+ -+/* -+ * Return the status of the DataFlash device. -+ */ -+static unsigned short at91_dataflash_status(void) -+{ -+ unsigned short status; -+ char* command = kmalloc(2, GFP_KERNEL); -+ -+ if (!command) -+ return 0; -+ -+ command[0] = OP_READ_STATUS; -+ command[1] = 0; -+ -+ do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0); -+ status = command[1]; -+ -+ kfree(command); -+ return status; -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Erase blocks of flash. -+ */ -+static int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) -+{ -+ struct dataflash_local *priv = (struct dataflash_local *) mtd->priv; -+ unsigned int pageaddr; -+ char* command; -+ -+#ifdef DEBUG_DATAFLASH -+ printk("dataflash_erase: addr=%i len=%i\n", instr->addr, instr->len); -+#endif -+ -+ /* Sanity checks */ -+ if (instr->addr + instr->len > mtd->size) -+ return -EINVAL; -+ if ((instr->len % mtd->erasesize != 0) || (instr->len % priv->page_size != 0)) -+ return -EINVAL; -+ if ((instr->addr % priv->page_size) != 0) -+ return -EINVAL; -+ -+ command = kmalloc(4, GFP_KERNEL); -+ if (!command) -+ return -ENOMEM; -+ -+ while (instr->len > 0) { -+ /* Calculate flash page address */ -+ pageaddr = (instr->addr / priv->page_size) << priv->page_offset; -+ -+ command[0] = OP_ERASE_PAGE; -+ command[1] = (pageaddr & 0x00FF0000) >> 16; -+ command[2] = (pageaddr & 0x0000FF00) >> 8; -+ command[3] = 0; -+#ifdef DEBUG_DATAFLASH -+ printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr); -+#endif -+ -+ /* Send command to SPI device */ -+ spi_access_bus(priv->spi); -+ do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0); -+ -+ at91_dataflash_waitready(); /* poll status until ready */ -+ spi_release_bus(priv->spi); -+ -+ instr->addr += priv->page_size; /* next page */ -+ instr->len -= priv->page_size; -+ } -+ -+ kfree(command); -+ -+ /* Inform MTD subsystem that erase is complete */ -+ instr->state = MTD_ERASE_DONE; -+ if (instr->callback) -+ instr->callback(instr); -+ -+ return 0; -+} -+ -+/* -+ * Read from the DataFlash device. -+ * from : Start offset in flash device -+ * len : Amount to read -+ * retlen : About of data actually read -+ * buf : Buffer containing the data -+ */ -+static int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) -+{ -+ struct dataflash_local *priv = (struct dataflash_local *) mtd->priv; -+ unsigned int addr; -+ char* command; -+ -+#ifdef DEBUG_DATAFLASH -+ printk("dataflash_read: %lli .. %lli\n", from, from+len); -+#endif -+ -+ *retlen = 0; -+ -+ /* Sanity checks */ -+ if (!len) -+ return 0; -+ if (from + len > mtd->size) -+ return -EINVAL; -+ -+ /* Calculate flash page/byte address */ -+ addr = (((unsigned)from / priv->page_size) << priv->page_offset) + ((unsigned)from % priv->page_size); -+ -+ command = kmalloc(8, GFP_KERNEL); -+ if (!command) -+ return -ENOMEM; -+ -+ command[0] = OP_READ_CONTINUOUS; -+ command[1] = (addr & 0x00FF0000) >> 16; -+ command[2] = (addr & 0x0000FF00) >> 8; -+ command[3] = (addr & 0x000000FF); -+#ifdef DEBUG_DATAFLASH -+ printk("READ: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); -+#endif -+ -+ /* Send command to SPI device */ -+ spi_access_bus(priv->spi); -+ do_spi_transfer(2, command, 8, command, 8, buf, len, buf, len); -+ spi_release_bus(priv->spi); -+ -+ *retlen = len; -+ kfree(command); -+ return 0; -+} -+ -+/* -+ * Write to the DataFlash device. -+ * to : Start offset in flash device -+ * len : Amount to write -+ * retlen : Amount of data actually written -+ * buf : Buffer containing the data -+ */ -+static int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) -+{ -+ struct dataflash_local *priv = (struct dataflash_local *) mtd->priv; -+ unsigned int pageaddr, addr, offset, writelen; -+ size_t remaining; -+ u_char *writebuf; -+ unsigned short status; -+ int res = 0; -+ char* command; -+ char* tmpbuf = NULL; -+ -+#ifdef DEBUG_DATAFLASH -+ printk("dataflash_write: %lli .. %lli\n", to, to+len); -+#endif -+ -+ *retlen = 0; -+ -+ /* Sanity checks */ -+ if (!len) -+ return 0; -+ if (to + len > mtd->size) -+ return -EINVAL; -+ -+ command = kmalloc(4, GFP_KERNEL); -+ if (!command) -+ return -ENOMEM; -+ -+ pageaddr = ((unsigned)to / priv->page_size); -+ offset = ((unsigned)to % priv->page_size); -+ if (offset + len > priv->page_size) -+ writelen = priv->page_size - offset; -+ else -+ writelen = len; -+ writebuf = (u_char *)buf; -+ remaining = len; -+ -+ /* Allocate temporary buffer */ -+ tmpbuf = kmalloc(priv->page_size, GFP_KERNEL); -+ if (!tmpbuf) { -+ kfree(command); -+ return -ENOMEM; -+ } -+ -+ /* Gain access to the SPI bus */ -+ spi_access_bus(priv->spi); -+ -+ while (remaining > 0) { -+#ifdef DEBUG_DATAFLASH -+ printk("write @ %i:%i len=%i\n", pageaddr, offset, writelen); -+#endif -+ -+ /* (1) Transfer to Buffer1 */ -+ if (writelen != priv->page_size) { -+ addr = pageaddr << priv->page_offset; -+ command[0] = OP_TRANSFER_BUF1; -+ command[1] = (addr & 0x00FF0000) >> 16; -+ command[2] = (addr & 0x0000FF00) >> 8; -+ command[3] = 0; -+#ifdef DEBUG_DATAFLASH -+ printk("TRANSFER: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); -+#endif -+ do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0); -+ at91_dataflash_waitready(); -+ } -+ -+ /* (2) Program via Buffer1 */ -+ addr = (pageaddr << priv->page_offset) + offset; -+ command[0] = OP_PROGRAM_VIA_BUF1; -+ command[1] = (addr & 0x00FF0000) >> 16; -+ command[2] = (addr & 0x0000FF00) >> 8; -+ command[3] = (addr & 0x000000FF); -+#ifdef DEBUG_DATAFLASH -+ printk("PROGRAM: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); -+#endif -+ do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, tmpbuf, writelen); -+ at91_dataflash_waitready(); -+ -+ /* (3) Compare to Buffer1 */ -+ addr = pageaddr << priv->page_offset; -+ command[0] = OP_COMPARE_BUF1; -+ command[1] = (addr & 0x00FF0000) >> 16; -+ command[2] = (addr & 0x0000FF00) >> 8; -+ command[3] = 0; -+#ifdef DEBUG_DATAFLASH -+ printk("COMPARE: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); -+#endif -+ do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0); -+ at91_dataflash_waitready(); -+ -+ /* Get result of the compare operation */ -+ status = at91_dataflash_status(); -+ if ((status & 0x40) == 1) { -+ printk("at91_dataflash: Write error on page %i\n", pageaddr); -+ remaining = 0; -+ res = -EIO; -+ } -+ -+ remaining = remaining - writelen; -+ pageaddr++; -+ offset = 0; -+ writebuf += writelen; -+ *retlen += writelen; -+ -+ if (remaining > priv->page_size) -+ writelen = priv->page_size; -+ else -+ writelen = remaining; -+ } -+ -+ /* Release SPI bus */ -+ spi_release_bus(priv->spi); -+ -+ kfree(tmpbuf); -+ kfree(command); -+ return res; -+} -+ -+/* ......................................................................... */ -+ -+/* -+ * Initialize and register DataFlash device with MTD subsystem. -+ */ -+static int __init add_dataflash(int channel, char *name, int IDsize, -+ int nr_pages, int pagesize, int pageoffset) -+{ -+ struct mtd_info *device; -+ struct dataflash_local *priv; -+#ifdef CONFIG_MTD_PARTITIONS -+ struct mtd_partition *mtd_parts = 0; -+ int mtd_parts_nr = 0; -+#endif -+ -+ if (nr_devices >= DATAFLASH_MAX_DEVICES) { -+ printk(KERN_ERR "at91_dataflash: Too many devices detected\n"); -+ return 0; -+ } -+ -+ device = kmalloc(sizeof(struct mtd_info) + strlen(name) + 8, GFP_KERNEL); -+ if (!device) -+ return -ENOMEM; -+ memset(device, 0, sizeof(struct mtd_info)); -+ -+ device->name = (char *)&device[1]; -+ sprintf(device->name, "%s.spi%d", name, channel); -+ device->size = nr_pages * pagesize; -+ device->erasesize = pagesize; -+ device->writesize = pagesize; -+ device->owner = THIS_MODULE; -+ device->type = MTD_DATAFLASH; -+ device->flags = MTD_WRITEABLE; -+ device->erase = at91_dataflash_erase; -+ device->read = at91_dataflash_read; -+ device->write = at91_dataflash_write; -+ -+ priv = (struct dataflash_local *) kmalloc(sizeof(struct dataflash_local), GFP_KERNEL); -+ if (!priv) { -+ kfree(device); -+ return -ENOMEM; -+ } -+ memset(priv, 0, sizeof(struct dataflash_local)); -+ -+ priv->spi = channel; -+ priv->page_size = pagesize; -+ priv->page_offset = pageoffset; -+ device->priv = priv; -+ -+ mtd_devices[nr_devices] = device; -+ nr_devices++; -+ printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, device->size); -+ -+#ifdef CONFIG_MTD_PARTITIONS -+#ifdef CONFIG_MTD_CMDLINE_PARTS -+ mtd_parts_nr = parse_mtd_partitions(device, part_probes, &mtd_parts, 0); -+#endif -+ if (mtd_parts_nr <= 0) { -+ switch (IDsize) { -+ case SZ_2M: -+ mtd_parts = static_partitions_2M; -+ mtd_parts_nr = ARRAY_SIZE(static_partitions_2M); -+ break; -+ case SZ_4M: -+ mtd_parts = static_partitions_4M; -+ mtd_parts_nr = ARRAY_SIZE(static_partitions_4M); -+ break; -+ case SZ_8M: -+ mtd_parts = static_partitions_8M; -+ mtd_parts_nr = ARRAY_SIZE(static_partitions_8M); -+ break; -+ } -+ } -+ -+ if (mtd_parts_nr > 0) { -+#ifdef DATAFLASH_ALWAYS_ADD_DEVICE -+ add_mtd_device(device); -+#endif -+ return add_mtd_partitions(device, mtd_parts, mtd_parts_nr); -+ } -+#endif -+ return add_mtd_device(device); /* add whole device */ -+} -+ -+/* -+ * Detect and initialize DataFlash device connected to specified SPI channel. -+ * -+ * Device Density ID code Nr Pages Page Size Page offset -+ * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9 -+ * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1025 264 9 -+ * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9 -+ * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9 -+ * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10 -+ * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10 -+ * AT45DB0642 64Mbit (8M) xx1111xx (0x3c) 8192 1056 11 -+ * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11 -+ */ -+static int __init at91_dataflash_detect(int channel) -+{ -+ int res = 0; -+ unsigned short status; -+ -+ spi_access_bus(channel); -+ status = at91_dataflash_status(); -+ spi_release_bus(channel); -+ if (status != 0xff) { /* no dataflash device there */ -+ switch (status & 0x3c) { -+ case 0x0c: /* 0 0 1 1 */ -+ res = add_dataflash(channel, "AT45DB011B", SZ_128K, 512, 264, 9); -+ break; -+ case 0x14: /* 0 1 0 1 */ -+ res = add_dataflash(channel, "AT45DB021B", SZ_256K, 1025, 264, 9); -+ break; -+ case 0x1c: /* 0 1 1 1 */ -+ res = add_dataflash(channel, "AT45DB041B", SZ_512K, 2048, 264, 9); -+ break; -+ case 0x24: /* 1 0 0 1 */ -+ res = add_dataflash(channel, "AT45DB081B", SZ_1M, 4096, 264, 9); -+ break; -+ case 0x2c: /* 1 0 1 1 */ -+ res = add_dataflash(channel, "AT45DB161B", SZ_2M, 4096, 528, 10); -+ break; -+ case 0x34: /* 1 1 0 1 */ -+ res = add_dataflash(channel, "AT45DB321B", SZ_4M, 8192, 528, 10); -+ break; -+ case 0x3c: /* 1 1 1 1 */ -+ res = add_dataflash(channel, "AT45DB642", SZ_8M, 8192, 1056, 11); -+ break; -+// Currently unsupported since Atmel removed the "Main Memory Program via Buffer" commands. -+// case 0x10: /* 0 1 0 0 */ -+// res = add_dataflash(channel, "AT45DB1282", SZ_16M, 16384, 1056, 11); -+// break; -+ default: -+ printk(KERN_ERR "at91_dataflash: Unknown device (%x)\n", status & 0x3c); -+ } -+ } -+ -+ return res; -+} -+ -+static int __init at91_dataflash_init(void) -+{ -+ spi_transfer_desc = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL); -+ if (!spi_transfer_desc) -+ return -ENOMEM; -+ -+ /* DataFlash (SPI chip select 0) */ -+ at91_dataflash_detect(0); -+ -+#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD -+ /* DataFlash card (SPI chip select 3) */ -+ at91_dataflash_detect(3); -+#endif -+ -+ return 0; -+} -+ -+static void __exit at91_dataflash_exit(void) -+{ -+ int i; -+ -+ for (i = 0; i < DATAFLASH_MAX_DEVICES; i++) { -+ if (mtd_devices[i]) { -+#ifdef CONFIG_MTD_PARTITIONS -+ del_mtd_partitions(mtd_devices[i]); -+#else -+ del_mtd_device(mtd_devices[i]); -+#endif -+ kfree(mtd_devices[i]->priv); -+ kfree(mtd_devices[i]); -+ } -+ } -+ nr_devices = 0; -+ kfree(spi_transfer_desc); -+} -+ -+ -+module_init(at91_dataflash_init); -+module_exit(at91_dataflash_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Andrew Victor"); -+MODULE_DESCRIPTION("DataFlash driver for Atmel AT91RM9200"); -diff -urN linux-2.6.22-rc5/drivers/mtd/devices/Kconfig linux-2.6.22-rc5.new/drivers/mtd/devices/Kconfig ---- linux-2.6.22-rc5/drivers/mtd/devices/Kconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/mtd/devices/Kconfig 2007-07-29 05:55:39.000000000 +0200 -@@ -269,5 +269,11 @@ - LinuxBIOS or if you need to recover a DiskOnChip Millennium on which - you have managed to wipe the first block. - --endmenu -+config MTD_AT91_DATAFLASH -+ tristate "AT91RM9200 DataFlash AT45DBxxx (legacy driver)" -+ depends on MTD && ARCH_AT91RM9200 && AT91_SPI -+ help -+ This enables access to the DataFlash (AT45DBxxx) on the AT91RM9200. -+ If you have such a board, say 'Y'. - -+endmenu -diff -urN linux-2.6.22-rc5/drivers/mtd/devices/Makefile linux-2.6.22-rc5.new/drivers/mtd/devices/Makefile ---- linux-2.6.22-rc5/drivers/mtd/devices/Makefile 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/mtd/devices/Makefile 2007-07-29 05:55:39.000000000 +0200 -@@ -18,3 +18,4 @@ - obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o - obj-$(CONFIG_MTD_DATAFLASH26) += at91_dataflash26.o - obj-$(CONFIG_MTD_M25P80) += m25p80.o -+obj-$(CONFIG_MTD_AT91_DATAFLASH)+= at91_dataflash.o -diff -urN linux-2.6.22-rc5/drivers/net/arm/at91_ether.c linux-2.6.22-rc5.new/drivers/net/arm/at91_ether.c ---- linux-2.6.22-rc5/drivers/net/arm/at91_ether.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/net/arm/at91_ether.c 2007-07-29 05:55:39.000000000 +0200 -@@ -894,6 +894,7 @@ - skb_reserve(skb, 2); - memcpy(skb_put(skb, pktlen), p_recv, pktlen); - -+ skb->dev = dev; - skb->protocol = eth_type_trans(skb, dev); - dev->last_rx = jiffies; - lp->stats.rx_bytes += pktlen; -@@ -978,14 +979,22 @@ - struct net_device *dev; - struct at91_private *lp; - unsigned int val; -- int res; -+ struct resource *res; -+ int ret; - - dev = alloc_etherdev(sizeof(struct at91_private)); - if (!dev) - return -ENOMEM; - -- dev->base_addr = AT91_VA_BASE_EMAC; -- dev->irq = AT91RM9200_ID_EMAC; -+ /* Get I/O base address and IRQ */ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ free_netdev(dev); -+ return -ENODEV; -+ } -+ dev->base_addr = res->start; -+ dev->irq = platform_get_irq(pdev, 0); -+ - SET_MODULE_OWNER(dev); - - /* Install the interrupt handler */ -@@ -1058,12 +1067,12 @@ - lp->phy_address = phy_address; /* MDI address of PHY */ - - /* Register the network interface */ -- res = register_netdev(dev); -- if (res) { -+ ret = register_netdev(dev); -+ if (ret) { - free_irq(dev->irq, dev); - free_netdev(dev); - dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); -- return res; -+ return ret; - } - - /* Determine current link speed */ -diff -urN linux-2.6.22-rc5/drivers/serial/atmel_serial.c linux-2.6.22-rc5.new/drivers/serial/atmel_serial.c ---- linux-2.6.22-rc5/drivers/serial/atmel_serial.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/serial/atmel_serial.c 2007-07-29 05:55:39.000000000 +0200 -@@ -7,6 +7,8 @@ - * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. - * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. - * -+ * DMA support added by Chip Coldwell. -+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or -@@ -33,6 +35,7 @@ - #include <linux/sysrq.h> - #include <linux/tty_flip.h> - #include <linux/platform_device.h> -+#include <linux/dma-mapping.h> - #include <linux/atmel_pdc.h> - - #include <asm/io.h> -@@ -47,6 +50,11 @@ - - #include "atmel_serial.h" - -+#define SUPPORT_PDC -+#define PDC_BUFFER_SIZE (L1_CACHE_BYTES << 3) -+#warning "Revisit" -+#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ -+ - #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) - #define SUPPORT_SYSRQ - #endif -@@ -107,6 +115,13 @@ - static int (*atmel_open_hook)(struct uart_port *); - static void (*atmel_close_hook)(struct uart_port *); - -+struct atmel_dma_buffer { -+ unsigned char *buf; -+ dma_addr_t dma_addr; -+ size_t dma_size; -+ unsigned int ofs; -+}; -+ - /* - * We wrap our port structure around the generic uart_port. - */ -@@ -114,10 +129,20 @@ - struct uart_port uart; /* uart */ - struct clk *clk; /* uart clock */ - unsigned short suspended; /* is port suspended? */ -+ -+ short use_dma_rx; /* enable PDC receiver */ -+ short pdc_rx_idx; /* current PDC RX buffer */ -+ struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ -+ -+ short use_dma_tx; /* enable PDC transmitter */ -+ struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ - }; - - static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; - -+#define PDC_RX_BUF(port) &(port)->pdc_rx[(port)->pdc_rx_idx] -+#define PDC_RX_SWITCH(port) (port)->pdc_rx_idx = !(port)->pdc_rx_idx -+ - #ifdef SUPPORT_SYSRQ - static struct console atmel_console; - #endif -@@ -205,7 +230,12 @@ - { - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - -- UART_PUT_IDR(port, ATMEL_US_TXRDY); -+ if (atmel_port->use_dma_tx) { -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); /* disable PDC transmit */ -+ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); -+ } -+ else -+ UART_PUT_IDR(port, ATMEL_US_TXRDY); - } - - /* -@@ -215,7 +245,17 @@ - { - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - -- UART_PUT_IER(port, ATMEL_US_TXRDY); -+ if (atmel_port->use_dma_tx) { -+ if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) -+ /* The transmitter is already running. Yes, we -+ really need this.*/ -+ return; -+ -+ UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); /* re-enable PDC transmit */ -+ } -+ else -+ UART_PUT_IER(port, ATMEL_US_TXRDY); - } - - /* -@@ -225,7 +265,12 @@ - { - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - -- UART_PUT_IDR(port, ATMEL_US_RXRDY); -+ if (atmel_port->use_dma_rx) { -+ UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); /* disable PDC receive */ -+ UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); -+ } -+ else -+ UART_PUT_IDR(port, ATMEL_US_RXRDY); - } - - /* -@@ -248,6 +293,134 @@ - } - - /* -+ * Receive data via the PDC. A buffer has been fulled. -+ */ -+static void atmel_pdc_endrx(struct uart_port *port) -+{ -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; -+ struct tty_struct *tty = port->info->tty; -+ struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port); -+ unsigned int count; -+ -+ count = pdc->dma_size - pdc->ofs; -+ if (likely(count > 0)) { -+ dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE); -+ tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count); -+ tty_flip_buffer_push(tty); -+ -+ port->icount.rx += count; -+ } -+ -+ /* Set this buffer as the next receive buffer */ -+ pdc->ofs = 0; -+ UART_PUT_RNPR(port, pdc->dma_addr); -+ UART_PUT_RNCR(port, pdc->dma_size); -+ -+ /* Switch to next buffer */ -+ PDC_RX_SWITCH(atmel_port); /* next PDC buffer */ -+} -+ -+/* -+ * Receive data via the PDC. At least one byte was received, but the -+ * buffer was not full when the inter-character timeout expired. -+ */ -+static void atmel_pdc_timeout(struct uart_port *port) -+{ -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; -+ struct tty_struct *tty = port->info->tty; -+ struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port); -+ /* unsigned */ int ofs, count; -+ -+ ofs = UART_GET_RPR(port) - pdc->dma_addr; /* current DMA adress */ -+ count = ofs - pdc->ofs; -+ -+ if (likely(count > 0)) { -+ dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE); -+ tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count); -+ tty_flip_buffer_push(tty); -+ -+ pdc->ofs = ofs; -+ port->icount.rx += count; -+ } -+ -+ /* reset the UART timeout */ -+ UART_PUT_CR(port, ATMEL_US_STTTO); -+} -+ -+/* -+ * Deal with parity, framing and overrun errors. -+ */ -+static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) -+{ -+ /* clear error */ -+ UART_PUT_CR(port, ATMEL_US_RSTSTA); -+ -+ if (status & ATMEL_US_RXBRK) { -+ status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */ -+ port->icount.brk++; -+ } -+ if (status & ATMEL_US_PARE) -+ port->icount.parity++; -+ if (status & ATMEL_US_FRAME) -+ port->icount.frame++; -+ if (status & ATMEL_US_OVRE) -+ port->icount.overrun++; -+} -+ -+/* -+ * A transmission via the PDC is complete. -+ */ -+static void atmel_pdc_endtx(struct uart_port *port) -+{ -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; -+ struct circ_buf *xmit = &port->info->xmit; -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; -+ -+ xmit->tail += pdc->ofs; -+ if (xmit->tail >= SERIAL_XMIT_SIZE) -+ xmit->tail -= SERIAL_XMIT_SIZE; -+ -+ port->icount.tx += pdc->ofs; -+ pdc->ofs = 0; -+ -+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) -+ uart_write_wakeup(port); -+} -+ -+/* -+ * The PDC transmitter is idle, so either start the next transfer or -+ * disable the transmitter. -+ */ -+static void atmel_pdc_txbufe(struct uart_port *port) -+{ -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; -+ struct circ_buf *xmit = &port->info->xmit; -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; -+ int count; -+ -+ if (!uart_circ_empty(xmit)) { -+ /* more to transmit - setup next transfer */ -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); /* disable PDC transmit */ -+ dma_sync_single_for_device(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE); -+ -+ if (xmit->tail < xmit->head) -+ count = xmit->head - xmit->tail; -+ else -+ count = SERIAL_XMIT_SIZE - xmit->tail; -+ pdc->ofs = count; -+ -+ UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); -+ UART_PUT_TCR(port, count); -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); /* re-enable PDC transmit */ -+ } -+ else { -+ /* nothing left to transmit - disable the transmitter */ -+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); /* disable PDC transmit */ -+ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); -+ } -+} -+ -+/* - * Characters received (called from interrupt handler) - */ - static void atmel_rx_chars(struct uart_port *port) -@@ -349,6 +522,14 @@ - status = UART_GET_CSR(port); - pending = status & UART_GET_IMR(port); - while (pending) { -+ /* PDC receive */ -+ if (pending & ATMEL_US_ENDRX) -+ atmel_pdc_endrx(port); -+ if (pending & ATMEL_US_TIMEOUT) -+ atmel_pdc_timeout(port); -+ if (atmel_port->use_dma_rx && pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | ATMEL_US_FRAME | ATMEL_US_PARE)) -+ atmel_pdc_rxerr(port, pending); -+ - /* Interrupt receive */ - if (pending & ATMEL_US_RXRDY) - atmel_rx_chars(port); -@@ -363,6 +544,12 @@ - if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC)) - wake_up_interruptible(&port->info->delta_msr_wait); - -+ /* PDC transmit */ -+ if (pending & ATMEL_US_ENDTX) -+ atmel_pdc_endtx(port); -+ if (pending & ATMEL_US_TXBUFE) -+ atmel_pdc_txbufe(port); -+ - /* Interrupt transmit */ - if (pending & ATMEL_US_TXRDY) - atmel_tx_chars(port); -@@ -401,6 +588,47 @@ - } - - /* -+ * Initialize DMA (if necessary) -+ */ -+ if (atmel_port->use_dma_rx) { -+ int i; -+ -+ for (i = 0; i < 2; i++) { -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; -+ -+ pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); -+ if (pdc->buf == NULL) { -+ if (i != 0) { -+ dma_unmap_single(port->dev, atmel_port->pdc_rx[0].dma_addr, PDC_BUFFER_SIZE, DMA_FROM_DEVICE); -+ kfree(atmel_port->pdc_rx[0].buf); -+ } -+ free_irq(port->irq, port); -+ return -ENOMEM; -+ } -+ pdc->dma_addr = dma_map_single(port->dev, pdc->buf, PDC_BUFFER_SIZE, DMA_FROM_DEVICE); -+ pdc->dma_size = PDC_BUFFER_SIZE; -+ pdc->ofs = 0; -+ } -+ -+ atmel_port->pdc_rx_idx = 0; -+ -+ UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); -+ UART_PUT_RCR(port, PDC_BUFFER_SIZE); -+ -+ UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); -+ UART_PUT_RNCR(port, PDC_BUFFER_SIZE); -+ } -+ if (atmel_port->use_dma_tx) { -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; -+ struct circ_buf *xmit = &port->info->xmit; -+ -+ pdc->buf = xmit->buf; -+ pdc->dma_addr = dma_map_single(port->dev, pdc->buf, SERIAL_XMIT_SIZE, DMA_TO_DEVICE); -+ pdc->dma_size = SERIAL_XMIT_SIZE; -+ pdc->ofs = 0; -+ } -+ -+ /* - * If there is a specific "open" function (to register - * control line interrupts) - */ -@@ -418,7 +646,15 @@ - UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); - UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */ - -- UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */ -+ if (atmel_port->use_dma_rx) { -+ UART_PUT_RTOR(port, PDC_RX_TIMEOUT); /* set UART timeout */ -+ UART_PUT_CR(port, ATMEL_US_STTTO); -+ -+ UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); -+ UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); /* enable PDC controller */ -+ } -+ else -+ UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */ - - return 0; - } -@@ -431,6 +667,31 @@ - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - - /* -+ * Ensure everything is stopped. -+ */ -+ atmel_stop_rx(port); -+ atmel_stop_tx(port); -+ -+ /* -+ * Shut-down the DMA. -+ */ -+ if (atmel_port->use_dma_rx) { -+ int i; -+ -+ for (i = 0; i < 2; i++) { -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; -+ -+ dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE); -+ kfree(pdc->buf); -+ } -+ } -+ if (atmel_port->use_dma_tx) { -+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; -+ -+ dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE); -+ } -+ -+ /* - * Disable all interrupts, port and break condition. - */ - UART_PUT_CR(port, ATMEL_US_RSTSTA); -@@ -481,6 +742,7 @@ - */ - static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old) - { -+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - unsigned long flags; - unsigned int mode, imr, quot, baud; - -@@ -490,7 +752,7 @@ - baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); - quot = uart_get_divisor(port, baud); - -- if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ -+ if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ - quot /= 8; - mode |= ATMEL_US_USCLKS_MCK_DIV8; - } -@@ -539,6 +801,9 @@ - if (termios->c_iflag & (BRKINT | PARMRK)) - port->read_status_mask |= ATMEL_US_RXBRK; - -+ if (atmel_port->use_dma_rx) /* need to enable error interrupts */ -+ UART_PUT_IER(port, port->read_status_mask); -+ - /* - * Characters to ignore - */ -@@ -717,6 +982,13 @@ - clk_enable(atmel_port->clk); - port->uartclk = clk_get_rate(atmel_port->clk); - } -+ -+#ifdef SUPPORT_PDC -+ atmel_port->use_dma_rx = data->use_dma_rx; -+ atmel_port->use_dma_tx = data->use_dma_tx; -+ if (atmel_port->use_dma_tx) -+ port->fifosize = PDC_BUFFER_SIZE; -+#endif - } - - /* -@@ -893,7 +1165,8 @@ - struct uart_port *port = platform_get_drvdata(pdev); - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; - -- if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock()) -+ if (device_may_wakeup(&pdev->dev) -+ && !clk_must_disable(atmel_port->clk)) - enable_irq_wake(port->irq); - else { - uart_suspend_port(&atmel_uart, port); -diff -urN linux-2.6.22-rc5/drivers/spi/Kconfig linux-2.6.22-rc5.new/drivers/spi/Kconfig ---- linux-2.6.22-rc5/drivers/spi/Kconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/spi/Kconfig 2007-07-29 05:55:39.000000000 +0200 -@@ -55,6 +55,7 @@ - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) && SPI_MASTER -+ select SPI_AT91_MANUAL_CS if ARCH_AT91RM9200 - help - This selects a driver for the Atmel SPI Controller, present on - many AT32 (AVR32) and AT91 (ARM) chips. -@@ -100,6 +101,24 @@ - inexpensive battery powered microcontroller evaluation board. - This same cable can be used to flash new firmware. - -+config SPI_AT91 -+ tristate "AT91RM9200 Bitbang SPI Master" -+ depends on SPI_MASTER && ARCH_AT91RM9200 && !SPI_ATMEL && EXPERIMENTAL -+ select SPI_BITBANG -+ select SPI_AT91_MANUAL_CS -+ help -+ This is dumb PIO bitbanging driver for the Atmel AT91RM9200. -+ The SPI_ATMEL driver will be its replacement, using the native -+ SPI hardware and its DMA controller. -+ -+config SPI_AT91_MANUAL_CS -+ bool -+ depends on ARCH_AT91RM9200 -+ help -+ Works around an AT91RM9200 problem whereby the SPI chip-select -+ will be wrongly disabled. The workaround uses those pins as -+ GPIOs instead of letting the SPI controller manage them. -+ - config SPI_IMX - tristate "Freescale iMX SPI controller" - depends on SPI_MASTER && ARCH_IMX && EXPERIMENTAL -diff -urN linux-2.6.22-rc5/drivers/spi/Makefile linux-2.6.22-rc5.new/drivers/spi/Makefile ---- linux-2.6.22-rc5/drivers/spi/Makefile 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/spi/Makefile 2007-07-29 05:55:39.000000000 +0200 -@@ -23,6 +23,7 @@ - obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o - obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o - obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o -+obj-$(CONFIG_SPI_AT91) += spi_at91_bitbang.o - # ... add above this line ... - - # SPI protocol drivers (device/link on bus) -diff -urN linux-2.6.22-rc5/drivers/spi/spi_at91_bitbang.c linux-2.6.22-rc5.new/drivers/spi/spi_at91_bitbang.c ---- linux-2.6.22-rc5/drivers/spi/spi_at91_bitbang.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/drivers/spi/spi_at91_bitbang.c 2007-07-29 05:55:39.000000000 +0200 -@@ -0,0 +1,207 @@ -+/* -+ * at91_spi.c - at91 SPI driver (BOOTSTRAP/BITBANG VERSION) -+ * -+ * Copyright (C) 2006 David Brownell -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+#include <linux/kernel.h> -+#include <linux/init.h> -+#include <linux/platform_device.h> -+ -+#include <linux/spi/spi.h> -+#include <linux/spi/spi_bitbang.h> -+ -+#include <asm/arch/gpio.h> -+ -+ -+/* -+ * FIXME this bitbanging version is just to help bootstrap systems until -+ * there's a native SPI+IRQ+DMA controller driver ... such a driver should -+ * be a drop-in replacement for this one, and much faster. -+ * -+ * remember: -+ * -+ * - other at91 parts (like at91sam9) have multiple controllers -+ * and different pin muxing; this version is at91rm9200 specfic. -+ * -+ * - at91sam9261 SPI0 pins are directly muxed with MMC/SD pins. -+ * -+ * - rm9200 spi chipselects drop wrongly, so the native driver -+ * will need to use gpios much like this does. -+ * -+ * - real hardware only allows 8..16 bits per word, while this -+ * bitbanger allows 1..32 (incompatible superset). -+ * -+ * - this disregards clock parameters. with inlined gpio calls, -+ * gcc 3.4.4 produces about 1.5 mbit/sec, more than 2x faster -+ * than using the subroutined veresion from txrx_word(). -+ * -+ * - suspend/resume and <linux/clk.h> support is missing ... -+ */ -+ -+#define spi_miso_bit AT91_PIN_PA0 -+#define spi_mosi_bit AT91_PIN_PA1 -+#define spi_sck_bit AT91_PIN_PA2 -+ -+struct at91_spi { -+ struct spi_bitbang bitbang; -+ struct platform_device *pdev; -+}; -+ -+/*----------------------------------------------------------------------*/ -+ -+static inline void setsck(struct spi_device *spi, int is_on) -+{ -+ at91_set_gpio_value(spi_sck_bit, is_on); -+} -+ -+static inline void setmosi(struct spi_device *spi, int is_on) -+{ -+ at91_set_gpio_value(spi_mosi_bit, is_on); -+} -+ -+static inline int getmiso(struct spi_device *spi) -+{ -+ return at91_get_gpio_value(spi_miso_bit); -+} -+ -+static void at91_spi_chipselect(struct spi_device *spi, int is_active) -+{ -+ unsigned long cs = (unsigned long) spi->controller_data; -+ -+ /* set default clock polarity */ -+ if (is_active) -+ setsck(spi, spi->mode & SPI_CPOL); -+ -+ /* only support active-low (default) */ -+ at91_set_gpio_value(cs, !is_active); -+} -+ -+/* -+ * NOTE: this is "as fast as we can"; it should be a function of -+ * the device clock ... -+ */ -+#define spidelay(X) do{} while(0) -+ -+#define EXPAND_BITBANG_TXRX -+#include <linux/spi/spi_bitbang.h> -+ -+static u32 at91_spi_txrx_word_mode0(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, 8); -+} -+ -+static u32 at91_spi_txrx_word_mode1(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, 8); -+} -+ -+static u32 at91_spi_txrx_word_mode2(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, 8); -+} -+ -+static u32 at91_spi_txrx_word_mode3(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, 8); -+} -+ -+/*----------------------------------------------------------------------*/ -+ -+static int __init at91_spi_probe(struct platform_device *pdev) -+{ -+ int status; -+ struct spi_master *master; -+ struct at91_spi *at91_spi; -+ -+ if (pdev->id != 0) /* SPI0 bus */ -+ return -EINVAL; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof *at91_spi); -+ if (!master) -+ return -ENOMEM; -+ -+ at91_spi = spi_master_get_devdata(master); -+ at91_spi->pdev = pdev; -+ platform_set_drvdata(pdev, at91_spi); -+ -+ /* SPI and bitbang hookup */ -+ master->bus_num = 0; -+ master->num_chipselect = 4; -+ -+ at91_spi->bitbang.master = spi_master_get(master); -+ at91_spi->bitbang.chipselect = at91_spi_chipselect; -+ at91_spi->bitbang.txrx_word[SPI_MODE_0] = at91_spi_txrx_word_mode0; -+ at91_spi->bitbang.txrx_word[SPI_MODE_1] = at91_spi_txrx_word_mode1; -+ at91_spi->bitbang.txrx_word[SPI_MODE_2] = at91_spi_txrx_word_mode2; -+ at91_spi->bitbang.txrx_word[SPI_MODE_3] = at91_spi_txrx_word_mode3; -+ -+ status = spi_bitbang_start(&at91_spi->bitbang); -+ if (status < 0) -+ (void) spi_master_put(at91_spi->bitbang.master); -+ -+ return status; -+} -+ -+static int __exit at91_spi_remove(struct platform_device *pdev) -+{ -+ struct at91_spi *at91_spi = platform_get_drvdata(pdev); -+ int status; -+ -+ /* stop() unregisters child devices too */ -+ status = spi_bitbang_stop(&at91_spi->bitbang); -+ (void) spi_master_put(at91_spi->bitbang.master); -+ -+ platform_set_drvdata(pdev, NULL); -+ return status; -+} -+ -+static struct platform_driver at91_spi_driver = { -+ .probe = at91_spi_probe, -+ .remove = __exit_p(at91_spi_remove), -+ .driver = { -+ .name = "at91_spi", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init at91_spi_init(void) -+{ -+ at91_set_gpio_output(spi_sck_bit, 0); -+ at91_set_gpio_output(spi_mosi_bit, 0); -+ at91_set_gpio_input(spi_miso_bit, 1 /* pullup */); -+ -+ /* register driver */ -+ return platform_driver_register(&at91_spi_driver); -+} -+ -+static void __exit at91_spi_exit(void) -+{ -+ platform_driver_unregister(&at91_spi_driver); -+} -+ -+device_initcall(at91_spi_init); -+module_exit(at91_spi_exit); -+ -+MODULE_ALIAS("at91_spi.0"); -+ -+MODULE_DESCRIPTION("AT91 SPI support (BOOTSTRAP/BITBANG VERSION)"); -+MODULE_AUTHOR("David Brownell"); -+MODULE_LICENSE("GPL"); -diff -urN linux-2.6.22-rc5/drivers/usb/gadget/at91_udc.c linux-2.6.22-rc5.new/drivers/usb/gadget/at91_udc.c ---- linux-2.6.22-rc5/drivers/usb/gadget/at91_udc.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/usb/gadget/at91_udc.c 2007-07-29 05:55:39.000000000 +0200 -@@ -1803,7 +1803,7 @@ - */ - if ((!udc->suspended && udc->addr) - || !wake -- || at91_suspend_entering_slow_clock()) { -+ || clk_must_disable(udc->fclk)) { - pullup(udc, 0); - wake = 0; - } else -diff -urN linux-2.6.22-rc5/drivers/usb/host/ohci-at91.c linux-2.6.22-rc5.new/drivers/usb/host/ohci-at91.c ---- linux-2.6.22-rc5/drivers/usb/host/ohci-at91.c 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/usb/host/ohci-at91.c 2007-07-29 05:55:39.000000000 +0200 -@@ -299,7 +299,7 @@ - * - * REVISIT: some boards will be able to turn VBUS off... - */ -- if (at91_suspend_entering_slow_clock()) { -+ if (clk_must_disable(fclk)) { - ohci_usb_reset (ohci); - at91_stop_clock(); - } -diff -urN linux-2.6.22-rc5/drivers/video/backlight/kb920x_bl.c linux-2.6.22-rc5.new/drivers/video/backlight/kb920x_bl.c ---- linux-2.6.22-rc5/drivers/video/backlight/kb920x_bl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/drivers/video/backlight/kb920x_bl.c 2007-07-29 05:55:39.000000000 +0200 -@@ -0,0 +1,164 @@ -+/* -+ * Backlight Driver for KB9202 -+ * -+ * Copyright (c) 2006 KwikByte -+ * -+ * Based on Sharp's Corgi Backlight Driver -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ */ -+ -+#include <linux/module.h> -+#include <linux/kernel.h> -+#include <linux/init.h> -+#include <linux/platform_device.h> -+#include <linux/spinlock.h> -+#include <linux/fb.h> -+#include <linux/backlight.h> -+ -+#include <asm/arch/gpio.h> -+ -+/* The backlight is on(1)/off(0) */ -+#define KB9202_DEFAULT_INTENSITY 1 -+#define KB9202_MAX_INTENSITY 1 -+ -+static int kb9202bl_suspended; -+static int current_intensity = 0; -+static DEFINE_SPINLOCK(bl_lock); -+ -+static int kb9202bl_set_intensity(struct backlight_device *bd) -+{ -+ unsigned long flags; -+ int intensity = bd->props.brightness; -+ -+ if (bd->props.power != FB_BLANK_UNBLANK) -+ intensity = 0; -+ if (bd->props.fb_blank != FB_BLANK_UNBLANK) -+ intensity = 0; -+ if (kb9202bl_suspended) -+ intensity = 0; -+ -+ if ((!current_intensity) && (bd->props.power == FB_BLANK_UNBLANK)) -+ intensity = 1; -+ -+ spin_lock_irqsave(&bl_lock, flags); -+ if (intensity) -+ gpio_set_value(AT91_PIN_PC23, 1); -+ else -+ gpio_set_value(AT91_PIN_PC23, 0); -+ spin_unlock_irqrestore(&bl_lock, flags); -+ -+ current_intensity = intensity; -+ -+ return 0; -+} -+ -+static int kb9202bl_get_intensity(struct backlight_device *bd) -+{ -+ return current_intensity; -+} -+ -+static struct backlight_ops kb9202bl_ops = { -+ .get_brightness = kb9202bl_get_intensity, -+ .update_status = kb9202bl_set_intensity, -+}; -+ -+static int __init kb9202bl_probe(struct platform_device *pdev) -+{ -+ struct backlight_device *bd; -+ -+ bd = backlight_device_register ("kb9202-bl", &pdev->dev, NULL, &kb9202bl_ops); -+ if (IS_ERR(bd)) -+ return PTR_ERR(bd); -+ -+ platform_set_drvdata(pdev, bd); -+ -+ bd->props.max_brightness = KB9202_MAX_INTENSITY; -+ bd->props.brightness = KB9202_DEFAULT_INTENSITY; -+ (void) kb9202bl_set_intensity(bd); -+ -+ return 0; -+} -+ -+static int kb9202bl_remove(struct platform_device *pdev) -+{ -+ struct backlight_device *bd = platform_get_drvdata(pdev); -+ -+ bd->props.brightness = 0; -+ bd->props.power = 0; -+ (void) kb9202bl_set_intensity(bd); -+ -+ backlight_device_unregister(bd); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static int kb9202bl_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ struct backlight_device *bd = platform_get_drvdata(pdev); -+ -+ kb9202bl_suspended = 1; -+ (void) kb9202bl_set_intensity(bd); -+ return 0; -+} -+ -+static int kb9202bl_resume(struct platform_device *dev) -+{ -+ struct backlight_device *bd = platform_get_drvdata(pdev); -+ -+ kb9202bl_suspended = 0; -+ (void) kb9202bl_set_intensity(bd); -+ return 0; -+} -+#else -+#define kb9202bl_suspend NULL -+#define kb9202bl_resume NULL -+#endif -+ -+static struct platform_driver kb9202bl_driver = { -+ .probe = kb9202bl_probe, -+ .remove = kb9202bl_remove, -+ .suspend = kb9202bl_suspend, -+ .resume = kb9202bl_resume, -+ .driver = { -+ .name = "kb9202-bl", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static struct platform_device *kb9202bl_device; -+ -+static int __init kb9202bl_init(void) -+{ -+ int ret; -+ -+ ret = platform_driver_register(&kb9202bl_driver); -+ if (!ret) { -+ kb9202bl_device = platform_device_alloc("kb9202-bl", -1); -+ if (!kb9202bl_device) -+ return -ENOMEM; -+ -+ ret = platform_device_add(kb9202bl_device); -+ if (ret) { -+ platform_device_put(kb9202bl_device); -+ platform_driver_unregister(&kb9202bl_driver); -+ } -+ } -+ return ret; -+} -+ -+static void __exit kb9202bl_exit(void) -+{ -+ platform_device_unregister(kb9202bl_device); -+ platform_driver_unregister(&kb9202bl_driver); -+} -+ -+module_init(kb9202bl_init); -+module_exit(kb9202bl_exit); -+ -+MODULE_AUTHOR("KwikByte <kb9200_dev@kwikbyte.com>"); -+MODULE_DESCRIPTION("KB9202 Backlight Driver"); -+MODULE_LICENSE("GPL"); -diff -urN linux-2.6.22-rc5/drivers/video/backlight/Kconfig linux-2.6.22-rc5.new/drivers/video/backlight/Kconfig ---- linux-2.6.22-rc5/drivers/video/backlight/Kconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/video/backlight/Kconfig 2007-07-29 05:55:39.000000000 +0200 -@@ -71,3 +71,11 @@ - help - If you have a Intel LE80578 (Carillo Ranch) say Y to enable the - backlight driver. -+ -+config BACKLIGHT_KB920x -+ tristate "KwikByte KB9202 Backlight Driver" -+ depends on BACKLIGHT_CLASS_DEVICE && MACH_KB9200 -+ default y -+ help -+ If you have a KwikByte KB9202 board, say Y to enable the -+ backlight driver. -diff -urN linux-2.6.22-rc5/drivers/video/backlight/Makefile linux-2.6.22-rc5.new/drivers/video/backlight/Makefile ---- linux-2.6.22-rc5/drivers/video/backlight/Makefile 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/video/backlight/Makefile 2007-07-29 05:55:39.000000000 +0200 -@@ -7,3 +7,4 @@ - obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o - obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o - obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o -+obj-$(CONFIG_BACKLIGHT_KB920x) += kb920x_bl.o -diff -urN linux-2.6.22-rc5/drivers/video/Kconfig linux-2.6.22-rc5.new/drivers/video/Kconfig ---- linux-2.6.22-rc5/drivers/video/Kconfig 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/video/Kconfig 2007-07-29 05:55:39.000000000 +0200 -@@ -822,6 +822,17 @@ - framebuffer. Product specs at - <http://www.erd.epson.com/vdc/html/products.htm>. - -+config FB_S1D15605 -+ tristate "Epson S1D15605 framebuffer support" -+ depends on FB -+ default m if MACH_KB9200 -+ select FB_CFB_FILLRECT -+ select FB_CFB_COPYAREA -+ select FB_CFB_IMAGEBLIT -+ help -+ Build in support for the S1D15605 Epson Research 128x64 -+ LCD controller as a framebuffer. -+ - config FB_S1D13XXX - tristate "Epson S1D13XXX framebuffer support" - depends on FB -@@ -835,7 +846,7 @@ - - config FB_ATMEL - tristate "AT91/AT32 LCD Controller support" -- depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || AVR32) -+ depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || AVR32) - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT -diff -urN linux-2.6.22-rc5/drivers/video/Makefile linux-2.6.22-rc5.new/drivers/video/Makefile ---- linux-2.6.22-rc5/drivers/video/Makefile 2007-06-17 04:09:12.000000000 +0200 -+++ linux-2.6.22-rc5.new/drivers/video/Makefile 2007-07-29 05:55:39.000000000 +0200 -@@ -87,7 +87,8 @@ - obj-$(CONFIG_FB_SA1100) += sa1100fb.o - obj-$(CONFIG_FB_HIT) += hitfb.o - obj-$(CONFIG_FB_EPSON1355) += epson1355fb.o --obj-$(CONFIG_FB_ATMEL) += atmel_lcdfb.o -+obj-$(CONFIG_FB_S1D15605) += s1d15605fb.o -+obj-$(CONFIG_FB_ATMEL) += atmel_lcdfb.o - obj-$(CONFIG_FB_PVR2) += pvr2fb.o - obj-$(CONFIG_FB_VOODOO1) += sstfb.o - obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o -diff -urN linux-2.6.22-rc5/drivers/video/s1d15605fb.c linux-2.6.22-rc5.new/drivers/video/s1d15605fb.c ---- linux-2.6.22-rc5/drivers/video/s1d15605fb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22-rc5.new/drivers/video/s1d15605fb.c 2007-07-29 05:55:39.000000000 +0200 -@@ -0,0 +1,659 @@ -+/* -+ * drivers/video/s1d15605.c -+ * -+ * Adapted from several sources including: -+ * 1) Driver for AT91 LCD Controller -+ * Copyright (C) 2006 Atmel -+ * -+ * 2) Copyright (C) 2005 S. Kevin Hester -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive for -+ * more details. -+ * -+ * This is a basic framebuffer driver for the Optrex F-51320 128x64 mono LCD -+ * display. This display uses a clone of the common Epson SED 1531 display -+ * controller. -+ * -+ * I've heavily borrowed code from the vfb.c driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifdef DEBUG -+#define MSG(string, args...) printk("s1d15605fb:" string, ##args) -+#else -+#define MSG(string, args...) -+#endif -+ -+#include <linux/kernel.h> -+#include <linux/platform_device.h> -+#include <linux/dma-mapping.h> -+#include <linux/interrupt.h> -+#include <linux/clk.h> -+#include <linux/fb.h> -+#include <linux/init.h> -+#include <linux/delay.h> -+ -+#include <asm/uaccess.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+ -+#ifdef CONFIG_PMAC_BACKLIGHT -+#include <asm/backlight.h> -+#endif -+ -+#define VIDEOWIDTH 128 -+#define VIDEOHEIGHT 64 -+#define VIDEODEPTH 1 /* bits/pixel */ -+#define VIDEOWIDTH_BYTES ((VIDEOWIDTH * VIDEODEPTH) / 8) -+ -+/* The number of bytes that actually go to the device */ -+#define ACTUALVIDEOMEMSIZE (VIDEOWIDTH_BYTES * VIDEOHEIGHT) -+#define VIDEOMEMSIZE PAGE_SIZE -+ -+static struct fb_var_screeninfo s1d15605_default __initdata = { -+ .xres = VIDEOWIDTH, -+ .yres = VIDEOHEIGHT, -+ .xres_virtual = VIDEOWIDTH, -+ .yres_virtual = VIDEOHEIGHT, -+ .bits_per_pixel = VIDEODEPTH, -+ .red = { 0, 1, 0 }, -+ .green = { 0, 1, 0 }, -+ .blue = { 0, 1, 0 }, -+ .activate = FB_ACTIVATE_NOW, -+ .pixclock = 20000, -+ .vmode = FB_VMODE_NONINTERLACED, -+}; -+ -+static struct fb_fix_screeninfo s1d15605_fix __initdata = { -+ .id = "s1d15605", -+ .type = FB_TYPE_PACKED_PIXELS, -+ .visual = FB_VISUAL_MONO10, -+ .xpanstep = 0, -+ .ypanstep = 0, -+ .ywrapstep = 0, -+ .accel = FB_ACCEL_NONE, -+}; -+ -+struct s1d15605fb_info { -+ struct fb_info *info; -+ char *mmio; -+ unsigned long reset_pin; -+ struct platform_device *pdev; -+}; -+ -+/* -+ * LCD device interface -+ */ -+#define RESET_DISPLAY 0xE2 -+#define LCD_BIAS_1_9 0xA2 -+#define ADC_SELECT_REVERSE 0xA1 -+#define COMMON_OUTPUT_NORMAL 0xC0 -+#define V5_RESISTOR_RATIO 0x26 -+#define ELECTRONIC_VOLUME_SET 0x81 -+#define ELECTRONIC_VOLUME_INIT 0x20 -+#define POWER_CONTROL_SET 0x28 -+#define VOLTAGE_REGULATOR 0x02 -+#define VOLTAGE_FOLLOWER 0x01 -+#define BOOSTER_CIRCUIT 0x04 -+#define DISPLAY_ON 0xAF -+#define START_LINE_SET 0x40 -+#define PAGE_ADDRESS_SET 0xB0 -+#define COLUMN_ADDRESS_HIGH 0x10 -+#define COLUMN_ADDRESS_LOW 0x00 -+#define RESISTOR_RATIO_START 0x20 -+ -+#define NUM_OF_PAGES 8 -+#define NUM_OF_COLUMNS 128 -+ -+#define WRITE_COMMAND(x) __raw_writeb((x), (sinfo)->mmio) -+#define READ_COMMAND __raw_readb((sinfo)->mmio) -+#define WRITE_DATA(x) __raw_writeb((x), (sinfo)->mmio + (0x10000)) -+#define READ_DATA __raw_readb((sinfo)->mmio + (0x10000)) -+ -+ -+/* -+ * s1d15605fb_resize_framebuffer -+ * -+ * Free allocated space if different. Allocate on new of changed. -+ * Returns -ENOMEM if the new framebuffer can not be allocated, -+ * zero on success. -+ */ -+static int s1d15605fb_resize_framebuffer(struct s1d15605fb_info *sinfo) -+{ -+ struct fb_info *info = sinfo->info; -+ struct fb_fix_screeninfo *fix = &info->fix; -+ struct fb_var_screeninfo *var = &info->var; -+ unsigned int new_size; -+ void *new_vaddr; -+ -+ new_size = ((var->xres_virtual * var->yres_virtual * var->bits_per_pixel) / 8); -+ -+ MSG("%s: x (%d) y (%d) bpp (%d): new size 0x%08x\n", __FUNCTION__, -+ var->xres_virtual, var->yres_virtual, var->bits_per_pixel, new_size); -+ -+ if (new_size == fix->smem_len) -+ return 0; -+ -+ if (fix->smem_len) { -+ kfree(info->screen_base); -+ } -+ -+ new_vaddr = kmalloc(new_size, GFP_KERNEL); -+ -+ if (!new_vaddr) { -+ fix->smem_len = 0; -+ return -ENOMEM; -+ } -+ -+ info->screen_base = new_vaddr; -+ fix->smem_start = (unsigned)new_vaddr; -+ fix->smem_len = new_size; -+ fix->line_length = (var->xres_virtual * var->bits_per_pixel) / 8; -+ -+ dev_info(info->device, -+ "%luKiB frame buffer at %08lx (mapped at %p)\n", -+ (unsigned long)info->fix.smem_len / 1024, -+ (unsigned long)info->fix.smem_start, -+ info->screen_base); -+ -+ return 0; -+} -+ -+ -+/* -+ * The s1d15605 seems to be divided into eight 128 pixel wide pages (from top to -+ * bottom) each page seems to be eight pixels high, where these eight pixels are -+ * one byte -+ */ -+static void s1d15605_update(struct fb_info *info) -+{ -+ struct s1d15605fb_info *sinfo = info->par; -+ int page, i, row, colmask; -+ u8 retVal, *rowPtr; -+ -+ WRITE_COMMAND(START_LINE_SET); -+ for (page = 0; page < NUM_OF_PAGES; ++page) { -+ WRITE_COMMAND(PAGE_ADDRESS_SET + page); -+ WRITE_COMMAND(COLUMN_ADDRESS_HIGH); -+ WRITE_COMMAND(COLUMN_ADDRESS_LOW); -+ -+ for (i = 0; i < NUM_OF_COLUMNS; ++i) -+ { -+ /* point of opportunity: optimization */ -+ colmask = (1 << (i & 0x7)); -+ rowPtr = (u8*)(info->screen_base); -+ rowPtr += (VIDEOWIDTH_BYTES * 8 * page); -+ rowPtr += (i >> 3); -+ retVal = 0; -+ for (row = 0; row < 8; ++row) -+ { -+ retVal = (retVal >> 1) | (((*rowPtr) & colmask) ? 0x80 : 0); -+ rowPtr += VIDEOWIDTH_BYTES; -+ } -+ WRITE_DATA(retVal); -+ } -+ } -+ -+ WRITE_COMMAND(DISPLAY_ON); -+} -+ -+ -+/* -+ * Setting the video mode has been split into two parts. -+ * First part, xxxfb_check_var, must not write anything -+ * to hardware, it should only verify and adjust var. -+ * This means it doesn't alter par but it does use hardware -+ * data from it to check this var. -+ */ -+static int s1d15605_check_var(struct fb_var_screeninfo *var, struct fb_info *info) -+{ -+ /* -+ * Some very basic checks -+ */ -+ if (!var->xres) -+ var->xres = 1; -+ if (!var->yres) -+ var->yres = 1; -+ if (var->xres > var->xres_virtual) -+ var->xres_virtual = var->xres; -+ if (var->yres > var->yres_virtual) -+ var->yres_virtual = var->yres; -+ -+ if(var->bits_per_pixel > VIDEODEPTH) -+ return -EINVAL; -+ -+ /* -+ * Memory limit -+ */ -+ if (((var->yres_virtual * var->bits_per_pixel * var->yres_virtual) >> 3) > -+ ACTUALVIDEOMEMSIZE) -+ return -ENOMEM; -+ -+ /* -+ * Now that we checked it we alter var. The reason being is that the video -+ * mode passed in might not work but slight changes to it might make it -+ * work. This way we let the user know what is acceptable. -+ */ -+ switch (var->bits_per_pixel) { -+ case 1: -+ var->red.offset = var->green.offset = var->blue.offset = 0; -+ var->red.length = var->green.length = var->blue.length -+ = var->bits_per_pixel; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ var->xoffset = var->yoffset = 0; -+ var->red.msb_right = var->green.msb_right = var->blue.msb_right = -+ var->transp.msb_right = 0; -+ -+ return 0; -+} -+ -+ -+/* -+ * This routine actually sets the video mode. It's in here where we -+ * the hardware state info->par and fix which can be affected by the -+ * change in par. For this driver it doesn't do much. -+ */ -+static int s1d15605_set_par(struct fb_info *info) -+{ -+ int ret; -+ -+ MSG("%s:\n", __func__); -+ MSG(" * resolution: %ux%u (%ux%u virtual)\n", -+ info->var.xres, info->var.yres, -+ info->var.xres_virtual, info->var.yres_virtual); -+ -+ ret = s1d15605fb_resize_framebuffer(info->par); -+ -+ info->fix.visual = FB_VISUAL_MONO10; -+ return ret; -+} -+ -+ -+/* -+ * Set a single color register. The values supplied are already -+ * rounded down to the hardware's capabilities (according to the -+ * entries in the var structure). Return != 0 for invalid regno. -+ */ -+static int s1d15605_setcolreg(u_int regno, u_int red, u_int green, u_int blue, -+ u_int transp, struct fb_info *info) -+{ -+ if (regno > 1) /* no. of hw registers - we only do mono now */ -+ return 1; -+ -+ return 0; -+} -+ -+ -+/* -+ * Currently, the routine will simply shut-off the backlight and prevent -+ * updates/refreshes. Modify according to application. -+ * -+ * 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off -+ */ -+static int s1d15605_blank(int blank, struct fb_info *info) -+{ -+#ifdef CONFIG_PMAC_BACKLIGHT -+ if (blank) -+ pmac_backlight->props.power = FB_BLANK_POWERDOWN; -+ else -+ pmac_backlight->props.power = FB_BLANK_UNBLANK; -+ backlight_update_status(pmac_backlight); -+#endif -+ return 1; -+} -+ -+ -+/* -+ * Pan or Wrap the Display -+ * -+ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag -+ */ -+/* -+static int s1d15605_pan_display(struct fb_var_screeninfo *var, -+ struct fb_info *info) -+{ -+ if (var->vmode & FB_VMODE_YWRAP) { -+ if (var->yoffset < 0 -+ || var->yoffset >= info->var.yres_virtual -+ || var->xoffset) -+ return -EINVAL; -+ } else { -+ if (var->xoffset + var->xres > info->var.xres_virtual || -+ var->yoffset + var->yres > info->var.yres_virtual) -+ return -EINVAL; -+ } -+ info->var.xoffset = var->xoffset; -+ info->var.yoffset = var->yoffset; -+ if (var->vmode & FB_VMODE_YWRAP) -+ info->var.vmode |= FB_VMODE_YWRAP; -+ else -+ info->var.vmode &= ~FB_VMODE_YWRAP; -+ return 0; -+} -+*/ -+ -+ -+static void s1d15605_copyarea(struct fb_info *info, const struct fb_copyarea *region) -+{ -+ cfb_copyarea(info, region); -+ s1d15605_update(info); -+} -+ -+ -+static void s1d15605_fillrect (struct fb_info *info, const struct fb_fillrect *rect) -+{ -+ cfb_fillrect(info, rect); -+ s1d15605_update(info); -+} -+ -+ -+static void s1d15605_imageblit(struct fb_info *p, const struct fb_image *image) -+{ -+ cfb_imageblit(p, image); -+ s1d15605_update(p); -+} -+ -+ -+/* -+ * Write the users data to our framebuffer, and then trigger a psuedo DMA -+ */ -+static ssize_t s1d15605_write(struct file *file, const char *buf, -+ size_t count, loff_t *ppos) -+{ -+ unsigned long p = *ppos; -+ struct inode *inode = file->f_dentry->d_inode; -+ int fbidx = iminor(inode); -+ struct fb_info *info = registered_fb[fbidx]; -+ int err; -+ -+ if (p > info->fix.smem_len) -+ return -ENOSPC; -+ if (count >= info->fix.smem_len) -+ count = info->fix.smem_len; -+ err = 0; -+ if (count + p > info->fix.smem_len) { -+ count = info->fix.smem_len - p; -+ err = -ENOSPC; -+ } -+ if (count) { -+ char *base_addr; -+ -+ base_addr = info->screen_base; -+ count -= copy_from_user(base_addr+p, buf, count); -+ *ppos += count; -+ err = -EFAULT; -+ } -+ -+ s1d15605_update(info); -+ -+ if (count) -+ return count; -+ -+ return err; -+} -+ -+#ifdef USE_PRIVATE_VMA_FXS -+static void s1d15605_vma_open(struct vm_area_struct *vma) -+{ -+ // FIXME - store stats in the device data via vm_private_data -+} -+ -+ -+static void s1d15605_vma_close(struct vm_area_struct *vma) -+{ -+ // FIXME - store stats in the device data via vm_private_data -+} -+ -+ -+static struct page *s1d15605_vma_nopage(struct vm_area_struct *vma, -+ unsigned long address, int *type) -+{ -+ struct page *page; -+ struct fb_info *info = vma->vm_private_data; -+ -+ page = virt_to_page(info->screen_base); -+ get_page(page); -+ -+ // FIXME - now someone has a link to our page, start periodically blitting -+ // latest updates to the actual device. -+ -+ return page; -+} -+ -+ -+static struct vm_operations_struct s1d15605_vm_ops = { -+ .open = s1d15605_vma_open, -+ .close = s1d15605_vma_close, -+ .nopage = s1d15605_vma_nopage -+}; -+ -+ -+/* We don't do much here - because we have special vm_ops */ -+static int s1d15605_mmap(struct fb_info *info, struct vm_area_struct *vma) -+{ -+ vma->vm_ops = &s1d15605_vm_ops; -+ vma->vm_flags |= VM_RESERVED; -+ vma->vm_private_data = info; -+ s1d15605_vma_open(vma); -+ -+ return 0; -+} -+#endif /* USE_PRIVATE_VMA_FXS */ -+ -+ -+static struct fb_ops s1d15605fb_ops = { -+ .owner = THIS_MODULE, -+ .fb_check_var = s1d15605_check_var, -+ .fb_set_par = s1d15605_set_par, -+ .fb_setcolreg = s1d15605_setcolreg, -+ .fb_blank = s1d15605_blank, -+// .fb_pan_display = s1d15605_pan_display, -+ .fb_fillrect = s1d15605_fillrect, -+ .fb_copyarea = s1d15605_copyarea, -+ .fb_imageblit = s1d15605_imageblit, -+ .fb_write = s1d15605_write, -+#ifdef USE_PRIVATE_VMA_FXS -+ .fb_mmap = s1d15605_mmap, -+#endif -+}; -+ -+ -+static void s1d15605_device_init(struct s1d15605fb_info *sinfo) { -+ -+ char value; -+ -+ /* release the reset line by reading the device - proto hardware */ -+ value = READ_COMMAND; -+ value = READ_COMMAND; -+ -+#ifdef CONFIG_MACH_KB9200 -+ /* new boards have dedicated reset line */ -+ gpio_set_value(sinfo->reset_pin, 1); -+#endif -+ -+ /* initialize the device within 5ms */ -+ WRITE_COMMAND(RESET_DISPLAY); -+ WRITE_COMMAND(LCD_BIAS_1_9); -+ WRITE_COMMAND(ADC_SELECT_REVERSE); -+ WRITE_COMMAND(COMMON_OUTPUT_NORMAL); -+ WRITE_COMMAND(V5_RESISTOR_RATIO); -+ WRITE_COMMAND(ELECTRONIC_VOLUME_SET); -+ WRITE_COMMAND(ELECTRONIC_VOLUME_INIT); -+ WRITE_COMMAND(POWER_CONTROL_SET | VOLTAGE_REGULATOR | VOLTAGE_FOLLOWER | BOOSTER_CIRCUIT); -+ WRITE_COMMAND(DISPLAY_ON); -+ -+ WRITE_COMMAND(RESISTOR_RATIO_START + 4); -+ WRITE_COMMAND(ELECTRONIC_VOLUME_SET); -+ WRITE_COMMAND(0x33); -+} -+ -+ -+static int s1d15605fb_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct fb_info *info; -+ struct s1d15605fb_info *sinfo; -+ int ret; -+ -+ MSG("%s\n", __func__); -+ -+ if (!(info = framebuffer_alloc(sizeof(struct s1d15605fb_info), dev))) { -+ dev_err(dev, "Cannot allocate framebuffer struct\n"); -+ return -ENOMEM; -+ } -+ -+ sinfo = info->par; -+ sinfo->info = info; -+ sinfo->pdev = pdev; -+ -+ if (pdev->num_resources < 2) { -+ dev_err(dev, "Resources unusable\n"); -+ ret = -ENODEV; -+ goto free_info; -+ } -+ -+ info->fbops = &s1d15605fb_ops; -+ strcpy(info->fix.id, pdev->name); -+ -+ info->fix.mmio_start = pdev->resource[0].start; -+ info->fix.mmio_len = pdev->resource[0].end - pdev->resource[0].start + 1; -+ sinfo->reset_pin = pdev->resource[1].start; -+ -+ ret = s1d15605fb_resize_framebuffer(sinfo); -+ if (ret < 0) { -+ dev_err(dev, "Cannot resize framebuffer: %d\n", ret); -+ goto free_fb; -+ } -+ -+ if (!request_mem_region(info->fix.mmio_start, -+ info->fix.mmio_len, pdev->name)) { -+ ret = -EBUSY; -+ goto free_fb; -+ } -+ -+ sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len); -+ if (!sinfo->mmio) { -+ dev_err(dev, "Cannot map LCD memory region\n"); -+ goto release_mem; -+ } -+ -+ s1d15605_device_init(sinfo); -+ -+ ret = fb_find_mode(&info->var, info, NULL, NULL, 0, NULL, 1); -+ -+ if (!ret || (ret == 4)) -+ info->var = s1d15605_default; -+ -+ info->fix = s1d15605_fix; -+ info->flags = FBINFO_FLAG_DEFAULT | -+/* FBINFO_HWACCEL_YPAN | */ -+ FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA; -+ -+ ret = register_framebuffer(info); -+ if (ret < 0) { -+ dev_err(dev, "Failed to register framebuffer device: %d\n", ret); -+ goto unmap_mmio; -+ } -+ -+ dev_set_drvdata(dev, info); -+ -+ memset(info->screen_base, 0, info->fix.smem_len); -+ info->var.activate |= FB_ACTIVATE_NOW; -+ ret = fb_set_var(info, &info->var); -+ if (ret) { -+ dev_warn(dev, "Unable to set display parameters\n"); -+ } -+ -+ info->var.activate &= ~(FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW); -+ -+ dev_dbg(dev, "%s SUCCESS\n", __func__); -+ -+ dev_info(dev, "Driver $Revision: 1.1 $\n"); -+ -+ return 0; -+ -+unmap_mmio: -+ iounmap(sinfo->mmio); -+release_mem: -+ release_mem_region(info->fix.mmio_start, info->fix.mmio_len); -+free_fb: -+ kfree(info->screen_base); -+ -+free_info: -+ framebuffer_release(info); -+ -+ dev_dbg(dev, "%s FAILED\n", __func__); -+ return ret; -+} -+ -+ -+static int s1d15605fb_remove(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct fb_info *info = dev_get_drvdata(dev); -+ struct s1d15605fb_info *sinfo = info->par; -+ -+ if (!sinfo) -+ return 0; -+ -+ unregister_framebuffer(info); -+ -+ iounmap(sinfo->mmio); -+ release_mem_region(info->fix.mmio_start, info->fix.mmio_len); -+ -+ kfree(info->screen_base); -+ -+ dev_set_drvdata(dev, NULL); -+ framebuffer_release(info); -+ return 0; -+} -+ -+ -+static struct platform_driver s1d15605fb_driver = { -+ .probe = s1d15605fb_probe, -+ .remove = s1d15605fb_remove, -+ .driver = { -+ .name = "s1d15605fb", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+ -+static int __init s1d15605fb_init(void) -+{ -+ return platform_driver_register(&s1d15605fb_driver); -+} -+ -+ -+static void __exit s1d15605fb_exit(void) -+{ -+ platform_driver_unregister(&s1d15605fb_driver); -+} -+ -+ -+module_init(s1d15605fb_init); -+module_exit(s1d15605fb_exit); -+ -+ -+MODULE_AUTHOR("KwikByte"); -+MODULE_DESCRIPTION("Epson S1D15605 LCD Controller framebuffer driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/at91-2.6/patches-2.6.22/001-vlink-machine.patch b/target/linux/at91-2.6/patches-2.6.22/001-vlink-machine.patch deleted file mode 100644 index d52c4526ec..0000000000 --- a/target/linux/at91-2.6/patches-2.6.22/001-vlink-machine.patch +++ /dev/null @@ -1,246 +0,0 @@ -diff -urN linux-2.6.22.1.old/arch/arm/boot/compressed/head-at91rm9200.S linux-2.6.22.1/arch/arm/boot/compressed/head-at91rm9200.S ---- linux-2.6.22.1.old/arch/arm/boot/compressed/head-at91rm9200.S 2007-07-29 06:33:09.000000000 +0200 -+++ linux-2.6.22.1/arch/arm/boot/compressed/head-at91rm9200.S 2007-07-29 06:39:45.000000000 +0200 -@@ -67,6 +67,12 @@ - cmp r7, r3 - beq 99f - -+ @ FDL Versalink : 1053 -+ mov r3, #(MACH_TYPE_VLINK & 0xff) -+ orr r3, r3, #(MACH_TYPE_VLINK & 0xff00) -+ cmp r7, r3 -+ beq 99f -+ - @ Ajeco 1ARM : 1075 - mov r3, #(MACH_TYPE_ONEARM & 0xff) - orr r3, r3, #(MACH_TYPE_ONEARM & 0xff00) -diff -urN linux-2.6.22.1.old/arch/arm/mach-at91/board-vlink.c linux-2.6.22.1/arch/arm/mach-at91/board-vlink.c ---- linux-2.6.22.1.old/arch/arm/mach-at91/board-vlink.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22.1/arch/arm/mach-at91/board-vlink.c 2007-07-29 06:40:47.000000000 +0200 -@@ -0,0 +1,191 @@ -+/* -+ * linux/arch/arm/mach-at91/board-vlink.c -+ * -+ * Copyright (C) 2005 SAN People -+ * Copyright (C) 2006,2007 Guthrie Consulting -+ * -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/types.h> -+#include <linux/init.h> -+#include <linux/mm.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+#include <linux/spi/spi.h> -+#include <linux/mtd/physmap.h> -+ -+#include <asm/hardware.h> -+#include <asm/setup.h> -+#include <asm/mach-types.h> -+#include <asm/irq.h> -+ -+#include <asm/mach/arch.h> -+#include <asm/mach/map.h> -+#include <asm/mach/irq.h> -+ -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+#include <asm/arch/at91rm9200_mc.h> -+ -+#include "generic.h" -+ -+ -+/* -+ * Serial port configuration. -+ * 0 .. 3 = USART0 .. USART3 -+ * 4 = DBGU -+ */ -+static struct at91_uart_config __initdata vlink_uart_config = { -+ .console_tty = 0, /* ttyS0 */ -+ .nr_tty = 5, -+ .tty_map = { 4, 1, 0, 3, 2 } /* ttyS0, ..., ttyS4 */ -+}; -+ -+static void __init vlink_map_io(void) -+{ -+ /* Initialize processor: 18.432 MHz crystal */ -+ at91rm9200_initialize(18432000, AT91RM9200_PQFP); -+ -+ /* Setup the LEDs */ -+ at91_init_leds(AT91_PIN_PC14, AT91_PIN_PC15); -+ -+ /* Setup the serial ports and console */ -+ at91_init_serial(&vlink_uart_config); -+} -+ -+static void __init vlink_init_irq(void) -+{ -+ at91rm9200_init_interrupts(NULL); -+} -+ -+static struct at91_eth_data __initdata vlink_eth_data = { -+ .phy_irq_pin = AT91_PIN_PC4, -+ .is_rmii = 1, -+}; -+ -+static struct at91_usbh_data __initdata vlink_usbh_data = { -+ .ports = 1, -+}; -+ -+/* -+static struct at91_udc_data __initdata vlink_udc_data = { -+ .vbus_pin = AT91_PIN_PD4, -+ .pullup_pin = AT91_PIN_PD5, -+}; -+*/ -+ -+static struct at91_mmc_data __initdata vlink_mmc_data = { -+// .det_pin = AT91_PIN_PB27, -+ .slot_b = 0, -+ .wire4 = 1, -+// .wp_pin = AT91_PIN_PA17, -+}; -+ -+static struct spi_board_info vlink_spi_devices[] = { -+ { /* DataFlash chip */ -+ .modalias = "mtd_dataflash", -+ .chip_select = 0, -+ .max_speed_hz = 15 * 1000 * 1000, -+ }, -+#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD -+ { /* DataFlash card */ -+ .modalias = "mtd_dataflash", -+ .chip_select = 3, -+ .max_speed_hz = 15 * 1000 * 1000, -+ }, -+#endif -+}; -+ -+/*static struct at91_gpio_led vlink_leds[] = { -+ { -+ .name = "led0", -+ .gpio = AT91_PIN_PC14, -+ .trigger = "heartbeat", -+ }, -+ { -+ .name = "led1", -+ .gpio = AT91_PIN_PC15, -+ .trigger = "timer", -+ } -+}; -+*/ -+ -+static void __init vlink_board_init(void) -+{ -+ /* Serial */ -+ at91_add_device_serial(); -+ /* Ethernet */ -+ at91_add_device_eth(&vlink_eth_data); -+ /* USB Host */ -+ at91_add_device_usbh(&vlink_usbh_data); -+ /* USB Device */ -+// at91_add_device_udc(&vlink_udc_data); -+// at91_set_multi_drive(vlink_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ -+ /* I2C */ -+ at91_add_device_i2c(); -+ /* SPI */ -+ at91_add_device_spi(vlink_spi_devices, ARRAY_SIZE(vlink_spi_devices)); -+#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD -+ /* DataFlash card */ -+// at91_set_gpio_output(AT91_PIN_PB22, 0); -+#else -+ /* MMC */ -+// at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ -+ at91_add_device_mmc(0, &vlink_mmc_data); -+#endif -+ /* LEDs */ -+// at91_gpio_leds(vlink_leds, ARRAY_SIZE(vlink_leds)); -+ -+/* Other LED's */ -+ at91_set_gpio_output(AT91_PIN_PC7, 1); // LED FRONT AP1 -+ at91_set_gpio_output(AT91_PIN_PC8, 1); // LED FRONT BP1 -+ at91_set_gpio_output(AT91_PIN_PB14, 1); // LED BACK AP1 -+ at91_set_gpio_output(AT91_PIN_PB15, 1); // LED BACK BP1 -+ at91_set_gpio_output(AT91_PIN_PB16, 1); // LED BACK AP2 -+ at91_set_gpio_output(AT91_PIN_PB17, 1); // LED BACK BP2 -+ -+/* SIM Cards */ -+ at91_set_gpio_output(AT91_PIN_PB9, 1); // ENBSC3 -+ at91_set_gpio_output(AT91_PIN_PB10, 1); // ENBSC2 -+ at91_set_gpio_output(AT91_PIN_PB11, 1); // ENBSC1 -+ -+/* GSM Module Control */ -+ at91_set_gpio_output(AT91_PIN_PB12, 1); // GSMONOFF -+ -+/* Test jig presence detection */ -+ at91_set_gpio_input(AT91_PIN_PB8, 1); // JIGPRESENT -+ -+/* Power indicator */ -+ at91_set_gpio_input(AT91_PIN_PB22, 1); // PWR_IND -+ -+/* USB Device control */ -+ at91_set_gpio_input(AT91_PIN_PB27, 1); // UDB_CNX -+ at91_set_gpio_output(AT91_PIN_PB28, 1); // UDB_PUP -+ at91_set_multi_drive(AT91_PIN_PB28, 1); // Set to multi-drive -+ -+} -+ -+MACHINE_START(VLINK, "FDL VersaLink") -+ /* Maintainer: Guthrie Consulting */ -+ .phys_io = AT91_BASE_SYS, -+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, -+ .boot_params = AT91_SDRAM_BASE + 0x100, -+ .timer = &at91rm9200_timer, -+ .map_io = vlink_map_io, -+ .init_irq = vlink_init_irq, -+ .init_machine = vlink_board_init, -+MACHINE_END -diff -urN linux-2.6.22.1.old/arch/arm/mach-at91/Kconfig linux-2.6.22.1/arch/arm/mach-at91/Kconfig ---- linux-2.6.22.1.old/arch/arm/mach-at91/Kconfig 2007-07-29 06:33:09.000000000 +0200 -+++ linux-2.6.22.1/arch/arm/mach-at91/Kconfig 2007-07-29 06:42:19.000000000 +0200 -@@ -103,6 +103,12 @@ - help - Select this if you are using Promwad's Chub board. - -+config MACH_VLINK -+ bool "Figment Design Labs VersaLink" -+ depends on ARCH_AT91RM9200 -+ help -+ Select this if you are using FDL's VersaLink board -+ - endif - - # ---------------------------------------------------------- -diff -urN linux-2.6.22.1.old/arch/arm/mach-at91/Makefile linux-2.6.22.1/arch/arm/mach-at91/Makefile ---- linux-2.6.22.1.old/arch/arm/mach-at91/Makefile 2007-07-29 06:33:09.000000000 +0200 -+++ linux-2.6.22.1/arch/arm/mach-at91/Makefile 2007-07-29 06:43:36.000000000 +0200 -@@ -29,6 +29,7 @@ - obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o - obj-$(CONFIG_MACH_KAFA) += board-kafa.o - obj-$(CONFIG_MACH_CHUB) += board-chub.o -+obj-$(CONFIG_MACH_VLINK) += board-vlink.o - obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o - - # AT91SAM9260 board-specific support -@@ -52,6 +53,7 @@ - led-$(CONFIG_MACH_CSB637) += leds.o - led-$(CONFIG_MACH_KB9200) += leds.o - led-$(CONFIG_MACH_KAFA) += leds.o -+led-$(CONFIG_MACH_VLINK) += leds.o - obj-$(CONFIG_LEDS) += $(led-y) - - # VGA support diff --git a/target/linux/at91-2.6/patches-2.6.22/002-led-driver.patch b/target/linux/at91-2.6/patches-2.6.22/002-led-driver.patch deleted file mode 100644 index 29956f4268..0000000000 --- a/target/linux/at91-2.6/patches-2.6.22/002-led-driver.patch +++ /dev/null @@ -1,121 +0,0 @@ -diff -urN linux-2.6.22.1.old/arch/arm/mach-at91/Makefile linux-2.6.22.1/arch/arm/mach-at91/Makefile ---- linux-2.6.22.1.old/arch/arm/mach-at91/Makefile 2007-07-29 06:46:13.000000000 +0200 -+++ linux-2.6.22.1/arch/arm/mach-at91/Makefile 2007-07-29 06:54:19.000000000 +0200 -@@ -53,7 +53,7 @@ - led-$(CONFIG_MACH_CSB637) += leds.o - led-$(CONFIG_MACH_KB9200) += leds.o - led-$(CONFIG_MACH_KAFA) += leds.o --led-$(CONFIG_MACH_VLINK) += leds.o -+led-$(CONFIG_MACH_VLINK) += vlink_leds.o - obj-$(CONFIG_LEDS) += $(led-y) - - # VGA support -diff -urN linux-2.6.22.1.old/arch/arm/mach-at91/vlink_leds.c linux-2.6.22.1/arch/arm/mach-at91/vlink_leds.c ---- linux-2.6.22.1.old/arch/arm/mach-at91/vlink_leds.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22.1/arch/arm/mach-at91/vlink_leds.c 2007-07-29 06:54:58.000000000 +0200 -@@ -0,0 +1,105 @@ -+/* -+ * LED driver for Atmel AT91-based boards. -+ * -+ * Copyright (C) SAN People (Pty) Ltd -+ * Modified for FDL VersaLink Copyright (C) Guthrie Consulting -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+*/ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/init.h> -+ -+#include <asm/mach-types.h> -+#include <asm/leds.h> -+#include <asm/arch/board.h> -+#include <asm/arch/gpio.h> -+ -+ -+static inline void at91_led_on(unsigned int led) -+{ -+ at91_set_gpio_value(led, 0); -+} -+ -+static inline void at91_led_off(unsigned int led) -+{ -+ at91_set_gpio_value(led, 1); -+} -+ -+static inline void at91_led_toggle(unsigned int led) -+{ -+ unsigned long is_off = at91_get_gpio_value(led); -+ if (is_off) { -+ at91_led_on(led); -+ at91_led_off(at91_leds_cpu); -+ } -+ else { -+ at91_led_on(at91_leds_cpu); -+ at91_led_off(led); -+ } -+} -+ -+ -+/* -+ * Handle LED events. -+ */ -+ -+/* -+ * VersaLink has a single bi-coloured LED which changes colour when the -+ * polarity is reversed -+ */ -+static void at91_leds_event(led_event_t evt) -+{ -+ unsigned long flags; -+ -+ local_irq_save(flags); -+ -+ switch(evt) { -+ case led_start: /* System startup */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+ -+ case led_stop: /* System stop / suspend */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+ -+#ifdef CONFIG_LEDS_TIMER -+ case led_timer: /* Every 50 timer ticks */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+#endif -+ -+#ifdef CONFIG_LEDS_CPU -+ case led_idle_start: /* Entering idle state */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+ -+ case led_idle_end: /* Exit idle state */ -+ at91_led_toggle(at91_leds_timer); -+ break; -+#endif -+ -+ default: -+ break; -+ } -+ -+ local_irq_restore(flags); -+} -+ -+ -+static int __init leds_init(void) -+{ -+ if (!at91_leds_timer || !at91_leds_cpu) -+ return -ENODEV; -+ -+ leds_event = at91_leds_event; -+ -+ leds_event(led_start); -+ return 0; -+} -+ -+__initcall(leds_init); diff --git a/target/linux/at91-2.6/patches-2.6.22/003-gpio-driver.patch b/target/linux/at91-2.6/patches-2.6.22/003-gpio-driver.patch deleted file mode 100644 index 766f962291..0000000000 --- a/target/linux/at91-2.6/patches-2.6.22/003-gpio-driver.patch +++ /dev/null @@ -1,359 +0,0 @@ -diff -urN linux-2.6.22.1.old/arch/arm/mach-at91/gpio.c linux-2.6.22.1/arch/arm/mach-at91/gpio.c ---- linux-2.6.22.1.old/arch/arm/mach-at91/gpio.c 2007-07-10 20:56:30.000000000 +0200 -+++ linux-2.6.22.1/arch/arm/mach-at91/gpio.c 2007-07-29 07:03:30.000000000 +0200 -@@ -27,6 +27,7 @@ - - static struct at91_gpio_bank *gpio; - static int gpio_banks; -+static u32 pio_gpio_pin[4] = { 0, 0, 0, 0 }; - - - static inline void __iomem *pin_to_controller(unsigned pin) -@@ -71,9 +72,13 @@ - { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); -+ int bank = (pin - PIN_BASE) / 32; - - if (!pio) - return -EINVAL; -+ -+ pio_gpio_pin[bank] |= mask; -+ - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_PER); -@@ -130,10 +135,13 @@ - { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); -+ int bank = (pin - PIN_BASE) / 32; - - if (!pio) - return -EINVAL; - -+ pio_gpio_pin[bank] |= mask; -+ - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_ODR); -@@ -151,10 +159,13 @@ - { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); -+ int bank = (pin - PIN_BASE) / 32; - - if (!pio) - return -EINVAL; - -+ pio_gpio_pin[bank] |= mask; -+ - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + PIO_PUDR); - __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); -@@ -262,6 +273,18 @@ - } - EXPORT_SYMBOL(at91_get_gpio_value); - -+int at91_is_pin_gpio(unsigned pin) -+{ -+ void __iomem *pio = pin_to_controller(pin); -+ unsigned mask = pin_to_mask(pin); -+ int bank = (pin - PIN_BASE) / 32; -+ -+ if (!pio) -+ return -EINVAL; -+ return (pio_gpio_pin[bank] & mask) != 0; -+} -+EXPORT_SYMBOL(at91_is_pin_gpio); -+ - /*--------------------------------------------------------------------------*/ - - #ifdef CONFIG_PM -diff -urN linux-2.6.22.1.old/drivers/char/Kconfig linux-2.6.22.1/drivers/char/Kconfig ---- linux-2.6.22.1.old/drivers/char/Kconfig 2007-07-29 06:46:13.000000000 +0200 -+++ linux-2.6.22.1/drivers/char/Kconfig 2007-07-29 07:05:30.000000000 +0200 -@@ -1099,5 +1099,12 @@ - The SPI driver gives user mode access to this serial - bus on the AT91RM9200 processor. - -+config AT91_VLIO -+ tristate "Versalink LED and GPIO interface" -+ depends on ARCH_AT91RM9200 && MACH_VLINK -+ default n -+ help -+ Provides a handler GPIO's in userspace -+ - endmenu - -diff -urN linux-2.6.22.1.old/drivers/char/Makefile linux-2.6.22.1/drivers/char/Makefile ---- linux-2.6.22.1.old/drivers/char/Makefile 2007-07-29 06:46:13.000000000 +0200 -+++ linux-2.6.22.1/drivers/char/Makefile 2007-07-29 07:06:06.000000000 +0200 -@@ -95,6 +95,7 @@ - obj-$(CONFIG_TELCLOCK) += tlclk.o - obj-$(CONFIG_AT91_SPI) += at91_spi.o - obj-$(CONFIG_AT91_SPIDEV) += at91_spidev.o -+obj-$(CONFIG_AT91_VLIO) += vlink_giu.o - - obj-$(CONFIG_WATCHDOG) += watchdog/ - obj-$(CONFIG_MWAVE) += mwave/ -diff -urN linux-2.6.22.1.old/drivers/char/vlink_giu.c linux-2.6.22.1/drivers/char/vlink_giu.c ---- linux-2.6.22.1.old/drivers/char/vlink_giu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.22.1/drivers/char/vlink_giu.c 2007-07-29 07:06:33.000000000 +0200 -@@ -0,0 +1,256 @@ -+/* -+ * Driver for FDL Versalink GPIO -+ * -+ * Copyright (C) 2005 Guthrie Consulting -+ * Author: Hamish Guthrie <hamish@prodigi.ch> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/module.h> -+#include <linux/moduleparam.h> -+#include <linux/init.h> -+#include <linux/platform_device.h> -+ -+#include <linux/kernel.h> -+#include <linux/slab.h> -+#include <linux/fs.h> -+#include <linux/errno.h> -+#include <linux/init.h> -+#include <linux/types.h> -+#include <linux/proc_fs.h> -+#include <linux/fcntl.h> -+#include <linux/seq_file.h> -+#include <linux/cdev.h> -+#include <asm/arch/gpio.h> -+#include <asm/uaccess.h> -+ -+static int major; /* default is dynamic major device number */ -+module_param(major, int, 0); -+MODULE_PARM_DESC(major, "Major device number"); -+ -+#define VIO_NR_DEVS 96 -+ -+struct vio_dev { -+ struct cdev cdev; -+}; -+ -+struct vio_dev *vio_devices; -+static struct class *vio_class; -+ -+static ssize_t gpio_read(struct file *file, char __user *buf, size_t len, -+ loff_t *ppos) -+{ -+ unsigned int pin; -+ int retval; -+ char value = '0'; -+ -+ pin = iminor(file->f_dentry->d_inode); -+ -+ retval = at91_get_gpio_value(PIN_BASE + pin); -+ if (retval < 0) -+ return -EFAULT; -+ -+ value = retval + 0x30; -+ if (put_user(value, buf)) -+ return -EFAULT; -+ -+ return 1; -+} -+ -+static ssize_t gpio_write(struct file *file, const char __user *data, -+ size_t len, loff_t *ppos) -+{ -+ unsigned int pin; -+ size_t i; -+ char c; -+ int retval = 0; -+ -+ pin = iminor(file->f_dentry->d_inode); -+ -+ for (i = 0; i < len; i++) { -+ if (get_user(c, data + i)) -+ return -EFAULT; -+ -+ switch (c) { -+ case '0': -+ case '1': -+ retval = at91_set_gpio_value(PIN_BASE + pin, (int)c - 0x30); -+ if (retval < 0) -+ return -EFAULT; -+ break; -+ default: -+ break; -+ } -+ -+ if (retval < 0) -+ break; -+ } -+ -+ return i; -+} -+ -+static int gpio_open(struct inode *inode, struct file *file) -+{ -+ return nonseekable_open(inode, file); -+} -+ -+static int gpio_release(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+static struct file_operations vio_fops = { -+ .owner = THIS_MODULE, -+ .read = gpio_read, -+ .write = gpio_write, -+ .open = gpio_open, -+ .release = gpio_release, -+}; -+ -+static void vio_setup_cdev(struct vio_dev *dev, int index) -+{ -+ int err, devno = MKDEV(major, index); -+ -+ cdev_init(&dev->cdev, &vio_fops); -+ dev->cdev.owner = THIS_MODULE; -+ dev->cdev.ops = &vio_fops; -+ err = cdev_add (&dev->cdev, devno, 1); -+ if (err) -+ printk(KERN_NOTICE "vio: Error %d adding vio%d", err, index); -+} -+ -+static int vio_remove(struct platform_device *dev) -+{ -+ int i; -+ dev_t devno = MKDEV(major, 0); -+ -+ if (vio_devices) { -+ for(i=0; i<VIO_NR_DEVS; i++) { -+ int iodev = at91_is_pin_gpio(PIN_BASE + i); -+ if (iodev) { -+ cdev_del(&vio_devices[i].cdev); -+ class_device_destroy(vio_class, MKDEV(major, i)); -+ } -+ } -+ kfree(vio_devices); -+ } -+ -+ class_destroy(vio_class); -+ unregister_chrdev_region(devno, VIO_NR_DEVS); -+ -+ platform_set_drvdata(dev, NULL); -+ -+ return 0; -+} -+ -+static int vio_probe(struct platform_device *dev) -+{ -+ int retval, i, j; -+ dev_t vdev = 0; -+ -+ if (major) { -+ vdev = MKDEV(major, 0); -+ retval = register_chrdev_region(vdev, VIO_NR_DEVS, "vio"); -+ } else { -+ retval = alloc_chrdev_region(&vdev, 0, VIO_NR_DEVS, "vio"); -+ major = MAJOR(vdev); -+ } -+ if (retval < 0) { -+ printk(KERN_WARNING "vio: can't get major %d\n", major); -+ return retval; -+ } -+ -+ if (major == 0) { -+ major = retval; -+ printk(KERN_INFO "vio: major number %d\n", major); -+ } -+ -+ vio_class = class_create(THIS_MODULE, "vio"); -+ -+ if (IS_ERR(vio_class)) { -+ printk(KERN_ERR "vio: Error creating vio class\n"); -+ vio_remove(dev); -+ return PTR_ERR(vio_class); -+ } -+ -+ vio_devices = kmalloc(VIO_NR_DEVS * sizeof(struct vio_dev), GFP_KERNEL); -+ if (!vio_devices) { -+ retval = -ENOMEM; -+ goto fail; -+ } -+ memset(vio_devices, 0, VIO_NR_DEVS * sizeof(struct vio_dev)); -+ -+ for (i=0; i<VIO_NR_DEVS/32; i++) -+ for(j=0; j<32; j++) { -+ int iodev = at91_is_pin_gpio(PIN_BASE + i*32 + j); -+ if (iodev) { -+ vio_setup_cdev(&vio_devices[i*32 + j], i*32 + j); -+ class_device_create(vio_class, NULL, MKDEV(major, i*32 + j), NULL, -+ "vio%c%d", i + 'A', j); -+ } -+ } -+ -+ platform_set_drvdata(dev, vio_devices); -+ -+ return 0; -+ -+fail: -+ vio_remove(dev); -+ return retval; -+} -+ -+static struct platform_device *vio_platform_device; -+ -+static struct platform_driver vio_driver = { -+ .probe = vio_probe, -+ .remove = vio_remove, -+ .driver = { -+ .name = "vio", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init vio_init(void) -+{ -+ int retval; -+ -+ vio_platform_device = platform_device_register_simple("vio", -1, NULL, 0); -+ if (IS_ERR(vio_platform_device)) { -+ printk(KERN_WARNING "vio: device registration failed\n"); -+ return PTR_ERR(vio_platform_device); -+ } -+ -+ retval = platform_driver_register(&vio_driver); -+ if (retval < 0) { -+ printk(KERN_WARNING "vio: driver registration failed\n"); -+ platform_device_unregister(vio_platform_device); -+ } -+ -+ return retval; -+} -+ -+static void __exit vio_exit(void) -+{ -+ platform_driver_unregister(&vio_driver); -+ platform_device_unregister(vio_platform_device); -+} -+ -+module_init(vio_init); -+module_exit(vio_exit); -+ -+MODULE_AUTHOR("Hamish Guthrie <hamish@prodigi.ch>"); -+MODULE_DESCRIPTION("FDL Versalink GPIO Driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/at91-2.6/patches-2.6.22/007-mtd-partition.patch b/target/linux/at91-2.6/patches-2.6.22/007-mtd-partition.patch deleted file mode 100644 index cd074cc025..0000000000 --- a/target/linux/at91-2.6/patches-2.6.22/007-mtd-partition.patch +++ /dev/null @@ -1,39 +0,0 @@ -diff -urN linux-2.6.22.1.old/drivers/mtd/devices/at91_dataflash.c linux-2.6.22.1/drivers/mtd/devices/at91_dataflash.c ---- linux-2.6.22.1.old/drivers/mtd/devices/at91_dataflash.c 2007-07-29 07:50:05.000000000 +0200 -+++ linux-2.6.22.1/drivers/mtd/devices/at91_dataflash.c 2007-07-29 07:56:11.000000000 +0200 -@@ -173,7 +173,7 @@ - }; - #endif - --static const char *part_probes[] = { "cmdlinepart", NULL, }; -+static const char *part_probes[] = { "cmdlinepart", "at91part", NULL, }; - - #endif - -diff -urN linux-2.6.22.1.old/drivers/mtd/Kconfig linux-2.6.22.1/drivers/mtd/Kconfig ---- linux-2.6.22.1.old/drivers/mtd/Kconfig 2007-07-29 07:54:27.000000000 +0200 -+++ linux-2.6.22.1/drivers/mtd/Kconfig 2007-07-29 07:55:21.000000000 +0200 -@@ -160,6 +160,12 @@ - for your particular device. It won't happen automatically. The - 'armflash' map driver (CONFIG_MTD_ARMFLASH) does this, for example. - -+config MTD_AT91_PARTS -+ tristate "Atmel AT91 partitioning support" -+ depends on MTD_PARTITIONS && ARCH_AT91RM9200 && AT91_SPI -+ ---help--- -+ Atmel AT91 partitioning support -+ - comment "User Modules And Translation Layers" - - config MTD_CHAR -diff -urN linux-2.6.22.1.old/drivers/mtd/Makefile linux-2.6.22.1/drivers/mtd/Makefile ---- linux-2.6.22.1.old/drivers/mtd/Makefile 2007-07-10 20:56:30.000000000 +0200 -+++ linux-2.6.22.1/drivers/mtd/Makefile 2007-07-29 07:55:39.000000000 +0200 -@@ -11,6 +11,7 @@ - obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o - obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o - obj-$(CONFIG_MTD_AFS_PARTS) += afs.o -+obj-$(CONFIG_MTD_AT91_PARTS) += at91part.o - - # 'Users' - code which presents functionality to userspace. - obj-$(CONFIG_MTD_CHAR) += mtdchar.o diff --git a/target/linux/at91-2.6/patches-2.6.22/008-fdl-serial.patch b/target/linux/at91-2.6/patches-2.6.22/008-fdl-serial.patch deleted file mode 100644 index 42589197be..0000000000 --- a/target/linux/at91-2.6/patches-2.6.22/008-fdl-serial.patch +++ /dev/null @@ -1,160 +0,0 @@ ---- linux-2.6.21.1.orig/drivers/serial/atmel_serial.c 2007-05-28 12:22:29.000000000 +0200 -+++ linux-2.6.21.1/drivers/serial/atmel_serial.c 2007-05-28 16:39:09.000000000 +0200 -@@ -174,7 +174,35 @@ - at91_set_gpio_value(AT91_PIN_PA21, 0); - else - at91_set_gpio_value(AT91_PIN_PA21, 1); -+ -+ /* -+ * FDL VersaLink adds GPIOS to provide full modem control on -+ * USART 0 - Drive DTR and RI pins manually -+ */ -+ if (mctrl & TIOCM_DTR) -+ at91_set_gpio_value(AT91_PIN_PB6, 0); -+ else -+ at91_set_gpio_value(AT91_PIN_PB6, 1); -+ if (mctrl & TIOCM_RI) -+ at91_set_gpio_value(AT91_PIN_PB7, 0); -+ else -+ at91_set_gpio_value(AT91_PIN_PB7, 1); - } -+ -+ /* -+ * FDL VersaLink adds GPIOS to provide full modem control on -+ * USART 3 - Drive DTR and RI pins manually -+ */ -+ if (port->mapbase == AT91RM9200_BASE_US3) { -+ if (mctrl & TIOCM_DTR) -+ at91_set_gpio_value(AT91_PIN_PB29, 0); -+ else -+ at91_set_gpio_value(AT91_PIN_PB29, 1); -+ if (mctrl & TIOCM_RI) -+ at91_set_gpio_value(AT91_PIN_PB2, 0); -+ else -+ at91_set_gpio_value(AT91_PIN_PB2, 1); -+ } - } - #endif - -@@ -211,8 +239,10 @@ - /* - * The control signals are active low. - */ -- if (!(status & ATMEL_US_DCD)) -- ret |= TIOCM_CD; -+ -+ if (!(port->mapbase == AT91RM9200_BASE_US0 || port->mapbase == AT91RM9200_BASE_US3)) -+ if (!(status & ATMEL_US_DCD)) -+ ret |= TIOCM_CD; - if (!(status & ATMEL_US_CTS)) - ret |= TIOCM_CTS; - if (!(status & ATMEL_US_DSR)) -@@ -220,6 +250,16 @@ - if (!(status & ATMEL_US_RI)) - ret |= TIOCM_RI; - -+ /* -+ * Read the GPIO's for the FDL VersaLink special case -+ */ -+ if (port->mapbase == AT91RM9200_BASE_US0) -+ if (!(at91_get_gpio_value(AT91_PIN_PA19))) -+ ret |= TIOCM_CD; -+ if (port->mapbase == AT91RM9200_BASE_US3) -+ if (!(at91_get_gpio_value(AT91_PIN_PA24))) -+ ret |= TIOCM_CD; -+ - return ret; - } - -@@ -511,6 +551,34 @@ - } - - /* -+ * USART0 DCD Interrupt handler -+ */ -+ -+static irqreturn_t atmel_u0_DCD_interrupt(int irq, void *dev_id) -+{ -+ struct uart_port *port = dev_id; -+ int status = at91_get_gpio_value(irq); -+ -+ uart_handle_dcd_change(port, !(status)); -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * USART3 DCD Interrupt handler -+ */ -+ -+static irqreturn_t atmel_u3_DCD_interrupt(int irq, void *dev_id) -+{ -+ struct uart_port *port = dev_id; -+ int status = at91_get_gpio_value(irq); -+ -+ uart_handle_dcd_change(port, !(status)); -+ -+ return IRQ_HANDLED; -+} -+ -+/* - * Interrupt handler - */ - static irqreturn_t atmel_interrupt(int irq, void *dev_id) -@@ -587,6 +655,23 @@ - return retval; - } - -+ if (port->mapbase == AT91RM9200_BASE_US0) { -+ retval = request_irq(AT91_PIN_PA19, atmel_u0_DCD_interrupt, 0, "atmel_serial", port); -+ if (retval) { -+ printk("atmel_serial: atmel_startup - Can't get u0DCD irq\n"); -+ free_irq(port->irq, port); -+ return retval; -+ } -+ } -+ if (port->mapbase == AT91RM9200_BASE_US3) { -+ retval = request_irq(AT91_PIN_PA24, atmel_u3_DCD_interrupt, 0, "atmel_serial", port); -+ if (retval) { -+ printk("atmel_serial: atmel_startup - Can't get u3DCD irq\n"); -+ free_irq(port->irq, port); -+ return retval; -+ } -+ } -+ - /* - * Initialize DMA (if necessary) - */ -@@ -603,6 +688,10 @@ - kfree(atmel_port->pdc_rx[0].buf); - } - free_irq(port->irq, port); -+ if (port->mapbase == AT91RM9200_BASE_US0) -+ free_irq(AT91_PIN_PA19, port); -+ if (port->mapbase == AT91RM9200_BASE_US3) -+ free_irq(AT91_PIN_PA24, port); - return -ENOMEM; - } - pdc->dma_addr = dma_map_single(port->dev, pdc->buf, PDC_BUFFER_SIZE, DMA_FROM_DEVICE); -@@ -636,6 +725,10 @@ - retval = atmel_open_hook(port); - if (retval) { - free_irq(port->irq, port); -+ if (port->mapbase == AT91RM9200_BASE_US0) -+ free_irq(AT91_PIN_PA19, port); -+ if (port->mapbase == AT91RM9200_BASE_US3) -+ free_irq(AT91_PIN_PA24, port); - return retval; - } - } -@@ -701,6 +794,10 @@ - * Free the interrupt - */ - free_irq(port->irq, port); -+ if (port->mapbase == AT91RM9200_BASE_US0) -+ free_irq(AT91_PIN_PA19, port); -+ if (port->mapbase == AT91RM9200_BASE_US3) -+ free_irq(AT91_PIN_PA24, port); - - /* - * If there is a specific "close" function (to unregister diff --git a/target/linux/at91-2.6/patches-2.6.22/009-fdl-uartinit.patch b/target/linux/at91-2.6/patches-2.6.22/009-fdl-uartinit.patch deleted file mode 100644 index f36f386824..0000000000 --- a/target/linux/at91-2.6/patches-2.6.22/009-fdl-uartinit.patch +++ /dev/null @@ -1,27 +0,0 @@ -diff -urN linux-2.6.22.1.old/arch/arm/mach-at91/at91rm9200_devices.c linux-2.6.22.1/arch/arm/mach-at91/at91rm9200_devices.c ---- linux-2.6.22.1.old/arch/arm/mach-at91/at91rm9200_devices.c 2007-07-29 06:46:13.000000000 +0200 -+++ linux-2.6.22.1/arch/arm/mach-at91/at91rm9200_devices.c 2007-07-29 07:23:35.000000000 +0200 -@@ -721,6 +721,10 @@ - * We need to drive the pin manually. Default is off (RTS is active low). - */ - at91_set_gpio_output(AT91_PIN_PA21, 1); -+ at91_set_gpio_output(AT91_PIN_PB6, 1); /* DTR0 */ -+ at91_set_gpio_output(AT91_PIN_PB7, 1); /* RI0 */ -+ at91_set_gpio_input(AT91_PIN_PA19, 1); /* DCD0 */ -+ at91_set_deglitch(AT91_PIN_PA19, 1); - } - - static struct resource uart1_resources[] = { -@@ -832,6 +836,12 @@ - { - at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */ - at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */ -+ at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */ -+ at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */ -+ at91_set_gpio_output(AT91_PIN_PB29, 1); /* DTR0 */ -+ at91_set_gpio_output(AT91_PIN_PB2, 1); /* RI0 */ -+ at91_set_gpio_input(AT91_PIN_PA24, 1); /* DCD0 */ -+ at91_set_deglitch(AT91_PIN_PA24, 1); - } - - struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ diff --git a/target/linux/at91-2.6/patches-2.6.22/010-dm9161a-phyfix.patch b/target/linux/at91-2.6/patches-2.6.22/010-dm9161a-phyfix.patch deleted file mode 100644 index 9ad8c42530..0000000000 --- a/target/linux/at91-2.6/patches-2.6.22/010-dm9161a-phyfix.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- linux-2.6.21.1/drivers/net/arm/at91_ether.c.old 2007-06-04 18:15:49.000000000 +0200 -+++ linux-2.6.21.1/drivers/net/arm/at91_ether.c 2007-06-04 18:10:36.000000000 +0200 -@@ -146,6 +146,7 @@ - struct at91_private *lp = netdev_priv(dev); - unsigned int bmsr, bmcr, lpa, mac_cfg; - unsigned int speed, duplex; -+ unsigned long timeout = jiffies + HZ; - - if (!mii_link_ok(&lp->mii)) { /* no link */ - netif_carrier_off(dev); -@@ -158,8 +159,15 @@ - read_phy(lp->phy_address, MII_BMSR, &bmsr); - read_phy(lp->phy_address, MII_BMCR, &bmcr); - if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ -- if (!(bmsr & BMSR_ANEGCOMPLETE)) -- return; /* Do nothing - another interrupt generated when negotiation complete */ -+ while (!(bmsr & BMSR_ANEGCOMPLETE)) { -+ if (time_after(jiffies, timeout)) { -+ printk("at91_ether: Auto-negotiate timeout\n"); -+ return; -+ } -+ read_phy(lp->phy_address, MII_BMSR, &bmsr); -+ read_phy(lp->phy_address, MII_BMCR, &bmcr); -+ cpu_relax(); -+ } - - read_phy(lp->phy_address, MII_LPA, &lpa); - if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; diff --git a/target/linux/at91-2.6/patches-2.6.22/014-initpartition.patch b/target/linux/at91-2.6/patches-2.6.22/014-initpartition.patch deleted file mode 100644 index cfcd062fce..0000000000 --- a/target/linux/at91-2.6/patches-2.6.22/014-initpartition.patch +++ /dev/null @@ -1,19 +0,0 @@ -diff -urN linux-2.6.22.1.old/drivers/mtd/devices/at91_dataflash.c linux-2.6.22.1/drivers/mtd/devices/at91_dataflash.c ---- linux-2.6.22.1.old/drivers/mtd/devices/at91_dataflash.c 2007-07-29 07:18:10.000000000 +0200 -+++ linux-2.6.22.1/drivers/mtd/devices/at91_dataflash.c 2007-07-29 07:32:52.000000000 +0200 -@@ -161,12 +161,12 @@ - .mask_flags = MTD_WRITEABLE, /* read-only */ - }, - { -- .name = "kernel", -+ .name = "knlroot", - .offset = MTDPART_OFS_NXTBLK, -- .size = 5 * 32 * 8 * 1056, /* 5 sectors */ -+ .size = 0x320400, - }, - { -- .name = "filesystem", -+ .name = "jffs2", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL, /* rest = 26 sectors */ - } |