diff options
author | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-03-04 09:40:44 +0000 |
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committer | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-03-04 09:40:44 +0000 |
commit | af050ad637452346501799ea906111a41e9e4e12 (patch) | |
tree | 4fb95ac5deffb6f79aca8b56815c804acfb5259b /target/linux/ar71xx/patches-3.8/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch | |
parent | 5c88b794d6bb3926e80b4ad66e1b51d6bb386a98 (diff) |
ar71xx: use backported SPI patches
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35873 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-3.8/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch')
-rw-r--r-- | target/linux/ar71xx/patches-3.8/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.8/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch b/target/linux/ar71xx/patches-3.8/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch new file mode 100644 index 0000000000..393ffa5158 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch @@ -0,0 +1,31 @@ +From c7c943b1e3813ff5764ee6417a14530cb7cd6f57 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Thu, 27 Dec 2012 10:42:25 +0100 +Subject: [PATCH] spi/ath79: add missing HIGH->LOW SCK transition + +commit 72611db0eef21f4456d79ba302af4b34ea384f30 upstream. + +The 'ath79_spi_txrx_mode0' function does not +set the SCK signal to LOW at the end of a word +transfer. This causes communications errors with +certain devices (e.g. the PCF2123 RTC chip). + +The patch ensures that the SCK signal will be LOW. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Signed-off-by: Grant Likely <grant.likely@secretlab.ca> +--- + drivers/spi/spi-ath79.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -200,6 +200,8 @@ static u32 ath79_spi_txrx_mode0(struct s + ath79_spi_delay(sp, nsecs); + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); + ath79_spi_delay(sp, nsecs); ++ if (bits == 1) ++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); + + word <<= 1; + } |