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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2008-10-07 12:29:33 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2008-10-07 12:29:33 +0000
commit7d216315d8c894e6f485d106831b9d07ef2b1a87 (patch)
treec52deb38b4dc6f0694740d1649cc37b4ee3004d0 /target/linux/ar71xx/patches-2.6.27
parentc0c9902079afdd76ba4137877628f4395b392ab0 (diff)
[kernel] refresh 2.6.27 patches based on -rc9
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12892 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-2.6.27')
-rw-r--r--target/linux/ar71xx/patches-2.6.27/300-mips_fw_myloader.patch2
-rw-r--r--target/linux/ar71xx/patches-2.6.27/900-mips_multi_machine_support.patch6
-rw-r--r--target/linux/ar71xx/patches-2.6.27/901-get_c0_compare_irq_function.patch2
-rw-r--r--target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch73
4 files changed, 37 insertions, 46 deletions
diff --git a/target/linux/ar71xx/patches-2.6.27/300-mips_fw_myloader.patch b/target/linux/ar71xx/patches-2.6.27/300-mips_fw_myloader.patch
index bfff74aad1..a774d21945 100644
--- a/target/linux/ar71xx/patches-2.6.27/300-mips_fw_myloader.patch
+++ b/target/linux/ar71xx/patches-2.6.27/300-mips_fw_myloader.patch
@@ -10,7 +10,7 @@
libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
-@@ -781,6 +781,9 @@
+@@ -782,6 +782,9 @@
config MIPS_DISABLE_OBSOLETE_IDE
bool
diff --git a/target/linux/ar71xx/patches-2.6.27/900-mips_multi_machine_support.patch b/target/linux/ar71xx/patches-2.6.27/900-mips_multi_machine_support.patch
index df64d3ff5d..7bb410f1f3 100644
--- a/target/linux/ar71xx/patches-2.6.27/900-mips_multi_machine_support.patch
+++ b/target/linux/ar71xx/patches-2.6.27/900-mips_multi_machine_support.patch
@@ -113,7 +113,7 @@
+
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
-@@ -82,6 +82,7 @@
+@@ -83,6 +83,7 @@
obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
@@ -123,7 +123,7 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
-@@ -614,6 +614,7 @@
+@@ -615,6 +615,7 @@
endchoice
@@ -131,7 +131,7 @@
source "arch/mips/au1000/Kconfig"
source "arch/mips/basler/excite/Kconfig"
source "arch/mips/jazz/Kconfig"
-@@ -787,6 +788,9 @@
+@@ -788,6 +789,9 @@
config SYNC_R4K
bool
diff --git a/target/linux/ar71xx/patches-2.6.27/901-get_c0_compare_irq_function.patch b/target/linux/ar71xx/patches-2.6.27/901-get_c0_compare_irq_function.patch
index 52044c9570..c1fee78e28 100644
--- a/target/linux/ar71xx/patches-2.6.27/901-get_c0_compare_irq_function.patch
+++ b/target/linux/ar71xx/patches-2.6.27/901-get_c0_compare_irq_function.patch
@@ -8,7 +8,7 @@
extern void check_wait(void);
extern asmlinkage void r4k_wait(void);
-@@ -1482,6 +1483,8 @@
+@@ -1484,6 +1485,8 @@
*/
if (cpu_has_mips_r2) {
cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
diff --git a/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch b/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch
index bdf0d0fb69..564321c7c8 100644
--- a/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch
+++ b/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch
@@ -1,10 +1,9 @@
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -13,6 +13,22 @@
- #include <asm/smtc_ipi.h>
- #include <asm/time.h>
+@@ -15,6 +15,22 @@
+ #include <asm/cevt-r4k.h>
-+/*
+ /*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register. 4 time the
@@ -20,46 +19,38 @@
+ irq_disable_hazard(); \
+ } while (0)
+
- static int mips_next_event(unsigned long delta,
- struct clock_event_device *evt)
- {
-@@ -28,6 +44,7 @@
++/*
+ * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
+ * of these routines with SMTC-specific variants.
+ */
+@@ -30,6 +46,7 @@
cnt = read_c0_count();
cnt += delta;
write_c0_compare(cnt);
+ compare_change_hazard();
res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
- #ifdef CONFIG_MIPS_MT_SMTC
- evpe(vpflags);
-@@ -187,7 +204,7 @@
- */
- if (c0_compare_int_pending()) {
- write_c0_compare(read_c0_count());
-- irq_disable_hazard();
-+ compare_change_hazard();
- if (c0_compare_int_pending())
- return 0;
- }
-@@ -196,7 +213,7 @@
- cnt = read_c0_count();
- cnt += delta;
- write_c0_compare(cnt);
-- irq_disable_hazard();
-+ compare_change_hazard();
- if ((int)(read_c0_count() - cnt) < 0)
- break;
- /* increase delta if the timer was already expired */
-@@ -205,11 +222,12 @@
- while ((int)(read_c0_count() - cnt) <= 0)
- ; /* Wait for expiry */
-
-+ compare_change_hazard();
- if (!c0_compare_int_pending())
- return 0;
-
- write_c0_compare(read_c0_count());
-- irq_disable_hazard();
-+ compare_change_hazard();
- if (c0_compare_int_pending())
- return 0;
+ return res;
+ }
+@@ -99,22 +116,6 @@
+ return (read_c0_cause() >> cp0_compare_irq) & 0x100;
+ }
+-/*
+- * Compare interrupt can be routed and latched outside the core,
+- * so a single execution hazard barrier may not be enough to give
+- * it time to clear as seen in the Cause register. 4 time the
+- * pipeline depth seems reasonably conservative, and empirically
+- * works better in configurations with high CPU/bus clock ratios.
+- */
+-
+-#define compare_change_hazard() \
+- do { \
+- irq_disable_hazard(); \
+- irq_disable_hazard(); \
+- irq_disable_hazard(); \
+- irq_disable_hazard(); \
+- } while (0)
+-
+ int c0_compare_int_usable(void)
+ {
+ unsigned int delta;