diff options
| author | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-09-01 14:41:26 +0000 |
|---|---|---|
| committer | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-09-01 14:41:26 +0000 |
| commit | c5b95dd0e91944a32d67681e7e618ae3ce8d76ed (patch) | |
| tree | 2f7c32e8905230e23356c72c476a057b8b045743 /target/linux/ar71xx/files/include | |
| parent | 3fc481198cf10dfbd70072acd4710d828497065b (diff) | |
make openwrt boot on ar9130 (currently no ethernet yet)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12463 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/include')
| -rw-r--r-- | target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h index 22fd2e6d1e..af824d979a 100644 --- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h @@ -103,14 +103,21 @@ extern u32 ar71xx_ddr_freq; #define PLL_REG_ETH_EXT_CLK 0x18 #define PLL_REG_PCI_CLK 0x1c -#define PLL_DIV_SHIFT 3 -#define PLL_DIV_MASK 0x1f -#define CPU_DIV_SHIFT 16 -#define CPU_DIV_MASK 0x3 -#define DDR_DIV_SHIFT 18 -#define DDR_DIV_MASK 0x3 -#define AHB_DIV_SHIFT 20 -#define AHB_DIV_MASK 0x7 +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR91XX_PLL_DIV_SHIFT 0 +#define AR91XX_PLL_DIV_MASK 0x3ff +#define AR91XX_DDR_DIV_SHIFT 22 +#define AR91XX_DDR_DIV_MASK 0x3 +#define AR91XX_AHB_DIV_SHIFT 19 +#define AR91XX_AHB_DIV_MASK 0x1 extern void __iomem *ar71xx_pll_base; @@ -306,6 +313,7 @@ extern void ar71xx_ddr_flush(u32 reg); #define REV_ID_CHIP_AR7130 0xa0 #define REV_ID_CHIP_AR7141 0xa1 #define REV_ID_CHIP_AR7161 0xa2 +#define REV_ID_CHIP_AR9130 0xb0 #define REV_ID_REVISION_MASK 0x3 #define REV_ID_REVISION_SHIFT 2 |