amazon: work on pci controller

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19013 3c298f89-4303-0410-b956-a3cf2f4a3e73

2 files changed, 42 insertions, 44 deletions

diff --git a/target/linux/amazon/files/arch/mips/amazon/pci.c b/target/linux/amazon/files/arch/mips/amazon/pci.c
index a5596c80d4..1b2afb9d4f 100644
--- a/target/linux/amazon/files/arch/mips/amazon/pci.c
+++ b/target/linux/amazon/files/arch/mips/amazon/pci.c
@@ -36,7 +36,7 @@
 #endif
 #define AMAZON_PCI_MEM_SIZE    0x00400000
 #define AMAZON_PCI_IO_BASE     0xb2400000
-#define AMAZON_PCI_IO_SIZE     0x00002000
+#define AMAZON_PCI_IO_SIZE     0x00200000
 
 #define AMAZON_PCI_CFG_BUSNUM_SHF 16
 #define AMAZON_PCI_CFG_DEVNUM_SHF 11
@@ -45,27 +45,15 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
-static inline u32 amazon_r32(u32 addr)
-{
-	u32 *ptr = (u32 *) addr;
-	return __raw_readl(ptr);
-}
-
-static inline void amazon_w32(u32 addr, u32 val)
-{
-	u32 *ptr = (u32 *) addr;
-	__raw_writel(val, ptr);
-}
-
-
 static struct resource pci_io_resource = {
 	.name = "io pci IO space",
-#if 0
+#if 1
 	.start = AMAZON_PCI_IO_BASE,
 	.end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
-#endif
+#else
 	.start = 0,
-	.end = AMAZON_PCI_IO_SIZE - 1,
+	.end = 0x00002000 - 1,
+#endif
 	.flags = IORESOURCE_IO
 };
 
@@ -76,15 +64,6 @@ static struct resource pci_mem_resource = {
 	.flags = IORESOURCE_MEM
 };
 
-static inline u32 amazon_pci_swap(u32 val)
-{
-#ifdef CONFIG_AMAZON_PCI_HW_SWAP
-	return swab32(val);
-#else
-	return val;
-#endif
-}
-
 static int amazon_pci_config_access(unsigned char access_type,
 	struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
 {
@@ -92,31 +71,43 @@ static int amazon_pci_config_access(unsigned char access_type,
 	u32 pci_addr;
 	u32 val;
 	int ret;
-   
+
 	/* Amazon support slot from 0 to 15 */
 	/* devfn 0 & 0x20 is itself */
-	if ((bus->number != 0) || (devfn == 0) || (devfn == 0x20))
+	if ((bus->number != 0) || (devfn > 0x7f) || (devfn == 0) || (devfn == 0x20))
 		return 1;
 
-	pci_addr=AMAZON_PCI_CFG_BASE |
+	local_irq_save(flags);
+
+	pci_addr = AMAZON_PCI_CFG_BASE |
 		bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
 		devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
 		(where & ~0x3);
-    
-	local_irq_save(flags);
-	if (access_type == PCI_ACCESS_WRITE) {
-		val = amazon_pci_swap(*data);
+
+	if (access_type == PCI_ACCESS_WRITE)
+	{
+#ifdef CONFIG_SWAP_IO_SPACE
+		val = swab32(*data);
+#endif
 		ret = put_dbe(val, (u32 *)pci_addr);
 	} else {
 		ret = get_dbe(val, (u32 *)pci_addr);
-		*data = amazon_pci_swap(val);
+#ifdef CONFIG_SWAP_IO_SPACE
+		*data = swab32(val);
+#else
+		*data = val;
+#endif
 	}
 
-	amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
-	amazon_w32(STATUS_COMMAND_ADDR, amazon_r32(STATUS_COMMAND_ADDR));
-	amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
+	amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
+	amazon_writel(amazon_readl(STATUS_COMMAND_ADDR), STATUS_COMMAND_ADDR);
+	amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
+	mb();
 	local_irq_restore(flags);
 
+	if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
+		return 1;
+
 	return ret; 
 }
 
@@ -172,7 +163,9 @@ static struct pci_ops amazon_pci_ops = {
 static struct pci_controller amazon_pci_controller = {
 	.pci_ops = &amazon_pci_ops,
 	.mem_resource = &pci_mem_resource,
-	.io_resource = &pci_io_resource
+	.mem_offset	= 0x00000000UL,
+	.io_resource = &pci_io_resource,
+	.io_offset	= 0x00000000UL,
 };
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
@@ -237,13 +230,13 @@ int __init amazon_pci_init(void)
 {
 	u32 temp_buffer;
 
-#ifdef CONFIG_AMAZON_PCI_HW_SWAP
+#ifdef CONFIG_SWAP_IO_SPACE
 	AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
 	wmb();
 #endif
 
 	AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
-	amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
+	amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
 
 	AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
 
@@ -271,15 +264,15 @@ int __init amazon_pci_init(void)
 	AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5) = 0xb2500000;
 	AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
 	AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
-	   
-	AMAZON_PCI_REG32(BAR11_MASK) = 0x0f000008;
+
+	AMAZON_PCI_REG32(BAR11_MASK) = 0x0c000008;
 	AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
 	AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
-	amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
+	amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
 	//use 8 dw burse length
 	AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
 
-	amazon_pci_controller.io_map_base = (unsigned long)ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE);
+	amazon_pci_controller.io_map_base = (unsigned long)ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE - 1);
 	register_pci_controller(&amazon_pci_controller);
 	return 0;
 }
diff --git a/target/linux/amazon/files/arch/mips/amazon/setup.c b/target/linux/amazon/files/arch/mips/amazon/setup.c
index a96b565c69..45ff2544fc 100644
--- a/target/linux/amazon/files/arch/mips/amazon/setup.c
+++ b/target/linux/amazon/files/arch/mips/amazon/setup.c
@@ -155,6 +155,11 @@ void __init plat_mem_setup(void)
 	amazon_writel(0x3fff, AMAZON_PMU_PWDCR);
 	//reenable trace capability
 	part_no = readl(AMAZON_BCU_ECON);
+
+	ioport_resource.start = IOPORT_RESOURCE_START;
+	ioport_resource.end = IOPORT_RESOURCE_END;
+	iomem_resource.start = IOMEM_RESOURCE_START;
+	iomem_resource.end = IOMEM_RESOURCE_END;
 }
 
 static void amazon_machine_restart(char *command)