add uboot-lantiq (based on a patch contributed by Lantiq)

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20561 3c298f89-4303-0410-b956-a3cf2f4a3e73

4 files changed, 882 insertions, 0 deletions

diff --git a/package/uboot-lantiq/files/drivers/net/ifx_etop.c b/package/uboot-lantiq/files/drivers/net/ifx_etop.c
new file mode 100644
index 0000000000..9a9e51fa04
--- /dev/null
+++ b/package/uboot-lantiq/files/drivers/net/ifx_etop.c
@@ -0,0 +1,374 @@
+/*
+ * Lantiq CPE device ethernet driver.
+ * Supposed to work on Twinpass/Danube.
+ *
+ * Based on INCA-IP driver:
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2010
+ * Thomas Langer, Ralph Hempel 
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <malloc.h>
+#include <net.h>
+#include <miiphy.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+
+#include "ifx_etop.h"
+
+#define TX_CHAN_NO   7
+#define RX_CHAN_NO   6
+
+#define NUM_RX_DESC	PKTBUFSRX
+#define NUM_TX_DESC	8
+#define TOUT_LOOP	100
+
+typedef struct
+{
+	union
+	{
+		struct
+		{
+			volatile u32 OWN	:1;
+			volatile u32 C		:1;
+			volatile u32 Sop	:1;
+			volatile u32 Eop	:1;
+			volatile u32 reserved	:3;
+			volatile u32 Byteoffset	:2;
+			volatile u32 reserve	:7;
+			volatile u32 DataLen	:16;
+		}field;
+
+		volatile u32 word;
+	}status;
+
+	volatile u32 DataPtr;
+} dma_rx_descriptor_t;
+
+typedef struct
+{
+	union
+	{
+		struct
+		{
+			volatile u32 OWN	:1;
+			volatile u32 C		:1;
+			volatile u32 Sop	:1;
+			volatile u32 Eop	:1;
+			volatile u32 Byteoffset	:5;
+			volatile u32 reserved	:7;
+			volatile u32 DataLen	:16;
+		}field;
+
+		volatile u32 word;
+	}status;
+
+	volatile u32 DataPtr;
+} dma_tx_descriptor_t;
+
+static volatile dma_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8)));
+static volatile dma_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8)));
+static int tx_num, rx_num;
+
+static volatile IfxDMA_t *pDma = (IfxDMA_t *)CKSEG1ADDR(DANUBE_DMA_BASE);
+
+static int lq_eth_init(struct eth_device *dev, bd_t * bis);
+static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length);
+static int lq_eth_recv(struct eth_device *dev);
+static void lq_eth_halt(struct eth_device *dev);
+static void lq_eth_init_chip(void);
+static void lq_eth_init_dma(void);
+
+static int lq_eth_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
+{
+	u32 timeout = 50000;
+	u32 phy, reg;
+
+	if ((phyAddr > 0x1F) || (regAddr > 0x1F) || (retVal == NULL))
+		return -1;
+
+	phy = (phyAddr & 0x1F) << 21;
+	reg = (regAddr & 0x1F) << 16;
+
+	*ETOP_MDIO_ACC = 0xC0000000 | phy | reg;
+	while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
+		udelay(10);
+
+	if (timeout==0) {
+		*retVal = 0;
+		return -1;
+	}
+	*retVal = *ETOP_MDIO_ACC & 0xFFFF;
+	return 0;
+}
+
+static int lq_eth_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data)
+{
+	u32 timeout = 50000;
+	u32 phy, reg;
+
+	if ((phyAddr > 0x1F) || (regAddr > 0x1F))
+		return -1;
+
+	phy = (phyAddr & 0x1F) << 21;
+	reg = (regAddr & 0x1F) << 16;
+
+	*ETOP_MDIO_ACC = 0x80000000 | phy | reg | data;
+	while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
+		udelay(10);
+
+	if (timeout==0)
+		return -1;
+	return 0;
+}
+
+
+int lq_eth_initialize(bd_t * bis)
+{
+	struct eth_device *dev;
+
+	debug("Entered lq_eth_initialize()\n");
+
+	if (!(dev = malloc (sizeof *dev))) {
+		printf("Failed to allocate memory\n");
+		return -1;
+	}
+	memset(dev, 0, sizeof(*dev));
+
+	sprintf(dev->name, "lq_cpe_eth");
+	dev->init = lq_eth_init;
+	dev->halt = lq_eth_halt;
+	dev->send = lq_eth_send;
+	dev->recv = lq_eth_recv;
+
+	eth_register(dev);
+
+#if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
+	/* register mii command access routines */
+	miiphy_register(dev->name,
+			lq_eth_miiphy_read, lq_eth_miiphy_write);
+#endif
+
+	lq_eth_init_dma();
+	lq_eth_init_chip();
+
+	return 0;
+}
+
+static int lq_eth_init(struct eth_device *dev, bd_t * bis)
+{
+	int i;
+	uchar *enetaddr = dev->enetaddr;
+
+	debug("lq_eth_init %x:%x:%x:%x:%x:%x\n",
+		enetaddr[0], enetaddr[1], enetaddr[2], enetaddr[3], enetaddr[4], enetaddr[5]);
+
+	*ENET_MAC_DA0 = (enetaddr[0]<<24) + (enetaddr[1]<<16) + (enetaddr[2]<< 8) + enetaddr[3];
+	*ENET_MAC_DA1 = (enetaddr[4]<<24) + (enetaddr[5]<<16);
+	*ENETS_CFG |= 1<<28;	/* enable filter for unicast packets */
+
+	tx_num=0;
+	rx_num=0;
+
+	for(i=0;i < NUM_RX_DESC; i++) {
+		dma_rx_descriptor_t * rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[i]);
+		rx_desc->status.word=0;
+		rx_desc->status.field.OWN=1;
+		rx_desc->status.field.DataLen=PKTSIZE_ALIGN;   /* 1536  */
+		rx_desc->DataPtr=(u32)CKSEG1ADDR(NetRxPackets[i]);
+		NetRxPackets[i][0] = 0xAA;
+	}
+
+	/* Reset DMA */
+	dma_writel(dma_cs, RX_CHAN_NO);
+	dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
+	dma_writel(dma_cpoll, 0x80000040);
+	/*set descriptor base*/
+	dma_writel(dma_cdba, (u32)rx_des_ring);
+	dma_writel(dma_cdlen, NUM_RX_DESC);
+	dma_writel(dma_cie, 0);
+	dma_writel(dma_cctrl, 0x30000);
+
+	for(i=0;i < NUM_TX_DESC; i++) {
+		dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[i]);
+		memset(tx_desc, 0, sizeof(tx_des_ring[0]));
+	}
+
+	dma_writel(dma_cs, TX_CHAN_NO);
+	dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
+	dma_writel(dma_cpoll, 0x80000040);
+	dma_writel(dma_cdba, (u32)tx_des_ring);
+	dma_writel(dma_cdlen, NUM_TX_DESC);
+	dma_writel(dma_cie, 0);
+	dma_writel(dma_cctrl, 0x30100);
+
+	/* turn on DMA rx & tx channel
+	*/
+	dma_writel(dma_cs, RX_CHAN_NO);
+	dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1); /*reset and turn on the channel*/
+
+	return 0;
+}
+
+static void lq_eth_halt(struct eth_device *dev)
+{
+	int i;
+
+	debug("lq_eth_halt()\n");
+
+	for(i=0;i<8;i++) {
+		dma_writel(dma_cs, i);
+		dma_writel(dma_cctrl, dma_readl(dma_cctrl) & ~1);/*stop the dma channel*/
+	}
+}
+
+static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length)
+{
+	int i;
+	int res = -1;
+	volatile dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[tx_num]);
+
+	if (length <= 0) {
+		printf ("%s: bad packet size: %d\n", dev->name, length);
+		goto Done;
+	}
+
+	for(i=0; tx_desc->status.field.OWN==1; i++) {
+		if (i>=TOUT_LOOP) {
+			printf("NO Tx Descriptor...");
+			goto Done;
+		}
+	}
+
+	tx_desc->status.field.Sop=1;
+	tx_desc->status.field.Eop=1;
+	tx_desc->status.field.C=0;
+	tx_desc->DataPtr = (u32)CKSEG1ADDR(packet);
+	if (length<60)
+		tx_desc->status.field.DataLen = 60;
+	else
+		tx_desc->status.field.DataLen = (u32)length;
+
+	flush_cache((u32)packet, tx_desc->status.field.DataLen);
+	tx_desc->status.field.OWN=1;
+
+	res=length;
+	tx_num++;
+	if (tx_num==NUM_TX_DESC) tx_num=0;
+
+	dma_writel(dma_cs, TX_CHAN_NO);
+	if (!(dma_readl(dma_cctrl) & 1)) {
+		dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1);
+	}
+
+Done:
+	return res;
+}
+
+static int lq_eth_recv(struct eth_device *dev)
+{
+	int length  = 0;
+	volatile dma_rx_descriptor_t * rx_desc;
+
+	rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[rx_num]);
+
+	if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1)) {
+		return 0;
+	}
+	length = rx_desc->status.field.DataLen;
+	if (length > 4) {
+		invalidate_dcache_range((u32)CKSEG0ADDR(rx_desc->DataPtr), (u32) CKSEG0ADDR(rx_desc->DataPtr) + length);
+		NetReceive(NetRxPackets[rx_num], length);
+	} else {
+		printf("ERROR: Invalid rx packet length.\n");
+	}
+
+	rx_desc->status.field.Sop=0;
+	rx_desc->status.field.Eop=0;
+	rx_desc->status.field.C=0;
+	rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
+	rx_desc->status.field.OWN=1;
+
+	rx_num++;
+	if (rx_num == NUM_RX_DESC)
+		rx_num=0;
+
+	return length;
+}
+
+static void lq_eth_init_chip(void)
+{
+	*ETOP_MDIO_CFG &= ~0x6;
+	*ENET_MAC_CFG = 0x187;
+
+	// turn on port0, set to rmii and turn off port1.
+#ifdef CONFIG_RMII
+	*ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x0000000A;
+#else
+	*ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x00000008;
+#endif
+
+	*ETOP_IG_PLEN_CTRL = 0x004005EE; // set packetlen.
+	*ENET_MAC_CFG |= 1<<11; /*enable the crc*/
+	return;
+}
+
+static void lq_eth_init_dma(void)
+{
+	/* Reset DMA */
+	dma_writel(dma_ctrl, dma_readl(dma_ctrl) | 1);
+	dma_writel(dma_irnen, 0);/*disable all the interrupts first*/
+
+	/* Clear Interrupt Status Register */
+	dma_writel(dma_irncr, 0xfffff);
+	/*disable all the dma interrupts*/
+	dma_writel(dma_irnen, 0);
+	/*disable channel 0 and channel 1 interrupts*/
+
+	dma_writel(dma_cs, RX_CHAN_NO);
+	dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
+	dma_writel(dma_cpoll, 0x80000040);
+	/*set descriptor base*/
+	dma_writel(dma_cdba, (u32)rx_des_ring);
+	dma_writel(dma_cdlen, NUM_RX_DESC);
+	dma_writel(dma_cie, 0);
+	dma_writel(dma_cctrl, 0x30000);
+
+	dma_writel(dma_cs, TX_CHAN_NO);
+	dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
+	dma_writel(dma_cpoll, 0x80000040);
+	dma_writel(dma_cdba, (u32)tx_des_ring);
+	dma_writel(dma_cdlen, NUM_TX_DESC);
+	dma_writel(dma_cie, 0);
+	dma_writel(dma_cctrl, 0x30100);
+	/*enable the poll function and set the poll counter*/
+	//dma_writel(DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4);
+	/*set port properties, enable endian conversion for switch*/
+	dma_writel(dma_ps, 0);
+	dma_writel(dma_pctrl, dma_readl(dma_pctrl) | (0xf<<8));/*enable 32 bit endian conversion*/
+
+	return;
+}
diff --git a/package/uboot-lantiq/files/drivers/net/ifx_etop.h b/package/uboot-lantiq/files/drivers/net/ifx_etop.h
new file mode 100644
index 0000000000..99708684e5
--- /dev/null
+++ b/package/uboot-lantiq/files/drivers/net/ifx_etop.h
@@ -0,0 +1,91 @@
+/*
+ * Lantiq switch ethernet driver for Danube family.
+ *
+ * Based on INCA-IP driver:
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __DRIVERS_IFX_SW_H__
+#define __DRIVERS_IFX_SW_H__
+
+#define DANUBE_PPE32_BASE  0xBE180000
+#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE   (DANUBE_PPE32_BASE + (0x4000 * 4))
+
+#define ETOP_MDIO_CFG           ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
+#define ETOP_MDIO_ACC           ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
+#define ETOP_CFG                ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
+#define ETOP_IG_VLAN_COS        ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
+#define ETOP_IG_DSCP_COS3       ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
+#define ETOP_IG_DSCP_COS2       ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
+#define ETOP_IG_DSCP_COS1       ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
+#define ETOP_IG_DSCP_COS0       ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
+#define ETOP_IG_PLEN_CTRL       ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
+#define ETOP_ISR                ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
+#define ETOP_IER                ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
+#define ETOP_VPID               ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
+#define ENET_MAC_CFG            ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
+#define ENETS_DBA               ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
+#define ENETS_CBA               ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
+#define ENETS_CFG               ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
+#define ENETS_PGCNT             ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
+#define ENETS_PKTCNT            ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
+#define ENETS_BUF_CTRL          ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
+#define ENETS_COS_CFG           ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
+#define ENETS_IGDROP            ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
+#define ENETS_IGERR             ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
+#define ENET_MAC_DA0            ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
+#define ENET_MAC_DA1            ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
+
+
+
+#define DANUBE_DMA_BASE                 0xBE104100
+
+typedef struct IfxDMA_s
+{
+	unsigned long  dma_clc;                            /*0x0000*/
+	unsigned long  dma_rsvd1[1];   /* for mapping */   /*0x0004*/
+	unsigned long  dma_id;                             /*0x0008*/
+	unsigned long  dma_rsvd2[1];   /* for mapping */   /*0x000C*/
+	unsigned long  dma_ctrl;                           /*0x0010*/
+	unsigned long  dma_cpoll;                          /*0x0014*/
+	unsigned long  dma_cs;                             /*0x0018*/
+	unsigned long  dma_cctrl;                          /*0x001C*/
+	unsigned long  dma_cdba;                           /*0x0020*/
+	unsigned long  dma_cdlen;                          /*0x0024*/
+	unsigned long  dma_cis;                            /*0x0028*/
+	unsigned long  dma_cie;                            /*0x002C*/
+	unsigned long  dma_rsvd3[4];   /* for mapping */   /*0x0030*/
+	unsigned long  dma_ps;                             /*0x0040*/
+	unsigned long  dma_pctrl;                          /*0x0044*/
+	unsigned long  dma_rsvd4[43];  /* for mapping */   /*0x0048*/
+	unsigned long  dma_irnen;                          /*0x00F4*/
+	unsigned long  dma_irncr;                          /*0x00F8*/
+	unsigned long  dma_irnicr;                         /*0x00FC*/
+} IfxDMA_t;
+
+/* Register access macros */
+#define dma_readl(reg)				\
+	readl(&pDma->reg)
+#define dma_writel(reg,value)			\
+	writel((value), &pDma->reg)
+
+int lq_eth_initialize(bd_t * bis);
+
+#endif /* __DRIVERS_IFX_SW_H__ */
diff --git a/package/uboot-lantiq/files/drivers/serial/ifx_asc.c b/package/uboot-lantiq/files/drivers/serial/ifx_asc.c
new file mode 100644
index 0000000000..5c13f26622
--- /dev/null
+++ b/package/uboot-lantiq/files/drivers/serial/ifx_asc.c
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2009
+ * Infineon Technologies AG, http://www.infineon.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+
+#include "ifx_asc.h"
+
+#define SET_BIT(reg, mask)			asc_writel(reg, asc_readl(reg) | (mask))
+#define CLEAR_BIT(reg, mask)			asc_writel(reg, asc_readl(reg) & (~mask))
+#define SET_BITFIELD(reg, mask, off, val)	asc_writel(reg, (asc_readl(reg) & (~mask)) | (val << off) )
+
+#undef DEBUG_ASC_RAW
+#ifdef DEBUG_ASC_RAW
+#define DEBUG_ASC_RAW_RX_BUF			0xA0800000
+#define DEBUG_ASC_RAW_TX_BUF			0xA0900000
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static IfxAsc_t *pAsc = (IfxAsc_t *)CKSEG1ADDR(CONFIG_SYS_IFX_ASC_BASE);
+
+/*
+ *             FDV            fASC
+ * BaudRate = ----- * --------------------
+ *             512    16 * (ReloadValue+1)
+ */
+
+/*
+ *                  FDV          fASC
+ * ReloadValue = ( ----- * --------------- ) - 1
+ *                  512     16 * BaudRate
+ */
+static void serial_divs(u32 baudrate, u32 fasc, u32 *pfdv, u32 *preload)
+{
+   u32 clock = fasc / 16;
+
+   u32 fdv; /* best fdv */
+   u32 reload = 0; /* best reload */
+   u32 diff; /* smallest diff */
+   u32 idiff; /* current diff */
+   u32 ireload; /* current reload */
+   u32 i; /* current fdv */
+   u32 result; /* current resulting baudrate */
+
+   if (clock > 0x7FFFFF)
+      clock /= 512;
+   else
+      baudrate *= 512;
+
+   fdv = 512; /* start with 1:1 fraction */
+   diff = baudrate; /* highest possible */
+
+   /* i is the test fdv value -- start with the largest possible */
+   for (i = 512; i > 0; i--)
+   {
+      ireload = (clock * i) / baudrate;
+      if (ireload < 1)
+         break; /* already invalid */
+      result = (clock * i) / ireload;
+
+      idiff = (result > baudrate) ? (result - baudrate) : (baudrate - result);
+      if (idiff == 0)
+      {
+         fdv = i;
+         reload = ireload;
+         break; /* can't do better */
+      }
+      else if (idiff < diff)
+      {
+         fdv = i; /* best so far */
+         reload = ireload;
+         diff = idiff; /* update lowest diff*/
+      }
+   }
+
+   *pfdv = (fdv == 512) ? 0 : fdv;
+   *preload = reload - 1;
+}
+
+
+void serial_setbrg (void)
+{
+	u32 ReloadValue, fdv;
+
+	serial_divs(gd->baudrate, get_bus_freq(0), &fdv, &ReloadValue);
+
+	/* Disable Baud Rate Generator; BG should only be written when R=0 */
+	CLEAR_BIT(asc_con, ASCCON_R);
+
+	/* Enable Fractional Divider */
+	SET_BIT(asc_con, ASCCON_FDE);	/* FDE = 1 */
+
+	/* Set fractional divider value */
+	asc_writel(asc_fdv, fdv & ASCFDV_VALUE_MASK);
+
+	/* Set reload value in BG */
+	asc_writel(asc_bg, ReloadValue);
+
+	/* Enable Baud Rate Generator */
+	SET_BIT(asc_con, ASCCON_R);	/* R = 1 */
+}
+
+
+int serial_init (void)
+{
+
+	/* and we have to set CLC register*/
+	CLEAR_BIT(asc_clc, ASCCLC_DISS);
+	SET_BITFIELD(asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
+
+	/* initialy we are in async mode */
+	asc_writel(asc_con, ASCCON_M_8ASYNC);
+
+	/* select input port */
+	asc_writel(asc_pisel, CONSOLE_TTY & 0x1);
+
+	/* TXFIFO's filling level */
+	SET_BITFIELD(asc_txfcon, ASCTXFCON_TXFITLMASK,
+			ASCTXFCON_TXFITLOFF, ASC_TXFIFO_FL);
+	/* enable TXFIFO */
+	SET_BIT(asc_txfcon, ASCTXFCON_TXFEN);
+
+	/* RXFIFO's filling level */
+	SET_BITFIELD(asc_txfcon, ASCRXFCON_RXFITLMASK,
+			ASCRXFCON_RXFITLOFF, ASC_RXFIFO_FL);
+	/* enable RXFIFO */
+	SET_BIT(asc_rxfcon, ASCRXFCON_RXFEN);
+
+	/* set baud rate */
+	serial_setbrg();
+
+	/* enable error signals &  Receiver enable  */
+	SET_BIT(asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
+
+	return 0;
+}
+
+
+void serial_putc (const char c)
+{
+	u32 txFl = 0;
+#ifdef DEBUG_ASC_RAW
+	static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
+	*debug++=c;
+#endif
+	if (c == '\n')
+		serial_putc ('\r');
+	/* check do we have a free space in the TX FIFO */
+	/* get current filling level */
+	do {
+		txFl = ( asc_readl(asc_fstat) & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
+	}
+	while ( txFl == ASC_TXFIFO_FULL );
+
+	asc_writel(asc_tbuf, c); /* write char to Transmit Buffer Register */
+
+	/* check for errors */
+	if ( asc_readl(asc_state) & ASCSTATE_TOE ) {
+		SET_BIT(asc_whbstate, ASCWHBSTATE_CLRTOE);
+		return;
+	}
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int serial_getc (void)
+{
+	char c;
+	while ((asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 );
+	c = (char)(asc_readl(asc_rbuf) & 0xff);
+
+#ifdef 	DEBUG_ASC_RAW
+	static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
+	*debug++=c;
+#endif
+	return c;
+}
+
+
+int serial_tstc (void)
+{
+	int res = 1;
+
+	if ( (asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ) {
+		res = 0;
+	}
+	return res;
+}
diff --git a/package/uboot-lantiq/files/drivers/serial/ifx_asc.h b/package/uboot-lantiq/files/drivers/serial/ifx_asc.h
new file mode 100644
index 0000000000..2d3a49e1e5
--- /dev/null
+++ b/package/uboot-lantiq/files/drivers/serial/ifx_asc.h
@@ -0,0 +1,199 @@
+/*****************************************************************************
+ * DANUBE BootROM
+ * Copyright (c) 2005, Infineon Technologies AG, All rights reserved
+ * IFAP DC COM SD
+ *****************************************************************************/
+#ifndef __ASC_H
+#define __ASC_H
+
+/* channel operating modes */
+#define	ASCOPT_CSIZE		0x00000003
+#define	ASCOPT_CS7		0x00000001
+#define	ASCOPT_CS8		0x00000002
+#define	ASCOPT_PARENB		0x00000004
+#define	ASCOPT_STOPB		0x00000008
+#define	ASCOPT_PARODD		0x00000010
+#define	ASCOPT_CREAD		0x00000020
+
+#define ASC_OPTIONS		(ASCOPT_CREAD | ASCOPT_CS8)
+
+/* ASC input select (0 or 1) */
+#define CONSOLE_TTY		0
+
+#define ASC_TXFIFO_FL		1
+#define ASC_RXFIFO_FL		1
+#define ASC_TXFIFO_FULL		16
+
+/* CLC register's bits and bitfields */
+#define ASCCLC_DISR		0x00000001
+#define ASCCLC_DISS		0x00000002
+#define ASCCLC_RMCMASK		0x0000FF00
+#define ASCCLC_RMCOFFSET	8
+
+/* CON register's bits and bitfields */
+#define ASCCON_MODEMASK		0x0000000f
+#define ASCCON_M_8ASYNC		0x0
+#define ASCCON_M_8IRDA		0x1
+#define ASCCON_M_7ASYNC		0x2
+#define ASCCON_M_7IRDA		0x3
+#define ASCCON_WLSMASK		0x0000000c
+#define ASCCON_WLSOFFSET	2
+#define ASCCON_WLS_8BIT		0x0
+#define ASCCON_WLS_7BIT		0x1
+#define ASCCON_PEN		0x00000010
+#define ASCCON_ODD		0x00000020
+#define ASCCON_SP		0x00000040
+#define ASCCON_STP		0x00000080
+#define ASCCON_BRS		0x00000100
+#define ASCCON_FDE		0x00000200
+#define ASCCON_ERRCLK		0x00000400
+#define ASCCON_EMMASK		0x00001800
+#define ASCCON_EMOFFSET		11
+#define ASCCON_EM_ECHO_OFF	0x0
+#define ASCCON_EM_ECHO_AB	0x1
+#define ASCCON_EM_ECHO_ON	0x2
+#define ASCCON_LB		0x00002000
+#define ASCCON_ACO 		0x00004000
+#define ASCCON_R		0x00008000
+#define ASCCON_PAL		0x00010000
+#define ASCCON_FEN		0x00020000
+#define ASCCON_RUEN		0x00040000
+#define ASCCON_ROEN		0x00080000
+#define ASCCON_TOEN		0x00100000
+#define ASCCON_BEN		0x00200000
+#define ASCCON_TXINV		0x01000000
+#define ASCCON_RXINV		0x02000000
+#define ASCCON_TXMSB		0x04000000
+#define ASCCON_RXMSB		0x08000000
+
+/* STATE register's bits and bitfields */
+#define ASCSTATE_REN		0x00000001
+#define ASCSTATE_PE		0x00010000
+#define ASCSTATE_FE		0x00020000
+#define ASCSTATE_RUE		0x00040000
+#define ASCSTATE_ROE		0x00080000
+#define ASCSTATE_TOE		0x00100000
+#define ASCSTATE_BE		0x00200000
+#define ASCSTATE_TXBVMASK	0x07000000
+#define ASCSTATE_TXBVOFFSET	24
+#define ASCSTATE_TXEOM		0x08000000
+#define ASCSTATE_RXBVMASK	0x70000000
+#define ASCSTATE_RXBVOFFSET	28
+#define ASCSTATE_RXEOM		0x80000000
+
+/* WHBSTATE register's bits and bitfields */
+#define ASCWHBSTATE_CLRREN	0x00000001
+#define ASCWHBSTATE_SETREN	0x00000002
+#define ASCWHBSTATE_CLRPE	0x00000004
+#define ASCWHBSTATE_CLRFE	0x00000008
+#define ASCWHBSTATE_CLRRUE	0x00000010
+#define ASCWHBSTATE_CLRROE	0x00000020
+#define ASCWHBSTATE_CLRTOE	0x00000040
+#define ASCWHBSTATE_CLRBE	0x00000080
+#define ASCWHBSTATE_SETPE	0x00000100
+#define ASCWHBSTATE_SETFE	0x00000200
+#define ASCWHBSTATE_SETRUE	0x00000400
+#define ASCWHBSTATE_SETROE	0x00000800
+#define ASCWHBSTATE_SETTOE	0x00001000
+#define ASCWHBSTATE_SETBE	0x00002000
+
+/* ABCON register's bits and bitfields */
+#define ASCABCON_ABEN		0x0001
+#define ASCABCON_AUREN		0x0002
+#define ASCABCON_ABSTEN		0x0004
+#define ASCABCON_ABDETEN	0x0008
+#define ASCABCON_FCDETEN	0x0010
+
+/* FDV register mask, offset and bitfields*/
+#define ASCFDV_VALUE_MASK	0x000001FF
+
+/* WHBABCON register's bits and bitfields */
+#define ASCWHBABCON_CLRABEN	0x0001
+#define ASCWHBABCON_SETABEN	0x0002
+
+/* ABSTAT register's bits and bitfields */
+#define ASCABSTAT_FCSDET	0x0001
+#define ASCABSTAT_FCCDET	0x0002
+#define ASCABSTAT_SCSDET	0x0004
+#define ASCABSTAT_SCCDET	0x0008
+#define ASCABSTAT_DETWAIT	0x0010
+
+/* WHBABSTAT register's bits and bitfields */
+#define ASCWHBABSTAT_CLRFCSDET	0x0001
+#define ASCWHBABSTAT_SETFCSDET	0x0002
+#define ASCWHBABSTAT_CLRFCCDET	0x0004
+#define ASCWHBABSTAT_SETFCCDET	0x0008
+#define ASCWHBABSTAT_CLRSCSDET	0x0010
+#define ASCWHBABSTAT_SETSCSDET	0x0020
+#define ASCWHBABSTAT_CLRSCCDET	0x0040
+#define ASCWHBABSTAT_SETSCCDET	0x0080
+#define ASCWHBABSTAT_CLRDETWAIT	0x0100
+#define ASCWHBABSTAT_SETDETWAIT	0x0200
+
+/* TXFCON register's bits and bitfields */
+#define ASCTXFCON_TXFIFO1       0x00000400
+#define ASCTXFCON_TXFEN         0x0001
+#define ASCTXFCON_TXFFLU        0x0002
+#define ASCTXFCON_TXFITLMASK    0x3F00
+#define ASCTXFCON_TXFITLOFF     8
+
+/* RXFCON register's bits and bitfields */
+#define ASCRXFCON_RXFIFO1       0x00000400
+#define ASCRXFCON_RXFEN         0x0001
+#define ASCRXFCON_RXFFLU        0x0002
+#define ASCRXFCON_RXFITLMASK    0x3F00
+#define ASCRXFCON_RXFITLOFF     8
+
+/* FSTAT register's bits and bitfields */
+#define ASCFSTAT_RXFFLMASK      0x003F
+#define ASCFSTAT_TXFFLMASK      0x3F00
+#define ASCFSTAT_TXFFLOFF       8
+
+typedef struct IfxAsc_s
+{
+	unsigned long  asc_clc;                            /*0x0000*/
+	unsigned long  asc_pisel;                          /*0x0004*/
+	unsigned long  asc_id;                             /*0x0008*/
+	unsigned long  asc_rsvd1[1];   /* for mapping */   /*0x000C*/
+	unsigned long  asc_con;                            /*0x0010*/
+	unsigned long  asc_state;                          /*0x0014*/
+	unsigned long  asc_whbstate;                       /*0x0018*/
+	unsigned long  asc_rsvd2[1];   /* for mapping */   /*0x001C*/
+	unsigned long  asc_tbuf;                           /*0x0020*/
+	unsigned long  asc_rbuf;                           /*0x0024*/
+	unsigned long  asc_rsvd3[2];   /* for mapping */   /*0x0028*/
+	unsigned long  asc_abcon;                          /*0x0030*/
+	unsigned long  asc_abstat;     /* not used */      /*0x0034*/
+	unsigned long  asc_whbabcon;                       /*0x0038*/
+	unsigned long  asc_whbabstat;  /* not used */      /*0x003C*/
+	unsigned long  asc_rxfcon;                         /*0x0040*/
+	unsigned long  asc_txfcon;                         /*0x0044*/
+	unsigned long  asc_fstat;                          /*0x0048*/
+	unsigned long  asc_rsvd4[1];   /* for mapping */   /*0x004C*/
+	unsigned long  asc_bg;                             /*0x0050*/
+	unsigned long  asc_bg_timer;                       /*0x0054*/
+	unsigned long  asc_fdv;                            /*0x0058*/
+	unsigned long  asc_pmw;                            /*0x005C*/
+	unsigned long  asc_modcon;                         /*0x0060*/
+	unsigned long  asc_modstat;                        /*0x0064*/
+	unsigned long  asc_rsvd5[2];   /* for mapping */   /*0x0068*/
+	unsigned long  asc_sfcc;                           /*0x0070*/
+	unsigned long  asc_rsvd6[3];   /* for mapping */   /*0x0074*/
+	unsigned long  asc_eomcon;                         /*0x0080*/
+	unsigned long  asc_rsvd7[26];   /* for mapping */  /*0x0084*/
+	unsigned long  asc_dmacon;                         /*0x00EC*/
+	unsigned long  asc_rsvd8[1];   /* for mapping */   /*0x00F0*/
+	unsigned long  asc_irnen;                          /*0x00F4*/
+	unsigned long  asc_irnicr;                         /*0x00F8*/
+	unsigned long  asc_irncr;                          /*0x00FC*/
+} IfxAsc_t;
+
+
+/* Register access macros */
+#define asc_readl(reg)				\
+	readl(&pAsc->reg)
+#define asc_writel(reg,value)			\
+	writel((value), &pAsc->reg)
+
+
+#endif /* __ASC_H */