[lantiq] drop unmaintained packages

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33723 3c298f89-4303-0410-b956-a3cf2f4a3e73

45 files changed, 0 insertions, 7566 deletions

diff --git a/package/uboot-lantiq/files/board/arcadyan/Makefile b/package/uboot-lantiq/files/board/arcadyan/Makefile
deleted file mode 100644
index 0038ac4d2a..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/Makefile
+++ /dev/null
@@ -1,62 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
-
-BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
-
-COBJS-y	+= board.o athrs26_phy.o
-
-SOBJS	= lowlevel_init.o pmuenable.o
-
-BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
-BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
-
-BOOTSTRAP_SRCS	:= $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
-
-SRCS	:= $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-BOOTSTRAP_OBJS	:= $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
-BOOTSTRAP_SOBJS	:= $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
-
-
-all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-$(BOOTSTRAP_LIB):	 $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
-	$(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/package/uboot-lantiq/files/board/arcadyan/arcadyan_bootstrap.c b/package/uboot-lantiq/files/board/arcadyan/arcadyan_bootstrap.c
deleted file mode 100644
index 11bf6d0b71..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/arcadyan_bootstrap.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2007
- * Vlad Lungu vlad.lungu@windriver.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-
-phys_size_t bootstrap_initdram(int board_type)
-{
-	/* Sdram is setup by assembler code */
-	/* If memory could be changed, we should return the true value here */
-	return CONFIG_SYS_MAX_RAM;
-}
-
-int bootstrap_checkboard(void)
-{
-	return 0;
-}
-
-int bootstrap_misc_init_r(void)
-{
-	set_io_port_base(0);
-	return 0;
-}
diff --git a/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.c b/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.c
deleted file mode 100644
index 663c4aa201..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.c
+++ /dev/null
@@ -1,812 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright © 2003 Atheros Communications, Inc.,  All Rights Reserved.
- */
-
-/*
- * Manage the atheros ethernet PHY.
- *
- * All definitions in this file are operating system independent!
- */
-
-#include <config.h>
-#include <linux/types.h>
-#include <common.h>
-#include <miiphy.h>
-//#include "phy.h"
-//#include "ar7100_soc.h"
-#include "athrs26_phy.h"
-
-#define phy_reg_read(base, addr, reg, datap)                    \
-    miiphy_read("lq_cpe_eth", addr, reg, datap);
-#define phy_reg_write(base, addr, reg, data)                   \
-    miiphy_write("lq_cpe_eth", addr, reg, data);
-            
-
-/* PHY selections and access functions */
-
-typedef enum {
-    PHY_SRCPORT_INFO, 
-    PHY_PORTINFO_SIZE,
-} PHY_CAP_TYPE;
-
-typedef enum {
-    PHY_SRCPORT_NONE,
-    PHY_SRCPORT_VLANTAG, 
-    PHY_SRCPORT_TRAILER,
-} PHY_SRCPORT_TYPE;
-
-#ifdef DEBUG
-#define DRV_DEBUG 1
-#endif
-//#define DRV_DEBUG 1
-
-#define DRV_DEBUG_PHYERROR  0x00000001
-#define DRV_DEBUG_PHYCHANGE 0x00000002
-#define DRV_DEBUG_PHYSETUP  0x00000004
-
-#if DRV_DEBUG
-int athrPhyDebug = DRV_DEBUG_PHYERROR|DRV_DEBUG_PHYCHANGE|DRV_DEBUG_PHYSETUP;
-
-#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6)    \
-{                                                   \
-    if (athrPhyDebug & (FLG)) {                       \
-        logMsg(X0, X1, X2, X3, X4, X5, X6);         \
-    }                                               \
-}
-
-#define DRV_MSG(x,a,b,c,d,e,f)                      \
-    logMsg(x,a,b,c,d,e,f)
-
-#define DRV_PRINT(FLG, X)                           \
-{                                                   \
-    if (athrPhyDebug & (FLG)) {                       \
-        printf X;                                   \
-    }                                               \
-}
-
-#else /* !DRV_DEBUG */
-#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
-#define DRV_MSG(x,a,b,c,d,e,f)
-#define DRV_PRINT(DBG_SW,X)
-#endif
-
-#define ATHR_LAN_PORT_VLAN          1
-#define ATHR_WAN_PORT_VLAN          2
-
-#define ENET_UNIT_LAN 0
-
-#define TRUE    1
-#define FALSE   0
-
-#define ATHR_PHY0_ADDR   0x0
-#define ATHR_PHY1_ADDR   0x1
-#define ATHR_PHY2_ADDR   0x2
-#define ATHR_PHY3_ADDR   0x3
-#define ATHR_PHY4_ADDR   0x4
-
-/*
- * Track per-PHY port information.
- */
-typedef struct {
-    BOOL   isEnetPort;       /* normal enet port */
-    BOOL   isPhyAlive;       /* last known state of link */
-    int    ethUnit;          /* MAC associated with this phy port */
-    uint32_t phyBase;
-    uint32_t phyAddr;          /* PHY registers associated with this phy port */
-    uint32_t VLANTableSetting; /* Value to be written to VLAN table */
-} athrPhyInfo_t;
-
-/*
- * Per-PHY information, indexed by PHY unit number.
- */
-static athrPhyInfo_t athrPhyInfo[] = {
-    {TRUE,   /* phy port 0 -- LAN port 0 */
-     FALSE,
-     ENET_UNIT_LAN,
-     0,
-     ATHR_PHY0_ADDR,
-     ATHR_LAN_PORT_VLAN
-    },
-
-    {TRUE,   /* phy port 1 -- LAN port 1 */
-     FALSE,
-     ENET_UNIT_LAN,
-     0,
-     ATHR_PHY1_ADDR,
-     ATHR_LAN_PORT_VLAN
-    },
-
-    {TRUE,   /* phy port 2 -- LAN port 2 */
-     FALSE,
-     ENET_UNIT_LAN,
-     0,
-     ATHR_PHY2_ADDR, 
-     ATHR_LAN_PORT_VLAN
-    },
-
-    {TRUE,   /* phy port 3 -- LAN port 3 */
-     FALSE,
-     ENET_UNIT_LAN,
-     0,
-     ATHR_PHY3_ADDR, 
-     ATHR_LAN_PORT_VLAN
-    },
-
-    {TRUE,   /* phy port 4 -- WAN port or LAN port 4 */
-     FALSE,
-     1,
-     0,
-     ATHR_PHY4_ADDR, 
-     ATHR_LAN_PORT_VLAN   /* Send to all ports */
-    },
-
-    {FALSE,  /* phy port 5 -- CPU port (no RJ45 connector) */
-     TRUE,
-     ENET_UNIT_LAN,
-     0,
-     0x00, 
-     ATHR_LAN_PORT_VLAN    /* Send to all ports */
-    },
-};
-
-#ifdef CFG_ATHRHDR_EN
-typedef struct {
-    uint8_t data[ATHRHDR_MAX_DATA];
-    uint8_t len;
-    uint32_t seq;
-} cmd_resp_t;
-
-typedef struct {
- uint16_t reg_addr;
- uint16_t cmd_len;
- uint8_t *reg_data;
-}cmd_write_t;
-
-static cmd_write_t cmd_write,cmd_read;
-static cmd_resp_t cmd_resp;
-static struct eth_device *lan_mac;
-//static atomic_t seqcnt = ATOMIC_INIT(0);
-static int  seqcnt = 0;
-static int cmd = 1;
-//volatile uchar AthrHdrPkt[60];
-#endif
-
-#define ATHR_GLOBALREGBASE    0
-
-//#define ATHR_PHY_MAX (sizeof(athrPhyInfo) / sizeof(athrPhyInfo[0]))
-#define ATHR_PHY_MAX 5
-
-/* Range of valid PHY IDs is [MIN..MAX] */
-#define ATHR_ID_MIN 0
-#define ATHR_ID_MAX (ATHR_PHY_MAX-1)
-
-/* Convenience macros to access myPhyInfo */
-#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort)
-#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive)
-#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit)
-#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase)
-#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr)
-#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting)
-
-
-#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) \
-            (ATHR_IS_ENET_PORT(phyUnit) &&        \
-            ATHR_ETHUNIT(phyUnit) == (ethUnit))
-
-#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit)==ENET_UNIT_LAN))
-            
-/* Forward references */
-BOOL       athrs26_phy_is_link_alive(int phyUnit);
-//static uint32_t athrs26_reg_read(uint16_t reg_addr);
-static void athrs26_reg_write(uint16_t reg_addr, 
-                              uint32_t reg_val);
-
-/******************************************************************************
-*
-* athrs26_phy_is_link_alive - test to see if the specified link is alive
-*
-* RETURNS:
-*    TRUE  --> link is alive
-*    FALSE --> link is down
-*/
-
-void athrs26_reg_init(void)
-{
-
-    athrs26_reg_write(0x200, 0x200);
-    athrs26_reg_write(0x300, 0x200);
-    athrs26_reg_write(0x400, 0x200);
-    athrs26_reg_write(0x500, 0x200);
-    athrs26_reg_write(0x600, 0x7d);
-
-#ifdef S26_VER_1_0
-    phy_reg_write(0, 0, 29, 41);
-    phy_reg_write(0, 0, 30, 0);
-    phy_reg_write(0, 1, 29, 41);
-    phy_reg_write(0, 1, 30, 0);
-    phy_reg_write(0, 2, 29, 41);
-    phy_reg_write(0, 2, 30, 0);
-    phy_reg_write(0, 3, 29, 41);
-    phy_reg_write(0, 3, 30, 0);
-    phy_reg_write(0, 4, 29, 41);
-    phy_reg_write(0, 4, 30, 0);
-#endif
-
-    athrs26_reg_write(0x38, 0xc000050e);
-
-#ifdef CFG_ATHRHDR_EN
-    athrs26_reg_write(0x104, 0x4804);
-#else
-    athrs26_reg_write(0x104, 0x4004);
-#endif
-
-    athrs26_reg_write(0x60, 0xffffffff);
-    athrs26_reg_write(0x64, 0xaaaaaaaa);
-    athrs26_reg_write(0x68, 0x55555555);
-    athrs26_reg_write(0x6c, 0x0);
-
-    athrs26_reg_write(0x70, 0x41af);
-}
-
-BOOL
-athrs26_phy_is_link_alive(int phyUnit)
-{
-    uint16_t phyHwStatus;
-    uint32_t phyBase;
-    uint32_t phyAddr;
-
-    phyBase = ATHR_PHYBASE(phyUnit);
-    phyAddr = ATHR_PHYADDR(phyUnit);
-
-    phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
-
-    if (phyHwStatus & ATHR_STATUS_LINK_PASS)
-        return TRUE;
-
-    return FALSE;
-}
-
-
-/******************************************************************************
-*
-* athrs26_phy_setup - reset and setup the PHY associated with
-* the specified MAC unit number.
-*
-* Resets the associated PHY port.
-*
-* RETURNS:
-*    TRUE  --> associated PHY is alive
-*    FALSE --> no LINKs on this ethernet unit
-*/
-
-BOOL
-athrs26_phy_setup(int ethUnit)
-{
-    int         phyUnit;
-    uint16_t    phyHwStatus;
-    uint16_t    timeout;
-    int         liveLinks = 0;
-    uint32_t    phyBase = 0;
-    BOOL        foundPhy = FALSE;
-    uint32_t  phyAddr = 0;
-    uint32_t  regVal;
-    
-
-    /* See if there's any configuration data for this enet */
-    /* start auto negogiation on each phy */
-    for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
-        if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
-			continue;
-        }
-
-
-        foundPhy = TRUE;
-        phyBase = ATHR_PHYBASE(phyUnit);
-        phyAddr = ATHR_PHYADDR(phyUnit);
-
-        phy_reg_write(phyBase, phyAddr, ATHR_AUTONEG_ADVERT,
-                      ATHR_ADVERTISE_ALL);
-
-        /* Reset PHYs*/
-        phy_reg_write(phyBase, phyAddr, ATHR_PHY_CONTROL,
-                      ATHR_CTRL_AUTONEGOTIATION_ENABLE
-                      | ATHR_CTRL_SOFTWARE_RESET);
-
-	}
-
-    if (!foundPhy) {
-        return FALSE; /* No PHY's configured for this ethUnit */
-    }
-
-    /*
-     * After the phy is reset, it takes a little while before
-     * it can respond properly.
-     */
-    sysMsDelay(1000);
-    
-    /*
-     * Wait up to .75 seconds for ALL associated PHYs to finish
-     * autonegotiation.  The only way we get out of here sooner is
-     * if ALL PHYs are connected AND finish autonegotiation.
-     */
-    for (phyUnit=0; (phyUnit < ATHR_PHY_MAX) /*&& (timeout > 0) */; phyUnit++) {
-        if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
-            continue;
-        }
-
-        timeout=20;
-        for (;;) {
-			phyHwStatus = 0;
-            phy_reg_read(phyBase, phyAddr, ATHR_PHY_CONTROL, &phyHwStatus);
-
-		if (ATHR_RESET_DONE(phyHwStatus)) {
-                DRV_PRINT(DRV_DEBUG_PHYSETUP,
-                          ("Port %d, Neg Success\n", phyUnit));
-                break;
-            }
-            if (timeout == 0) {
-                DRV_PRINT(DRV_DEBUG_PHYSETUP,
-                          ("Port %d, Negogiation timeout\n", phyUnit));
-                break;
-            }
-            if (--timeout == 0) {
-                DRV_PRINT(DRV_DEBUG_PHYSETUP,
-                          ("Port %d, Negogiation timeout\n", phyUnit));
-                break;
-            }
-
-            sysMsDelay(150);
-        }
-    }
-
-	/*
-     * All PHYs have had adequate time to autonegotiate.
-     * Now initialize software status.
-     *
-     * It's possible that some ports may take a bit longer
-     * to autonegotiate; but we can't wait forever.  They'll
-     * get noticed by mv_phyCheckStatusChange during regular
-     * polling activities.
-     */
-    for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
-        if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
-            continue;
-        }
-
-        if (athrs26_phy_is_link_alive(phyUnit)) {
-            liveLinks++;
-            ATHR_IS_PHY_ALIVE(phyUnit) = TRUE;
-        } else {
-            ATHR_IS_PHY_ALIVE(phyUnit) = FALSE;
-        }
-
-        phy_reg_read(ATHR_PHYBASE(phyUnit), ATHR_PHYADDR(phyUnit), 
-                    ATHR_PHY_SPEC_STATUS, &regVal);
-        DRV_PRINT(DRV_DEBUG_PHYSETUP,
-            ("eth%d: Phy Specific Status=%4.4x\n", ethUnit, regVal)); 
-    }
-#if 0
-    /* if using header for register configuration, we have to     */
-    /* configure s26 register after frame transmission is enabled */
-
-    athrs26_reg_write(0x200, 0x200);
-    athrs26_reg_write(0x300, 0x200);
-    athrs26_reg_write(0x400, 0x200);
-    athrs26_reg_write(0x500, 0x200);
-    athrs26_reg_write(0x600, 0x200);
-	athrs26_reg_write(0x38, 0x50e);
-#endif
-#ifndef CFG_ATHRHDR_EN       
-/* if using header for register configuration, we have to     */
-    /* configure s26 register after frame transmission is enabled */
-        athrs26_reg_init();
-#endif
-    
-    return (liveLinks > 0);
-}
-
-/******************************************************************************
-*
-* athrs26_phy_is_fdx - Determines whether the phy ports associated with the
-* specified device are FULL or HALF duplex.
-*
-* RETURNS:
-*    1  --> FULL
-*    0 --> HALF
-*/
-int
-athrs26_phy_is_fdx(int ethUnit)
-{
-    int         phyUnit;
-    uint32_t    phyBase;
-    uint32_t    phyAddr;
-    uint16_t    phyHwStatus;
-    int         ii = 200;
-    
-    if (ethUnit == ENET_UNIT_LAN)
-        return TRUE;
-    
-    for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
-        if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
-            continue;
-        }
-
-        if (athrs26_phy_is_link_alive(phyUnit)) {
-
-            phyBase = ATHR_PHYBASE(phyUnit);
-            phyAddr = ATHR_PHYADDR(phyUnit);
-
-            do {
-                phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
-        	    sysMsDelay(10);
-            } while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
-
-            if (phyHwStatus & ATHER_STATUS_FULL_DEPLEX)
-                return TRUE;
-        }
-    }
-
-    return FALSE;
-}
-
-
-/******************************************************************************
-*
-* athrs26_phy_speed - Determines the speed of phy ports associated with the
-* specified device.
-*
-* RETURNS:
-*               AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
-*               AG7100_PHY_SPEED_1000T;
-*/
-
-BOOL
-athrs26_phy_speed(int ethUnit)
-{
-    int         phyUnit;
-    uint16_t    phyHwStatus;
-    uint32_t    phyBase;
-    uint32_t    phyAddr;
-    int         ii = 200;
-    
-    if (ethUnit == ENET_UNIT_LAN)
-        return _100BASET;
-
-    for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
-        if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
-            continue;
-        }
-
-        if (athrs26_phy_is_link_alive(phyUnit)) {
-
-            phyBase = ATHR_PHYBASE(phyUnit);
-            phyAddr = ATHR_PHYADDR(phyUnit);
-            
-            do {
-                phy_reg_read(phyBase, phyAddr, 
-                                           ATHR_PHY_SPEC_STATUS, &phyHwStatus);
-                sysMsDelay(10);
-            }while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
-
-            phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >>
-                           ATHER_STATUS_LINK_SHIFT);
-
-            switch(phyHwStatus) {
-            case 0:
-                return _10BASET;
-            case 1:
-                return _100BASET;
-            case 2:
-                return _1000BASET;
-            default:
-                DRV_PRINT(DRV_DEBUG_PHYERROR, ("Unkown speed read!\n"));
-            }
-        }
-    }
-
-    return _10BASET;
-}
-
-/*****************************************************************************
-*
-* athr_phy_is_up -- checks for significant changes in PHY state.
-*
-* A "significant change" is:
-*     dropped link (e.g. ethernet cable unplugged) OR
-*     autonegotiation completed + link (e.g. ethernet cable plugged in)
-*
-* When a PHY is plugged in, phyLinkGained is called.
-* When a PHY is unplugged, phyLinkLost is called.
-*/
-
-int
-athrs26_phy_is_up(int ethUnit)
-{
-    int             phyUnit;
-    uint16_t        phyHwStatus;
-    athrPhyInfo_t  *lastStatus;
-    int             linkCount   = 0;
-    int             lostLinks   = 0;
-    int             gainedLinks = 0;
-    uint32_t        phyBase;
-    uint32_t        phyAddr;
-#ifdef CFG_ATHRHDR_REG
-    /* if using header to config s26, the link of MAC0 should always be up */
-    if (ethUnit == ENET_UNIT_LAN)
-        return 1;
-#endif
-
-    for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
-        if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
-            continue;
-        }
-
-        phyBase = ATHR_PHYBASE(phyUnit);
-        phyAddr = ATHR_PHYADDR(phyUnit);
-
-
-        lastStatus = &athrPhyInfo[phyUnit];
-        phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
-
-        if (lastStatus->isPhyAlive) { /* last known link status was ALIVE */
-            /* See if we've lost link */
-            if (phyHwStatus & ATHR_STATUS_LINK_PASS) {
-                linkCount++;
-            } else {
-                lostLinks++;
-                DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d down\n",
-                                               ethUnit, phyUnit));
-                lastStatus->isPhyAlive = FALSE;
-            }
-        } else { /* last known link status was DEAD */
-            /* Check for reset complete */
-            phy_reg_read(phyBase, phyAddr, ATHR_PHY_STATUS, &phyHwStatus);
-            if (!ATHR_RESET_DONE(phyHwStatus))
-                continue;
-
-            /* Check for AutoNegotiation complete */            
-            if (ATHR_AUTONEG_DONE(phyHwStatus)) {
-                //printk("autoneg done\n");
-                gainedLinks++;
-                linkCount++;
-                DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d up\n",
-                                               ethUnit, phyUnit));
-                lastStatus->isPhyAlive = TRUE;
-            }
-        }
-    }
-
-    return (linkCount);
-
-#if 0
-    if (linkCount == 0) {
-        if (lostLinks) {
-            /* We just lost the last link for this MAC */
-            phyLinkLost(ethUnit);
-        }
-    } else {
-        if (gainedLinks == linkCount) {
-            /* We just gained our first link(s) for this MAC */
-            phyLinkGained(ethUnit);
-        }
-    }
-#endif
-}
-
-#ifdef CFG_ATHRHDR_EN
-void athr_hdr_timeout(void){
-	eth_halt();
-        NetState = NETLOOP_FAIL; 
-}
-
-void athr_hdr_handler(uchar *recv_pkt, unsigned dest, unsigned src, unsigned len){
-	header_receive_pkt(recv_pkt);
-	NetState = NETLOOP_SUCCESS;
-}
-static int
-athrs26_header_config_reg (struct eth_device *dev, uint8_t wr_flag,
-                           uint16_t reg_addr, uint16_t cmd_len,
-                           uint8_t *val)
-{
-    at_header_t at_header;
-    reg_cmd_t reg_cmd;
-    uchar *AthrHdrPkt;
-
-    AthrHdrPkt = NetTxPacket;
-
-    if(AthrHdrPkt == NULL) {
-		printf("Null packet\n");
-		return;
-    }
-    memset(AthrHdrPkt,0,60);
-
-    /*fill at_header*/
-    at_header.reserved0 = 0x10;  //default
-    at_header.priority = 0;
-    at_header.type = 0x5;
-    at_header.broadcast = 0;
-    at_header.from_cpu = 1;
-    at_header.reserved1 = 0x01; //default
-    at_header.port_num = 0;
-
-    AthrHdrPkt[0] = at_header.port_num;
-    AthrHdrPkt[0] |= at_header.reserved1 << 4;
-    AthrHdrPkt[0] |= at_header.from_cpu << 6;
-    AthrHdrPkt[0] |= at_header.broadcast << 7;
-
-    AthrHdrPkt[1] = at_header.type;
-    AthrHdrPkt[1] |= at_header.priority << 4;
-    AthrHdrPkt[1] |= at_header.reserved0 << 6;
-
-
-    /*fill reg cmd*/
-    if(cmd_len > 4)
-        cmd_len = 4;//only support 32bits register r/w
-
-    reg_cmd.reg_addr = reg_addr&0x3FFFC;
-    reg_cmd.cmd_len = cmd_len;
-    reg_cmd.cmd = wr_flag;
-    reg_cmd.reserved2 = 0x5; //default
-    reg_cmd.seq_num = seqcnt;
-
-    AthrHdrPkt[2] = reg_cmd.reg_addr & 0xff;
-    AthrHdrPkt[3] = (reg_cmd.reg_addr & 0xff00) >> 8;
-    AthrHdrPkt[4] = (reg_cmd.reg_addr & 0x30000) >> 16;
-    AthrHdrPkt[4] |= reg_cmd.cmd_len << 4;
-    AthrHdrPkt[5] = reg_cmd.cmd << 4;
-    AthrHdrPkt[5] |= reg_cmd.reserved2 << 5;
-    AthrHdrPkt[6] = (reg_cmd.seq_num & 0x7f) << 1;
-    AthrHdrPkt[7] = (reg_cmd.seq_num & 0x7f80) >> 7;
-    AthrHdrPkt[8] = (reg_cmd.seq_num & 0x7f8000) >> 15;
-    AthrHdrPkt[9] = (reg_cmd.seq_num & 0x7f800000) >> 23;
-
-    /*fill reg data*/
-    if(!wr_flag)//write
-        memcpy((AthrHdrPkt + 10), val, cmd_len);
-    
-    /*start xmit*/
-    if(dev == NULL) {
-	printf("ERROR device not found\n");
-	return -1;
-    }
-    header_xmit(dev, AthrHdrPkt ,60);
-    return 0;
-}
-void athr_hdr_func(void) {
-
-   NetSetTimeout (1 * CFG_HZ,athr_hdr_timeout );
-   NetSetHandler (athr_hdr_handler);
-
-   if(cmd) 
-   	athrs26_header_config_reg(lan_mac, cmd, cmd_read.reg_addr, cmd_read.cmd_len, cmd_read.reg_data);
-   else 
-        athrs26_header_config_reg(lan_mac, cmd, cmd_write.reg_addr, cmd_write.cmd_len, cmd_write.reg_data);
-}
-static int
-athrs26_header_write_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
-{
-    int i = 2;
-    cmd_write.reg_addr = reg_addr;
-    cmd_write.cmd_len = cmd_len;
-    cmd_write.reg_data = reg_data;
-    cmd = 0;
-    seqcnt++;
-
-    do {
-	if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
-	   break;
-    } while (i--);
-
-    return i;
-}
-
-static int
-athrs26_header_read_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
-{
-    int i = 2;
-
-    cmd_read.reg_addr = reg_addr;
-    cmd_read.cmd_len = cmd_len;
-    cmd_read.reg_data = reg_data;
-    cmd = 1;
-    seqcnt++;
-
-    do {
-        if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
-           break;
-    } while (i--);
-
-    if ((i==0) || (seqcnt != cmd_resp.seq) || (cmd_len != cmd_resp.len)) {
-        return -1;
-    }
-    memcpy (cmd_read.reg_data, cmd_resp.data, cmd_len);
-    return 0;
-}
-int header_receive_pkt(uchar *recv_pkt)
-{
-    cmd_resp.len = recv_pkt[4] >> 4;
-    if (cmd_resp.len > 10)
-        goto out;
-
-    cmd_resp.seq = recv_pkt[6] >> 1;
-    cmd_resp.seq |= recv_pkt[7] << 7;
-    cmd_resp.seq |= recv_pkt[8] << 15;
-    cmd_resp.seq |= recv_pkt[9] << 23;
-
-    if (cmd_resp.seq < seqcnt)
-        goto out;
-    memcpy (cmd_resp.data, (recv_pkt + 10), cmd_resp.len);
-out:
-     return 0;
-}
-
-void athrs26_reg_dev(struct eth_device *mac)
-{
-    lan_mac = mac;
-}
-
-#endif
-
-/*static uint32_t
-athrs26_reg_read(uint16_t reg_addr)
-{
-#ifndef CFG_ATHRHDR_REG
-    uint16_t reg_word_addr = reg_addr / 2, phy_val;
-    uint32_t phy_addr;
-    uint8_t phy_reg; 
-    
-    phy_addr = 0x18;
-    phy_reg = 0x0;
-    phy_val = (reg_word_addr >> 8) & 0x1ff;        
-    phy_reg_write (0, phy_addr, phy_reg, phy_val);
-
-    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); 
-    phy_reg = reg_word_addr & 0x1f;            
-    phy_reg_read(0, phy_addr, phy_reg, &phy_val);
-    
-    return phy_val;
-#else
-    uint8_t reg_data[4];
-
-    memset (reg_data, 0, 4);
-    athrs26_header_read_reg(reg_addr, 4, reg_data);
-    return (reg_data[0] | (reg_data[1] << 8) | (reg_data[2] << 16) | (reg_data[3] << 24));
-#endif
-}
-*/
-static void
-athrs26_reg_write(uint16_t reg_addr, uint32_t reg_val)
-{
-#ifndef CFG_ATHRHDR_REG
-    uint16_t reg_word_addr = reg_addr / 2, phy_val;
-    uint32_t phy_addr;
-    uint8_t phy_reg; 
-
-    /* configure register high address */
-    phy_addr = 0x18;
-    phy_reg = 0x0;
-    phy_val = (reg_word_addr >> 8) & 0x1ff;         /* bit16-8 of reg address*/
-    phy_reg_write (0, phy_addr, phy_reg, phy_val);
-
-    /* read register with low address */
-    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
-    phy_reg = reg_word_addr & 0x1f;                 /* bit 4-0 of reg address */
-    phy_reg_write (0, phy_addr, phy_reg, reg_val);
-#else
-    uint8_t reg_data[4];
-
-    memset (reg_data, 0, 4);
-    reg_data[0] = (uint8_t)(0x00ff & reg_val);
-    reg_data[1] = (uint8_t)((0xff00 & reg_val) >> 8);
-    reg_data[2] = (uint8_t)((0xff0000 & reg_val) >> 16);
-    reg_data[3] = (uint8_t)((0xff000000 & reg_val) >> 24);
-
-    athrs26_header_write_reg (reg_addr, 4, reg_data);
-#endif
-
-}
-
diff --git a/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.h b/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.h
deleted file mode 100644
index 0fdde376eb..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.h
+++ /dev/null
@@ -1,134 +0,0 @@
-#ifndef _ATHRS26_PHY_H
-#define _ATHRS26_PHY_H
-
-/*****************/
-/* PHY Registers */
-/*****************/
-#define ATHR_PHY_CONTROL                 0
-#define ATHR_PHY_STATUS                  1
-#define ATHR_PHY_ID1                     2
-#define ATHR_PHY_ID2                     3
-#define ATHR_AUTONEG_ADVERT              4
-#define ATHR_LINK_PARTNER_ABILITY        5
-#define ATHR_AUTONEG_EXPANSION           6
-#define ATHR_NEXT_PAGE_TRANSMIT          7
-#define ATHR_LINK_PARTNER_NEXT_PAGE      8
-#define ATHR_1000BASET_CONTROL           9
-#define ATHR_1000BASET_STATUS            10
-#define ATHR_PHY_SPEC_CONTROL            16
-#define ATHR_PHY_SPEC_STATUS             17
-#define ATHR_DEBUG_PORT_ADDRESS          29
-#define ATHR_DEBUG_PORT_DATA             30
-
-/* ATHR_PHY_CONTROL fields */
-#define ATHR_CTRL_SOFTWARE_RESET                    0x8000
-#define ATHR_CTRL_SPEED_LSB                         0x2000
-#define ATHR_CTRL_AUTONEGOTIATION_ENABLE            0x1000
-#define ATHR_CTRL_RESTART_AUTONEGOTIATION           0x0200
-#define ATHR_CTRL_SPEED_FULL_DUPLEX                 0x0100
-#define ATHR_CTRL_SPEED_MSB                         0x0040
-
-#define ATHR_RESET_DONE(phy_control)                   \
-    (((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0)
-    
-/* Phy status fields */
-#define ATHR_STATUS_AUTO_NEG_DONE                   0x0020
-
-#define ATHR_AUTONEG_DONE(ip_phy_status)                   \
-    (((ip_phy_status) &                                  \
-        (ATHR_STATUS_AUTO_NEG_DONE)) ==                    \
-        (ATHR_STATUS_AUTO_NEG_DONE))
-        
-/* Link Partner ability */
-#define ATHR_LINK_100BASETX_FULL_DUPLEX       0x0100
-#define ATHR_LINK_100BASETX                   0x0080
-#define ATHR_LINK_10BASETX_FULL_DUPLEX        0x0040
-#define ATHR_LINK_10BASETX                    0x0020
-
-/* Advertisement register. */
-#define ATHR_ADVERTISE_NEXT_PAGE              0x8000
-#define ATHR_ADVERTISE_ASYM_PAUSE             0x0800
-#define ATHR_ADVERTISE_PAUSE                  0x0400
-#define ATHR_ADVERTISE_100FULL                0x0100
-#define ATHR_ADVERTISE_100HALF                0x0080  
-#define ATHR_ADVERTISE_10FULL                 0x0040  
-#define ATHR_ADVERTISE_10HALF                 0x0020  
-
-#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
-                            ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
-                       
-/* 1000BASET_CONTROL */
-#define ATHR_ADVERTISE_1000FULL               0x0200
-
-/* Phy Specific status fields */
-#define ATHER_STATUS_LINK_MASK                0xC000
-#define ATHER_STATUS_LINK_SHIFT               14
-#define ATHER_STATUS_FULL_DEPLEX              0x2000
-#define ATHR_STATUS_LINK_PASS                 0x0400
-#define ATHR_STATUS_RESOVLED                  0x0800
-
-/*phy debug port  register */
-#define ATHER_DEBUG_SERDES_REG                5
-
-/* Serdes debug fields */
-#define ATHER_SERDES_BEACON                   0x0100
-
-#ifndef BOOL
-#define BOOL    int
-#define TRUE    1
-#define FALSE   0
-#endif
-
-#define sysMsDelay(_x) udelay((_x) * 1000)
-
-#undef S26_VER_1_0
-
-#ifdef CFG_ATHRHDR_EN
-
-#include <net.h>
-#define header_xmit(dev,pkt,len) dev->send(dev,pkt,len) //dev_queue_xmit(skb)
-#define header_recv_ack(dev) dev->recv(dev) //dev_queue_xmit(skb)
-
-typedef enum {
-    NORMAL_PACKET,
-    RESERVED0,
-    MIB_1ST,
-    RESERVED1,
-    RESERVED2,
-    READ_WRITE_REG,
-    READ_WRITE_REG_ACK,
-    RESERVED3
-} ATHR_HDR_TYPE;
-
-typedef struct {
-    uint16_t    reserved0;
-    uint16_t    priority;
-    uint16_t    type ;
-    uint16_t    broadcast;
-    uint16_t    from_cpu;
-    uint16_t    reserved1;
-    uint16_t    port_num;
-}at_header_t;
-
-typedef struct {
-    uint64_t    reg_addr;
-    uint64_t    reserved0;
-    uint64_t    cmd_len;
-    uint64_t    reserved1;
-    uint64_t    cmd;
-    uint64_t    reserved2;
-    uint64_t    seq_num;
-}reg_cmd_t;
-void athrs26_reg_init(void);
-int header_receive_pkt(uchar *pkt);
-void athrs26_reg_dev(struct eth_device *mac);
-
-#endif
-
-int athrs26_phy_is_up(int unit);
-int athrs26_phy_is_fdx(int unit);
-int athrs26_phy_speed(int unit);
-BOOL athrs26_phy_setup(int unit);
-
-#endif /* _ATHRS26_PHY_H */
-
diff --git a/package/uboot-lantiq/files/board/arcadyan/board.c b/package/uboot-lantiq/files/board/arcadyan/board.c
deleted file mode 100644
index 57f4603628..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/board.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2010
- * Thomas Langer, Ralph Hempel
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <asm/addrspace.h>
-#include <asm/danube.h>
-#include <asm/reboot.h>
-#include <asm/io.h>
-#if defined(CONFIG_CMD_HTTPD)
-#include <httpd.h>
-#endif
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#if defined(CONFIG_AR8216_SWITCH)
-#include "athrs26_phy.h"
-#endif
-
-extern ulong ifx_get_ddr_hz(void);
-extern ulong ifx_get_cpuclk(void);
-
-/* IDs and registers of known external switches */
-void _machine_restart(void)
-{
-	*DANUBE_RCU_RST_REQ |=1<<30;
-}
-
-#ifdef CONFIG_SYS_RAMBOOT
-phys_size_t initdram(int board_type)
-{
-	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
-}
-#elif defined(CONFIG_USE_DDR_RAM)
-phys_size_t initdram(int board_type)
-{
-	return (CONFIG_SYS_MAX_RAM);
-}
-#else
-
-static ulong max_sdram_size(void)     /* per Chip Select */
-{
-	/* The only supported SDRAM data width is 16bit.
-	 */
-#define CFG_DW	4
-
-	/* The only supported number of SDRAM banks is 4.
-	 */
-#define CFG_NB	4
-
-	ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
-	int   cols   = cfgpb0 & 0xF;
-	int   rows   = (cfgpb0 & 0xF0) >> 4;
-	ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
-
-	return size;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'.
- */
-
-static long int dram_size(long int *base, long int maxsize)
-{
-	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
-	unsigned char i = 0;
-
-	for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
-		addr = base + cnt;		/* pointer arith! */
-
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
-
-	/* write 0 to base address */
-	addr = base;
-	save[i] = *addr;
-	*addr = 0;
-
-	/* check at base address */
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
-		addr = base + cnt;		/* pointer arith! */
-
-		val = *addr;
-		*addr = save[--i];
-
-		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
-}
-
-phys_size_t initdram(int board_type)
-{
-	int   rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
-	ulong size, max_size       = 0;
-	ulong our_address;
-
-	/* load t9 into our_address */
-	asm volatile ("move %0, $25" : "=r" (our_address) :);
-
-	/* Can't probe for RAM size unless we are running from Flash.
-	 * find out whether running from DRAM or Flash.
-	 */
-	if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
-	{
-		return max_sdram_size();
-	}
-
-	for (cols = 0x8; cols <= 0xC; cols++)
-	{
-		for (rows = 0xB; rows <= 0xD; rows++)
-		{
-			*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
-			                          (rows << 4) | cols;
-			size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-			                          max_sdram_size());
-
-			if (size > max_size)
-			{
-				best_val = *DANUBE_SDRAM_MC_CFGPB0;
-				max_size = size;
-			}
-		}
-	}
-
-	*DANUBE_SDRAM_MC_CFGPB0 = best_val;
-	return max_size;
-}
-#endif
-
-static void gpio_default(void)
-{
-#ifdef CONFIG_SWITCH_PORT0
-	*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
-#elif defined(CONFIG_SWITCH_PORT1)
-	*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
-#endif
-#ifdef CONFIG_EBU_GPIO
-	{
-		int i = 0;
-		printf ("bring up ebu gpio\n");
-		*DANUBE_EBU_BUSCON1 = 0x1e7ff;
-		*DANUBE_EBU_ADDSEL1 = 0x14000001;
-
-		*((volatile u16*)0xb4000000) = 0x0;
-		for(i = 0; i < 1000; i++)
-			udelay(1000);
-		*((volatile u16*)0xb4000000) = CONFIG_EBU_GPIO;
-		*DANUBE_EBU_BUSCON1 = 0x8001e7ff;
-	}
-#endif
-#ifdef CONFIG_BUTTON_PORT0
-	*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
-	*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
-	*DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
-	if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
-	{
-		printf("button is pressed\n");
-		setenv("bootdelay", "0");
-		setenv("bootcmd", "httpd");
-	}
-#elif defined(CONFIG_BUTTON_PORT1)
-	*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
-	*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
-	*DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
-	if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
-	{
-		printf("button is pressed\n");
-		setenv("bootdelay", "0");
-		setenv("bootcmd", "httpd");
-	}
-#endif
-#ifdef CONFIG_ARV4525
-	*DANUBE_GPIO_P0_ALTSEL0 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
-	*DANUBE_GPIO_P0_ALTSEL1 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
-	*DANUBE_GPIO_P0_OD |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
-	*DANUBE_GPIO_P0_DIR |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
-	*DANUBE_GPIO_P0_OUT &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
-#endif
-}
-
-int checkboard (void)
-{
-	unsigned long chipid = *DANUBE_MPS_CHIPID;
-	int part_num;
-
-	puts ("Board: "CONFIG_ARCADYAN"\n");
-	puts ("SoC: ");
-
-	part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
-	switch (part_num)
-	{
-	case 0x129:
-	case 0x12D:
-	case 0x12b: 
-		puts("Danube/Twinpass/Vinax-VE ");
-		break;
-	default:
-		printf ("unknown, chip part number 0x%03X ", part_num);
-		break;
-	}
-	printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
-
-	printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
-	printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
-
-
-	return 0;
-}
-
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-int board_early_init_f(void)
-{
-#ifdef CONFIG_EBU_ADDSEL0
-	(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
-#endif
-#ifdef CONFIG_EBU_ADDSEL1
-	(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
-#endif
-#ifdef CONFIG_EBU_ADDSEL2
-	(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
-#endif
-#ifdef CONFIG_EBU_ADDSEL3
-	(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
-#endif
-#ifdef CONFIG_EBU_BUSCON0
-	(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
-#endif
-#ifdef CONFIG_EBU_BUSCON1
-	(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
-#endif
-#ifdef CONFIG_EBU_BUSCON2
-	(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
-#endif
-#ifdef CONFIG_EBU_BUSCON3
-	(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
-#endif
-
-	return 0;
-}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifdef CONFIG_RTL8306_SWITCH
-#define ID_RTL8306	0x5988
-static int external_switch_rtl8306(void)
-{
-	unsigned short chipid;
-	static char * const name = "lq_cpe_eth";
-
-	udelay(100000);
-
-	puts("\nsearching for rtl8306 switch ... ");
-	if (miiphy_read(name, 4, 30, &chipid) == 0) {
-		if (chipid == ID_RTL8306) {
-			puts("found");
-			/* set led mode */
-			miiphy_write(name, 0, 19, 0xffff);
-			/* magic */
-			miiphy_write(name, 4, 22, 0x877f);
-			puts("\n");
-			return 0;
-		}
-		puts("failed\n");
-	}
-	puts("\nno known switch found ... \n");
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_RTL8306G_SWITCH
-#define ID_RTL8306	0x5988
-
-static int external_switch_rtl8306G(void)
-{
-	unsigned short chipid,val;
-	int i;
-	static char * const name = "lq_cpe_eth";
-	unsigned int chipid2, chipver, chiptype;
-	char str[128];
-	int cpu_mask = 1 << 5;
-	udelay(100000);
-
-	puts("\nsearching for rtl8306 switch ... ");
-	if (miiphy_read(name, 4, 30, &chipid) == 0) {
-		if (chipid == ID_RTL8306) {
-			puts("found\nReset Hard\n");
-#ifdef CONFIG_ARV752DPW
-			//gpio 19
-			//reset reset ping to high
-			*DANUBE_GPIO_P1_DIR |= 8;
-			*DANUBE_GPIO_P1_OUT |= 8;
-			udelay(500*1000);
-			*DANUBE_GPIO_P1_OUT &= ~(8); // now low again for at least 10 ms
-			udelay(500*1000);
-			*DANUBE_GPIO_P1_OUT |= 8;
-			udelay(500*1000);
-			puts("Done\n");
-#endif
-			/* set led mode */
-
-			miiphy_write(name, 0, 0, 0x3100);
-			miiphy_write(name, 0, 18, 0x7fff);
-			miiphy_write(name, 0, 19, 0xffff);
-			miiphy_write(name, 0, 22, 0x877f);
-			miiphy_write(name, 0, 24, 0x0ed1);
-
-			miiphy_write(name, 1, 0, 0x3100);
-			miiphy_write(name, 1, 22, 0x877f);
-			miiphy_write(name, 1, 24, 0x1ed2);
-
-			miiphy_write(name, 2, 0, 0x3100);
-			miiphy_write(name, 2, 22, 0x877f);
-			miiphy_write(name, 2, 23, 0x0020);
-			miiphy_write(name, 2, 24, 0x2ed4);
-
-			miiphy_write(name, 3, 0, 0x3100);
-			miiphy_write(name, 3, 22, 0x877f);
-			miiphy_write(name, 3, 24, 0x3ed8);
-
-			miiphy_write(name, 4, 0, 0x3100);
-			miiphy_write(name, 4, 22, 0x877f);
-			miiphy_write(name, 4, 24, 0x4edf);
-
-			miiphy_write(name, 5, 0, 0x3100);
-			miiphy_write(name, 6, 0, 0x2100);
-
-			//important. enable phy 5 link status, for rmii
-			miiphy_write(name, 6, 22, 0x873f);
-
-			miiphy_write(name, 6, 24, 0x8eff);
-			//disable ports
-			for (i=0;i<5;i++) {
-				miiphy_read(name, 0, 24, &val);
-				val&=~(1<<10);
-				val&=~(1<<11);
-				miiphy_write(name, 0, 24, val);
-			}
-
-			puts("Reset Soft\n");
-			miiphy_write(name,0 ,0 ,1<<15);
-			for (i=0;i<1000;i++)
-			{
-				miiphy_read(name,0 ,0 ,&val);
-				if (!(val&1<<15))
-					break;
-				udelay(1000);
-			}
-			if (i==1000)
-				puts("Failed\n");
-			else
-				puts("Success\n");
-			//enable ports egain
-			for (i=0;i<5;i++) // enable ports
-			{
-				miiphy_read(name, 0, 24, &val);
-				val|=(1<<10);
-				val|=(1<<11);
-				miiphy_write(name, 0, 24, val);
-			}
-			puts("\n");
-			return 0;
-		}
-		puts("failed\n");
-	}
-	puts("\nno known switch found ... \n");
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_AR8216_SWITCH
-static int external_switch_ar8216(void)
-{
-	puts("initializing ar8216 switch... ");
-	if (athrs26_phy_setup(0)==0) {
-	   printf("initialized\n");
-	   return 0;
-	}
-	puts("failed ... \n");
-	return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	gpio_default();
-
-#if defined(CONFIG_IFX_ETOP)
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-               eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
-
-	*DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
-	*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
-
-	if (lq_eth_initialize(bis))
-		return -1;
-
-	*DANUBE_RCU_RST_REQ |=1;
-	udelay(200000);
-	*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
-	udelay(1000);
-
-#ifdef CONFIG_RTL8306G_SWITCH
-	if (external_switch_rtl8306G()<0)
-		return -1;
-#endif
-#ifdef CONFIG_RTL8306_SWITCH
-	if (external_switch_rtl8306()<0)
-		return -1;
-#endif
-#ifdef CONFIG_AR8216_SWITCH
-	if (external_switch_ar8216()<0)
-		return -1;
-#endif
-#endif
-	return 0;
-}
-
-#if defined(CONFIG_CMD_HTTPD)
-int do_http_upgrade(const unsigned char *data, const ulong size)
-{
-	char buf[128];
-
-	if(getenv ("ram_addr") == NULL)
-		return -1;
-	if(getenv ("kernel_addr") == NULL)
-		return -1;
-	/* check the image */
-	if(run_command("imi ${ram_addr}", 0) < 0) {
-		return -1;
-	}
-	/* write the image to the flash */
-	puts("http ugrade ...\n");
-	sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
-	return run_command(buf, 0);
-}
-
-int do_http_progress(const int state)
-{
-	/* toggle LED's here */
-	switch(state) {
-		case HTTP_PROGRESS_START:
-		puts("http start\n");
-		break;
-		case HTTP_PROGRESS_TIMEOUT:
-		puts(".");
-		break;
-		case HTTP_PROGRESS_UPLOAD_READY:
-		puts("http upload ready\n");
-		break;
-		case HTTP_PROGRESS_UGRADE_READY:
-		puts("http ugrade ready\n");
-		break;
-		case HTTP_PROGRESS_UGRADE_FAILED:
-		puts("http ugrade failed\n");
-		break;
-	}
-	return 0;
-}
-
-unsigned long do_http_tmp_address(void)
-{
-	char *s = getenv ("ram_addr");
-	if (s) {
-		ulong tmp = simple_strtoul (s, NULL, 16);
-		return tmp;
-	}
-	return 0 /*0x80a00000*/;
-}
-
-#endif
diff --git a/package/uboot-lantiq/files/board/arcadyan/config.mk b/package/uboot-lantiq/files/board/arcadyan/config.mk
deleted file mode 100644
index cc8cd30906..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/config.mk
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifdef CONFIG_BOOTSTRAP
-TEXT_BASE = 0x80001000
-CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
-CONFIG_SYS_RAMBOOT = y
-else
-
-ifndef TEXT_BASE
-$(info redefine TEXT_BASE = 0xB0000000 )
-TEXT_BASE = 0xB0000000
-endif
-
-endif
diff --git a/package/uboot-lantiq/files/board/arcadyan/ddr_settings.h b/package/uboot-lantiq/files/board/arcadyan/ddr_settings.h
deleted file mode 100644
index 4df6f1170c..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/ddr_settings.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x130  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA03  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1b00
-#define MC_DC22_VALUE	0x1b1b
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x59   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x4e20
-#define MC_DC30_VALUE	0x8235
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_32.h b/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_32.h
deleted file mode 100644
index 445b7dac1f..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_32.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x120  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1700
-#define MC_DC22_VALUE	0x1717
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x52   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x4e20
-#define MC_DC30_VALUE	0x8235
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_64.h b/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_64.h
deleted file mode 100644
index c5afb8e21c..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_64.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x134  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA03  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1400
-#define MC_DC22_VALUE	0x1414
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x5b  /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x4e20
-#define MC_DC30_VALUE	0x8235
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/arcadyan/lowlevel_bootstrap_init.S b/package/uboot-lantiq/files/board/arcadyan/lowlevel_bootstrap_init.S
deleted file mode 100644
index 4747ad6db2..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/lowlevel_bootstrap_init.S
+++ /dev/null
@@ -1,583 +0,0 @@
-/*
- *  Memory sub-system initialization code for Danube board.
- *  Andre Messerschmidt
- *  Copyright (c) 2005	Infineon Technologies AG
- *
- *  Based on Inca-IP code
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
-      peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_PSC_32)
-#include "ddr_settings_psc_32.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_PSC_64)
-#include "ddr_settings_psc_64.h"
-#define DDR166
-#else
-#error "missing definition for RAM"
-#endif
-
-#define EBU_MODUL_BASE		0xBE105300
-#define EBU_CLC(value)		0x0000(value)
-#define EBU_CON(value)		0x0010(value)
-#define EBU_ADDSEL0(value)	0x0020(value)
-#define EBU_ADDSEL1(value)	0x0024(value)
-#define EBU_ADDSEL2(value)	0x0028(value)
-#define EBU_ADDSEL3(value)	0x002C(value)
-#define EBU_BUSCON0(value)	0x0060(value)
-#define EBU_BUSCON1(value)	0x0064(value)
-#define EBU_BUSCON2(value)	0x0068(value)
-#define EBU_BUSCON3(value)	0x006C(value)
-
-#define MC_MODUL_BASE		0xBF800000
-#define MC_ERRCAUSE(value)	0x0010(value)
-#define MC_ERRADDR(value)	0x0020(value)
-#define MC_CON(value)		0x0060(value)
-
-#define MC_SRAM_ENABLE		0x00000004
-#define MC_SDRAM_ENABLE		0x00000002
-#define MC_DDRRAM_ENABLE	0x00000001
-
-#define MC_SDR_MODUL_BASE	0xBF800200
-#define MC_IOGP(value)		0x0000(value)
-#define MC_CTRLENA(value)	0x0010(value)
-#define MC_MRSCODE(value)	0x0020(value)
-#define MC_CFGDW(value)		0x0030(value)
-#define MC_CFGPB0(value)	0x0040(value)
-#define MC_LATENCY(value)	0x0080(value)
-#define MC_TREFRESH(value)	0x0090(value)
-#define MC_SELFRFSH(value)	0x00A0(value)
-
-#define MC_DDR_MODUL_BASE	0xBF801000
-#define MC_DC00(value)		0x0000(value)
-#define MC_DC01(value)		0x0010(value)
-#define MC_DC02(value)		0x0020(value)
-#define MC_DC03(value)		0x0030(value)
-#define MC_DC04(value)		0x0040(value)
-#define MC_DC05(value)		0x0050(value)
-#define MC_DC06(value)		0x0060(value)
-#define MC_DC07(value)		0x0070(value)
-#define MC_DC08(value)		0x0080(value)
-#define MC_DC09(value)		0x0090(value)
-#define MC_DC10(value)		0x00A0(value)
-#define MC_DC11(value)		0x00B0(value)
-#define MC_DC12(value)		0x00C0(value)
-#define MC_DC13(value)		0x00D0(value)
-#define MC_DC14(value)		0x00E0(value)
-#define MC_DC15(value)		0x00F0(value)
-#define MC_DC16(value)		0x0100(value)
-#define MC_DC17(value)		0x0110(value)
-#define MC_DC18(value)		0x0120(value)
-#define MC_DC19(value)		0x0130(value)
-#define MC_DC20(value)		0x0140(value)
-#define MC_DC21(value)		0x0150(value)
-#define MC_DC22(value)		0x0160(value)
-#define MC_DC23(value)		0x0170(value)
-#define MC_DC24(value)		0x0180(value)
-#define MC_DC25(value)		0x0190(value)
-#define MC_DC26(value)		0x01A0(value)
-#define MC_DC27(value)		0x01B0(value)
-#define MC_DC28(value)		0x01C0(value)
-#define MC_DC29(value)		0x01D0(value)
-#define MC_DC30(value)		0x01E0(value)
-#define MC_DC31(value)		0x01F0(value)
-#define MC_DC32(value)		0x0200(value)
-#define MC_DC33(value)		0x0210(value)
-#define MC_DC34(value)		0x0220(value)
-#define MC_DC35(value)		0x0230(value)
-#define MC_DC36(value)		0x0240(value)
-#define MC_DC37(value)		0x0250(value)
-#define MC_DC38(value)		0x0260(value)
-#define MC_DC39(value)		0x0270(value)
-#define MC_DC40(value)		0x0280(value)
-#define MC_DC41(value)		0x0290(value)
-#define MC_DC42(value)		0x02A0(value)
-#define MC_DC43(value)		0x02B0(value)
-#define MC_DC44(value)		0x02C0(value)
-#define MC_DC45(value)		0x02D0(value)
-#define MC_DC46(value)		0x02E0(value)
-
-#define RCU_OFFSET  0xBF203000
-#define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
-#define RCU_STS          (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET  0xBF103000
-#define  PLL0_CFG     (CGU_OFFSET + 0x0004)
-#define  PLL1_CFG     (CGU_OFFSET + 0x0008)
-#define  PLL2_CFG     (CGU_OFFSET + 0x000C)
-#define  CGU_SYS      (CGU_OFFSET + 0x0010)
-#define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
-#define  IF_CLK       (CGU_OFFSET + 0x0018)
-#define  CGU_SMD      (CGU_OFFSET + 0x0020)
-#define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
-#define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
-#define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
-#define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
-#define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
-
-//05252006
-#define  pll0_35MHz_CONFIG 0x9D861059
-#define  pll1_35MHz_CONFIG 0x1A260CD9
-#define  pll2_35MHz_CONFIG 0x8000f1e5
-#define  pll0_36MHz_CONFIG 0x1000125D
-#define  pll1_36MHz_CONFIG 0x1B1E0C99
-#define  pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET  0xBE105400
-#define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE  0xB7000000
-#define CS_CFM		(PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
-	.set	noreorder
-
-
-/*
- * void ebu_init(void)
- */
-	.globl	ebu_init
-	.ent	ebu_init
-ebu_init:
-
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
-	defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
-	defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
-	defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
-	li	t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
-	li	t2, CONFIG_EBU_ADDSEL0
-	sw	t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
-	li	t2, CONFIG_EBU_ADDSEL1
-	sw	t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
-	li	t2, CONFIG_EBU_ADDSEL2
-	sw	t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
-	li	t2, CONFIG_EBU_ADDSEL3
-	sw	t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
-	li	t2, CONFIG_EBU_BUSCON0
-	sw	t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
-	li	t2, CONFIG_EBU_BUSCON1
-	sw	t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
-	li	t2, CONFIG_EBU_BUSCON2
-	sw	t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
-	li	t2, CONFIG_EBU_BUSCON3
-	sw	t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
-	j	ra
-	nop
-
-	.end	ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
-	.globl	cgu_init
-	.ent	cgu_init
-cgu_init:
-	li  t2, CGU_SYS
-	lw  t2,0(t2)
-	beq t2,a0,freq_up2date
-	nop
-
-	li  t2, RCU_STS
-	lw  t2, 0(t2)
-	and t2,0x00020000
-	beq t2,0x00020000,boot_36MHZ
-	nop
-//05252006
-	li  t1, PLL0_CFG
-	li  t2, pll0_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-	b   wait_reset
-	nop
-boot_36MHZ:
-	li  t1, PLL0_CFG
-	li  t2, pll0_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-//05252006
-
-wait_reset:
-	b   wait_reset
-	nop
-freq_up2date:
-	j ra
-	nop
-
-	.end	cgu_init
-
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	sdram_init
-	.ent	sdram_init
-sdram_init:
-
-	/* SDRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable SDRAM module in memory controller */
-	li	t3, MC_SDRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_SDR_MODUL_BASE
-
-	/* disable the controller */
-	li	t2, 0
-	sw	t2, MC_CTRLENA(t1)
-
-	li	t2, 0x822
-	sw	t2, MC_IOGP(t1)
-
-	li	t2, 0x2
-	sw	t2, MC_CFGDW(t1)
-
-	/* Set CAS Latency */
-	li	t2, 0x00000020
-	sw	t2, MC_MRSCODE(t1)
-
-	/* Set CS0 to SDRAM parameters */
-	li	t2, 0x000014d8
-	sw	t2, MC_CFGPB0(t1)
-
-	/* Set SDRAM latency parameters */
-	li  	t2, 0x00036325;   /* BC PC100 */
-	sw	t2, MC_LATENCY(t1)
-
-	/* Set SDRAM refresh rate */
-	li	t2, 0x00000C30
-	sw	t2, MC_TREFRESH(t1)
-
-	/* Clear Power-down registers */
-	sw	zero, MC_SELFRFSH(t1)
-
-	/* Finally enable the controller */
-	li	t2, 1
-	sw	t2, MC_CTRLENA(t1)
-
-	j	ra
-	nop
-
-	.end	sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	ddrram_init
-	.ent	ddrram_init
-ddrram_init:
-
-	/* DDR-DRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable DDR module in memory controller */
-	li	t3, MC_DDRRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_DDR_MODUL_BASE
-
-	/* Write configuration to DDR controller registers */
-	li	t2, MC_DC0_VALUE
-	sw	t2, MC_DC00(t1)
-
-	li	t2, MC_DC1_VALUE
-	sw	t2, MC_DC01(t1)
-
-	li	t2, MC_DC2_VALUE
-	sw	t2, MC_DC02(t1)
-
-	li	t2, MC_DC3_VALUE
-	sw	t2, MC_DC03(t1)
-
-	li	t2, MC_DC4_VALUE
-	sw	t2, MC_DC04(t1)
-
-	li	t2, MC_DC5_VALUE
-	sw	t2, MC_DC05(t1)
-
-	li	t2, MC_DC6_VALUE
-	sw	t2, MC_DC06(t1)
-
-	li	t2, MC_DC7_VALUE
-	sw	t2, MC_DC07(t1)
-
-	li	t2, MC_DC8_VALUE
-	sw	t2, MC_DC08(t1)
-
-	li	t2, MC_DC9_VALUE
-	sw	t2, MC_DC09(t1)
-
-	li	t2, MC_DC10_VALUE
-	sw	t2, MC_DC10(t1)
-
-	li	t2, MC_DC11_VALUE
-	sw	t2, MC_DC11(t1)
-
-	li	t2, MC_DC12_VALUE
-	sw	t2, MC_DC12(t1)
-
-	li	t2, MC_DC13_VALUE
-	sw	t2, MC_DC13(t1)
-
-	li	t2, MC_DC14_VALUE
-	sw	t2, MC_DC14(t1)
-
-	li	t2, MC_DC15_VALUE
-	sw	t2, MC_DC15(t1)
-
-	li	t2, MC_DC16_VALUE
-	sw	t2, MC_DC16(t1)
-
-	li	t2, MC_DC17_VALUE
-	sw	t2, MC_DC17(t1)
-
-	li	t2, MC_DC18_VALUE
-	sw	t2, MC_DC18(t1)
-
-	li	t2, MC_DC19_VALUE
-	sw	t2, MC_DC19(t1)
-
-	li	t2, MC_DC20_VALUE
-	sw	t2, MC_DC20(t1)
-
-	li	t2, MC_DC21_VALUE
-	sw	t2, MC_DC21(t1)
-
-	li	t2, MC_DC22_VALUE
-	sw	t2, MC_DC22(t1)
-
-	li	t2, MC_DC23_VALUE
-	sw	t2, MC_DC23(t1)
-
-	li	t2, MC_DC24_VALUE
-	sw	t2, MC_DC24(t1)
-
-	li	t2, MC_DC25_VALUE
-	sw	t2, MC_DC25(t1)
-
-	li	t2, MC_DC26_VALUE
-	sw	t2, MC_DC26(t1)
-
-	li	t2, MC_DC27_VALUE
-	sw	t2, MC_DC27(t1)
-
-	li	t2, MC_DC28_VALUE
-	sw	t2, MC_DC28(t1)
-
-	li	t2, MC_DC29_VALUE
-	sw	t2, MC_DC29(t1)
-
-	li	t2, MC_DC30_VALUE
-	sw	t2, MC_DC30(t1)
-
-	li	t2, MC_DC31_VALUE
-	sw	t2, MC_DC31(t1)
-
-	li	t2, MC_DC32_VALUE
-	sw	t2, MC_DC32(t1)
-
-	li	t2, MC_DC33_VALUE
-	sw	t2, MC_DC33(t1)
-
-	li	t2, MC_DC34_VALUE
-	sw	t2, MC_DC34(t1)
-
-	li	t2, MC_DC35_VALUE
-	sw	t2, MC_DC35(t1)
-
-	li	t2, MC_DC36_VALUE
-	sw	t2, MC_DC36(t1)
-
-	li	t2, MC_DC37_VALUE
-	sw	t2, MC_DC37(t1)
-
-	li	t2, MC_DC38_VALUE
-	sw	t2, MC_DC38(t1)
-
-	li	t2, MC_DC39_VALUE
-	sw	t2, MC_DC39(t1)
-
-	li	t2, MC_DC40_VALUE
-	sw	t2, MC_DC40(t1)
-
-	li	t2, MC_DC41_VALUE
-	sw	t2, MC_DC41(t1)
-
-	li	t2, MC_DC42_VALUE
-	sw	t2, MC_DC42(t1)
-
-	li	t2, MC_DC43_VALUE
-	sw	t2, MC_DC43(t1)
-
-	li	t2, MC_DC44_VALUE
-	sw	t2, MC_DC44(t1)
-
-	li	t2, MC_DC45_VALUE
-	sw	t2, MC_DC45(t1)
-
-	li	t2, MC_DC46_VALUE
-	sw	t2, MC_DC46(t1)
-
-	li	t2, 0x00000100
-	sw	t2, MC_DC03(t1)
-
-	j	ra
-	nop
-
-	.end	ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
-	.globl	lowlevel_init
-	.ent	lowlevel_init
-lowlevel_init:
-	/* EBU, CGU and SDRAM/DDR-RAM Initialization.
-	 */
-	move	t0, ra
-	/* We rely on the fact that non of the following ..._init() functions
-	 * modify t0
-	 */
-#if defined(DDR166)
-	/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
-	li  a0,0xe8
-#elif defined(DDR133)
-	/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
-	li  a0,0xe9
-#else /* defined(DDR111) */
-	/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
-	li  a0,0xea
-#endif
-	bal	cgu_init
-	nop
-
-	bal	ebu_init
-	nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
-	li  t1, PCI_CR_PCI	//mw bf103034 80000000
-	li  t2, 0x80000000
-	sw	t2,0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x103
-	sw  t2,0(t1)
-
-	li  t1, CS_CFM			//mw b700006c 0
-	li  t2, 0x00
-	sw  t2, 0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x1000103
-	sw  t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
-#ifdef CONFIG_USE_DDR_RAM
-	bal	ddrram_init
-	nop
-#else
-	bal	sdram_init
-	nop
-#endif
-	move	ra, t0
-	j	ra
-	nop
-
-	.end	lowlevel_init
diff --git a/package/uboot-lantiq/files/board/arcadyan/lowlevel_init.S b/package/uboot-lantiq/files/board/arcadyan/lowlevel_init.S
deleted file mode 100644
index d9fe38bc67..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/lowlevel_init.S
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- *  Memory sub-system initialization code for Danube board.
- *  Andre Messerschmidt
- *  Copyright (c) 2005	Infineon Technologies AG
- *
- *  Based on Inca-IP code
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
-      peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_PSC_32)
-#include "ddr_settings_psc_32.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_PSC_64)
-#include "ddr_settings_psc_64.h"
-#define DDR166
-#else
-#error "missing definition for RAM"
-#endif
-
-#define EBU_MODUL_BASE		0xBE105300
-#define EBU_CLC(value)		0x0000(value)
-#define EBU_CON(value)		0x0010(value)
-#define EBU_ADDSEL0(value)	0x0020(value)
-#define EBU_ADDSEL1(value)	0x0024(value)
-#define EBU_ADDSEL2(value)	0x0028(value)
-#define EBU_ADDSEL3(value)	0x002C(value)
-#define EBU_BUSCON0(value)	0x0060(value)
-#define EBU_BUSCON1(value)	0x0064(value)
-#define EBU_BUSCON2(value)	0x0068(value)
-#define EBU_BUSCON3(value)	0x006C(value)
-
-#define MC_MODUL_BASE		0xBF800000
-#define MC_ERRCAUSE(value)	0x0010(value)
-#define MC_ERRADDR(value)	0x0020(value)
-#define MC_CON(value)		0x0060(value)
-
-#define MC_SRAM_ENABLE		0x00000004
-#define MC_SDRAM_ENABLE		0x00000002
-#define MC_DDRRAM_ENABLE	0x00000001
-
-#define MC_SDR_MODUL_BASE	0xBF800200
-#define MC_IOGP(value)		0x0000(value)
-#define MC_CTRLENA(value)	0x0010(value)
-#define MC_MRSCODE(value)	0x0020(value)
-#define MC_CFGDW(value)		0x0030(value)
-#define MC_CFGPB0(value)	0x0040(value)
-#define MC_LATENCY(value)	0x0080(value)
-#define MC_TREFRESH(value)	0x0090(value)
-#define MC_SELFRFSH(value)	0x00A0(value)
-
-#define MC_DDR_MODUL_BASE	0xBF801000
-#define MC_DC00(value)		0x0000(value)
-#define MC_DC01(value)		0x0010(value)
-#define MC_DC02(value)		0x0020(value)
-#define MC_DC03(value)		0x0030(value)
-#define MC_DC04(value)		0x0040(value)
-#define MC_DC05(value)		0x0050(value)
-#define MC_DC06(value)		0x0060(value)
-#define MC_DC07(value)		0x0070(value)
-#define MC_DC08(value)		0x0080(value)
-#define MC_DC09(value)		0x0090(value)
-#define MC_DC10(value)		0x00A0(value)
-#define MC_DC11(value)		0x00B0(value)
-#define MC_DC12(value)		0x00C0(value)
-#define MC_DC13(value)		0x00D0(value)
-#define MC_DC14(value)		0x00E0(value)
-#define MC_DC15(value)		0x00F0(value)
-#define MC_DC16(value)		0x0100(value)
-#define MC_DC17(value)		0x0110(value)
-#define MC_DC18(value)		0x0120(value)
-#define MC_DC19(value)		0x0130(value)
-#define MC_DC20(value)		0x0140(value)
-#define MC_DC21(value)		0x0150(value)
-#define MC_DC22(value)		0x0160(value)
-#define MC_DC23(value)		0x0170(value)
-#define MC_DC24(value)		0x0180(value)
-#define MC_DC25(value)		0x0190(value)
-#define MC_DC26(value)		0x01A0(value)
-#define MC_DC27(value)		0x01B0(value)
-#define MC_DC28(value)		0x01C0(value)
-#define MC_DC29(value)		0x01D0(value)
-#define MC_DC30(value)		0x01E0(value)
-#define MC_DC31(value)		0x01F0(value)
-#define MC_DC32(value)		0x0200(value)
-#define MC_DC33(value)		0x0210(value)
-#define MC_DC34(value)		0x0220(value)
-#define MC_DC35(value)		0x0230(value)
-#define MC_DC36(value)		0x0240(value)
-#define MC_DC37(value)		0x0250(value)
-#define MC_DC38(value)		0x0260(value)
-#define MC_DC39(value)		0x0270(value)
-#define MC_DC40(value)		0x0280(value)
-#define MC_DC41(value)		0x0290(value)
-#define MC_DC42(value)		0x02A0(value)
-#define MC_DC43(value)		0x02B0(value)
-#define MC_DC44(value)		0x02C0(value)
-#define MC_DC45(value)		0x02D0(value)
-#define MC_DC46(value)		0x02E0(value)
-
-#define RCU_OFFSET  0xBF203000
-#define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
-#define RCU_STS          (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET  0xBF103000
-#define  PLL0_CFG     (CGU_OFFSET + 0x0004)
-#define  PLL1_CFG     (CGU_OFFSET + 0x0008)
-#define  PLL2_CFG     (CGU_OFFSET + 0x000C)
-#define  CGU_SYS      (CGU_OFFSET + 0x0010)
-#define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
-#define  IF_CLK       (CGU_OFFSET + 0x0018)
-#define  CGU_SMD      (CGU_OFFSET + 0x0020)
-#define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
-#define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
-#define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
-#define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
-#define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
-
-//05252006
-#define  pll0_35MHz_CONFIG 0x9D861059
-#define  pll1_35MHz_CONFIG 0x1A260CD9
-#define  pll2_35MHz_CONFIG 0x8000f1e5
-#define  pll0_36MHz_CONFIG 0x1000125D
-#define  pll1_36MHz_CONFIG 0x1B1E0C99
-#define  pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET  0xBE105400
-#define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE  0xB7000000
-#define CS_CFM		(PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
-	.set	noreorder
-
-
-/*
- * void ebu_init(void)
- */
-	.globl	ebu_init
-	.ent	ebu_init
-ebu_init:
-
-	j	ra
-	nop
-
-	.end	ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
-	.globl	cgu_init
-	.ent	cgu_init
-cgu_init:
-	li  t2, CGU_SYS
-	lw  t2,0(t2)
-	beq t2,a0,freq_up2date
-	nop
-
-	li  t2, RCU_STS
-	lw  t2, 0(t2)
-	and t2,0x00020000
-	beq t2,0x00020000,boot_36MHZ
-	nop
-//05252006
-	li  t1, PLL0_CFG
-	li  t2, pll0_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-	b   wait_reset
-	nop
-boot_36MHZ:
-	li  t1, PLL0_CFG
-	li  t2, pll0_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-//05252006
-
-wait_reset:
-	b   wait_reset
-	nop
-freq_up2date:
-	j ra
-	nop
-
-	.end	cgu_init
-
-	.globl	lowlevel_init
-	.ent	lowlevel_init
-lowlevel_init:
-	/* EBU, CGU and SDRAM/DDR-RAM Initialization.
-	 */
-	move	t0, ra
-	/* We rely on the fact that non of the following ..._init() functions
-	 * modify t0
-	 */
-
-	bal	ebu_init
-	nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
-	li  t1, PCI_CR_PCI	//mw bf103034 80000000
-	li  t2, 0x80000000
-	sw	t2,0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x103
-	sw  t2,0(t1)
-
-	li  t1, CS_CFM			//mw b700006c 0
-	li  t2, 0x00
-	sw  t2, 0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x1000103
-	sw  t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
-	move	ra, t0
-	j	ra
-	nop
-
-	.end	lowlevel_init
diff --git a/package/uboot-lantiq/files/board/arcadyan/pmuenable.S b/package/uboot-lantiq/files/board/arcadyan/pmuenable.S
deleted file mode 100644
index e0d7971d89..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/pmuenable.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  Power Management unit initialization code for AMAZON development board.
- *
- *  Copyright (c) 2003	Ou Ke, Infineon.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#define PMU_PWDCR 		0xBF10201C
-#define PMU_SR			0xBF102020
-
-	.globl	pmuenable
-
-pmuenable:
-	li      t0, PMU_PWDCR
-	li      t1, 0x2		/* enable everything */
-	sw      t1, 0(t0)
-#if 0
-1:
-	li	t0, PMU_SR
-	lw      t2, 0(t0)
-	bne     t1, t2, 1b
-	nop
-#endif
-	j	ra
-	nop
-
-
diff --git a/package/uboot-lantiq/files/board/arcadyan/u-boot-bootstrap.lds b/package/uboot-lantiq/files/board/arcadyan/u-boot-bootstrap.lds
deleted file mode 100644
index 52d7dafadb..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/u-boot-bootstrap.lds
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = .;
-	_gp = ALIGN(16) +0x7ff0;
-
-	.got  : {
-	__got_start = .;
-		*(.got)
-	__got_end = .;
-	}
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	. = .;
-	. = ALIGN(4);
-	.payload : { *(.payload) }
-	. = ALIGN(4);
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) . = ALIGN(4); }
-	uboot_end = .;
-}
-
diff --git a/package/uboot-lantiq/files/board/arcadyan/u-boot.lds b/package/uboot-lantiq/files/board/arcadyan/u-boot.lds
deleted file mode 100644
index 9a6cd1b8a3..0000000000
--- a/package/uboot-lantiq/files/board/arcadyan/u-boot.lds
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	.got : {
-	  __got_start = .;
-	  *(.got)
-	  __got_end = .;
-	}
-
-	.sdata  : { *(.sdata) }
-
-	.u_boot_cmd : {
-	  __u_boot_cmd_start = .;
-	  *(.u_boot_cmd)
-	  __u_boot_cmd_end = .;
-	}
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss (NOLOAD)  : { *(.sbss) }
-	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
-	uboot_end = .;
-}
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/Makefile b/package/uboot-lantiq/files/board/infineon/easy50712/Makefile
deleted file mode 100644
index 67570505d9..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/Makefile
+++ /dev/null
@@ -1,62 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
-
-BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
-
-COBJS-y	+= danube.o
-
-SOBJS	= lowlevel_init.o pmuenable.o
-
-BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
-BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
-
-BOOTSTRAP_SRCS	:= $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
-
-SRCS	:= $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-BOOTSTRAP_OBJS	:= $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
-BOOTSTRAP_SOBJS	:= $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
-
-
-all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-$(BOOTSTRAP_LIB):	 $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
-	$(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/config.mk b/package/uboot-lantiq/files/board/infineon/easy50712/config.mk
deleted file mode 100644
index b110f6f329..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/config.mk
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Danube board with MIPS 24Kc CPU core
-#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifdef CONFIG_BOOTSTRAP
-TEXT_BASE = 0x80001000
-CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
-CONFIG_SYS_RAMBOOT = y
-else
-
-ifndef TEXT_BASE
-$(info redefine TEXT_BASE = 0xB0000000 )
-TEXT_BASE = 0xB0000000
-endif
-
-endif
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/danube.c b/package/uboot-lantiq/files/board/infineon/easy50712/danube.c
deleted file mode 100644
index e3845cb38f..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/danube.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2010
- * Thomas Langer, Ralph Hempel
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <asm/addrspace.h>
-#include <asm/danube.h>
-#include <asm/reboot.h>
-#include <asm/io.h>
-#if defined(CONFIG_CMD_HTTPD)
-#include <httpd.h>
-#endif
-
-extern ulong ifx_get_ddr_hz(void);
-extern ulong ifx_get_cpuclk(void);
-
-/* definitions for external PHYs / Switches */
-/* Split values into phy address and register address */
-#define PHYADDR(_reg)	((_reg >> 5) & 0xff), (_reg & 0x1f)
-
-/* IDs and registers of known external switches */
-#define ID_SAMURAI_0	0x1020
-#define ID_SAMURAI_1	0x0007
-#define SAMURAI_ID_REG0	0xA0
-#define SAMURAI_ID_REG1	0xA1
-
-#define ID_TANTOS	0x2599
-
-void _machine_restart(void)
-{
-	*DANUBE_RCU_RST_REQ |=1<<30;
-}
-
-#ifdef CONFIG_SYS_RAMBOOT
-phys_size_t initdram(int board_type)
-{
-	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
-}
-#elif defined(CONFIG_USE_DDR_RAM)
-phys_size_t initdram(int board_type)
-{
-	return (CONFIG_SYS_MAX_RAM);
-}
-#else
-
-static ulong max_sdram_size(void)     /* per Chip Select */
-{
-	/* The only supported SDRAM data width is 16bit.
-	 */
-#define CFG_DW	4
-
-	/* The only supported number of SDRAM banks is 4.
-	 */
-#define CFG_NB	4
-
-	ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
-	int   cols   = cfgpb0 & 0xF;
-	int   rows   = (cfgpb0 & 0xF0) >> 4;
-	ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
-
-	return size;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'.
- */
-
-static long int dram_size(long int *base, long int maxsize)
-{
-	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
-	unsigned char i = 0;
-
-	for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
-		addr = base + cnt;		/* pointer arith! */
-
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
-
-	/* write 0 to base address */
-	addr = base;
-	save[i] = *addr;
-	*addr = 0;
-
-	/* check at base address */
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
-		addr = base + cnt;		/* pointer arith! */
-
-		val = *addr;
-		*addr = save[--i];
-
-		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
-}
-
-phys_size_t initdram(int board_type)
-{
-	int   rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
-	ulong size, max_size       = 0;
-	ulong our_address;
-
-	/* load t9 into our_address */
-	asm volatile ("move %0, $25" : "=r" (our_address) :);
-
-	/* Can't probe for RAM size unless we are running from Flash.
-	 * find out whether running from DRAM or Flash.
-	 */
-	if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
-	{
-		return max_sdram_size();
-	}
-
-	for (cols = 0x8; cols <= 0xC; cols++)
-	{
-		for (rows = 0xB; rows <= 0xD; rows++)
-		{
-			*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
-			                          (rows << 4) | cols;
-			size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-			                          max_sdram_size());
-
-			if (size > max_size)
-			{
-				best_val = *DANUBE_SDRAM_MC_CFGPB0;
-				max_size = size;
-			}
-		}
-	}
-
-	*DANUBE_SDRAM_MC_CFGPB0 = best_val;
-	return max_size;
-}
-#endif
-
-int checkboard (void)
-{
-	unsigned long chipid = *DANUBE_MPS_CHIPID;
-	int part_num;
-
-	puts ("Board: ");
-
-	part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
-	switch (part_num)
-	{
-	case 0x129:
-	case 0x12B:
-	case 0x12D:
-		puts("Danube/Twinpass/Vinax-VE ");
-		break;
-	default:
-		printf ("unknown, chip part number 0x%03X ", part_num);
-		break;
-	}
-	printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
-
-	printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
-	printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
-
-	return 0;
-}
-
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-int board_early_init_f(void)
-{
-#ifdef CONFIG_EBU_ADDSEL0
-	(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
-#endif
-#ifdef CONFIG_EBU_ADDSEL1
-	(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
-#endif
-#ifdef CONFIG_EBU_ADDSEL2
-	(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
-#endif
-#ifdef CONFIG_EBU_ADDSEL3
-	(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
-#endif
-#ifdef CONFIG_EBU_BUSCON0
-	(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
-#endif
-#ifdef CONFIG_EBU_BUSCON1
-	(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
-#endif
-#ifdef CONFIG_EBU_BUSCON2
-	(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
-#endif
-#ifdef CONFIG_EBU_BUSCON3
-	(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
-#endif
-
-	return 0;
-}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifdef CONFIG_EXTRA_SWITCH
-static int external_switch_init(void)
-{
-	unsigned short chipid0=0xdead, chipid1=0xbeef;
-	static char * const name = "lq_cpe_eth";
-
-#ifdef CONFIG_SWITCH_PORT0
-	*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
-#elif defined(CONFIG_SWITCH_PORT1)
-	*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
-	*DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
-#endif
-#ifdef CLK_OUT2_25MHZ
-	*DANUBE_GPIO_P0_DIR=0x0000ae78;
-	*DANUBE_GPIO_P0_ALTSEL0=0x00008078;
-	//joelin for Mii-1       *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
-	*DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
-	*DANUBE_CGU_IFCCR=0x00400010;
-	*DANUBE_GPIO_P0_OD=0x0000ae78;
-#endif
-
-	/* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */
-	udelay(100000);
-
-	debug("\nsearching for Samurai switch ... ");
-	if ( (miiphy_read(name, PHYADDR(SAMURAI_ID_REG0), &chipid0)==0) &&
-	     (miiphy_read(name, PHYADDR(SAMURAI_ID_REG1), &chipid1)==0) ) {
-		if (((chipid0 & 0xFFF0) == ID_SAMURAI_0) &&
-		    ((chipid1 & 0x000F) == ID_SAMURAI_1)) {
-			debug("found");
-
-			/* enable "Crossover Auto Detect" + defaults */
-			/* P0 */
-			miiphy_write(name, PHYADDR(0x01), 0x840F);
-			/* P1 */
-			miiphy_write(name, PHYADDR(0x03), 0x840F);
-			/* P2 */
-			miiphy_write(name, PHYADDR(0x05), 0x840F);
-			/* P3 */
-			miiphy_write(name, PHYADDR(0x07), 0x840F);
-			/* P4 */
-			miiphy_write(name, PHYADDR(0x08), 0x840F);
-			/* P5 */
-			miiphy_write(name, PHYADDR(0x09), 0x840F);
-			/* System Control 4: CPU on port 1 and other */
-			miiphy_write(name, PHYADDR(0x12), 0x3602);
-			#ifdef CLK_OUT2_25MHZ
-			/* Bandwidth Control Enable Register: enable */
-			miiphy_write(name, PHYADDR(0x33), 0x4000);
-			#endif
-		}
-	}
-
-	debug("\nsearching for TANTOS switch ... ");
-	if (miiphy_read(name, PHYADDR(0x101), &chipid0) == 0) {
-		if (chipid0 == ID_TANTOS) {
-			debug("found");
-
-			/* P5 Basic Control: Force Link Up */
-			miiphy_write(name, PHYADDR(0xA1), 0x0004);
-			/* P6 Basic Control: Force Link Up */
-			miiphy_write(name, PHYADDR(0xC1), 0x0004);
-			/* RGMII/MII Port Control (P4/5/6) */
-			miiphy_write(name, PHYADDR(0xF5), 0x0773);
-
-			/* Software workaround. */
-			/* PHY reset from P0 to P4. */
-
-			/* set data for indirect write */
-			miiphy_write(name, PHYADDR(0x121), 0x8000);
-
-			/* P0 */
-			miiphy_write(name, PHYADDR(0x120), 0x0400);
-			udelay(1000);
-			/* P1 */
-			miiphy_write(name, PHYADDR(0x120), 0x0420);
-			udelay(1000);
-			/* P2 */
-			miiphy_write(name, PHYADDR(0x120), 0x0440);
-			udelay(1000);
-			/* P3 */
-			miiphy_write(name, PHYADDR(0x120), 0x0460);
-			udelay(1000);
-			/* P4 */
-			miiphy_write(name, PHYADDR(0x120), 0x0480);
-			udelay(1000);
-		}
-	}
-	debug("\n");
-
-	return 0;
-}
-#endif /* CONFIG_EXTRA_SWITCH */
-
-int board_gpio_init(void)
-{
-#ifdef CONFIG_BUTTON_PORT0
-	*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
-	*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
-	*DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
-	if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
-	{
-		printf("button is pressed\n");
-		setenv("bootdelay", "0");
-		setenv("bootcmd", "httpd");
-	}
-#elif defined(CONFIG_BUTTON_PORT1)
-	*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
-	*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
-	*DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
-	if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
-	{
-		printf("button is pressed\n");
-		setenv("bootdelay", "0");
-		setenv("bootcmd", "httpd");
-	}
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
-
-	board_gpio_init();
-
-#if defined(CONFIG_IFX_ETOP)
-
-	*DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
-	*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
-
-	if (lq_eth_initialize(bis)<0)
-		return -1;
-
-	*DANUBE_RCU_RST_REQ |=1;
-	udelay(200000);
-	*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
-	udelay(1000);
-
-#ifdef CONFIG_EXTRA_SWITCH
-	if (external_switch_init()<0)
-		return -1;
-#endif /* CONFIG_EXTRA_SWITCH */
-#endif /* CONFIG_IFX_ETOP */
-
-	return 0;
-}
-
-#if defined(CONFIG_CMD_HTTPD)
-int do_http_upgrade(const unsigned char *data, const ulong size)
-{
-	char buf[128];
-
-	if(getenv ("ram_addr") == NULL)
-		return -1;
-	if(getenv ("kernel_addr") == NULL)
-		return -1;
-	/* check the image */
-	if(run_command("imi ${ram_addr}", 0) < 0) {
-		return -1;
-	}
-	/* write the image to the flash */
-	puts("http ugrade ...\n");
-	sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
-	return run_command(buf, 0);
-}
-
-int do_http_progress(const int state)
-{
-	/* toggle LED's here */
-	switch(state) {
-		case HTTP_PROGRESS_START:
-		puts("http start\n");
-		break;
-		case HTTP_PROGRESS_TIMEOUT:
-		puts(".");
-		break;
-		case HTTP_PROGRESS_UPLOAD_READY:
-		puts("http upload ready\n");
-		break;
-		case HTTP_PROGRESS_UGRADE_READY:
-		puts("http ugrade ready\n");
-		break;
-		case HTTP_PROGRESS_UGRADE_FAILED:
-		puts("http ugrade failed\n");
-		break;
-	}
-	return 0;
-}
-
-unsigned long do_http_tmp_address(void)
-{
-	char *s = getenv ("ram_addr");
-	if (s) {
-		ulong tmp = simple_strtoul (s, NULL, 16);
-		return tmp;
-	}
-	return 0 /*0x80a00000*/;
-}
-
-#endif
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
deleted file mode 100644
index 3a4b1350e4..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0xf3c
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x300
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA03
-#define MC_DC21_VALUE	0x1d00
-#define MC_DC22_VALUE	0x1d1d
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x5e   /* was 0x7f */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x2d89
-#define MC_DC30_VALUE	0x8300
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_PROMOSDDR400.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_PROMOSDDR400.h
deleted file mode 100644
index 54bb6c9e37..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_PROMOSDDR400.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xa02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x0
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0xf3c  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x300
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1200
-#define MC_DC22_VALUE	0x1212
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x62   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x4e20
-#define MC_DC30_VALUE	0x8300
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_Samsung_166.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_Samsung_166.h
deleted file mode 100644
index 7975c3ec0d..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_Samsung_166.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x120  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1400
-#define MC_DC22_VALUE	0x1414
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x4e   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x2d93
-#define MC_DC30_VALUE	0x8235
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e111.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e111.h
deleted file mode 100644
index b655ca2898..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e111.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0xf3c  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x300
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA03  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1800
-#define MC_DC22_VALUE	0x1818
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x5e   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x2d89
-#define MC_DC30_VALUE	0x8300
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e166.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e166.h
deleted file mode 100644
index b655ca2898..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e166.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0xf3c  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x300
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA03  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1800
-#define MC_DC22_VALUE	0x1818
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x5e   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x2d89
-#define MC_DC30_VALUE	0x8300
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h
deleted file mode 100644
index 445b7dac1f..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x120  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1700
-#define MC_DC22_VALUE	0x1717
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x52   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x4e20
-#define MC_DC30_VALUE	0x8235
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h
deleted file mode 100644
index fd155973ee..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0xf3c  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x300
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1200
-#define MC_DC22_VALUE	0x1212
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x5e   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x2d89
-#define MC_DC30_VALUE	0x8300
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r166.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r166.h
deleted file mode 100644
index 742d34f1d3..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r166.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0xf3c  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x300
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0xd00
-#define MC_DC22_VALUE	0xd0d
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x62   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x2d89
-#define MC_DC30_VALUE	0x8300
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/easy50712_bootstrap.c b/package/uboot-lantiq/files/board/infineon/easy50712/easy50712_bootstrap.c
deleted file mode 100644
index 11bf6d0b71..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/easy50712_bootstrap.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2007
- * Vlad Lungu vlad.lungu@windriver.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-
-phys_size_t bootstrap_initdram(int board_type)
-{
-	/* Sdram is setup by assembler code */
-	/* If memory could be changed, we should return the true value here */
-	return CONFIG_SYS_MAX_RAM;
-}
-
-int bootstrap_checkboard(void)
-{
-	return 0;
-}
-
-int bootstrap_misc_init_r(void)
-{
-	set_io_port_base(0);
-	return 0;
-}
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_bootstrap_init.S b/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_bootstrap_init.S
deleted file mode 100644
index 216c381455..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_bootstrap_init.S
+++ /dev/null
@@ -1,606 +0,0 @@
-/*
- *  Memory sub-system initialization code for Danube board.
- *  Andre Messerschmidt
- *  Copyright (c) 2005	Infineon Technologies AG
- *
- *  Based on Inca-IP code
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
-      peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_RAM)
-
-#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
-#include "ddr_settings_r111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
-#include "ddr_settings_r166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
-#include "ddr_settings_e111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
-#include "ddr_settings_e166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
-#include "ddr_settings_PROMOSDDR400.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
-#include "ddr_settings_Samsung_166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
-#include "ddr_settings_psc_166.h"
-#define DDR166
-#else
-#warning "missing definition for ddr_settings.h, use default!"
-#include "ddr_settings.h"
-#endif
-#endif /* CONFIG_USE_DDR_RAM */
-
-#if defined(CONFIG_USE_DDR_RAM) &&  !defined(MC_DC0_VALUE)
-#error "missing include of ddr_settings.h"
-#endif
-
-#define EBU_MODUL_BASE		0xBE105300
-#define EBU_CLC(value)		0x0000(value)
-#define EBU_CON(value)		0x0010(value)
-#define EBU_ADDSEL0(value)	0x0020(value)
-#define EBU_ADDSEL1(value)	0x0024(value)
-#define EBU_ADDSEL2(value)	0x0028(value)
-#define EBU_ADDSEL3(value)	0x002C(value)
-#define EBU_BUSCON0(value)	0x0060(value)
-#define EBU_BUSCON1(value)	0x0064(value)
-#define EBU_BUSCON2(value)	0x0068(value)
-#define EBU_BUSCON3(value)	0x006C(value)
-
-#define MC_MODUL_BASE		0xBF800000
-#define MC_ERRCAUSE(value)	0x0010(value)
-#define MC_ERRADDR(value)	0x0020(value)
-#define MC_CON(value)		0x0060(value)
-
-#define MC_SRAM_ENABLE		0x00000004
-#define MC_SDRAM_ENABLE		0x00000002
-#define MC_DDRRAM_ENABLE	0x00000001
-
-#define MC_SDR_MODUL_BASE	0xBF800200
-#define MC_IOGP(value)		0x0000(value)
-#define MC_CTRLENA(value)	0x0010(value)
-#define MC_MRSCODE(value)	0x0020(value)
-#define MC_CFGDW(value)		0x0030(value)
-#define MC_CFGPB0(value)	0x0040(value)
-#define MC_LATENCY(value)	0x0080(value)
-#define MC_TREFRESH(value)	0x0090(value)
-#define MC_SELFRFSH(value)	0x00A0(value)
-
-#define MC_DDR_MODUL_BASE	0xBF801000
-#define MC_DC00(value)		0x0000(value)
-#define MC_DC01(value)		0x0010(value)
-#define MC_DC02(value)		0x0020(value)
-#define MC_DC03(value)		0x0030(value)
-#define MC_DC04(value)		0x0040(value)
-#define MC_DC05(value)		0x0050(value)
-#define MC_DC06(value)		0x0060(value)
-#define MC_DC07(value)		0x0070(value)
-#define MC_DC08(value)		0x0080(value)
-#define MC_DC09(value)		0x0090(value)
-#define MC_DC10(value)		0x00A0(value)
-#define MC_DC11(value)		0x00B0(value)
-#define MC_DC12(value)		0x00C0(value)
-#define MC_DC13(value)		0x00D0(value)
-#define MC_DC14(value)		0x00E0(value)
-#define MC_DC15(value)		0x00F0(value)
-#define MC_DC16(value)		0x0100(value)
-#define MC_DC17(value)		0x0110(value)
-#define MC_DC18(value)		0x0120(value)
-#define MC_DC19(value)		0x0130(value)
-#define MC_DC20(value)		0x0140(value)
-#define MC_DC21(value)		0x0150(value)
-#define MC_DC22(value)		0x0160(value)
-#define MC_DC23(value)		0x0170(value)
-#define MC_DC24(value)		0x0180(value)
-#define MC_DC25(value)		0x0190(value)
-#define MC_DC26(value)		0x01A0(value)
-#define MC_DC27(value)		0x01B0(value)
-#define MC_DC28(value)		0x01C0(value)
-#define MC_DC29(value)		0x01D0(value)
-#define MC_DC30(value)		0x01E0(value)
-#define MC_DC31(value)		0x01F0(value)
-#define MC_DC32(value)		0x0200(value)
-#define MC_DC33(value)		0x0210(value)
-#define MC_DC34(value)		0x0220(value)
-#define MC_DC35(value)		0x0230(value)
-#define MC_DC36(value)		0x0240(value)
-#define MC_DC37(value)		0x0250(value)
-#define MC_DC38(value)		0x0260(value)
-#define MC_DC39(value)		0x0270(value)
-#define MC_DC40(value)		0x0280(value)
-#define MC_DC41(value)		0x0290(value)
-#define MC_DC42(value)		0x02A0(value)
-#define MC_DC43(value)		0x02B0(value)
-#define MC_DC44(value)		0x02C0(value)
-#define MC_DC45(value)		0x02D0(value)
-#define MC_DC46(value)		0x02E0(value)
-
-#define RCU_OFFSET  0xBF203000
-#define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
-#define RCU_STS          (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET  0xBF103000
-#define  PLL0_CFG     (CGU_OFFSET + 0x0004)
-#define  PLL1_CFG     (CGU_OFFSET + 0x0008)
-#define  PLL2_CFG     (CGU_OFFSET + 0x000C)
-#define  CGU_SYS      (CGU_OFFSET + 0x0010)
-#define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
-#define  IF_CLK       (CGU_OFFSET + 0x0018)
-#define  CGU_SMD      (CGU_OFFSET + 0x0020)
-#define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
-#define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
-#define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
-#define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
-#define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
-
-//05252006
-#define  pll0_35MHz_CONFIG 0x9D861059
-#define  pll1_35MHz_CONFIG 0x1A260CD9
-#define  pll2_35MHz_CONFIG 0x8000f1e5
-#define  pll0_36MHz_CONFIG 0x1000125D
-#define  pll1_36MHz_CONFIG 0x1B1E0C99
-#define  pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET  0xBE105400
-#define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE  0xB7000000
-#define CS_CFM		(PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
-	.set	noreorder
-
-
-/*
- * void ebu_init(void)
- */
-	.globl	ebu_init
-	.ent	ebu_init
-ebu_init:
-
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
-	defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
-	defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
-	defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
-	li	t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
-	li	t2, CONFIG_EBU_ADDSEL0
-	sw	t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
-	li	t2, CONFIG_EBU_ADDSEL1
-	sw	t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
-	li	t2, CONFIG_EBU_ADDSEL2
-	sw	t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
-	li	t2, CONFIG_EBU_ADDSEL3
-	sw	t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
-	li	t2, CONFIG_EBU_BUSCON0
-	sw	t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
-	li	t2, CONFIG_EBU_BUSCON1
-	sw	t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
-	li	t2, CONFIG_EBU_BUSCON2
-	sw	t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
-	li	t2, CONFIG_EBU_BUSCON3
-	sw	t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
-	j	ra
-	nop
-
-	.end	ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
-	.globl	cgu_init
-	.ent	cgu_init
-cgu_init:
-	li  t2, CGU_SYS
-	lw  t2,0(t2)
-	beq t2,a0,freq_up2date
-	nop
-
-	li  t2, RCU_STS
-	lw  t2, 0(t2)
-	and t2,0x00020000
-	beq t2,0x00020000,boot_36MHZ
-	nop
-//05252006
-	li  t1, PLL0_CFG
-	li  t2, pll0_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-	b   wait_reset
-	nop
-boot_36MHZ:
-	li  t1, PLL0_CFG
-	li  t2, pll0_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-//05252006
-
-wait_reset:
-	b   wait_reset
-	nop
-freq_up2date:
-	j ra
-	nop
-
-	.end	cgu_init
-
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	sdram_init
-	.ent	sdram_init
-sdram_init:
-
-	/* SDRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable SDRAM module in memory controller */
-	li	t3, MC_SDRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_SDR_MODUL_BASE
-
-	/* disable the controller */
-	li	t2, 0
-	sw	t2, MC_CTRLENA(t1)
-
-	li	t2, 0x822
-	sw	t2, MC_IOGP(t1)
-
-	li	t2, 0x2
-	sw	t2, MC_CFGDW(t1)
-
-	/* Set CAS Latency */
-	li	t2, 0x00000020
-	sw	t2, MC_MRSCODE(t1)
-
-	/* Set CS0 to SDRAM parameters */
-	li	t2, 0x000014d8
-	sw	t2, MC_CFGPB0(t1)
-
-	/* Set SDRAM latency parameters */
-	li  	t2, 0x00036325;   /* BC PC100 */
-	sw	t2, MC_LATENCY(t1)
-
-	/* Set SDRAM refresh rate */
-	li	t2, 0x00000C30
-	sw	t2, MC_TREFRESH(t1)
-
-	/* Clear Power-down registers */
-	sw	zero, MC_SELFRFSH(t1)
-
-	/* Finally enable the controller */
-	li	t2, 1
-	sw	t2, MC_CTRLENA(t1)
-
-	j	ra
-	nop
-
-	.end	sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	ddrram_init
-	.ent	ddrram_init
-ddrram_init:
-
-	/* DDR-DRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable DDR module in memory controller */
-	li	t3, MC_DDRRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_DDR_MODUL_BASE
-
-	/* Write configuration to DDR controller registers */
-	li	t2, MC_DC0_VALUE
-	sw	t2, MC_DC00(t1)
-
-	li	t2, MC_DC1_VALUE
-	sw	t2, MC_DC01(t1)
-
-	li	t2, MC_DC2_VALUE
-	sw	t2, MC_DC02(t1)
-
-	li	t2, MC_DC3_VALUE
-	sw	t2, MC_DC03(t1)
-
-	li	t2, MC_DC4_VALUE
-	sw	t2, MC_DC04(t1)
-
-	li	t2, MC_DC5_VALUE
-	sw	t2, MC_DC05(t1)
-
-	li	t2, MC_DC6_VALUE
-	sw	t2, MC_DC06(t1)
-
-	li	t2, MC_DC7_VALUE
-	sw	t2, MC_DC07(t1)
-
-	li	t2, MC_DC8_VALUE
-	sw	t2, MC_DC08(t1)
-
-	li	t2, MC_DC9_VALUE
-	sw	t2, MC_DC09(t1)
-
-	li	t2, MC_DC10_VALUE
-	sw	t2, MC_DC10(t1)
-
-	li	t2, MC_DC11_VALUE
-	sw	t2, MC_DC11(t1)
-
-	li	t2, MC_DC12_VALUE
-	sw	t2, MC_DC12(t1)
-
-	li	t2, MC_DC13_VALUE
-	sw	t2, MC_DC13(t1)
-
-	li	t2, MC_DC14_VALUE
-	sw	t2, MC_DC14(t1)
-
-	li	t2, MC_DC15_VALUE
-	sw	t2, MC_DC15(t1)
-
-	li	t2, MC_DC16_VALUE
-	sw	t2, MC_DC16(t1)
-
-	li	t2, MC_DC17_VALUE
-	sw	t2, MC_DC17(t1)
-
-	li	t2, MC_DC18_VALUE
-	sw	t2, MC_DC18(t1)
-
-	li	t2, MC_DC19_VALUE
-	sw	t2, MC_DC19(t1)
-
-	li	t2, MC_DC20_VALUE
-	sw	t2, MC_DC20(t1)
-
-	li	t2, MC_DC21_VALUE
-	sw	t2, MC_DC21(t1)
-
-	li	t2, MC_DC22_VALUE
-	sw	t2, MC_DC22(t1)
-
-	li	t2, MC_DC23_VALUE
-	sw	t2, MC_DC23(t1)
-
-	li	t2, MC_DC24_VALUE
-	sw	t2, MC_DC24(t1)
-
-	li	t2, MC_DC25_VALUE
-	sw	t2, MC_DC25(t1)
-
-	li	t2, MC_DC26_VALUE
-	sw	t2, MC_DC26(t1)
-
-	li	t2, MC_DC27_VALUE
-	sw	t2, MC_DC27(t1)
-
-	li	t2, MC_DC28_VALUE
-	sw	t2, MC_DC28(t1)
-
-	li	t2, MC_DC29_VALUE
-	sw	t2, MC_DC29(t1)
-
-	li	t2, MC_DC30_VALUE
-	sw	t2, MC_DC30(t1)
-
-	li	t2, MC_DC31_VALUE
-	sw	t2, MC_DC31(t1)
-
-	li	t2, MC_DC32_VALUE
-	sw	t2, MC_DC32(t1)
-
-	li	t2, MC_DC33_VALUE
-	sw	t2, MC_DC33(t1)
-
-	li	t2, MC_DC34_VALUE
-	sw	t2, MC_DC34(t1)
-
-	li	t2, MC_DC35_VALUE
-	sw	t2, MC_DC35(t1)
-
-	li	t2, MC_DC36_VALUE
-	sw	t2, MC_DC36(t1)
-
-	li	t2, MC_DC37_VALUE
-	sw	t2, MC_DC37(t1)
-
-	li	t2, MC_DC38_VALUE
-	sw	t2, MC_DC38(t1)
-
-	li	t2, MC_DC39_VALUE
-	sw	t2, MC_DC39(t1)
-
-	li	t2, MC_DC40_VALUE
-	sw	t2, MC_DC40(t1)
-
-	li	t2, MC_DC41_VALUE
-	sw	t2, MC_DC41(t1)
-
-	li	t2, MC_DC42_VALUE
-	sw	t2, MC_DC42(t1)
-
-	li	t2, MC_DC43_VALUE
-	sw	t2, MC_DC43(t1)
-
-	li	t2, MC_DC44_VALUE
-	sw	t2, MC_DC44(t1)
-
-	li	t2, MC_DC45_VALUE
-	sw	t2, MC_DC45(t1)
-
-	li	t2, MC_DC46_VALUE
-	sw	t2, MC_DC46(t1)
-
-	li	t2, 0x00000100
-	sw	t2, MC_DC03(t1)
-
-	j	ra
-	nop
-
-	.end	ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
-	.globl	lowlevel_init
-	.ent	lowlevel_init
-lowlevel_init:
-	/* EBU, CGU and SDRAM/DDR-RAM Initialization.
-	 */
-	move	t0, ra
-	/* We rely on the fact that non of the following ..._init() functions
-	 * modify t0
-	 */
-#if defined(DDR166)
-	/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
-	li  a0,0xe8
-#elif defined(DDR133)
-	/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
-	li  a0,0xe9
-#else /* defined(DDR111) */
-	/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
-	li  a0,0xea
-#endif
-	bal	cgu_init
-	nop
-
-	bal	ebu_init
-	nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
-	li  t1, PCI_CR_PCI	//mw bf103034 80000000
-	li  t2, 0x80000000
-	sw	t2,0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x103
-	sw  t2,0(t1)
-
-	li  t1, CS_CFM			//mw b700006c 0
-	li  t2, 0x00
-	sw  t2, 0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x1000103
-	sw  t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
-#ifdef CONFIG_USE_DDR_RAM
-	bal	ddrram_init
-	nop
-#else
-	bal	sdram_init
-	nop
-#endif
-	move	ra, t0
-	j	ra
-	nop
-
-	.end	lowlevel_init
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_init.S b/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_init.S
deleted file mode 100644
index 4dc179fc05..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_init.S
+++ /dev/null
@@ -1,613 +0,0 @@
-/*
- *  Memory sub-system initialization code for Danube board.
- *  Andre Messerschmidt
- *  Copyright (c) 2005	Infineon Technologies AG
- *
- *  Based on Inca-IP code
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
-      peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_RAM)
-
-#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
-#include "ddr_settings_r111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
-#include "ddr_settings_r166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
-#include "ddr_settings_e111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
-#include "ddr_settings_e166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
-#include "ddr_settings_PROMOSDDR400.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
-#include "ddr_settings_Samsung_166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
-#include "ddr_settings_psc_166.h"
-#define DDR166
-#else
-#warning "missing definition for ddr_settings.h, use default!"
-#include "ddr_settings.h"
-#endif
-#endif /* CONFIG_USE_DDR_RAM */
-
-#if defined(CONFIG_USE_DDR_RAM) &&  !defined(MC_DC0_VALUE)
-#error "missing include of ddr_settings.h"
-#endif
-
-#define EBU_MODUL_BASE		0xBE105300
-#define EBU_CLC(value)		0x0000(value)
-#define EBU_CON(value)		0x0010(value)
-#define EBU_ADDSEL0(value)	0x0020(value)
-#define EBU_ADDSEL1(value)	0x0024(value)
-#define EBU_ADDSEL2(value)	0x0028(value)
-#define EBU_ADDSEL3(value)	0x002C(value)
-#define EBU_BUSCON0(value)	0x0060(value)
-#define EBU_BUSCON1(value)	0x0064(value)
-#define EBU_BUSCON2(value)	0x0068(value)
-#define EBU_BUSCON3(value)	0x006C(value)
-
-#define MC_MODUL_BASE		0xBF800000
-#define MC_ERRCAUSE(value)	0x0010(value)
-#define MC_ERRADDR(value)	0x0020(value)
-#define MC_CON(value)		0x0060(value)
-
-#define MC_SRAM_ENABLE		0x00000004
-#define MC_SDRAM_ENABLE		0x00000002
-#define MC_DDRRAM_ENABLE	0x00000001
-
-#define MC_SDR_MODUL_BASE	0xBF800200
-#define MC_IOGP(value)		0x0000(value)
-#define MC_CTRLENA(value)	0x0010(value)
-#define MC_MRSCODE(value)	0x0020(value)
-#define MC_CFGDW(value)		0x0030(value)
-#define MC_CFGPB0(value)	0x0040(value)
-#define MC_LATENCY(value)	0x0080(value)
-#define MC_TREFRESH(value)	0x0090(value)
-#define MC_SELFRFSH(value)	0x00A0(value)
-
-#define MC_DDR_MODUL_BASE	0xBF801000
-#define MC_DC00(value)		0x0000(value)
-#define MC_DC01(value)		0x0010(value)
-#define MC_DC02(value)		0x0020(value)
-#define MC_DC03(value)		0x0030(value)
-#define MC_DC04(value)		0x0040(value)
-#define MC_DC05(value)		0x0050(value)
-#define MC_DC06(value)		0x0060(value)
-#define MC_DC07(value)		0x0070(value)
-#define MC_DC08(value)		0x0080(value)
-#define MC_DC09(value)		0x0090(value)
-#define MC_DC10(value)		0x00A0(value)
-#define MC_DC11(value)		0x00B0(value)
-#define MC_DC12(value)		0x00C0(value)
-#define MC_DC13(value)		0x00D0(value)
-#define MC_DC14(value)		0x00E0(value)
-#define MC_DC15(value)		0x00F0(value)
-#define MC_DC16(value)		0x0100(value)
-#define MC_DC17(value)		0x0110(value)
-#define MC_DC18(value)		0x0120(value)
-#define MC_DC19(value)		0x0130(value)
-#define MC_DC20(value)		0x0140(value)
-#define MC_DC21(value)		0x0150(value)
-#define MC_DC22(value)		0x0160(value)
-#define MC_DC23(value)		0x0170(value)
-#define MC_DC24(value)		0x0180(value)
-#define MC_DC25(value)		0x0190(value)
-#define MC_DC26(value)		0x01A0(value)
-#define MC_DC27(value)		0x01B0(value)
-#define MC_DC28(value)		0x01C0(value)
-#define MC_DC29(value)		0x01D0(value)
-#define MC_DC30(value)		0x01E0(value)
-#define MC_DC31(value)		0x01F0(value)
-#define MC_DC32(value)		0x0200(value)
-#define MC_DC33(value)		0x0210(value)
-#define MC_DC34(value)		0x0220(value)
-#define MC_DC35(value)		0x0230(value)
-#define MC_DC36(value)		0x0240(value)
-#define MC_DC37(value)		0x0250(value)
-#define MC_DC38(value)		0x0260(value)
-#define MC_DC39(value)		0x0270(value)
-#define MC_DC40(value)		0x0280(value)
-#define MC_DC41(value)		0x0290(value)
-#define MC_DC42(value)		0x02A0(value)
-#define MC_DC43(value)		0x02B0(value)
-#define MC_DC44(value)		0x02C0(value)
-#define MC_DC45(value)		0x02D0(value)
-#define MC_DC46(value)		0x02E0(value)
-
-#define RCU_OFFSET  0xBF203000
-#define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
-#define RCU_STS          (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET  0xBF103000
-#define  PLL0_CFG     (CGU_OFFSET + 0x0004)
-#define  PLL1_CFG     (CGU_OFFSET + 0x0008)
-#define  PLL2_CFG     (CGU_OFFSET + 0x000C)
-#define  CGU_SYS      (CGU_OFFSET + 0x0010)
-#define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
-#define  IF_CLK       (CGU_OFFSET + 0x0018)
-#define  CGU_SMD      (CGU_OFFSET + 0x0020)
-#define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
-#define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
-#define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
-#define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
-#define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
-
-//05252006
-#define  pll0_35MHz_CONFIG 0x9D861059
-#define  pll1_35MHz_CONFIG 0x1A260CD9
-#define  pll2_35MHz_CONFIG 0x8000f1e5
-#define  pll0_36MHz_CONFIG 0x1000125D
-#define  pll1_36MHz_CONFIG 0x1B1E0C99
-#define  pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET  0xBE105400
-#define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE  0xB7000000
-#define CS_CFM		(PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
-	.set	noreorder
-
-
-/*
- * void ebu_init(void)
- */
-	.globl	ebu_init
-	.ent	ebu_init
-ebu_init:
-
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
-	defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
-	defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
-	defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
-	li	t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
-	li	t2, CONFIG_EBU_ADDSEL0
-	sw	t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
-	li	t2, CONFIG_EBU_ADDSEL1
-	sw	t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
-	li	t2, CONFIG_EBU_ADDSEL2
-	sw	t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
-	li	t2, CONFIG_EBU_ADDSEL3
-	sw	t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
-	li	t2, CONFIG_EBU_BUSCON0
-	sw	t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
-	li	t2, CONFIG_EBU_BUSCON1
-	sw	t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
-	li	t2, CONFIG_EBU_BUSCON2
-	sw	t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
-	li	t2, CONFIG_EBU_BUSCON3
-	sw	t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
-	j	ra
-	nop
-
-	.end	ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
-	.globl	cgu_init
-	.ent	cgu_init
-cgu_init:
-	li  t2, CGU_SYS
-	lw  t2,0(t2)
-	beq t2,a0,freq_up2date
-	nop
-
-	li  t2, RCU_STS
-	lw  t2, 0(t2)
-	and t2,0x00020000
-	beq t2,0x00020000,boot_36MHZ
-	nop
-//05252006
-	li  t1, PLL0_CFG
-	li  t2, pll0_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-	b   wait_reset
-	nop
-boot_36MHZ:
-	li  t1, PLL0_CFG
-	li  t2, pll0_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-//05252006
-
-wait_reset:
-	b   wait_reset
-	nop
-freq_up2date:
-	j ra
-	nop
-
-	.end	cgu_init
-
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	sdram_init
-	.ent	sdram_init
-sdram_init:
-
-	/* SDRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable SDRAM module in memory controller */
-	li	t3, MC_SDRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_SDR_MODUL_BASE
-
-	/* disable the controller */
-	li	t2, 0
-	sw	t2, MC_CTRLENA(t1)
-
-	li	t2, 0x822
-	sw	t2, MC_IOGP(t1)
-
-	li	t2, 0x2
-	sw	t2, MC_CFGDW(t1)
-
-	/* Set CAS Latency */
-	li	t2, 0x00000020
-	sw	t2, MC_MRSCODE(t1)
-
-	/* Set CS0 to SDRAM parameters */
-	li	t2, 0x000014d8
-	sw	t2, MC_CFGPB0(t1)
-
-	/* Set SDRAM latency parameters */
-	li  	t2, 0x00036325;   /* BC PC100 */
-	sw	t2, MC_LATENCY(t1)
-
-	/* Set SDRAM refresh rate */
-	li	t2, 0x00000C30
-	sw	t2, MC_TREFRESH(t1)
-
-	/* Clear Power-down registers */
-	sw	zero, MC_SELFRFSH(t1)
-
-	/* Finally enable the controller */
-	li	t2, 1
-	sw	t2, MC_CTRLENA(t1)
-
-	j	ra
-	nop
-
-	.end	sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	ddrram_init
-	.ent	ddrram_init
-ddrram_init:
-
-	/* DDR-DRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable DDR module in memory controller */
-	li	t3, MC_DDRRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_DDR_MODUL_BASE
-
-	/* Write configuration to DDR controller registers */
-	li	t2, MC_DC0_VALUE
-	sw	t2, MC_DC00(t1)
-
-	li	t2, MC_DC1_VALUE
-	sw	t2, MC_DC01(t1)
-
-	li	t2, MC_DC2_VALUE
-	sw	t2, MC_DC02(t1)
-
-	li	t2, MC_DC3_VALUE
-	sw	t2, MC_DC03(t1)
-
-	li	t2, MC_DC4_VALUE
-	sw	t2, MC_DC04(t1)
-
-	li	t2, MC_DC5_VALUE
-	sw	t2, MC_DC05(t1)
-
-	li	t2, MC_DC6_VALUE
-	sw	t2, MC_DC06(t1)
-
-	li	t2, MC_DC7_VALUE
-	sw	t2, MC_DC07(t1)
-
-	li	t2, MC_DC8_VALUE
-	sw	t2, MC_DC08(t1)
-
-	li	t2, MC_DC9_VALUE
-	sw	t2, MC_DC09(t1)
-
-	li	t2, MC_DC10_VALUE
-	sw	t2, MC_DC10(t1)
-
-	li	t2, MC_DC11_VALUE
-	sw	t2, MC_DC11(t1)
-
-	li	t2, MC_DC12_VALUE
-	sw	t2, MC_DC12(t1)
-
-	li	t2, MC_DC13_VALUE
-	sw	t2, MC_DC13(t1)
-
-	li	t2, MC_DC14_VALUE
-	sw	t2, MC_DC14(t1)
-
-	li	t2, MC_DC15_VALUE
-	sw	t2, MC_DC15(t1)
-
-	li	t2, MC_DC16_VALUE
-	sw	t2, MC_DC16(t1)
-
-	li	t2, MC_DC17_VALUE
-	sw	t2, MC_DC17(t1)
-
-	li	t2, MC_DC18_VALUE
-	sw	t2, MC_DC18(t1)
-
-	li	t2, MC_DC19_VALUE
-	sw	t2, MC_DC19(t1)
-
-	li	t2, MC_DC20_VALUE
-	sw	t2, MC_DC20(t1)
-
-	li	t2, MC_DC21_VALUE
-	sw	t2, MC_DC21(t1)
-
-	li	t2, MC_DC22_VALUE
-	sw	t2, MC_DC22(t1)
-
-	li	t2, MC_DC23_VALUE
-	sw	t2, MC_DC23(t1)
-
-	li	t2, MC_DC24_VALUE
-	sw	t2, MC_DC24(t1)
-
-	li	t2, MC_DC25_VALUE
-	sw	t2, MC_DC25(t1)
-
-	li	t2, MC_DC26_VALUE
-	sw	t2, MC_DC26(t1)
-
-	li	t2, MC_DC27_VALUE
-	sw	t2, MC_DC27(t1)
-
-	li	t2, MC_DC28_VALUE
-	sw	t2, MC_DC28(t1)
-
-	li	t2, MC_DC29_VALUE
-	sw	t2, MC_DC29(t1)
-
-	li	t2, MC_DC30_VALUE
-	sw	t2, MC_DC30(t1)
-
-	li	t2, MC_DC31_VALUE
-	sw	t2, MC_DC31(t1)
-
-	li	t2, MC_DC32_VALUE
-	sw	t2, MC_DC32(t1)
-
-	li	t2, MC_DC33_VALUE
-	sw	t2, MC_DC33(t1)
-
-	li	t2, MC_DC34_VALUE
-	sw	t2, MC_DC34(t1)
-
-	li	t2, MC_DC35_VALUE
-	sw	t2, MC_DC35(t1)
-
-	li	t2, MC_DC36_VALUE
-	sw	t2, MC_DC36(t1)
-
-	li	t2, MC_DC37_VALUE
-	sw	t2, MC_DC37(t1)
-
-	li	t2, MC_DC38_VALUE
-	sw	t2, MC_DC38(t1)
-
-	li	t2, MC_DC39_VALUE
-	sw	t2, MC_DC39(t1)
-
-	li	t2, MC_DC40_VALUE
-	sw	t2, MC_DC40(t1)
-
-	li	t2, MC_DC41_VALUE
-	sw	t2, MC_DC41(t1)
-
-	li	t2, MC_DC42_VALUE
-	sw	t2, MC_DC42(t1)
-
-	li	t2, MC_DC43_VALUE
-	sw	t2, MC_DC43(t1)
-
-	li	t2, MC_DC44_VALUE
-	sw	t2, MC_DC44(t1)
-
-	li	t2, MC_DC45_VALUE
-	sw	t2, MC_DC45(t1)
-
-	li	t2, MC_DC46_VALUE
-	sw	t2, MC_DC46(t1)
-
-	li	t2, 0x00000100
-	sw	t2, MC_DC03(t1)
-
-	j	ra
-	nop
-
-	.end	ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
-	.globl	lowlevel_init
-	.ent	lowlevel_init
-lowlevel_init:
-	/* EBU, CGU and SDRAM/DDR-RAM Initialization.
-	 */
-	move	t0, ra
-	/* We rely on the fact that non of the following ..._init() functions
-	 * modify t0
-	 */
-#if defined(CONFIG_SYS_EBU_BOOT)
-#if defined(DDR166)
-	/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
-	li  a0,0xe8
-#elif defined(DDR133)
-	/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
-	li  a0,0xe9
-#else /* defined(DDR111) */
-	/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
-	li  a0,0xea
-#endif
-	bal	cgu_init
-	nop
-#endif /* CONFIG_SYS_EBU_BOOT */
-
-	bal	ebu_init
-	nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
-	li  t1, PCI_CR_PCI	//mw bf103034 80000000
-	li  t2, 0x80000000
-	sw	t2,0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x103
-	sw  t2,0(t1)
-
-	li  t1, CS_CFM			//mw b700006c 0
-	li  t2, 0x00
-	sw  t2, 0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x1000103
-	sw  t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
-#ifdef CONFIG_SYS_EBU_BOOT
-#ifndef CONFIG_SYS_RAMBOOT
-#ifdef CONFIG_USE_DDR_RAM
-	bal	ddrram_init
-	nop
-#else
-	bal	sdram_init
-	nop
-#endif
-#endif /* CONFIG_SYS_RAMBOOT */
-#endif /* CONFIG_SYS_EBU_BOOT */
-
-	move	ra, t0
-	j	ra
-	nop
-
-	.end	lowlevel_init
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/pmuenable.S b/package/uboot-lantiq/files/board/infineon/easy50712/pmuenable.S
deleted file mode 100644
index e0d7971d89..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/pmuenable.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  Power Management unit initialization code for AMAZON development board.
- *
- *  Copyright (c) 2003	Ou Ke, Infineon.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#define PMU_PWDCR 		0xBF10201C
-#define PMU_SR			0xBF102020
-
-	.globl	pmuenable
-
-pmuenable:
-	li      t0, PMU_PWDCR
-	li      t1, 0x2		/* enable everything */
-	sw      t1, 0(t0)
-#if 0
-1:
-	li	t0, PMU_SR
-	lw      t2, 0(t0)
-	bne     t1, t2, 1b
-	nop
-#endif
-	j	ra
-	nop
-
-
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/u-boot-bootstrap.lds b/package/uboot-lantiq/files/board/infineon/easy50712/u-boot-bootstrap.lds
deleted file mode 100644
index 52d7dafadb..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/u-boot-bootstrap.lds
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = .;
-	_gp = ALIGN(16) +0x7ff0;
-
-	.got  : {
-	__got_start = .;
-		*(.got)
-	__got_end = .;
-	}
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	. = .;
-	. = ALIGN(4);
-	.payload : { *(.payload) }
-	. = ALIGN(4);
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) . = ALIGN(4); }
-	uboot_end = .;
-}
-
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/u-boot.lds b/package/uboot-lantiq/files/board/infineon/easy50712/u-boot.lds
deleted file mode 100644
index 9a6cd1b8a3..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50712/u-boot.lds
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	.got : {
-	  __got_start = .;
-	  *(.got)
-	  __got_end = .;
-	}
-
-	.sdata  : { *(.sdata) }
-
-	.u_boot_cmd : {
-	  __u_boot_cmd_start = .;
-	  *(.u_boot_cmd)
-	  __u_boot_cmd_end = .;
-	}
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss (NOLOAD)  : { *(.sbss) }
-	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
-	uboot_end = .;
-}
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/Makefile b/package/uboot-lantiq/files/board/infineon/easy50812/Makefile
deleted file mode 100644
index 97d1898954..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/Makefile
+++ /dev/null
@@ -1,62 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
-
-BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
-
-COBJS-y	+= ar9.o
-
-SOBJS	= lowlevel_init.o pmuenable.o
-
-BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
-BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
-
-BOOTSTRAP_SRCS	:= $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
-
-SRCS	:= $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-BOOTSTRAP_OBJS	:= $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
-BOOTSTRAP_SOBJS	:= $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
-
-
-all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-$(BOOTSTRAP_LIB):	 $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
-	$(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9.c b/package/uboot-lantiq/files/board/infineon/easy50812/ar9.c
deleted file mode 100644
index d4cd049afe..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9.c
+++ /dev/null
@@ -1,619 +0,0 @@
-/*
-* (C) Copyright 2003
-* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-*
-* (C) Copyright 2010
-* Thomas Langer, Ralph Hempel
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <asm/addrspace.h>
-#include <asm/ar9.h>
-#include <asm/reboot.h>
-#include <asm/io.h>
-#if defined(CONFIG_CMD_HTTPD)
-#include <httpd.h>
-#endif
-
-extern ulong ifx_get_ddr_hz(void);
-extern ulong ifx_get_cpuclk(void);
-
-/* definitions for external PHYs / Switches */
-/* Split values into phy address and register address */
-#define PHYADDR(_reg)	((_reg >> 5) & 0xff), (_reg & 0x1f)
-
-/* IDs and registers of known external switches */
-#define ID_SAMURAI_0			0x1020
-#define ID_SAMURAI_1			0x0007
-#define SAMURAI_ID_REG0			0xA0
-#define SAMURAI_ID_REG1			0xA1
-#define ID_TANTOS			0x2599
-
-#define RGMII_MODE			0
-#define MII_MODE			1
-#define REV_MII_MODE			2
-#define RED_MII_MODE_IC			3		/*Input clock */
-#define RGMII_MODE_100MB		4
-#define TURBO_REV_MII_MODE		6		/*Turbo Rev Mii mode */
-#define RED_MII_MODE_OC			7		/*Output clock */
-#define RGMII_MODE_10MB			8
-
-#define mdelay(n)   udelay((n)*1000)
-
-static void ar9_sw_chip_init(u8 port, u8 mode);
-static void ar9_enable_sw_port(u8 port, u8 state);
-static void ar9_configure_sw_port(u8 port, u8 mode);
-static u16 ar9_smi_reg_read(u16 reg);
-static u16 ar9_smi_reg_write(u16 reg, u16 data);
-static char * const name = "lq_cpe_eth";
-static int external_switch_init(void);
-
-void _machine_restart(void)
-{
-	*AR9_RCU_RST_REQ |= AR9_RST_ALL;
-}
-
-#ifdef CONFIG_SYS_RAMBOOT
-phys_size_t initdram(int board_type)
-{
-	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
-}
-#elif defined(CONFIG_USE_DDR_RAM)
-phys_size_t initdram(int board_type)
-{
-	return (CONFIG_SYS_MAX_RAM);
-}
-#else
-
-static ulong max_sdram_size(void)     /* per Chip Select */
-{
-	/* The only supported SDRAM data width is 16bit.
-	*/
-#define CFG_DW	4
-
-	/* The only supported number of SDRAM banks is 4.
-	*/
-#define CFG_NB	4
-
-	ulong cfgpb0 = *AR9_SDRAM_MC_CFGPB0;
-	int   cols   = cfgpb0 & 0xF;
-	int   rows   = (cfgpb0 & 0xF0) >> 4;
-	ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
-
-	return size;
-}
-
-/*
-* Check memory range for valid RAM. A simple memory test determines
-* the actually available RAM size between addresses `base' and
-* `base + maxsize'.
-*/
-
-static long int dram_size(long int *base, long int maxsize)
-{
-	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
-	unsigned char i = 0;
-
-	for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
-		addr = base + cnt;		/* pointer arith! */
-
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
-
-	/* write 0 to base address */
-	addr = base;
-	save[i] = *addr;
-	*addr = 0;
-
-	/* check at base address */
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
-		addr = base + cnt;		/* pointer arith! */
-
-		val = *addr;
-		*addr = save[--i];
-
-		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
-}
-
-phys_size_t initdram(int board_type)
-{
-	int   rows, cols, best_val = *AR9_SDRAM_MC_CFGPB0;
-	ulong size, max_size       = 0;
-	ulong our_address;
-
-	/* load t9 into our_address */
-	asm volatile ("move %0, $25" : "=r" (our_address) :);
-
-	/* Can't probe for RAM size unless we are running from Flash.
-	* find out whether running from DRAM or Flash.
-	*/
-	if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
-	{
-		return max_sdram_size();
-	}
-
-	for (cols = 0x8; cols <= 0xC; cols++)
-	{
-		for (rows = 0xB; rows <= 0xD; rows++)
-		{
-			*AR9_SDRAM_MC_CFGPB0 = (0x14 << 8) |
-											(rows << 4) | cols;
-			size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-											max_sdram_size());
-
-			if (size > max_size)
-			{
-				best_val = *AR9_SDRAM_MC_CFGPB0;
-				max_size = size;
-			}
-		}
-	}
-
-	*AR9_SDRAM_MC_CFGPB0 = best_val;
-	return max_size;
-}
-#endif
-
-int checkboard (void)
-{
-	unsigned long chipid = *AR9_MPS_CHIPID;
-	int part_num;
-
-	puts ("Board: ");
-
-	part_num = AR9_MPS_CHIPID_PARTNUM_GET(chipid);
-	switch (part_num)
-	{
-	case 0x16C:
-		puts("ARX188 ");
-		break;
-	case 0x16D:
-		puts("ARX168 ");
-		break;
-	case 0x16F:
-		puts("ARX182 ");
-		break;
-	case 0x170:
-		puts("GRX188 ");
-		break;
-	case 0x171:
-		puts("GRX168 ");
-		break;
-	default:
-		printf ("unknown, chip part number 0x%03X ", part_num);
-		break;
-	}
-	printf ("V1.%ld, ", AR9_MPS_CHIPID_VERSION_GET(chipid));
-
-	printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
-	printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
-
-	return 0;
-}
-
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-int board_early_init_f(void)
-{
-#ifdef CONFIG_EBU_ADDSEL0
-	(*AR9_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
-#endif
-#ifdef CONFIG_EBU_ADDSEL1
-	(*AR9_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
-#endif
-#ifdef CONFIG_EBU_ADDSEL2
-	(*AR9_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
-#endif
-#ifdef CONFIG_EBU_ADDSEL3
-	(*AR9_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
-#endif
-#ifdef CONFIG_EBU_BUSCON0
-	(*AR9_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
-#endif
-#ifdef CONFIG_EBU_BUSCON1
-	(*AR9_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
-#endif
-#ifdef CONFIG_EBU_BUSCON2
-	(*AR9_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
-#endif
-#ifdef CONFIG_EBU_BUSCON3
-	(*AR9_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
-#endif
-
-	return 0;
-}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_IFX_ETOP)
-
-	*AR9_PMU_PWDCR &= 0xFFFFEFDF;
-	*AR9_PMU_PWDCR &= ~AR9_PMU_DMA; /* enable DMA from PMU */
-
-	if (lq_eth_initialize(bis) < 0)
-		return -1;
-
-	*AR9_RCU_RST_REQ |= 1;
-	udelay(200000);
-	*AR9_RCU_RST_REQ &= (unsigned long)~1;
-	udelay(1000);
-
-#ifdef CONFIG_EXTRA_SWITCH
-	if (external_switch_init()<0)
-		return -1;
-#endif /* CONFIG_EXTRA_SWITCH */
-#endif /* CONFIG_IFX_ETOP */
-
-	return 0;
-}
-
-static void ar9_configure_sw_port(u8 port, u8 mode)
-{
-	if(port)
-	{
-		if (mode  == 1) //MII mode
-		{
-			*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
-			*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
-			*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0xf000)) | 0x2000;
-			*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x2000;
-		}
-		else if(mode == 2 || mode == 6) //Rev Mii mode
-		{
-			*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
-			*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
-			*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0xf000)) & ~0x2000;
-			*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xd000;
-		}
-	}
-	else //Port 0
-	{
-		if (mode  == 1) //MII mode
-		{
-			*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
-			*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
-			*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0x0303)) | 0x0100;
-			*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0100;
-		}
-		else if(mode ==2 || mode ==6) //Rev Mii mode
-		{
-			*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
-			*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
-			*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0x0303)) & ~0x0100;
-			*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0203;
-		}
-	}
-}
-
-/*
-Call this function to place either MAC port 0 or 1 into working mode.
-Parameters:
-port - select ports 0 or 1.
-state of interface : state
-0: RGMII
-1: MII
-2: Rev MII
-3: Reduce MII (input clock)
-4: RGMII 100mb
-5: Reserve
-6: Turbo Rev MII
-7: Reduce MII (output clock)
-*/
-void ar9_enable_sw_port(u8 port, u8 state)
-{
-	REG32(AR9_SW_GCTL0) |= 0x80000000;
-	if (port == 0)
-	{
-		REG32(AR9_SW_RGMII_CTL) &= 0xffcffc0e ;
-	//#if AR9_REFBOARD_TANTOS
-		REG32(0xbf20302c) &= 0xffff81ff;
-		REG32(0xbf20302c) |= 4<<9 ;
-	//#endif
-		REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<8;
-		if((state &0x3) == 0)
-		{
-			REG32(AR9_SW_RGMII_CTL) &= 0xfffffff3;
-			if(state == 4)
-				REG32(AR9_SW_RGMII_CTL) |= 0x4;
-			else
-				REG32(AR9_SW_RGMII_CTL) |= 0x8;
-		}
-		if(state == 6)
-			REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<20));
-		if(state == 7)
-			REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<21));
-	}
-//  *AR9_PPE32_ETOP_CFG = *AR9_PPE32_ETOP_CFG & 0xfffffffe;
-	else
-	{
-		REG32(AR9_SW_RGMII_CTL) &= 0xff303fff ;
-		REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<18;
-		if((state &0x3) == 0)
-		{
-			REG32(AR9_SW_RGMII_CTL) &= 0xffffcfff;
-			if(state == 4)
-				REG32(AR9_SW_RGMII_CTL) |= 0x1000;
-			else
-				REG32(AR9_SW_RGMII_CTL) |= 0x2000;
-		}
-		if(state == 6)
-			REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<22));
-		if(state == 7)
-			REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<23));
-	}
-}
-
-void pci_reset(void)
-{
-	int i,j;
-#define AR9_V1_PCI_RST_FIX 1
-#if AR9_V1_PCI_RST_FIX // 5th June 2008 Add GPIO19 to control EJTAG_TRST
-	*AR9_GPIO_P1_ALTSEL0 = *AR9_GPIO_P1_ALTSEL0 & ~0x8;
-	*AR9_GPIO_P1_ALTSEL1 = *AR9_GPIO_P1_ALTSEL1 & ~0x8;
-	*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR | 0x8;
-	*AR9_GPIO_P1_OD = *AR9_GPIO_P1_OD | 0x8;
-	*AR9_GPIO_P1_OUT = *AR9_GPIO_P1_OUT | 0x8;
-	*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 & ~0x4000;
-	*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~0x4000;
-	*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | 0x4000;
-	*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | 0x4000;
-	for(j=0;j<5;j++) {
-		*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT & ~0x4000;
-		for(i=0;i<0x10000;i++);
-		*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT | 0x4000;
-		for(i=0;i<0x10000;i++);
-	}
-	*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR &  ~0x4000;
-	*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR &  ~0x8;
-#endif
-}
-
-static u16 ar9_smi_reg_read(u16 reg)
-{
-	int i;
-	while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
-	REG32(AR9_SW_MDIO_CTL) = 0x8000| 0x2<<10 | ((u32) (reg&0x3ff)) ; /*0x10=MDIO_OP_READ*/
-	for(i=0;i<0x3fff;i++);
-	udelay(50);
-        while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
-	return((u16) (REG32(AR9_SW_MDIO_DATA)));
-}
-
-static u16 ar9_smi_reg_write(u16 reg, u16 data)
-{
-	int i;
-	while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
-	REG32(AR9_SW_MDIO_CTL) = 0x8000| (((u32) data)<<16) | 0x01<<10 | ((u32) (reg&0x3ff)) ; /*0x01=MDIO_OP_WRITE*/
-	for(i=0;i<0x3fff;i++);
-		udelay(50);
-	return 0;
-}
-
-static void ar9_sw_chip_init(u8 port, u8 mode)
-{
-	int i;
-	u16 chipid;
-
-	debug("\nsearching for switches ... ");
-
-	asm("sync");
-	pci_reset();
-
-	/* 25mhz clock out */
-	*AR9_CGU_IFCCR &= ~(3<<10);
-	*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 | (1<<3);
-	*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~(1<<3);
-	*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR  | (1<<3);
-	*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | (1<<3);
-	*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 & ~(1<<0);
-	*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(1<<0);
-	*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR  | (1<<0);
-	*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | (1<<0);
-
-	*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & 0xFFFBDFDF) ; 
-	*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & ~(AR9_PMU_DMA | AR9_PMU_SWITCH));
-	*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR | AR9_PMU_USB0 | AR9_PMU_USB0_P);
-
-	*AR9_GPIO_P2_OUT &= ~(1<<0);
-	asm("sync");
-
-	ar9_configure_sw_port(port, mode);
-	ar9_enable_sw_port(port, mode);
-	REG32(AR9_SW_P0_CTL) |= 0x400000; /* disable mdio polling for tantos */
-	asm("sync");
-
-	/*GPIO 55(P3.7) used as output, set high*/
-	*AR9_GPIO_P3_OD |=(1<<7);
-	*AR9_GPIO_P3_DIR |= (1<<7);
-	*AR9_GPIO_P3_ALTSEL0 &=~(1<<7);
-	*AR9_GPIO_P3_ALTSEL1 &=~(1<<7);
-	asm("sync");
-	udelay(10);
-
-	*AR9_GPIO_P3_OUT &= ~(1<<7);
-	for(i=0;i<1000;i++)
-		udelay(110);
-	*AR9_GPIO_P3_OUT |=(1<<7);
-	udelay(100);
-
-	if(port==0)
-		REG32(AR9_SW_P0_CTL) |= 0x40001;
-	else
-		REG32(AR9_SW_P1_CTL) |= 0x40001;
-
-	REG32(AR9_SW_P2_CTL) |= 0x40001;
-	REG32(AR9_SW_PMAC_HD_CTL) |= 0x40000; /* enable CRC */
-
-	*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xc00);
-	*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xc00);
-	*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR  | 0xc00;
-	*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xc00;
-
-	asm("sync");
-	chipid = (unsigned short)(ar9_smi_reg_read(0x101));
-	printf("\nswitch chip id=%08x\n",chipid);
-	if (chipid != ID_TANTOS) {
-		debug("whatever detected\n");
-		ar9_smi_reg_write(0x1,0x840f);
-		ar9_smi_reg_write(0x3,0x840f);
-		ar9_smi_reg_write(0x5,0x840f);
-		ar9_smi_reg_write(0x7,0x840f);
-		ar9_smi_reg_write(0x8,0x840f);
-		ar9_smi_reg_write(0x12,0x3602);
-#ifdef CLK_OUT2_25MHZ
-		ar9_smi_reg_write(0x33,0x4000);
-#endif
-	} else { // Tantos switch ship
-		debug("Tantos switch detected\n");
-		ar9_smi_reg_write(0xa1,0x0004); /*port 5 force link up*/
-		ar9_smi_reg_write(0xc1,0x0004); /*port 6 force link up*/
-		ar9_smi_reg_write(0xf5,0x0BBB); /*port 4 duplex mode, flow control enable,1000Mbit/s*/
-										/*port 5 duplex mode, flow control enable, 1000Mbit/s*/
-										/*port 6 duplex mode, flow control enable, 1000Mbit/s*/
-	}
-	asm("sync");
-
-	/*reset GPHY*/
-	mdelay(200);
-	*AR9_RCU_RST_REQ |= (AR9_RCU_RST_REQ_DMA | AR9_RCU_RST_REQ_PPE) ;
-	udelay(50);
-	*AR9_GPIO_P2_OUT |= (1<<0);
-}
-
-static void ar9_dma_init(void)
-{
-	/* select port */
-	*AR9_DMA_PS = 0;
-
-	/* 
-	TXWGT 14:12 rw Port Weight for Transmit Direction (the default value “001”)
-
-	TXENDI 11:10 rw Endianness for Transmit Direction
-	Determine a byte swap between memory interface (left hand side) and
-	peripheral interface (right hand side).
-	00B B0_B1_B2_B3 No byte switching
-	01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
-	10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
-	
-	RXENDI 9:8 rw Endianness for Receive Direction
-	Determine a byte swap between peripheral (left hand side) and memory
-	interface (right hand side).
-	00B B0_B1_B2_B3 No byte switching
-	01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
-	10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
-	11B B3_B2_B1_B0 B0B1B2B3 => B3B2B1B0 
-
-	TXBL 5:4 rw Burst Length for Transmit Direction
-	Selects burst length for TX direction.
-	Others are reserved and will result in 2_WORDS burst length.
-	01B 2_WORDS 2 words
-	10B 4_WORDS 4 words
-	11B 8_WORDS 8 words
-
-	RXBL 3:2 rw Burst Length for Receive Direction
-	Selects burst length for RX direction.
-	Others are reserved and will result in 2_WORDS burst length.
-	01B 2_WORDS 2 words
-	10B 4_WORDS 4 words
-	11B 8_WORDS 8 words	
-	*/
-	*AR9_DMA_PCTRL = 0x1f28;
-}
-
-#ifdef CONFIG_EXTRA_SWITCH
-static int external_switch_init(void)
-{
-	ar9_sw_chip_init(0, RGMII_MODE);
-
-	ar9_dma_init();
-
-	return 0;
-}
-#endif /* CONFIG_EXTRA_SWITCH */
-
-#if defined(CONFIG_CMD_HTTPD)
-int do_http_upgrade(const unsigned char *data, const ulong size)
-{
-	char buf[128];
-
-	if(getenv ("ram_addr") == NULL)
-		return -1;
-	if(getenv ("kernel_addr") == NULL)
-		return -1;
-	/* check the image */
-	if(run_command("imi ${ram_addr}", 0) < 0) {
-		return -1;
-	}
-	/* write the image to the flash */
-	puts("http ugrade ...\n");
-	sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
-	return run_command(buf, 0);
-}
-
-int do_http_progress(const int state)
-{
-	/* toggle LED's here */
-	switch(state) {
-		case HTTP_PROGRESS_START:
-		puts("http start\n");
-		break;
-		case HTTP_PROGRESS_TIMEOUT:
-		puts(".");
-		break;
-		case HTTP_PROGRESS_UPLOAD_READY:
-		puts("http upload ready\n");
-		break;
-		case HTTP_PROGRESS_UGRADE_READY:
-		puts("http ugrade ready\n");
-		break;
-		case HTTP_PROGRESS_UGRADE_FAILED:
-		puts("http ugrade failed\n");
-		break;
-	}
-	return 0;
-}
-
-unsigned long do_http_tmp_address(void)
-{
-	char *s = getenv ("ram_addr");
-	if (s) {
-		ulong tmp = simple_strtoul (s, NULL, 16);
-		return tmp;
-	}
-	return 0 /*0x80a00000*/;
-}
-
-#endif
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h
deleted file mode 100644
index 766f1e00da..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x306
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x139  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0x2200
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1800
-#define MC_DC22_VALUE	0x1818
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x59   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x514
-#define MC_DC29_VALUE	0x2d93
-#define MC_DC30_VALUE	0x8235
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x600
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr166_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr166_settings.h
deleted file mode 100644
index 6d940ac6cb..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr166_settings.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x306
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x13f  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0x2200
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1600
-#define MC_DC22_VALUE	0x1616
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x5d   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x514
-#define MC_DC29_VALUE	0x2d93
-#define MC_DC30_VALUE	0x8235
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x600
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
deleted file mode 100644
index 45daa188d3..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x306
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x80B
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xD02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x144  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xF
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1200
-#define MC_DC22_VALUE	0x1212
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x66   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x5FB
-#define MC_DC29_VALUE	0x35DF
-#define MC_DC30_VALUE	0x99E9
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x600
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h
deleted file mode 100644
index 7f87d43f76..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x306
-#define MC_DC7_VALUE	0x403
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x90c
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xf02
-#define MC_DC12_VALUE	0x2c8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x12f  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xc800
-#define MC_DC17_VALUE	0xf
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1500
-#define MC_DC22_VALUE	0x1515
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x57   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x6b8
-#define MC_DC29_VALUE	0x3c84
-#define MC_DC30_VALUE	0xace5
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x600
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h
deleted file mode 100644
index 2e49db99d1..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x306
-#define MC_DC7_VALUE	0x403
-#define MC_DC8_VALUE	0x103
-#define MC_DC9_VALUE	0xb0e
-#define MC_DC10_VALUE	0x204
-#define MC_DC11_VALUE	0x1102
-#define MC_DC12_VALUE	0x2c8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x155  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xc800
-#define MC_DC17_VALUE	0x13
-#define MC_DC18_VALUE	0x401
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0xc00
-#define MC_DC22_VALUE	0xc0c
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x74   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x798
-#define MC_DC29_VALUE	0x445d
-#define MC_DC30_VALUE	0xc351
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x600
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/config.mk b/package/uboot-lantiq/files/board/infineon/easy50812/config.mk
deleted file mode 100644
index b110f6f329..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/config.mk
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Danube board with MIPS 24Kc CPU core
-#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifdef CONFIG_BOOTSTRAP
-TEXT_BASE = 0x80001000
-CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
-CONFIG_SYS_RAMBOOT = y
-else
-
-ifndef TEXT_BASE
-$(info redefine TEXT_BASE = 0xB0000000 )
-TEXT_BASE = 0xB0000000
-endif
-
-endif
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/easy50812_bootstrap.c b/package/uboot-lantiq/files/board/infineon/easy50812/easy50812_bootstrap.c
deleted file mode 100644
index 11bf6d0b71..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/easy50812_bootstrap.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2007
- * Vlad Lungu vlad.lungu@windriver.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-
-phys_size_t bootstrap_initdram(int board_type)
-{
-	/* Sdram is setup by assembler code */
-	/* If memory could be changed, we should return the true value here */
-	return CONFIG_SYS_MAX_RAM;
-}
-
-int bootstrap_checkboard(void)
-{
-	return 0;
-}
-
-int bootstrap_misc_init_r(void)
-{
-	set_io_port_base(0);
-	return 0;
-}
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_bootstrap_init.S b/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_bootstrap_init.S
deleted file mode 100644
index ec82e231c2..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_bootstrap_init.S
+++ /dev/null
@@ -1,597 +0,0 @@
-/*
- *  Memory sub-system initialization code for Danube board.
- *  Andre Messerschmidt
- *  Copyright (c) 2005	Infineon Technologies AG
- *
- *  Based on Inca-IP code
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
-      peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_RAM)
-
-#if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M)
-#	include "ar9_ddr111_settings.h"  
-#elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M) 
-#	include "ar9_ddr166_settings.h"
-#elif defined(CONFIG_CPU_442M_RAM_147M)
-#	include "ar9_ddr166_settings.h"
-#elif defined(CONFIG_CPU_393M_RAM_196M)
-#	ifdef CONFIG_ETRON_RAM
-#		include "etron_ddr196_settings.h"
-#	else
-#		include "ar9_ddr196_settings.h"
-#	endif
-#elif defined(CONFIG_CPU_442M_RAM_221M)
-#	include "ar9_ddr221_settings.h"
-#elif defined(CONFIG_CPU_500M_RAM_250M)
-#	include "ar9_ddr250_settings.h"
-#else
-#	warning "missing definition for ddr_settings.h, use default!"
-#	include "ar9_ddr_settings.h"
-#endif
-#endif /* CONFIG_USE_DDR_RAM */
-
-#define EBU_MODUL_BASE		0xBE105300
-#define EBU_CLC(value)		0x0000(value)
-#define EBU_CON(value)		0x0010(value)
-#define EBU_ADDSEL0(value)	0x0020(value)
-#define EBU_ADDSEL1(value)	0x0024(value)
-#define EBU_ADDSEL2(value)	0x0028(value)
-#define EBU_ADDSEL3(value)	0x002C(value)
-#define EBU_BUSCON0(value)	0x0060(value)
-#define EBU_BUSCON1(value)	0x0064(value)
-#define EBU_BUSCON2(value)	0x0068(value)
-#define EBU_BUSCON3(value)	0x006C(value)
-
-#define MC_MODUL_BASE		0xBF800000
-#define MC_ERRCAUSE(value)	0x0010(value)
-#define MC_ERRADDR(value)	0x0020(value)
-#define MC_CON(value)		0x0060(value)
-
-#define MC_SRAM_ENABLE		0x00000004
-#define MC_SDRAM_ENABLE		0x00000002
-#define MC_DDRRAM_ENABLE	0x00000001
-
-#define MC_SDR_MODUL_BASE	0xBF800200
-#define MC_IOGP(value)		0x0000(value)
-#define MC_CTRLENA(value)	0x0010(value)
-#define MC_MRSCODE(value)	0x0020(value)
-#define MC_CFGDW(value)		0x0030(value)
-#define MC_CFGPB0(value)	0x0040(value)
-#define MC_LATENCY(value)	0x0080(value)
-#define MC_TREFRESH(value)	0x0090(value)
-#define MC_SELFRFSH(value)	0x00A0(value)
-
-#define MC_DDR_MODUL_BASE	0xBF801000
-#define MC_DC00(value)		0x0000(value)
-#define MC_DC01(value)		0x0010(value)
-#define MC_DC02(value)		0x0020(value)
-#define MC_DC03(value)		0x0030(value)
-#define MC_DC04(value)		0x0040(value)
-#define MC_DC05(value)		0x0050(value)
-#define MC_DC06(value)		0x0060(value)
-#define MC_DC07(value)		0x0070(value)
-#define MC_DC08(value)		0x0080(value)
-#define MC_DC09(value)		0x0090(value)
-#define MC_DC10(value)		0x00A0(value)
-#define MC_DC11(value)		0x00B0(value)
-#define MC_DC12(value)		0x00C0(value)
-#define MC_DC13(value)		0x00D0(value)
-#define MC_DC14(value)		0x00E0(value)
-#define MC_DC15(value)		0x00F0(value)
-#define MC_DC16(value)		0x0100(value)
-#define MC_DC17(value)		0x0110(value)
-#define MC_DC18(value)		0x0120(value)
-#define MC_DC19(value)		0x0130(value)
-#define MC_DC20(value)		0x0140(value)
-#define MC_DC21(value)		0x0150(value)
-#define MC_DC22(value)		0x0160(value)
-#define MC_DC23(value)		0x0170(value)
-#define MC_DC24(value)		0x0180(value)
-#define MC_DC25(value)		0x0190(value)
-#define MC_DC26(value)		0x01A0(value)
-#define MC_DC27(value)		0x01B0(value)
-#define MC_DC28(value)		0x01C0(value)
-#define MC_DC29(value)		0x01D0(value)
-#define MC_DC30(value)		0x01E0(value)
-#define MC_DC31(value)		0x01F0(value)
-#define MC_DC32(value)		0x0200(value)
-#define MC_DC33(value)		0x0210(value)
-#define MC_DC34(value)		0x0220(value)
-#define MC_DC35(value)		0x0230(value)
-#define MC_DC36(value)		0x0240(value)
-#define MC_DC37(value)		0x0250(value)
-#define MC_DC38(value)		0x0260(value)
-#define MC_DC39(value)		0x0270(value)
-#define MC_DC40(value)		0x0280(value)
-#define MC_DC41(value)		0x0290(value)
-#define MC_DC42(value)		0x02A0(value)
-#define MC_DC43(value)		0x02B0(value)
-#define MC_DC44(value)		0x02C0(value)
-#define MC_DC45(value)		0x02D0(value)
-#define MC_DC46(value)		0x02E0(value)
-
-#define RCU_OFFSET  0xBF203000
-#define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
-#define RCU_STS          (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET  0xBF103000
-#define  PLL0_CFG     (CGU_OFFSET + 0x0004)
-#define  PLL1_CFG     (CGU_OFFSET + 0x0008)
-#define  PLL2_CFG     (CGU_OFFSET + 0x000C)
-#define  CGU_SYS      (CGU_OFFSET + 0x0010)
-#define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
-#define  IF_CLK       (CGU_OFFSET + 0x0018)
-#define  CGU_SMD      (CGU_OFFSET + 0x0020)
-#define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
-#define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
-#define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
-#define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
-#define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
-
-//05252006
-#define  pll0_35MHz_CONFIG 0x9D861059
-#define  pll1_35MHz_CONFIG 0x1A260CD9
-#define  pll2_35MHz_CONFIG 0x8000f1e5
-#define  pll0_36MHz_CONFIG 0x1000125D
-#define  pll1_36MHz_CONFIG 0x1B1E0C99
-#define  pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET  0xBE105400
-#define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE  0xB7000000
-#define CS_CFM		(PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
-	.set	noreorder
-
-
-/*
- * void ebu_init(void)
- */
-	.globl	ebu_init
-	.ent	ebu_init
-ebu_init:
-
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
-	defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
-	defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
-	defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
-	li	t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
-	li	t2, CONFIG_EBU_ADDSEL0
-	sw	t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
-	li	t2, CONFIG_EBU_ADDSEL1
-	sw	t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
-	li	t2, CONFIG_EBU_ADDSEL2
-	sw	t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
-	li	t2, CONFIG_EBU_ADDSEL3
-	sw	t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
-	li	t2, CONFIG_EBU_BUSCON0
-	sw	t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
-	li	t2, CONFIG_EBU_BUSCON1
-	sw	t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
-	li	t2, CONFIG_EBU_BUSCON2
-	sw	t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
-	li	t2, CONFIG_EBU_BUSCON3
-	sw	t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
-	j	ra
-	nop
-
-	.end	ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
-	.globl	cgu_init
-	.ent	cgu_init
-cgu_init:
-	li  t2, CGU_SYS
-	lw  t2,0(t2)
-	beq t2,a0,freq_up2date
-	nop
-
-	li  t2, RCU_STS
-	lw  t2, 0(t2)
-	and t2,0x00020000
-	beq t2,0x00020000,boot_36MHZ
-	nop
-//05252006
-	li  t1, PLL0_CFG
-	li  t2, pll0_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-	b   wait_reset
-	nop
-boot_36MHZ:
-	li  t1, PLL0_CFG
-	li  t2, pll0_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-//05252006
-
-wait_reset:
-	b   wait_reset
-	nop
-freq_up2date:
-	j ra
-	nop
-
-	.end	cgu_init
-
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	sdram_init
-	.ent	sdram_init
-sdram_init:
-
-	/* SDRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable SDRAM module in memory controller */
-	li	t3, MC_SDRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_SDR_MODUL_BASE
-
-	/* disable the controller */
-	li	t2, 0
-	sw	t2, MC_CTRLENA(t1)
-
-	li	t2, 0x822
-	sw	t2, MC_IOGP(t1)
-
-	li	t2, 0x2
-	sw	t2, MC_CFGDW(t1)
-
-	/* Set CAS Latency */
-	li	t2, 0x00000020
-	sw	t2, MC_MRSCODE(t1)
-
-	/* Set CS0 to SDRAM parameters */
-	li	t2, 0x000014d8
-	sw	t2, MC_CFGPB0(t1)
-
-	/* Set SDRAM latency parameters */
-	li  	t2, 0x00036325;   /* BC PC100 */
-	sw	t2, MC_LATENCY(t1)
-
-	/* Set SDRAM refresh rate */
-	li	t2, 0x00000C30
-	sw	t2, MC_TREFRESH(t1)
-
-	/* Clear Power-down registers */
-	sw	zero, MC_SELFRFSH(t1)
-
-	/* Finally enable the controller */
-	li	t2, 1
-	sw	t2, MC_CTRLENA(t1)
-
-	j	ra
-	nop
-
-	.end	sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	ddrram_init
-	.ent	ddrram_init
-ddrram_init:
-
-	/* DDR-DRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable DDR module in memory controller */
-	li	t3, MC_DDRRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_DDR_MODUL_BASE
-
-	/* Write configuration to DDR controller registers */
-	li	t2, MC_DC0_VALUE
-	sw	t2, MC_DC00(t1)
-
-	li	t2, MC_DC1_VALUE
-	sw	t2, MC_DC01(t1)
-
-	li	t2, MC_DC2_VALUE
-	sw	t2, MC_DC02(t1)
-
-	li	t2, MC_DC3_VALUE
-	sw	t2, MC_DC03(t1)
-
-	li	t2, MC_DC4_VALUE
-	sw	t2, MC_DC04(t1)
-
-	li	t2, MC_DC5_VALUE
-	sw	t2, MC_DC05(t1)
-
-	li	t2, MC_DC6_VALUE
-	sw	t2, MC_DC06(t1)
-
-	li	t2, MC_DC7_VALUE
-	sw	t2, MC_DC07(t1)
-
-	li	t2, MC_DC8_VALUE
-	sw	t2, MC_DC08(t1)
-
-	li	t2, MC_DC9_VALUE
-	sw	t2, MC_DC09(t1)
-
-	li	t2, MC_DC10_VALUE
-	sw	t2, MC_DC10(t1)
-
-	li	t2, MC_DC11_VALUE
-	sw	t2, MC_DC11(t1)
-
-	li	t2, MC_DC12_VALUE
-	sw	t2, MC_DC12(t1)
-
-	li	t2, MC_DC13_VALUE
-	sw	t2, MC_DC13(t1)
-
-	li	t2, MC_DC14_VALUE
-	sw	t2, MC_DC14(t1)
-
-	li	t2, MC_DC15_VALUE
-	sw	t2, MC_DC15(t1)
-
-	li	t2, MC_DC16_VALUE
-	sw	t2, MC_DC16(t1)
-
-	li	t2, MC_DC17_VALUE
-	sw	t2, MC_DC17(t1)
-
-	li	t2, MC_DC18_VALUE
-	sw	t2, MC_DC18(t1)
-
-	li	t2, MC_DC19_VALUE
-	sw	t2, MC_DC19(t1)
-
-	li	t2, MC_DC20_VALUE
-	sw	t2, MC_DC20(t1)
-
-	li	t2, MC_DC21_VALUE
-	sw	t2, MC_DC21(t1)
-
-	li	t2, MC_DC22_VALUE
-	sw	t2, MC_DC22(t1)
-
-	li	t2, MC_DC23_VALUE
-	sw	t2, MC_DC23(t1)
-
-	li	t2, MC_DC24_VALUE
-	sw	t2, MC_DC24(t1)
-
-	li	t2, MC_DC25_VALUE
-	sw	t2, MC_DC25(t1)
-
-	li	t2, MC_DC26_VALUE
-	sw	t2, MC_DC26(t1)
-
-	li	t2, MC_DC27_VALUE
-	sw	t2, MC_DC27(t1)
-
-	li	t2, MC_DC28_VALUE
-	sw	t2, MC_DC28(t1)
-
-	li	t2, MC_DC29_VALUE
-	sw	t2, MC_DC29(t1)
-
-	li	t2, MC_DC30_VALUE
-	sw	t2, MC_DC30(t1)
-
-	li	t2, MC_DC31_VALUE
-	sw	t2, MC_DC31(t1)
-
-	li	t2, MC_DC32_VALUE
-	sw	t2, MC_DC32(t1)
-
-	li	t2, MC_DC33_VALUE
-	sw	t2, MC_DC33(t1)
-
-	li	t2, MC_DC34_VALUE
-	sw	t2, MC_DC34(t1)
-
-	li	t2, MC_DC35_VALUE
-	sw	t2, MC_DC35(t1)
-
-	li	t2, MC_DC36_VALUE
-	sw	t2, MC_DC36(t1)
-
-	li	t2, MC_DC37_VALUE
-	sw	t2, MC_DC37(t1)
-
-	li	t2, MC_DC38_VALUE
-	sw	t2, MC_DC38(t1)
-
-	li	t2, MC_DC39_VALUE
-	sw	t2, MC_DC39(t1)
-
-	li	t2, MC_DC40_VALUE
-	sw	t2, MC_DC40(t1)
-
-	li	t2, MC_DC41_VALUE
-	sw	t2, MC_DC41(t1)
-
-	li	t2, MC_DC42_VALUE
-	sw	t2, MC_DC42(t1)
-
-	li	t2, MC_DC43_VALUE
-	sw	t2, MC_DC43(t1)
-
-	li	t2, MC_DC44_VALUE
-	sw	t2, MC_DC44(t1)
-
-	li	t2, MC_DC45_VALUE
-	sw	t2, MC_DC45(t1)
-
-	li	t2, MC_DC46_VALUE
-	sw	t2, MC_DC46(t1)
-
-	li	t2, 0x00000100
-	sw	t2, MC_DC03(t1)
-
-	j	ra
-	nop
-
-	.end	ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
-	.globl	lowlevel_init
-	.ent	lowlevel_init
-lowlevel_init:
-	/* EBU, CGU and SDRAM/DDR-RAM Initialization.
-	 */
-	move	t0, ra
-	/* We rely on the fact that non of the following ..._init() functions
-	 * modify t0
-	 */
-#if defined(DDR166)
-	/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
-	li  a0,0xe8
-#elif defined(DDR133)
-	/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
-	li  a0,0xe9
-#else /* defined(DDR111) */
-	/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
-	li  a0,0xea
-#endif
-	bal	cgu_init
-	nop
-
-	bal	ebu_init
-	nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
-	li  t1, PCI_CR_PCI	//mw bf103034 80000000
-	li  t2, 0x80000000
-	sw	t2,0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x103
-	sw  t2,0(t1)
-
-	li  t1, CS_CFM			//mw b700006c 0
-	li  t2, 0x00
-	sw  t2, 0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x1000103
-	sw  t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
-#ifdef CONFIG_USE_DDR_RAM
-	bal	ddrram_init
-	nop
-#else
-	bal	sdram_init
-	nop
-#endif
-	move	ra, t0
-	j	ra
-	nop
-
-	.end	lowlevel_init
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_init.S b/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_init.S
deleted file mode 100644
index 58f7a16eae..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_init.S
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- *  Memory sub-system initialization code for AR9 board.
- *
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *  Copyright (c) 2005	Andre Messerschmidt  Infineon
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
-      peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_RAM)
-
-#if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M)
-#	include "ar9_ddr111_settings.h"  
-#elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M) 
-#	include "ar9_ddr166_settings.h"
-#elif defined(CONFIG_CPU_442M_RAM_147M)
-#	include "ar9_ddr166_settings.h"
-#elif defined(CONFIG_CPU_393M_RAM_196M)
-#	ifdef CONFIG_ETRON_RAM
-#		include "etron_ddr196_settings.h"
-#	else
-#		include "ar9_ddr196_settings.h"
-#	endif
-#elif defined(CONFIG_CPU_442M_RAM_221M)
-#	include "ar9_ddr221_settings.h"
-#elif defined(CONFIG_CPU_500M_RAM_250M)
-#	include "ar9_ddr250_settings.h"
-#else
-#	warning "missing definition for ddr_settings.h, use default!"
-#	include "ar9_ddr_settings.h"
-#endif
-#endif /* CONFIG_USE_DDR_RAM */
-
-#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
-#error "missing include of ddr_settings.h"
-#endif
-
-#define EBU_MODUL_BASE		0xBE105300
-#define EBU_CLC(value)		0x0000(value)
-#define EBU_CON(value)		0x0010(value)
-#define EBU_ADDSEL0(value)	0x0020(value)
-#define EBU_ADDSEL1(value)	0x0024(value)
-#define EBU_ADDSEL2(value)	0x0028(value)
-#define EBU_ADDSEL3(value)	0x002C(value)
-#define EBU_BUSCON0(value)	0x0060(value)
-#define EBU_BUSCON1(value)	0x0064(value)
-#define EBU_BUSCON2(value)	0x0068(value)
-#define EBU_BUSCON3(value)	0x006C(value)
-
-#define MC_MODUL_BASE		0xBF800000
-#define MC_ERRCAUSE(value)	0x0010(value)
-#define MC_ERRADDR(value)	0x0020(value)
-#define MC_CON(value)		0x0060(value)
-
-#define MC_SRAM_ENABLE		0x00000004
-#define MC_SDRAM_ENABLE		0x00000002
-#define MC_DDRRAM_ENABLE	0x00000001
-
-#define MC_SDR_MODUL_BASE	0xBF800200
-#define MC_IOGP(value)		0x0000(value)
-#define MC_CTRLENA(value)	0x0010(value)
-#define MC_MRSCODE(value)	0x0020(value)
-#define MC_CFGDW(value)		0x0030(value)
-#define MC_CFGPB0(value)	0x0040(value)
-#define MC_LATENCY(value)	0x0080(value)
-#define MC_TREFRESH(value)	0x0090(value)
-#define MC_SELFRFSH(value)	0x00A0(value)
-
-#define MC_DDR_MODUL_BASE	0xBF801000
-#define MC_DC00(value)		0x0000(value)
-#define MC_DC01(value)		0x0010(value)
-#define MC_DC02(value)		0x0020(value)
-#define MC_DC03(value)		0x0030(value)
-#define MC_DC04(value)		0x0040(value)
-#define MC_DC05(value)		0x0050(value)
-#define MC_DC06(value)		0x0060(value)
-#define MC_DC07(value)		0x0070(value)
-#define MC_DC08(value)		0x0080(value)
-#define MC_DC09(value)		0x0090(value)
-#define MC_DC10(value)		0x00A0(value)
-#define MC_DC11(value)		0x00B0(value)
-#define MC_DC12(value)		0x00C0(value)
-#define MC_DC13(value)		0x00D0(value)
-#define MC_DC14(value)		0x00E0(value)
-#define MC_DC15(value)		0x00F0(value)
-#define MC_DC16(value)		0x0100(value)
-#define MC_DC17(value)		0x0110(value)
-#define MC_DC18(value)		0x0120(value)
-#define MC_DC19(value)		0x0130(value)
-#define MC_DC20(value)		0x0140(value)
-#define MC_DC21(value)		0x0150(value)
-#define MC_DC22(value)		0x0160(value)
-#define MC_DC23(value)		0x0170(value)
-#define MC_DC24(value)		0x0180(value)
-#define MC_DC25(value)		0x0190(value)
-#define MC_DC26(value)		0x01A0(value)
-#define MC_DC27(value)		0x01B0(value)
-#define MC_DC28(value)		0x01C0(value)
-#define MC_DC29(value)		0x01D0(value)
-#define MC_DC30(value)		0x01E0(value)
-#define MC_DC31(value)		0x01F0(value)
-#define MC_DC32(value)		0x0200(value)
-#define MC_DC33(value)		0x0210(value)
-#define MC_DC34(value)		0x0220(value)
-#define MC_DC35(value)		0x0230(value)
-#define MC_DC36(value)		0x0240(value)
-#define MC_DC37(value)		0x0250(value)
-#define MC_DC38(value)		0x0260(value)
-#define MC_DC39(value)		0x0270(value)
-#define MC_DC40(value)		0x0280(value)
-#define MC_DC41(value)		0x0290(value)
-#define MC_DC42(value)		0x02A0(value)
-#define MC_DC43(value)		0x02B0(value)
-#define MC_DC44(value)		0x02C0(value)
-#define MC_DC45(value)		0x02D0(value)
-#define MC_DC46(value)		0x02E0(value)
-
-#define RCU_OFFSET  0xBF203000
-#define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
-#define RCU_STS          (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET  0xBF103000
-#define  PLL0_CFG     (CGU_OFFSET + 0x0004)
-#define  PLL1_CFG     (CGU_OFFSET + 0x0008)
-#define  PLL2_CFG     (CGU_OFFSET + 0x000C)
-#define  CGU_SYS      (CGU_OFFSET + 0x0010)
-#define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
-#define  IF_CLK       (CGU_OFFSET + 0x0018)
-#define  CGU_SMD      (CGU_OFFSET + 0x0020)
-#define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
-#define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
-#define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
-#define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
-#define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
-
-#define  pll1_36MHz_CONFIG 0x9800f25f
-
-	.set	noreorder
-
-
-/*
- * void ebu_init(void)
- */
-	.globl	ebu_init
-	.ent	ebu_init
-ebu_init:
-
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
-	defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
-	defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
-	defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
-	li	t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
-	li	t2, CONFIG_EBU_ADDSEL0
-	sw	t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
-	li	t2, CONFIG_EBU_ADDSEL1
-	sw	t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
-	li	t2, CONFIG_EBU_ADDSEL2
-	sw	t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
-	li	t2, CONFIG_EBU_ADDSEL3
-	sw	t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
-	li	t2, CONFIG_EBU_BUSCON0
-	sw	t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
-	li	t2, CONFIG_EBU_BUSCON1
-	sw	t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
-	li	t2, CONFIG_EBU_BUSCON2
-	sw	t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
-	li	t2, CONFIG_EBU_BUSCON3
-	sw	t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
-	j	ra
-	nop
-
-	.end	ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
-	.globl	cgu_init
-	.ent	cgu_init
-cgu_init:
-        li  t2, CGU_SYS
-        lw  t2,0(t2)
-        beq t2,a0,freq_up2date
-        nop
-        li  t1, CGU_SYS
-        sw	a0,0(t1)
-
-#if defined(CONFIG_CPU_333M_RAM_166M) && defined(CONFIG_USE_PLL1)
-        li  t1, PLL1_CFG
-        li  a1, pll1_36MHz_CONFIG
-        sw  a1, 0(t1)
-#endif
-
-#if defined(CONFIG_CLASS_II_DDR_PAD) 
-        li  t1, CGU_SMD
-        li  a1, 0x200000
-        sw  a1, 0(t1)      // Turn on DDR PAD Class II to INC drive.
-#endif
-
-        li  t1, RCU_RST_REQ
-        li  t2, 0x40000008
-        sw	t2,0(t1)
-        b   wait_reset
-        nop
-
-wait_reset:
-        b   wait_reset
-        nop
-
-freq_up2date:
-        j ra
-        nop
-	.end	cgu_init
-
-
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	sdram_init
-	.ent	sdram_init
-sdram_init:
-
-	/* SDRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable SDRAM module in memory controller */
-	li	t3, MC_SDRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_SDR_MODUL_BASE
-
-	/* disable the controller */
-	li	t2, 0
-	sw	t2, MC_CTRLENA(t1)
-
-	li	t2, 0x822
-	sw	t2, MC_IOGP(t1)
-
-	li	t2, 0x2
-	sw	t2, MC_CFGDW(t1)
-
-	/* Set CAS Latency */
-	li	t2, 0x00000020
-	sw	t2, MC_MRSCODE(t1)
-
-	/* Set CS0 to SDRAM parameters */
-	li	t2, 0x000014d8
-	sw	t2, MC_CFGPB0(t1)
-
-	/* Set SDRAM latency parameters */
-	li  	t2, 0x00036325;   /* BC PC100 */
-	sw	t2, MC_LATENCY(t1)
-
-	/* Set SDRAM refresh rate */
-	li	t2, 0x00000C30
-	sw	t2, MC_TREFRESH(t1)
-
-	/* Clear Power-down registers */
-	sw	zero, MC_SELFRFSH(t1)
-
-	/* Finally enable the controller */
-	li	t2, 1
-	sw	t2, MC_CTRLENA(t1)
-
-	j	ra
-	nop
-
-	.end	sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	ddrram_init
-	.ent	ddrram_init
-ddrram_init:
-
-	/* DDR-DRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable DDR module in memory controller */
-	li	t3, MC_DDRRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_DDR_MODUL_BASE
-
-	/* Write configuration to DDR controller registers */
-	li	t2, MC_DC0_VALUE
-	sw	t2, MC_DC00(t1)
-
-	li	t2, MC_DC1_VALUE
-	sw	t2, MC_DC01(t1)
-
-	li	t2, MC_DC2_VALUE
-	sw	t2, MC_DC02(t1)
-
-	li	t2, MC_DC3_VALUE
-	sw	t2, MC_DC03(t1)
-
-	li	t2, MC_DC4_VALUE
-	sw	t2, MC_DC04(t1)
-
-	li	t2, MC_DC5_VALUE
-	sw	t2, MC_DC05(t1)
-
-	li	t2, MC_DC6_VALUE
-	sw	t2, MC_DC06(t1)
-
-	li	t2, MC_DC7_VALUE
-	sw	t2, MC_DC07(t1)
-
-	li	t2, MC_DC8_VALUE
-	sw	t2, MC_DC08(t1)
-
-	li	t2, MC_DC9_VALUE
-	sw	t2, MC_DC09(t1)
-
-	li	t2, MC_DC10_VALUE
-	sw	t2, MC_DC10(t1)
-
-	li	t2, MC_DC11_VALUE
-	sw	t2, MC_DC11(t1)
-
-	li	t2, MC_DC12_VALUE
-	sw	t2, MC_DC12(t1)
-
-	li	t2, MC_DC13_VALUE
-	sw	t2, MC_DC13(t1)
-
-	li	t2, MC_DC14_VALUE
-	sw	t2, MC_DC14(t1)
-
-	li	t2, MC_DC15_VALUE
-	sw	t2, MC_DC15(t1)
-
-	li	t2, MC_DC16_VALUE
-	sw	t2, MC_DC16(t1)
-
-	li	t2, MC_DC17_VALUE
-	sw	t2, MC_DC17(t1)
-
-	li	t2, MC_DC18_VALUE
-	sw	t2, MC_DC18(t1)
-
-	li	t2, MC_DC19_VALUE
-	sw	t2, MC_DC19(t1)
-
-	li	t2, MC_DC20_VALUE
-	sw	t2, MC_DC20(t1)
-
-	li	t2, MC_DC21_VALUE
-	sw	t2, MC_DC21(t1)
-
-	li	t2, MC_DC22_VALUE
-	sw	t2, MC_DC22(t1)
-
-	li	t2, MC_DC23_VALUE
-	sw	t2, MC_DC23(t1)
-
-	li	t2, MC_DC24_VALUE
-	sw	t2, MC_DC24(t1)
-
-	li	t2, MC_DC25_VALUE
-	sw	t2, MC_DC25(t1)
-
-	li	t2, MC_DC26_VALUE
-	sw	t2, MC_DC26(t1)
-
-	li	t2, MC_DC27_VALUE
-	sw	t2, MC_DC27(t1)
-
-	li	t2, MC_DC28_VALUE
-	sw	t2, MC_DC28(t1)
-
-	li	t2, MC_DC29_VALUE
-	sw	t2, MC_DC29(t1)
-
-	li	t2, MC_DC30_VALUE
-	sw	t2, MC_DC30(t1)
-
-	li	t2, MC_DC31_VALUE
-	sw	t2, MC_DC31(t1)
-
-	li	t2, MC_DC32_VALUE
-	sw	t2, MC_DC32(t1)
-
-	li	t2, MC_DC33_VALUE
-	sw	t2, MC_DC33(t1)
-
-	li	t2, MC_DC34_VALUE
-	sw	t2, MC_DC34(t1)
-
-	li	t2, MC_DC35_VALUE
-	sw	t2, MC_DC35(t1)
-
-	li	t2, MC_DC36_VALUE
-	sw	t2, MC_DC36(t1)
-
-	li	t2, MC_DC37_VALUE
-	sw	t2, MC_DC37(t1)
-
-	li	t2, MC_DC38_VALUE
-	sw	t2, MC_DC38(t1)
-
-	li	t2, MC_DC39_VALUE
-	sw	t2, MC_DC39(t1)
-
-	li	t2, MC_DC40_VALUE
-	sw	t2, MC_DC40(t1)
-
-	li	t2, MC_DC41_VALUE
-	sw	t2, MC_DC41(t1)
-
-	li	t2, MC_DC42_VALUE
-	sw	t2, MC_DC42(t1)
-
-	li	t2, MC_DC43_VALUE
-	sw	t2, MC_DC43(t1)
-
-	li	t2, MC_DC44_VALUE
-	sw	t2, MC_DC44(t1)
-
-	li	t2, MC_DC45_VALUE
-	sw	t2, MC_DC45(t1)
-
-	li	t2, MC_DC46_VALUE
-	sw	t2, MC_DC46(t1)
-
-	li	t2, 0x00000100
-	sw	t2, MC_DC03(t1)
-
-	j	ra
-	nop
-
-	.end	ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
-	.globl	lowlevel_init
-	.ent	lowlevel_init
-lowlevel_init:
-	/* EBU, CGU and SDRAM/DDR-RAM Initialization.
-	 */
-	move	t0, ra
-	/* We rely on the fact that non of the following ..._init() functions
-	 * modify t0
-	 */
-#if defined(CONFIG_SYS_EBU_BOOT)
-/*
-	using PPL1 value
-*/
-	li  a0,0x90
-	bal	cgu_init
-	nop
-#endif /* CONFIG_SYS_EBU_BOOT */
-
-	bal	ebu_init
-	nop
-
-#ifdef CONFIG_SYS_EBU_BOOT
-#ifndef CONFIG_SYS_RAMBOOT
-#ifdef CONFIG_USE_DDR_RAM
-	bal	ddrram_init
-	nop
-#else
-	bal	sdram_init
-	nop
-#endif
-#endif /* CONFIG_SYS_RAMBOOT */
-#endif /* CONFIG_SYS_EBU_BOOT */
-
-	move	ra, t0
-	j	ra
-	nop
-
-	.end	lowlevel_init
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/pmuenable.S b/package/uboot-lantiq/files/board/infineon/easy50812/pmuenable.S
deleted file mode 100644
index e0d7971d89..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/pmuenable.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  Power Management unit initialization code for AMAZON development board.
- *
- *  Copyright (c) 2003	Ou Ke, Infineon.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#define PMU_PWDCR 		0xBF10201C
-#define PMU_SR			0xBF102020
-
-	.globl	pmuenable
-
-pmuenable:
-	li      t0, PMU_PWDCR
-	li      t1, 0x2		/* enable everything */
-	sw      t1, 0(t0)
-#if 0
-1:
-	li	t0, PMU_SR
-	lw      t2, 0(t0)
-	bne     t1, t2, 1b
-	nop
-#endif
-	j	ra
-	nop
-
-
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/u-boot-bootstrap.lds b/package/uboot-lantiq/files/board/infineon/easy50812/u-boot-bootstrap.lds
deleted file mode 100644
index 52d7dafadb..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/u-boot-bootstrap.lds
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = .;
-	_gp = ALIGN(16) +0x7ff0;
-
-	.got  : {
-	__got_start = .;
-		*(.got)
-	__got_end = .;
-	}
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	. = .;
-	. = ALIGN(4);
-	.payload : { *(.payload) }
-	. = ALIGN(4);
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) . = ALIGN(4); }
-	uboot_end = .;
-}
-
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/u-boot.lds b/package/uboot-lantiq/files/board/infineon/easy50812/u-boot.lds
deleted file mode 100644
index 9a6cd1b8a3..0000000000
--- a/package/uboot-lantiq/files/board/infineon/easy50812/u-boot.lds
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	.got : {
-	  __got_start = .;
-	  *(.got)
-	  __got_end = .;
-	}
-
-	.sdata  : { *(.sdata) }
-
-	.u_boot_cmd : {
-	  __u_boot_cmd_start = .;
-	  *(.u_boot_cmd)
-	  __u_boot_cmd_end = .;
-	}
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss (NOLOAD)  : { *(.sbss) }
-	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
-	uboot_end = .;
-}