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authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2011-07-02 10:48:58 +0000
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2011-07-02 10:48:58 +0000
commit6ee23701f2b114abaca7c05c2468333abcae151f (patch)
tree408884daf46676b8d1f8cccd4ae43c76ed4418ef /package/mac80211/patches/541-ath9k_pllclock_fix.patch
parent49e32bd67811d89d81558b956c260e74aefdbe88 (diff)
ath9k: clean up pll code for ar9002 to fix 5/10 mhz pll settings for 5ghz
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27362 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/mac80211/patches/541-ath9k_pllclock_fix.patch')
-rw-r--r--package/mac80211/patches/541-ath9k_pllclock_fix.patch42
1 files changed, 42 insertions, 0 deletions
diff --git a/package/mac80211/patches/541-ath9k_pllclock_fix.patch b/package/mac80211/patches/541-ath9k_pllclock_fix.patch
new file mode 100644
index 0000000000..4738159fd9
--- /dev/null
+++ b/package/mac80211/patches/541-ath9k_pllclock_fix.patch
@@ -0,0 +1,42 @@
+--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+@@ -447,26 +447,27 @@ static void ar9002_olc_init(struct ath_h
+ static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
+ struct ath9k_channel *chan)
+ {
++ int ref_div = 5;
++ int pll_div = 0x2c;
+ u32 pll;
+
+- pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
++ if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) {
++ if (AR_SREV_9280_20(ah)) {
++ ref_div = 10;
++ pll_div = 0x50;
++ } else {
++ pll_div = 0x28;
++ }
++ }
++
++ pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
++ pll |= SM(pll_div, AR_RTC_9160_PLL_DIV);
+
+ if (chan && IS_CHAN_HALF_RATE(chan))
+ pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
+ else if (chan && IS_CHAN_QUARTER_RATE(chan))
+ pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
+
+- if (chan && IS_CHAN_5GHZ(chan)) {
+- if (IS_CHAN_A_FAST_CLOCK(ah, chan))
+- pll = 0x142c;
+- else if (AR_SREV_9280_20(ah))
+- pll = 0x2850;
+- else
+- pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
+- } else {
+- pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
+- }
+-
+ return pll;
+ }
+