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authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2006-01-10 19:43:00 +0000
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2006-01-10 19:43:00 +0000
commit489f9455f265caba0edd3488fe9580e36418eb32 (patch)
tree227994a76fef5a3c7c651667756984dc69bddb2d /openwrt/target/linux/ar7-2.4
parent3224e1420fd9c58ce5bf3b67e871730be18f8fdd (diff)
large target/linux cleanup
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@2877 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'openwrt/target/linux/ar7-2.4')
-rw-r--r--openwrt/target/linux/ar7-2.4/Makefile66
-rw-r--r--openwrt/target/linux/ar7-2.4/config1082
-rw-r--r--openwrt/target/linux/ar7-2.4/patches/000-ar7_support.patch9549
-rw-r--r--openwrt/target/linux/ar7-2.4/patches/001-flash_map.patch307
-rw-r--r--openwrt/target/linux/ar7-2.4/patches/002-led_driver.patch1915
-rw-r--r--openwrt/target/linux/ar7-2.4/patches/003-net_driver_cpmac.patch13341
-rw-r--r--openwrt/target/linux/ar7-2.4/patches/004-atm_driver.patch27232
-rw-r--r--openwrt/target/linux/ar7-2.4/patches/005-wdt_driver.patch392
-rw-r--r--openwrt/target/linux/ar7-2.4/patches/006-sched_use_tsc.patch84
9 files changed, 53968 insertions, 0 deletions
diff --git a/openwrt/target/linux/ar7-2.4/Makefile b/openwrt/target/linux/ar7-2.4/Makefile
new file mode 100644
index 0000000000..daa734107d
--- /dev/null
+++ b/openwrt/target/linux/ar7-2.4/Makefile
@@ -0,0 +1,66 @@
+include $(TOPDIR)/rules.mk
+
+LINUX_VERSION:=2.4.32
+LINUX_RELEASE:=1
+LINUX_KERNEL_MD5SUM:=38f4d0830e95a20f4bfed17622d5557c
+
+include ../rules.mk
+include ./config
+
+ATM_FIRMWARE_VERSION:=0.4
+ATM_FIRMWARE_DIR=sangam-atm-firmware-$(ATM_FIRMWARE_VERSION)
+
+$(eval $(call KMOD_template,SANGAM_ATM_A,sangam-atm-annex-a,\
+ $(MODULES_DIR)/kernel/drivers/atm/tiatm.o \
+,CONFIG_MIPS_SANGAM_ATM,kmod-atm,60,tiatm, \
+ cp $(BUILD_DIR)/$(ATM_FIRMWARE_DIR)/ar0700xx_a.bin $$(I_SANGAM_ATM_A)/lib/modules/ar0700xx.bin \
+))
+
+$(eval $(call KMOD_template,SANGAM_ATM_B,sangam-atm-annex-b,\
+ $(MODULES_DIR)/kernel/drivers/atm/tiatm.o \
+,CONFIG_MIPS_SANGAM_ATM,kmod-atm,60,tiatm, \
+ cp $(BUILD_DIR)/$(ATM_FIRMWARE_DIR)/ar0700xx_b.bin $$(I_SANGAM_ATM_B)/lib/modules/ar0700xx.bin \
+))
+
+$(eval $(call KMOD_template,CPMAC,cpmac,\
+ $(MODULES_DIR)/kernel/drivers/net/avalanche_cpmac/avalanche_cpmac.o \
+,CONFIG_MIPS_AVALANCHE_CPMAC,,10,avalanche_cpmac))
+
+include ../generic-$(KERNEL)/modules.mk
+include ../kernel.mk
+
+
+$(LINUX_DIR)/.patched: $(LINUX_DIR)/.unpacked
+ [ -d ../generic-$(KERNEL)/patches ] && $(PATCH) $(LINUX_DIR) ../generic-$(KERNEL)/patches $(MAKE_TRACE)
+ [ -d ./patches ] && $(PATCH) $(LINUX_DIR) ./patches $(MAKE_TRACE)
+ @cp config $(LINUX_DIR)/.config
+ touch $@
+
+
+###############################################
+# ATM firmware for the DSL modem
+###############################################
+
+DOWNLOAD_SITE=http://openwrt.org/downloads/sources
+# extracted from netgear DG834B V1.0.5 GPL release
+ATM_FIRMWARE_FILE=$(ATM_FIRMWARE_DIR).tar.gz
+ATM_FIRMWARE_MD5SUM=8bfcb31109796502d66b11baaeb2fba6
+
+$(DL_DIR)/$(ATM_FIRMWARE_FILE):
+ $(SCRIPT_DIR)/download.pl $(DL_DIR) $(ATM_FIRMWARE_FILE) $(ATM_FIRMWARE_MD5SUM) $(DOWNLOAD_SITE) $(MAKE_TRACE)
+
+$(LINUX_DIR)/.unpacked: $(DL_DIR)/$(ATM_FIRMWARE_FILE)
+$(LINUX_DIR)/.depend_done: $(LINUX_DIR)/.drivers-unpacked
+$(LINUX_DIR)/.modules_done: $(LINUX_DIR)/.drivers-unpacked
+
+$(LINUX_DIR)/.drivers-unpacked: $(LINUX_DIR)/.unpacked
+ -mkdir -p $(BUILD_DIR)
+ zcat $(DL_DIR)/$(ATM_FIRMWARE_FILE) | tar -C $(BUILD_DIR) $(TAR_OPTIONS) -
+ touch $@
+
+linux-dirclean: drivers-clean
+
+drivers-clean:
+ rm -rf $(BUILD_DIR)/$(ATM_FIRMWARE_DIR)
+
+
diff --git a/openwrt/target/linux/ar7-2.4/config b/openwrt/target/linux/ar7-2.4/config
new file mode 100644
index 0000000000..fb4ede0903
--- /dev/null
+++ b/openwrt/target/linux/ar7-2.4/config
@@ -0,0 +1,1082 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+# CONFIG_MIPS64 is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+CONFIG_AR7=y
+# CONFIG_AR7DB is not set
+# CONFIG_AR7RD is not set
+CONFIG_AR7WRD=y
+CONFIG_AR7_CPU=150
+CONFIG_AR7_SYS=125
+CONFIG_AR7_MEMORY=0x14000000
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_FICMMP is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_HYDROGEN3 is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_COGENT_CSB250 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_CASIO_E55 is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_IBM_WORKPAD is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_PMC_BIG_SUR is not set
+# CONFIG_PMC_STRETCH is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_NEC_EAGLE is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SIBYTE_SB1xxx_SOC is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TANBAC_TB0226 is not set
+# CONFIG_TANBAC_TB0229 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_VICTOR_MPC30X is not set
+# CONFIG_ZAO_CAPCELLA is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_IRQ_CPU=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_SWAP_IO_SPACE=y
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_VTAG_ICACHE is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_LLDSCD is not set
+# CONFIG_CPU_HAS_WB is not set
+CONFIG_CPU_HAS_SYNC=y
+
+#
+# General setup
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_BUILD_ELF64 is not set
+CONFIG_NET=y
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+# CONFIG_PCMCIA is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+# CONFIG_HOTPLUG_PCI_SHPC_POLL_EVENT_MODE is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODE is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_ELF_AOUT is not set
+# CONFIG_MIPS32_COMPAT is not set
+# CONFIG_MIPS32_O32 is not set
+# CONFIG_MIPS32_N32 is not set
+# CONFIG_BINFMT_ELF32 is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_OOM_KILLER is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd"
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_B1 is not set
+CONFIG_MTD_CFI_B2=y
+# CONFIG_MTD_CFI_B4 is not set
+# CONFIG_MTD_CFI_B8 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_CFI_SSTSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_AR7=y
+CONFIG_MTD_AR7_DEFAULTS=y
+CONFIG_MTD_AR7_START=0x10000000
+CONFIG_MTD_AR7_LEN=0x400000
+CONFIG_MTD_AR7_BUSWIDTH=2
+# CONFIG_MTD_PB1000 is not set
+# CONFIG_MTD_PB1500 is not set
+# CONFIG_MTD_PB1100 is not set
+# CONFIG_MTD_BOSPORUS is not set
+# CONFIG_MTD_XXS1500 is not set
+# CONFIG_MTD_MTX1 is not set
+# CONFIG_MTD_DB1X00 is not set
+# CONFIG_MTD_PB1550 is not set
+# CONFIG_MTD_HYDROGEN3 is not set
+# CONFIG_MTD_MIRAGE is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_LASAT is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PCMCIA is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_CISS_MONITOR_THREAD is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_BLK_STATS is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_NETLINK_DEV=m
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_FWMARK=y
+CONFIG_IP_ROUTE_NAT=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_TOS=y
+# CONFIG_IP_ROUTE_VERBOSE is not set
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_FTP=y
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_IRC=y
+CONFIG_IP_NF_CT_ACCT=m
+CONFIG_IP_NF_MATCH_CONNBYTES=m
+CONFIG_IP_NF_CT_PROTO_GRE=m
+CONFIG_IP_NF_PPTP=m
+CONFIG_IP_NF_SIP=m
+CONFIG_IP_NF_H323=m
+CONFIG_IP_NF_MMS=m
+CONFIG_IP_NF_RTSP=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_LIMIT=m
+CONFIG_IP_NF_MATCH_QUOTA=m
+CONFIG_IP_NF_SET=m
+CONFIG_IP_NF_SET_MAX=256
+CONFIG_IP_NF_SET_HASHSIZE=1024
+CONFIG_IP_NF_MATCH_SET=m
+CONFIG_IP_NF_TARGET_SET=m
+CONFIG_IP_NF_SET_IPMAP=m
+CONFIG_IP_NF_SET_PORTMAP=m
+CONFIG_IP_NF_SET_MACIPMAP=m
+CONFIG_IP_NF_SET_IPHASH=m
+CONFIG_IP_NF_SET_NETHASH=m
+CONFIG_IP_NF_SET_IPTREE=m
+CONFIG_IP_NF_MATCH_MAC=m
+CONFIG_IP_NF_MATCH_PKTTYPE=m
+CONFIG_IP_NF_MATCH_MARK=y
+CONFIG_IP_NF_MATCH_MULTIPORT=y
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_TIME=m
+CONFIG_IP_NF_MATCH_CONDITION=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_IPP2P=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_TCPMSS=m
+CONFIG_IP_NF_MATCH_HELPER=m
+CONFIG_IP_NF_MATCH_STATE=y
+CONFIG_IP_NF_MATCH_CONNTRACK=m
+CONFIG_IP_NF_MATCH_CONNMARK=m
+CONFIG_IP_NF_MATCH_UNCLEAN=m
+CONFIG_IP_NF_MATCH_STRING=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_LAYER7=m
+# CONFIG_IP_NF_MATCH_LAYER7_DEBUG is not set
+CONFIG_IP_NF_MATCH_LAYER7_MAXDATALEN=2048
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_MIRROR=m
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_NAT_PPTP=m
+CONFIG_IP_NF_NAT_PROTO_GRE=m
+CONFIG_IP_NF_NAT_SIP=m
+CONFIG_IP_NF_NAT_H323=m
+CONFIG_IP_NF_NAT_MMS=m
+CONFIG_IP_NF_NAT_RTSP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=y
+CONFIG_IP_NF_NAT_FTP=y
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_MARK=y
+CONFIG_IP_NF_TARGET_IMQ=m
+CONFIG_IP_NF_TARGET_CONNMARK=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=y
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+CONFIG_IPV6=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_LIMIT=m
+CONFIG_IP6_NF_MATCH_CONDITION=m
+CONFIG_IP6_NF_MATCH_MAC=m
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+CONFIG_IP6_NF_MATCH_MULTIPORT=m
+CONFIG_IP6_NF_MATCH_OWNER=m
+CONFIG_IP6_NF_MATCH_MARK=m
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_AHESP is not set
+CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_IMQ=m
+# CONFIG_KHTTPD is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+CONFIG_ATM=m
+# CONFIG_ATM_CLIP is not set
+# CONFIG_ATM_LANE is not set
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+CONFIG_VLAN_8021Q=y
+
+#
+#
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+CONFIG_BRIDGE=y
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_CSZ=m
+CONFIG_NET_SCH_HFSC=m
+# CONFIG_NET_SCH_ATM is not set
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+# CONFIG_NET_SCH_NETEM is not set
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_QOS=y
+CONFIG_NET_ESTIMATOR=y
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_POLICE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_IPSEC_NAT_TRAVERSAL=y
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=m
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+CONFIG_SD_EXTRA_DEVS=5
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_MEGARAID2 is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_SATA_AHCI is not set
+# CONFIG_SCSI_SATA_SVW is not set
+# CONFIG_SCSI_ATA_PIIX is not set
+# CONFIG_SCSI_SATA_NV is not set
+# CONFIG_SCSI_SATA_QSTOR is not set
+# CONFIG_SCSI_SATA_PROMISE is not set
+# CONFIG_SCSI_SATA_SX4 is not set
+# CONFIG_SCSI_SATA_SIL is not set
+# CONFIG_SCSI_SATA_SIS is not set
+# CONFIG_SCSI_SATA_ULI is not set
+# CONFIG_SCSI_SATA_VIA is not set
+# CONFIG_SCSI_SATA_VITESSE is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_BOOT is not set
+# CONFIG_FUSION_ISENSE is not set
+# CONFIG_FUSION_CTL is not set
+# CONFIG_FUSION_LAN is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_IMQ=m
+CONFIG_TUN=m
+CONFIG_NET_RANDOM=y
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MIPS_AVALANCHE_CPMAC=m
+CONFIG_MIPS_CPMAC_INIT_BUF_MALLOC=y
+CONFIG_MIPS_CPMAC_PORTS=1
+CONFIG_AVALANCHE_CPMAC_AUTO=y
+# CONFIG_AVALANCHE_LOW_CPMAC is not set
+# CONFIG_AVALANCHE_HIGH_CPMAC is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE_MPPC=m
+CONFIG_PPPOE=m
+CONFIG_PPPOATM=m
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+CONFIG_NET_RADIO=y
+# CONFIG_STRIP is not set
+# CONFIG_WAVELAN is not set
+# CONFIG_ARLAN is not set
+# CONFIG_AIRONET4500 is not set
+# CONFIG_AIRONET4500_NONCS is not set
+# CONFIG_AIRONET4500_PROC is not set
+# CONFIG_HERMES is not set
+
+#
+# Prism54 PCI/PCMCIA GT/Duette Driver - 802.11(a/b/g)
+#
+# CONFIG_PRISM54 is not set
+# CONFIG_NET_WIRELESS is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+CONFIG_SHAPER=m
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# ATM drivers
+#
+# CONFIG_ATM_TCP is not set
+CONFIG_MIPS_SANGAM_ATM=m
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_UINPUT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_AR7_LED=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=128
+CONFIG_AR7_VLYNQ=y
+CONFIG_VLYNQ_CLK_LOCAL=y
+CONFIG_AR7_VLYNQ_PORTS=2
+CONFIG_AR7_ADAM2=y
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_IPMI_PANIC_EVENT is not set
+# CONFIG_IPMI_DEVICE_INTERFACE is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_IPMI_WATCHDOG is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_AR7_WDT=y
+CONFIG_SOFT_WATCHDOG=m
+# CONFIG_SCx200 is not set
+# CONFIG_SCx200_GPIO is not set
+# CONFIG_AMD_PM768 is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+
+#
+# Direct Rendering Manager (XFree86 DRI support)
+#
+# CONFIG_DRM is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_QFMT_V2 is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BEFS_DEBUG is not set
+# CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=m
+CONFIG_JBD=m
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=m
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=m
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_BBC_ARMLIB is not set
+# CONFIG_JFFS2_BBC_LZO is not set
+CONFIG_JFFS2_BBC_LZARI=y
+# CONFIG_JFFS2_BBC_LZHD is not set
+# CONFIG_JFFS2_BBC_LZSS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_TMPFS=y
+CONFIG_RAMFS=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=m
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_TRACE is not set
+# CONFIG_XFS_DEBUG is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_NFSD_TCP is not set
+CONFIG_SUNRPC=m
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+CONFIG_CIFS_POSIX=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# Support for USB gadgets
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Bluetooth support
+#
+CONFIG_BLUEZ=m
+CONFIG_BLUEZ_L2CAP=m
+CONFIG_BLUEZ_SCO=m
+CONFIG_BLUEZ_RFCOMM=m
+CONFIG_BLUEZ_RFCOMM_TTY=y
+CONFIG_BLUEZ_BNEP=m
+CONFIG_BLUEZ_BNEP_MC_FILTER=y
+CONFIG_BLUEZ_BNEP_PROTO_FILTER=y
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BLUEZ_HCIUSB is not set
+CONFIG_BLUEZ_HCIUART=m
+CONFIG_BLUEZ_HCIUART_H4=y
+CONFIG_BLUEZ_HCIUART_BCSP=y
+CONFIG_BLUEZ_HCIUART_BCSP_TXCRC=y
+# CONFIG_BLUEZ_HCIBFUSB is not set
+# CONFIG_BLUEZ_HCIDTL1 is not set
+# CONFIG_BLUEZ_HCIBT3C is not set
+# CONFIG_BLUEZ_HCIBLUECARD is not set
+# CONFIG_BLUEZ_HCIBTUART is not set
+# CONFIG_BLUEZ_HCIVHCI is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_RUNTIME_DEBUG is not set
+# CONFIG_KGDB is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG_INFO is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MIPS_UNCACHED is not set
+CONFIG_LOG_BUF_SHIFT=0
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC32 is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+# CONFIG_FW_LOADER is not set
diff --git a/openwrt/target/linux/ar7-2.4/patches/000-ar7_support.patch b/openwrt/target/linux/ar7-2.4/patches/000-ar7_support.patch
new file mode 100644
index 0000000000..0c9c0d3028
--- /dev/null
+++ b/openwrt/target/linux/ar7-2.4/patches/000-ar7_support.patch
@@ -0,0 +1,9549 @@
+diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
+--- linux.old/arch/mips/Makefile 2005-10-21 16:43:16.316951500 +0200
++++ linux.dev/arch/mips/Makefile 2005-11-10 01:10:45.775570250 +0100
+@@ -369,6 +369,16 @@
+ endif
+
+ #
++# Texas Instruments AR7
++#
++
++ifdef CONFIG_AR7
++LIBS += arch/mips/ar7/ar7.o
++SUBDIRS += arch/mips/ar7
++LOADADDR += 0x94020000
++endif
++
++#
+ # DECstation family
+ #
+ ifdef CONFIG_DECSTATION
+diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
+--- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/Makefile 2005-11-10 01:13:51.443173750 +0100
+@@ -0,0 +1,14 @@
++.S.s:
++ $(CPP) $(AFLAGS) $< -o $*.s
++
++.S.o:
++ $(CC) $(AFLAGS) -c $< -o $*.o
++
++EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
++O_TARGET := ar7.o
++
++obj-y := tnetd73xx_misc.o misc.o
++export-objs := misc.o irq.o init.o
++obj-y += setup.o irq.o int-handler.o reset.o init.o psp_env.o memory.o promlib.o cmdline.o
++
++include $(TOPDIR)/Rules.make
+diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
+--- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/cmdline.c 2005-11-10 01:14:16.372731750 +0100
+@@ -0,0 +1,88 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Kernel command line creation using the prom monitor (YAMON) argc/argv.
++ */
++#include <linux/init.h>
++#include <linux/string.h>
++
++#include <asm/bootinfo.h>
++
++extern int prom_argc;
++extern int *_prom_argv;
++
++/*
++ * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
++ * This macro take care of sign extension.
++ */
++#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
++
++char arcs_cmdline[CL_SIZE];
++#ifdef CONFIG_CMDLINE_BOOL
++char __initdata cfg_cmdline[] = CONFIG_CMDLINE;
++#endif
++
++char * __init prom_getcmdline(void)
++{
++ return &(arcs_cmdline[0]);
++}
++
++
++void __init prom_init_cmdline(void)
++{
++ char *cp, *end;
++ int actr;
++ char *env_cmdline = prom_getenv("kernel_args");
++ size_t len;
++
++ actr = 1; /* Always ignore argv[0] */
++
++ cp = end = &(arcs_cmdline[0]);
++ end += sizeof(arcs_cmdline);
++
++ if (env_cmdline) {
++ len = strlen(env_cmdline);
++ if (len > end - cp - 1)
++ len = end - cp - 1;
++ strncpy(cp, env_cmdline, len);
++ cp += len;
++ *cp++ = ' ';
++ }
++#ifdef CONFIG_CMDLINE_BOOL
++ else {
++ len = strlen(cfg_cmdline);
++ if (len > end - cp - 1)
++ len = end - cp - 1;
++ strncpy(cp, cfg_cmdline, len);
++ cp += len;
++ *cp++ = ' ';
++ }
++#endif
++
++ while(actr < prom_argc) {
++ len = strlen(prom_argv(actr));
++ if (len > end - cp - 1)
++ break;
++ strncpy(cp, prom_argv(actr), len);
++ cp += len;
++ *cp++ = ' ';
++ actr++;
++ }
++ if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
++ --cp;
++ *cp = '\0';
++}
+diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
+--- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/init.c 2005-11-10 01:10:45.795571500 +0100
+@@ -0,0 +1,199 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * PROM library initialisation code.
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/string.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++
++#include <asm/io.h>
++#include <asm/mips-boards/prom.h>
++#include <asm/mips-boards/generic.h>
++
++#include <asm/ar7/adam2_env.h>
++
++int prom_argc;
++int *_prom_argv, *_prom_envp;
++
++/* max # of Adam2 environment variables */
++#define MAX_ENV_ENTRY 80
++
++static t_env_var local_envp[MAX_ENV_ENTRY];
++static int env_type = 0;
++int init_debug = 0;
++
++unsigned int max_env_entry;
++
++extern char *prom_psp_getenv(char *envname);
++
++static inline char *prom_adam2_getenv(char *envname)
++{
++ /*
++ * Return a pointer to the given environment variable.
++ * In 64-bit mode: we're using 64-bit pointers, but all pointers
++ * in the PROM structures are only 32-bit, so we need some
++ * workarounds, if we are running in 64-bit mode.
++ */
++ int i;
++ t_env_var *env = (t_env_var *) local_envp;
++
++ if (strcmp("bootloader", envname) == 0)
++ return "Adam2";
++
++ i = strlen(envname);
++ while (env->name) {
++ if(strncmp(envname, env->name, i) == 0) {
++ return(env->val);
++ }
++ env++;
++ }
++
++ return NULL;
++}
++
++/* XXX "bootloader" won't be returned.
++ * Better make it an element of local_envp */
++static inline t_env_var *
++prom_adam2_iterenv(t_env_var *env) {
++ if (!env)
++ env = local_envp;
++ else
++ env++;
++ if (env - local_envp > MAX_ENV_ENTRY || !env->name)
++ return 0;
++ return env;
++}
++
++char *prom_getenv(char *envname)
++{
++ if (env_type == 1)
++ return prom_psp_getenv(envname);
++ else
++ return prom_adam2_getenv(envname);
++}
++
++t_env_var *
++prom_iterenv(t_env_var *last)
++{
++ if (env_type == 1)
++ return 0; /* not yet implemented */
++ return prom_adam2_iterenv(last);
++}
++
++static inline unsigned char str2hexnum(unsigned char c)
++{
++ if (c >= '0' && c <= '9')
++ return c - '0';
++ if (c >= 'a' && c <= 'f')
++ return c - 'a' + 10;
++ return 0; /* foo */
++}
++
++static inline void str2eaddr(unsigned char *ea, unsigned char *str)
++{
++ int i;
++
++ for (i = 0; i < 6; i++) {
++ unsigned char num;
++
++ if((*str == '.') || (*str == ':'))
++ str++;
++ num = str2hexnum(*str++) << 4;
++ num |= (str2hexnum(*str++));
++ ea[i] = num;
++ }
++}
++
++int get_ethernet_addr(char *ethernet_addr)
++{
++ char *ethaddr_str;
++
++ ethaddr_str = prom_getenv("ethaddr");
++ if (!ethaddr_str) {
++ printk("ethaddr not set in boot prom\n");
++ return -1;
++ }
++ str2eaddr(ethernet_addr, ethaddr_str);
++
++ if (init_debug > 1) {
++ int i;
++ printk("get_ethernet_addr: ");
++ for (i=0; i<5; i++)
++ printk("%02x:", (unsigned char)*(ethernet_addr+i));
++ printk("%02x\n", *(ethernet_addr+i));
++ }
++
++ return 0;
++}
++
++struct psbl_rec {
++ unsigned int psbl_size;
++ unsigned int env_base;
++ unsigned int env_size;
++ unsigned int ffs_base;
++ unsigned int ffs_size;
++};
++
++static const char psp_env_version[] = "TIENV0.8";
++
++int __init prom_init(int argc, char **argv, char **envp)
++{
++ int i;
++
++ t_env_var *env = (t_env_var *) envp;
++ struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
++ void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
++
++ prom_argc = argc;
++ _prom_argv = (int *)argv;
++ _prom_envp = (int *)envp;
++
++ if(strcmp(psp_env, psp_env_version) == 0) {
++ /* PSPBOOT */
++
++ env_type = 1;
++ _prom_envp = psp_env;
++ max_env_entry = (psbl->env_size / 16) - 1;
++ } else {
++ /* Copy what we need locally so we are not dependent on
++ * bootloader RAM. In Adam2, the environment parameters
++ * are in flash but the table that references them is in
++ * RAM
++ */
++
++ for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
++ if (env->name) {
++ local_envp[i].name = env->name;
++ local_envp[i].val = env->val;
++ } else {
++ local_envp[i].name = NULL;
++ local_envp[i].val = NULL;
++ }
++ }
++ }
++
++ set_io_port_base(0);
++
++ prom_printf("\nLINUX started...\n");
++ prom_init_cmdline();
++ prom_meminit();
++
++ return 0;
++}
+diff -urN linux.old/arch/mips/ar7/int-handler.S linux.dev/arch/mips/ar7/int-handler.S
+--- linux.old/arch/mips/ar7/int-handler.S 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/int-handler.S 2005-11-10 01:12:43.938955000 +0100
+@@ -0,0 +1,63 @@
++/*
++ * Copyright 2004 PMC-Sierra Inc.
++ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
++ * Adaption for AR7: Enrik Berkhan <enrik@akk.org>
++ *
++ * First-level interrupt dispatcher for the TI AR7
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++#define __ASSEMBLY__
++#include <linux/config.h>
++#include <asm/asm.h>
++#include <asm/mipsregs.h>
++#include <asm/addrspace.h>
++#include <asm/regdef.h>
++#include <asm/stackframe.h>
++
++/*
++ * First level interrupt dispatcher for TI AR7 based boards
++ */
++
++ .align 5
++ NESTED(ar7IRQ, PT_SIZE, sp)
++ SAVE_ALL
++ CLI
++ .set at
++
++ mfc0 t0, CP0_CAUSE
++ mfc0 t2, CP0_STATUS
++
++ and t0, t2
++
++ andi t1, t0, STATUSF_IP2 /* hw0 hardware interrupt */
++ bnez t1, ll_hw0_irq
++
++ andi t1, t0, STATUSF_IP7 /* R4k CPU timer */
++ bnez t1, ll_timer_irq
++
++ .set reorder
++
++ /* wrong alarm or masked ... */
++ j spurious_interrupt
++ nop
++ END(ar7IRQ)
++
++ .align 5
++
++ll_hw0_irq:
++ li a0, 2
++ move a1, sp
++ jal do_IRQ
++ j ret_from_irq
++
++ll_timer_irq:
++ li a0, 7
++ move a1, sp
++ jal do_IRQ
++ j ret_from_irq
++
++
+diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
+--- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/irq.c 2005-11-10 01:12:43.938955000 +0100
+@@ -0,0 +1,427 @@
++/*
++ * Nitin Dhingra, iamnd@ti.com
++ * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Routines for generic manipulation of the interrupts found on the Texas
++ * Instruments avalanche board
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/interrupt.h>
++
++#include <asm/irq.h>
++#include <asm/mipsregs.h>
++#include <asm/ar7/ar7.h>
++#include <asm/ar7/avalanche_intc.h>
++
++#define shutdown_avalanche_irq disable_avalanche_irq
++#define mask_and_ack_avalanche_irq disable_avalanche_irq
++
++static unsigned int startup_avalanche_irq(unsigned int irq);
++static void end_avalanche_irq(unsigned int irq);
++void enable_avalanche_irq(unsigned int irq_nr);
++void disable_avalanche_irq(unsigned int irq_nr);
++void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs);
++
++static struct hw_interrupt_type avalanche_irq_type = {
++ "AR7",
++ startup_avalanche_irq,
++ shutdown_avalanche_irq,
++ enable_avalanche_irq,
++ disable_avalanche_irq,
++ mask_and_ack_avalanche_irq,
++ end_avalanche_irq,
++ NULL
++};
++
++static int ar7_irq_base;
++
++static struct irqaction ar7_hw0_action = {
++ ar7_hw0_interrupt, 0, 0, "AR7 on hw0", NULL, NULL
++};
++
++struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
++struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
++struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
++struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
++
++/*
++ This remaps interrupts to exist on other channels than the default
++ channels. essentially we can use the line # as the index for this
++ array
++ */
++
++static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
++unsigned long uni_secondary_interrupt = 0;
++
++static void end_avalanche_irq(unsigned int irq)
++{
++ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
++ enable_avalanche_irq(irq);
++}
++
++void disable_avalanche_irq(unsigned int irq_nr)
++{
++ unsigned long flags;
++ unsigned long chan_nr=0;
++
++ save_and_cli(flags);
++
++ /* irq_nr represents the line number for the interrupt. We must
++ * disable the channel number associated with that line number.
++ */
++
++ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
++ chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
++ else
++ chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
++
++ /* disable the interrupt channel bit */
++
++ /* primary interrupt #'s 0-31 */
++
++ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
++ avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
++
++ /* primary interrupt #'s 32-39 */
++
++ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
++ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
++ avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
++
++ else /* secondary interrupt #'s 0-31 */
++ avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
++
++ restore_flags(flags);
++}
++
++void enable_avalanche_irq(unsigned int irq_nr)
++{
++ unsigned long flags;
++ unsigned long chan_nr=0;
++
++ save_and_cli(flags);
++
++ /* irq_nr represents the line number for the interrupt. We must
++ * disable the channel number associated with that line number.
++ */
++
++ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
++ chan_nr = AVINTNUM(irq_nr);
++ else
++ chan_nr = line_to_channel[AVINTNUM(irq_nr)];
++
++ /* enable the interrupt channel bit */
++
++ /* primary interrupt #'s 0-31 */
++ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
++ avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
++
++ /* primary interrupt #'s 32 throuth 39 */
++ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
++ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
++ avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
++
++ else /* secondary interrupt #'s 0-31 */
++ avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
++
++ restore_flags(flags);
++}
++
++static unsigned int startup_avalanche_irq(unsigned int irq)
++{
++ enable_avalanche_irq(irq);
++ return 0; /* never anything pending */
++}
++
++void __init ar7_irq_init(int base)
++{
++ int i;
++
++ avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
++ avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
++ avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
++ avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
++
++ /* Disable interrupts and clear pending
++ */
++
++ avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
++ avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
++ avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
++ avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
++ avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
++ avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
++
++
++ // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
++ /* hack for speeding up the pacing. */
++ printk("the pacing pre-scalar has been set as 600.\n");
++ avalanche_hw0_ipaceregs->ipacep = 600;
++ /* Channel to line mapping, Line to Channel mapping */
++
++ for(i = 0; i < 40; i++)
++ avalanche_int_set(i,i);
++
++ ar7_irq_base = base;
++ for (i = base; i <= base+40; i++)
++ {
++ irq_desc[i].status = IRQ_DISABLED;
++ irq_desc[i].action = 0;
++ irq_desc[i].depth = 1;
++ irq_desc[i].handler = &avalanche_irq_type;
++ }
++
++ setup_irq(2, &ar7_hw0_action);
++ set_c0_status(IE_IRQ0);
++
++ return;
++}
++
++void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs)
++{
++ int irq;
++ unsigned long int_line_number, status;
++ int i, chan_nr = 0;
++
++ int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
++ chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
++
++ if(chan_nr < 32) /* primary 0-31 */
++ {
++ if( chan_nr != uni_secondary_interrupt)
++ avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
++
++ }
++
++ if((chan_nr < 40) && (chan_nr > 31)) /* primary 32-39 */
++ {
++ avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-32));
++ }
++
++
++ /* If the Priority Interrupt Index Register returns 40 then no
++ * interrupts are pending
++ */
++
++ if(chan_nr == 40)
++ return;
++
++ if(chan_nr == uni_secondary_interrupt) /* secondary 0-31 */
++ {
++ status = avalanche_hw0_ecregs->exsr;
++ for(i=0; i < 32; i++)
++ {
++ if (status & 1<<i)
++ {
++ /* clear secondary interrupt */
++ avalanche_hw0_ecregs->excr = 1 << i;
++ break;
++ }
++ }
++ irq = i+40;
++
++ /* clear the universal secondary interrupt */
++ avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
++
++ }
++ else
++ irq = chan_nr;
++
++ do_IRQ(irq + ar7_irq_base, regs);
++ return;
++}
++
++void avalanche_int_set(int channel, int line)
++{
++ switch(channel)
++ {
++ case(0):
++ avalanche_hw0_chregs->cintnr0 = line;
++ break;
++ case(1):
++ avalanche_hw0_chregs->cintnr1 = line;
++ break;
++ case(2):
++ avalanche_hw0_chregs->cintnr2 = line;
++ break;
++ case(3):
++ avalanche_hw0_chregs->cintnr3 = line;
++ break;
++ case(4):
++ avalanche_hw0_chregs->cintnr4 = line;
++ break;
++ case(5):
++ avalanche_hw0_chregs->cintnr5 = line;
++ break;
++ case(6):
++ avalanche_hw0_chregs->cintnr6 = line;
++ break;
++ case(7):
++ avalanche_hw0_chregs->cintnr7 = line;
++ break;
++ case(8):
++ avalanche_hw0_chregs->cintnr8 = line;
++ break;
++ case(9):
++ avalanche_hw0_chregs->cintnr9 = line;
++ break;
++ case(10):
++ avalanche_hw0_chregs->cintnr10 = line;
++ break;
++ case(11):
++ avalanche_hw0_chregs->cintnr11 = line;
++ break;
++ case(12):
++ avalanche_hw0_chregs->cintnr12 = line;
++ break;
++ case(13):
++ avalanche_hw0_chregs->cintnr13 = line;
++ break;
++ case(14):
++ avalanche_hw0_chregs->cintnr14 = line;
++ break;
++ case(15):
++ avalanche_hw0_chregs->cintnr15 = line;
++ break;
++ case(16):
++ avalanche_hw0_chregs->cintnr16 = line;
++ break;
++ case(17):
++ avalanche_hw0_chregs->cintnr17 = line;
++ break;
++ case(18):
++ avalanche_hw0_chregs->cintnr18 = line;
++ break;
++ case(19):
++ avalanche_hw0_chregs->cintnr19 = line;
++ break;
++ case(20):
++ avalanche_hw0_chregs->cintnr20 = line;
++ break;
++ case(21):
++ avalanche_hw0_chregs->cintnr21 = line;
++ break;
++ case(22):
++ avalanche_hw0_chregs->cintnr22 = line;
++ break;
++ case(23):
++ avalanche_hw0_chregs->cintnr23 = line;
++ break;
++ case(24):
++ avalanche_hw0_chregs->cintnr24 = line;
++ break;
++ case(25):
++ avalanche_hw0_chregs->cintnr25 = line;
++ break;
++ case(26):
++ avalanche_hw0_chregs->cintnr26 = line;
++ break;
++ case(27):
++ avalanche_hw0_chregs->cintnr27 = line;
++ break;
++ case(28):
++ avalanche_hw0_chregs->cintnr28 = line;
++ break;
++ case(29):
++ avalanche_hw0_chregs->cintnr29 = line;
++ break;
++ case(30):
++ avalanche_hw0_chregs->cintnr30 = line;
++ break;
++ case(31):
++ avalanche_hw0_chregs->cintnr31 = line;
++ break;
++ case(32):
++ avalanche_hw0_chregs->cintnr32 = line;
++ break;
++ case(33):
++ avalanche_hw0_chregs->cintnr33 = line;
++ break;
++ case(34):
++ avalanche_hw0_chregs->cintnr34 = line;
++ break;
++ case(35):
++ avalanche_hw0_chregs->cintnr35 = line;
++ break;
++ case(36):
++ avalanche_hw0_chregs->cintnr36 = line;
++ break;
++ case(37):
++ avalanche_hw0_chregs->cintnr37 = line;
++ break;
++ case(38):
++ avalanche_hw0_chregs->cintnr38 = line;
++ break;
++ case(39):
++ avalanche_hw0_chregs->cintnr39 = line;
++ break;
++ default:
++ printk("Error: Unknown Avalanche interrupt channel\n");
++ }
++
++ line_to_channel[line] = channel; /* Suraj check */
++
++ if (channel == UNIFIED_SECONDARY_INTERRUPT)
++ uni_secondary_interrupt = line;
++
++}
++
++
++#define AVALANCHE_MAX_PACING_BLK 3
++#define AVALANCHE_PACING_LOW_VAL 2
++#define AVALANCHE_PACING_HIGH_VAL 63
++
++int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
++ unsigned int pace_value)
++{
++ unsigned int blk_offset;
++ unsigned long flags;
++
++ if(irq_nr < MIPS_EXCEPTION_OFFSET &&
++ irq_nr >= AVALANCHE_INT_END_PRIMARY)
++ return (0);
++
++ if(blk_num > AVALANCHE_MAX_PACING_BLK)
++ return(-1);
++
++ if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
++ pace_value < AVALANCHE_PACING_LOW_VAL)
++ return(-1);
++
++ blk_offset = blk_num*8;
++
++ save_and_cli(flags);
++
++ /* disable the interrupt pacing, if enabled previously */
++ avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
++
++ /* clear the pacing map */
++ avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
++
++ /* setup the new values */
++ avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
++ avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
++
++ restore_flags(flags);
++
++ return(0);
++}
+diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
+--- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/memory.c 2005-11-10 01:14:16.372731750 +0100
+@@ -0,0 +1,103 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ */
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/bootmem.h>
++
++#include <asm/bootinfo.h>
++#include <asm/page.h>
++#include <asm/mips-boards/prom.h>
++
++extern char _ftext;
++extern int preserve_adam2;
++
++void __init prom_meminit(void)
++{
++ char *memsize_str;
++ unsigned long memsize, adam2size;
++
++ /* assume block before kernel is used by bootloader */
++ adam2size = __pa(&_ftext) - PHYS_OFFSET;
++
++ memsize_str = prom_getenv("memsize");
++ if (!memsize_str) {
++ memsize = 0x02000000;
++ } else {
++ memsize = simple_strtol(memsize_str, NULL, 0);
++ }
++
++#if 0
++ add_memory_region(0x00000000, PHYS_OFFSET, BOOT_MEM_RESERVED);
++#endif
++ add_memory_region(PHYS_OFFSET, adam2size, BOOT_MEM_ROM_DATA);
++ add_memory_region(PHYS_OFFSET+adam2size, memsize-adam2size,
++ BOOT_MEM_RAM);
++}
++
++unsigned long __init prom_free_prom_memory (void)
++{
++ int i;
++ unsigned long freed = 0;
++ unsigned long addr;
++
++ if (preserve_adam2) {
++ char *firstfree_str = prom_getenv("firstfreeaddress");
++ unsigned long firstfree = 0;
++
++ if (firstfree_str)
++ firstfree = simple_strtol(firstfree_str, NULL, 0);
++
++ if (firstfree && firstfree < (unsigned long)&_ftext) {
++ printk("Preserving ADAM2 memory.\n");
++ } else if (firstfree) {
++ printk("Can't preserve ADAM2 memory, "
++ "firstfreeaddress = %08lx.\n", firstfree);
++ preserve_adam2 = 0;
++ } else {
++ printk("Can't preserve ADAM2 memory, "
++ "firstfreeaddress unknown!\n");
++ preserve_adam2 = 0;
++ }
++ }
++
++ if (!preserve_adam2) {
++ for (i = 0; i < boot_mem_map.nr_map; i++) {
++ if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
++ continue;
++
++ addr = boot_mem_map.map[i].addr;
++ while (addr < boot_mem_map.map[i].addr
++ + boot_mem_map.map[i].size) {
++ ClearPageReserved(virt_to_page(__va(addr)));
++ set_page_count(virt_to_page(__va(addr)), 1);
++ free_page((unsigned long)__va(addr));
++ addr += PAGE_SIZE;
++ freed += PAGE_SIZE;
++ }
++ }
++ printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
++ }
++ return freed >> PAGE_SHIFT;
++}
+diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
+--- linux.old/arch/mips/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/misc.c 2005-11-10 01:12:43.946955500 +0100
+@@ -0,0 +1,322 @@
++#include <asm/ar7/sangam.h>
++#include <asm/ar7/avalanche_misc.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++
++#define TRUE 1
++
++static unsigned int avalanche_vbus_freq;
++
++REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
++
++/*****************************************************************************
++ * Reset Control Module.
++ *****************************************************************************/
++void avalanche_reset_ctrl(unsigned int module_reset_bit,
++ AVALANCHE_RESET_CTRL_T reset_ctrl)
++{
++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++
++ if(module_reset_bit >= 32 && module_reset_bit < 64)
++ return;
++
++ if(module_reset_bit >= 64)
++ {
++ if(p_remote_vlynq_dev_reset_ctrl) {
++ p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl);
++ return;
++ }
++ else
++ return;
++ }
++
++ if(reset_ctrl == OUT_OF_RESET)
++ *reset_reg |= 1 << module_reset_bit;
++ else
++ *reset_reg &= ~(1 << module_reset_bit);
++ return;
++}
++
++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
++{
++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++
++ return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
++}
++
++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
++{
++ volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
++ *sw_reset_reg = mode;
++}
++
++#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
++
++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
++{
++ volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
++
++ return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
++}
++
++
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
++#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
++
++
++void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
++{
++ volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++ if (power_ctrl == POWER_CTRL_POWER_DOWN)
++ /* power down the module */
++ *power_reg |= (1 << module_power_bit);
++ else
++ /* power on the module */
++ *power_reg &= (~(1 << module_power_bit));
++}
++
++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
++{
++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++ return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
++}
++
++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
++{
++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++ *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
++ *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
++}
++
++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
++{
++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++ return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
++ >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
++}
++
++/*****************************************************************************
++ * GPIO Control
++ *****************************************************************************/
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_init
++ ***************************************************************************/
++void avalanche_gpio_init(void)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++ spin_lock_irqsave(&closeLock, closeFlag);
++ *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_ctrl
++ ***************************************************************************/
++int avalanche_gpio_ctrl(unsigned int gpio_pin,
++ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
++
++ if(gpio_pin >= 32)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++
++ if(pin_mode == GPIO_PIN)
++ {
++ *gpio_ctrl |= (1 << gpio_pin);
++
++ gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
++
++ if(pin_direction == GPIO_INPUT_PIN)
++ *gpio_ctrl |= (1 << gpio_pin);
++ else
++ *gpio_ctrl &= ~(1 << gpio_pin);
++ }
++ else /* FUNCTIONAL PIN */
++ {
++ *gpio_ctrl &= ~(1 << gpio_pin);
++ }
++
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return (0);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_out
++ ***************************************************************************/
++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
++
++ if(gpio_pin >= 32)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++ if(value == TRUE)
++ *gpio_out |= 1 << gpio_pin;
++ else
++ *gpio_out &= ~(1 << gpio_pin);
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return(0);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_in
++ ***************************************************************************/
++int avalanche_gpio_in_bit(unsigned int gpio_pin)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
++ int ret_val = 0;
++
++ if(gpio_pin >= 32)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++ ret_val = ((*gpio_in) & (1 << gpio_pin));
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return (ret_val);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_out_val
++ ***************************************************************************/
++int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
++ unsigned int reg_index)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
++
++ if(reg_index > 0)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++ *gpio_out &= ~out_mask;
++ *gpio_out |= out_val;
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return(0);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_in_value
++ ***************************************************************************/
++int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
++
++ if(reg_index > 0)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++ *in_val = *gpio_in;
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return (0);
++}
++
++/***********************************************************************
++ *
++ * Wakeup Control Module for TNETV1050 Communication Processor
++ *
++ ***********************************************************************/
++
++#define AVALANCHE_WAKEUP_POLARITY_BIT 16
++
++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
++ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
++ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
++{
++ volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
++
++ /* enable/disable */
++ if (wakeup_ctrl == WAKEUP_ENABLED)
++ /* enable wakeup */
++ *wakeup_status_reg |= wakeup_int;
++ else
++ /* disable wakeup */
++ *wakeup_status_reg &= (~wakeup_int);
++
++ /* set polarity */
++ if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
++ *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
++ else
++ *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
++}
++
++void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
++{
++ avalanche_vbus_freq = new_vbus_freq;
++}
++
++unsigned int avalanche_get_vbus_freq()
++{
++ return(avalanche_vbus_freq);
++}
++
++unsigned int avalanche_get_chip_version_info()
++{
++ return(*(volatile unsigned int*)AVALANCHE_CVR);
++}
++
++SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
++
++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
++{
++ if(p_set_mdix_on_chip_fn)
++ return (p_set_mdix_on_chip_fn(base_addr, operation));
++ else
++ return(-1);
++}
++
++unsigned int avalanche_is_mdix_on_chip(void)
++{
++ return(p_set_mdix_on_chip_fn ? 1:0);
++}
++
++EXPORT_SYMBOL(avalanche_reset_ctrl);
++EXPORT_SYMBOL(avalanche_get_reset_status);
++EXPORT_SYMBOL(avalanche_sys_reset);
++EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
++EXPORT_SYMBOL(avalanche_power_ctrl);
++EXPORT_SYMBOL(avalanche_get_power_status);
++EXPORT_SYMBOL(avalanche_set_global_power_mode);
++EXPORT_SYMBOL(avalanche_get_global_power_mode);
++EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
++EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
++
++EXPORT_SYMBOL(avalanche_gpio_init);
++EXPORT_SYMBOL(avalanche_gpio_ctrl);
++EXPORT_SYMBOL(avalanche_gpio_out_bit);
++EXPORT_SYMBOL(avalanche_gpio_in_bit);
++EXPORT_SYMBOL(avalanche_gpio_out_value);
++EXPORT_SYMBOL(avalanche_gpio_in_value);
++
++EXPORT_SYMBOL(avalanche_set_vbus_freq);
++EXPORT_SYMBOL(avalanche_get_vbus_freq);
++
++EXPORT_SYMBOL(avalanche_get_chip_version_info);
++
+diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
+--- linux.old/arch/mips/ar7/platform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/platform.h 2005-11-10 01:10:45.799571750 +0100
+@@ -0,0 +1,65 @@
++#ifndef _PLATFORM_H_
++#define _PLATFORM_H_
++
++#include <linux/config.h>
++
++
++/* Important: The definition of ENV_SPACE_SIZE should match with that in
++ * PSPBoot. (/psp_boot/inc/psbl/env.h)
++ */
++#ifdef CONFIG_MIPS_AVALANCHE_TICFG
++#define ENV_SPACE_SIZE (10 * 1024)
++#endif
++
++#ifdef CONFIG_MIPS_TNETV1050SDB
++#define TNETV1050SDB
++#define DUAL_FLASH
++#endif
++
++#ifdef CONFIG_MIPS_AR7DB
++#define TNETD73XX_BOARD
++#define AR7DB
++#endif
++
++#ifdef CONFIG_MIPS_AR7RD
++#define TNETD73XX_BOARD
++#define AR7RD
++#endif
++
++#ifdef CONFIG_AR7WRD
++#define TNETD73XX_BOARD
++#define AR7WRD
++#endif
++
++#ifdef CONFIG_MIPS_AR7VWI
++#define TNETD73XX_BOARD
++#define AR7VWi
++#endif
++
++/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
++#ifdef CONFIG_MIPS_AR7VW
++#define TNETD73XX_BOARD
++#define AR7WRD
++#endif
++
++#ifdef CONFIG_MIPS_AR7WI
++#define TNETD73XX_BOARD
++#define AR7Wi
++#endif
++
++#ifdef CONFIG_MIPS_AR7V
++#define TNETD73XX_BOARD
++#define AR7V
++#endif
++
++#ifdef CONFIG_MIPS_AR7V
++#define TNETD73XX_BOARD
++#define AR7V
++#endif
++
++#ifdef CONFIG_MIPS_WA1130
++#define AVALANCHE
++#define WLAN
++#endif
++
++#endif
+diff -urN linux.old/arch/mips/ar7/promlib.c linux.dev/arch/mips/ar7/promlib.c
+--- linux.old/arch/mips/ar7/promlib.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/promlib.c 2005-11-10 01:14:16.372731750 +0100
+@@ -0,0 +1,48 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Putting things on the screen/serial line using Adam2 facilities.
++ */
++
++#include <linux/types.h>
++#include <asm/addrspace.h>
++
++#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR \
++ (AVALANCHE_YAMON_FUNCTION_BASE + 1 * 0x4)
++#define AVALANCHE_YAMON_PROM_EXIT \
++ (AVALANCHE_YAMON_FUNCTION_BASE + 8 * 0x4)
++
++void prom_putchar(char c)
++{
++ static char buf[1];
++ void (*prom_print_str)(unsigned int dummy, char *s, int len) =
++ (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR);
++
++ buf[0] = c;
++ prom_print_str(1, buf, 1);
++ return;
++}
++
++void adam2_exit(int retval)
++{
++ void (*yamon_exit)(int retval) =
++ (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_EXIT);
++
++ yamon_exit(retval);
++ return;
++}
+diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
+--- linux.old/arch/mips/ar7/psp_env.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/psp_env.c 2005-11-10 01:10:45.799571750 +0100
+@@ -0,0 +1,350 @@
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/string.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <asm/io.h>
++
++#include "platform.h"
++
++#define ENV_CELL_SIZE 16
++
++/* control field decode */
++#define ENV_GARBAGE_BIT 0x01 /* Env is garbage if this bit is off */
++#define ENV_DYNAMIC_BIT 0x02 /* Env is dynamic if this bit is off */
++
++#define ENV_CTRL_MASK 0x03
++#define ENV_PREFINED (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
++#define ENV_DYNAMIC (ENV_GARBAGE_BIT)
++
++struct env_variable {
++ unsigned char varNum;
++ unsigned char ctrl;
++ unsigned short chksum;
++ unsigned char numCells;
++ unsigned char data[ENV_CELL_SIZE - 5]; /* The data section starts
++ * here, continues for
++ * numCells.
++ */
++};
++
++extern unsigned int max_env_entry;
++
++/* Internal macros */
++#define get_next_block(var) ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
++
++typedef enum ENV_VARS {
++ env_vars_start = 0,
++ CPUFREQ,
++ MEMSZ,
++ FLASHSZ,
++ MODETTY0,
++ MODETTY1,
++ PROMPT,
++ BOOTCFG,
++ HWA_0,
++#if !defined (AVALANCHE) || defined(TNETC401B)
++ HWA_1,
++#endif
++#if !defined(TNETV1020_BOARD)
++ HWA_RNDIS,
++#endif
++#if defined (TNETD73XX_BOARD)
++ HWA_3,
++#endif
++ IPA,
++ IPA_SVR,
++ BLINE_MAC0,
++#if !defined (AVALANCHE) || defined(TNETC401B)
++ BLINE_MAC1,
++#endif
++#if !defined(TNETV1020_BOARD)
++ BLINE_RNDIS,
++#endif
++#if defined (TNETD73XX_BOARD)
++ BLINE_ATM,
++#endif
++#if !defined(TNETV1020_BOARD)
++ USB_PID,
++ USB_VID,
++ USB_EPPOLLI,
++#endif
++ IPA_GATEWAY,
++ SUBNET_MASK,
++#if defined (TNETV1050_BOARD)
++ BLINE_ESWITCH,
++#endif
++#if !defined(TNETV1020_BOARD)
++ USB_SERIAL,
++ HWA_HRNDIS, /* Host (PC) side RNDIS address */
++#endif
++ REMOTE_USER,
++ REMOTE_PASS,
++ REMOTE_DIR,
++ SYSFREQ,
++ LINK_TIMEOUT,
++#ifndef AVALANCHE /* Avalanche boards use only one mac port */
++ MAC_PORT,
++#endif
++ PATH,
++ HOSTNAME,
++#ifdef WLAN
++ HW_REV_MAJOR,
++ HW_REV_MINOR,
++ HW_PATCH,
++ SW_PATCH,
++ SERIAL_NUMBER,
++#endif
++ TFTPCFG,
++#if defined (TNETV1050_BOARD)
++ HWA_ESWITCH,
++#endif
++ /*
++ * Add new env variables here.
++ * NOTE: New environment variables should always be placed at the end, ie
++ * just before env_vars_end.
++ */
++
++ env_vars_end
++} ENV_VARS;
++
++
++struct env_description {
++ ENV_VARS idx;
++ char *nm;
++ char *alias;
++};
++
++#define ENVSTR(x) #x
++#define _ENV_ENTRY(x) {.idx = x, .nm = ENVSTR(x), .alias = NULL}
++
++struct env_description env_ns[] = {
++ _ENV_ENTRY(env_vars_start), /* start. */
++ _ENV_ENTRY(CPUFREQ),
++ _ENV_ENTRY(MEMSZ),
++ _ENV_ENTRY(FLASHSZ),
++ _ENV_ENTRY(MODETTY0),
++ _ENV_ENTRY(MODETTY1),
++ _ENV_ENTRY(PROMPT),
++ _ENV_ENTRY(BOOTCFG),
++ _ENV_ENTRY(HWA_0),
++#if !defined (AVALANCHE) || defined(TNETC401B)
++ _ENV_ENTRY(HWA_1),
++#endif
++#if !defined(TNETV1020_BOARD)
++ _ENV_ENTRY(HWA_RNDIS),
++#endif
++#if defined (TNETD73XX_BOARD)
++ _ENV_ENTRY(HWA_3),
++#endif
++ _ENV_ENTRY(IPA),
++ _ENV_ENTRY(IPA_SVR),
++ _ENV_ENTRY(IPA_GATEWAY),
++ _ENV_ENTRY(SUBNET_MASK),
++ _ENV_ENTRY(BLINE_MAC0),
++#if !defined (AVALANCHE) || defined(TNETC401B)
++ _ENV_ENTRY(BLINE_MAC1),
++#endif
++#if !defined(TNETV1020_BOARD)
++ _ENV_ENTRY(BLINE_RNDIS),
++#endif
++#if defined (TNETD73XX_BOARD)
++ _ENV_ENTRY(BLINE_ATM),
++#endif
++#if !defined(TNETV1020_BOARD)
++ _ENV_ENTRY(USB_PID),
++ _ENV_ENTRY(USB_VID),
++ _ENV_ENTRY(USB_EPPOLLI),
++#endif
++#if defined (TNETV1050_BOARD)
++ _ENV_ENTRY(BLINE_ESWITCH),
++#endif
++#if !defined(TNETV1020_BOARD)
++ _ENV_ENTRY(USB_SERIAL),
++ _ENV_ENTRY(HWA_HRNDIS),
++#endif
++ _ENV_ENTRY(REMOTE_USER),
++ _ENV_ENTRY(REMOTE_PASS),
++ _ENV_ENTRY(REMOTE_DIR),
++ _ENV_ENTRY(SYSFREQ),
++ _ENV_ENTRY(LINK_TIMEOUT),
++#ifndef AVALANCHE /* Avalanche boards use only one mac port */
++ _ENV_ENTRY(MAC_PORT),
++#endif
++ _ENV_ENTRY(PATH),
++ _ENV_ENTRY(HOSTNAME),
++#ifdef WLAN
++ _ENV_ENTRY(HW_REV_MAJOR),
++ _ENV_ENTRY(HW_REV_MINOR),
++ _ENV_ENTRY(HW_PATCH),
++ _ENV_ENTRY(SW_PATCH),
++ _ENV_ENTRY(SERIAL_NUMBER),
++#endif
++ _ENV_ENTRY(TFTPCFG),
++#if defined (TNETV1050_BOARD)
++ _ENV_ENTRY(HWA_ESWITCH),
++#endif
++ /*
++ * Add new entries below this.
++ */
++ /* Adam2 environment name alias. */
++ { .idx = IPA, .nm = "my_ipaddress" },
++ { .idx = CPUFREQ, .nm = "cpufrequency" },
++ { .idx = SYSFREQ, .nm = "sysfrequency" },
++ { .idx = HWA_0, .nm = "maca" },
++#ifndef AVALANCHE
++ { .idx = HWA_1, .nm = "macb" },
++#endif
++ { .idx = MODETTY0, .nm = "modetty0" },
++ { .idx = MODETTY1, .nm = "modetty1" },
++ { .idx = MEMSZ, .nm = "memsize" },
++
++ _ENV_ENTRY(env_vars_end) /* delimiter. */
++};
++
++static inline int var_to_idx(const char* var)
++{
++ int ii;
++
++ /* go over the list of pre-defined environment variables */
++ for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
++ /* check if the env variable is listed */
++ if (strcmp(env_ns[ii].nm, var) == 0) {
++ return env_ns[ii].idx;
++ }
++
++ /* if an alias is present, check if the alias matches
++ * the description
++ */
++ if (env_ns[ii].alias != NULL) {
++ if (strcmp(env_ns[ii].alias, var) == 0) {
++ return env_ns[ii].idx;
++ }
++ }
++ }
++ return 0;
++}
++
++extern int *_prom_envp;
++
++/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
++ * the next read some seconds later is ok. It looks like something is hidding or
++ * overlay the flash address at 0xb0000000. Is this possible?
++ *
++ * The readb() and while() usage below is a attempt of a workarround - with limited success.
++ */
++
++static inline struct env_variable* get_var_by_number(int index)
++{
++ struct env_variable *env_var = (struct env_variable *)_prom_envp;
++ volatile unsigned char nr;
++ int i;
++
++ env_var++; /* skip signature */
++
++ i = 0;
++ nr = readb(&(env_var->varNum));
++
++ while (i < max_env_entry && nr != 0xFF) {
++ if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
++ if (nr == index) {
++ return env_var;
++ }
++ }
++ i++;
++ env_var = get_next_block(env_var);
++ nr = readb(&(env_var->varNum));
++ }
++
++ return NULL;
++}
++
++static inline struct env_variable* get_var_by_name(char *var)
++{
++ struct env_variable *env_var = (struct env_variable *)_prom_envp;
++ volatile unsigned char nr;
++ int i;
++
++ env_var++; /* skip signature */
++
++ nr = readb(&(env_var->varNum));
++ i = 0;
++
++ while (i < max_env_entry && nr != 0xFF) {
++ if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
++ if (strcmp(var, env_var->data) == 0)
++ return env_var;
++ }
++ i++;
++ env_var = get_next_block(env_var);
++ nr = readb(&(env_var->varNum));
++ }
++ return NULL;
++}
++
++static inline struct env_variable* get_var(char *var)
++{
++ int index = var_to_idx(var);
++
++ if (index)
++ return get_var_by_number(index);
++ else
++ return get_var_by_name(var);
++
++ return NULL;
++}
++
++static inline char *get_value(struct env_variable* env_var)
++{
++ unsigned char *name;
++ unsigned char *value;
++ unsigned short chksum;
++ int i;
++
++ chksum = env_var->varNum + env_var->ctrl + env_var->numCells;
++
++ if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
++ name = env_var->data;
++ value = env_var->data + strlen(name) + 1;
++
++ for(i = 0; i < strlen(name); i++)
++ chksum += name[i];
++ } else
++ value = env_var->data;
++
++ for (i = 0; i < strlen(value); i++)
++ chksum += value[i];
++
++ chksum += env_var->chksum;
++ chksum = ~(chksum);
++
++ if(chksum != 0) {
++ return NULL;
++ }
++
++ return value;
++}
++
++struct psbl_rec {
++ unsigned int psbl_size;
++ unsigned int env_base;
++ unsigned int env_size;
++ unsigned int ffs_base;
++ unsigned int ffs_size;
++};
++
++char *prom_psp_getenv(char *envname)
++{
++ struct env_variable* env_var;
++ char *value;
++
++ if (strcmp("bootloader", envname) == 0)
++ return "PSPBoot";
++
++ if (!(env_var = get_var(envname)))
++ return NULL;
++
++ value = get_value(env_var);
++
++ return value;
++}
+diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
+--- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/reset.c 2005-11-10 01:14:16.372731750 +0100
+@@ -0,0 +1,98 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Reset the AR7 boards.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/types.h>
++
++#include <asm/mipsregs.h>
++#include <asm/reboot.h>
++#include <asm/addrspace.h>
++
++int preserve_adam2 = 1;
++
++extern void adam2_exit(int retval);
++
++static void ar7_machine_restart(char *command);
++static void ar7_machine_halt(void);
++static void ar7_machine_power_off(void);
++
++static void ar7_machine_restart(char *command)
++{
++ volatile uint32_t *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
++
++ *softres_reg = 1;
++}
++
++static void ar7_machine_halt(void)
++{
++
++ if (preserve_adam2) {
++ set_c0_status(ST0_BEV);
++ adam2_exit(0);
++ } else {
++ /* I'd like to have Alt-SysRq-b work in this state.
++ * What's missing here? The timer interrupt is still running.
++ * Why doesn't the UART work anymore? */
++ while(1) {
++ __asm__(".set\tmips3\n\t"
++ "wait\n\t"
++ ".set\tmips0");
++ }
++ }
++}
++
++static void ar7_machine_power_off(void)
++{
++ volatile uint32_t *power_reg = (void *)(KSEG1ADDR(0x08610A00));
++ uint32_t power_state = *power_reg;
++
++ /* add something to turn LEDs off? */
++
++ power_state &= ~(3 << 30);
++ power_state |= (3 << 30); /* power down */
++ *power_reg = power_state;
++
++ printk("after power down?\n");
++}
++
++void ar7_reboot_setup(void)
++{
++ _machine_restart = ar7_machine_restart;
++ _machine_halt = ar7_machine_halt;
++ _machine_power_off = ar7_machine_power_off;
++}
++
++static int __init ar7_do_preserve_adam2(char *s)
++{
++ if (!strcmp(s, "no") || !strcmp(s, "0"))
++ preserve_adam2 = 0;
++ else
++ preserve_adam2 = 1;
++ return 1;
++}
++
++__setup("adam2=", ar7_do_preserve_adam2);
+diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
+--- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/setup.c 2005-11-10 01:12:43.946955500 +0100
+@@ -0,0 +1,143 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ */
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/string.h>
++#include <linux/irq.h>
++
++#include <asm/processor.h>
++#include <asm/irq.h>
++#include <asm/irq_cpu.h>
++#include <asm/time.h>
++#include <asm/mipsregs.h>
++#include <asm/mips-boards/prom.h>
++
++#ifdef CONFIG_KGDB
++extern void rs_kgdb_hook(int);
++extern void breakpoint(void);
++int remote_debug = 0;
++#endif
++
++extern void ar7_reboot_setup(void);
++extern void ar7_irq_init(int);
++extern asmlinkage void ar7IRQ(void);
++
++void ar7_time_init(void)
++{
++ /* XXX runtime */
++ mips_hpt_frequency = CONFIG_AR7_CPU * 500000;
++}
++
++void ar7_timer_setup(struct irqaction *irq)
++{
++ setup_irq(7, irq);
++ set_c0_status(IE_IRQ5);
++}
++
++void __init init_IRQ(void)
++{
++ init_generic_irq();
++ mips_cpu_irq_init(0);
++ ar7_irq_init(8);
++
++ /* Now safe to set the exception vector. */
++ set_except_vector(0, ar7IRQ);
++
++#ifdef CONFIG_KGDB
++ if (remote_debug)
++ {
++ set_debug_traps();
++ breakpoint();
++ }
++#endif
++}
++
++const char *get_system_type(void)
++{
++ return "Texas Instruments AR7";
++}
++
++void __init ar7_setup(void)
++{
++#ifdef CONFIG_KGDB
++ int rs_putDebugChar(char);
++ char rs_getDebugChar(void);
++ extern int (*generic_putDebugChar)(char);
++ extern char (*generic_getDebugChar)(void);
++#endif
++ char *argptr;
++#ifdef CONFIG_SERIAL_CONSOLE
++ argptr = prom_getcmdline();
++ if ((argptr = strstr(argptr, "console=")) == NULL) {
++ char console[20];
++ char *s;
++ int i = 0;
++
++ s = prom_getenv("modetty0");
++ strcpy(console, "38400");
++
++ if (s != NULL) {
++ while (s[i] >= '0' && s[i] <= '9')
++ i++;
++
++ if (i > 0) {
++ strncpy(console, s, i);
++ console[i] = 0;
++ }
++ }
++
++ argptr = prom_getcmdline();
++ strcat(argptr, " console=ttyS0,");
++ strcat(argptr, console);
++ }
++#endif
++
++#ifdef CONFIG_KGDB
++ argptr = prom_getcmdline();
++ if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
++ int line;
++ argptr += strlen("kgdb=ttyS");
++ if (*argptr != '0' && *argptr != '1')
++ printk("KGDB: Uknown serial line /dev/ttyS%c, "
++ "falling back to /dev/ttyS1\n", *argptr);
++ line = *argptr == '0' ? 0 : 1;
++ printk("KGDB: Using serial line /dev/ttyS%d for session\n",
++ line ? 1 : 0);
++
++ rs_kgdb_hook(line);
++ generic_putDebugChar = rs_putDebugChar;
++ generic_getDebugChar = rs_getDebugChar;
++
++ prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
++ "please connect your debugger\n", line ? 1 : 0);
++
++ remote_debug = 1;
++ /* Breakpoints are in init_IRQ() */
++ }
++#endif
++
++ argptr = prom_getcmdline();
++ if ((argptr = strstr(argptr, "nofpu")) != NULL)
++ cpu_data[0].options &= ~MIPS_CPU_FPU;
++
++ ar7_reboot_setup();
++
++ board_time_init = ar7_time_init;
++ board_timer_setup = ar7_timer_setup;
++}
+diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
+--- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-11-10 01:12:43.946955500 +0100
+@@ -0,0 +1,921 @@
++/******************************************************************************
++ * FILE PURPOSE: TNETD73xx Misc modules API Source
++ ******************************************************************************
++ * FILE NAME: tnetd73xx_misc.c
++ *
++ * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
++ * FSER Modules API
++ * As per TNETD73xx specifications
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - Sharath Kumar PSP TII
++ * 14 Feb 03 - Anant Gole PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++#include <linux/types.h>
++#include <asm/ar7/tnetd73xx.h>
++#include <asm/ar7/tnetd73xx_misc.h>
++
++/* TNETD73XX Revision */
++u32 tnetd73xx_get_revision(void)
++{
++ /* Read Chip revision register - This register is from GPIO module */
++ return ( (u32) REG32_DATA(TNETD73XX_CVR));
++}
++
++/*****************************************************************************
++ * Reset Control Module
++ *****************************************************************************/
++
++
++void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
++{
++ u32 reset_status;
++
++ /* read current reset register */
++ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
++
++ if (reset_ctrl == OUT_OF_RESET)
++ {
++ /* bring module out of reset */
++ reset_status |= (1 << reset_module);
++ }
++ else
++ {
++ /* put module in reset */
++ reset_status &= (~(1 << reset_module));
++ }
++
++ /* write to the reset register */
++ REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
++}
++
++
++TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
++{
++ u32 reset_status;
++
++ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
++ return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
++}
++
++void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
++{
++ REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
++}
++
++#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
++
++TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
++{
++ u32 sys_reset_status;
++
++ REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
++
++ return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
++}
++
++
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
++#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
++
++
++void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
++{
++ u32 power_status;
++
++ /* read current power down control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++
++ if (power_ctrl == POWER_CTRL_POWER_DOWN)
++ {
++ /* power down the module */
++ power_status |= (1 << power_module);
++ }
++ else
++ {
++ /* power on the module */
++ power_status &= (~(1 << power_module));
++ }
++
++ /* write to the reset register */
++ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
++}
++
++TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
++{
++ u32 power_status;
++
++ /* read current power down control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++
++ return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
++}
++
++void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
++{
++ u32 power_status;
++
++ /* read current power down control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++
++ power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
++ power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
++
++ /* write to power down control register */
++ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
++}
++
++TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
++{
++ u32 power_status;
++
++ /* read current power down control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++
++ power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
++ power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
++
++ return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
++}
++
++
++/*****************************************************************************
++ * Wakeup Control
++ *****************************************************************************/
++
++#define TNETD73XX_WAKEUP_POLARITY_BIT 16
++
++void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
++ TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
++ TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
++{
++ u32 wakeup_status;
++
++ /* read the wakeup control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
++
++ /* enable/disable */
++ if (wakeup_ctrl == WAKEUP_ENABLED)
++ {
++ /* enable wakeup */
++ wakeup_status |= wakeup_int;
++ }
++ else
++ {
++ /* disable wakeup */
++ wakeup_status &= (~wakeup_int);
++ }
++
++ /* set polarity */
++ if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
++ {
++ wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
++ }
++ else
++ {
++ wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
++ }
++
++ /* write the wakeup control register */
++ REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
++}
++
++
++/*****************************************************************************
++ * FSER Control
++ *****************************************************************************/
++
++void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
++{
++ REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
++}
++
++/*****************************************************************************
++ * Clock Control
++ *****************************************************************************/
++
++#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
++#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
++#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
++#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
++
++#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
++#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
++
++#define CLKC_PRE_DIVIDER 0x0000001F
++#define CLKC_POST_DIVIDER 0x001F0000
++
++#define CLKC_PLL_STATUS 0x1
++#define CLKC_PLL_FACTOR 0x0000F000
++
++#define BOOTCR_PLL_BYPASS (1 << 5)
++#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
++
++#define MIPS_PLL_SELECT 0x00030000
++#define SYSTEM_PLL_SELECT 0x0000C000
++#define USB_PLL_SELECT 0x000C0000
++#define ADSLSS_PLL_SELECT 0x00C00000
++
++#define MIPS_AFECLKI_SELECT 0x00000000
++#define MIPS_REFCLKI_SELECT 0x00010000
++#define MIPS_XTAL3IN_SELECT 0x00020000
++
++#define SYSTEM_AFECLKI_SELECT 0x00000000
++#define SYSTEM_REFCLKI_SELECT 0x00004000
++#define SYSTEM_XTAL3IN_SELECT 0x00008000
++#define SYSTEM_MIPSPLL_SELECT 0x0000C000
++
++#define USB_SYSPLL_SELECT 0x00000000
++#define USB_REFCLKI_SELECT 0x00040000
++#define USB_XTAL3IN_SELECT 0x00080000
++#define USB_MIPSPLL_SELECT 0x000C0000
++
++#define ADSLSS_AFECLKI_SELECT 0x00000000
++#define ADSLSS_REFCLKI_SELECT 0x00400000
++#define ADSLSS_XTAL3IN_SELECT 0x00800000
++#define ADSLSS_MIPSPLL_SELECT 0x00C00000
++
++#define SYS_MAX CLK_MHZ(150)
++#define SYS_MIN CLK_MHZ(1)
++
++#define MIPS_SYNC_MAX SYS_MAX
++#define MIPS_ASYNC_MAX CLK_MHZ(160)
++#define MIPS_MIN CLK_MHZ(1)
++
++#define USB_MAX CLK_MHZ(100)
++#define USB_MIN CLK_MHZ(1)
++
++#define ADSL_MAX CLK_MHZ(180)
++#define ADSL_MIN CLK_MHZ(1)
++
++#define PLL_MUL_MAXFACTOR 15
++#define MAX_DIV_VALUE 32
++#define MIN_DIV_VALUE 1
++
++#define MIN_PLL_INP_FREQ CLK_MHZ(8)
++#define MAX_PLL_INP_FREQ CLK_MHZ(100)
++
++#define DIVIDER_LOCK_TIME 10100
++#define PLL_LOCK_TIME 10100 * 75
++
++
++
++ /****************************************************************************
++ * DATA PURPOSE: PRIVATE Variables
++ **************************************************************************/
++ static u32 *clk_src[4];
++ static u32 mips_pll_out;
++ static u32 sys_pll_out;
++ static u32 afeclk_inp;
++ static u32 refclk_inp;
++ static u32 xtal_inp;
++ static u32 present_min;
++ static u32 present_max;
++
++ /* Forward References */
++ static u32 find_gcd(u32 min, u32 max);
++ static u32 compute_prediv( u32 divider, u32 min, u32 max);
++ static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
++ static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
++ static void find_approx(u32 *,u32 *,u32);
++
++ /****************************************************************************
++ * FUNCTION: tnetd73xx_clkc_init
++ ****************************************************************************
++ * Description: The routine initializes the internal variables depending on
++ * on the sources selected for different clocks.
++ ***************************************************************************/
++void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
++{
++
++ u32 choice;
++
++ afeclk_inp = afeclk;
++ refclk_inp = refclk;
++ xtal_inp = xtal3in;
++
++ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
++ switch(choice)
++ {
++ case MIPS_AFECLKI_SELECT:
++ clk_src[CLKC_MIPS] = &afeclk_inp;
++ break;
++
++ case MIPS_REFCLKI_SELECT:
++ clk_src[CLKC_MIPS] = &refclk_inp;
++ break;
++
++ case MIPS_XTAL3IN_SELECT:
++ clk_src[CLKC_MIPS] = &xtal_inp;
++ break;
++
++ default :
++ clk_src[CLKC_MIPS] = 0;
++
++ }
++
++ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
++ switch(choice)
++ {
++ case SYSTEM_AFECLKI_SELECT:
++ clk_src[CLKC_SYS] = &afeclk_inp;
++ break;
++
++ case SYSTEM_REFCLKI_SELECT:
++ clk_src[CLKC_SYS] = &refclk_inp;
++ break;
++
++ case SYSTEM_XTAL3IN_SELECT:
++ clk_src[CLKC_SYS] = &xtal_inp;
++ break;
++
++ case SYSTEM_MIPSPLL_SELECT:
++ clk_src[CLKC_SYS] = &mips_pll_out;
++ break;
++
++ default :
++ clk_src[CLKC_SYS] = 0;
++
++ }
++
++
++ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
++ switch(choice)
++ {
++ case ADSLSS_AFECLKI_SELECT:
++ clk_src[CLKC_ADSLSS] = &afeclk_inp;
++ break;
++
++ case ADSLSS_REFCLKI_SELECT:
++ clk_src[CLKC_ADSLSS] = &refclk_inp;
++ break;
++
++ case ADSLSS_XTAL3IN_SELECT:
++ clk_src[CLKC_ADSLSS] = &xtal_inp;
++ break;
++
++ case ADSLSS_MIPSPLL_SELECT:
++ clk_src[CLKC_ADSLSS] = &mips_pll_out;
++ break;
++
++ default :
++ clk_src[CLKC_ADSLSS] = 0;
++
++ }
++
++
++ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
++ switch(choice)
++ {
++ case USB_SYSPLL_SELECT:
++ clk_src[CLKC_USB] = &sys_pll_out ;
++ break;
++
++ case USB_REFCLKI_SELECT:
++ clk_src[CLKC_USB] = &refclk_inp;
++ break;
++
++ case USB_XTAL3IN_SELECT:
++ clk_src[CLKC_USB] = &xtal_inp;
++ break;
++
++ case USB_MIPSPLL_SELECT:
++ clk_src[CLKC_USB] = &mips_pll_out;
++ break;
++
++ default :
++ clk_src[CLKC_USB] = 0;
++
++ }
++}
++
++
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_clkc_set_freq
++ ****************************************************************************
++ * Description: The above routine is called to set the output_frequency of the
++ * selected clock(using clk_id) to the required value given
++ * by the variable output_freq.
++ ***************************************************************************/
++TNETD73XX_ERR tnetd73xx_clkc_set_freq
++(
++ TNETD73XX_CLKC_ID_T clk_id,
++ u32 output_freq
++ )
++{
++ u32 base_freq;
++ u32 multiplier;
++ u32 divider;
++ u32 min_prediv;
++ u32 max_prediv;
++ u32 prediv;
++ u32 postdiv;
++ u32 temp;
++
++ /* check if PLLs are bypassed*/
++ if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++ /*check if the requested output_frequency is in valid range*/
++ switch( clk_id )
++ {
++ case CLKC_SYS:
++ if( output_freq < SYS_MIN || output_freq > SYS_MAX)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++ present_min = SYS_MIN;
++ present_max = SYS_MAX;
++ break;
++
++ case CLKC_MIPS:
++ if((output_freq < MIPS_MIN) ||
++ (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++ present_min = MIPS_MIN;
++ present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
++ break;
++
++ case CLKC_USB:
++ if( output_freq < USB_MIN || output_freq > USB_MAX)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++ present_min = USB_MIN;
++ present_max = USB_MAX;
++ break;
++
++ case CLKC_ADSLSS:
++ if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++ present_min = ADSL_MIN;
++ present_max = ADSL_MAX;
++ break;
++ }
++
++
++ base_freq = get_base_frequency(clk_id);
++
++
++ /* check for minimum base frequency value */
++ if( base_freq < MIN_PLL_INP_FREQ)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++ get_val(output_freq, base_freq, &multiplier, &divider);
++
++ /* check multiplier range */
++ if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++ /* check divider value */
++ if( divider == 0 )
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++ /*compute minimum and maximum predivider values */
++ min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
++ max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
++
++ /*adjust the value of divider so that it not less than minimum predivider value*/
++ if (divider < min_prediv)
++ {
++ temp = CEIL(min_prediv, divider);
++ if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
++ {
++ return TNETD73XX_ERR_ERROR ;
++ }
++ else
++ {
++ multiplier = temp * multiplier;
++ divider = min_prediv;
++ }
++
++ }
++
++ /* compute predivider and postdivider values */
++ prediv = compute_prediv (divider, min_prediv, max_prediv);
++ postdiv = CEIL(divider,prediv);
++
++ /*return fail if postdivider value falls out of range */
++ if(postdiv > MAX_DIV_VALUE)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++
++ /*write predivider and postdivider values*/
++ /* pre-Divider and post-divider are 5 bit N+1 dividers */
++ REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
++
++ /*wait for divider output to stabilise*/
++ for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
++
++ /*write to PLL clock register*/
++
++ if(clk_id == CLKC_SYS)
++ {
++ /* but before writing put DRAM to hold mode */
++ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
++ }
++ /*Bring PLL into div mode */
++ REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
++
++ /*compute the word to be written to PLLCR
++ *corresponding to multiplier value
++ */
++ multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
++
++ /* wait till PLL enters div mode */
++ while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
++ /*nothing*/;
++
++ REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
++
++ while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
++ /*nothing*/;
++
++
++ /*wait for External pll to lock*/
++ for(temp =0; temp < PLL_LOCK_TIME; temp++);
++
++ if(clk_id == CLKC_SYS)
++ {
++ /* Bring DRAM out of hold */
++ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
++ }
++
++ return TNETD73XX_ERR_OK ;
++}
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_clkc_get_freq
++ ****************************************************************************
++ * Description: The above routine is called to get the output_frequency of the
++ * selected clock( clk_id)
++ ***************************************************************************/
++u32 tnetd73xx_clkc_get_freq
++(
++ TNETD73XX_CLKC_ID_T clk_id
++ )
++{
++
++ u32 clk_ctrl_register;
++ u32 clk_pll_setting;
++ u32 clk_predivider;
++ u32 clk_postdivider;
++ u16 pll_factor;
++ u32 base_freq;
++ u32 divider;
++
++ base_freq = get_base_frequency(clk_id);
++
++ clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
++
++ /* pre-Divider and post-divider are 5 bit N+1 dividers */
++ clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
++ clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
++
++ divider = clk_predivider * clk_postdivider;
++
++
++ if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
++ {
++ return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
++ }
++
++
++ else
++ {
++ /* return the current clock speed based upon the PLL setting */
++ clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
++
++ /* Get the PLL multiplication factor */
++ pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
++
++ /* Check if we're in divide mode or multiply mode */
++ if((clk_pll_setting & 0x1) == 0)
++ {
++ /* We're in divide mode */
++ if(pll_factor < 0x10)
++ return (CEIL(base_freq >> 1, divider));
++ else
++ return (CEIL(base_freq >> 2, divider));
++ }
++
++ else /* We're in PLL mode */
++ {
++ /* See if PLLNDIV & PLLDIV are set */
++ if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
++ {
++ if(clk_pll_setting & 0x1000)
++ {
++ /* clk = base_freq * k/2 */
++ return(CEIL((base_freq * pll_factor) >> 1, divider));
++ }
++ else
++ {
++ /* clk = base_freq * (k-1) / 4)*/
++ return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
++ }
++ }
++ else
++ {
++ if(pll_factor < 0x10)
++ {
++ /* clk = base_freq * k */
++ return(CEIL(base_freq * pll_factor, divider));
++ }
++
++ else
++ {
++ /* clk = base_freq */
++ return(CEIL(base_freq, divider));
++ }
++ }
++ }
++ return(0); /* Should never reach here */
++
++ }
++
++}
++
++
++/* local helper functions */
++
++/****************************************************************************
++ * FUNCTION: get_base_frequency
++ ****************************************************************************
++ * Description: The above routine is called to get base frequency of the clocks.
++ ***************************************************************************/
++
++static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
++{
++ /* update the current MIPs PLL output value, if the required
++ * source is MIPS PLL
++ */
++ if ( clk_src[clk_id] == &mips_pll_out)
++ {
++ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
++ }
++
++
++ /* update the current System PLL output value, if the required
++ * source is system PLL
++ */
++ if ( clk_src[clk_id] == &sys_pll_out)
++ {
++ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
++ }
++
++ return (*clk_src[clk_id]);
++
++}
++
++
++
++/****************************************************************************
++ * FUNCTION: find_gcd
++ ****************************************************************************
++ * Description: The above routine is called to find gcd of 2 numbers.
++ ***************************************************************************/
++static u32 find_gcd
++(
++ u32 min,
++ u32 max
++ )
++{
++ if (max % min == 0)
++ {
++ return min;
++ }
++ else
++ {
++ return find_gcd(max % min, min);
++ }
++}
++
++/****************************************************************************
++ * FUNCTION: compute_prediv
++ ****************************************************************************
++ * Description: The above routine is called to compute predivider value
++ ***************************************************************************/
++static u32 compute_prediv(u32 divider, u32 min, u32 max)
++{
++ u16 prediv;
++
++ /* return the divider itself it it falls within the range of predivider*/
++ if (min <= divider && divider <= max)
++ {
++ return divider;
++ }
++
++ /* find a value for prediv such that it is a factor of divider */
++ for (prediv = max; prediv >= min ; prediv--)
++ {
++ if ( (divider % prediv) == 0 )
++ {
++ return prediv;
++ }
++ }
++
++ /* No such factor exists, return min as prediv */
++ return min;
++}
++
++/****************************************************************************
++ * FUNCTION: get_val
++ ****************************************************************************
++ * Description: This routine is called to get values of divider and multiplier.
++ ***************************************************************************/
++
++static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
++{
++ u32 temp_mul;
++ u32 temp_div;
++ u32 gcd;
++ u32 min_freq;
++ u32 max_freq;
++
++ /* find gcd of base_freq, output_freq */
++ min_freq = (base_freq < output_freq) ? base_freq : output_freq;
++ max_freq = (base_freq > output_freq) ? base_freq : output_freq;
++ gcd = find_gcd(min_freq , max_freq);
++
++ if(gcd == 0)
++ return; /* ERROR */
++
++ /* compute values of multiplier and divider */
++ temp_mul = output_freq / gcd;
++ temp_div = base_freq / gcd;
++
++
++ /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
++ if( temp_mul > PLL_MUL_MAXFACTOR )
++ {
++ if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
++ return;
++
++ find_approx(&temp_mul,&temp_div,base_freq);
++ }
++
++ *multiplier = temp_mul;
++ *divider = temp_div;
++}
++
++/****************************************************************************
++ * FUNCTION: find_approx
++ ****************************************************************************
++ * Description: This function gets the approx value of num/denom.
++ ***************************************************************************/
++
++static void find_approx(u32 *num,u32 *denom,u32 base_freq)
++{
++ u32 num1;
++ u32 denom1;
++ u32 num2;
++ u32 denom2;
++ int32_t closest;
++ int32_t prev_closest;
++ u32 temp_num;
++ u32 temp_denom;
++ u32 normalize;
++ u32 gcd;
++ u32 output_freq;
++
++ num1 = *num;
++ denom1 = *denom;
++
++ prev_closest = 0x7fffffff; /* maximum possible value */
++ num2 = num1;
++ denom2 = denom1;
++
++ /* start with max */
++ for(temp_num = 15; temp_num >=1; temp_num--)
++ {
++
++ temp_denom = CEIL(temp_num * denom1, num1);
++ output_freq = (temp_num * base_freq) / temp_denom;
++
++ if(temp_denom < 1)
++ {
++ break;
++ }
++ else
++ {
++ normalize = CEIL(num1,temp_num);
++ closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
++ if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
++ {
++ prev_closest = closest;
++ num2 = temp_num;
++ denom2 = temp_denom;
++ }
++
++ }
++
++ }
++
++ gcd = find_gcd(num2,denom2);
++ num2 = num2 / gcd;
++ denom2 = denom2 /gcd;
++
++ *num = num2;
++ *denom = denom2;
++}
++
++
++/*****************************************************************************
++ * GPIO Control
++ *****************************************************************************/
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_init
++ ***************************************************************************/
++void tnetd73xx_gpio_init()
++{
++ /* Bring module out of reset */
++ tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
++ REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
++}
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_ctrl
++ ***************************************************************************/
++void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
++ TNETD73XX_GPIO_PIN_MODE_T pin_mode,
++ TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
++{
++ u32 pin_status;
++ REG32_READ(TNETD73XX_GPIOENR, pin_status);
++ if (pin_mode == GPIO_PIN)
++ {
++ pin_status |= (1 << gpio_pin);
++ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
++
++ /* Set pin direction */
++ REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
++ if (pin_direction == GPIO_INPUT_PIN)
++ {
++ pin_status |= (1 << gpio_pin);
++ }
++ else /* GPIO_OUTPUT_PIN */
++ {
++ pin_status &= (~(1 << gpio_pin));
++ }
++ REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
++ }
++ else /* FUNCTIONAL PIN */
++ {
++ pin_status &= (~(1 << gpio_pin));
++ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
++ }
++
++}
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_out
++ ***************************************************************************/
++void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
++{
++ u32 pin_value;
++
++ REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
++ if (value == 1)
++ {
++ pin_value |= (1 << gpio_pin);
++ }
++ else
++ {
++ pin_value &= (~(1 << gpio_pin));
++ }
++ REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
++}
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_in
++ ***************************************************************************/
++int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
++{
++ u32 pin_value;
++ REG32_READ(TNETD73XX_GPIODINR, pin_value);
++ return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
++}
++
+diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
+--- linux.old/arch/mips/config-shared.in 2005-10-21 16:43:18.917114000 +0200
++++ linux.dev/arch/mips/config-shared.in 2005-11-10 01:12:43.950955750 +0100
+@@ -20,6 +20,16 @@
+ mainmenu_option next_comment
+ comment 'Machine selection'
+ dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
++dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
++if [ "$CONFIG_AR7" = "y" ]; then
++ choice 'Texas Instruments Reference Platform' \
++ "AR7DB CONFIG_AR7DB \
++ AR7RD CONFIG_AR7RD \
++ AR7WRD CONFIG_AR7WRD" AR7DB
++ int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
++ int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
++ hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
++fi
+ dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
+ dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
+ dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
+@@ -239,6 +249,11 @@
+ define_bool CONFIG_NONCOHERENT_IO y
+ define_bool CONFIG_PC_KEYB y
+ fi
++if [ "$CONFIG_AR7" = "y" ]; then
++ define_bool CONFIG_IRQ_CPU y
++ define_bool CONFIG_NONCOHERENT_IO y
++ define_bool CONFIG_SWAP_IO_SPACE y
++fi
+ if [ "$CONFIG_CASIO_E55" = "y" ]; then
+ define_bool CONFIG_IRQ_CPU y
+ define_bool CONFIG_NONCOHERENT_IO y
+@@ -736,6 +751,7 @@
+ mainmenu_option next_comment
+ comment 'General setup'
+ if [ "$CONFIG_ACER_PICA_61" = "y" -o \
++ "$CONFIG_AR7" = "y" -o \
+ "$CONFIG_CASIO_E55" = "y" -o \
+ "$CONFIG_DDB5074" = "y" -o \
+ "$CONFIG_DDB5476" = "y" -o \
+@@ -797,6 +813,7 @@
+ bool 'Networking support' CONFIG_NET
+
+ if [ "$CONFIG_ACER_PICA_61" = "y" -o \
++ "$CONFIG_AR7" = "y" -o \
+ "$CONFIG_CASIO_E55" = "y" -o \
+ "$CONFIG_DECSTATION" = "y" -o \
+ "$CONFIG_IBM_WORKPAD" = "y" -o \
+diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
+--- linux.old/arch/mips/kernel/head.S 2005-10-21 16:43:16.396956500 +0200
++++ linux.dev/arch/mips/kernel/head.S 2005-11-10 01:10:45.807572250 +0100
+@@ -75,11 +75,11 @@
+ * size!
+ */
+ NESTED(except_vec4, 0, sp)
+- .set push
+- .set noreorder
+-1: j 1b /* Dummy, will be replaced */
+- nop
+- .set pop
++ .set mips2
++ lui k0, 0x9400
++ ori k0, 0x200
++ jr k0
++ nop
+ END(except_vec4)
+
+ /*
+diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
+--- linux.old/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
++++ linux.dev/arch/mips/kernel/mips_ksyms.c 2005-11-10 01:10:45.811572500 +0100
+@@ -40,6 +40,12 @@
+ extern long __strnlen_user_nocheck_asm(const char *s);
+ extern long __strnlen_user_asm(const char *s);
+
++#ifdef CONFIG_AR7
++#include <asm/ar7/adam2_env.h>
++int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
++#endif
++
++
+ EXPORT_SYMBOL(mips_machtype);
+ #ifdef CONFIG_EISA
+ EXPORT_SYMBOL(EISA_bus);
+@@ -103,3 +109,10 @@
+ #endif
+
+ EXPORT_SYMBOL(get_wchan);
++
++#ifdef CONFIG_AR7
++EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
++EXPORT_SYMBOL_NOVERS(prom_getenv);
++EXPORT_SYMBOL_NOVERS(prom_iterenv);
++#endif
++
+diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
+--- linux.old/arch/mips/kernel/setup.c 2005-10-21 16:43:16.396956500 +0200
++++ linux.dev/arch/mips/kernel/setup.c 2005-11-10 01:14:16.376732000 +0100
+@@ -38,6 +38,7 @@
+ #include <asm/io.h>
+ #include <asm/ptrace.h>
+ #include <asm/system.h>
++#include <asm/addrspace.h>
+
+ struct cpuinfo_mips cpu_data[NR_CPUS];
+ EXPORT_SYMBOL(cpu_data);
+@@ -88,7 +89,7 @@
+ struct boot_mem_map boot_mem_map;
+
+ unsigned char aux_device_present;
+-extern char _ftext, _etext, _fdata, _edata, _end;
++extern char _ftext, _etext, _fdata, _edata, _fbss, _end;
+
+ static char command_line[CL_SIZE];
+ char saved_command_line[CL_SIZE];
+@@ -116,6 +117,7 @@
+
+ static struct resource code_resource = { "Kernel code" };
+ static struct resource data_resource = { "Kernel data" };
++static struct resource bss_resource = { "Kernel bss" };
+
+ asmlinkage void __init
+ init_arch(int argc, char **argv, char **envp, int *prom_vec)
+@@ -272,7 +274,7 @@
+ for (i = 0; i < boot_mem_map.nr_map; i++) {
+ unsigned long start, end;
+
+- if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
++ if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
+ continue;
+
+ start = PFN_UP(boot_mem_map.map[i].addr);
+@@ -320,7 +322,8 @@
+ #endif
+
+ /* Initialize the boot-time allocator with low memory only. */
+- bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
++ bootmap_size = init_bootmem_node(NODE_DATA(0), first_usable_pfn,
++ PFN_UP(PHYS_OFFSET), max_low_pfn);
+
+ /*
+ * Register fully available low RAM pages with the bootmem allocator.
+@@ -371,11 +374,12 @@
+ continue;
+
+ /* Register lowmem ranges */
+- free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
++ free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
++ size<<PAGE_SHIFT);
+ }
+
+ /* Reserve the bootmap memory. */
+- reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
++ reserve_bootmem_node(NODE_DATA(0), PFN_PHYS(first_usable_pfn), bootmap_size);
+
+ #ifdef CONFIG_BLK_DEV_INITRD
+ /* Board specific code should have set up initrd_start and initrd_end */
+@@ -409,6 +413,8 @@
+ code_resource.end = virt_to_bus(&_etext) - 1;
+ data_resource.start = virt_to_bus(&_fdata);
+ data_resource.end = virt_to_bus(&_edata) - 1;
++ bss_resource.start = virt_to_bus(&_fbss);
++ bss_resource.end = virt_to_bus(&_end) - 1;
+
+ /*
+ * Request address space for all standard RAM.
+@@ -448,6 +454,7 @@
+ */
+ request_resource(res, &code_resource);
+ request_resource(res, &data_resource);
++ request_resource(res, &bss_resource);
+ }
+ }
+
+@@ -494,6 +501,7 @@
+ void hp_setup(void);
+ void au1x00_setup(void);
+ void frame_info_init(void);
++ void ar7_setup(void);
+
+ frame_info_init();
+ #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
+@@ -691,6 +699,11 @@
+ pmc_yosemite_setup();
+ break;
+ #endif
++#ifdef CONFIG_AR7
++ case MACH_GROUP_UNKNOWN:
++ ar7_setup();
++ break;
++#endif
+ default:
+ panic("Unsupported architecture");
+ }
+diff -urN linux.old/arch/mips/kernel/time.c linux.dev/arch/mips/kernel/time.c
+--- linux.old/arch/mips/kernel/time.c 2005-01-19 15:09:29.000000000 +0100
++++ linux.dev/arch/mips/kernel/time.c 2005-11-10 01:12:43.950955750 +0100
+@@ -143,7 +143,6 @@
+ expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
+ write_c0_count(expirelo - cycles_per_jiffy);
+ write_c0_compare(expirelo);
+- write_c0_count(count);
+ }
+
+ int (*mips_timer_state)(void);
+diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
+--- linux.old/arch/mips/kernel/traps.c 2005-10-21 16:43:16.400956750 +0200
++++ linux.dev/arch/mips/kernel/traps.c 2005-11-10 01:13:28.301727500 +0100
+@@ -869,9 +869,24 @@
+
+ exception_handlers[n] = handler;
+ if (n == 0 && cpu_has_divec) {
++ printk(KERN_DEBUG "%s: using long jump via k0 to reach %08x\n",
++ __FUNCTION__, handler);
++ /* where does the 8 byte limit mentioned in head.S come from??? */
++ if (handler > 0x0fffffff) { /* maximum for single J instruction */
++ /* lui k0, 0x0000 */
++ *(volatile u32 *)(KSEG0+0x200) = 0x3c1a0000 | (handler >> 16);
++ /* ori k0, 0x0000 */
++ *(volatile u32 *)(KSEG0+0x204) = 0x375a0000 | (handler & 0xffff);
++ /* jr k0 */
++ *(volatile u32 *)(KSEG0+0x208) = 0x03400008;
++ /* nop */
++ *(volatile u32 *)(KSEG0+0x20C) = 0x00000000;
++ flush_icache_range(KSEG0+0x200, KSEG0+0x210);
++ } else {
+ *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
+ (0x03ffffff & (handler >> 2));
+- flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
++ flush_icache_range(KSEG0+0x200, KSEG0+0x204);
++ }
+ }
+ return (void *)old_handler;
+ }
+diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
+--- linux.old/arch/mips/mm/init.c 2004-02-18 14:36:30.000000000 +0100
++++ linux.dev/arch/mips/mm/init.c 2005-11-10 01:14:16.376732000 +0100
+@@ -235,10 +235,13 @@
+ #endif
+ }
+
++#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
++#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
++
+ void __init paging_init(void)
+ {
+ unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
+- unsigned long max_dma, high, low;
++ unsigned long max_dma, high, low, start;
+
+ pagetable_init();
+
+@@ -247,7 +250,8 @@
+ #endif
+
+ max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
+- low = max_low_pfn;
++ start = START_PFN;
++ low = MAX_LOW_PFN - start;
+ high = highend_pfn;
+
+ #ifdef CONFIG_ISA
+@@ -270,7 +274,8 @@
+ zones_size[ZONE_HIGHMEM] = high - low;
+ #endif
+
+- free_area_init(zones_size);
++ free_area_init_node(0, NODE_DATA(0), 0, zones_size,
++ start << PAGE_SHIFT, 0);
+ }
+
+ #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
+@@ -283,7 +288,7 @@
+ for (i = 0; i < boot_mem_map.nr_map; i++) {
+ unsigned long addr, end;
+
+- if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
++ if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
+ /* not usable memory */
+ continue;
+
+@@ -313,16 +318,17 @@
+ max_mapnr = num_physpages = highend_pfn;
+ num_mappedpages = max_low_pfn;
+ #else
+- max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
++ max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
+ #endif
+- high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
+-
+- totalram_pages += free_all_bootmem();
++
++ high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
++
++ totalram_pages += free_all_bootmem_node(NODE_DATA(0));
+ totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */
+
+ reservedpages = ram = 0;
+- for (tmp = 0; tmp < max_low_pfn; tmp++)
+- if (page_is_ram(tmp)) {
++ for (tmp = 0; tmp < max_mapnr; tmp++)
++ if (page_is_ram(START_PFN + tmp)) {
+ ram++;
+ if (PageReserved(mem_map+tmp))
+ reservedpages++;
+@@ -377,13 +383,13 @@
+ #endif
+
+ extern char __init_begin, __init_end;
+-extern void prom_free_prom_memory(void) __init;
++extern unsigned long prom_free_prom_memory(void) __init;
+
+ void free_initmem(void)
+ {
+ unsigned long addr;
+
+- prom_free_prom_memory ();
++ totalram_pages += prom_free_prom_memory ();
+
+ addr = (unsigned long) &__init_begin;
+ while (addr < (unsigned long) &__init_end) {
+diff -urN linux.old/drivers/char/Config.in linux.dev/drivers/char/Config.in
+--- linux.old/drivers/char/Config.in 2005-10-21 16:43:16.440959250 +0200
++++ linux.dev/drivers/char/Config.in 2005-11-10 01:10:45.843574500 +0100
+@@ -188,6 +188,14 @@
+ tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
+ fi
+
++if [ "$CONFIG_AR7" = "y" ]; then
++ bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
++ dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
++
++ define_int CONFIG_AR7_VLYNQ_PORTS 2
++ tristate 'ADAM2 environment support (read-only)' CONFIG_AR7_ADAM2
++fi
++
+ source drivers/i2c/Config.in
+
+ mainmenu_option next_comment
+diff -urN linux.old/drivers/char/Config.in.orig linux.dev/drivers/char/Config.in.orig
+--- linux.old/drivers/char/Config.in.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/char/Config.in.orig 2005-11-10 01:10:45.863575750 +0100
+@@ -0,0 +1,414 @@
++#
++# Character device configuration
++#
++mainmenu_option next_comment
++comment 'Character devices'
++
++bool 'Virtual terminal' CONFIG_VT
++if [ "$CONFIG_VT" = "y" ]; then
++ bool ' Support for console on virtual terminal' CONFIG_VT_CONSOLE
++ if [ "$CONFIG_GSC_LASI" = "y" ]; then
++ bool ' Support for Lasi/Dino PS2 port' CONFIG_GSC_PS2
++ fi
++fi
++tristate 'Standard/generic (8250/16550 and compatible UARTs) serial support' CONFIG_SERIAL
++if [ "$CONFIG_SERIAL" = "y" ]; then
++ bool ' Support for console on serial port' CONFIG_SERIAL_CONSOLE
++ if [ "$CONFIG_GSC_LASI" = "y" ]; then
++ bool ' serial port on GSC support' CONFIG_SERIAL_GSC
++ fi
++ if [ "$CONFIG_IA64" = "y" ]; then
++ bool ' Support for serial port described by EFI HCDP table' CONFIG_SERIAL_HCDP
++ fi
++ if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
++ tristate ' Atomwide serial port support' CONFIG_ATOMWIDE_SERIAL
++ tristate ' Dual serial port support' CONFIG_DUALSP_SERIAL
++ fi
++fi
++dep_mbool 'Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED $CONFIG_SERIAL
++if [ "$CONFIG_SERIAL_EXTENDED" = "y" ]; then
++ bool ' Support more than 4 serial ports' CONFIG_SERIAL_MANY_PORTS
++ bool ' Support for sharing serial interrupts' CONFIG_SERIAL_SHARE_IRQ
++ bool ' Autodetect IRQ on standard ports (unsafe)' CONFIG_SERIAL_DETECT_IRQ
++ bool ' Support special multiport boards' CONFIG_SERIAL_MULTIPORT
++ bool ' Support the Bell Technologies HUB6 card' CONFIG_HUB6
++fi
++bool 'Non-standard serial port support' CONFIG_SERIAL_NONSTANDARD
++if [ "$CONFIG_SERIAL_NONSTANDARD" = "y" ]; then
++ tristate ' Computone IntelliPort Plus serial support' CONFIG_COMPUTONE
++ tristate ' Comtrol Rocketport support' CONFIG_ROCKETPORT
++ tristate ' Cyclades async mux support' CONFIG_CYCLADES
++ if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_CYCLADES" != "n" ]; then
++ bool ' Cyclades-Z interrupt mode operation (EXPERIMENTAL)' CONFIG_CYZ_INTR
++ fi
++ if [ "$CONFIG_X86_64" != "y" ]; then
++ tristate ' Digiboard Intelligent Async Support' CONFIG_DIGIEPCA
++ if [ "$CONFIG_DIGIEPCA" = "n" ]; then
++ tristate ' Digiboard PC/Xx Support' CONFIG_DIGI
++ fi
++ fi
++ dep_tristate ' Hayes ESP serial port support' CONFIG_ESPSERIAL $CONFIG_ISA
++ tristate ' Moxa Intellio support' CONFIG_MOXA_INTELLIO
++ tristate ' Moxa SmartIO support' CONFIG_MOXA_SMARTIO
++ if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
++ dep_tristate ' Multi-Tech multiport card support (EXPERIMENTAL)' CONFIG_ISI m
++ fi
++ tristate ' Microgate SyncLink card support' CONFIG_SYNCLINK
++ tristate ' SyncLink Multiport support' CONFIG_SYNCLINKMP
++ tristate ' HDLC line discipline support' CONFIG_N_HDLC
++ tristate ' SDL RISCom/8 card support' CONFIG_RISCOM8
++ if [ "$CONFIG_X86_64" != "y" ]; then
++ tristate ' Specialix IO8+ card support' CONFIG_SPECIALIX
++ if [ "$CONFIG_SPECIALIX" != "n" ]; then
++ bool ' Specialix DTR/RTS pin is RTS' CONFIG_SPECIALIX_RTSCTS
++ fi
++ tristate ' Specialix SX (and SI) card support' CONFIG_SX
++ tristate ' Specialix RIO system support' CONFIG_RIO
++ if [ "$CONFIG_RIO" != "n" ]; then
++ bool ' Support really old RIO/PCI cards' CONFIG_RIO_OLDPCI
++ fi
++ fi
++ bool ' Stallion multiport serial support' CONFIG_STALDRV
++ if [ "$CONFIG_STALDRV" = "y" ]; then
++ tristate ' Stallion EasyIO or EC8/32 support' CONFIG_STALLION
++ tristate ' Stallion EC8/64, ONboard, Brumby support' CONFIG_ISTALLION
++ fi
++ if [ "$CONFIG_PARISC" = "y" ]; then
++ if [ "$CONFIG_PDC_CONSOLE" != "y" ]; then
++ bool ' Serial MUX support' CONFIG_SERIAL_MUX CONFIG_SERIAL_NONSTANDARD
++ fi
++ if [ "$CONFIG_SERIAL_MUX" != "y" ]; then
++ bool ' PDC software console support' CONFIG_PDC_CONSOLE CONFIG_SERIAL_NONSTANDARD
++ fi
++ fi
++ if [ "$CONFIG_MIPS" = "y" ]; then
++ bool ' TX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
++ dep_bool ' Console on TX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
++ bool ' TMPTX39XX/49XX serial port support' CONFIG_SERIAL_TXX9
++ dep_bool ' Console on TMPTX39XX/49XX serial port' CONFIG_SERIAL_TXX9_CONSOLE $CONFIG_SERIAL_TXX9
++ if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
++ bool ' Enable Au1x00 UART Support' CONFIG_AU1X00_UART
++ if [ "$CONFIG_AU1X00_UART" = "y" ]; then
++ bool ' Enable Au1x00 serial console' CONFIG_AU1X00_SERIAL_CONSOLE
++ fi
++ dep_tristate ' Au1x00 USB TTY Device support' CONFIG_AU1X00_USB_TTY $CONFIG_SOC_AU1X00
++ if [ "$CONFIG_AU1000_USB_TTY" != "y" ]; then
++ dep_tristate ' Au1x00 USB Raw Device support' CONFIG_AU1X00_USB_RAW $CONFIG_SOC_AU1X00
++ fi
++ if [ "$CONFIG_AU1X00_USB_TTY" != "n" -o \
++ "$CONFIG_AU1X00_USB_RAW" != "n" ]; then
++ define_bool CONFIG_AU1X00_USB_DEVICE y
++ fi
++ fi
++ bool ' TXx927 SIO support' CONFIG_TXX927_SERIAL
++ if [ "$CONFIG_TXX927_SERIAL" = "y" ]; then
++ bool ' TXx927 SIO Console support' CONFIG_TXX927_SERIAL_CONSOLE
++ fi
++ if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]; then
++ bool ' Support for BCM1xxx onchip DUART' CONFIG_SIBYTE_SB1250_DUART
++ if [ "$CONFIG_SIBYTE_SB1250_DUART" = "y" ]; then
++ bool ' Console on BCM1xxx DUART' CONFIG_SIBYTE_SB1250_DUART_CONSOLE
++ if [ "$CONFIG_SIBYTE_SB1250_DUART_CONSOLE" = "y" ]; then
++ define_bool CONFIG_SERIAL_CONSOLE y
++ fi
++ fi
++ fi
++ fi
++ if [ "$CONFIG_DECSTATION" = "y" ]; then
++ bool ' DECstation serial support' CONFIG_SERIAL_DEC
++ dep_bool ' Support for console on a DECstation serial port' CONFIG_SERIAL_DEC_CONSOLE $CONFIG_SERIAL_DEC
++ dep_bool ' DZ11 serial support' CONFIG_DZ $CONFIG_SERIAL_DEC $CONFIG_MIPS32
++ dep_bool ' Z85C30 serial support' CONFIG_ZS $CONFIG_SERIAL_DEC $CONFIG_TC
++ fi
++ if [ "$CONFIG_SGI_IP22" = "y" ]; then
++ bool ' SGI Zilog85C30 serial support' CONFIG_IP22_SERIAL
++ fi
++ if [ "$CONFIG_IA64" = "y" ]; then
++ bool ' SGI SN2 l1 serial port support' CONFIG_SGI_L1_SERIAL
++ if [ "$CONFIG_SGI_L1_SERIAL" = "y" ]; then
++ bool ' SGI SN2 l1 Console support' CONFIG_SGI_L1_SERIAL_CONSOLE
++ fi
++ if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ]; then
++ bool ' SGI SN2 IOC4 serial port support' CONFIG_SGI_IOC4_SERIAL
++ fi
++ fi
++fi
++if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
++ tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
++fi
++if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
++ bool 'DC21285 serial port support' CONFIG_SERIAL_21285
++ if [ "$CONFIG_SERIAL_21285" = "y" ]; then
++ if [ "$CONFIG_OBSOLETE" = "y" ]; then
++ bool ' Use /dev/ttyS0 device (OBSOLETE)' CONFIG_SERIAL_21285_OLD
++ fi
++ bool ' Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE
++ fi
++ if [ "$CONFIG_PARISC" = "y" ]; then
++ bool ' PDC software console support' CONFIG_PDC_CONSOLE
++ fi
++fi
++if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
++ bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
++ if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
++ define_bool CONFIG_IT8172_CIR y
++ else
++ bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
++ fi
++ bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
++ bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
++fi
++if [ "$CONFIG_MIPS_IVR" = "y" ]; then
++ bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
++ if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
++ define_bool CONFIG_IT8172_CIR y
++ fi
++ bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
++fi
++if [ "$CONFIG_CPU_VR41XX" = "y" ]; then
++ bool 'NEC VR4100 series Keyboard Interface Unit Support ' CONFIG_VR41XX_KIU
++fi
++bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
++if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
++ int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 256
++fi
++if [ "$CONFIG_PARPORT" != "n" ]; then
++ dep_tristate 'Parallel printer support' CONFIG_PRINTER $CONFIG_PARPORT
++ if [ "$CONFIG_PRINTER" != "n" ]; then
++ bool ' Support for console on line printer' CONFIG_LP_CONSOLE
++ fi
++ dep_tristate 'Support for user-space parallel port device drivers' CONFIG_PPDEV $CONFIG_PARPORT
++ dep_tristate 'Texas Instruments parallel link cable support' CONFIG_TIPAR $CONFIG_PARPORT
++fi
++
++if [ "$CONFIG_PPC64" = "y" ] ; then
++ bool 'pSeries Hypervisor Virtual Console support' CONFIG_HVC_CONSOLE
++fi
++if [ "$CONFIG_ALL_PPC" = "y" ]; then
++ tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
++fi
++
++if [ "$CONFIG_AR7" = "y" ]; then
++ bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
++ dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
++
++ define_int CONFIG_AR7_VLYNQ_PORTS 2
++fi
++
++source drivers/i2c/Config.in
++
++mainmenu_option next_comment
++comment 'Mice'
++tristate 'Bus Mouse Support' CONFIG_BUSMOUSE
++if [ "$CONFIG_BUSMOUSE" != "n" ]; then
++ dep_tristate ' ATIXL busmouse support' CONFIG_ATIXL_BUSMOUSE $CONFIG_BUSMOUSE
++ dep_tristate ' Logitech busmouse support' CONFIG_LOGIBUSMOUSE $CONFIG_BUSMOUSE
++ dep_tristate ' Microsoft busmouse support' CONFIG_MS_BUSMOUSE $CONFIG_BUSMOUSE
++ if [ "$CONFIG_ADB" = "y" -a "$CONFIG_ADB_KEYBOARD" = "y" ]; then
++ dep_tristate ' Apple Desktop Bus mouse support (old driver)' CONFIG_ADBMOUSE $CONFIG_BUSMOUSE
++ fi
++# if [ "$CONFIG_DECSTATION" = "y" ]; then
++# dep_bool ' MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE $CONFIG_ACCESSBUS
++# fi
++fi
++
++tristate 'Mouse Support (not serial and bus mice)' CONFIG_MOUSE
++if [ "$CONFIG_MOUSE" != "n" ]; then
++ bool ' PS/2 mouse (aka "auxiliary device") support' CONFIG_PSMOUSE
++ tristate ' C&T 82C710 mouse port support (as on TI Travelmate)' CONFIG_82C710_MOUSE
++ tristate ' PC110 digitizer pad support' CONFIG_PC110_PAD
++ tristate ' MK712 touch screen support' CONFIG_MK712_MOUSE
++fi
++endmenu
++
++source drivers/char/joystick/Config.in
++
++tristate 'QIC-02 tape support' CONFIG_QIC02_TAPE
++if [ "$CONFIG_QIC02_TAPE" != "n" ]; then
++ bool ' Do you want runtime configuration for QIC-02' CONFIG_QIC02_DYNCONF
++ if [ "$CONFIG_QIC02_DYNCONF" != "y" ]; then
++ comment ' Edit configuration parameters in ./include/linux/tpqic02.h!'
++ else
++ comment ' Setting runtime QIC-02 configuration is done with qic02conf'
++ comment ' from the tpqic02-support package. It is available at'
++ comment ' metalab.unc.edu or ftp://titus.cfw.com/pub/Linux/util/'
++ fi
++fi
++
++tristate 'IPMI top-level message handler' CONFIG_IPMI_HANDLER
++dep_mbool ' Generate a panic event to all BMCs on a panic' CONFIG_IPMI_PANIC_EVENT $CONFIG_IPMI_HANDLER
++dep_tristate ' Device interface for IPMI' CONFIG_IPMI_DEVICE_INTERFACE $CONFIG_IPMI_HANDLER
++dep_tristate ' IPMI KCS handler' CONFIG_IPMI_KCS $CONFIG_IPMI_HANDLER
++dep_tristate ' IPMI Watchdog Timer' CONFIG_IPMI_WATCHDOG $CONFIG_IPMI_HANDLER
++
++mainmenu_option next_comment
++comment 'Watchdog Cards'
++bool 'Watchdog Timer Support' CONFIG_WATCHDOG
++if [ "$CONFIG_WATCHDOG" != "n" ]; then
++ bool ' Disable watchdog shutdown on close' CONFIG_WATCHDOG_NOWAYOUT
++ tristate ' Acquire SBC Watchdog Timer' CONFIG_ACQUIRE_WDT
++ tristate ' Advantech SBC Watchdog Timer' CONFIG_ADVANTECH_WDT
++ tristate ' ALi M7101 PMU on ALi 1535D+ Watchdog Timer' CONFIG_ALIM1535_WDT
++ tristate ' ALi M7101 PMU Watchdog Timer' CONFIG_ALIM7101_WDT
++ tristate ' AMD "Elan" SC520 Watchdog Timer' CONFIG_SC520_WDT
++ tristate ' Berkshire Products PC Watchdog' CONFIG_PCWATCHDOG
++ if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
++ tristate ' DC21285 watchdog' CONFIG_21285_WATCHDOG
++ if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
++ tristate ' NetWinder WB83C977 watchdog' CONFIG_977_WATCHDOG
++ fi
++ fi
++ tristate ' Eurotech CPU-1220/1410 Watchdog Timer' CONFIG_EUROTECH_WDT
++ tristate ' IB700 SBC Watchdog Timer' CONFIG_IB700_WDT
++ tristate ' ICP ELectronics Wafer 5823 Watchdog' CONFIG_WAFER_WDT
++ tristate ' Intel i810 TCO timer / Watchdog' CONFIG_I810_TCO
++ tristate ' Mixcom Watchdog' CONFIG_MIXCOMWD
++ tristate ' SBC-60XX Watchdog Timer' CONFIG_60XX_WDT
++ dep_tristate ' SC1200 Watchdog Timer (EXPERIMENTAL)' CONFIG_SC1200_WDT $CONFIG_EXPERIMENTAL
++ tristate ' NatSemi SCx200 Watchdog' CONFIG_SCx200_WDT
++ tristate ' Software Watchdog' CONFIG_SOFT_WATCHDOG
++ tristate ' W83877F (EMACS) Watchdog Timer' CONFIG_W83877F_WDT
++ tristate ' WDT Watchdog timer' CONFIG_WDT
++ tristate ' WDT PCI Watchdog timer' CONFIG_WDTPCI
++ if [ "$CONFIG_WDT" != "n" ]; then
++ bool ' WDT501 features' CONFIG_WDT_501
++ if [ "$CONFIG_WDT_501" = "y" ]; then
++ bool ' Fan Tachometer' CONFIG_WDT_501_FAN
++ fi
++ fi
++ tristate ' ZF MachZ Watchdog' CONFIG_MACHZ_WDT
++ if [ "$CONFIG_SGI_IP22" = "y" ]; then
++ dep_tristate ' Indy/I2 Hardware Watchdog' CONFIG_INDYDOG $CONFIG_SGI_IP22
++ fi
++ if [ "$CONFIG_8xx" = "y" ]; then
++ tristate ' MPC8xx Watchdog Timer' CONFIG_8xx_WDT
++ fi
++fi
++endmenu
++
++if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
++ tristate 'NetWinder thermometer support' CONFIG_DS1620
++ tristate 'NetWinder Button' CONFIG_NWBUTTON
++ if [ "$CONFIG_NWBUTTON" != "n" ]; then
++ bool ' Reboot Using Button' CONFIG_NWBUTTON_REBOOT
++ fi
++ tristate 'NetWinder flash support' CONFIG_NWFLASH
++fi
++tristate 'NatSemi SCx200 Support' CONFIG_SCx200
++dep_tristate ' NatSemi SCx200 GPIO Support' CONFIG_SCx200_GPIO $CONFIG_SCx200
++
++if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ] ; then
++ bool 'SGI SN2 fetchop support' CONFIG_FETCHOP
++fi
++
++if [ "$CONFIG_X86" = "y" -o "$CONFIG_X86_64" = "y" ]; then
++ dep_tristate 'AMD 768/8111 Random Number Generator support' CONFIG_AMD_RNG $CONFIG_PCI
++fi
++if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
++ dep_tristate 'Intel i8x0 Random Number Generator support' CONFIG_INTEL_RNG $CONFIG_PCI
++fi
++if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" -o \
++ "$CONFIG_X86_64" = "y" ]; then
++ dep_tristate 'Intel/AMD/VIA HW Random Number Generator support' CONFIG_HW_RANDOM $CONFIG_PCI
++fi
++dep_tristate 'AMD 76x native power management (Experimental)' CONFIG_AMD_PM768 $CONFIG_PCI
++tristate '/dev/nvram support' CONFIG_NVRAM
++tristate 'Enhanced Real Time Clock Support' CONFIG_RTC
++if [ "$CONFIG_IA64" = "y" ]; then
++ bool 'EFI Real Time Clock Services' CONFIG_EFI_RTC
++fi
++if [ "$CONFIG_OBSOLETE" = "y" -a "$CONFIG_ALPHA_BOOK1" = "y" ]; then
++ bool 'Tadpole ANA H8 Support (OBSOLETE)' CONFIG_H8
++fi
++if [ "$CONFIG_SGI_IP22" = "y" ]; then
++ tristate 'Dallas DS1286 RTC support' CONFIG_DS1286
++fi
++if [ "$CONFIG_SGI_IP27" = "y" ]; then
++ tristate 'SGI M48T35 RTC support' CONFIG_SGI_IP27_RTC
++fi
++if [ "$CONFIG_TOSHIBA_RBTX4927" = "y" -o "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
++ tristate 'Dallas DS1742 RTC support' CONFIG_DS1742
++fi
++
++tristate 'Double Talk PC internal speech card support' CONFIG_DTLK
++tristate 'Siemens R3964 line discipline' CONFIG_R3964
++tristate 'Applicom intelligent fieldbus card support' CONFIG_APPLICOM
++if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_X86" = "y" -a "$CONFIG_X86_64" != "y" ]; then
++ dep_tristate 'Sony Vaio Programmable I/O Control Device support (EXPERIMENTAL)' CONFIG_SONYPI $CONFIG_PCI
++fi
++
++mainmenu_option next_comment
++comment 'Ftape, the floppy tape device driver'
++tristate 'Ftape (QIC-80/Travan) support' CONFIG_FTAPE
++if [ "$CONFIG_FTAPE" != "n" ]; then
++ source drivers/char/ftape/Config.in
++fi
++
++endmenu
++
++if [ "$CONFIG_GART_IOMMU" = "y" ]; then
++ bool '/dev/agpgart (AGP Support)' CONFIG_AGP
++ define_bool CONFIG_AGP_AMD_K8 y
++else
++ tristate '/dev/agpgart (AGP Support)' CONFIG_AGP
++fi
++if [ "$CONFIG_AGP" != "n" ]; then
++ bool ' Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support' CONFIG_AGP_INTEL
++ bool ' Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
++ bool ' VIA chipset support' CONFIG_AGP_VIA
++ bool ' AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD
++ if [ "$CONFIG_GART_IOMMU" != "y" ]; then
++ bool ' AMD Opteron/Athlon64 on-CPU GART support' CONFIG_AGP_AMD_K8
++ fi
++ bool ' Generic SiS support' CONFIG_AGP_SIS
++ bool ' ALI chipset support' CONFIG_AGP_ALI
++ bool ' Serverworks LE/HE support' CONFIG_AGP_SWORKS
++ if [ "$CONFIG_X86" = "y" ]; then
++ bool ' NVIDIA chipset support' CONFIG_AGP_NVIDIA
++ fi
++ if [ "$CONFIG_IA64" = "y" ]; then
++ bool ' Intel 460GX support' CONFIG_AGP_I460
++ bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
++ fi
++ bool ' ATI IGP chipset support' CONFIG_AGP_ATI
++fi
++
++mainmenu_option next_comment
++comment 'Direct Rendering Manager (XFree86 DRI support)'
++bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM
++if [ "$CONFIG_DRM" = "y" ]; then
++ bool ' Build drivers for old (XFree 4.0) DRM' CONFIG_DRM_OLD
++ if [ "$CONFIG_DRM_OLD" = "y" ]; then
++ comment 'DRM 4.0 drivers'
++ source drivers/char/drm-4.0/Config.in
++ else
++ comment 'DRM 4.1 drivers'
++ define_bool CONFIG_DRM_NEW y
++ source drivers/char/drm/Config.in
++ fi
++fi
++
++if [ "$CONFIG_X86" = "y" ]; then
++ tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
++fi
++
++endmenu
++
++if [ "$CONFIG_HOTPLUG" = "y" -a "$CONFIG_PCMCIA" != "n" ]; then
++ source drivers/char/pcmcia/Config.in
++fi
++if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
++ tristate ' Alchemy Au1x00 GPIO device support' CONFIG_AU1X00_GPIO
++ tristate ' Au1000/ADS7846 touchscreen support' CONFIG_TS_AU1X00_ADS7846
++ #tristate ' Alchemy Au1550 PSC SPI support' CONFIG_AU1550_PSC_SPI
++fi
++if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
++ tristate ' ITE GPIO' CONFIG_ITE_GPIO
++fi
++
++if [ "$CONFIG_X86" = "y" ]; then
++ tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
++ dep_tristate 'HP OB600 C/CT Pop-up mouse support' CONFIG_OBMOUSE $CONFIG_INPUT_MOUSEDEV
++fi
++
++endmenu
+diff -urN linux.old/drivers/char/Makefile linux.dev/drivers/char/Makefile
+--- linux.old/drivers/char/Makefile 2005-10-21 16:43:16.460960500 +0200
++++ linux.dev/drivers/char/Makefile 2005-11-10 01:10:45.871576250 +0100
+@@ -240,6 +240,13 @@
+ obj-y += joystick/js.o
+ endif
+
++#
++# Texas Intruments VLYNQ driver
++#
++
++subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
++obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
++
+ obj-$(CONFIG_FETCHOP) += fetchop.o
+ obj-$(CONFIG_BUSMOUSE) += busmouse.o
+ obj-$(CONFIG_DTLK) += dtlk.o
+@@ -340,6 +347,11 @@
+ obj-y += ipmi/ipmi.o
+ endif
+
++subdir-$(CONFIG_AR7_ADAM2) += ticfg
++ifeq ($(CONFIG_AR7_ADAM2),y)
++ obj-y += ticfg/ticfg.o
++endif
++
+ include $(TOPDIR)/Rules.make
+
+ fastdep:
+diff -urN linux.old/drivers/char/Makefile.orig linux.dev/drivers/char/Makefile.orig
+--- linux.old/drivers/char/Makefile.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/char/Makefile.orig 2005-11-10 01:10:45.871576250 +0100
+@@ -0,0 +1,374 @@
++#
++# Makefile for the kernel character device drivers.
++#
++# Note! Dependencies are done automagically by 'make dep', which also
++# removes any old dependencies. DON'T put your own dependencies here
++# unless it's something special (ie not a .c file).
++#
++# Note 2! The CFLAGS definitions are now inherited from the
++# parent makes..
++#
++
++#
++# This file contains the font map for the default (hardware) font
++#
++FONTMAPFILE = cp437.uni
++
++O_TARGET := char.o
++
++obj-y += mem.o tty_io.o n_tty.o tty_ioctl.o raw.o pty.o misc.o random.o
++
++# All of the (potential) objects that export symbols.
++# This list comes from 'grep -l EXPORT_SYMBOL *.[hc]'.
++
++export-objs := busmouse.o console.o keyboard.o sysrq.o \
++ misc.o pty.o random.o selection.o serial.o \
++ sonypi.o tty_io.o tty_ioctl.o generic_serial.o \
++ au1000_gpio.o vac-serial.o hp_psaux.o nvram.o \
++ scx200.o fetchop.o
++
++mod-subdirs := joystick ftape drm drm-4.0 pcmcia
++
++list-multi :=
++
++KEYMAP =defkeymap.o
++KEYBD =pc_keyb.o
++CONSOLE =console.o
++SERIAL =serial.o
++
++ifeq ($(ARCH),s390)
++ KEYMAP =
++ KEYBD =
++ CONSOLE =
++ SERIAL =
++endif
++
++ifeq ($(ARCH),mips)
++ ifneq ($(CONFIG_PC_KEYB),y)
++ KEYBD =
++ endif
++ ifeq ($(CONFIG_VR41XX_KIU),y)
++ ifeq ($(CONFIG_IBM_WORKPAD),y)
++ KEYMAP = ibm_workpad_keymap.o
++ endif
++ ifeq ($(CONFIG_VICTOR_MPC30X),y)
++ KEYMAP = victor_mpc30x_keymap.o
++ endif
++ KEYBD = vr41xx_keyb.o
++ endif
++endif
++
++ifeq ($(ARCH),s390x)
++ KEYMAP =
++ KEYBD =
++ CONSOLE =
++ SERIAL =
++endif
++
++ifeq ($(ARCH),m68k)
++ ifdef CONFIG_AMIGA
++ KEYBD = amikeyb.o
++ else
++ ifndef CONFIG_MAC
++ KEYBD =
++ endif
++ endif
++ SERIAL =
++endif
++
++ifeq ($(ARCH),parisc)
++ ifdef CONFIG_GSC_PS2
++ KEYBD = hp_psaux.o hp_keyb.o
++ else
++ KEYBD =
++ endif
++ ifdef CONFIG_SERIAL_MUX
++ CONSOLE += mux.o
++ endif
++ ifdef CONFIG_PDC_CONSOLE
++ CONSOLE += pdc_console.o
++ endif
++endif
++
++ifdef CONFIG_Q40
++ KEYBD += q40_keyb.o
++ SERIAL = serial.o
++endif
++
++ifdef CONFIG_APOLLO
++ KEYBD += dn_keyb.o
++endif
++
++ifeq ($(ARCH),parisc)
++ ifdef CONFIG_GSC_PS2
++ KEYBD = hp_psaux.o hp_keyb.o
++ else
++ KEYBD =
++ endif
++ ifdef CONFIG_PDC_CONSOLE
++ CONSOLE += pdc_console.o
++ endif
++endif
++
++ifeq ($(ARCH),arm)
++ ifneq ($(CONFIG_PC_KEYMAP),y)
++ KEYMAP =
++ endif
++ ifneq ($(CONFIG_PC_KEYB),y)
++ KEYBD =
++ endif
++endif
++
++ifeq ($(ARCH),sh)
++ KEYMAP =
++ KEYBD =
++ CONSOLE =
++ ifeq ($(CONFIG_SH_HP600),y)
++ KEYMAP = defkeymap.o
++ KEYBD = scan_keyb.o hp600_keyb.o
++ CONSOLE = console.o
++ endif
++ ifeq ($(CONFIG_SH_DMIDA),y)
++ # DMIDA does not connect the HD64465 PS/2 keyboard port
++ # but we allow for USB keyboards to be plugged in.
++ KEYMAP = defkeymap.o
++ KEYBD = # hd64465_keyb.o pc_keyb.o
++ CONSOLE = console.o
++ endif
++ ifeq ($(CONFIG_SH_EC3104),y)
++ KEYMAP = defkeymap.o
++ KEYBD = ec3104_keyb.o
++ CONSOLE = console.o
++ endif
++ ifeq ($(CONFIG_SH_DREAMCAST),y)
++ KEYMAP = defkeymap.o
++ KEYBD =
++ CONSOLE = console.o
++ endif
++endif
++
++ifeq ($(CONFIG_DECSTATION),y)
++ KEYMAP =
++ KEYBD =
++endif
++
++ifeq ($(CONFIG_BAGET_MIPS),y)
++ KEYBD =
++ SERIAL = vac-serial.o
++endif
++
++ifeq ($(CONFIG_NINO),y)
++ SERIAL =
++endif
++
++ifneq ($(CONFIG_SUN_SERIAL),)
++ SERIAL =
++endif
++
++ifeq ($(CONFIG_QTRONIX_KEYBOARD),y)
++ KEYBD = qtronix.o
++ KEYMAP = qtronixmap.o
++endif
++
++ifeq ($(CONFIG_DUMMY_KEYB),y)
++ KEYBD = dummy_keyb.o
++endif
++
++obj-$(CONFIG_VT) += vt.o vc_screen.o consolemap.o consolemap_deftbl.o $(CONSOLE) selection.o
++obj-$(CONFIG_SERIAL) += $(SERIAL)
++obj-$(CONFIG_PARPORT_SERIAL) += parport_serial.o
++obj-$(CONFIG_SERIAL_HCDP) += hcdp_serial.o
++obj-$(CONFIG_SERIAL_21285) += serial_21285.o
++obj-$(CONFIG_SERIAL_SA1100) += serial_sa1100.o
++obj-$(CONFIG_SERIAL_AMBA) += serial_amba.o
++obj-$(CONFIG_TS_AU1X00_ADS7846) += au1000_ts.o
++obj-$(CONFIG_SERIAL_DEC) += decserial.o
++
++ifndef CONFIG_SUN_KEYBOARD
++ obj-$(CONFIG_VT) += keyboard.o $(KEYMAP) $(KEYBD)
++else
++ obj-$(CONFIG_PCI) += keyboard.o $(KEYMAP)
++endif
++
++obj-$(CONFIG_HIL) += hp_keyb.o
++obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
++obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
++obj-$(CONFIG_ROCKETPORT) += rocket.o
++obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
++obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
++obj-$(CONFIG_DIGI) += pcxx.o
++obj-$(CONFIG_DIGIEPCA) += epca.o
++obj-$(CONFIG_CYCLADES) += cyclades.o
++obj-$(CONFIG_STALLION) += stallion.o
++obj-$(CONFIG_ISTALLION) += istallion.o
++obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
++obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o
++obj-$(CONFIG_RISCOM8) += riscom8.o
++obj-$(CONFIG_ISI) += isicom.o
++obj-$(CONFIG_ESPSERIAL) += esp.o
++obj-$(CONFIG_SYNCLINK) += synclink.o
++obj-$(CONFIG_SYNCLINKMP) += synclinkmp.o
++obj-$(CONFIG_N_HDLC) += n_hdlc.o
++obj-$(CONFIG_SPECIALIX) += specialix.o
++obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
++obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
++obj-$(CONFIG_SX) += sx.o generic_serial.o
++obj-$(CONFIG_RIO) += rio/rio.o generic_serial.o
++obj-$(CONFIG_SH_SCI) += sh-sci.o generic_serial.o
++obj-$(CONFIG_SERIAL167) += serial167.o
++obj-$(CONFIG_MVME147_SCC) += generic_serial.o vme_scc.o
++obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o
++obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o
++obj-$(CONFIG_HVC_CONSOLE) += hvc_console.o
++obj-$(CONFIG_SERIAL_TX3912) += generic_serial.o serial_tx3912.o
++obj-$(CONFIG_TXX927_SERIAL) += serial_txx927.o
++obj-$(CONFIG_SERIAL_TXX9) += generic_serial.o serial_txx9.o
++obj-$(CONFIG_IP22_SERIAL) += sgiserial.o
++obj-$(CONFIG_AU1X00_UART) += au1x00-serial.o
++obj-$(CONFIG_SGI_L1_SERIAL) += sn_serial.o
++
++subdir-$(CONFIG_RIO) += rio
++subdir-$(CONFIG_INPUT) += joystick
++
++obj-$(CONFIG_ATIXL_BUSMOUSE) += atixlmouse.o
++obj-$(CONFIG_LOGIBUSMOUSE) += logibusmouse.o
++obj-$(CONFIG_PRINTER) += lp.o
++obj-$(CONFIG_TIPAR) += tipar.o
++obj-$(CONFIG_OBMOUSE) += obmouse.o
++
++ifeq ($(CONFIG_INPUT),y)
++obj-y += joystick/js.o
++endif
++
++#
++# Texas Intruments VLYNQ driver
++#
++
++subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
++obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
++
++obj-$(CONFIG_FETCHOP) += fetchop.o
++obj-$(CONFIG_BUSMOUSE) += busmouse.o
++obj-$(CONFIG_DTLK) += dtlk.o
++obj-$(CONFIG_R3964) += n_r3964.o
++obj-$(CONFIG_APPLICOM) += applicom.o
++obj-$(CONFIG_SONYPI) += sonypi.o
++obj-$(CONFIG_MS_BUSMOUSE) += msbusmouse.o
++obj-$(CONFIG_82C710_MOUSE) += qpmouse.o
++obj-$(CONFIG_AMIGAMOUSE) += amigamouse.o
++obj-$(CONFIG_ATARIMOUSE) += atarimouse.o
++obj-$(CONFIG_ADBMOUSE) += adbmouse.o
++obj-$(CONFIG_PC110_PAD) += pc110pad.o
++obj-$(CONFIG_MK712_MOUSE) += mk712.o
++obj-$(CONFIG_RTC) += rtc.o
++obj-$(CONFIG_GEN_RTC) += genrtc.o
++obj-$(CONFIG_EFI_RTC) += efirtc.o
++obj-$(CONFIG_MIPS_RTC) += mips_rtc.o
++obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
++ifeq ($(CONFIG_PPC),)
++ obj-$(CONFIG_NVRAM) += nvram.o
++endif
++obj-$(CONFIG_TOSHIBA) += toshiba.o
++obj-$(CONFIG_I8K) += i8k.o
++obj-$(CONFIG_DS1286) += ds1286.o
++obj-$(CONFIG_DS1620) += ds1620.o
++obj-$(CONFIG_DS1742) += ds1742.o
++obj-$(CONFIG_INTEL_RNG) += i810_rng.o
++obj-$(CONFIG_AMD_RNG) += amd768_rng.o
++obj-$(CONFIG_HW_RANDOM) += hw_random.o
++obj-$(CONFIG_AMD_PM768) += amd76x_pm.o
++obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o
++
++obj-$(CONFIG_ITE_GPIO) += ite_gpio.o
++obj-$(CONFIG_AU1X00_GPIO) += au1000_gpio.o
++obj-$(CONFIG_AU1550_PSC_SPI) += au1550_psc_spi.o
++obj-$(CONFIG_AU1X00_USB_TTY) += au1000_usbtty.o
++obj-$(CONFIG_AU1X00_USB_RAW) += au1000_usbraw.o
++obj-$(CONFIG_COBALT_LCD) += lcd.o
++
++obj-$(CONFIG_QIC02_TAPE) += tpqic02.o
++
++subdir-$(CONFIG_FTAPE) += ftape
++subdir-$(CONFIG_DRM_OLD) += drm-4.0
++subdir-$(CONFIG_DRM_NEW) += drm
++subdir-$(CONFIG_PCMCIA) += pcmcia
++subdir-$(CONFIG_AGP) += agp
++
++ifeq ($(CONFIG_FTAPE),y)
++obj-y += ftape/ftape.o
++endif
++
++obj-$(CONFIG_H8) += h8.o
++obj-$(CONFIG_PPDEV) += ppdev.o
++obj-$(CONFIG_DZ) += dz.o
++obj-$(CONFIG_NWBUTTON) += nwbutton.o
++obj-$(CONFIG_NWFLASH) += nwflash.o
++obj-$(CONFIG_SCx200) += scx200.o
++obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
++
++# Only one watchdog can succeed. We probe the hardware watchdog
++# drivers first, then the softdog driver. This means if your hardware
++# watchdog dies or is 'borrowed' for some reason the software watchdog
++# still gives you some cover.
++
++obj-$(CONFIG_PCWATCHDOG) += pcwd.o
++obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
++obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o
++obj-$(CONFIG_IB700_WDT) += ib700wdt.o
++obj-$(CONFIG_MIXCOMWD) += mixcomwd.o
++obj-$(CONFIG_60XX_WDT) += sbc60xxwdt.o
++obj-$(CONFIG_W83877F_WDT) += w83877f_wdt.o
++obj-$(CONFIG_SC520_WDT) += sc520_wdt.o
++obj-$(CONFIG_WDT) += wdt.o
++obj-$(CONFIG_WDTPCI) += wdt_pci.o
++obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
++obj-$(CONFIG_977_WATCHDOG) += wdt977.o
++obj-$(CONFIG_I810_TCO) += i810-tco.o
++obj-$(CONFIG_MACHZ_WDT) += machzwd.o
++obj-$(CONFIG_SH_WDT) += shwdt.o
++obj-$(CONFIG_EUROTECH_WDT) += eurotechwdt.o
++obj-$(CONFIG_ALIM7101_WDT) += alim7101_wdt.o
++obj-$(CONFIG_ALIM1535_WDT) += alim1535d_wdt.o
++obj-$(CONFIG_INDYDOG) += indydog.o
++obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
++obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
++obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
++obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
++obj-$(CONFIG_INDYDOG) += indydog.o
++obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
++
++subdir-$(CONFIG_MWAVE) += mwave
++ifeq ($(CONFIG_MWAVE),y)
++ obj-y += mwave/mwave.o
++endif
++
++subdir-$(CONFIG_IPMI_HANDLER) += ipmi
++ifeq ($(CONFIG_IPMI_HANDLER),y)
++ obj-y += ipmi/ipmi.o
++endif
++
++include $(TOPDIR)/Rules.make
++
++fastdep:
++
++conmakehash: conmakehash.c
++ $(HOSTCC) $(HOSTCFLAGS) -o conmakehash conmakehash.c
++
++consolemap_deftbl.c: $(FONTMAPFILE) conmakehash
++ ./conmakehash $(FONTMAPFILE) > consolemap_deftbl.c
++
++consolemap_deftbl.o: consolemap_deftbl.c $(TOPDIR)/include/linux/types.h
++
++.DELETE_ON_ERROR:
++
++defkeymap.c: defkeymap.map
++ set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
++
++qtronixmap.c: qtronixmap.map
++ set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
++
++ibm_workpad_keymap.c: ibm_workpad_keymap.map
++ set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
++
++victor_mpc30x_keymap.c: victor_mpc30x_keymap.map
++ set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
+diff -urN linux.old/drivers/char/avalanche_vlynq/Makefile linux.dev/drivers/char/avalanche_vlynq/Makefile
+--- linux.old/drivers/char/avalanche_vlynq/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/char/avalanche_vlynq/Makefile 2005-11-10 01:10:45.871576250 +0100
+@@ -0,0 +1,16 @@
++#
++# Makefile for the linux kernel.
++#
++# Note! Dependencies are done automagically by 'make dep', which also
++# removes any old dependencies. DON'T put your own dependencies here
++# unless it's something special (ie not a .c file).
++#
++# Note 2! The CFLAGS definitions are now in the main makefile...
++
++O_TARGET := avalanche_vlynq.o
++
++export-objs := vlynq_board.o
++
++obj-y += vlynq_drv.o vlynq_hal.o vlynq_board.o
++
++include $(TOPDIR)/Rules.make
+diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_board.c linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c
+--- linux.old/drivers/char/avalanche_vlynq/vlynq_board.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c 2005-11-10 01:10:45.871576250 +0100
+@@ -0,0 +1,184 @@
++/*
++ * Jeff Harrell, jharrell@ti.com
++ * Copyright (C) 2001 Texas Instruments, Inc. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Texas Instruments Sangam specific setup.
++ */
++#include <linux/config.h>
++#include <linux/module.h>
++#include <asm/ar7/sangam.h>
++#include <asm/ar7/avalanche_misc.h>
++#include <asm/ar7/vlynq.h>
++
++#define SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR 30 /* MSB - 1 bit */
++#define SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR 31 /* MSB bit */
++#define SYS_VLYNQ_OPTIONS 0x7F; /* all options*/
++
++/* These defines are board specific */
++
++
++#define VLYNQ0_REMOTE_WINDOW1_OFFSET (0x0C000000)
++#define VLYNQ0_REMOTE_WINDOW1_SIZE (0x500)
++
++
++#define VLYNQ1_REMOTE_WINDOW1_OFFSET (0x0C000000)
++#define VLYNQ1_REMOTE_WINDOW1_SIZE (0x500)
++
++
++extern VLYNQ_DEV vlynqDevice0, vlynqDevice1;
++int vlynq_init_status[2] = {0, 0};
++EXPORT_SYMBOL(vlynq_init_status);
++static int reset_hack = 1;
++
++void vlynq_ar7wrd_dev_init()
++{
++ *(unsigned long*) AVALANCHE_GPIO_ENBL |= (1<<18);
++ vlynq_delay(20000);
++ *(unsigned long*) AVALANCHE_GPIO_DIR &= ~(1<<18);
++ vlynq_delay(20000);
++ *(unsigned long*) AVALANCHE_GPIO_DATA_OUT&= ~(1<<18);
++ vlynq_delay(50000);
++ *(unsigned long*) AVALANCHE_GPIO_DATA_OUT|= (1<<18);
++ vlynq_delay(50000);
++
++ /* Initialize the MIPS host vlynq driver for a given vlynq interface */
++ vlynqDevice0.dev_idx = 0; /* first vlynq module - this parameter is for reference only */
++ vlynqDevice0.module_base = AVALANCHE_LOW_VLYNQ_CONTROL_BASE; /* vlynq0 module base address */
++
++#if defined(CONFIG_VLYNQ_CLK_LOCAL)
++ vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_LOCAL;
++#else
++ vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_REMOTE;
++#endif
++ vlynqDevice0.clk_div = 0x01; /* board/hardware specific */
++ vlynqDevice0.state = VLYNQ_DRV_STATE_UNINIT; /* uninitialized module */
++
++ /* Populate vlynqDevice0.local_mem & Vlynq0.remote_mem based on system configuration */
++ /*Local memory configuration */
++
++ /* Demiurg : not good !*/
++#if 0
++ vlynqDevice0.local_mem.Txmap= AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE & ~(0xc0000000) ; /* physical address */
++ vlynqDevice0.remote_mem.RxOffset[0]= VLYNQ0_REMOTE_WINDOW1_OFFSET; /* This is specific to the board on the other end */
++ vlynqDevice0.remote_mem.RxSize[0]=VLYNQ0_REMOTE_WINDOW1_SIZE;
++#endif
++
++ /* Demiurg : This is how it should be ! */
++ vlynqDevice0.local_mem.Txmap = PHYSADDR(AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE);
++#define VLYNQ_ACX111_MEM_OFFSET 0xC0000000 /* Physical address of ACX111 memory */
++#define VLYNQ_ACX111_MEM_SIZE 0x00040000 /* Total size of the ACX111 memory */
++#define VLYNQ_ACX111_REG_OFFSET 0xF0000000 /* PHYS_ADDR of ACX111 control registers */
++#define VLYNQ_ACX111_REG_SIZE 0x00022000 /* Size of ACX111 registers area, MAC+PHY */
++#define ACX111_VL1_REMOTE_SIZE 0x1000000
++ vlynqDevice0.remote_mem.RxOffset[0] = VLYNQ_ACX111_MEM_OFFSET;
++ vlynqDevice0.remote_mem.RxSize[0] = VLYNQ_ACX111_MEM_SIZE ;
++ vlynqDevice0.remote_mem.RxOffset[1] = VLYNQ_ACX111_REG_OFFSET;
++ vlynqDevice0.remote_mem.RxSize[1] = VLYNQ_ACX111_REG_SIZE ;
++ vlynqDevice0.remote_mem.Txmap = 0;
++ vlynqDevice0.local_mem.RxOffset[0] = AVALANCHE_SDRAM_BASE;
++ vlynqDevice0.local_mem.RxSize[0] = ACX111_VL1_REMOTE_SIZE;
++
++
++ /* Local interrupt configuration */
++ vlynqDevice0.local_irq.intLocal = VLYNQ_INT_LOCAL; /* Host handles vlynq interrupts*/
++ vlynqDevice0.local_irq.intRemote = VLYNQ_INT_ROOT_ISR; /* vlynq root isr used */
++ vlynqDevice0.local_irq.map_vector = SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR;
++ vlynqDevice0.local_irq.intr_ptr = 0; /* Since remote interrupts part of vlynq root isr this is unused */
++
++ /* Remote interrupt configuration */
++ vlynqDevice0.remote_irq.intLocal = VLYNQ_INT_REMOTE; /* MIPS handles interrupts */
++ vlynqDevice0.remote_irq.intRemote = VLYNQ_INT_ROOT_ISR; /* Not significant since MIPS handles interrupts */
++ vlynqDevice0.remote_irq.map_vector = SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR;
++ vlynqDevice0. remote_irq.intr_ptr = AVALANCHE_INTC_BASE; /* Not significant since MIPS handles interrupts */
++
++ if(reset_hack != 1)
++ printk("About to re-init the VLYNQ.\n");
++
++ if(vlynq_init(&vlynqDevice0,VLYNQ_INIT_PERFORM_ALL)== 0)
++ {
++ /* Suraj added the following to keep the 1130 going. */
++ vlynq_interrupt_vector_set(&vlynqDevice0, 0 /* intr vector line running into 1130 vlynq */,
++ 0 /* intr mapped onto the interrupt register on remote vlynq and this vlynq */,
++ VLYNQ_REMOTE_DVC, 0 /* polarity active high */, 0 /* interrupt Level triggered */);
++
++ /* System wide interrupt is 80 for 1130, please note. */
++ vlynq_init_status[0] = 1;
++ reset_hack = 2;
++ }
++ else
++ {
++ if(reset_hack == 1)
++ printk("VLYNQ INIT FAILED: Please try cold reboot. \n");
++ else
++ printk("Failed to initialize the VLYNQ interface at insmod.\n");
++
++ }
++}
++
++void vlynq_dev_init(void)
++{
++ volatile unsigned int *reset_base = (unsigned int *) AVALANCHE_RESET_CONTROL_BASE;
++
++ *reset_base &= ~((1 << AVALANCHE_LOW_VLYNQ_RESET_BIT)); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT)); */
++
++ vlynq_delay(20000);
++
++ /* Bring vlynq out of reset if not already done */
++ *reset_base |= (1 << AVALANCHE_LOW_VLYNQ_RESET_BIT); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT); */
++ vlynq_delay(20000); /* Allowing sufficient time to VLYNQ to settle down.*/
++
++ vlynq_ar7wrd_dev_init( );
++
++}
++
++/* This function is board specific and should be ported for each board. */
++void remote_vlynq_dev_reset_ctrl(unsigned int module_reset_bit,
++ AVALANCHE_RESET_CTRL_T reset_ctrl)
++{
++ if(module_reset_bit >= 32)
++ return;
++
++ switch(module_reset_bit)
++ {
++ case 0:
++ if(OUT_OF_RESET == reset_ctrl)
++ {
++ if(reset_hack) return;
++
++ vlynq_delay(20000);
++ printk("Un-resetting the remote device.\n");
++ vlynq_dev_init();
++ printk("Re-initialized the VLYNQ.\n");
++ reset_hack = 2;
++ }
++ else if(IN_RESET == reset_ctrl)
++ {
++ *(unsigned long*) AVALANCHE_GPIO_DATA_OUT &= ~(1<<18);
++
++ vlynq_delay(20000);
++ printk("Resetting the remote device.\n");
++ reset_hack = 0;
++ }
++ else
++ ;
++ break;
++
++ default:
++ break;
++
++ }
++}
++
+diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c
+--- linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c 2005-11-10 01:10:45.891577500 +0100
+@@ -0,0 +1,243 @@
++/******************************************************************************
++ * FILE PURPOSE: Vlynq Linux Device Driver Source
++ ******************************************************************************
++ * FILE NAME: vlynq_drv.c
++ *
++ * DESCRIPTION: Vlynq Linux Device Driver Source
++ *
++ * REVISION HISTORY:
++ *
++ * Date Description Author
++ *-----------------------------------------------------------------------------
++ * 17 July 2003 Initial Creation Anant Gole
++ * 17 Dec 2003 Updates Sharath Kumar
++ *
++ * (C) Copyright 2003, Texas Instruments, Inc
++ *******************************************************************************/
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/sched.h>
++#include <linux/miscdevice.h>
++#include <linux/smp_lock.h>
++#include <linux/delay.h>
++#include <linux/proc_fs.h>
++#include <linux/capability.h>
++#include <asm/ar7/avalanche_intc.h>
++#include <asm/ar7/sangam.h>
++#include <asm/ar7/vlynq.h>
++
++
++#define TI_VLYNQ_VERSION "0.2"
++
++/* debug on ? */
++#define VLYNQ_DEBUG
++
++/* Macro for debug and error printf's */
++#ifdef VLYNQ_DEBUG
++#define DBGPRINT printk
++#else
++#define DBGPRINT(x)
++#endif
++
++#define ERRPRINT printk
++
++/* Define the max vlynq ports this driver will support.
++ Device name strings are statically added here */
++#define MAX_VLYNQ_PORTS 2
++
++
++/* Type define for VLYNQ private structure */
++typedef struct vlynqPriv{
++ int irq;
++ VLYNQ_DEV *vlynqDevice;
++}VLYNQ_PRIV;
++
++extern int vlynq_init_status[2];
++
++/* Extern Global variable for vlynq devices used in initialization of the vlynq device
++ * These variables need to be populated/initialized by the system as part of initialization
++ * process. The vlynq enumerator can run at initialization and populate these globals
++ */
++
++VLYNQ_DEV vlynqDevice0;
++VLYNQ_DEV vlynqDevice1;
++
++/* Defining dummy macro AVALANCHE_HIGH_VLYNQ_INT to take
++ * care of compilation in case of single vlynq device
++ */
++
++#ifndef AVALANCHE_HIGH_VLYNQ_INT
++#define AVALANCHE_HIGH_VLYNQ_INT 0
++#endif
++
++
++
++/* vlynq private object */
++VLYNQ_PRIV vlynq_priv[CONFIG_AR7_VLYNQ_PORTS] = {
++ { LNXINTNUM(AVALANCHE_LOW_VLYNQ_INT),&vlynqDevice0},
++ { LNXINTNUM(AVALANCHE_HIGH_VLYNQ_INT),&vlynqDevice1},
++};
++
++extern void vlynq_dev_init(void);
++
++
++/* =================================== all the operations */
++
++static int
++vlynq_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
++{
++ return 0;
++}
++
++static struct file_operations vlynq_fops = {
++ owner: THIS_MODULE,
++ ioctl: vlynq_ioctl,
++};
++
++/* Vlynq device object */
++static struct miscdevice vlynq_dev [MAX_VLYNQ_PORTS] = {
++ { MISC_DYNAMIC_MINOR , "vlynq0", &vlynq_fops },
++ { MISC_DYNAMIC_MINOR , "vlynq1", &vlynq_fops },
++};
++
++
++/* Proc read function */
++static int
++vlynq_read_link_proc(char *buf, char **start, off_t offset, int count, int *eof, void *unused)
++{
++ int instance;
++ int len = 0;
++
++ len += sprintf(buf +len,"VLYNQ Devices : %d\n",CONFIG_AR7_VLYNQ_PORTS);
++
++ for(instance =0;instance < CONFIG_AR7_VLYNQ_PORTS;instance++)
++ {
++ int link_state;
++ char *link_msg[] = {" DOWN "," UP "};
++
++ if(vlynq_init_status[instance] == 0)
++ link_state = 0;
++
++ else if (vlynq_link_check(vlynq_priv[instance].vlynqDevice))
++ link_state = 1;
++
++ else
++ link_state = 0;
++
++ len += sprintf(buf + len, "VLYNQ %d: Link state: %s\n",instance,link_msg[link_state]);
++
++ }
++ /* Print info about vlynq device 1 */
++
++ return len;
++}
++
++
++/* Proc function to display driver version */
++static int
++vlynq_read_ver_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data)
++{
++ int instance;
++ int len=0;
++
++ len += sprintf(buf +len,"\nTI Linux VLYNQ Driver Version %s\n",TI_VLYNQ_VERSION);
++ return len;
++}
++
++
++
++
++/* Wrapper for vlynq ISR */
++static void lnx_vlynq_root_isr(int irq, void * arg, struct pt_regs *regs)
++{
++ vlynq_root_isr(arg);
++}
++
++/* =================================== init and cleanup */
++
++int vlynq_init_module(void)
++{
++ int ret;
++ int unit = 0;
++ int instance_count = CONFIG_AR7_VLYNQ_PORTS;
++ volatile int *ptr;
++
++ vlynq_dev_init();
++
++ DBGPRINT("Vlynq CONFIG_AR7_VLYNQ_PORTS=%d\n", CONFIG_AR7_VLYNQ_PORTS);
++ /* If num of configured vlynq ports > supported by driver return error */
++ if (instance_count > MAX_VLYNQ_PORTS)
++ {
++ ERRPRINT("ERROR: vlynq_init_module(): Max %d supported\n", MAX_VLYNQ_PORTS);
++ return (-1);
++ }
++
++ /* register the misc device */
++ for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
++ {
++ ret = misc_register(&vlynq_dev[unit]);
++
++ if(ret < 0)
++ {
++ ERRPRINT("ERROR:Could not register vlynq device:%d\n",unit);
++ continue;
++ }
++ else
++ DBGPRINT("Vlynq Device %s registered with minor no %d as misc device. Result=%d\n",
++ vlynq_dev[unit].name, vlynq_dev[unit].minor, ret);
++#if 0
++
++ DBGPRINT("Calling vlynq init\n");
++
++ /* Read the global variable for VLYNQ device structure and initialize vlynq driver */
++ ret = vlynq_init(vlynq_priv[unit].vlynqDevice,VLYNQ_INIT_PERFORM_ALL );
++#endif
++
++ if(vlynq_init_status[unit] == 0)
++ {
++ printk("VLYNQ %d : init failed\n",unit);
++ continue;
++ }
++
++ /* Check link before proceeding */
++ if (!vlynq_link_check(vlynq_priv[unit].vlynqDevice))
++ {
++ DBGPRINT("\nError: Vlynq link not available.trying once before Exiting");
++ }
++ else
++ {
++ DBGPRINT("Vlynq instance:%d Link UP\n",unit);
++
++ /* Install the vlynq local root ISR */
++ request_irq(vlynq_priv[unit].irq,lnx_vlynq_root_isr,0,vlynq_dev[unit].name,vlynq_priv[unit].vlynqDevice);
++ }
++ }
++
++ proc_mkdir("avalanche", NULL);
++ /* Creating proc entry for the devices */
++ create_proc_read_entry("avalanche/vlynq_link", 0, NULL, vlynq_read_link_proc, NULL);
++ create_proc_read_entry("avalanche/vlynq_ver", 0, NULL, vlynq_read_ver_proc, NULL);
++
++ return 0;
++}
++
++void vlynq_cleanup_module(void)
++{
++ int unit = 0;
++
++ for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
++ {
++ DBGPRINT("vlynq_cleanup_module(): Unregistring misc device %s\n",vlynq_dev[unit].name);
++ misc_deregister(&vlynq_dev[unit]);
++ }
++
++ remove_proc_entry("avalanche/vlynq_link", NULL);
++ remove_proc_entry("avalanche/vlynq_ver", NULL);
++}
++
++
++module_init(vlynq_init_module);
++module_exit(vlynq_cleanup_module);
++
+diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c
+--- linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c 2005-11-10 01:10:45.975582750 +0100
+@@ -0,0 +1,1214 @@
++/***************************************************************************
++**+----------------------------------------------------------------------+**
++**| **** |**
++**| **** |**
++**| ******o*** |**
++**| ********_///_**** |**
++**| ***** /_//_/ **** |**
++**| ** ** (__/ **** |**
++**| ********* |**
++**| **** |**
++**| *** |**
++**| |**
++**| Copyright (c) 2003 Texas Instruments Incorporated |**
++**| ALL RIGHTS RESERVED |**
++**| |**
++**| Permission is hereby granted to licensees of Texas Instruments |**
++**| Incorporated (TI) products to use this computer program for the sole |**
++**| purpose of implementing a licensee product based on TI products. |**
++**| No other rights to reproduce, use, or disseminate this computer |**
++**| program, whether in part or in whole, are granted. |**
++**| |**
++**| TI makes no representation or warranties with respect to the |**
++**| performance of this computer program, and specifically disclaims |**
++**| any responsibility for any damages, special or consequential, |**
++**| connected with the use of this program. |**
++**| |**
++**+----------------------------------------------------------------------+**
++***************************************************************************/
++
++/***************************************************************************
++ * ------------------------------------------------------------------------------
++ * Module : vlynq_hal.c
++ * Description : This file implements VLYNQ HAL API.
++ * ------------------------------------------------------------------------------
++ ***************************************************************************/
++
++#include <linux/stddef.h>
++#include <linux/types.h>
++#include <asm/ar7/vlynq.h>
++
++/**** Local Function prototypes *******/
++static int vlynqInterruptInit(VLYNQ_DEV *pdev);
++static void vlynq_configClock(VLYNQ_DEV *pdev);
++
++/*** Second argument must be explicitly type casted to
++ * (VLYNQ_DEV*) inside the following functions */
++static void vlynq_local_module_isr(void *arg1, void *arg2, void *arg3);
++static void vlynq_remote_module_isr(void *arg1, void *arg2, void *arg3);
++
++
++volatile int vlynq_delay_value = 0;
++
++/* Code adopted from original vlynq driver */
++void vlynq_delay(unsigned int clktime)
++{
++ int i = 0;
++ volatile int *ptr = &vlynq_delay_value;
++ *ptr = 0;
++
++ /* We are assuming that the each cycle takes about
++ * 23 assembly instructions. */
++ for(i = 0; i < (clktime + 23)/23; i++)
++ {
++ *ptr = *ptr + 1;
++ }
++}
++
++
++/* ----------------------------------------------------------------------------
++ * Function : vlynq_configClock()
++ * Description: Configures clock settings based on input parameters
++ * Adapted from original vlyna driver from Cable
++ */
++static void vlynq_configClock(VLYNQ_DEV * pdev)
++{
++ unsigned int tmp;
++
++ switch( pdev->clk_source)
++ {
++ case VLYNQ_CLK_SOURCE_LOCAL: /* we output the clock, clk_div in range [1..8]. */
++ tmp = ((pdev->clk_div - 1) << 16) | VLYNQ_CTL_CLKDIR_MASK ;
++ VLYNQ_CTRL_REG = tmp;
++ VLYNQ_R_CTRL_REG = 0ul;
++ break;
++ case VLYNQ_CLK_SOURCE_REMOTE: /* we need to set the clock pin as input */
++ VLYNQ_CTRL_REG = 0ul;
++ tmp = ((pdev->clk_div - 1) << 16) | VLYNQ_CTL_CLKDIR_MASK ;
++ VLYNQ_R_CTRL_REG = tmp;
++ break;
++ default: /* do nothing about the clock, but clear other bits. */
++ tmp = ~(VLYNQ_CTL_CLKDIR_MASK | VLYNQ_CTL_CLKDIV_MASK);
++ VLYNQ_CTRL_REG &= tmp;
++ break;
++ }
++}
++
++ /* ----------------------------------------------------------------------------
++ * Function : vlynq_link_check()
++ * Description: This function checks the current VLYNQ for a link.
++ * An arbitrary amount of time is allowed for the link to come up .
++ * Returns 0 for "no link / failure " and 1 for "link available".
++ * -----------------------------------------------------------------------------
++ */
++unsigned int vlynq_link_check( VLYNQ_DEV * pdev)
++{
++ /*sleep for 64 cycles, allow link to come up*/
++ vlynq_delay(64);
++
++ /* check status register return OK if link is found. */
++ if (VLYNQ_STATUS_REG & VLYNQ_STS_LINK_MASK)
++ {
++ return 1; /* Link Available */
++ }
++ else
++ {
++ return 0; /* Link Failure */
++ }
++}
++
++/* ----------------------------------------------------------------------------
++ * Function : vlynq_init()
++ * Description: Initialization function accepting paramaters for VLYNQ module
++ * initialization. The Options bitmap decides what operations are performed
++ * as a part of initialization. The Input parameters are obtained through the
++ * sub fields of VLYNQ_DEV structure.
++ */
++
++int vlynq_init(VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options)
++{
++ unsigned int map;
++ unsigned int val=0,cnt,tmp;
++ unsigned int counter=0;
++ VLYNQ_INTERRUPT_CNTRL *intSetting=NULL;
++
++ /* validate arguments */
++ if( VLYNQ_OUTRANGE(pdev->clk_source, VLYNQ_CLK_SOURCE_REMOTE, VLYNQ_CLK_SOURCE_NONE) ||
++ VLYNQ_OUTRANGE(pdev->clk_div, 8, 1) )
++ {
++ return VLYNQ_INVALID_ARG;
++ }
++
++ /** perform all sanity checks first **/
++ if(pdev->state != VLYNQ_DRV_STATE_UNINIT)
++ return VLYNQ_INVALID_DRV_STATE;
++
++ /** Initialize local and remote register set addresses- additional
++ * provision to access the registers directly if need be */
++ pdev->local = (VLYNQ_REG_SET*)pdev->module_base;
++ pdev->remote = (VLYNQ_REG_SET*) (pdev->module_base + VLYNQ_REMOTE_REGS_OFFSET);
++
++ /* Detect faulty int configuration that might induce int pkt looping */
++ if ( (options & VLYNQ_INIT_LOCAL_INTERRUPTS) && (options & VLYNQ_INIT_REMOTE_INTERRUPTS) )
++ {
++ /* case when both local and remote are configured */
++ if((pdev->local_irq.intLocal== VLYNQ_INT_REMOTE ) /* interrupts transfered to remote from local */
++ && (pdev->remote_irq.intLocal== VLYNQ_INT_REMOTE) /* interrupts transfered from remote to local */
++ && ((pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) || (pdev->remote_irq.intRemote == VLYNQ_INT_ROOT_ISR)) )
++ {
++ return (VLYNQ_INT_CONFIG_ERR);
++ }
++ }
++
++ pdev->state = VLYNQ_DRV_STATE_ININIT;
++ pdev->intCount = 0;
++ pdev->isrCount = 0;
++
++ /*** Its assumed that the vlynq module has been brought out of reset
++ * before invocation of vlynq_init. Since, this operation is board specific
++ * it must be handled outside this generic driver */
++
++ /* Assert reset the remote device, call reset_cb,
++ * reset CB holds Reset according to the device needs. */
++ VLYNQ_RESETCB(VLYNQ_RESET_ASSERT);
++
++ /* Handle VLYNQ clock, HW default (Sense On Reset) is
++ * usually input for all the devices. */
++ if (options & VLYNQ_INIT_CONFIG_CLOCK)
++ {
++ vlynq_configClock(pdev);
++ }
++
++ /* Call reset_cb again. It will release the remote device
++ * from reset, and wait for a while. */
++ VLYNQ_RESETCB(VLYNQ_RESET_DEASSERT);
++
++ if(options & VLYNQ_INIT_CHECK_LINK )
++ {
++ /* Check for link up during initialization*/
++ while( counter < 25 )
++ {
++ /* loop around giving a chance for link status to settle down */
++ counter++;
++ if(vlynq_link_check(pdev))
++ {
++ /* Link is up exit loop*/
++ break;
++ }
++
++ vlynq_delay(4000);
++ }/*end of while counter loop */
++
++ if(!vlynq_link_check(pdev))
++ {
++ /* Handle this case as abort */
++ pdev->state = VLYNQ_DRV_STATE_ERROR;
++ VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
++ return VLYNQ_LINK_DOWN;
++ }/* end of if not vlynq_link_check conditional block */
++
++ }/*end of if options & VLYNQ_INIT_CHECK_LINK conditional block */
++
++
++ if (options & VLYNQ_INIT_LOCAL_MEM_REGIONS)
++ {
++ /* Initialise local memory regions . This initialization lets
++ * the local host access remote device memory regions*/
++ int i;
++
++ /* configure the VLYNQ portal window to a PHYSICAL
++ * address of the local CPU */
++ VLYNQ_ALIGN4(pdev->local_mem.Txmap);
++ VLYNQ_TXMAP_REG = (pdev->local_mem.Txmap);
++
++ /*This code assumes input parameter is itself a physical address */
++ for(i=0; i < VLYNQ_MAX_MEMORY_REGIONS ; i++)
++ {
++ /* Physical address on the remote */
++ map = i+1;
++ VLYNQ_R_RXMAP_SIZE_REG(map) = 0;
++ if( pdev->remote_mem.RxSize[i])
++ {
++ VLYNQ_ALIGN4(pdev->remote_mem.RxOffset[i]);
++ VLYNQ_ALIGN4(pdev->remote_mem.RxSize[i]);
++ VLYNQ_R_RXMAP_OFFSET_REG(map) = pdev->remote_mem.RxOffset[i];
++ VLYNQ_R_RXMAP_SIZE_REG(map) = pdev->remote_mem.RxSize[i];
++ }
++ }
++ }
++
++ if(options & VLYNQ_INIT_REMOTE_MEM_REGIONS )
++ {
++ int i;
++
++ /* Initialise remote memory regions. This initialization lets remote
++ * device access local host memory regions. It configures the VLYNQ portal
++ * window to a PHYSICAL address of the remote */
++ VLYNQ_ALIGN4(pdev->remote_mem.Txmap);
++ VLYNQ_R_TXMAP_REG = pdev->remote_mem.Txmap;
++
++ for( i=0; i<VLYNQ_MAX_MEMORY_REGIONS; i++)
++ {
++ /* Physical address on the local */
++ map = i+1;
++ VLYNQ_RXMAP_SIZE_REG(map) = 0;
++ if( pdev->local_mem.RxSize[i])
++ {
++ VLYNQ_ALIGN4(pdev->local_mem.RxOffset[i]);
++ VLYNQ_ALIGN4(pdev->local_mem.RxSize[i]);
++ VLYNQ_RXMAP_OFFSET_REG(map) = (pdev->local_mem.RxOffset[i]);
++ VLYNQ_RXMAP_SIZE_REG(map) = (pdev->local_mem.RxSize[i]);
++ }
++ }
++ }
++
++ /* Adapted from original vlynq driver from cable - Calculate VLYNQ bus width */
++ pdev->width = 3 + VLYNQ_STATUS_FLD_WIDTH(VLYNQ_STATUS_REG)
++ + VLYNQ_STATUS_FLD_WIDTH(VLYNQ_R_STATUS_REG);
++
++ /* chance to initialize the device, e.g. to boost VLYNQ
++ * clock by modifying pdev->clk_div or and verify the width. */
++ VLYNQ_RESETCB(VLYNQ_RESET_LINKESTABLISH);
++
++ /* Handle VLYNQ clock, HW default (Sense On Reset) is
++ * usually input for all the devices. */
++ if(options & VLYNQ_INIT_CONFIG_CLOCK )
++ {
++ vlynq_configClock(pdev);
++ }
++
++ /* last check for link*/
++ if(options & VLYNQ_INIT_CHECK_LINK )
++ {
++ /* Final Check for link during initialization*/
++ while( counter < 25 )
++ {
++ /* loop around giving a chance for link status to settle down */
++ counter++;
++ if(vlynq_link_check(pdev))
++ {
++ /* Link is up exit loop*/
++ break;
++ }
++
++ vlynq_delay(4000);
++ }/*end of while counter loop */
++
++ if(!vlynq_link_check(pdev))
++ {
++ /* Handle this case as abort */
++ pdev->state = VLYNQ_DRV_STATE_ERROR;
++ VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
++ return VLYNQ_LINK_DOWN;
++ }/* end of if not vlynq_link_check conditional block */
++
++ } /* end of if options & VLYNQ_INIT_CHECK_LINK */
++
++ if(options & VLYNQ_INIT_LOCAL_INTERRUPTS )
++ {
++ /* Configure local interrupt settings */
++ intSetting = &(pdev->local_irq);
++
++ /* Map local module status interrupts to interrupt vector*/
++ val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
++
++ /* enable local module status interrupts */
++ val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
++
++ if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
++ {
++ /*set the intLocal bit*/
++ val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
++ }
++
++ /* Irrespective of whether interrupts are handled locally, program
++ * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
++ * i.e remote packets are set intPending register->which will result in
++ * same packet being sent out) has been done already
++ */
++
++ if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
++ {
++ /* Set the int2Cfg register, so that remote interrupt
++ * packets are written to intPending register */
++ val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
++
++ /* Set intPtr register to point to intPending register */
++ VLYNQ_INT_PTR_REG = VLYNQ_INT_PENDING_REG_PTR ;
++ }
++ else
++ {
++ /*set the interrupt pointer register*/
++ VLYNQ_INT_PTR_REG = intSetting->intr_ptr;
++ /* Dont bother to modify int2Cfg as it would be zero */
++ }
++
++ /** Clear bits related to INT settings in control register **/
++ VLYNQ_CTRL_REG = VLYNQ_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
++
++ /** Or the bits to be set with Control register **/
++ VLYNQ_CTRL_REG = VLYNQ_CTRL_REG | val;
++
++ /* initialise local ICB */
++ if(vlynqInterruptInit(pdev)==VLYNQ_MEMALLOC_FAIL)
++ return VLYNQ_MEMALLOC_FAIL;
++
++ /* Install handler for local module status interrupts. By default when
++ * local interrupt setting is initialised, the local module status are
++ * enabled and handler hooked up */
++ if(vlynq_install_isr(pdev, intSetting->map_vector, vlynq_local_module_isr,
++ pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
++ return VLYNQ_INVALID_ARG;
++ } /* end of init local interrupts */
++
++ if(options & VLYNQ_INIT_REMOTE_INTERRUPTS )
++ {
++ /* Configure remote interrupt settings from configuration */
++ intSetting = &(pdev->remote_irq);
++
++ /* Map remote module status interrupts to remote interrupt vector*/
++ val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
++ /* enable remote module status interrupts */
++ val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
++
++ if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
++ {
++ /*set the intLocal bit*/
++ val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
++ }
++
++ /* Irrespective of whether interrupts are handled locally, program
++ * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
++ * i.e remote packets are set intPending register->which will result in
++ * same packet being sent out) has been done already
++ */
++
++ if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
++ {
++ /* Set the int2Cfg register, so that remote interrupt
++ * packets are written to intPending register */
++ val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
++ /* Set intPtr register to point to intPending register */
++ VLYNQ_R_INT_PTR_REG = VLYNQ_R_INT_PENDING_REG_PTR ;
++ }
++ else
++ {
++ /*set the interrupt pointer register*/
++ VLYNQ_R_INT_PTR_REG = intSetting->intr_ptr;
++ /* Dont bother to modify int2Cfg as it would be zero */
++ }
++
++ if( (intSetting->intLocal == VLYNQ_INT_REMOTE) &&
++ (options & VLYNQ_INIT_LOCAL_INTERRUPTS) &&
++ (pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) )
++ {
++ /* Install handler for remote module status interrupts. By default when
++ * remote interrupts are forwarded to local root_isr then remote_module_isr is
++ * enabled and handler hooked up */
++ if(vlynq_install_isr(pdev,intSetting->map_vector,vlynq_remote_module_isr,
++ pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
++ return VLYNQ_INVALID_ARG;
++ }
++
++
++ /** Clear bits related to INT settings in control register **/
++ VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
++
++ /** Or the bits to be set with the remote Control register **/
++ VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG | val;
++
++ } /* init remote interrupt settings*/
++
++ if(options & VLYNQ_INIT_CLEAR_ERRORS )
++ {
++ /* Clear errors during initialization */
++ tmp = VLYNQ_STATUS_REG & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
++ VLYNQ_STATUS_REG = tmp;
++ tmp = VLYNQ_R_STATUS_REG & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
++ VLYNQ_R_STATUS_REG = tmp;
++ }
++
++ /* clear int status */
++ val = VLYNQ_INT_STAT_REG;
++ VLYNQ_INT_STAT_REG = val;
++
++ /* finish initialization */
++ pdev->state = VLYNQ_DRV_STATE_RUN;
++ VLYNQ_RESETCB( VLYNQ_RESET_INITOK);
++ return VLYNQ_SUCCESS;
++
++}
++
++
++/* ----------------------------------------------------------------------------
++ * Function : vlynqInterruptInit()
++ * Description: This local function is used to set up the ICB table for the
++ * VLYNQ_STATUS_REG vlynq module. The input parameter "pdev" points the vlynq
++ * device instance whose ICB is allocated.
++ * Return : returns VLYNQ_SUCCESS or vlynq error for failure
++ * -----------------------------------------------------------------------------
++ */
++static int vlynqInterruptInit(VLYNQ_DEV *pdev)
++{
++ int i, numslots;
++
++ /* Memory allocated statically.
++ * Initialise ICB,free list.Indicate primary slot empty.
++ * Intialise intVector <==> map_vector translation table*/
++ for(i=0; i < VLYNQ_NUM_INT_BITS; i++)
++ {
++ pdev->pIntrCB[i].isr = NULL;
++ pdev->pIntrCB[i].next = NULL; /*nothing chained */
++ pdev->vector_map[i] = -1; /* indicates unmapped */
++ }
++
++ /* In the ICB slots, [VLYNQ_NUM_INT_BITS i.e 32 to ICB array size) are expansion slots
++ * required only when interrupt chaining/sharing is supported. In case
++ * of chained interrupts the list starts from primary slot and the
++ * additional slots are obtained from the common free area */
++
++ /* Initialise freelist */
++
++ numslots = VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS;
++
++ if (numslots > VLYNQ_NUM_INT_BITS)
++ {
++ pdev->freelist = &(pdev->pIntrCB[VLYNQ_NUM_INT_BITS]);
++
++ for(i = VLYNQ_NUM_INT_BITS; i < (numslots-1) ; i++)
++ {
++ pdev->pIntrCB[i].next = &(pdev->pIntrCB[i+1]);
++ pdev->pIntrCB[i].isr = NULL;
++ }
++ pdev->pIntrCB[i].next=NULL; /* Indicate end of freelist*/
++ pdev->pIntrCB[i].isr=NULL;
++ }
++ else
++ {
++ pdev->freelist = NULL;
++ }
++
++ /** Reset mapping for IV 0-7 **/
++ VLYNQ_IVR_03TO00_REG = 0;
++ VLYNQ_IVR_07TO04_REG = 0;
++
++ return VLYNQ_SUCCESS;
++}
++
++/** remember that hooking up of root ISR handler with the interrupt controller
++ * is not done as a part of this driver. Typically, it must be done after
++ * invoking vlynq_init*/
++
++
++ /* ----------------------------------------------------------------------------
++ * ISR with the SOC interrupt controller. This ISR typically scans
++ * the Int PENDING/SET register in the VLYNQ module and calls the
++ * appropriate ISR associated with the correponding vector number.
++ * -----------------------------------------------------------------------------
++ */
++void vlynq_root_isr(void *arg)
++{
++ int source; /* Bit position of pending interrupt, start from 0 */
++ unsigned int interrupts, clrInterrupts;
++ VLYNQ_DEV * pdev;
++ VLYNQ_INTR_CNTRL_ICB *entry;
++
++ pdev=(VLYNQ_DEV*)(arg); /*obtain the vlynq device pointer*/
++
++ interrupts = VLYNQ_INT_STAT_REG; /* Get the list of pending interrupts */
++ VLYNQ_INT_STAT_REG = interrupts; /* clear the int CR register */
++ clrInterrupts = interrupts; /* save them for further analysis */
++
++ debugPrint("vlynq_root_isr: dev %u. INTCR = 0x%08lx\n", pdev->dev_idx, clrInterrupts,0,0,0,0);
++
++ /* Scan interrupt bits */
++ source =0;
++ while( clrInterrupts != 0)
++ {
++ /* test if bit is set? */
++ if( 0x1ul & clrInterrupts)
++ {
++ entry = &(pdev->pIntrCB[source]); /* Get the ISR entry */
++ pdev->intCount++; /* update interrupt count */
++ if(entry->isr != NULL)
++ {
++ do
++ {
++ pdev->isrCount++; /* update isr invocation count */
++ /* Call the user ISR and update the count for ISR */
++ entry->isrCount++;
++ entry->isr(entry->arg1, entry->arg2, entry->arg3);
++ if (entry->next == NULL) break;
++ entry = entry->next;
++
++ } while (entry->isr != NULL);
++ }
++ else
++ {
++ debugPrint(" ISR not installed for vlynq vector:%d\n",source,0,0,0,0,0);
++ }
++ }
++ clrInterrupts >>= 1; /* Next source bit */
++ ++source;
++ } /* endWhile clrInterrupts != 0 */
++}
++
++
++ /* ----------------------------------------------------------------------------
++ * Function : vlynq_local__module_isr()
++ * Description: This ISR is attached to the local VLYNQ interrupt vector
++ * by the Vlynq Driver when local interrupts are being handled. i.e.
++ * intLocal=1. This ISR handles local Vlynq module status interrupts only
++ * AS a part of this ISR, user callback in VLYNQ_DEV structure
++ * is invoked.
++ * VLYNQ_DEV is passed as arg1. arg2 and arg3 are unused.
++ * -----------------------------------------------------------------------------
++ */
++static void vlynq_local_module_isr(void *arg1,void *arg2, void *arg3)
++{
++ VLYNQ_REPORT_CB func;
++ unsigned int dwStatRegVal;
++ VLYNQ_DEV * pdev;
++
++ pdev = (VLYNQ_DEV*) arg1;
++ /* Callback function is read from the device pointer that is passed as an argument */
++ func = pdev->report_cb;
++
++ /* read local status register */
++ dwStatRegVal = VLYNQ_STATUS_REG;
++
++ /* clear pending events */
++ VLYNQ_STATUS_REG = dwStatRegVal;
++
++ /* invoke user callback */
++ if( func != NULL)
++ func( pdev, VLYNQ_LOCAL_DVC, dwStatRegVal);
++
++}
++
++ /* ----------------------------------------------------------------------------
++ * Function : vlynq_remote_module_isr()
++ * Description: This ISR is attached to the remote VLYNQ interrupt vector
++ * by the Vlynq Driver when remote interrupts are being handled locally. i.e.
++ * intLocal=1. This ISR handles local Vlynq module status interrupts only
++ * AS a part of this ISR, user callback in VLYNQ_DEV structure
++ * is invoked.
++ * The parameters irq,regs ar unused.
++ * -----------------------------------------------------------------------------
++ */
++static void vlynq_remote_module_isr(void *arg1,void *arg2, void *arg3)
++{
++ VLYNQ_REPORT_CB func;
++ unsigned int dwStatRegVal;
++ VLYNQ_DEV * pdev;
++
++
++ pdev = (VLYNQ_DEV*) arg1;
++
++ /* Callback function is read from the device pointer that is passed as an argument */
++ func = pdev->report_cb;
++
++ /* read local status register */
++ dwStatRegVal = VLYNQ_R_STATUS_REG;
++
++ /* clear pending events */
++ VLYNQ_R_STATUS_REG = dwStatRegVal;
++
++ /* invoke user callback */
++ if( func != NULL)
++ func( pdev, VLYNQ_REMOTE_DVC, dwStatRegVal);
++
++}
++
++/* ----------------------------------------------------------------------------
++ * Function : vlynq_interrupt_get_count()
++ * Description: This function returns the number of times a particular intr
++ * has been invoked.
++ *
++ * It returns 0, if erroneous map_vector is specified or if the corres isr
++ * has not been registered with VLYNQ.
++ */
++unsigned int vlynq_interrupt_get_count(VLYNQ_DEV *pdev,
++ unsigned int map_vector)
++{
++ VLYNQ_INTR_CNTRL_ICB *entry;
++ unsigned int count = 0;
++
++ if (map_vector > (VLYNQ_NUM_INT_BITS-1))
++ return count;
++
++ entry = &(pdev->pIntrCB[map_vector]);
++
++ if (entry)
++ count = entry->isrCount;
++
++ return (count);
++}
++
++
++/* ----------------------------------------------------------------------------
++ * Function : vlynq_install_isr()
++ * Description: This function installs ISR for Vlynq interrupt vector
++ * bits(in IntPending register). This function should be used only when
++ * Vlynq interrupts are being handled locally(remote may be programmed to send
++ * interrupt packets).Also, the int2cfg should be 1 and the least significant
++ * 8 bits of the Interrupt Pointer Register must point to Interrupt
++ * Pending/Set Register).
++ * If host int2cfg=0 and the Interrupt Pointer register contains
++ * the address of the interrupt set register in the interrupt controller
++ * module of the local device , then the ISR for the remote interrupt must be
++ * directly registered with the Interrupt controller and must not use this API
++ * Note: this function simply installs the ISR in ICB It doesnt modify
++ * any register settings
++ */
++int
++vlynq_install_isr(VLYNQ_DEV *pdev,
++ unsigned int map_vector,
++ VLYNQ_INTR_CNTRL_ISR isr,
++ void *arg1, void *arg2, void *arg3)
++{
++ VLYNQ_INTR_CNTRL_ICB *entry;
++
++ if ( (map_vector > (VLYNQ_NUM_INT_BITS-1)) || (isr == NULL) )
++ return VLYNQ_INVALID_ARG;
++
++ entry = &(pdev->pIntrCB[map_vector]);
++
++ if(entry->isr == NULL)
++ {
++ entry->isr = isr;
++ entry->arg1 = arg1;
++ entry->arg2 = arg2;
++ entry->arg3 = arg3;
++ entry->next = NULL;
++ }
++ else
++ {
++ /** No more empty slots,return error */
++ if(pdev->freelist == NULL)
++ return VLYNQ_MEMALLOC_FAIL;
++
++ while(entry->next != NULL)
++ {
++ entry = entry->next;
++ }
++
++ /* Append new node to the chain */
++ entry->next = pdev->freelist;
++ /* Remove the appended node from freelist */
++ pdev->freelist = pdev->freelist->next;
++ entry= entry->next;
++
++ /*** Set the ICB fields ***/
++ entry->isr = isr;
++ entry->arg1 = arg1;
++ entry->arg2 = arg2;
++ entry->arg3 = arg3;
++ entry->next = NULL;
++ }
++
++ return VLYNQ_SUCCESS;
++}
++
++
++
++/* ----------------------------------------------------------------------------
++ * Function : vlynq_uninstall_isr
++ * Description: This function is used to uninstall a previously
++ * registered ISR. In case of shared/chained interrupts, the
++ * void * arg parameter must uniquely identify the ISR to be
++ * uninstalled.
++ * Note: this function simply uninstalls the ISR in ICB
++ * It doesnt modify any register settings
++ */
++int
++vlynq_uninstall_isr(VLYNQ_DEV *pdev,
++ unsigned int map_vector,
++ void *arg1, void *arg2, void *arg3)
++{
++ VLYNQ_INTR_CNTRL_ICB *entry,*temp;
++
++ if (map_vector > (VLYNQ_NUM_INT_BITS-1))
++ return VLYNQ_INVALID_ARG;
++
++ entry = &(pdev->pIntrCB[map_vector]);
++
++ if(entry->isr == NULL )
++ return VLYNQ_ISR_NON_EXISTENT;
++
++ if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
++ {
++ if(entry->next == NULL)
++ {
++ entry->isr=NULL;
++ return VLYNQ_SUCCESS;
++ }
++ else
++ {
++ temp = entry->next;
++ /* Copy next node in the chain to prim.slot */
++ entry->isr = temp->isr;
++ entry->arg1 = temp->arg1;
++ entry->arg2 = temp->arg2;
++ entry->arg3 = temp->arg3;
++ entry->next = temp->next;
++ /* Free the just copied node */
++ temp->isr = NULL;
++ temp->arg1 = NULL;
++ temp->arg2 = NULL;
++ temp->arg3 = NULL;
++ temp->next = pdev->freelist;
++ pdev->freelist = temp;
++ return VLYNQ_SUCCESS;
++ }
++ }
++ else
++ {
++ temp = entry;
++ while ( (entry = temp->next) != NULL)
++ {
++ if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
++ {
++ /* remove node from chain */
++ temp->next = entry->next;
++ /* Add the removed node to freelist */
++ entry->isr = NULL;
++ entry->arg1 = NULL;
++ entry->arg2 = NULL;
++ entry->arg3 = NULL;
++ entry->next = pdev->freelist;
++ entry->isrCount = 0;
++ pdev->freelist = entry;
++ return VLYNQ_SUCCESS;
++ }
++ temp = entry;
++ }
++
++ return VLYNQ_ISR_NON_EXISTENT;
++ }
++}
++
++
++
++
++/* ----------------------------------------------------------------------------
++ * function : vlynq_interrupt_vector_set()
++ * description:configures interrupt vector mapping,interrupt type
++ * polarity -all in one go.
++ */
++int
++vlynq_interrupt_vector_set(VLYNQ_DEV *pdev, /* vlynq device */
++ unsigned int int_vector, /* int vector on vlynq device */
++ unsigned int map_vector, /* bit for this interrupt */
++ VLYNQ_DEV_TYPE dev_type, /* local or remote device */
++ VLYNQ_INTR_POLARITY pol, /* polarity of interrupt */
++ VLYNQ_INTR_TYPE type) /* pulsed/level interrupt */
++{
++ volatile unsigned int * vecreg;
++ unsigned int val=0;
++ unsigned int bytemask=0XFF;
++
++ /* use the lower 8 bits of val to set the value , shift it to
++ * appropriate byte position in the ivr and write it to the
++ * corresponding register */
++
++ /* validate the number of interrupts supported */
++ if (int_vector >= VLYNQ_IVR_MAXIVR)
++ return VLYNQ_INVALID_ARG;
++
++ if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
++ return VLYNQ_INVALID_ARG;
++
++ if (dev_type == VLYNQ_LOCAL_DVC)
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
++ }
++ else
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
++ }
++
++ /* Update the intVector<==> bit position translation table */
++ pdev->vector_map[map_vector] = int_vector;
++
++ /* val has been initialised to zero. we only have to turn on appropriate bits*/
++ if(type == VLYNQ_INTR_PULSED)
++ val |= VLYNQ_IVR_INTTYPE_MASK;
++
++ if(pol == VLYNQ_INTR_ACTIVE_LOW)
++ val |= VLYNQ_IVR_INTPOL_MASK;
++
++ val |= map_vector;
++
++ /** clear the correct byte position and then or val **/
++ *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
++
++ /** write to correct byte position in vecreg*/
++ *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
++
++ /* Setting a interrupt vector, leaves the interrupt disabled
++ * which must be enabled subsequently */
++
++ return VLYNQ_SUCCESS;
++}
++
++
++/* ----------------------------------------------------------------------------
++ * Function : vlynq_interrupt_vector_cntl()
++ * Description:enables/disable interrupt
++ */
++int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
++ unsigned int int_vector,
++ VLYNQ_DEV_TYPE dev_type,
++ unsigned int enable)
++{
++ volatile unsigned int *vecReg;
++ unsigned int val=0;
++ unsigned int intenMask=0x80;
++
++ /* validate the number of interrupts supported */
++ if (int_vector >= VLYNQ_IVR_MAXIVR)
++ return VLYNQ_INVALID_ARG;
++
++ if (dev_type == VLYNQ_LOCAL_DVC)
++ {
++ vecReg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
++ }
++ else
++ {
++ vecReg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
++ }
++
++ /** Clear the correct byte position and then or val **/
++ *vecReg = (*vecReg) & ( ~(intenMask << ( (int_vector %4)*8) ) );
++
++ if(enable)
++ {
++ val |= VLYNQ_IVR_INTEN_MASK;
++ /** Write to correct byte position in vecReg*/
++ *vecReg = (*vecReg) | (val << ( (int_vector % 4)*8) ) ;
++ }
++
++ return VLYNQ_SUCCESS;
++
++}/* end of function vlynq_interrupt_vector_cntl */
++
++
++
++/* ----------------------------------------------------------------------------
++ * Function : vlynq_interrupt_vector_map()
++ * Description:Configures interrupt vector mapping alone
++ */
++int
++vlynq_interrupt_vector_map( VLYNQ_DEV *pdev,
++ VLYNQ_DEV_TYPE dev_type,
++ unsigned int int_vector,
++ unsigned int map_vector)
++{
++ volatile unsigned int * vecreg;
++ unsigned int val=0;
++ unsigned int bytemask=0x1f; /* mask to turn off bits corresponding to int vector */
++
++ /* use the lower 8 bits of val to set the value , shift it to
++ * appropriate byte position in the ivr and write it to the
++ * corresponding register */
++
++ /* validate the number of interrupts supported */
++ if (int_vector >= VLYNQ_IVR_MAXIVR)
++ return VLYNQ_INVALID_ARG;
++
++ if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
++ return VLYNQ_INVALID_ARG;
++
++ if (dev_type == VLYNQ_LOCAL_DVC)
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
++ }
++ else
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
++ }
++
++ /* Update the intVector<==> bit position translation table */
++ pdev->vector_map[map_vector] = int_vector;
++
++ /** val has been initialised to zero. we only have to turn on
++ * appropriate bits*/
++ val |= map_vector;
++
++ /** clear the correct byte position and then or val **/
++ *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
++
++ /** write to correct byte position in vecreg*/
++ *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
++
++ return VLYNQ_SUCCESS;
++}
++
++
++/* ----------------------------------------------------------------------------
++ * function : vlynq_interrupt_set_polarity()
++ * description:configures interrupt polarity .
++ */
++int
++vlynq_interrupt_set_polarity( VLYNQ_DEV *pdev ,
++ VLYNQ_DEV_TYPE dev_type,
++ unsigned int map_vector,
++ VLYNQ_INTR_POLARITY pol)
++{
++ volatile unsigned int * vecreg;
++ int int_vector;
++ unsigned int val=0;
++ unsigned int bytemask=0x20; /** mask to turn off bits corresponding to int polarity */
++
++ /* get the int_vector from map_vector */
++ int_vector = pdev->vector_map[map_vector];
++
++ if(int_vector == -1)
++ return VLYNQ_INTVEC_MAP_NOT_FOUND;
++
++ /* use the lower 8 bits of val to set the value , shift it to
++ * appropriate byte position in the ivr and write it to the
++ * corresponding register */
++
++ if (dev_type == VLYNQ_LOCAL_DVC)
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
++ }
++ else
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
++ }
++
++ /* val has been initialised to zero. we only have to turn on
++ * appropriate bits, if need be*/
++
++ /** clear the correct byte position and then or val **/
++ *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
++
++ if( pol == VLYNQ_INTR_ACTIVE_LOW)
++ {
++ val |= VLYNQ_IVR_INTPOL_MASK;
++ /** write to correct byte position in vecreg*/
++ *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
++ }
++
++ return VLYNQ_SUCCESS;
++}
++
++int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
++ VLYNQ_DEV_TYPE dev_type,
++ unsigned int map_vector)
++{
++ volatile unsigned int * vecreg;
++ int int_vector;
++ unsigned int val=0;
++
++ /* get the int_vector from map_vector */
++ int_vector = pdev->vector_map[map_vector];
++
++ if (map_vector > (VLYNQ_NUM_INT_BITS-1))
++ return(-1);
++
++ if(int_vector == -1)
++ return VLYNQ_INTVEC_MAP_NOT_FOUND;
++
++ /* use the lower 8 bits of val to set the value , shift it to
++ * appropriate byte position in the ivr and write it to the
++ * corresponding register */
++
++ if (dev_type == VLYNQ_LOCAL_DVC)
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
++ }
++ else
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
++ }
++
++ /** read the information into val **/
++ val = (*vecreg) & ((VLYNQ_IVR_INTPOL_MASK << ( (int_vector %4)*8) ) );
++
++ return (val ? (VLYNQ_INTR_ACTIVE_LOW) : (VLYNQ_INTR_ACTIVE_HIGH));
++}
++
++
++/* ----------------------------------------------------------------------------
++ * function : vlynq_interrupt_set_type()
++ * description:configures interrupt type .
++ */
++int vlynq_interrupt_set_type( VLYNQ_DEV *pdev,
++ VLYNQ_DEV_TYPE dev_type,
++ unsigned int map_vector,
++ VLYNQ_INTR_TYPE type)
++{
++ volatile unsigned int * vecreg;
++ unsigned int val=0;
++ int int_vector;
++
++ /** mask to turn off bits corresponding to interrupt type */
++ unsigned int bytemask=0x40;
++
++ /* get the int_vector from map_vector */
++ int_vector = pdev->vector_map[map_vector];
++ if(int_vector == -1)
++ return VLYNQ_INTVEC_MAP_NOT_FOUND;
++
++ /* use the lower 8 bits of val to set the value , shift it to
++ * appropriate byte position in the ivr and write it to the
++ * corresponding register */
++ if (dev_type == VLYNQ_LOCAL_DVC)
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
++ }
++ else
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
++ }
++
++ /** val has been initialised to zero. we only have to turn on
++ * appropriate bits if need be*/
++
++ /** clear the correct byte position and then or val **/
++ *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
++
++ if( type == VLYNQ_INTR_PULSED)
++ {
++ val |= VLYNQ_IVR_INTTYPE_MASK;
++ /** write to correct byte position in vecreg*/
++ *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
++ }
++
++ return VLYNQ_SUCCESS;
++}
++
++/* ----------------------------------------------------------------------------
++ * function : vlynq_interrupt_get_type()
++ * description:returns interrupt type .
++ */
++int vlynq_interrupt_get_type( VLYNQ_DEV *pdev, VLYNQ_DEV_TYPE dev_type,
++ unsigned int map_vector)
++{
++ volatile unsigned int * vecreg;
++ unsigned int val=0;
++ int int_vector;
++
++ if (map_vector > (VLYNQ_NUM_INT_BITS-1))
++ return(-1);
++
++ /* get the int_vector from map_vector */
++ int_vector = pdev->vector_map[map_vector];
++ if(int_vector == -1)
++ return VLYNQ_INTVEC_MAP_NOT_FOUND;
++
++ /* use the lower 8 bits of val to set the value , shift it to
++ * appropriate byte position in the ivr and write it to the
++ * corresponding register */
++ if (dev_type == VLYNQ_LOCAL_DVC)
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
++ }
++ else
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
++ }
++
++ /** Read the correct bit position into val **/
++ val = (*vecreg) & ((VLYNQ_IVR_INTTYPE_MASK << ( (int_vector %4)*8) ) );
++
++ return (val ? (VLYNQ_INTR_PULSED) : (VLYNQ_INTR_LEVEL));
++}
++
++/* ----------------------------------------------------------------------------
++ * function : vlynq_interrupt_enable()
++ * description:Enable interrupt by writing to IVR register.
++ */
++int vlynq_interrupt_enable( VLYNQ_DEV *pdev,
++ VLYNQ_DEV_TYPE dev_type,
++ unsigned int map_vector)
++{
++ volatile unsigned int * vecreg;
++ unsigned int val=0;
++ int int_vector;
++
++ /** mask to turn off bits corresponding to interrupt enable */
++ unsigned int bytemask=0x80;
++
++ /* get the int_vector from map_vector */
++ int_vector = pdev->vector_map[map_vector];
++ if(int_vector == -1)
++ return VLYNQ_INTVEC_MAP_NOT_FOUND;
++
++ /* use the lower 8 bits of val to set the value , shift it to
++ * appropriate byte position in the ivr and write it to the
++ * corresponding register */
++
++ if (dev_type == VLYNQ_LOCAL_DVC)
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
++ }
++ else
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
++ }
++
++ /** val has been initialised to zero. we only have to turn on
++ * bit corresponding to interrupt enable*/
++ val |= VLYNQ_IVR_INTEN_MASK;
++
++ /** clear the correct byte position and then or val **/
++ *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
++
++ /** write to correct byte position in vecreg*/
++ *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
++
++ return VLYNQ_SUCCESS;
++}
++
++
++/* ----------------------------------------------------------------------------
++ * function : vlynq_interrupt_disable()
++ * description:Disable interrupt by writing to IVR register.
++ */
++int
++vlynq_interrupt_disable( VLYNQ_DEV *pdev,
++ VLYNQ_DEV_TYPE dev_type,
++ unsigned int map_vector)
++{
++ volatile unsigned int * vecreg;
++ int int_vector;
++
++ /** mask to turn off bits corresponding to interrupt enable */
++ unsigned int bytemask=0x80;
++
++ /* get the int_vector from map_vector */
++ int_vector = pdev->vector_map[map_vector];
++ if(int_vector == -1)
++ return VLYNQ_INTVEC_MAP_NOT_FOUND;
++
++ /* use the lower 8 bits of val to set the value , shift it to
++ * appropriate byte position in the ivr and write it to the
++ * corresponding register */
++ if (dev_type == VLYNQ_LOCAL_DVC)
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
++ }
++ else
++ {
++ vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
++ }
++
++ /* We disable the interrupt by simply turning off the bit
++ * corresponding to Interrupt enable.
++ * Clear the interrupt enable bit in the correct byte position **/
++ *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
++
++ /* Dont have to set any bit positions */
++
++ return VLYNQ_SUCCESS;
++
++}
++
++
++
++
+diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
+--- linux.old/drivers/char/serial.c 2005-10-21 16:43:20.709226000 +0200
++++ linux.dev/drivers/char/serial.c 2005-11-10 01:10:46.015585250 +0100
+@@ -419,7 +419,40 @@
+ return 0;
+ }
+
+-#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
++#if defined(CONFIG_AR7)
++
++static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
++{
++ return (inb(info->port + (offset * 4)) & 0xff);
++}
++
++
++static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
++{
++#ifdef CONFIG_SERIAL_NOPAUSE_IO
++ return (inb(info->port + (offset * 4)) & 0xff);
++#else
++ return (inb_p(info->port + (offset * 4)) & 0xff);
++#endif
++}
++
++static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
++{
++ outb(value, info->port + (offset * 4));
++}
++
++
++static _INLINE_ void serial_outp(struct async_struct *info, int offset,
++ int value)
++{
++#ifdef CONFIG_SERIAL_NOPAUSE_IO
++ outb(value, info->port + (offset * 4));
++#else
++ outb_p(value, info->port + (offset * 4));
++#endif
++}
++
++#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
+
+ #include <asm/mips-boards/atlas.h>
+
+@@ -478,8 +511,10 @@
+ * needed for certain old 386 machines, I've left these #define's
+ * in....
+ */
++#ifndef CONFIG_AR7
+ #define serial_inp(info, offset) serial_in(info, offset)
+ #define serial_outp(info, offset, value) serial_out(info, offset, value)
++#endif
+
+
+ /*
+@@ -1728,7 +1763,15 @@
+ /* Special case since 134 is really 134.5 */
+ quot = (2*baud_base / 269);
+ else if (baud)
++#ifdef CONFIG_AR7
++ quot = (CONFIG_AR7_SYS*500000) / baud;
++
++ if ((quot%16)>7)
++ quot += 8;
++ quot /=16;
++#else
+ quot = baud_base / baud;
++#endif
+ }
+ /* If the quotient is zero refuse the change */
+ if (!quot && old_termios) {
+@@ -5540,8 +5583,10 @@
+ state->irq = irq_cannonicalize(state->irq);
+ if (state->hub6)
+ state->io_type = SERIAL_IO_HUB6;
++#ifndef CONFIG_AR7
+ if (state->port && check_region(state->port,8))
+ continue;
++#endif
+ #ifdef CONFIG_MCA
+ if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
+ continue;
+@@ -5997,7 +6042,15 @@
+ info->io_type = state->io_type;
+ info->iomem_base = state->iomem_base;
+ info->iomem_reg_shift = state->iomem_reg_shift;
++#ifdef CONFIG_AR7
++ quot = (CONFIG_AR7_SYS*500000) / baud;
++
++ if ((quot%16)>7)
++ quot += 8;
++ quot /=16;
++#else
+ quot = state->baud_base / baud;
++#endif
+ cval = cflag & (CSIZE | CSTOPB);
+ #if defined(__powerpc__) || defined(__alpha__)
+ cval >>= 8;
+diff -urN linux.old/drivers/char/ticfg/Makefile linux.dev/drivers/char/ticfg/Makefile
+--- linux.old/drivers/char/ticfg/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/char/ticfg/Makefile 2005-11-10 01:10:46.051587500 +0100
+@@ -0,0 +1,6 @@
++
++O_TARGET := ticfg.o
++
++obj-$(CONFIG_AR7_ADAM2) := adam2_env.o
++
++include $(TOPDIR)/Rules.make
+diff -urN linux.old/drivers/char/ticfg/adam2_env.c linux.dev/drivers/char/ticfg/adam2_env.c
+--- linux.old/drivers/char/ticfg/adam2_env.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/char/ticfg/adam2_env.c 2005-11-10 01:10:46.051587500 +0100
+@@ -0,0 +1,85 @@
++#include <linux/types.h>
++#include <linux/errno.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/proc_fs.h>
++#include <linux/fcntl.h>
++#include <linux/init.h>
++
++#include <asm/ar7/adam2_env.h>
++
++#undef ADAM2_ENV_DEBUG
++
++#ifdef ADAM2_ENV_DEBUG
++#define DPRINTK(args...) do { printk(args); } while(0);
++#else
++#define DPRINTK(args...) do { } while(0);
++#endif
++
++#define ADAM2_ENV_DIR "ticfg"
++#define ADAM2_ENV_NAME "env"
++
++static struct proc_dir_entry *adam2_env_proc_dir;
++static struct proc_dir_entry *adam2_env_proc_ent;
++
++static int
++adam2_proc_read_env(char *page, char **start, off_t pos, int count,
++ int *eof, void *data)
++{
++ int len;
++ t_env_var *env;
++
++ if (pos > 0)
++ return 0;
++
++ len=0;
++ for (env = prom_iterenv(0); env; env = prom_iterenv(env)) {
++ if (env->val) {
++ /* XXX check for page len */
++ len += sprintf(page + len, "%s\t%s\n",
++ env->name, env->val);
++ }
++ }
++
++ *eof=1;
++ return len;
++}
++
++static int __init
++adam2_env_init(void)
++{
++
++ DPRINTK("%s\n", __FUNCTION__);
++
++ adam2_env_proc_dir = proc_mkdir(ADAM2_ENV_DIR, NULL);
++ if (!adam2_env_proc_dir) {
++ printk(KERN_ERR "%s: Unable to create /proc/%s entry\n",
++ __FUNCTION__, ADAM2_ENV_DIR);
++ return -ENOMEM;
++ }
++
++ adam2_env_proc_ent =
++ create_proc_entry(ADAM2_ENV_NAME, 0444, adam2_env_proc_dir);
++ if (!adam2_env_proc_ent) {
++ printk(KERN_ERR "%s: Unable to create /proc/%s/%s entry\n",
++ __FUNCTION__, ADAM2_ENV_DIR, ADAM2_ENV_NAME);
++ remove_proc_entry(ADAM2_ENV_DIR, NULL);
++ return -ENOMEM;
++ }
++ adam2_env_proc_ent->read_proc = adam2_proc_read_env;
++
++ return 0;
++}
++
++static
++void __exit
++adam2_env_cleanup(void)
++{
++ remove_proc_entry(ADAM2_ENV_NAME, adam2_env_proc_dir);
++ remove_proc_entry(ADAM2_ENV_DIR, NULL);
++}
++
++module_init(adam2_env_init);
++module_exit(adam2_env_cleanup);
++
++MODULE_LICENSE("GPL");
+diff -urN linux.old/include/asm-mips/addrspace.h linux.dev/include/asm-mips/addrspace.h
+--- linux.old/include/asm-mips/addrspace.h 2002-11-29 00:53:15.000000000 +0100
++++ linux.dev/include/asm-mips/addrspace.h 2005-11-10 01:14:16.400733500 +0100
+@@ -11,6 +11,8 @@
+ #ifndef __ASM_MIPS_ADDRSPACE_H
+ #define __ASM_MIPS_ADDRSPACE_H
+
++#include <linux/config.h>
++
+ /*
+ * Configure language
+ */
+@@ -102,4 +104,11 @@
+ #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
+ #define PHYS_TO_XKPHYS(cm,a) (0x8000000000000000 | ((cm)<<59) | (a))
+
++#ifdef CONFIG_AR7_MEMORY
++#define PHYS_OFFSET ((unsigned long)(CONFIG_AR7_MEMORY))
++#else
++#define PHYS_OFFSET (0)
++#endif
++#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
++
+ #endif /* __ASM_MIPS_ADDRSPACE_H */
+diff -urN linux.old/include/asm-mips/ar7/adam2_env.h linux.dev/include/asm-mips/ar7/adam2_env.h
+--- linux.old/include/asm-mips/ar7/adam2_env.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/adam2_env.h 2005-11-10 01:10:46.067588500 +0100
+@@ -0,0 +1,13 @@
++#ifndef _INCLUDE_ASM_AR7_ADAM2_ENV_H_
++#define _INCLUDE_ASM_AR7_ADAM2_ENV_H_
++
++/* Environment variable */
++typedef struct {
++ char *name;
++ char *val;
++} t_env_var;
++
++char *prom_getenv(char *);
++t_env_var *prom_iterenv(t_env_var *);
++
++#endif /* _INCLUDE_ASM_AR7_ADAM2_ENV_H_ */
+diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
+--- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/ar7.h 2005-11-10 01:10:46.067588500 +0100
+@@ -0,0 +1,33 @@
++/*
++ * $Id$
++ * Copyright (C) $Date$ $Author$
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ *
++ */
++
++#ifndef _AR7_H
++#define _AR7_H
++
++#include <asm/addrspace.h>
++#include <linux/config.h>
++
++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
++
++#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
++#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))
++#define AR7_BASE_BAUD ( 3686400 / 16 )
++
++#endif
+diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
+--- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-11-10 01:10:46.067588500 +0100
+@@ -0,0 +1,292 @@
++ /*
++ * Nitin Dhingra, iamnd@ti.com
++ * Copyright (C) 2000 Texas Instruments Inc.
++ *
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Defines of the Sead board specific address-MAP, registers, etc.
++ *
++ */
++#ifndef _AVALANCHE_INTC_H
++#define _AVALANCHE_INTC_H
++
++#include <linux/config.h>
++
++/* ----- */
++
++#define KSEG1_BASE 0xA0000000
++#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
++#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
++#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
++#define AVALANCHE_INTC_BASE PHYS_TO_K1(0x08612400)
++
++/* ----- */
++
++#define MIPS_EXCEPTION_OFFSET 8
++
++/******************************************************************************
++ Avalanche Interrupt number
++******************************************************************************/
++#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
++
++/*******************************************************************************
++*Linux Interrupt number
++*******************************************************************************/
++#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
++
++
++
++#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
++#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
++
++#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
++#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
++
++#define AVALANCHE_INTC_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
++ AVINTNUM(AVALANCHE_INT_END_SECONDARY) + \
++ MIPS_EXCEPTION_OFFSET)
++
++#if defined(CONFIG_AR7_VLYNQ)
++#define AVALANCHE_INT_END_LOW_VLYNQ (AVALANCHE_INTC_END + 32)
++#define AVALANCHE_INT_END_VLYNQ (AVALANCHE_INTC_END + 32 * CONFIG_AR7_VLYNQ_PORTS)
++#define AVALANCHE_INT_END AVALANCHE_INT_END_VLYNQ
++#else
++#define AVALANCHE_INT_END AVALANCHE_INTC_END
++#endif
++
++
++/*
++ * Avalanche interrupt controller register base (primary)
++ */
++#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
++
++/******************************************************************************
++ * Avalanche exception controller register base (secondary)
++ ******************************************************************************/
++#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
++
++
++/******************************************************************************
++ * Avalanche Interrupt pacing register base (secondary)
++ ******************************************************************************/
++#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
++
++
++
++/******************************************************************************
++ * Avalanche Interrupt Channel Control register base
++ *****************************************************************************/
++#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
++
++
++struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
++{
++ volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
++ volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
++ volatile unsigned long unused1; /*0x08 */
++ volatile unsigned long unused2; /*0x0C */
++ volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
++ volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
++ volatile unsigned long unused3; /*0x18 */
++ volatile unsigned long unused4; /*0x1C */
++ volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
++ volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
++ volatile unsigned long unused5; /*0x28 */
++ volatile unsigned long unused6; /*0x2C */
++ volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
++ volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
++ volatile unsigned long unused7; /* 0x38 */
++ volatile unsigned long unused8; /* 0x3c */
++ volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
++ volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
++ volatile unsigned long unused9; /* 0x48 */
++ volatile unsigned long unused10; /* 0x4C */
++ volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
++ volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
++ volatile unsigned long unused11; /* 0x58 */
++ volatile unsigned long unused12; /*0x5C */
++ volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
++ volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
++};
++
++struct avalanche_exctrl_regs /* Avalanche Exception control registers */
++{
++ volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
++ volatile unsigned long reserved; /*0x84 */
++ volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
++ volatile unsigned long reserved1; /*0x8c */
++ volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
++ volatile unsigned long reserved2; /*0x94 */
++ volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
++};
++struct avalanche_ipace_regs
++{
++
++ volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
++ volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
++ volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
++};
++struct avalanche_channel_int_number
++{
++ volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
++ volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
++ volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
++ volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
++ volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
++ volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
++ volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
++ volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
++ volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
++ volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
++ volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
++ volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
++ volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
++ volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
++ volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
++ volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
++ volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
++ volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
++ volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
++ volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
++ volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
++ volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
++ volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
++ volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
++ volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
++ volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
++ volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
++ volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
++ volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
++ volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
++ volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
++ volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
++ volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
++ volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
++ volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
++ volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
++ volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
++ volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
++ volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
++ volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
++};
++
++struct avalanche_interrupt_line_to_channel
++{
++ unsigned long int_line0; /* Start of primary interrupts */
++ unsigned long int_line1;
++ unsigned long int_line2;
++ unsigned long int_line3;
++ unsigned long int_line4;
++ unsigned long int_line5;
++ unsigned long int_line6;
++ unsigned long int_line7;
++ unsigned long int_line8;
++ unsigned long int_line9;
++ unsigned long int_line10;
++ unsigned long int_line11;
++ unsigned long int_line12;
++ unsigned long int_line13;
++ unsigned long int_line14;
++ unsigned long int_line15;
++ unsigned long int_line16;
++ unsigned long int_line17;
++ unsigned long int_line18;
++ unsigned long int_line19;
++ unsigned long int_line20;
++ unsigned long int_line21;
++ unsigned long int_line22;
++ unsigned long int_line23;
++ unsigned long int_line24;
++ unsigned long int_line25;
++ unsigned long int_line26;
++ unsigned long int_line27;
++ unsigned long int_line28;
++ unsigned long int_line29;
++ unsigned long int_line30;
++ unsigned long int_line31;
++ unsigned long int_line32;
++ unsigned long int_line33;
++ unsigned long int_line34;
++ unsigned long int_line35;
++ unsigned long int_line36;
++ unsigned long int_line37;
++ unsigned long int_line38;
++ unsigned long int_line39;
++};
++
++
++/* Interrupt Line #'s (Sangam peripherals) */
++
++/*------------------------------*/
++/* Sangam primary interrupts */
++/*------------------------------*/
++
++#define UNIFIED_SECONDARY_INTERRUPT 0
++#define AVALANCHE_EXT_INT_0 1
++#define AVALANCHE_EXT_INT_1 2
++/* Line #3 Reserved */
++/* Line #4 Reserved */
++#define AVALANCHE_TIMER_0_INT 5
++#define AVALANCHE_TIMER_1_INT 6
++#define AVALANCHE_UART0_INT 7
++#define AVALANCHE_UART1_INT 8
++#define AVALANCHE_PDMA_INT0 9
++#define AVALANCHE_PDMA_INT1 10
++/* Line #11 Reserved */
++/* Line #12 Reserved */
++/* Line #13 Reserved */
++/* Line #14 Reserved */
++#define AVALANCHE_ATM_SAR_INT 15
++/* Line #16 Reserved */
++/* Line #17 Reserved */
++/* Line #18 Reserved */
++#define AVALANCHE_MAC0_INT 19
++/* Line #20 Reserved */
++#define AVALANCHE_VLYNQ0_INT 21
++#define AVALANCHE_CODEC_WAKE_INT 22
++/* Line #23 Reserved */
++#define AVALANCHE_USB_INT 24
++#define AVALANCHE_VLYNQ1_INT 25
++/* Line #26 Reserved */
++/* Line #27 Reserved */
++#define AVALANCHE_MAC1_INT 28
++#define AVALANCHE_I2CM_INT 29
++#define AVALANCHE_PDMA_INT2 30
++#define AVALANCHE_PDMA_INT3 31
++/* Line #32 Reserved */
++/* Line #33 Reserved */
++/* Line #34 Reserved */
++/* Line #35 Reserved */
++/* Line #36 Reserved */
++#define AVALANCHE_VDMA_VT_RX_INT 37
++#define AVALANCHE_VDMA_VT_TX_INT 38
++#define AVALANCHE_ADSLSS_INT 39
++
++/*-----------------------------------*/
++/* Sangam Secondary Interrupts */
++/*-----------------------------------*/
++#define PRIMARY_INTS 40
++
++#define EMIF_INT (7 + PRIMARY_INTS)
++
++
++extern void avalanche_int_set(int channel, int line);
++
++
++#endif /* _AVALANCHE_INTC_H */
+diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
+--- linux.old/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-11-10 01:10:46.067588500 +0100
+@@ -0,0 +1,174 @@
++#ifndef _AVALANCHE_MISC_H_
++#define _AVALANCHE_MISC_H_
++
++typedef enum AVALANCHE_ERR_t
++{
++ AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */
++ AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
++
++ /* Pointers and args */
++ AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */
++ AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */
++ AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
++
++ /* Memory issues */
++ AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */
++ AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */
++ AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */
++ AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */
++
++ /* Device issues */
++ AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
++ AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
++
++ AVALANCHE_ERR_INVID = -30 /* Invalid ID */
++
++} AVALANCHE_ERR;
++
++/*****************************************************************************
++ * Reset Control Module
++ *****************************************************************************/
++
++typedef enum AVALANCHE_RESET_MODULE_tag
++{
++ RESET_MODULE_UART0 = 0,
++ RESET_MODULE_UART1 = 1,
++ RESET_MODULE_I2C = 2,
++ RESET_MODULE_TIMER0 = 3,
++ RESET_MODULE_TIMER1 = 4,
++ RESET_MODULE_GPIO = 6,
++ RESET_MODULE_ADSLSS = 7,
++ RESET_MODULE_USBS = 8,
++ RESET_MODULE_SAR = 9,
++ RESET_MODULE_VDMA_VT = 11,
++ RESET_MODULE_FSER = 12,
++ RESET_MODULE_VLYNQ1 = 16,
++ RESET_MODULE_EMAC0 = 17,
++ RESET_MODULE_DMA = 18,
++ RESET_MODULE_BIST = 19,
++ RESET_MODULE_VLYNQ0 = 20,
++ RESET_MODULE_EMAC1 = 21,
++ RESET_MODULE_MDIO = 22,
++ RESET_MODULE_ADSLSS_DSP = 23,
++ RESET_MODULE_EPHY = 26
++} AVALANCHE_RESET_MODULE_T;
++
++typedef enum AVALANCHE_RESET_CTRL_tag
++{
++ IN_RESET = 0,
++ OUT_OF_RESET
++} AVALANCHE_RESET_CTRL_T;
++
++typedef enum AVALANCHE_SYS_RST_MODE_tag
++{
++ RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
++ RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
++} AVALANCHE_SYS_RST_MODE_T;
++
++typedef enum AVALANCHE_SYS_RESET_STATUS_tag
++{
++ HARDWARE_RESET = 0,
++ SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
++ WATCHDOG_RESET,
++ SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
++} AVALANCHE_SYS_RESET_STATUS_T;
++
++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
++
++typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
++
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++
++typedef enum AVALANCHE_POWER_CTRL_tag
++{
++ POWER_CTRL_POWER_UP = 0,
++ POWER_CTRL_POWER_DOWN
++} AVALANCHE_POWER_CTRL_T;
++
++typedef enum AVALANCHE_SYS_POWER_MODE_tag
++{
++ GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
++ GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
++ GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
++ GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
++} AVALANCHE_SYS_POWER_MODE_T;
++
++void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl);
++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
++
++/*****************************************************************************
++ * Wakeup Control
++ *****************************************************************************/
++
++typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
++{
++ WAKEUP_INT0 = 1,
++ WAKEUP_INT1 = 2,
++ WAKEUP_INT2 = 4,
++ WAKEUP_INT3 = 8
++} AVALANCHE_WAKEUP_INTERRUPT_T;
++
++typedef enum TNETV1050_WAKEUP_CTRL_tag
++{
++ WAKEUP_DISABLED = 0,
++ WAKEUP_ENABLED
++} AVALANCHE_WAKEUP_CTRL_T;
++
++typedef enum TNETV1050_WAKEUP_POLARITY_tag
++{
++ WAKEUP_ACTIVE_HIGH = 0,
++ WAKEUP_ACTIVE_LOW
++} AVALANCHE_WAKEUP_POLARITY_T;
++
++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
++ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
++ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
++
++/*****************************************************************************
++ * GPIO Control
++ *****************************************************************************/
++
++typedef enum AVALANCHE_GPIO_PIN_MODE_tag
++{
++ FUNCTIONAL_PIN = 0,
++ GPIO_PIN = 1
++} AVALANCHE_GPIO_PIN_MODE_T;
++
++typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
++{
++ GPIO_OUTPUT_PIN = 0,
++ GPIO_INPUT_PIN = 1
++} AVALANCHE_GPIO_PIN_DIRECTION_T;
++
++typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
++
++void avalanche_gpio_init(void);
++int avalanche_gpio_ctrl(unsigned int gpio_pin,
++ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
++int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
++ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
++int avalanche_gpio_in_bit(unsigned int gpio_pin);
++int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
++int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
++int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
++
++unsigned int avalanche_get_chip_version_info(void);
++
++unsigned int avalanche_get_vbus_freq(void);
++void avalanche_set_vbus_freq(unsigned int);
++
++
++typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
++unsigned int avalanche_is_mdix_on_chip(void);
++
++#endif
+diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
+--- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-11-10 01:10:46.071588750 +0100
+@@ -0,0 +1,567 @@
++/*
++ * $Id$
++ * Avalanche Register Descriptions
++ *
++ * Jeff Harrell, jharrell@ti.com
++ * 2000 (c) Texas Instruments Inc.
++ */
++
++#ifndef __AVALANCHE_REGS_H
++#define __AVALANCHE_REGS_H
++
++#include <asm/addrspace.h>
++#include <linux/config.h>
++
++/*----------------------------------------*/
++/* Base offsets within the Avalanche ASIC */
++/*----------------------------------------*/
++
++#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
++#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
++#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
++#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
++#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
++#define DES_BASE (KSEG1ADDR(0x08600000))
++#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
++#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
++#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
++#define GPIO_BASE (KSEG1ADDR(0x08610900))
++#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
++#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
++#define TMR1_BASE (KSEG1ADDR(0x08610C00))
++#define TRM2_BASE (KSEG1ADDR(0x08610D00))
++#define UARTA_BASE (KSEG1ADDR(0x08610E00))
++#define UARTB_BASE (KSEG1ADDR(0x08610F00))
++#define I2C_BASE (KSEG1ADDR(0x08611000))
++#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
++#define USB_BASE (KSEG1ADDR(0x08611200))
++#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
++#define DMA_BASE (KSEG1ADDR(0x08611400))
++#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
++#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
++#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
++#define PHY_BASE (KSEG1ADDR(0x1E000000))
++
++/*---------------------------------*/
++/* Device ID, chip version number */
++/*---------------------------------*/
++
++#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
++#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
++#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
++
++/*----------------------------------*/
++/* Reset Control VW changed to ptrs */
++/*----------------------------------*/
++
++#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
++#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
++#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
++
++/* reset control bits */
++
++#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
++#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
++#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
++#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
++#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
++#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
++#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
++/*
++ JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
++ If you reset the GPIO interface all of the directions (i/o) of the UART B
++ interface pins are inputs and must be reconfigured so as not to lose the
++ serial console interface
++ JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
++*/
++#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
++#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
++#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
++#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
++#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
++#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
++#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
++#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
++#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
++#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
++
++/*----------------------*/
++/* Physical interfaces */
++/*----------------------*/
++
++/* Phy loopback */
++#define PHY_LOOPBACK 1
++
++
++/* Phy 0 */
++#define PHY0BASE (PHY_BASE)
++#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
++#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
++#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
++#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
++#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
++
++
++/* Phy 1 */
++
++#define PHY1BASE (PHY_BASE + 0x100000)
++#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
++#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
++#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
++#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
++#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
++
++/* Phy 2 */
++
++#define PHY2BASE (PHY_BASE + 0x200000)
++#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
++#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
++#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
++#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
++#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
++
++/*-------------------*/
++/* Avalanche ATM SAR */
++/*-------------------*/
++
++#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
++#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
++#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
++#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
++#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
++#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
++
++/* Transmit completion ring registers */
++
++#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
++#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
++#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
++#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
++#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
++#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
++#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
++#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
++#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
++#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
++#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
++#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
++#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
++#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
++
++/* Transmit Queue Packet registers */
++#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
++#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
++#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
++#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
++/* Receive completion ring registers */
++
++#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
++#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
++#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
++#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
++#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
++#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
++#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
++#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
++#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
++#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
++#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
++#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
++#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
++#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
++
++#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
++#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
++#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
++#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
++#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
++#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
++#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
++
++
++#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
++
++#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
++#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
++#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
++#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
++#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
++#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
++#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
++#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
++#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
++#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
++#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
++#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
++#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
++#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
++#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
++#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
++#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
++
++
++/*
++
++#define OAM_CPID_ADD 0xa30104e0
++
++#define OAM_LLID_ADD 0xa30104f0
++
++#define OAM_LLID_VAL 0xffffffff
++
++#define OAM_CORR_TAG 0xa3010500
++
++#define OAM_FAR_COUNT_ADD 0xa3010520
++
++#define OAM_NEAR_COUNT_ADD 0xa3010540
++
++#define OAM_CONFIG_REG_ADD 0xa3000018
++*/
++
++
++#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
++
++#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
++#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
++#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
++#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
++
++#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
++
++
++#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
++#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
++#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
++#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
++#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
++#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
++
++/*------------------------------------------*/
++/* DSL Interface */
++/*------------------------------------------*/
++
++#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
++#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
++#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
++
++/* Fast */
++
++#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
++#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
++#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
++#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
++#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
++#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
++#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
++#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
++
++/* Interleaved */
++
++#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
++#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
++#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
++#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
++#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
++#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
++#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
++#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
++
++/*------------------------------------------*/
++/* Broadband I/F */
++/*------------------------------------------*/
++
++#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
++#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
++#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
++#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
++#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
++#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
++
++#define AVBBIF_DISABLED 0x0
++#define AVBBIF_LBT4040_INT 0x1
++#define AVBBIF_XBUS 0x2
++#define AVBBIF_LBT4040_EXT 0x4
++
++#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
++#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
++#define AVBBIF_TRANS_MASK 0xff000000
++/*------------------------------------------*/
++/* GPIO I/F */
++/*------------------------------------------*/
++
++#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
++#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
++#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
++#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
++
++#define GPIO_0 (1<<21)
++#define GPIO_1 (1<<22)
++#define GPIO_2 (1<<23)
++#define GPIO_3 (1<<24)
++#define EINT_1 (1<<18)
++
++/*
++ JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
++ If you reset the GPIO interface all of the directions (i/o) of the UART B
++ interface pins are inputs and must be reconfigured so as not to lose the
++ serial console interface
++ JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
++*/
++
++/*------------------------------------------*/
++/* CLK_CTRL */
++/*------------------------------------------*/
++#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
++
++#define PCLK_0_HALF_VBUS (0<<16)
++#define PCLK_EQ_INPUT (1<<16)
++#define BBIF_CLK_HALF_VBUS (0<<17)
++#define BBIF_CLK_EQ_VBUS (1<<17)
++#define BBIF_CLK_EQ_BBCLK (3<<17)
++#define DSP_MODCLK_DSPCLKI (0<<20)
++#define DSP_MODCLK_REFCLKI (1<<20)
++#define USB_CLK_EQ_USBCLKI (0<<21)
++#define USB_CLK_EQ_REFCLKI (1<<21)
++
++/*------------------------------------------*/
++/* PCI Control Registers */
++/*------------------------------------------*/
++#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
++#define PCIC_CONTROL_CFG_DONE (1<<0)
++#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
++#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
++#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
++#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
++#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
++#define PCIC_CONTROL_MEM_MASK (1<<6)
++#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
++#define PCIC_CONTROL_IO_MASK (1<<8)
++/* PCIC_CONTROL_RESERVED (1<<9) */
++#define PCIC_CONTROL_BASE0_EN (1<<10)
++#define PCIC_CONTROL_BASE1_EN (1<<11)
++#define PCIC_CONTROL_BASE2_EN (1<<12)
++#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
++#define PCIC_CONTROL_ARBITER_EN (1<<14)
++#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
++#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
++#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
++#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
++#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
++#define PCIC_INT_SOURCE_PMEIN (1<<4)
++/* PCIC_INT_SOURCE_RESERVED (1<<5) */
++/* PCIC_INT_SOURCE_RESERVED (1<<6) */
++#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
++#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
++#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
++#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
++#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
++#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
++#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
++#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
++#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
++#define PCIC_INT_CLEAR_PM (1<<0)
++#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
++#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
++/* PCIC_INT_CLEAR_RESERVED (1<<3) */
++#define PCIC_INT_CLEAR_PMEIN (1<<4)
++/* PCIC_INT_CLEAR_RESERVED (1<<5) */
++/* PCIC_INT_CLEAR_RESERVED (1<<6) */
++#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
++#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
++#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
++#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
++#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
++#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
++#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
++#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
++#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
++#define PCIC_INT_EN_AVAL_PM (1<<0)
++#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
++#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
++/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
++#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
++/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
++/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
++#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
++#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
++#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
++#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
++#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
++#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
++#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
++#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
++#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
++#define PCIC_INT_EN_PCI_PM (1<<0)
++#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
++#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
++/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
++#define PCIC_INT_EN_PCI_PMEIN (1<<4)
++/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
++/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
++#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
++#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
++#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
++#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
++#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
++#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
++#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
++#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
++#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
++#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
++#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
++#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
++#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
++#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
++#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
++/* PCIC_PM_CTL_RESERVED (1<<2) */
++/* PCIC_PM_CTL_RESERVED (1<<3) */
++/* PCIC_PM_CTL_RESERVED (1<<4) */
++/* PCIC_PM_CTL_RESERVED (1<<5) */
++/* PCIC_PM_CTL_RESERVED (1<<6) */
++/* PCIC_PM_CTL_RESERVED (1<<7) */
++/* PCIC_PM_CTL_RESERVED (1<<8) */
++/* PCIC_PM_CTL_RESERVED (1<<9) */
++#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
++#define PCIC_PM_CTL_PMEIN (1<<11)
++#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
++#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
++#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
++#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
++#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
++#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
++#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
++#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
++#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
++#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
++#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
++#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
++#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
++#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
++#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
++#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
++#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
++#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
++#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
++#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
++#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
++#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
++#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
++#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
++#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
++#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
++#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
++#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
++
++/*------------------------------------------*/
++/* IIC_INTERFACE */
++/*------------------------------------------*/
++#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
++#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
++#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
++#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
++#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
++
++#define I2CWRITE 0x200
++#define I2CREAD 0x300
++#define I2C_END_BURST 0x400
++
++/* read bits */
++#define I2C_READ_ERROR 0x8000
++#define I2C_READ_COMPLETE 0x4000
++#define I2C_READ_BUSY 0x2000
++
++/* device types */
++#define I2C_IO_EXPANDER 0x2
++#define I2C_RTC 0xd
++
++/* device Addresses on I2C bus (EVM3) */
++#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
++#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
++#define EVM3_RTC_I2C_ADDR 0x0
++
++/*------------------------------------------*/
++/* Ethernet MAC register offset definitions */
++/*------------------------------------------*/
++#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
++#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
++#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
++
++#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
++#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
++
++#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
++#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
++#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
++#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
++#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
++#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
++#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
++#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
++
++
++#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
++#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
++#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
++#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
++#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
++#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
++#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
++#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
++#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
++#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
++#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
++#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
++
++#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
++#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
++#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
++#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
++#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
++#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
++#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
++#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
++
++#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
++#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
++#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
++#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
++#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
++#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
++#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
++#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
++#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
++#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
++#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
++#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
++
++#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
++#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
++#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
++#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
++
++#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
++#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
++#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
++#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
++#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
++#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
++
++#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
++#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
++#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
++#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
++
++#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
++#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
++#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
++#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
++#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
++
++#define VMAC_STATS_BASE(X) (X + 0x00000400)
++
++#endif __AVALANCHE_REGS_H
++
++
++
++
++
++
+diff -urN linux.old/include/asm-mips/ar7/avalanche_types.h linux.dev/include/asm-mips/ar7/avalanche_types.h
+--- linux.old/include/asm-mips/ar7/avalanche_types.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_types.h 2005-11-10 01:10:46.071588750 +0100
+@@ -0,0 +1,126 @@
++/*------------------------------------------------------------------------------------------*\
++\*------------------------------------------------------------------------------------------*/
++#ifndef _avalanche_types_h_
++#define _avalanche_types_h_
++
++/*--- #include <asm/avalanche/generic/hal_modules/haltypes.h> ---*/
++#ifndef TRUE
++#define TRUE 1
++#endif
++#ifndef FALSE
++#define FALSE 0
++#endif
++#ifndef NULL
++#define NULL (void *)0
++#endif
++
++/*------------------------------------------------------------------------------------------*\
++ * Typen für Texas GPL Module
++\*------------------------------------------------------------------------------------------*/
++#ifndef __UINT8_T__
++typedef unsigned char UINT8;
++#define __UINT8_T__
++#endif
++
++#ifndef __UCHAR_T__
++typedef unsigned char UCHAR;
++#define __UCHAR_T__
++#endif
++
++#ifndef __INT8_T__
++typedef signed char INT8;
++#define __INT8_T__
++#endif
++
++#ifndef __UINT16_T__
++typedef unsigned short UINT16;
++#define __UINT16_T__
++#endif
++
++#ifndef __USHORT_T__
++typedef unsigned short USHORT;
++#define __USHORT_T__
++#endif
++
++#ifndef __INT16_T__
++typedef signed short INT16;
++#define __INT16_T__
++#endif
++
++#ifndef __UINT32_T__
++typedef unsigned int UINT32;
++#define __UINT32_T__
++#endif
++
++#ifndef __UINT_T__
++typedef unsigned int UINT;
++#define __UINT_T__
++#endif
++
++#ifndef __INT32_T__
++typedef signed int INT32;
++#define __INT32_T__
++#endif
++
++#ifndef __ULONG_T__
++typedef unsigned long ULONG;
++#define __ULONG_T__
++#endif
++
++#ifndef __BOOL_T__
++typedef int BOOL;
++#define __BOOL_T__
++#endif
++
++#ifndef __STATUS_T__
++typedef int STATUS;
++#define __STATUS_T__
++#endif
++
++/*------------------------------------------------------------------------------------------*\
++\*------------------------------------------------------------------------------------------*/
++typedef void (*p_vlynq_intr_cntrl_isr_t)(void *,void *,void *);
++typedef INT32 (*p_vlynq_interrupt_vector_set_t)(void *, UINT32, UINT32, INT32, INT32, INT32);
++typedef INT32 (*p_vlynq_interrupt_vector_cntl_t)(void *, UINT32, INT32, UINT32);
++typedef UINT32 (*p_vlynq_interrupt_get_count_t)(void *, UINT32);
++typedef INT32 (*p_vlynq_install_isr_t)(void *, UINT32, p_vlynq_intr_cntrl_isr_t, void *, void *, void *);
++typedef INT32 (*p_vlynq_uninstall_isr_t)(void *, UINT32, void *, void *, void *);
++typedef void (*p_vlynq_root_isr_t)(void *);
++typedef void (*p_vlynq_delay_t)(UINT32);
++typedef INT32 (*p_vlynq_interrupt_vector_map_t)(void *, INT32, UINT32, UINT32);
++typedef INT32 (*p_vlynq_interrupt_set_polarity_t)(void *, INT32, UINT32, INT32);
++typedef INT32 (*p_vlynq_interrupt_get_polarity_t)(void *, INT32, UINT32);
++typedef INT32 (*p_vlynq_interrupt_set_type_t)(void *, INT32, UINT32, INT32);
++typedef INT32 (*p_vlynq_interrupt_get_type_t)(void *, INT32, UINT32);
++typedef INT32 (*p_vlynq_interrupt_enable_t)(void *, INT32, UINT32);
++typedef INT32 (*p_vlynq_interrupt_disable_t)(void *, INT32, UINT32);
++
++/*------------------------------------------------------------------------------------------*\
++\*------------------------------------------------------------------------------------------*/
++extern p_vlynq_interrupt_vector_set_t p_vlynq_interrupt_vector_set;
++extern p_vlynq_interrupt_vector_cntl_t p_vlynq_interrupt_vector_cntl;
++extern p_vlynq_interrupt_get_count_t p_vlynq_interrupt_get_count;
++extern p_vlynq_install_isr_t p_vlynq_install_isr;
++extern p_vlynq_uninstall_isr_t p_vlynq_uninstall_isr;
++extern p_vlynq_root_isr_t p_vlynq_root_isr;
++extern p_vlynq_delay_t p_vlynq_delay;
++extern p_vlynq_interrupt_vector_map_t p_vlynq_interrupt_vector_map;
++extern p_vlynq_interrupt_set_polarity_t p_vlynq_interrupt_set_polarity;
++extern p_vlynq_interrupt_get_polarity_t p_vlynq_interrupt_get_polarity;
++extern p_vlynq_interrupt_set_type_t p_vlynq_interrupt_set_type;
++extern p_vlynq_interrupt_get_type_t p_vlynq_interrupt_get_type;
++extern p_vlynq_interrupt_enable_t p_vlynq_interrupt_enable;
++extern p_vlynq_interrupt_disable_t p_vlynq_interrupt_disable;
++extern void *p_vlynqDevice0;
++extern void *p_vlynqDevice1;
++
++/*------------------------------------------------------------------------------------------*\
++\*------------------------------------------------------------------------------------------*/
++enum _avalanche_need_ {
++ avalanche_need_vlynq,
++ avalanche_need_auto_mdix
++};
++
++int avalanche_need(enum _avalanche_need_);
++
++#endif /*--- #ifndef _avalanche_types_h_ ---*/
+diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
+--- linux.old/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/if_port.h 2005-11-10 01:10:46.071588750 +0100
+@@ -0,0 +1,26 @@
++/*******************************************************************************
++ * FILE PURPOSE: Interface port id Header file
++ *******************************************************************************
++ * FILE NAME: if_port.h
++ *
++ * DESCRIPTION: Header file carrying information about port ids of interfaces
++ *
++ *
++ * (C) Copyright 2003, Texas Instruments, Inc
++ ******************************************************************************/
++#ifndef _IF_PORT_H_
++#define _IF_PORT_H_
++
++#define AVALANCHE_CPMAC_LOW_PORT_ID 0
++#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
++#define AVALANCHE_USB_PORT_ID 2
++#define AVALANCHE_WLAN_PORT_ID 3
++
++
++#define AVALANCHE_MARVELL_BASE_PORT_ID 4
++
++/* The marvell ports occupy port ids from 4 to 8 */
++/* so the next port id number should start at 9 */
++
++
++#endif /* _IF_PORT_H_ */
+diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
+--- linux.old/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/sangam.h 2005-11-10 01:10:46.071588750 +0100
+@@ -0,0 +1,180 @@
++#ifndef _SANGAM_H_
++#define _SANGAM_H_
++
++#include <linux/config.h>
++#include <asm/addrspace.h>
++
++/*----------------------------------------------------
++ * Sangam's Module Base Addresses
++ *--------------------------------------------------*/
++#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
++#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
++#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
++#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
++#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
++#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
++#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
++#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
++#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
++#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
++#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
++#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
++#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
++#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
++#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
++#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
++#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
++#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
++#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
++#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
++#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
++#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
++#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
++#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
++#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
++#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
++#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
++
++#define AVALANCHE_SDRAM_BASE 0x14000000UL
++
++
++/*----------------------------------------------------
++ * Sangam Interrupt Map (Primary Interrupts)
++ *--------------------------------------------------*/
++
++#define AVALANCHE_UNIFIED_SECONDARY_INT 0
++#define AVALANCHE_EXT_INT_0 1
++#define AVALANCHE_EXT_INT_1 2
++/* Line# 3 to 4 are reserved */
++#define AVALANCHE_TIMER_0_INT 5
++#define AVALANCHE_TIMER_1_INT 6
++#define AVALANCHE_UART0_INT 7
++#define AVALANCHE_UART1_INT 8
++#define AVALANCHE_DMA_INT0 9
++#define AVALANCHE_DMA_INT1 10
++/* Line# 11 to 14 are reserved */
++#define AVALANCHE_ATM_SAR_INT 15
++/* Line# 16 to 18 are reserved */
++#define AVALANCHE_LOW_CPMAC_INT 19
++/* Line# 20 is reserved */
++#define AVALANCHE_LOW_VLYNQ_INT 21
++#define AVALANCHE_CODEC_WAKEUP_INT 22
++/* Line# 23 is reserved */
++#define AVALANCHE_USB_SLAVE_INT 24
++#define AVALANCHE_HIGH_VLYNQ_INT 25
++/* Line# 26 to 27 are reserved */
++#define AVALANCHE_UNIFIED_PHY_INT 28
++#define AVALANCHE_I2C_INT 29
++#define AVALANCHE_DMA_INT2 30
++#define AVALANCHE_DMA_INT3 31
++/* Line# 32 is reserved */
++#define AVALANCHE_HIGH_CPMAC_INT 33
++/* Line# 34 to 36 is reserved */
++#define AVALANCHE_VDMA_VT_RX_INT 37
++#define AVALANCHE_VDMA_VT_TX_INT 38
++#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
++
++
++#define AVALANCHE_EMIF_INT 47
++
++
++
++/*-----------------------------------------------------------
++ * Sangam's Reset Bits
++ *---------------------------------------------------------*/
++
++#define AVALANCHE_UART0_RESET_BIT 0
++#define AVALANCHE_UART1_RESET_BIT 1
++#define AVALANCHE_I2C_RESET_BIT 2
++#define AVALANCHE_TIMER0_RESET_BIT 3
++#define AVALANCHE_TIMER1_RESET_BIT 4
++/* Reset bit 5 is reserved. */
++#define AVALANCHE_GPIO_RESET_BIT 6
++#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
++#define AVALANCHE_USB_SLAVE_RESET_BIT 8
++#define AVALANCHE_ATM_SAR_RESET_BIT 9
++/* Reset bit 10 is reserved. */
++#define AVALANCHE_VDMA_VT_RESET_BIT 11
++#define AVALANCHE_FSER_RESET_BIT 12
++/* Reset bit 13 to 15 are reserved */
++#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
++#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
++#define AVALANCHE_MCDMA_RESET_BIT 18
++#define AVALANCHE_BIST_RESET_BIT 19
++#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
++#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
++#define AVALANCHE_MDIO_RESET_BIT 22
++#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
++/* Reset bit 24 to 25 are reserved */
++#define AVALANCHE_LOW_EPHY_RESET_BIT 26
++/* Reset bit 27 to 31 are reserved */
++
++
++#define AVALANCHE_POWER_MODULE_USBSP 0
++#define AVALANCHE_POWER_MODULE_WDTP 1
++#define AVALANCHE_POWER_MODULE_UT0P 2
++#define AVALANCHE_POWER_MODULE_UT1P 3
++#define AVALANCHE_POWER_MODULE_IICP 4
++#define AVALANCHE_POWER_MODULE_VDMAP 5
++#define AVALANCHE_POWER_MODULE_GPIOP 6
++#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
++#define AVALANCHE_POWER_MODULE_SARP 8
++#define AVALANCHE_POWER_MODULE_ADSLP 9
++#define AVALANCHE_POWER_MODULE_EMIFP 10
++#define AVALANCHE_POWER_MODULE_ADSPP 12
++#define AVALANCHE_POWER_MODULE_RAMP 13
++#define AVALANCHE_POWER_MODULE_ROMP 14
++#define AVALANCHE_POWER_MODULE_DMAP 15
++#define AVALANCHE_POWER_MODULE_BISTP 16
++#define AVALANCHE_POWER_MODULE_TIMER0P 18
++#define AVALANCHE_POWER_MODULE_TIMER1P 19
++#define AVALANCHE_POWER_MODULE_EMAC0P 20
++#define AVALANCHE_POWER_MODULE_EMAC1P 22
++#define AVALANCHE_POWER_MODULE_EPHYP 24
++#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
++
++
++
++
++
++/*
++ * Sangam board vectors
++ */
++
++#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
++
++/*-----------------------------------------------------------------------------
++ * Sangam's system register.
++ *
++ *---------------------------------------------------------------------------*/
++#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
++#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
++#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
++#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
++#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
++
++#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
++#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
++
++#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
++#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
++#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
++#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
++#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
++
++/*
++ * Yamon Prom print address.
++ */
++#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
++#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
++
++#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
++
++#define AVALANCHE_GPIO_PIN_COUNT 32
++#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
++
++#include "sangam_boards.h"
++
++#endif /*_SANGAM_H_ */
+diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
+--- linux.old/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-11-10 01:10:46.071588750 +0100
+@@ -0,0 +1,77 @@
++#ifndef _SANGAM_BOARDS_H
++#define _SANGAM_BOARDS_H
++
++// Let us define board specific information here.
++
++
++#if defined(CONFIG_AR7DB)
++
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++
++#endif
++
++
++#if defined(CONFIG_AR7RD)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7WI)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7V)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7WRD)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7VWI)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined CONFIG_SEAD2
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
++#include <asm/mips-boards/sead.h>
++#endif
++
++
++#endif
+diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
+--- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-11-10 01:10:46.075589000 +0100
+@@ -0,0 +1,338 @@
++/******************************************************************************
++ * FILE PURPOSE: TNETD73xx Common Header File
++ ******************************************************************************
++ * FILE NAME: tnetd73xx.h
++ *
++ * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++/*
++ *
++ *
++ * These are const, typedef, and api definitions for tnetd73xx.
++ *
++ * NOTES:
++ * 1. This file may be included into both C and Assembly files.
++ * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
++ * avoid C data types (typedefs) below;
++ * - for .c files, you don't have to do anything special.
++ *
++ * 2. This file has a number of sections for each SOC subsystem. When adding
++ * a new constant, find the subsystem you are working on and follow the
++ * name pattern. If you are adding another typedef for your interface, please,
++ * place it with other typedefs and function prototypes.
++ *
++ * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
++ * cluttering. Include such items directly into the module's .c file or have a
++ * local .h file to pass data between smaller modules. This file defines only
++ * shared items.
++ */
++
++#ifndef __TNETD73XX_H__
++#define __TNETD73XX_H__
++
++#ifndef _ASMLANGUAGE /* This part not for assembly language */
++
++extern unsigned int tnetd73xx_mips_freq;
++extern unsigned int tnetd73xx_vbus_freq;
++
++#include "tnetd73xx_err.h"
++
++#endif /* _ASMLANGUAGE */
++
++
++/*******************************************************************************************
++* Emerald core specific
++******************************************************************************************** */
++
++#ifdef BIG_ENDIAN
++#elif defined(LITTLE_ENDIAN)
++#else
++#error Need to define endianism
++#endif
++
++#ifndef KSEG_MSK
++#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
++#endif
++
++#ifndef KSEG_INV_MASK
++#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
++#endif
++
++#ifndef KSEG0_BASE
++#define KSEG0_BASE 0x80000000
++#endif
++
++#ifndef KSEG1_BASE
++#define KSEG1_BASE 0xA0000000
++#endif
++
++#ifndef KSEG0
++#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
++#endif
++
++#ifndef KSEG1
++#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
++#endif
++
++#ifndef KUSEG
++#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
++#endif
++
++#ifndef PHYS_ADDR
++#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
++#endif
++
++#ifndef PHYS_TO_K0
++#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
++#endif
++
++#ifndef PHYS_TO_K1
++#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
++#endif
++
++#ifndef REG8_ADDR
++#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
++#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
++#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
++#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
++#endif
++
++#ifndef REG16_ADDR
++#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
++#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
++#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
++#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
++#endif
++
++#ifndef REG32_ADDR
++#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
++#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
++#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
++#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
++#endif
++
++#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
++#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
++#endif
++
++#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
++#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
++#endif
++
++#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
++#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
++#endif
++
++/* TNETD73XX chip definations */
++
++#define FREQ_1MHZ 1000000
++#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
++#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
++
++#ifdef AR7SEAD2
++#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
++#else
++#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
++#endif
++#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
++
++
++
++/* Module base addresses */
++#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
++#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
++#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
++#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
++#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
++#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
++#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
++#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
++#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
++#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
++#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
++#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
++#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
++#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
++#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
++#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
++#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
++#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
++#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
++#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
++#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
++#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
++#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
++#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
++#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
++#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
++#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
++#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
++
++/* BBIF Registers */
++#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
++
++/* Device Configuration Latch Registers */
++#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
++#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
++#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
++#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
++#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
++
++/* GPIO Control */
++#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
++#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
++#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
++#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
++#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
++#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
++#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
++
++/* Reset Control */
++#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
++#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
++#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
++
++/* Power Control */
++#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
++#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
++#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
++#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
++
++/* Clock Control */
++#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
++#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
++#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
++#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
++#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
++#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
++#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
++#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
++#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
++#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
++
++/* EMIF control */
++#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
++
++/* UART */
++#ifdef AR7SEAD2
++#define TNETD73XX_UART_FREQ 3686400
++#else
++#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
++#endif
++
++/* Interrupt Controller */
++
++/* Primary interrupts */
++#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
++#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
++#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
++#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
++#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
++#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
++#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
++#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
++#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
++#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
++#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
++#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
++#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
++#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
++#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
++#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
++#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
++#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
++#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
++#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
++#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
++#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
++#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
++#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
++#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
++#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
++#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
++#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
++#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
++#define TNETD73XX_INTC_I2C 29 /* I2C int */
++#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
++#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
++#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
++#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
++#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
++#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
++#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
++#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
++#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
++#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
++
++/* Secondary interrupts */
++#define TNETD73XX_INTC_SEC0 40 /* Secondary */
++#define TNETD73XX_INTC_SEC1 41 /* Secondary */
++#define TNETD73XX_INTC_SEC2 42 /* Secondary */
++#define TNETD73XX_INTC_SEC3 43 /* Secondary */
++#define TNETD73XX_INTC_SEC4 44 /* Secondary */
++#define TNETD73XX_INTC_SEC5 45 /* Secondary */
++#define TNETD73XX_INTC_SEC6 46 /* Secondary */
++#define TNETD73XX_INTC_EMIF 47 /* EMIF */
++#define TNETD73XX_INTC_SEC8 48 /* Secondary */
++#define TNETD73XX_INTC_SEC9 49 /* Secondary */
++#define TNETD73XX_INTC_SEC10 50 /* Secondary */
++#define TNETD73XX_INTC_SEC11 51 /* Secondary */
++#define TNETD73XX_INTC_SEC12 52 /* Secondary */
++#define TNETD73XX_INTC_SEC13 53 /* Secondary */
++#define TNETD73XX_INTC_SEC14 54 /* Secondary */
++#define TNETD73XX_INTC_SEC15 55 /* Secondary */
++#define TNETD73XX_INTC_SEC16 56 /* Secondary */
++#define TNETD73XX_INTC_SEC17 57 /* Secondary */
++#define TNETD73XX_INTC_SEC18 58 /* Secondary */
++#define TNETD73XX_INTC_SEC19 59 /* Secondary */
++#define TNETD73XX_INTC_SEC20 60 /* Secondary */
++#define TNETD73XX_INTC_SEC21 61 /* Secondary */
++#define TNETD73XX_INTC_SEC22 62 /* Secondary */
++#define TNETD73XX_INTC_SEC23 63 /* Secondary */
++#define TNETD73XX_INTC_SEC24 64 /* Secondary */
++#define TNETD73XX_INTC_SEC25 65 /* Secondary */
++#define TNETD73XX_INTC_SEC26 66 /* Secondary */
++#define TNETD73XX_INTC_SEC27 67 /* Secondary */
++#define TNETD73XX_INTC_SEC28 68 /* Secondary */
++#define TNETD73XX_INTC_SEC29 69 /* Secondary */
++#define TNETD73XX_INTC_SEC30 70 /* Secondary */
++#define TNETD73XX_INTC_SEC31 71 /* Secondary */
++
++/* These ugly macros are to access the -1 registers, like config1 */
++#define MFC0_SEL1_OPCODE(dst, src)\
++ .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
++ nop; \
++ nop; \
++ nop
++
++#define MTC0_SEL1_OPCODE(dst, src)\
++ .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
++ nop; \
++ nop; \
++ nop
++
++
++/* Below are Jade core specific */
++#define CFG0_4K_IL_MASK 0x00380000
++#define CFG0_4K_IL_SHIFT 19
++#define CFG0_4K_IA_MASK 0x00070000
++#define CFG0_4K_IA_SHIFT 16
++#define CFG0_4K_IS_MASK 0x01c00000
++#define CFG0_4K_IS_SHIFT 22
++
++#define CFG0_4K_DL_MASK 0x00001c00
++#define CFG0_4K_DL_SHIFT 10
++#define CFG0_4K_DA_MASK 0x00000380
++#define CFG0_4K_DA_SHIFT 7
++#define CFG0_4K_DS_MASK 0x0000E000
++#define CFG0_4K_DS_SHIFT 13
++
++
++
++#endif /* __TNETD73XX_H_ */
+diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
+--- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-11-10 01:10:46.075589000 +0100
+@@ -0,0 +1,42 @@
++/******************************************************************************
++ * FILE PURPOSE: TNETD73xx Error Definations Header File
++ ******************************************************************************
++ * FILE NAME: tnetd73xx_err.h
++ *
++ * DESCRIPTION: Error definations for TNETD73XX
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++
++#ifndef __TNETD73XX_ERR_H__
++#define __TNETD73XX_ERR_H__
++
++typedef enum TNETD73XX_ERR_t
++{
++ TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
++ TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
++
++ /* Pointers and args */
++ TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
++ TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
++ TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
++
++ /* Memory issues */
++ TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
++ TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
++ TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
++ TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
++
++ /* Device issues */
++ TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
++ TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
++
++ TNETD73XX_ERR_INVID = -30 /* Invalid ID */
++
++} TNETD73XX_ERR;
++
++#endif /* __TNETD73XX_ERR_H__ */
+diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
+--- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-11-10 01:10:46.075589000 +0100
+@@ -0,0 +1,239 @@
++/******************************************************************************
++ * FILE PURPOSE: TNETD73xx Misc modules API Header
++ ******************************************************************************
++ * FILE NAME: tnetd73xx_misc.h
++ *
++ * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
++ * FSER Modules API
++ * As per TNETD73xx specifications
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - Sharath Kumar PSP TII
++ * 14 Feb 03 - Anant Gole PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++#ifndef __TNETD73XX_MISC_H__
++#define __TNETD73XX_MISC_H__
++
++/*****************************************************************************
++ * Reset Control Module
++ *****************************************************************************/
++
++typedef enum TNETD73XX_RESET_MODULE_tag
++{
++ RESET_MODULE_UART0 = 0,
++ RESET_MODULE_UART1 = 1,
++ RESET_MODULE_I2C = 2,
++ RESET_MODULE_TIMER0 = 3,
++ RESET_MODULE_TIMER1 = 4,
++ RESET_MODULE_GPIO = 6,
++ RESET_MODULE_ADSLSS = 7,
++ RESET_MODULE_USBS = 8,
++ RESET_MODULE_SAR = 9,
++ RESET_MODULE_VDMA_VT = 11,
++ RESET_MODULE_FSER = 12,
++ RESET_MODULE_VLYNQ1 = 16,
++ RESET_MODULE_EMAC0 = 17,
++ RESET_MODULE_DMA = 18,
++ RESET_MODULE_BIST = 19,
++ RESET_MODULE_VLYNQ0 = 20,
++ RESET_MODULE_EMAC1 = 21,
++ RESET_MODULE_MDIO = 22,
++ RESET_MODULE_ADSLSS_DSP = 23,
++ RESET_MODULE_EPHY = 26
++} TNETD73XX_RESET_MODULE_T;
++
++typedef enum TNETD73XX_RESET_CTRL_tag
++{
++ IN_RESET = 0,
++ OUT_OF_RESET
++} TNETD73XX_RESET_CTRL_T;
++
++typedef enum TNETD73XX_SYS_RST_MODE_tag
++{
++ RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
++ RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
++} TNETD73XX_SYS_RST_MODE_T;
++
++typedef enum TNETD73XX_SYS_RESET_STATUS_tag
++{
++ HARDWARE_RESET = 0,
++ SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
++ WATCHDOG_RESET,
++ SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
++} TNETD73XX_SYS_RESET_STATUS_T;
++
++void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
++ TNETD73XX_RESET_CTRL_T reset_ctrl);
++TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
++void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
++TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
++
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++
++typedef enum TNETD73XX_POWER_MODULE_tag
++{
++ POWER_MODULE_USBSP = 0,
++ POWER_MODULE_WDTP = 1,
++ POWER_MODULE_UT0P = 2,
++ POWER_MODULE_UT1P = 3,
++ POWER_MODULE_IICP = 4,
++ POWER_MODULE_VDMAP = 5,
++ POWER_MODULE_GPIOP = 6,
++ POWER_MODULE_VLYNQ1P = 7,
++ POWER_MODULE_SARP = 8,
++ POWER_MODULE_ADSLP = 9,
++ POWER_MODULE_EMIFP = 10,
++ POWER_MODULE_ADSPP = 12,
++ POWER_MODULE_RAMP = 13,
++ POWER_MODULE_ROMP = 14,
++ POWER_MODULE_DMAP = 15,
++ POWER_MODULE_BISTP = 16,
++ POWER_MODULE_TIMER0P = 18,
++ POWER_MODULE_TIMER1P = 19,
++ POWER_MODULE_EMAC0P = 20,
++ POWER_MODULE_EMAC1P = 22,
++ POWER_MODULE_EPHYP = 24,
++ POWER_MODULE_VLYNQ0P = 27,
++} TNETD73XX_POWER_MODULE_T;
++
++typedef enum TNETD73XX_POWER_CTRL_tag
++{
++ POWER_CTRL_POWER_UP = 0,
++ POWER_CTRL_POWER_DOWN
++} TNETD73XX_POWER_CTRL_T;
++
++typedef enum TNETD73XX_SYS_POWER_MODE_tag
++{
++ GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
++ GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
++ GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
++ GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
++} TNETD73XX_SYS_POWER_MODE_T;
++
++void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
++TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
++void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
++TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
++
++/*****************************************************************************
++ * Wakeup Control
++ *****************************************************************************/
++
++typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
++{
++ WAKEUP_INT0 = 1,
++ WAKEUP_INT1 = 2,
++ WAKEUP_INT2 = 4,
++ WAKEUP_INT3 = 8
++} TNETD73XX_WAKEUP_INTERRUPT_T;
++
++typedef enum TNETD73XX_WAKEUP_CTRL_tag
++{
++ WAKEUP_DISABLED = 0,
++ WAKEUP_ENABLED
++} TNETD73XX_WAKEUP_CTRL_T;
++
++typedef enum TNETD73XX_WAKEUP_POLARITY_tag
++{
++ WAKEUP_ACTIVE_HIGH = 0,
++ WAKEUP_ACTIVE_LOW
++} TNETD73XX_WAKEUP_POLARITY_T;
++
++void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
++ TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
++ TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
++
++/*****************************************************************************
++ * FSER Control
++ *****************************************************************************/
++
++typedef enum TNETD73XX_FSER_MODE_tag
++{
++ FSER_I2C = 0,
++ FSER_UART = 1
++} TNETD73XX_FSER_MODE_T;
++
++void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
++
++/*****************************************************************************
++ * Clock Control
++ *****************************************************************************/
++
++#define CLK_MHZ(x) ( (x) * 1000000 )
++
++typedef enum TNETD73XX_CLKC_ID_tag
++{
++ CLKC_SYS = 0,
++ CLKC_MIPS,
++ CLKC_USB,
++ CLKC_ADSLSS
++} TNETD73XX_CLKC_ID_T;
++
++void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
++TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
++__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
++
++/*****************************************************************************
++ * GPIO Control
++ *****************************************************************************/
++
++typedef enum TNETD73XX_GPIO_PIN_tag
++{
++ GPIO_UART0_RD = 0,
++ GPIO_UART0_TD = 1,
++ GPIO_UART0_RTS = 2,
++ GPIO_UART0_CTS = 3,
++ GPIO_FSER_CLK = 4,
++ GPIO_FSER_D = 5,
++ GPIO_EXT_AFE_SCLK = 6,
++ GPIO_EXT_AFE_TX_FS = 7,
++ GPIO_EXT_AFE_TXD = 8,
++ GPIO_EXT_AFE_RS_FS = 9,
++ GPIO_EXT_AFE_RXD1 = 10,
++ GPIO_EXT_AFE_RXD0 = 11,
++ GPIO_EXT_AFE_CDIN = 12,
++ GPIO_EXT_AFE_CDOUT = 13,
++ GPIO_EPHY_SPEED100 = 14,
++ GPIO_EPHY_LINKON = 15,
++ GPIO_EPHY_ACTIVITY = 16,
++ GPIO_EPHY_FDUPLEX = 17,
++ GPIO_EINT0 = 18,
++ GPIO_EINT1 = 19,
++ GPIO_MBSP0_TCLK = 20,
++ GPIO_MBSP0_RCLK = 21,
++ GPIO_MBSP0_RD = 22,
++ GPIO_MBSP0_TD = 23,
++ GPIO_MBSP0_RFS = 24,
++ GPIO_MBSP0_TFS = 25,
++ GPIO_MII_DIO = 26,
++ GPIO_MII_DCLK = 27,
++} TNETD73XX_GPIO_PIN_T;
++
++typedef enum TNETD73XX_GPIO_PIN_MODE_tag
++{
++ FUNCTIONAL_PIN = 0,
++ GPIO_PIN = 1
++} TNETD73XX_GPIO_PIN_MODE_T;
++
++typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
++{
++ GPIO_OUTPUT_PIN = 0,
++ GPIO_INPUT_PIN = 1
++} TNETD73XX_GPIO_PIN_DIRECTION_T;
++
++void tnetd73xx_gpio_init(void);
++void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
++ TNETD73XX_GPIO_PIN_MODE_T pin_mode,
++ TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
++void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
++int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
++
++/* TNETD73XX Revision */
++__u32 tnetd73xx_get_revision(void);
++
++#endif /* __TNETD73XX_MISC_H__ */
+diff -urN linux.old/include/asm-mips/ar7/vlynq.h linux.dev/include/asm-mips/ar7/vlynq.h
+--- linux.old/include/asm-mips/ar7/vlynq.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/vlynq.h 2005-11-10 01:10:46.095590250 +0100
+@@ -0,0 +1,610 @@
++/***************************************************************************
++**+----------------------------------------------------------------------+**
++**| **** |**
++**| **** |**
++**| ******o*** |**
++**| ********_///_**** |**
++**| ***** /_//_/ **** |**
++**| ** ** (__/ **** |**
++**| ********* |**
++**| **** |**
++**| *** |**
++**| |**
++**| Copyright (c) 2003 Texas Instruments Incorporated |**
++**| ALL RIGHTS RESERVED |**
++**| |**
++**| Permission is hereby granted to licensees of Texas Instruments |**
++**| Incorporated (TI) products to use this computer program for the sole |**
++**| purpose of implementing a licensee product based on TI products. |**
++**| No other rights to reproduce, use, or disseminate this computer |**
++**| program, whether in part or in whole, are granted. |**
++**| |**
++**| TI makes no representation or warranties with respect to the |**
++**| performance of this computer program, and specifically disclaims |**
++**| any responsibility for any damages, special or consequential, |**
++**| connected with the use of this program. |**
++**| |**
++**+----------------------------------------------------------------------+**
++***************************************************************************/
++
++/*********************************************************************************
++ * ------------------------------------------------------------------------------
++ * Module : vlynq_hal.h
++ * Description :
++ * This header file provides the set of functions exported by the
++ * VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
++ * ------------------------------------------------------------------------------
++ *********************************************************************************/
++
++#ifndef _VLYNQ_HAL_H_
++#define _VLYNQ_HAL_H_
++
++/* Enable/Disable debug feature */
++#undef VLYNQ_DEBUG
++
++#ifdef VLYNQ_DEBUG /* This needs to be OS abstracted - for testing use vxworks/linux calls */
++#define debugPrint(format,args...)
++#else
++#define debugPrint(format,args...)
++#endif
++
++ /* number of VLYNQ memory regions supported */
++#define VLYNQ_MAX_MEMORY_REGIONS 0x04
++
++ /* Max.number of external interrupt inputs supported by VLYNQ module */
++#define VLYNQ_IVR_MAXIVR 0x08
++
++#define VLYNQ_CLK_DIV_MAX 0x08
++#define VLYNQ_CLK_DIV_MIN 0x01
++
++
++/*** the total number of entries allocated for ICB would be
++ * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
++#define VLYNQ_IVR_CHAIN_SLOTS 10
++
++
++/* Error defines */
++#define VLYNQ_SUCCESS 0
++
++#define VLYNQ_ERRCODE_BASE 0 /* Chosen by system */
++#define VLYNQ_INVALID_ARG -(VLYNQ_ERRCODE_BASE+1)
++#define VLYNQ_INVALID_DRV_STATE -(VLYNQ_ERRCODE_BASE+2)
++#define VLYNQ_INT_CONFIG_ERR -(VLYNQ_ERRCODE_BASE+3)
++#define VLYNQ_LINK_DOWN -(VLYNQ_ERRCODE_BASE+4)
++#define VLYNQ_MEMALLOC_FAIL -(VLYNQ_ERRCODE_BASE+5)
++#define VLYNQ_ISR_NON_EXISTENT -(VLYNQ_ERRCODE_BASE+6)
++#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
++
++/* Vlynq Defines and Macros */
++
++#define VLYNQ_NUM_INT_BITS 32 /* 32 bit interrupt staus register */
++
++/* Base address of module */
++#define VLYNQ_BASE (pdev->module_base)
++
++#define VLYNQ_REMOTE_REGS_OFFSET 0x0080
++
++#define VLYNQ_REV_OFFSET 0x0000
++#define VLYNQ_CTRL_OFFSET 0x0004
++#define VLYNQ_STATUS_OFFSET 0x0008
++#define VLYNQ_INT_STAT_OFFSET 0x0010
++#define VLYNQ_INT_PEND_OFFSET 0x0014
++#define VLYNQ_INT_PTR_OFFSET 0x0018
++#define VLYNQ_TXMAP_OFFSET 0x001c
++
++#define VLYNQ_RX0MAP_SIZE_REG_OFFSET 0x0020
++#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET 0x0024
++
++#define VLYNQ_CHIP_VER_OFFSET 0x0040
++#define VLYNQ_IVR_REGS_OFFSET 0x0060
++
++#define VLYNQ_INT_PENDING_REG_PTR 0x14
++#define VLYNQ_R_INT_PENDING_REG_PTR VLYNQ_REMOTE_REGS_OFFSET + 0x14
++
++#define VLYNQ_REV_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
++#define VLYNQ_CTRL_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
++#define VLYNQ_STATUS_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
++#define VLYNQ_INT_STAT_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
++#define VLYNQ_INT_PEND_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
++#define VLYNQ_INT_PTR_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
++#define VLYNQ_TXMAP_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
++
++/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
++#define VLYNQ_RXMAP_SIZE_REG(map) \
++ *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
++
++/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
++#define VLYNQ_RXMAP_OFFSET_REG(map) \
++ *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
++
++#define VLYNQ_CHIP_VER_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
++
++/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
++#define VLYNQ_IVR_OFFSET(ivr) \
++ (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
++
++#define VLYNQ_IVR_03TO00_REG *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(0)) )
++#define VLYNQ_IVR_07TO04_REG *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(4)) )
++/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
++
++#define VLYNQ_IVR_INTEN(ivr) (((unsigned int)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
++#define VLYNQ_IVR_INTTYPE(ivr) (((unsigned int)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
++#define VLYNQ_IVR_INTPOL(ivr) (((unsigned int)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
++#define VLYNQ_IVR_INTVEC(ivr) (((unsigned int)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
++#define VLYNQ_IVR_INTALL(ivr) (((unsigned int)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
++
++
++
++/*********************************
++ * Remote VLYNQ register set *
++ *********************************/
++
++#define VLYNQ_R_REV_OFFSET 0x0080
++#define VLYNQ_R_CTRL_OFFSET 0x0084
++#define VLYNQ_R_STATUS_OFFSET 0x0088
++#define VLYNQ_R_INT_STAT_OFFSET 0x0090
++#define VLYNQ_R_INT_PEND_OFFSET 0x0094
++#define VLYNQ_R_INT_PTR_OFFSET 0x0098
++#define VLYNQ_R_TXMAP_OFFSET 0x009c
++
++#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET 0x00A0
++#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
++
++#define VLYNQ_R_CHIP_VER_OFFSET 0x00C0
++#define VLYNQ_R_IVR_REGS_OFFSET 0x00E0
++
++#define VLYNQ_R_REV_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
++#define VLYNQ_R_CTRL_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
++#define VLYNQ_R_STATUS_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
++#define VLYNQ_R_INT_STAT_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
++#define VLYNQ_R_INT_PEND_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
++#define VLYNQ_R_INT_PTR_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
++#define VLYNQ_R_TXMAP_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
++
++/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
++#define VLYNQ_R_RXMAP_SIZE_REG(map) \
++ *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
++
++/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
++#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
++ *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
++
++#define VLYNQ_R_CHIP_VER_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
++
++#define VLYNQ_R_IVR_OFFSET(ivr) \
++ (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
++
++
++/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
++#define VLYNQ_R_IVR_03TO00_REG *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(0)) )
++#define VLYNQ_R_IVR_07TO04_REG *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(4)) )
++
++
++/****End of remote register set definition******/
++
++
++/*** Masks for individual register fields ***/
++
++#define VLYNQ_MODULE_ID_MASK 0xffff0000
++#define VLYNQ_MAJOR_REV_MASK 0x0000ff00
++#define VLYNQ_MINOR_REV_MASK 0x000000ff
++
++
++#define VLYNQ_CTL_ILOOP_MASK 0x00000002
++#define VLYNQ_CTL_INT2CFG_MASK 0x00000080
++#define VLYNQ_CTL_INTVEC_MASK 0x00001f00
++#define VLYNQ_CTL_INTEN_MASK 0x00002000
++#define VLYNQ_CTL_INTLOCAL_MASK 0x00004000
++#define VLYNQ_CTL_CLKDIR_MASK 0x00008000
++#define VLYNQ_CTL_CLKDIV_MASK 0x00070000
++#define VLYNQ_CTL_MODE_MASK 0x00e00000
++
++
++#define VLYNQ_STS_LINK_MASK 0x00000001 /* Link is active */
++#define VLYNQ_STS_MPEND_MASK 0x00000002 /* Pending master requests */
++#define VLYNQ_STS_SPEND_MASK 0x00000004 /* Pending slave requests */
++#define VLYNQ_STS_NFEMPTY0_MASK 0x00000008 /* Master data FIFO not empty */
++#define VLYNQ_STS_NFEMPTY1_MASK 0x00000010 /* Master command FIFO not empty */
++#define VLYNQ_STS_NFEMPTY2_MASK 0x00000020 /* Slave data FIFO not empty */
++#define VLYNQ_STS_NFEMPTY3_MASK 0x00000040 /* Slave command FIFO not empty */
++#define VLYNQ_STS_LERROR_MASK 0x00000080 /* Local error, w/c */
++#define VLYNQ_STS_RERROR_MASK 0x00000100 /* remote error w/c */
++#define VLYNQ_STS_OFLOW_MASK 0x00000200
++#define VLYNQ_STS_IFLOW_MASK 0x00000400
++#define VLYNQ_STS_MODESUP_MASK 0x00E00000 /* Highest mode supported */
++#define VLYNQ_STS_SWIDTH_MASK 0x07000000 /* Used for reading the width of VLYNQ bus */
++#define VLYNQ_STS_DEBUG_MASK 0xE0000000
++
++#define VLYNQ_CTL_INTVEC_SHIFT 0x08
++#define VLYNQ_CTL_INTEN_SHIFT 0x0D
++#define VLYNQ_CTL_INT2CFG_SHIFT 0x07
++#define VLYNQ_CTL_INTLOCAL_SHIFT 0x0E
++
++#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK 0x7F80
++
++#define VLYNQ_CHIPVER_DEVREV_MASK 0xffff0000
++#define VLYNQ_CHIPVER_DEVID_MASK 0x0000ffff
++
++#define VLYNQ_IVR_INTEN_MASK 0x80
++#define VLYNQ_IVR_INTTYPE_MASK 0x40
++#define VLYNQ_IVR_INTPOL_MASK 0x20
++
++
++/**** Helper macros ****/
++
++#define VLYNQ_RESETCB(arg) \
++ if( pdev->reset_cb != NULL) \
++ { \
++ (pdev->reset_cb)(pdev, (arg)); \
++ }
++
++#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
++#define VLYNQ_CTL_INTVEC(x) (((x) & 31) << 8 )
++
++#define VLYNQ_INRANGE(x,hi,lo) (((x) <= (hi)) && ((x) >= (lo)))
++#define VLYNQ_OUTRANGE(x,hi,lo) (((x) > (hi)) || ((x) < (lo)))
++
++#define VLYNQ_ALIGN4(x) (x)=(x)&(~3)
++
++
++/*************************************
++ * Enums *
++ *************************************/
++
++/* Initialization options define what operations are
++ * undertaken during vlynq module initialization */
++typedef enum
++{
++ /* Init host local memory regions.This allows
++ * local host access remote memory regions */
++ VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
++ /* Init host remote memory regions.This allows
++ * remote device access local memory regions */
++ VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
++ /* Init local interrupt config*/
++ VLYNQ_INIT_LOCAL_INTERRUPTS =0x04,
++ /* Init remote interrupt config*/
++ VLYNQ_INIT_REMOTE_INTERRUPTS =0x08,
++ /* Check link during initialization*/
++ VLYNQ_INIT_CHECK_LINK =0x10,
++ /* configure clock during init */
++ VLYNQ_INIT_CONFIG_CLOCK =0x20,
++ /* Clear errors during init */
++ VLYNQ_INIT_CLEAR_ERRORS =0x40,
++ /* All options */
++ VLYNQ_INIT_PERFORM_ALL =0x7F
++}VLYNQ_INIT_OPTIONS;
++
++
++/* VLYNQ_DEV_TYPE identifies local or remote device */
++typedef enum
++{
++ VLYNQ_LOCAL_DVC = 0, /* vlynq local device (SOC's vlynq module) */
++ VLYNQ_REMOTE_DVC = 1 /* vlynq remote device (remote vlynq module) */
++}VLYNQ_DEV_TYPE;
++
++
++/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
++typedef enum
++{
++ VLYNQ_CLK_SOURCE_NONE = 0, /* do not initialize clock generator*/
++ VLYNQ_CLK_SOURCE_LOCAL = 1, /* clock is generated by local machine */
++ VLYNQ_CLK_SOURCE_REMOTE = 2 /* clock is generated by remote machine */
++}VLYNQ_CLK_SOURCE;
++
++
++/* VLYNQ_DRV_STATE indicates the current driver state */
++typedef enum
++{
++ VLYNQ_DRV_STATE_UNINIT = 0, /* driver is uninitialized */
++ VLYNQ_DRV_STATE_ININIT = 1, /* VLYNQ is being initialized */
++ VLYNQ_DRV_STATE_RUN = 2, /* VLYNQ is running properly */
++ VLYNQ_DRV_STATE_HOLD = 3, /* driver stopped temporarily */
++ VLYNQ_DRV_STATE_ERROR = 4 /* driver stopped on unrecoverable error */
++}VLYNQ_DRV_STATE;
++
++
++/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
++typedef enum
++{
++ VLYNQ_BUS_WIDTH_3 = 3,
++ VLYNQ_BUS_WIDTH_5 = 5,
++ VLYNQ_BUS_WIDTH_7 = 7,
++ VLYNQ_BUS_WIDTH_9 = 9
++}VLYNQ_BUS_WIDTH;
++
++
++/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
++ * interrupts are processed by the host or passed on to the
++ * remote device.
++ */
++typedef enum
++{
++ VLYNQ_INT_REMOTE = 0, /* Interrupt packets sent to remote, intlocal=0 */
++ VLYNQ_INT_LOCAL = 1 /* Interrupts are handled locally, intlocal=1 */
++}VLYNQ_LOCAL_INT_CONFIG;
++
++
++/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
++ * interrupts are to be handled by the SOC system ISR
++ * or via the vlynq root ISR
++ */
++typedef enum
++{
++ VLYNQ_INT_ROOT_ISR = 0, /* remote ints handled via vlynq root ISR */
++ VLYNQ_INT_SYSTEM_ISR = 1 /* remote ints handled via system ISR */
++}VLYNQ_REMOTE_INT_CONFIG;
++
++
++/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
++typedef enum
++{
++ VLYNQ_INTR_ACTIVE_HIGH = 0,
++ VLYNQ_INTR_ACTIVE_LOW = 1
++}VLYNQ_INTR_POLARITY;
++
++
++/* VLYNQ_INTR_TYPE - vlynq interrupt type */
++typedef enum
++{
++ VLYNQ_INTR_LEVEL = 0,
++ VLYNQ_INTR_PULSED = 1
++}VLYNQ_INTR_TYPE;
++
++
++/* VLYNQ_RESET_MODE - vlynq reset mode */
++typedef enum
++{
++ VLYNQ_RESET_ASSERT, /* hold device in reset state */
++ VLYNQ_RESET_DEASSERT, /* release device from reset state */
++ VLYNQ_RESET_INITFAIL, /* handle the device in case driver initialization fails */
++ VLYNQ_RESET_LINKESTABLISH, /* handle the device in case driver established link */
++ VLYNQ_RESET_INITFAIL2, /* Driver initialization failed but VLYNQ link exist. */
++ VLYNQ_RESET_INITOK /* Driver initialization finished OK. */
++}VLYNQ_RESET_MODE;
++
++
++
++/*************************************
++ * Typedefs *
++ *************************************/
++
++struct VLYNQ_DEV_t; /*forward declaration*/
++
++/*--------Function Pointers defintions -----------*/
++
++/* prototype for interrupt handler definition */
++typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
++
++typedef void
++(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
++
++typedef void
++(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev, /* This VLYNQ */
++ VLYNQ_DEV_TYPE aSrcDvc, /* Event Cause -local/remote? */
++ unsigned int dwStatRegVal); /* Value of the relevant status register */
++
++
++/*-------Structure Definitions------------*/
++
++typedef struct VLYNQ_MEMORY_MAP_t
++{
++ unsigned int Txmap;
++ unsigned int RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
++ unsigned int RxSize[VLYNQ_MAX_MEMORY_REGIONS];
++}VLYNQ_MEMORY_MAP;
++
++
++/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
++ * settings in vlynq Control register */
++typedef struct VLYNQ_INTERRUPT_CNTRL_t
++{
++ /* vlynq interrupts handled by host or remote - maps to
++ * intLocal bit in vlynq control register */
++ VLYNQ_LOCAL_INT_CONFIG intLocal;
++
++ /* remote interrupts handled by vlynq isr or host system
++ * interrupt controller - maps to the int2Cfg in vlynq
++ * control register */
++ VLYNQ_REMOTE_INT_CONFIG intRemote;
++
++ /* bit in pending/set register used for module interrupts*/
++ unsigned int map_vector;
++
++ /* used only if remote interrupts are to be handled by system ISR*/
++ unsigned int intr_ptr;
++
++}VLYNQ_INTERRUPT_CNTRL;
++
++
++/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
++ * the interrupt dispatch table. The vlynq_root_isr() indexes into this
++ * table to identify the ISR to be invoked
++ */
++typedef struct VLYNQ_INTR_CNTRL_ICB_t
++{
++ VLYNQ_INTR_CNTRL_ISR isr; /* Clear errors during initialization */
++ void *arg1 ; /* Arg 1 for the ISR */
++ void *arg2 ; /* Arg 2 for the ISR */
++ void *arg3 ; /* Arg 3 for the ISR */
++ unsigned int isrCount; /* number of ISR invocations so far */
++ struct VLYNQ_INTR_CNTRL_ICB_t *next;
++}VLYNQ_INTR_CNTRL_ICB;
++
++/* overlay of vlynq register set */
++typedef struct VLYNQ_REG_SET_t
++{
++ unsigned int revision; /*offset : 0x00 */
++ unsigned int control; /* 0x04*/
++ unsigned int status; /* 0x08*/
++ unsigned int pad1; /* 0x0c*/
++ unsigned int intStatus; /*0x10*/
++ unsigned int intPending; /*0x14*/
++ unsigned int intPtr; /*0x18*/
++ unsigned int txMap; /*0x1C*/
++ unsigned int rxSize1; /*0x20*/
++ unsigned int rxOffset1; /*0x24*/
++ unsigned int rxSize2; /*0x28*/
++ unsigned int rxOffset2; /*0x2C*/
++ unsigned int rxSize3; /*0x30*/
++ unsigned int rxOffset3; /*0x34*/
++ unsigned int rxSize4; /*0x38*/
++ unsigned int rxOffset4; /*0x3C*/
++ unsigned int chipVersion; /*0x40*/
++ unsigned int pad2[8];
++ unsigned int ivr30; /*0x60*/
++ unsigned int ivr74; /*0x64*/
++ unsigned int pad3[7];
++}VLYNQ_REG_SET;
++
++
++typedef struct VLYNQ_DEV_t
++{
++ /** module index:1,2,3... used for debugging purposes */
++ unsigned int dev_idx;
++
++ /*VLYNQ module base address */
++ unsigned int module_base;
++
++ /* clock source selection */
++ VLYNQ_CLK_SOURCE clk_source;
++
++ /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
++ unsigned int clk_div;
++
++ /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
++ VLYNQ_DRV_STATE state;
++
++ /* Valid VLYNQ bus width, filled by driver */
++ VLYNQ_BUS_WIDTH width;
++
++ /* local memory mapping */
++ VLYNQ_MEMORY_MAP local_mem;
++
++ /* remote memory mapping */
++ VLYNQ_MEMORY_MAP remote_mem;
++
++ /* Local module interrupt params */
++ VLYNQ_INTERRUPT_CNTRL local_irq;
++
++ /* remote module interrupt params */
++ VLYNQ_INTERRUPT_CNTRL remote_irq;
++
++ /*** ICB related fields **/
++
++ /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
++ * expansion slots for shared interrupts*/
++ VLYNQ_INTR_CNTRL_ICB pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
++ VLYNQ_INTR_CNTRL_ICB *freelist;
++
++ /* table holding mapping between intVector and the bit position the interrupt
++ * is mapped to(mapVector)*/
++ char vector_map[32];
++
++ /* user callback for vlynq events, NULL if unused */
++ VLYNQ_REPORT_CB report_cb;
++
++ /* user callback for resetting/realeasing remote device */
++ VLYNQ_RESET_REMOTE reset_cb;
++
++ /*** Handles provided for direct access to register set if need be
++ * Must be intialized to point to appropriate address during
++ * vlynq_init */
++ volatile VLYNQ_REG_SET * local;
++ volatile VLYNQ_REG_SET * remote;
++
++ unsigned int intCount; /* number of interrupts generated so far */
++ unsigned int isrCount; /* number of ISR invocations so far */
++}VLYNQ_DEV;
++
++
++typedef struct VLYNQ_ISR_ARGS_t
++{
++ int irq;
++ void * arg;
++ void * regset;
++}VLYNQ_ISR_ARGS;
++
++
++/****************************************
++ * Function Prototypes *
++ * API exported by generic vlynq driver *
++ ****************************************/
++/* Initialization function */
++int vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
++
++/* Check vlynq link */
++unsigned int vlynq_link_check( VLYNQ_DEV * pdev);
++
++/* Set interrupt vector in local or remote device */
++int vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
++ unsigned int int_vector,
++ unsigned int map_vector,
++ VLYNQ_DEV_TYPE dev,
++ VLYNQ_INTR_POLARITY pol,
++ VLYNQ_INTR_TYPE type);
++
++
++int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
++ unsigned int int_vector,
++ VLYNQ_DEV_TYPE dev,
++ unsigned int enable);
++
++unsigned int vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
++ unsigned int map_vector);
++
++int vlynq_install_isr( VLYNQ_DEV *pdev,
++ unsigned int map_vector,
++ VLYNQ_INTR_CNTRL_ISR isr,
++ void *arg1, void *arg2, void *arg3);
++
++int vlynq_uninstall_isr( VLYNQ_DEV *pdev,
++ unsigned int map_vector,
++ void *arg1, void *arg2, void *arg3);
++
++
++void vlynq_root_isr(void *arg);
++
++void vlynq_delay(unsigned int clktime);
++
++/* The following functions, provide better granularity in setting
++ * interrupt parameters. (for better support of linux INT Controller)
++ * Note: The interrupt source is identified by "map_vector"- the bit
++ * position in interrupt status register*/
++
++int vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
++ VLYNQ_DEV_TYPE dev,
++ unsigned int int_vector,
++ unsigned int map_vector);
++
++int vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
++ VLYNQ_DEV_TYPE dev,
++ unsigned int map_vector,
++ VLYNQ_INTR_POLARITY pol);
++
++int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
++ VLYNQ_DEV_TYPE dev_type,
++ unsigned int map_vector);
++
++int vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
++ VLYNQ_DEV_TYPE dev,
++ unsigned int map_vector,
++ VLYNQ_INTR_TYPE type);
++
++int vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
++ VLYNQ_DEV_TYPE dev_type,
++ unsigned int map_vector);
++
++int vlynq_interrupt_enable(VLYNQ_DEV* pdev,
++ VLYNQ_DEV_TYPE dev,
++ unsigned int map_vector);
++
++int vlynq_interrupt_disable(VLYNQ_DEV * pdev,
++ VLYNQ_DEV_TYPE dev,
++ unsigned int map_vector);
++
++
++
++
++
++#endif /* _VLYNQ_HAL_H_ */
+diff -urN linux.old/include/asm-mips/ar7/vlynq_hal.h linux.dev/include/asm-mips/ar7/vlynq_hal.h
+--- linux.old/include/asm-mips/ar7/vlynq_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/vlynq_hal.h 2005-11-10 01:10:46.095590250 +0100
+@@ -0,0 +1,606 @@
++/***************************************************************************
++**+----------------------------------------------------------------------+**
++**| **** |**
++**| **** |**
++**| ******o*** |**
++**| ********_///_**** |**
++**| ***** /_//_/ **** |**
++**| ** ** (__/ **** |**
++**| ********* |**
++**| **** |**
++**| *** |**
++**| |**
++**| Copyright (c) 2003 Texas Instruments Incorporated |**
++**| ALL RIGHTS RESERVED |**
++**| |**
++**| Permission is hereby granted to licensees of Texas Instruments |**
++**| Incorporated (TI) products to use this computer program for the sole |**
++**| purpose of implementing a licensee product based on TI products. |**
++**| No other rights to reproduce, use, or disseminate this computer |**
++**| program, whether in part or in whole, are granted. |**
++**| |**
++**| TI makes no representation or warranties with respect to the |**
++**| performance of this computer program, and specifically disclaims |**
++**| any responsibility for any damages, special or consequential, |**
++**| connected with the use of this program. |**
++**| |**
++**+----------------------------------------------------------------------+**
++***************************************************************************/
++
++/*********************************************************************************
++ * ------------------------------------------------------------------------------
++ * Module : vlynq_hal.h
++ * Description :
++ * This header file provides the set of functions exported by the
++ * VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
++ * ------------------------------------------------------------------------------
++ *********************************************************************************/
++
++#ifndef _VLYNQ_HAL_H_
++#define _VLYNQ_HAL_H_
++
++#include <asm/ar7/avalanche_types.h>
++#include <asm/ar7/vlynq_hal_params.h>
++
++#ifndef PRIVATE
++#define PRIVATE static
++#endif
++
++#ifndef GLOBAL
++#define GLOBAL
++#endif
++
++/* Enable/Disable debug feature */
++#undef VLYNQ_DEBUG
++
++#ifdef VLYNQ_DEBUG /* This needs to be OS abstracted - for testing use vxworks/linux calls */
++#define debugPrint(format,args...)
++#else
++#define debugPrint(format,args...)
++#endif
++
++/* Error defines */
++#define VLYNQ_SUCCESS 0
++
++#define VLYNQ_ERRCODE_BASE 0 /* Chosen by system */
++#define VLYNQ_INVALID_ARG -(VLYNQ_ERRCODE_BASE+1)
++#define VLYNQ_INVALID_DRV_STATE -(VLYNQ_ERRCODE_BASE+2)
++#define VLYNQ_INT_CONFIG_ERR -(VLYNQ_ERRCODE_BASE+3)
++#define VLYNQ_LINK_DOWN -(VLYNQ_ERRCODE_BASE+4)
++#define VLYNQ_MEMALLOC_FAIL -(VLYNQ_ERRCODE_BASE+5)
++#define VLYNQ_ISR_NON_EXISTENT -(VLYNQ_ERRCODE_BASE+6)
++#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
++
++/* Vlynq Defines and Macros */
++
++#define VLYNQ_NUM_INT_BITS 32 /* 32 bit interrupt staus register */
++
++/* Base address of module */
++#define VLYNQ_BASE (pdev->module_base)
++
++#define VLYNQ_REMOTE_REGS_OFFSET 0x0080
++
++#define VLYNQ_REV_OFFSET 0x0000
++#define VLYNQ_CTRL_OFFSET 0x0004
++#define VLYNQ_STATUS_OFFSET 0x0008
++#define VLYNQ_INT_STAT_OFFSET 0x0010
++#define VLYNQ_INT_PEND_OFFSET 0x0014
++#define VLYNQ_INT_PTR_OFFSET 0x0018
++#define VLYNQ_TXMAP_OFFSET 0x001c
++
++#define VLYNQ_RX0MAP_SIZE_REG_OFFSET 0x0020
++#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET 0x0024
++
++#define VLYNQ_CHIP_VER_OFFSET 0x0040
++#define VLYNQ_IVR_REGS_OFFSET 0x0060
++
++#define VLYNQ_INT_PENDING_REG_PTR 0x14
++#define VLYNQ_R_INT_PENDING_REG_PTR VLYNQ_REMOTE_REGS_OFFSET + 0x14
++
++#define VLYNQ_REV_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
++#define VLYNQ_CTRL_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
++#define VLYNQ_STATUS_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
++#define VLYNQ_INT_STAT_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
++#define VLYNQ_INT_PEND_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
++#define VLYNQ_INT_PTR_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
++#define VLYNQ_TXMAP_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
++
++/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
++#define VLYNQ_RXMAP_SIZE_REG(map) \
++ *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
++
++/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
++#define VLYNQ_RXMAP_OFFSET_REG(map) \
++ *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
++
++#define VLYNQ_CHIP_VER_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
++
++/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
++#define VLYNQ_IVR_OFFSET(ivr) \
++ (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
++
++#define VLYNQ_IVR_03TO00_REG *((volatile UINT32*) (VLYNQ_IVR_OFFSET(0)) )
++#define VLYNQ_IVR_07TO04_REG *((volatile UINT32*) (VLYNQ_IVR_OFFSET(4)) )
++/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
++
++#define VLYNQ_IVR_INTEN(ivr) (((UINT32)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
++#define VLYNQ_IVR_INTTYPE(ivr) (((UINT32)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
++#define VLYNQ_IVR_INTPOL(ivr) (((UINT32)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
++#define VLYNQ_IVR_INTVEC(ivr) (((UINT32)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
++#define VLYNQ_IVR_INTALL(ivr) (((UINT32)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
++
++
++
++/*********************************
++ * Remote VLYNQ register set *
++ *********************************/
++
++#define VLYNQ_R_REV_OFFSET 0x0080
++#define VLYNQ_R_CTRL_OFFSET 0x0084
++#define VLYNQ_R_STATUS_OFFSET 0x0088
++#define VLYNQ_R_INT_STAT_OFFSET 0x0090
++#define VLYNQ_R_INT_PEND_OFFSET 0x0094
++#define VLYNQ_R_INT_PTR_OFFSET 0x0098
++#define VLYNQ_R_TXMAP_OFFSET 0x009c
++
++#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET 0x00A0
++#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
++
++#define VLYNQ_R_CHIP_VER_OFFSET 0x00C0
++#define VLYNQ_R_IVR_REGS_OFFSET 0x00E0
++
++#define VLYNQ_R_REV_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
++#define VLYNQ_R_CTRL_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
++#define VLYNQ_R_STATUS_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
++#define VLYNQ_R_INT_STAT_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
++#define VLYNQ_R_INT_PEND_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
++#define VLYNQ_R_INT_PTR_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
++#define VLYNQ_R_TXMAP_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
++
++/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
++#define VLYNQ_R_RXMAP_SIZE_REG(map) \
++ *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
++
++/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
++#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
++ *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
++
++#define VLYNQ_R_CHIP_VER_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
++
++#define VLYNQ_R_IVR_OFFSET(ivr) \
++ (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
++
++
++/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
++#define VLYNQ_R_IVR_03TO00_REG *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(0)) )
++#define VLYNQ_R_IVR_07TO04_REG *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(4)) )
++
++
++/****End of remote register set definition******/
++
++
++/*** Masks for individual register fields ***/
++
++#define VLYNQ_MODULE_ID_MASK 0xffff0000
++#define VLYNQ_MAJOR_REV_MASK 0x0000ff00
++#define VLYNQ_MINOR_REV_MASK 0x000000ff
++
++
++#define VLYNQ_CTL_ILOOP_MASK 0x00000002
++#define VLYNQ_CTL_INT2CFG_MASK 0x00000080
++#define VLYNQ_CTL_INTVEC_MASK 0x00001f00
++#define VLYNQ_CTL_INTEN_MASK 0x00002000
++#define VLYNQ_CTL_INTLOCAL_MASK 0x00004000
++#define VLYNQ_CTL_CLKDIR_MASK 0x00008000
++#define VLYNQ_CTL_CLKDIV_MASK 0x00070000
++#define VLYNQ_CTL_MODE_MASK 0x00e00000
++
++
++#define VLYNQ_STS_LINK_MASK 0x00000001 /* Link is active */
++#define VLYNQ_STS_MPEND_MASK 0x00000002 /* Pending master requests */
++#define VLYNQ_STS_SPEND_MASK 0x00000004 /* Pending slave requests */
++#define VLYNQ_STS_NFEMPTY0_MASK 0x00000008 /* Master data FIFO not empty */
++#define VLYNQ_STS_NFEMPTY1_MASK 0x00000010 /* Master command FIFO not empty */
++#define VLYNQ_STS_NFEMPTY2_MASK 0x00000020 /* Slave data FIFO not empty */
++#define VLYNQ_STS_NFEMPTY3_MASK 0x00000040 /* Slave command FIFO not empty */
++#define VLYNQ_STS_LERROR_MASK 0x00000080 /* Local error, w/c */
++#define VLYNQ_STS_RERROR_MASK 0x00000100 /* remote error w/c */
++#define VLYNQ_STS_OFLOW_MASK 0x00000200
++#define VLYNQ_STS_IFLOW_MASK 0x00000400
++#define VLYNQ_STS_MODESUP_MASK 0x00E00000 /* Highest mode supported */
++#define VLYNQ_STS_SWIDTH_MASK 0x07000000 /* Used for reading the width of VLYNQ bus */
++#define VLYNQ_STS_DEBUG_MASK 0xE0000000
++
++#define VLYNQ_CTL_INTVEC_SHIFT 0x08
++#define VLYNQ_CTL_INTEN_SHIFT 0x0D
++#define VLYNQ_CTL_INT2CFG_SHIFT 0x07
++#define VLYNQ_CTL_INTLOCAL_SHIFT 0x0E
++
++#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK 0x7F80
++
++#define VLYNQ_CHIPVER_DEVREV_MASK 0xffff0000
++#define VLYNQ_CHIPVER_DEVID_MASK 0x0000ffff
++
++#define VLYNQ_IVR_INTEN_MASK 0x80
++#define VLYNQ_IVR_INTTYPE_MASK 0x40
++#define VLYNQ_IVR_INTPOL_MASK 0x20
++
++
++/**** Helper macros ****/
++
++#define VLYNQ_RESETCB(arg) \
++ if( pdev->reset_cb != NULL) \
++ { \
++ (pdev->reset_cb)(pdev, (arg)); \
++ }
++
++#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
++#define VLYNQ_CTL_INTVEC(x) (((x) & 31) << 8 )
++
++#define VLYNQ_INRANGE(x,hi,lo) (((x) <= (hi)) && ((x) >= (lo)))
++#define VLYNQ_OUTRANGE(x,hi,lo) (((x) > (hi)) || ((x) < (lo)))
++
++#define VLYNQ_ALIGN4(x) (x)=(x)&(~3)
++
++
++/*************************************
++ * Enums *
++ *************************************/
++
++/* Initialization options define what operations are
++ * undertaken during vlynq module initialization */
++typedef enum
++{
++ /* Init host local memory regions.This allows
++ * local host access remote memory regions */
++ VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
++ /* Init host remote memory regions.This allows
++ * remote device access local memory regions */
++ VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
++ /* Init local interrupt config*/
++ VLYNQ_INIT_LOCAL_INTERRUPTS =0x04,
++ /* Init remote interrupt config*/
++ VLYNQ_INIT_REMOTE_INTERRUPTS =0x08,
++ /* Check link during initialization*/
++ VLYNQ_INIT_CHECK_LINK =0x10,
++ /* configure clock during init */
++ VLYNQ_INIT_CONFIG_CLOCK =0x20,
++ /* Clear errors during init */
++ VLYNQ_INIT_CLEAR_ERRORS =0x40,
++ /* All options */
++ VLYNQ_INIT_PERFORM_ALL =0x7F
++}VLYNQ_INIT_OPTIONS;
++
++
++/* VLYNQ_DEV_TYPE identifies local or remote device */
++typedef enum
++{
++ VLYNQ_LOCAL_DVC = 0, /* vlynq local device (SOC's vlynq module) */
++ VLYNQ_REMOTE_DVC = 1 /* vlynq remote device (remote vlynq module) */
++}VLYNQ_DEV_TYPE;
++
++
++/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
++typedef enum
++{
++ VLYNQ_CLK_SOURCE_NONE = 0, /* do not initialize clock generator*/
++ VLYNQ_CLK_SOURCE_LOCAL = 1, /* clock is generated by local machine */
++ VLYNQ_CLK_SOURCE_REMOTE = 2 /* clock is generated by remote machine */
++}VLYNQ_CLK_SOURCE;
++
++
++/* VLYNQ_DRV_STATE indicates the current driver state */
++typedef enum
++{
++ VLYNQ_DRV_STATE_UNINIT = 0, /* driver is uninitialized */
++ VLYNQ_DRV_STATE_ININIT = 1, /* VLYNQ is being initialized */
++ VLYNQ_DRV_STATE_RUN = 2, /* VLYNQ is running properly */
++ VLYNQ_DRV_STATE_HOLD = 3, /* driver stopped temporarily */
++ VLYNQ_DRV_STATE_ERROR = 4 /* driver stopped on unrecoverable error */
++}VLYNQ_DRV_STATE;
++
++
++/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
++typedef enum
++{
++ VLYNQ_BUS_WIDTH_3 = 3,
++ VLYNQ_BUS_WIDTH_5 = 5,
++ VLYNQ_BUS_WIDTH_7 = 7,
++ VLYNQ_BUS_WIDTH_9 = 9
++}VLYNQ_BUS_WIDTH;
++
++
++/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
++ * interrupts are processed by the host or passed on to the
++ * remote device.
++ */
++typedef enum
++{
++ VLYNQ_INT_REMOTE = 0, /* Interrupt packets sent to remote, intlocal=0 */
++ VLYNQ_INT_LOCAL = 1 /* Interrupts are handled locally, intlocal=1 */
++}VLYNQ_LOCAL_INT_CONFIG;
++
++
++/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
++ * interrupts are to be handled by the SOC system ISR
++ * or via the vlynq root ISR
++ */
++typedef enum
++{
++ VLYNQ_INT_ROOT_ISR = 0, /* remote ints handled via vlynq root ISR */
++ VLYNQ_INT_SYSTEM_ISR = 1 /* remote ints handled via system ISR */
++}VLYNQ_REMOTE_INT_CONFIG;
++
++
++/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
++typedef enum
++{
++ VLYNQ_INTR_ACTIVE_HIGH = 0,
++ VLYNQ_INTR_ACTIVE_LOW = 1
++}VLYNQ_INTR_POLARITY;
++
++
++/* VLYNQ_INTR_TYPE - vlynq interrupt type */
++typedef enum
++{
++ VLYNQ_INTR_LEVEL = 0,
++ VLYNQ_INTR_PULSED = 1
++}VLYNQ_INTR_TYPE;
++
++
++/* VLYNQ_RESET_MODE - vlynq reset mode */
++typedef enum
++{
++ VLYNQ_RESET_ASSERT, /* hold device in reset state */
++ VLYNQ_RESET_DEASSERT, /* release device from reset state */
++ VLYNQ_RESET_INITFAIL, /* handle the device in case driver initialization fails */
++ VLYNQ_RESET_LINKESTABLISH, /* handle the device in case driver established link */
++ VLYNQ_RESET_INITFAIL2, /* Driver initialization failed but VLYNQ link exist. */
++ VLYNQ_RESET_INITOK /* Driver initialization finished OK. */
++}VLYNQ_RESET_MODE;
++
++
++
++/*************************************
++ * Typedefs *
++ *************************************/
++
++struct VLYNQ_DEV_t; /*forward declaration*/
++
++/*--------Function Pointers defintions -----------*/
++
++/* prototype for interrupt handler definition */
++typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
++
++typedef void
++(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
++
++typedef void
++(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev, /* This VLYNQ */
++ VLYNQ_DEV_TYPE aSrcDvc, /* Event Cause -local/remote? */
++ UINT32 dwStatRegVal); /* Value of the relevant status register */
++
++
++/*-------Structure Definitions------------*/
++
++typedef struct VLYNQ_MEMORY_MAP_t
++{
++ UINT32 Txmap;
++ UINT32 RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
++ UINT32 RxSize[VLYNQ_MAX_MEMORY_REGIONS];
++}VLYNQ_MEMORY_MAP;
++
++
++/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
++ * settings in vlynq Control register */
++typedef struct VLYNQ_INTERRUPT_CNTRL_t
++{
++ /* vlynq interrupts handled by host or remote - maps to
++ * intLocal bit in vlynq control register */
++ VLYNQ_LOCAL_INT_CONFIG intLocal;
++
++ /* remote interrupts handled by vlynq isr or host system
++ * interrupt controller - maps to the int2Cfg in vlynq
++ * control register */
++ VLYNQ_REMOTE_INT_CONFIG intRemote;
++
++ /* bit in pending/set register used for module interrupts*/
++ UINT32 map_vector;
++
++ /* used only if remote interrupts are to be handled by system ISR*/
++ UINT32 intr_ptr;
++
++}VLYNQ_INTERRUPT_CNTRL;
++
++
++/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
++ * the interrupt dispatch table. The vlynq_root_isr() indexes into this
++ * table to identify the ISR to be invoked
++ */
++typedef struct VLYNQ_INTR_CNTRL_ICB_t
++{
++ VLYNQ_INTR_CNTRL_ISR isr; /* Clear errors during initialization */
++ void *arg1 ; /* Arg 1 for the ISR */
++ void *arg2 ; /* Arg 2 for the ISR */
++ void *arg3 ; /* Arg 3 for the ISR */
++ UINT32 isrCount; /* number of ISR invocations so far */
++ struct VLYNQ_INTR_CNTRL_ICB_t *next;
++}VLYNQ_INTR_CNTRL_ICB;
++
++/* overlay of vlynq register set */
++typedef struct VLYNQ_REG_SET_t
++{
++ UINT32 revision; /*offset : 0x00 */
++ UINT32 control; /* 0x04*/
++ UINT32 status; /* 0x08*/
++ UINT32 pad1; /* 0x0c*/
++ UINT32 intStatus; /*0x10*/
++ UINT32 intPending; /*0x14*/
++ UINT32 intPtr; /*0x18*/
++ UINT32 txMap; /*0x1C*/
++ UINT32 rxSize1; /*0x20*/
++ UINT32 rxOffset1; /*0x24*/
++ UINT32 rxSize2; /*0x28*/
++ UINT32 rxOffset2; /*0x2C*/
++ UINT32 rxSize3; /*0x30*/
++ UINT32 rxOffset3; /*0x34*/
++ UINT32 rxSize4; /*0x38*/
++ UINT32 rxOffset4; /*0x3C*/
++ UINT32 chipVersion; /*0x40*/
++ UINT32 pad2[8];
++ UINT32 ivr30; /*0x60*/
++ UINT32 ivr74; /*0x64*/
++ UINT32 pad3[7];
++}VLYNQ_REG_SET;
++
++
++typedef struct VLYNQ_DEV_t
++{
++ /** module index:1,2,3... used for debugging purposes */
++ UINT32 dev_idx;
++
++ /*VLYNQ module base address */
++ UINT32 module_base;
++
++ /* clock source selection */
++ VLYNQ_CLK_SOURCE clk_source;
++
++ /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
++ UINT32 clk_div;
++
++ /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
++ VLYNQ_DRV_STATE state;
++
++ /* Valid VLYNQ bus width, filled by driver */
++ VLYNQ_BUS_WIDTH width;
++
++ /* local memory mapping */
++ VLYNQ_MEMORY_MAP local_mem;
++
++ /* remote memory mapping */
++ VLYNQ_MEMORY_MAP remote_mem;
++
++ /* Local module interrupt params */
++ VLYNQ_INTERRUPT_CNTRL local_irq;
++
++ /* remote module interrupt params */
++ VLYNQ_INTERRUPT_CNTRL remote_irq;
++
++ /*** ICB related fields **/
++
++ /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
++ * expansion slots for shared interrupts*/
++ VLYNQ_INTR_CNTRL_ICB pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
++ VLYNQ_INTR_CNTRL_ICB *freelist;
++
++ /* table holding mapping between intVector and the bit position the interrupt
++ * is mapped to(mapVector)*/
++ INT8 vector_map[32];
++
++ /* user callback for vlynq events, NULL if unused */
++ VLYNQ_REPORT_CB report_cb;
++
++ /* user callback for resetting/realeasing remote device */
++ VLYNQ_RESET_REMOTE reset_cb;
++
++ /*** Handles provided for direct access to register set if need be
++ * Must be intialized to point to appropriate address during
++ * vlynq_init */
++ volatile VLYNQ_REG_SET * local;
++ volatile VLYNQ_REG_SET * remote;
++
++ UINT32 intCount; /* number of interrupts generated so far */
++ UINT32 isrCount; /* number of ISR invocations so far */
++}VLYNQ_DEV;
++
++
++typedef struct VLYNQ_ISR_ARGS_t
++{
++ int irq;
++ void * arg;
++ void * regset;
++}VLYNQ_ISR_ARGS;
++
++
++/****************************************
++ * Function Prototypes *
++ * API exported by generic vlynq driver *
++ ****************************************/
++/* Initialization function */
++GLOBAL INT32 vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
++
++/* Check vlynq link */
++GLOBAL UINT32 vlynq_link_check( VLYNQ_DEV * pdev);
++
++/* Set interrupt vector in local or remote device */
++GLOBAL INT32 vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
++ UINT32 int_vector,
++ UINT32 map_vector,
++ VLYNQ_DEV_TYPE dev,
++ VLYNQ_INTR_POLARITY pol,
++ VLYNQ_INTR_TYPE type);
++
++
++GLOBAL INT32 vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
++ UINT32 int_vector,
++ VLYNQ_DEV_TYPE dev,
++ UINT32 enable);
++
++GLOBAL UINT32 vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
++ UINT32 map_vector);
++
++GLOBAL INT32 vlynq_install_isr( VLYNQ_DEV *pdev,
++ UINT32 map_vector,
++ VLYNQ_INTR_CNTRL_ISR isr,
++ void *arg1, void *arg2, void *arg3);
++
++GLOBAL INT32 vlynq_uninstall_isr( VLYNQ_DEV *pdev,
++ UINT32 map_vector,
++ void *arg1, void *arg2, void *arg3);
++
++
++GLOBAL void vlynq_root_isr(void *arg);
++
++GLOBAL void vlynq_delay(UINT32 clktime);
++
++/* The following functions, provide better granularity in setting
++ * interrupt parameters. (for better support of linux INT Controller)
++ * Note: The interrupt source is identified by "map_vector"- the bit
++ * position in interrupt status register*/
++
++GLOBAL INT32 vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
++ VLYNQ_DEV_TYPE dev,
++ UINT32 int_vector,
++ UINT32 map_vector);
++
++GLOBAL INT32 vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
++ VLYNQ_DEV_TYPE dev,
++ UINT32 map_vector,
++ VLYNQ_INTR_POLARITY pol);
++
++GLOBAL INT32 vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
++ VLYNQ_DEV_TYPE dev_type,
++ UINT32 map_vector);
++
++GLOBAL INT32 vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
++ VLYNQ_DEV_TYPE dev,
++ UINT32 map_vector,
++ VLYNQ_INTR_TYPE type);
++
++GLOBAL INT32 vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
++ VLYNQ_DEV_TYPE dev_type,
++ UINT32 map_vector);
++
++GLOBAL INT32 vlynq_interrupt_enable(VLYNQ_DEV* pdev,
++ VLYNQ_DEV_TYPE dev,
++ UINT32 map_vector);
++
++GLOBAL INT32 vlynq_interrupt_disable(VLYNQ_DEV * pdev,
++ VLYNQ_DEV_TYPE dev,
++ UINT32 map_vector);
++
++
++
++
++
++#endif /* _VLYNQ_HAL_H_ */
+diff -urN linux.old/include/asm-mips/ar7/vlynq_hal_params.h linux.dev/include/asm-mips/ar7/vlynq_hal_params.h
+--- linux.old/include/asm-mips/ar7/vlynq_hal_params.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/vlynq_hal_params.h 2005-11-10 01:10:46.095590250 +0100
+@@ -0,0 +1,50 @@
++/***************************************************************************
++**+----------------------------------------------------------------------+**
++**| **** |**
++**| **** |**
++**| ******o*** |**
++**| ********_///_**** |**
++**| ***** /_//_/ **** |**
++**| ** ** (__/ **** |**
++**| ********* |**
++**| **** |**
++**| *** |**
++**| |**
++**| Copyright (c) 2003 Texas Instruments Incorporated |**
++**| ALL RIGHTS RESERVED |**
++**| |**
++**| Permission is hereby granted to licensees of Texas Instruments |**
++**| Incorporated (TI) products to use this computer program for the sole |**
++**| purpose of implementing a licensee product based on TI products. |**
++**| No other rights to reproduce, use, or disseminate this computer |**
++**| program, whether in part or in whole, are granted. |**
++**| |**
++**| TI makes no representation or warranties with respect to the |**
++**| performance of this computer program, and specifically disclaims |**
++**| any responsibility for any damages, special or consequential, |**
++**| connected with the use of this program. |**
++**| |**
++**+----------------------------------------------------------------------+**
++***************************************************************************/
++
++/* This file defines Vlynq module parameters*/
++
++#ifndef _VLYNQ_HAL_PARAMS_H
++#define _VLYNQ_HAL_PARAMS_H
++
++ /* number of VLYNQ memory regions supported */
++#define VLYNQ_MAX_MEMORY_REGIONS 0x04
++
++ /* Max.number of external interrupt inputs supported by VLYNQ module */
++#define VLYNQ_IVR_MAXIVR 0x08
++
++#define VLYNQ_CLK_DIV_MAX 0x08
++#define VLYNQ_CLK_DIV_MIN 0x01
++
++
++/*** the total number of entries allocated for ICB would be
++ * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
++#define VLYNQ_IVR_CHAIN_SLOTS 10
++
++
++#endif /* _VLYNQ_HAL_PARAMS_H */
+diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
+--- linux.old/include/asm-mips/io.h 2003-08-25 13:44:43.000000000 +0200
++++ linux.dev/include/asm-mips/io.h 2005-11-10 01:14:16.400733500 +0100
+@@ -61,9 +61,9 @@
+ * Change "struct page" to physical address.
+ */
+ #ifdef CONFIG_64BIT_PHYS_ADDR
+-#define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
++#define page_to_phys(page) (((u64)(page - mem_map) << PAGE_SHIFT) + PHYS_OFFSET)
+ #else
+-#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
++#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + PHYS_OFFSET)
+ #endif
+
+ #define IO_SPACE_LIMIT 0xffff
+diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
+--- linux.old/include/asm-mips/irq.h 2003-08-25 13:44:43.000000000 +0200
++++ linux.dev/include/asm-mips/irq.h 2005-11-10 01:12:43.950955750 +0100
+@@ -14,7 +14,20 @@
+ #include <linux/config.h>
+ #include <linux/linkage.h>
+
++#ifdef CONFIG_AR7
++/* MIPS has 8 irqs
++ * AR7 has 40 primary and 32 secondary irqs
++ * vlynq0 has 32 irqs
++ * vlynq1 has 32 irqs
++ */
++#ifdef CONFIG_AR7_VLYNQ
++#define NR_IRQS (80 + 32 * CONFIG_AR7_VLYNQ_PORTS)
++#else
++#define NR_IRQS 80
++#endif
++#else
+ #define NR_IRQS 128 /* Largest number of ints of all machines. */
++#endif
+
+ #ifdef CONFIG_I8259
+ static inline int irq_cannonicalize(int irq)
+diff -urN linux.old/include/asm-mips/mips-boards/prom.h linux.dev/include/asm-mips/mips-boards/prom.h
+--- linux.old/include/asm-mips/mips-boards/prom.h 2001-09-09 19:43:02.000000000 +0200
++++ linux.dev/include/asm-mips/mips-boards/prom.h 2005-11-10 01:14:16.436735750 +0100
+@@ -33,7 +33,7 @@
+ extern void prom_init_cmdline(void);
+ extern void prom_meminit(void);
+ extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
+-extern void prom_free_prom_memory (void);
++extern unsigned long prom_free_prom_memory (void);
+ extern void mips_display_message(const char *str);
+ extern void mips_display_word(unsigned int num);
+ extern int get_ethernet_addr(char *ethernet_addr);
+diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
+--- linux.old/include/asm-mips/page.h 2004-02-18 14:36:32.000000000 +0100
++++ linux.dev/include/asm-mips/page.h 2005-11-10 01:14:16.436735750 +0100
+@@ -12,6 +12,7 @@
+
+ #include <linux/config.h>
+ #include <asm/break.h>
++#include <asm/addrspace.h>
+
+ #ifdef __KERNEL__
+
+@@ -129,7 +130,7 @@
+
+ #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
+ #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
+-#define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
++#define virt_to_page(kaddr) (mem_map + ((__pa(kaddr)-PHYS_OFFSET) >> PAGE_SHIFT))
+ #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
+
+ #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
+--- linux.old/include/asm-mips/pgtable-32.h 2004-02-18 14:36:32.000000000 +0100
++++ linux.dev/include/asm-mips/pgtable-32.h 2005-11-10 01:14:16.436735750 +0100
+@@ -108,7 +108,7 @@
+ * and a page entry and page directory to the page they refer to.
+ */
+
+-#ifdef CONFIG_CPU_VR41XX
++#if defined(CONFIG_CPU_VR41XX)
+ #define mk_pte(page, pgprot) \
+ ({ \
+ pte_t __pte; \
+@@ -123,13 +123,14 @@
+ ({ \
+ pte_t __pte; \
+ \
+- pte_val(__pte) = ((phys_t)(page - mem_map) << PAGE_SHIFT) | \
+- pgprot_val(pgprot); \
++ pte_val(__pte) = (((phys_t)(page - mem_map) << PAGE_SHIFT) + \
++ PHYS_OFFSET) | pgprot_val(pgprot); \
+ \
+ __pte; \
+ })
+ #endif
+
++
+ static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
+ {
+ #ifdef CONFIG_CPU_VR41XX
+@@ -175,12 +176,12 @@
+ set_pte(ptep, __pte(0));
+ }
+
+-#ifdef CONFIG_CPU_VR41XX
++#if defined(CONFIG_CPU_VR41XX)
+ #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
+ #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
+ #else
+-#define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> PAGE_SHIFT))))
+-#define __mk_pte(page_nr,pgprot) __pte(((page_nr) << PAGE_SHIFT) | pgprot_val(pgprot))
++#define pte_page(x) (mem_map+((unsigned long)((((x).pte_low-PHYS_OFFSET) >> PAGE_SHIFT))))
++#define __mk_pte(page_nr,pgprot) __pte((((page_nr) << PAGE_SHIFT)+PHYS_OFFSET)|pgprot_val(pgprot))
+ #endif
+
+ #endif
+diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
+--- linux.old/include/asm-mips/serial.h 2005-01-19 15:10:12.000000000 +0100
++++ linux.dev/include/asm-mips/serial.h 2005-11-10 01:14:16.436735750 +0100
+@@ -65,6 +65,16 @@
+
+ #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
+
++#ifdef CONFIG_AR7
++#include <asm/ar7/ar7.h>
++#include <asm/ar7/avalanche_intc.h>
++#define AR7_SERIAL_PORT_DEFNS \
++ { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
++ { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
++#else
++#define AR7_SERIAL_PORT_DEFNS
++#endif
++
+ #ifdef CONFIG_MIPS_JAZZ
+ #define _JAZZ_SERIAL_INIT(int, base) \
+ { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
+@@ -468,6 +478,7 @@
+ #endif
+
+ #define SERIAL_PORT_DFNS \
++ AR7_SERIAL_PORT_DEFNS \
+ ATLAS_SERIAL_PORT_DEFNS \
+ AU1000_SERIAL_PORT_DEFNS \
+ COBALT_SERIAL_PORT_DEFNS \
diff --git a/openwrt/target/linux/ar7-2.4/patches/001-flash_map.patch b/openwrt/target/linux/ar7-2.4/patches/001-flash_map.patch
new file mode 100644
index 0000000000..83bc103bef
--- /dev/null
+++ b/openwrt/target/linux/ar7-2.4/patches/001-flash_map.patch
@@ -0,0 +1,307 @@
+diff -urN linux.old/drivers/mtd/maps/ar7-flash.c linux.dev/drivers/mtd/maps/ar7-flash.c
+--- linux.old/drivers/mtd/maps/ar7-flash.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/mtd/maps/ar7-flash.c 2005-07-22 04:35:26.624453992 +0200
+@@ -0,0 +1,267 @@
++/*
++ * $Id$
++ *
++ * Normal mappings of chips in physical memory
++ */
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <asm/io.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/map.h>
++#include <linux/config.h>
++#include <linux/mtd/partitions.h>
++#include <linux/squashfs_fs.h>
++
++#define WINDOW_ADDR CONFIG_MTD_AR7_START
++#define WINDOW_SIZE CONFIG_MTD_AR7_LEN
++#define BUSWIDTH CONFIG_MTD_AR7_BUSWIDTH
++
++#include <asm/mips-boards/prom.h>
++extern char *prom_getenv(char *name);
++
++static int create_mtd_partitions(void);
++static void __exit ar7_mtd_cleanup(void);
++
++#define MAX_NUM_PARTITIONS 5
++static struct mtd_partition ar7_partinfo[MAX_NUM_PARTITIONS];
++
++static struct mtd_info *ar7_mtd_info;
++
++__u8 ar7_read8(struct map_info *map, unsigned long ofs)
++{
++ return __raw_readb(map->map_priv_1 + ofs);
++}
++
++__u16 ar7_read16(struct map_info *map, unsigned long ofs)
++{
++ return __raw_readw(map->map_priv_1 + ofs);
++}
++
++__u32 ar7_read32(struct map_info *map, unsigned long ofs)
++{
++ return __raw_readl(map->map_priv_1 + ofs);
++}
++
++void ar7_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
++{
++ memcpy_fromio(to, map->map_priv_1 + from, len);
++}
++
++void ar7_write8(struct map_info *map, __u8 d, unsigned long adr)
++{
++ __raw_writeb(d, map->map_priv_1 + adr);
++ mb();
++}
++
++void ar7_write16(struct map_info *map, __u16 d, unsigned long adr)
++{
++ __raw_writew(d, map->map_priv_1 + adr);
++ mb();
++}
++
++void ar7_write32(struct map_info *map, __u32 d, unsigned long adr)
++{
++ __raw_writel(d, map->map_priv_1 + adr);
++ mb();
++}
++
++void ar7_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
++{
++ memcpy_toio(map->map_priv_1 + to, from, len);
++}
++
++struct map_info ar7_map = {
++ name: "Physically mapped flash",
++ size: WINDOW_SIZE,
++ buswidth: BUSWIDTH,
++ read8: ar7_read8,
++ read16: ar7_read16,
++ read32: ar7_read32,
++ copy_from: ar7_copy_from,
++ write8: ar7_write8,
++ write16: ar7_write16,
++ write32: ar7_write32,
++ copy_to: ar7_copy_to
++};
++
++int __init ar7_mtd_init(void)
++{
++ int partitions;
++
++ printk(KERN_NOTICE "ar7 flash device: 0x%lx at 0x%lx.\n", (unsigned long)WINDOW_SIZE, (unsigned long)WINDOW_ADDR);
++ ar7_map.map_priv_1 = (unsigned long)ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);
++
++ if (!ar7_map.map_priv_1) {
++ printk("Failed to ioremap\n");
++ return -EIO;
++ }
++
++ ar7_mtd_info = do_map_probe("cfi_probe", &ar7_map);
++ if (!ar7_mtd_info)
++ {
++ ar7_mtd_cleanup();
++ return -ENXIO;
++ }
++
++ ar7_mtd_info->module = THIS_MODULE;
++
++ if (!(partitions = create_mtd_partitions()))
++ add_mtd_device(ar7_mtd_info);
++ else
++ add_mtd_partitions(ar7_mtd_info, ar7_partinfo, partitions);
++
++ return 0;
++}
++
++static char *strdup(char *str)
++{
++ int n = strlen(str)+1;
++ char *s = kmalloc(n, GFP_KERNEL);
++ if (!s) return NULL;
++ return strcpy(s, str);
++}
++
++
++static int create_mtd_partitions(void)
++{
++ unsigned int offset;
++ unsigned int size;
++ unsigned int found = 0;
++ unsigned int p = 0;
++ unsigned char *flash_base;
++ unsigned char *flash_end;
++ char *env_ptr;
++ char *base_ptr;
++ char *end_ptr;
++ unsigned int adam2_size = 0x20000;
++ unsigned int config_offset = WINDOW_SIZE;
++ unsigned int rootfs_start = 0xe0000;
++
++ printk("Parsing ADAM2 partition map...\n");
++
++ do {
++ char env_name[20];
++
++ /* get base and end addresses of flash file system from environment */
++ sprintf(env_name, "mtd%1u", p);
++ printk("Looking for mtd device :%s:\n", env_name);
++
++ env_ptr = prom_getenv(env_name);
++ if(env_ptr == NULL) {
++ /* No more partitions to find */
++ break;
++ }
++
++ /* Extract the start and stop addresses of the partition */
++ base_ptr = strtok(env_ptr, ",");
++ end_ptr = strtok(NULL, ",");
++ if ((base_ptr == NULL) || (end_ptr == NULL)) {
++ printk("ADAM2 partition error: Invalid %s start,end.\n", env_name);
++ break;
++ }
++
++ flash_base = (unsigned char*) simple_strtol(base_ptr, NULL, 0);
++ flash_end = (unsigned char*) simple_strtol(end_ptr, NULL, 0);
++ if((!flash_base) || (!flash_end)) {
++ printk("ADAM2 partition error: Invalid %s start,end.\n", env_name);
++ break;
++ }
++
++ offset = virt_to_bus(flash_base) - WINDOW_ADDR;
++ size = flash_end - flash_base;
++ printk("Found a %s image (0x%x), with size (0x%x).\n",env_name, offset, size);
++
++
++ if (offset == 0) {
++ printk("Assuming adam2 size of 0x%x\n", size);
++ adam2_size = size; // boot loader
++ } else if (offset > 0x120000) {
++ if (config_offset > offset)
++ config_offset = offset; // reserved at the end of the flash chip
++ } else if (offset > 0x30000) {
++ printk("Assuming default rootfs offset of 0x%x\n", offset);
++ rootfs_start = offset; // probably root fs
++ }
++
++ p++;
++ } while (p < MAX_NUM_PARTITIONS);
++
++ p = 0;
++
++ ar7_partinfo[p].name = strdup("adam2");
++ ar7_partinfo[p].offset = 0;
++ ar7_partinfo[p].size = adam2_size;
++ ar7_partinfo[p++].mask_flags = 0;
++
++ ar7_partinfo[p].name = strdup("linux");
++ ar7_partinfo[p].offset = adam2_size;
++ ar7_partinfo[p].size = config_offset - adam2_size;
++ ar7_partinfo[p++].mask_flags = 0;
++
++ if (ar7_read32(&ar7_map, adam2_size) == 0xfeedfa42) {
++ rootfs_start = ar7_read32(&ar7_map, adam2_size + 4) + adam2_size + 28;
++ printk("Setting new rootfs offset to %08x\n", rootfs_start);
++ }
++
++ ar7_partinfo[p].name = strdup("rootfs");
++ ar7_partinfo[p].offset = rootfs_start;
++ ar7_partinfo[p].size = config_offset - rootfs_start;
++
++ ar7_partinfo[p++].mask_flags = 0;
++
++ ar7_partinfo[p].name = strdup("config");
++ ar7_partinfo[p].offset = config_offset;
++ ar7_partinfo[p].size = WINDOW_SIZE - config_offset;
++ ar7_partinfo[p++].mask_flags = 0;
++
++ if (ar7_read32(&ar7_map, rootfs_start) == SQUASHFS_MAGIC) {
++ int newsize, newoffset;
++ squashfs_super_block sb;
++
++ ar7_copy_from(&ar7_map, &sb, rootfs_start, sizeof(sb));
++ printk("Squashfs detected (size = 0x%08x)\n", sb.bytes_used);
++
++ newoffset = rootfs_start + sb.bytes_used;
++
++ if ((newoffset % ar7_mtd_info->erasesize) > 0)
++ newoffset += ar7_mtd_info->erasesize - (newoffset % ar7_mtd_info->erasesize);
++
++ ar7_partinfo[p - 2].size = newoffset - rootfs_start;
++
++ ar7_partinfo[p].name = strdup("OpenWrt");
++ ar7_partinfo[p].offset = newoffset;
++ ar7_partinfo[p].size = config_offset - newoffset;
++ ar7_partinfo[p++].mask_flags = 0;
++ } else {
++ printk("Unknown filesystem. Moving rootfs partition to next erase block");
++ if ((rootfs_start % ar7_mtd_info->erasesize) > 0) {
++ ar7_partinfo[p - 2].offset += ar7_mtd_info->erasesize - (rootfs_start % ar7_mtd_info->erasesize);
++ ar7_partinfo[p - 2].size -= ar7_mtd_info->erasesize - (rootfs_start % ar7_mtd_info->erasesize);
++ }
++ }
++
++ return p;
++}
++
++static void __exit ar7_mtd_cleanup(void)
++{
++ if (ar7_mtd_info) {
++ del_mtd_partitions(ar7_mtd_info);
++ del_mtd_device(ar7_mtd_info);
++ map_destroy(ar7_mtd_info);
++ }
++
++ if (ar7_map.map_priv_1) {
++ iounmap((void *)ar7_map.map_priv_1);
++ ar7_map.map_priv_1 = 0;
++ }
++}
++
++module_init(ar7_mtd_init);
++module_exit(ar7_mtd_cleanup);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Felix Fietkau");
++MODULE_DESCRIPTION("AR7 CFI map driver");
+diff -urN linux.old/drivers/mtd/maps/Config.in linux.dev/drivers/mtd/maps/Config.in
+--- linux.old/drivers/mtd/maps/Config.in 2005-07-21 05:36:32.414242296 +0200
++++ linux.dev/drivers/mtd/maps/Config.in 2005-07-21 06:29:04.067118232 +0200
+@@ -48,6 +48,21 @@
+ fi
+
+ if [ "$CONFIG_MIPS" = "y" ]; then
++ if [ "$CONFIG_AR7" = "y" ]; then
++ dep_tristate ' Flash chip mapping on Texas Instruments AR7' CONFIG_MTD_AR7 $CONFIG_MTD_CFI $CONFIG_MTD_PARTITIONS
++ dep_bool ' Use defaults for Texas Instruments AR7' CONFIG_MTD_AR7_DEFAULTS $CONFIG_MTD_AR7
++ if [ "$CONFIG_MTD_AR7" = "y" -o "$CONFIG_MTD_AR7" = "m" ]; then
++ if [ "$CONFIG_MTD_AR7_DEFAULTS" = "y" ]; then
++ define_hex CONFIG_MTD_AR7_START 0x10000000
++ define_hex CONFIG_MTD_AR7_LEN 0x400000
++ define_int CONFIG_MTD_AR7_BUSWIDTH 2
++ else
++ hex ' Physical start address of flash mapping' CONFIG_MTD_AR7_START 0x10000000
++ hex ' Physical length of flash mapping' CONFIG_MTD_AR7_LEN 0x400000
++ int ' Bus width in octets' CONFIG_MTD_AR7_BUSWIDTH 2
++ fi
++ fi
++ fi
+ dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
+ dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
+ dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
+diff -urN linux.old/drivers/mtd/maps/Makefile linux.dev/drivers/mtd/maps/Makefile
+--- linux.old/drivers/mtd/maps/Makefile 2005-07-21 05:36:32.414242296 +0200
++++ linux.dev/drivers/mtd/maps/Makefile 2005-07-21 06:56:33.265401984 +0200
+@@ -10,6 +10,7 @@
+ endif
+
+ # Chip mappings
++obj-$(CONFIG_MTD_AR7) += ar7-flash.o
+ obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
+ obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
+ obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
diff --git a/openwrt/target/linux/ar7-2.4/patches/002-led_driver.patch b/openwrt/target/linux/ar7-2.4/patches/002-led_driver.patch
new file mode 100644
index 0000000000..81fe153cc3
--- /dev/null
+++ b/openwrt/target/linux/ar7-2.4/patches/002-led_driver.patch
@@ -0,0 +1,1915 @@
+diff -urN linux.dev/drivers/char/Config.in linux.dev2/drivers/char/Config.in
+--- linux.dev/drivers/char/Config.in 2005-10-21 17:02:20.199991500 +0200
++++ linux.dev2/drivers/char/Config.in 2005-10-21 18:03:44.541778750 +0200
+@@ -133,6 +133,10 @@
+ fi
+ fi
+ fi
++if [ "$CONFIG_AR7" = "y" ]; then
++ bool 'Enable LED support' CONFIG_AR7_LED
++fi
++
+ if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
+ tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
+ fi
+diff -urN linux.dev/drivers/char/Makefile linux.dev2/drivers/char/Makefile
+--- linux.dev/drivers/char/Makefile 2005-10-21 17:02:20.199991500 +0200
++++ linux.dev2/drivers/char/Makefile 2005-10-21 18:03:44.541778750 +0200
+@@ -190,6 +190,12 @@
+ obj-$(CONFIG_PCI) += keyboard.o $(KEYMAP)
+ endif
+
++#
++# Texas Intruments LED driver
++#
++obj-$(CONFIG_AR7_LED) += avalanche_led/avalanche_led.o
++subdir-$(CONFIG_AR7_LED) += avalanche_led
++
+ obj-$(CONFIG_HIL) += hp_keyb.o
+ obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
+ obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
+diff -urN linux.dev/drivers/char/avalanche_led/Makefile linux.dev2/drivers/char/avalanche_led/Makefile
+--- linux.dev/drivers/char/avalanche_led/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev2/drivers/char/avalanche_led/Makefile 2005-10-21 18:03:44.513777000 +0200
+@@ -0,0 +1,23 @@
++# File: drivers/char/avalanche_led/Makefile
++#
++# Makefile for the Linux LED device driver.
++#
++
++
++O_TARGET := avalanche_led.o
++obj-m := avalanche_led.o
++list-multi := avalanche_led.o
++
++EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7
++
++export-objs := ledmod.o leds.o
++
++avalanche_led-objs := ledmod.o gpio.o uartled.o leds.o
++
++include $(TOPDIR)/Rules.make
++
++avalanche_led.o: $(avalanche_led-objs)
++ $(LD) -r -o $@ $(avalanche_led-objs)
++
++clean:
++ rm -f core *.o *.a *.s
+diff -urN linux.dev/drivers/char/avalanche_led/gpio.c linux.dev2/drivers/char/avalanche_led/gpio.c
+--- linux.dev/drivers/char/avalanche_led/gpio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev2/drivers/char/avalanche_led/gpio.c 2005-10-21 18:03:44.513777000 +0200
+@@ -0,0 +1,382 @@
++#include <linux/kernel.h>
++#include <asm/uaccess.h>
++#include <linux/spinlock.h>
++#include <linux/proc_fs.h>
++#include <linux/fs.h>
++#include <linux/timer.h>
++#include <linux/module.h>
++
++#include <asm/ar7/tnetd73xx_err.h>
++#include <asm/ar7/tnetd73xx_misc.h>
++#include <asm/ar7/ledapp.h>
++
++#define TRUE 1
++#define FALSE 0
++
++#if defined CONFIG_AR7WRD || defined CONFIG_AR7RD
++
++#define AR7_RESET_FILE "led_mod/ar7reset"
++#define AR7_VERSION_FILE "led_mod/hardware_version"
++#define AR7_RESET_GPIO 11
++#define RESET_POLL_TIME 1
++#define RESET_HOLD_TIME 4
++#define NO_OF_LEDS
++
++static struct proc_dir_entry *reset_file;
++static int res_state = 0;
++static int count;
++static struct timer_list *pTimer = NULL;
++static ssize_t proc_read_reset_fops(struct file *filp,
++ char *buf,size_t count , loff_t *offp);
++
++static ssize_t proc_read_hwversion_fops(struct file *filp,
++ char *buf,size_t count , loff_t *offp);
++
++struct file_operations reset_fops = {
++ read: proc_read_reset_fops
++ };
++struct file_operations hardware_version_fops = {
++ read: proc_read_hwversion_fops
++ };
++#endif
++
++static spinlock_t device_lock;
++led_reg_t temp[15];
++
++static void gpio_led_on( unsigned long param )
++{
++ unsigned int flags;
++
++ spin_lock_irqsave(&device_lock, flags);
++
++ tnetd73xx_gpio_out(param,FALSE);
++ spin_unlock_irqrestore(&device_lock, flags);
++}
++
++static void gpio_led_off ( unsigned long param )
++{
++ unsigned int flags = 0x00;
++
++ spin_lock_irqsave(&device_lock, flags);
++
++ tnetd73xx_gpio_out(param,TRUE);
++ spin_unlock_irqrestore(&device_lock, flags);
++}
++
++static void gpio_led_init( unsigned long param)
++{
++ tnetd73xx_gpio_ctrl(param,GPIO_PIN,GPIO_OUTPUT_PIN);
++}
++
++static void board_gpio_reset(void)
++{
++ /* Initialize the link mask */
++ device_lock = SPIN_LOCK_UNLOCKED;
++ return;
++}
++
++#if defined CONFIG_AR7WRD || defined CONFIG_AR7RD
++
++static ssize_t proc_read_hwversion_fops(struct file *filp, char *buf,
++ size_t count, loff_t *offp)
++{
++ char line[8];
++ int len = 0;
++ if( *offp != 0 )
++ return 0;
++
++ len = sprintf(line, "%d%d.%d%d%d%d\n", tnetd73xx_gpio_in(20),
++ tnetd73xx_gpio_in(21), tnetd73xx_gpio_in(22),
++ tnetd73xx_gpio_in(23), tnetd73xx_gpio_in(24),
++ tnetd73xx_gpio_in(25));
++
++ copy_to_user(buf, line, len);
++ *offp = len;
++ return len;
++}
++
++static ssize_t proc_read_reset_fops(struct file *filp,
++ char *buf,size_t count , loff_t *offp)
++{
++ char * pdata = NULL;
++ char line[3];
++ int len = 0;
++ if( *offp != 0 )
++ return 0;
++
++ pdata = buf;
++ len = sprintf(line,"%d\n", res_state );
++//wwzh
++// res_state = 0;
++ copy_to_user(buf,line,len );
++ *offp = len;
++ return len;
++}
++
++static void reset_timer_func(unsigned long data)
++{
++//wwzh
++#if 0
++ count = (tnetd73xx_gpio_in(AR7_RESET_GPIO) == 0) ? count + 1: 0;
++ if( count >= RESET_HOLD_TIME/RESET_POLL_TIME )
++#endif
++ if (tnetd73xx_gpio_in(AR7_RESET_GPIO) == 0)
++ res_state = 1;
++ else
++ res_state = 0;
++ pTimer->expires = jiffies + HZ*RESET_POLL_TIME;
++ add_timer (pTimer);
++ return;
++}
++
++static void hardware_version_init(void)
++{
++ static struct proc_dir_entry *hardware_version_file;
++ hardware_version_file = create_proc_entry(AR7_VERSION_FILE, 0777, NULL);
++ if(hardware_version_file == NULL)
++ return;
++
++ hardware_version_file->owner = THIS_MODULE;
++ hardware_version_file->proc_fops = &hardware_version_fops;
++
++ tnetd73xx_gpio_ctrl(20,GPIO_PIN,GPIO_INPUT_PIN);
++ tnetd73xx_gpio_ctrl(21,GPIO_PIN,GPIO_INPUT_PIN);
++ tnetd73xx_gpio_ctrl(22,GPIO_PIN,GPIO_INPUT_PIN);
++ tnetd73xx_gpio_ctrl(23,GPIO_PIN,GPIO_INPUT_PIN);
++ tnetd73xx_gpio_ctrl(24,GPIO_PIN,GPIO_INPUT_PIN);
++ tnetd73xx_gpio_ctrl(25,GPIO_PIN,GPIO_INPUT_PIN);
++
++ return;
++}
++
++static void reset_init(void)
++{
++ /* Create board reset proc file */
++ reset_file = create_proc_entry( AR7_RESET_FILE, 0777, NULL);
++ if( reset_file == NULL)
++ goto reset_file;
++ reset_file->owner = THIS_MODULE;
++ reset_file->proc_fops = &reset_fops;
++
++ /* Initialise GPIO 11 for input */
++ tnetd73xx_gpio_ctrl(AR7_RESET_GPIO,GPIO_PIN,GPIO_INPUT_PIN);
++
++ /* Create a timer which fires every seconds */
++ pTimer = kmalloc(sizeof(struct timer_list),GFP_KERNEL);
++ init_timer( pTimer );
++ pTimer->function = reset_timer_func;
++ pTimer->data = 0;
++ /* Start the timer */
++ reset_timer_func(0);
++ return ;
++
++ reset_file:
++ remove_proc_entry("AR7_RESET_FILE",NULL);
++ return;
++}
++#endif
++/*************wwzh****************/
++#if 1
++extern unsigned int sys_mod_state;
++extern unsigned int wan_mod_state;
++extern unsigned int wlan_mod_state;
++void sys_led_init(void)
++{
++ tnetd73xx_gpio_ctrl(4, GPIO_PIN, GPIO_OUTPUT_PIN);
++ tnetd73xx_gpio_ctrl(5, GPIO_PIN, GPIO_OUTPUT_PIN);
++ tnetd73xx_gpio_ctrl(8, GPIO_PIN, GPIO_OUTPUT_PIN);
++
++ tnetd73xx_gpio_out(4, FALSE);
++ tnetd73xx_gpio_out(5, TRUE);
++ tnetd73xx_gpio_out(8, TRUE);
++
++
++ sys_mod_state = 2;
++
++}
++void wan_led_init(void)
++{
++
++ tnetd73xx_gpio_ctrl(2, GPIO_PIN, GPIO_OUTPUT_PIN);
++ tnetd73xx_gpio_ctrl(3, GPIO_PIN, GPIO_OUTPUT_PIN);
++
++ tnetd73xx_gpio_out(2, FALSE);
++ tnetd73xx_gpio_out(3, FALSE);
++
++ wan_mod_state = 1;
++}
++//wwzh wireless
++#if 0
++void wlan_led_init(void)
++{
++ //unsigned long i = 0;
++ tnetd73xx_gpio_ctrl(12, GPIO_PIN, GPIO_OUTPUT_PIN);
++ tnetd73xx_gpio_ctrl(13, GPIO_PIN, GPIO_OUTPUT_PIN);
++
++ tnetd73xx_gpio_out(12, FALSE);
++ tnetd73xx_gpio_out(13, TRUE);
++ //for (i = 0; i < 0x20000000; i++);
++ wlan_mod_state = 1;
++}
++#endif
++
++#endif
++/*************end ****************/
++
++void board_gpio_init(void)
++{
++
++ board_gpio_reset();
++/**************wwzh*************/
++ sys_led_init();
++ wan_led_init();
++
++ //junzhao 2004.3.15
++ hardware_version_init();
++
++ //wlan_led_init();
++
++ /* Register Device MAX_LED_ID + 1 for reset to factory default */
++ temp[0].param = 0;
++ temp[0].init = reset_init;
++ temp[0].onfunc = 0;
++ temp[0].offfunc = 0;
++ register_led_drv( MAX_LED_ID + 1 , &temp[0]);
++//wwzh for wireless led
++#if 1
++ /* Register led 12 WiFi 6 */
++ temp[1].param = 6;
++ temp[1].init = gpio_led_init;
++ temp[1].onfunc = gpio_led_on;
++ temp[1].offfunc = gpio_led_off;
++ register_led_drv( 12 , &temp[1]);
++
++#endif
++
++#if 0
++/**************end ************/
++#if defined(CONFIG_AR5D01)
++ /* Register led 1 GPIO0 */
++ temp[0].param = GPIO_0;
++ temp[0].init = gpio_led_init;
++ temp[0].onfunc = gpio_led_on;
++ temp[0].offfunc = gpio_led_off;
++ register_led_drv( 1 , &temp[0]);
++
++ /* Register led 2 EINT1 */
++ temp[1].param = EINT_1;
++ temp[1].init = gpio_led_init;
++ temp[1].onfunc = gpio_led_on;
++ temp[1].offfunc = gpio_led_off;
++ register_led_drv( 2 , &temp[1]);
++
++ /* Register led 5 EINT1 */
++ temp[2].param = GPIO_1;
++ temp[2].init = gpio_led_init;
++ temp[2].onfunc = gpio_led_on;
++ temp[2].offfunc = gpio_led_off;
++ register_led_drv( 5 , &temp[2]);
++#endif
++
++#if defined(CONFIG_AR5W01)
++ /* Register led 5 GPIO_1 */
++ temp[0].param = GPIO_1;
++ temp[0].init = gpio_led_init;
++ temp[0].onfunc = gpio_led_on;
++ temp[0].offfunc = gpio_led_off;
++ register_led_drv( 5 , &temp[0]);
++
++ /* Register led 7 GPIO_0 */
++ temp[1].param = GPIO_0;
++ temp[1].init = gpio_led_init;
++ temp[1].onfunc = gpio_led_on;
++ temp[1].offfunc = gpio_led_off;
++ register_led_drv( 7 , &temp[1]);
++#endif
++
++//wwzh #if defined(CONFIG_AR7RD)
++#if defined CONFIG_AR7WRD || defined CONFIG_AR7RD
++ /* Register led 5 Green PPPOE GPIO 13 */
++ temp[0].param = 13;
++ temp[0].init = gpio_led_init;
++ temp[0].onfunc = gpio_led_on;
++ temp[0].offfunc = gpio_led_off;
++ register_led_drv( 5 , &temp[0]);
++
++ /* Register led 7 Green USB GPIO 12 */
++ temp[1].param = 12;
++ temp[1].init = gpio_led_init;
++ temp[1].onfunc = gpio_led_on;
++ temp[1].offfunc = gpio_led_off;
++ register_led_drv( 7 , &temp[1]);
++
++ /* Register Device MAX_LED_ID + 1 for reset to factory default */
++ temp[2].param = 0;
++ temp[2].init = reset_init;
++ temp[2].onfunc = 0;
++ temp[2].offfunc = 0;
++ register_led_drv( MAX_LED_ID + 1 , &temp[2]);
++
++ /* Register led 8 RED DSL GPIO 10 */
++ temp[3].param = 10;
++ temp[3].init = gpio_led_init;
++ temp[3].onfunc = gpio_led_on;
++ temp[3].offfunc = gpio_led_off;
++ register_led_drv( 8 , &temp[3]);
++
++ /* Register led 9 RED PPPoE down GPIO 9 */
++ temp[4].param = 9;
++ temp[4].init = gpio_led_init;
++ temp[4].onfunc = gpio_led_on;
++ temp[4].offfunc = gpio_led_off;
++ register_led_drv( 9 , &temp[4]);
++
++ /* Register led 10 DSL down GPIO 8 */
++ temp[5].param = 8;
++ temp[5].init = gpio_led_init;
++ temp[5].onfunc = gpio_led_on;
++ temp[5].offfunc = gpio_led_off;
++ register_led_drv( 10 , &temp[5]);
++
++ /* Register led 11 Power GPIO 7 */
++ temp[6].param = 7;
++ temp[6].init = gpio_led_init;
++ temp[6].onfunc = gpio_led_on;
++ temp[6].offfunc = gpio_led_off;
++ register_led_drv( 11 , &temp[6]);
++
++ /* Register led 12 WiFi 6 */
++ temp[7].param = 6;
++ temp[7].init = gpio_led_init;
++ temp[7].onfunc = gpio_led_on;
++ temp[7].offfunc = gpio_led_off;
++ register_led_drv( 12 , &temp[7]);
++
++ /* Register led 13 ELINK(AA1313) GPIO 15 */
++ temp[8].param = 15;
++ temp[8].init = gpio_led_init;
++ temp[8].onfunc = gpio_led_on;
++ temp[8].offfunc = gpio_led_off;
++ register_led_drv( 13 , &temp[8]);
++
++ /* Register led 14 EACT(Y13) GPIO 16 */
++ temp[9].param = 16;
++ temp[9].init = gpio_led_init;
++ temp[9].onfunc = gpio_led_on;
++ temp[9].offfunc = gpio_led_off;
++ register_led_drv( 14 , &temp[9]);
++
++#endif
++/**************wwzh**************/
++#endif
++/**************end **************/
++ return;
++}
++
++
++
++
++
++
++
++
+diff -urN linux.dev/drivers/char/avalanche_led/ledmod.c linux.dev2/drivers/char/avalanche_led/ledmod.c
+--- linux.dev/drivers/char/avalanche_led/ledmod.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev2/drivers/char/avalanche_led/ledmod.c 2005-10-21 18:03:44.513777000 +0200
+@@ -0,0 +1,1116 @@
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/proc_fs.h>
++#include <asm/uaccess.h>
++#include <linux/fs.h>
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/spinlock.h>
++#include <asm/ar7/avalanche_regs.h>
++#include <asm/ar7/ledapp.h>
++#include <linux/module.h>
++
++#define LED_ON 1
++#define LED_OFF 2
++#define LED_BLINK 3
++#define LED_FLASH 4
++
++#define LED_BLINK_UP 5
++#define LED_BLINK_DOWN 6
++
++extern void avalanche_leds_init(void);
++
++/***********wwzh**************/
++unsigned int sys_mod_state;
++unsigned int wan_mod_state;
++unsigned int wlan_mod_state;
++
++struct timer_list *pWanTimer = NULL;
++struct timer_list *pWlanTimer = NULL;
++/***********end **************/
++
++typedef struct state_entry{
++ unsigned char mode;
++ unsigned char led;
++ void (*handler)(struct state_entry *pState);
++ unsigned long param;
++}state_entry_t;
++
++typedef struct mod_entry{
++ state_entry_t *states[MAX_STATE_ID];
++}mod_entry_t;
++
++static mod_entry_t *modArr[MAX_MOD_ID];
++static struct proc_dir_entry *led_proc_dir,*led_file;
++
++/* index of the array is the led number HARDWARE SPECIFIC*/
++typedef struct led_data{
++ led_reg_t *led;
++ int state;
++ struct timer_list *pTimer;
++ unsigned char timer_running;
++ unsigned long param;
++}led_data_t;
++
++led_data_t led_arr[MAX_LED_ID + 1];
++/*!!! The last device is actually being used for ar7 reset to factory default */
++
++
++static spinlock_t config_lock;
++
++static void board_led_link_up( state_entry_t *pState );
++static void board_led_link_down( state_entry_t *pState );
++static void board_led_activity_on( state_entry_t *pState );
++static void board_led_activity_off( state_entry_t *pState );
++static void led_timer_func(unsigned long data);
++
++extern void board_gpio_init(void);
++extern void uart_led_init(void);
++
++static ssize_t proc_read_led_fops(struct file *filp,
++ char *buf,size_t count , loff_t *offp);
++static ssize_t proc_write_led_fops(struct file *filp,const char *buffer,
++ size_t count , loff_t *offp);
++static int config_led( unsigned long y);
++
++struct file_operations led_fops = {
++ read: proc_read_led_fops,
++ write: proc_write_led_fops,
++ };
++
++static int led_atoi( char *name)
++{
++ int val = 0;
++ for(;;name++)
++ {
++ switch(*name)
++ {
++ case '0'...'9':
++ val = val*10+(*name - '0');
++ break;
++ default:
++ return val;
++ }
++ }
++}
++
++static int free_memory(void)
++{
++ int i, j;
++
++ for( i = 0; i < MAX_MOD_ID ; i++)
++ {
++ if( modArr[i] != NULL )
++ {
++ for( j = 0; j < MAX_STATE_ID ; j++ )
++ {
++ if( modArr[i]->states[j] != NULL )
++ kfree( modArr[i]->states[j]);
++ }
++ kfree(modArr[i]);
++ modArr[i] = NULL;
++ }
++ }
++ return 0;
++}
++
++static int led_on( state_entry_t *pState )
++{
++ if( led_arr[pState->led].led == NULL)
++ return -1;
++ led_arr[pState->led].led->onfunc( led_arr[pState->led].led->param);
++ return 0;
++}
++
++static int led_off( state_entry_t *pState )
++{
++ if( led_arr[pState->led].led == NULL)
++ return -1;
++ led_arr[pState->led].led->offfunc( led_arr[pState->led].led->param);
++ return 0;
++}
++
++static void board_led_link_up( state_entry_t *pState )
++{
++ led_arr[pState->led].state = LED_ON;
++ if( led_arr[pState->led].timer_running == 0 )
++ led_on(pState);
++ return;
++}
++
++static void board_led_link_down( state_entry_t *pState )
++{
++ led_arr[pState->led].state = LED_OFF;
++ if( led_arr[pState->led].timer_running == 0 )
++ led_off(pState);
++ return;
++}
++
++static void add_led_timer(state_entry_t *pState)
++{
++ led_arr[pState->led].pTimer->expires = jiffies + HZ*(pState->param)/1000;
++ led_arr[pState->led].param = pState->param;
++ led_arr[pState->led].pTimer->data = pState;
++ add_timer (led_arr[pState->led].pTimer);
++}
++
++static void board_led_activity_on(state_entry_t *pState)
++{
++ if(led_arr[pState->led].timer_running == 0)
++ {
++ led_on(pState);
++ add_led_timer(pState);
++ led_arr[pState->led].timer_running = 1;
++ led_arr[pState->led].state = LED_BLINK_UP;
++ }
++ else if( led_arr[pState->led].timer_running > 0xF0)
++ {
++ led_arr[pState->led].state = LED_BLINK_UP;
++ led_arr[pState->led].pTimer->expires = jiffies + HZ*(pState->param)/1000;
++ led_arr[pState->led].param = pState->param;
++ led_arr[pState->led].pTimer->data = pState;
++ }
++ return;
++}
++
++static void board_led_activity_off(state_entry_t *pState)
++{
++ if(led_arr[pState->led].timer_running == 0)
++ {
++ led_off(pState);
++ add_led_timer(pState);
++ led_arr[pState->led].timer_running = 1;
++ led_arr[pState->led].state = LED_BLINK_UP;
++ }
++ else if( led_arr[pState->led].timer_running > 0xF0)
++ {
++ led_arr[pState->led].state = LED_BLINK_UP;
++ led_arr[pState->led].pTimer->expires = jiffies + HZ*(pState->param)/1000;
++ led_arr[pState->led].param = pState->param;
++ led_arr[pState->led].pTimer->data = pState;
++ }
++ return;
++}
++
++static void board_led_link_flash(state_entry_t *pState)
++{
++ if(led_on(pState))
++ return;
++ if(led_arr[pState->led].timer_running == 0)
++ add_led_timer(pState);
++ else
++ led_arr[pState->led].param = pState->param;
++ led_arr[pState->led].timer_running = 0xFF;
++ led_arr[pState->led].state = LED_FLASH;
++ return;
++}
++
++static void led_timer_func(unsigned long data)
++{
++ state_entry_t *pState = NULL;
++ mod_entry_t *pMod = NULL;
++ unsigned int flags;
++
++ spin_lock_irqsave(&config_lock, flags);
++
++ pState = (state_entry_t *)data;
++
++ if( led_arr[pState->led].state == LED_BLINK_DOWN )
++ {
++ led_arr[pState->led].timer_running = 0;
++ if( pState->mode == 2 )
++ led_arr[pState->led].state = LED_OFF;
++ else
++ led_arr[pState->led].state = LED_ON;
++ }
++ else if( led_arr[pState->led].state == LED_BLINK_UP )
++ {
++ led_arr[pState->led].pTimer->expires = jiffies + HZ*(led_arr[pState->led].param)/1000;
++ led_arr[pState->led].pTimer->data = pState;
++ add_timer (led_arr[pState->led].pTimer);
++ if( pState->mode == 2 )
++ {
++ led_off(pState);
++ led_arr[pState->led].state = LED_BLINK_DOWN;
++ }
++ else
++ {
++ led_on(pState);
++ led_arr[pState->led].state = LED_BLINK_DOWN;
++ }
++ led_arr[pState->led].timer_running = 1;
++ }
++ else if( led_arr[pState->led].state == LED_FLASH )
++ {
++ led_arr[pState->led].pTimer->expires = jiffies + HZ*(led_arr[pState->led].param)/1000;
++ led_arr[pState->led].pTimer->data = pState;
++ add_timer (led_arr[pState->led].pTimer);
++
++ if( led_arr[pState->led].timer_running == 0xFF )
++ {
++ led_off(pState);
++ led_arr[pState->led].timer_running--;
++ }
++ else
++ {
++ led_on(pState);
++ led_arr[pState->led].timer_running++;
++ }
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
++ }
++ else if(led_arr[pState->led].state == LED_OFF)
++ {
++ led_off(pState);
++ led_arr[pState->led].timer_running = 0;
++ }
++ else if( led_arr[pState->led].state == LED_ON )
++ {
++ led_on(pState);
++ led_arr[pState->led].timer_running = 0;
++ }
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
++}
++/************wwzh*****************/
++#if 0
++/************end *****************/
++static ssize_t proc_read_led_fops(struct file *filp,
++ char *buf,size_t count , loff_t *offp)
++{
++ char * pdata = NULL;
++ int i = 0, j = 0, len = 0, totallen = 0;
++ char line[255];
++
++ if( *offp != 0 )
++ return 0;
++
++ pdata = buf;
++ len += sprintf(line,"LEDS Registered for use are:");
++ for( i = 0; i< MAX_LED_ID; i++)
++ if( led_arr[i].led != NULL )
++ len += sprintf(&line[len]," %d ", i );
++ line[len++] = '\n';
++
++ copy_to_user(pdata, line,len );
++ pdata += len;
++ totallen += len;
++ len = 0;
++ len = sprintf(line,"USER MODULE INFORMATION:\n");
++ copy_to_user(pdata, line,len );
++ pdata += len;
++ totallen += len;
++ len = 0;
++ for( i = 0; i< MAX_MOD_ID; i++)
++ {
++ if( modArr[i] != NULL )
++ {
++ len = sprintf(line," Module ID = %d \n" , i);
++ copy_to_user(pdata, line,len );
++ pdata += len;
++ totallen += len;
++ len = 0;
++ for( j = 0; j < MAX_STATE_ID; j++)
++ {
++ if( modArr[i]->states[j] != NULL)
++ {
++ len = sprintf(line ,
++ " State = %d , Led = %d," , j , modArr[i]->states[j]->led);
++ copy_to_user(pdata, line,len );
++ pdata += len;
++ totallen += len;
++
++ len = 0;
++ switch( modArr[i]->states[j]->mode )
++ {
++ case 1:
++ len = sprintf(line ," Mode = OFF\n");
++ break;
++ case 2:
++ len = sprintf(line ," Mode = BLINK_ON , On Time(ms) = %d\n" ,
++ (unsigned int)modArr[i]->states[j]->param);
++ break;
++ case 3:
++ len = sprintf(line ," Mode = BLINK_OFF , Off Time(ms) = %d\n" ,
++ (unsigned int)modArr[i]->states[j]->param);
++ break;
++ case 4:
++ len = sprintf(line ," Mode = ON \n");
++ break;
++ case 5:
++ len = sprintf(line ," Mode = FLASH , Time Period(ms) = %d\n" ,
++ (unsigned int)modArr[i]->states[j]->param);
++ break;
++ default:
++ break;
++
++ }
++ copy_to_user(pdata, line,len );
++ pdata += len;
++ totallen += len;
++
++ len = 0;
++ }
++ }
++ }
++ }
++ /* Return with configuration information for LEDs */
++ *offp = totallen;
++ return totallen;
++}
++static ssize_t proc_write_led_fops(struct file *filp,const char *buffer,
++ size_t count , loff_t *offp)
++{
++ char *pdata = NULL, *ptemp = NULL;
++ char line[10],temp[10];
++ int i = 0;
++ int mod = 0xFFFF , state = 0xFFFF;
++ int flag = 0;
++
++ /* Check if this write is for configuring stuff */
++ if( *(int *)(buffer) == 0xFFEEDDCC )
++ {
++ printk("<1>proc write:Calling Configuration\n");
++ config_led((unsigned long)(buffer + sizeof(int)) );
++ return count;
++ }
++
++ if( count >= 10)
++ {
++ printk("<1>proc write:Input too long,max length = %d\n",10);
++ return count;
++ }
++ memset( temp, 0x00 , 10);
++ memset( line, 0x00 , 10);
++ copy_from_user(line,buffer,count);
++ line[count] = 0x00;
++ pdata = line;
++ ptemp = temp;
++ while( flag == 0)
++ {
++ if( i > 10 )
++ break;
++ if( ((*pdata) >= '0' ) && ((*pdata) <= '9') )
++ {
++ *ptemp = *pdata ;
++ ptemp++;
++ }
++ else if( (*pdata) == ',' )
++ {
++ *ptemp = 0x00;
++ flag = 1;
++ }
++ pdata++;
++ i++;
++ };
++ if( flag == 1)
++ mod = led_atoi( temp);
++ else
++ return count;
++
++ ptemp = temp;
++ *ptemp = 0x00;
++ flag = 0;
++ while( flag == 0)
++ {
++ if( i > 10 )
++ break;
++ if( ((*pdata) >= '0' ) && ((*pdata) <= '9') )
++ {
++ *ptemp = *pdata ;
++ ptemp++;
++ }
++ else if( (*pdata) == 0x00 )
++ {
++ *ptemp = 0x00;
++ flag = 1;
++ }
++ pdata++;
++ i++;
++ };
++ if( flag == 1)
++ state = led_atoi( temp);
++ else
++ return count;
++ if( (mod == 0xFFFF) || (state == 0xFFFF))
++ return count;
++ else
++ led_operation( mod , state );
++ return count;
++}
++
++/************wwzh*******************/
++#else
++
++#define TRUE 1
++#define FALSE 0
++#define FLICK_TIME (HZ*100/1000)
++static unsigned int wan_txrx_state = 0;
++static unsigned int wlan_txrx_state = 0;
++
++void led_operation( int mod , int state)
++{
++
++ unsigned int flags;
++
++ spin_lock_irqsave(&config_lock, flags);
++
++ if( (mod >= MAX_MOD_ID) || ( state >= MAX_STATE_ID) )
++ {
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
++ }
++ if ( modArr[mod] == NULL )
++ {
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
++ }
++ if( modArr[mod]->states[state] == NULL )
++ {
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
++ }
++ /* Call the function handler */
++ modArr[mod]->states[state]->handler(modArr[mod]->states[state]);
++
++ spin_unlock_irqrestore(&config_lock, flags);
++}
++
++static void wan_led_func(unsigned long data)
++{
++ if (wan_txrx_state == 0)
++ {
++ tnetd73xx_gpio_out(2, TRUE);
++ tnetd73xx_gpio_out(3, FALSE);
++ wan_txrx_state = 1;
++ }
++ else
++ {
++ tnetd73xx_gpio_out(2, FALSE);
++ tnetd73xx_gpio_out(3, FALSE);
++ wan_txrx_state = 0;
++ }
++ pWanTimer->expires = jiffies + FLICK_TIME;
++ add_timer(pWanTimer);
++}
++//wwzh for wireless
++#if 0
++static void wlan_led_func(unsigned long data)
++{
++ if (wlan_txrx_state == 0)
++ {
++ tnetd73xx_gpio_out(12, TRUE);
++ tnetd73xx_gpio_out(13, FALSE);
++ wlan_txrx_state = 1;
++ }
++ else
++ {
++ tnetd73xx_gpio_out(12, FALSE);
++ tnetd73xx_gpio_out(13, FALSE);
++ wlan_txrx_state = 0;
++
++ }
++ pWlanTimer->expires = jiffies + FLICK_TIME;
++ add_timer(pWlanTimer);
++}
++#endif
++
++void led_active(int mod, int state)
++{
++ unsigned int flags = 0;
++
++//printk("mod = %d state = %d\n", mod, state);
++ spin_lock_irqsave(&config_lock, flags);
++ if ((mod >= 5) || (state >= 5))
++ {
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
++ }
++
++ switch (mod)
++ {
++ case 2: /*system led */
++ sys_mod_state = state;
++ switch (state)
++ {
++ case 1:
++ break;
++ case 2: /*sys led flashing green */
++ tnetd73xx_gpio_out(4, FALSE);
++ tnetd73xx_gpio_out(5, TRUE);
++ tnetd73xx_gpio_out(8, TRUE);
++ break;
++ case 3: /*sys led solid green */
++ tnetd73xx_gpio_out(4, TRUE);
++ tnetd73xx_gpio_out(5, TRUE);
++ tnetd73xx_gpio_out(8, TRUE);
++
++ break;
++ case 4: /*sys fail red */
++ tnetd73xx_gpio_out(4, TRUE);
++ tnetd73xx_gpio_out(5, FALSE);
++ tnetd73xx_gpio_out(8, FALSE);
++ break;
++ default:
++ break;
++ }
++ break;
++ case 3: /*wan led */
++ wan_mod_state = state;
++ switch (state)
++ {
++ case 1: /*no wan interface*/
++ if (pWanTimer)
++ {
++ del_timer(pWanTimer);
++ kfree(pWanTimer);
++ pWanTimer = NULL;
++ }
++ tnetd73xx_gpio_out(2, FALSE);
++ tnetd73xx_gpio_out(3, FALSE);
++ break;
++ case 2: /*wan connected */
++ if (pWanTimer)
++ {
++ del_timer(pWanTimer);
++ kfree(pWanTimer);
++ pWanTimer = NULL;
++ }
++ tnetd73xx_gpio_out(2, TRUE);
++ tnetd73xx_gpio_out(3, FALSE);
++ break;
++ case 3: /*rx/tx activity */
++ if (pWanTimer != NULL)
++ break;
++
++ pWanTimer = kmalloc(sizeof(struct timer_list), GFP_KERNEL);
++ init_timer(pWanTimer);
++
++ pWanTimer->function = wan_led_func;
++ pWanTimer->data = 0;
++ pWanTimer->expires = jiffies + FLICK_TIME;
++ tnetd73xx_gpio_out(2, FALSE);
++ tnetd73xx_gpio_out(3, FALSE);
++ wan_txrx_state = 0;
++ add_timer(pWanTimer);
++
++ break;
++ case 4: /*no ipaddress */
++ if (pWanTimer)
++ {
++ del_timer(pWanTimer);
++ kfree(pWanTimer);
++ pWanTimer = NULL;
++ }
++ tnetd73xx_gpio_out(2, FALSE);
++ tnetd73xx_gpio_out(3, TRUE);
++ break;
++ default:
++ if (pWanTimer)
++ {
++ del_timer(pWanTimer);
++ kfree(pWanTimer);
++ pWanTimer = NULL;
++ }
++ break;
++ }
++ break;
++ //wwzh for wireless
++ #if 0
++ case 4: /*wlan led */
++ wlan_mod_state = state;
++ switch (state)
++ {
++ case 1: /* wlan off */
++ if (pWlanTimer)
++ {
++ del_timer(pWlanTimer);
++ kfree(pWlanTimer);
++ pWlanTimer = NULL;
++ }
++ tnetd73xx_gpio_out(12, FALSE);
++ tnetd73xx_gpio_out(13, FALSE);
++ break;
++ case 2: /* wlan ready */
++ if (pWlanTimer)
++ {
++ del_timer(pWlanTimer);
++ kfree(pWlanTimer);
++ pWlanTimer = NULL;
++ }
++ tnetd73xx_gpio_out(12, TRUE);
++ tnetd73xx_gpio_out(13, FALSE);
++ break;
++ case 3: /* wlan rx/tx activity */
++ if (pWlanTimer != NULL)
++ break;
++
++ pWlanTimer = kmalloc(sizeof(struct timer_list), GFP_KERNEL);
++ init_timer(pWlanTimer);
++
++ pWlanTimer->function = wlan_led_func;
++ pWlanTimer->data = 0;
++ pWlanTimer->expires = jiffies + FLICK_TIME;
++ tnetd73xx_gpio_out(12, FALSE);
++ tnetd73xx_gpio_out(13, FALSE);
++ wlan_txrx_state = 0;
++ add_timer(pWlanTimer);
++
++ break;
++ default:
++ if (pWlanTimer)
++ {
++ del_timer(pWlanTimer);
++ kfree(pWlanTimer);
++ pWlanTimer = NULL;
++ }
++
++ break;
++ }
++ break;
++ #endif //for wireless
++ default:
++ break;
++ }
++ spin_unlock_irqrestore(&config_lock, flags);
++}
++static ssize_t proc_read_led_fops(struct file *filp,
++ char *buf,size_t count , loff_t *offp)
++{
++ char *pdata = NULL;
++ int i = 0, j = 0, len = 0, totallen = 0;
++ char line[255];
++
++ if (*offp != 0)
++ return 0;
++ pdata = buf;
++ len = sprintf(line, "USER MODULE INFORMATION:\n");
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++
++ //*******add Module 1 , this Module is ADSL ********/
++ for (i = 0; i < MAX_MOD_ID; i++)
++ {
++ if (modArr[i] != NULL)
++ {
++ len = sprintf(line, " Module ID = %d\n", i);
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++ for(j = 0; j < MAX_STATE_ID; j++)
++ {
++ if (modArr[i]->states[j] != NULL)
++ {
++ len = sprintf(line, "State =%d, Led = %d,", j, modArr[i]->states[j]->led);
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++ switch(modArr[i]->states[j]->mode)
++ {
++ case 1:
++ len = sprintf(line, "Mode = OFF\n");
++ break;
++ case 2:
++ len = sprintf(line, "Mode = BLINK_ON, On Time(ms) = %d\n", (unsigned int)modArr[i]->states[j]->param);
++ break;
++ case 3:
++ len = sprintf(line, "Mode = BLINK_OFF, Off Time(ms) = %d\n", (unsigned int)modArr[i]->states[j]->param);
++ break;
++ case 4:
++ len = sprintf(line, "Mode = On\n");
++ break;
++ case 5:
++ len = sprintf(line, "Mode = FLASH, Time Period(ms) = %d\n", (unsigned int)modArr[i]->states[j]->param);
++ break;
++ default:
++ break;
++ }
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++ }
++ }
++ }
++
++ }
++
++ len = sprintf(line, "Module ID = 2(system led)\n");
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++ switch(sys_mod_state)
++ {
++ case 1:
++ len = sprintf(line, "State = OFF\n");
++ break;
++ case 2:
++ len = sprintf(line, "State = Booting\n");
++ break;
++ case 3:
++ len = sprintf(line, "State = System Ready\n");
++ break;
++ case 4:
++ len = sprintf(line, "State = System Failure\n");
++ break;
++ default:
++ break;
++ }
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++
++ len = sprintf(line, "Module ID = 3(WAN led)\n");
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++ switch(wan_mod_state)
++ {
++ case 1:
++ len = sprintf(line, "State = OFF\n");
++ break;
++ case 2:
++ len = sprintf(line, "State = Wan Connected\n");
++ break;
++ case 3:
++ len = sprintf(line, "State = Wan Tx/Rx Activity\n");
++ break;
++ case 4:
++ len = sprintf(line, "State = Wan Connect Failure\n");
++ break;
++ default:
++ break;
++ }
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++
++//wwzh for wireless
++#if 0
++ len = sprintf(line, "Module ID = 4(WLAN led)\n");
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++ switch(wlan_mod_state)
++ {
++ case 1:
++ len = sprintf(line, "State = OFF\n");
++ break;
++ case 2:
++ len = sprintf(line, "State = wlan Ready\n");
++ break;
++ case 3:
++ len = sprintf(line, "State = wlan rx/tx activity\n");
++ break;
++ default:
++ break;
++ }
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++#endif //for wireless
++
++ *offp = totallen;
++ return totallen;
++}
++static ssize_t proc_write_led_fops(struct file *filp,const char *buffer,
++ size_t count , loff_t *offp)
++{
++ char *pdata = NULL, *ptemp = NULL;
++ char line[10], temp[10];
++ int i = 0;
++ int mod = 0xffff, state = 0xffff;
++ int flag = 0;
++
++ /* Check if this write is for configuring ADSL */
++ if( *(int *)(buffer) == 0xFFEEDDCC )
++ {
++ printk("<1>proc write:Calling Configuration\n");
++ config_led((unsigned long)(buffer + sizeof(int)) );
++ return count;
++ }
++
++ if (count > 10)
++ {
++ printk("<1> proc write: Input too long, max length = 10\n");
++ return count;
++ }
++ memset(temp, 0x00, 10);
++ memset(line, 0x00, 10);
++ copy_from_user(line, buffer, count);
++ line[count] = 0x00;
++ pdata = line;
++ ptemp = temp;
++
++ while (flag == 0)
++ {
++ if (i > 10)
++ break;
++ if (((*pdata) >= '0') && ((*pdata) <= '9'))
++ {
++ *ptemp = *pdata;
++ ptemp++;
++ }
++ else if ((*pdata) == ',')
++ {
++ *ptemp = 0x00;
++ flag = 1;
++ }
++ pdata++;
++ i++;
++ }
++ if (flag == 1)
++ mod = led_atoi(temp);
++ else
++ return count;
++
++ ptemp = temp;
++ *ptemp = 0x00;
++ flag = 0;
++
++ while(flag == 0)
++ {
++ if (i > 10)
++ break;
++ if (((*pdata) >= '0') && ((*pdata) <= '9'))
++ {
++ *ptemp = *pdata;
++ ptemp++;
++ }
++ else if ((*pdata) == 0x00)
++ {
++ *ptemp = 0x00;
++ flag = 1;
++ }
++ pdata++;
++ i++;
++ }
++ if (flag == 1)
++ state = led_atoi(temp);
++ else
++ return count;
++ if ((mod == 0xFFFF) || (state == 0xFFFF))
++ return count;
++ else
++ {
++ if (mod != 4)
++ led_active(mod, state);
++ else
++ led_operation(mod, state);
++ }
++ return 1;
++}
++#endif
++/************end *******************/
++static int config_led(unsigned long y)
++{
++ config_elem_t *pcfg = NULL;
++ char *pdata = NULL;
++ int i;
++ int length = 0 , number = 0;
++ unsigned int flags;
++
++ spin_lock_irqsave(&config_lock, flags);
++
++ /* ioctl to configure */
++ length = *((int*)y);
++ pdata = (char *)y + sizeof(int);
++ number = (length - sizeof(int))/sizeof(config_elem_t);
++ pcfg = (config_elem_t *)(pdata);
++
++ /* Check if an earlier configuration exists IF yes free it up */
++ free_memory();
++
++ for ( i = 0 ; i < number ; i++ )
++ {
++ /* If no structure has been allocated for the module do so */
++ if ( modArr[pcfg->name] == NULL )
++ {
++ printk("<1>module = %d\n",pcfg->name);
++ if( pcfg->name >= MAX_MOD_ID)
++ {
++ printk("<1>Exiting Configuration: Module ID too large %d\n",pcfg->name);
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ modArr[pcfg->name] = kmalloc(sizeof(mod_entry_t),GFP_KERNEL);
++ if(modArr[pcfg->name] == NULL)
++ {
++ printk("<1>Exiting Configuration: Error in allocating memory\n");
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ memset( modArr[pcfg->name], 0x00, sizeof(mod_entry_t));
++ }
++
++ /* if no structure is allocated previously for this state
++ allocate a structure, if it's already there fill it up */
++ if( modArr[pcfg->name]->states[pcfg->state] == NULL)
++ {
++ printk("<1>STATE = %d\n",pcfg->state);
++ if( pcfg->state >= MAX_STATE_ID)
++ {
++ printk("<1>Exiting Configuration: State ID too large\n");
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ modArr[pcfg->name]->states[pcfg->state] =
++ kmalloc(sizeof(state_entry_t),GFP_KERNEL);
++ if( modArr[pcfg->name]->states[pcfg->state] == NULL)
++ {
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ memset( modArr[pcfg->name]->states[pcfg->state], 0x00, sizeof(state_entry_t));
++ }
++ /* Fill up the fields of the state */
++ if( pcfg->led >= MAX_LED_ID)
++ {
++ printk("<1>led = %d\n",pcfg->led);
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ modArr[pcfg->name]->states[pcfg->state]->led = pcfg->led;
++ modArr[pcfg->name]->states[pcfg->state]->mode = pcfg->mode;
++ modArr[pcfg->name]->states[pcfg->state]->param = pcfg->param;
++ switch(pcfg->mode)
++ {
++ case 1:
++ modArr[pcfg->name]->states[pcfg->state]->handler = board_led_link_down;
++ break;
++ case 2:
++ case 3:
++ case 5:
++ if( pcfg->mode == 2 )
++ modArr[pcfg->name]->states[pcfg->state]->handler = board_led_activity_on;
++ else if( pcfg->mode == 3)
++ modArr[pcfg->name]->states[pcfg->state]->handler = board_led_activity_off;
++ else
++ modArr[pcfg->name]->states[pcfg->state]->handler = board_led_link_flash;
++ break;
++ case 4:
++ modArr[pcfg->name]->states[pcfg->state]->handler = board_led_link_up;
++ break;
++ default:
++ printk("<1>Exiting Configuration: Unknown LED Mode\n");
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ pcfg++;
++ }
++ spin_unlock_irqrestore(&config_lock, flags);
++ return 0;
++}
++
++
++int __init led_init(void)
++{
++
++ /* Clear our memory */
++ memset(modArr,0x00,sizeof(mod_entry_t *)*MAX_MOD_ID);
++ memset(led_arr,0x00,sizeof(led_data_t *)*MAX_LED_ID);
++
++ /* Create spin lock for config data structure */
++ config_lock=SPIN_LOCK_UNLOCKED;
++
++ /* Create directory */
++ led_proc_dir = proc_mkdir("led", NULL);
++ if( led_proc_dir == NULL )
++ goto out;
++
++ /* Create adsl file */
++ led_file = create_proc_entry("led", 0777, led_proc_dir);
++ if( led_file == NULL)
++ goto led_file;
++ led_file->owner = THIS_MODULE;
++ led_file->proc_fops = &led_fops;
++
++ memset( modArr , 0x00 , sizeof(mod_entry_t *) * MAX_MOD_ID);
++ /* Reset the GPIO pins */
++ board_gpio_init();
++
++ /* Register the UART controlled LEDS */
++ uart_led_init();
++ /* Create the usb proc file */
++ avalanche_leds_init();
++ return 0;
++
++ led_file:
++ remove_proc_entry("led",led_proc_dir);
++ out:
++ return 0;
++
++}
++
++void led_exit()
++{
++ remove_proc_entry("led", led_proc_dir);
++}
++
++module_init(led_init);
++module_exit(led_exit);
++
++void register_led_drv( int device , led_reg_t *pInfo)
++{
++ unsigned int flags;
++ struct timer_list *pTimer = NULL;
++
++ spin_lock_irqsave(&config_lock, flags);
++
++ led_arr[device].led = pInfo;
++ if( led_arr[device].led->init != 0x00)
++ led_arr[device].led->init(led_arr[device].led->param);
++ if( led_arr[device].led->offfunc != 0x00)
++ led_arr[device].led->offfunc(led_arr[device].led->param);
++
++ /* Create a timer for blinking */
++ pTimer = kmalloc(sizeof(struct timer_list),GFP_KERNEL);
++ init_timer( pTimer );
++ pTimer->function = led_timer_func;
++ pTimer->data = 0;
++ led_arr[device].pTimer = pTimer;
++ led_arr[device].timer_running = 0;
++
++ spin_unlock_irqrestore(&config_lock, flags);
++
++ return;
++}
++
++void deregister_led_drv( int device)
++{
++ unsigned int flags;
++
++ spin_lock_irqsave(&config_lock, flags);
++ led_arr[device].led = NULL;
++
++ if( led_arr[device].pTimer != NULL)
++ {
++ del_timer(led_arr[device].pTimer);
++ kfree(led_arr[device].pTimer);
++ }
++ spin_unlock_irqrestore(&config_lock, flags);
++
++ return;
++}
++
++EXPORT_SYMBOL_NOVERS(led_operation);
++EXPORT_SYMBOL_NOVERS(register_led_drv);
++EXPORT_SYMBOL_NOVERS(deregister_led_drv);
++
+diff -urN linux.dev/drivers/char/avalanche_led/leds.c linux.dev2/drivers/char/avalanche_led/leds.c
+--- linux.dev/drivers/char/avalanche_led/leds.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev2/drivers/char/avalanche_led/leds.c 2005-10-21 18:03:44.513777000 +0200
+@@ -0,0 +1,133 @@
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <asm/ar7/avalanche_regs.h>
++#include <linux/spinlock.h>
++#include <linux/timer.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/proc_fs.h>
++#include <asm/uaccess.h>
++#include <linux/fs.h>
++
++#include <asm/ar7/ledapp.h>
++
++#if defined(CONFIG_AR5D01) || defined(CONFIG_AR5W01) || defined(CONFIG_AR7)
++
++#define ETH_MASK 0x01
++#define USB_MASK 0x02
++
++static struct proc_dir_entry *usb_file;
++static ssize_t proc_read_usb_fops(struct file *filp,
++ char *buf,size_t count , loff_t *offp);
++struct file_operations usb_fops = {read: proc_read_usb_fops};
++
++typedef struct mod_states{
++ int module;
++ int activity;
++ int linkup;
++ int idle;
++}mod_states_t;
++
++mod_states_t state_arr[] = {
++ { MOD_ETH,DEF_ETH_ACTIVITY,DEF_ETH_LINK_UP,DEF_ETH_IDLE },
++ { MOD_USB,DEF_USB_ACTIVITY,DEF_USB_LINK_UP,DEF_USB_IDLE },
++ { MOD_LAN,DEF_LAN_ACTIVITY,DEF_LAN_LINK_UP,DEF_LAN_IDLE }
++ };
++
++unsigned char device_links = 0; /* Bitmask with the devices that are up */
++
++
++void avalanche_led_activity_pulse(unsigned long device)
++{
++ /* If device link is not up return */
++ if( !(device_links & (unsigned char)(1 << device)))
++ return;
++#ifdef MULTIPLEX_LED
++ led_operation( state_arr[2].module, state_arr[2].activity);
++#else
++ led_operation( state_arr[device].module, state_arr[device].activity);
++#endif
++}
++
++void avalanche_led_link_up( unsigned long device )
++{
++
++ /* If already UP ignore */
++ if( device_links & (unsigned char)(1 << device))
++ return;
++ /* Turn on the bit for the device */
++ device_links |= (unsigned char)(1 << device);
++#ifdef MULTIPLEX_LED
++ led_operation( state_arr[2].module, state_arr[2].linkup);
++#else
++ led_operation( state_arr[device].module, state_arr[device].linkup);
++#endif
++}
++
++void avalanche_led_link_down ( unsigned long device )
++{
++
++ /* If already DOWN ignore */
++ if( !(device_links & (unsigned char)(1 << device)))
++ return;
++
++ /* Turn off the bit for the device */
++ device_links &= ~(unsigned char)(1 << device);
++#ifdef MULTIPLEX_LED
++ /* If no links, then shut the LED off */
++ if(!device_links)
++ led_operation( state_arr[2].module, state_arr[2].idle);
++#else
++ led_operation( state_arr[device].module, state_arr[device].idle);
++#endif
++}
++
++static ssize_t proc_read_usb_fops(struct file *filp,
++ char *buf,size_t count , loff_t *offp)
++{
++ char * pdata = NULL;
++ char line[3];
++ if( *offp != 0 )
++ return 0;
++ pdata = buf;
++ if( device_links & USB_MASK)
++ sprintf(line,"%s\n","1");
++ else
++ sprintf(line,"%s\n","0");
++ copy_to_user(pdata,line,2);
++ *offp = 2;
++ return 2;
++}
++
++
++void avalanche_leds_init(void)
++{
++ /* Create usb link proc file */
++ usb_file = create_proc_entry("avalanche/usb_link", 0444, NULL);
++ if( usb_file == NULL)
++ return;
++ usb_file->owner = THIS_MODULE;
++ usb_file->proc_fops = &usb_fops;
++ return;
++}
++
++EXPORT_SYMBOL(avalanche_led_activity_pulse);
++EXPORT_SYMBOL(avalanche_led_link_up);
++EXPORT_SYMBOL(avalanche_led_link_down);
++
++#else
++/* We make a dummy init routine for the platforms that do not support this led
++ API
++*/
++
++void avalanche_leds_init(void)
++{
++}
++
++#endif
++
++
++
++
++
+diff -urN linux.dev/drivers/char/avalanche_led/uartled.c linux.dev2/drivers/char/avalanche_led/uartled.c
+--- linux.dev/drivers/char/avalanche_led/uartled.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev2/drivers/char/avalanche_led/uartled.c 2005-10-21 18:03:44.529778000 +0200
+@@ -0,0 +1,55 @@
++#include <linux/kernel.h>
++#include <asm/uaccess.h>
++#include <linux/spinlock.h>
++#include <asm/ar7/avalanche_regs.h>
++#include <asm/ar7/ledapp.h>
++
++#define UART_LED_REG (*(volatile unsigned int *)(UARTA_BASE + 0x10))
++
++static spinlock_t device_lock;
++led_reg_t temp1[2];
++
++static void uart_led_on(unsigned long param)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&device_lock,flags);
++ UART_LED_REG &= 0xFFFD;
++ spin_unlock_irqrestore(&device_lock, flags);
++}
++
++static void uart_led_off ( unsigned long param )
++{
++ unsigned int flags = 0x00;
++ spin_lock_irqsave(&device_lock, flags);
++ UART_LED_REG |= 0x02;
++ spin_unlock_irqrestore(&device_lock, flags);
++}
++
++void uart_led_init(void)
++{
++
++#if defined(CONFIG_AR5D01)
++ /* Register led 6 UART Pin 1 */
++ temp1[0].param = 0;
++ temp1[0].init = NULL;
++ temp1[0].onfunc = uart_led_on;
++ temp1[0].offfunc = uart_led_off;
++ register_led_drv( 6 , &temp1[0]);
++#endif
++
++#if defined(CONFIG_AR5W01)
++ /* Register led 8 UART Pin 1 */
++ temp1[0].param = 0;
++ temp1[0].init = NULL;
++ temp1[0].onfunc = uart_led_on;
++ temp1[0].offfunc = uart_led_off;
++ register_led_drv( 8 , &temp1[0]);
++#endif
++
++ /* Initialize the link mask */
++ device_lock = SPIN_LOCK_UNLOCKED;
++
++ return;
++}
++
+diff -urN linux.dev/include/asm-mips/ar7/led_config.h linux.dev2/include/asm-mips/ar7/led_config.h
+--- linux.dev/include/asm-mips/ar7/led_config.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev2/include/asm-mips/ar7/led_config.h 2005-10-21 17:02:25.568327000 +0200
+@@ -0,0 +1,55 @@
++/******************************************************************************
++ * FILE PURPOSE: - LED config Header
++ ******************************************************************************
++ * FILE NAME: led_config.h
++ *
++ * DESCRIPTION: Header file for LED configuration parameters
++ * and data structures
++ *
++ * REVISION HISTORY:
++ * 11 Oct 03 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++
++#ifndef __LED_CONFIG__
++#define __LED_CONFIG__
++
++/* LED config parameters */
++#define MAX_GPIO_PIN_NUM 64
++#define MAX_GPIOS_PER_STATE 5
++#define MAX_MODULE_ENTRIES 25
++#define MAX_MODULE_INSTANCES 4
++#define MAX_STATE_ENTRIES 25
++#define MAX_LED_ENTRIES 25
++
++
++/* LED modes */
++#define LED_OFF 0
++#define LED_ON 1
++#define LED_ONESHOT_OFF 2
++#define LED_ONESHOT_ON 3
++#define LED_FLASH 4
++#define LED_BLINK_CODE0 5 /*--- param1: on time, param2: blink nr , (param2 > 100 blink off) ---*/
++#define LED_BLINK_CODE1 6
++#define LED_BLINK_CODE2 7
++
++#define NUM_LED_MODES 8
++
++
++
++/* Data structure for LED configuration */
++typedef struct led_config{
++ unsigned char name[80];
++ unsigned int instance;
++ unsigned int state;
++ unsigned int gpio[MAX_GPIOS_PER_STATE];
++ unsigned int mode[MAX_GPIOS_PER_STATE];
++ unsigned int gpio_num;
++ unsigned int param1;
++ unsigned int param2;
++}LED_CONFIG_T;
++
++
++#endif /* __LED_CONFIG__ */
+diff -urN linux.dev/include/asm-mips/ar7/led_hal.h linux.dev2/include/asm-mips/ar7/led_hal.h
+--- linux.dev/include/asm-mips/ar7/led_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev2/include/asm-mips/ar7/led_hal.h 2005-10-21 17:02:25.568327000 +0200
+@@ -0,0 +1,30 @@
++/******************************************************************************
++ * FILE PURPOSE: - LED HAL module Header
++ ******************************************************************************
++ * FILE NAME: led_hal.h
++ *
++ * DESCRIPTION: LED HAL API's.
++ *
++ * REVISION HISTORY:
++ * 11 Oct 03 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++#ifndef __LED_HAL__
++#define __LED_HAL__
++
++/* Interface prototypes */
++#include "led_config.h"
++
++int avalanche_led_hal_init (int *gpio_off_value, int num_gpio_pins);
++int avalanche_led_config_set (LED_CONFIG_T * led_cfg);
++int avalanche_led_config_get (LED_CONFIG_T *led_cfg,int module_id,int instance, int state);
++void *avalanche_led_register (const char *module_name, int instance_num);
++void avalanche_led_action (void *handle, int state_id);
++void avalanche_led_late_actions(void);
++int avalanche_led_unregister (void *handle);
++void avalanche_led_free_all(void);
++void avalanche_led_hal_exit (void);
++
++#endif /*__LED_HAL__ */
+diff -urN linux.dev/include/asm-mips/ar7/ledapp.h linux.dev2/include/asm-mips/ar7/ledapp.h
+--- linux.dev/include/asm-mips/ar7/ledapp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev2/include/asm-mips/ar7/ledapp.h 2005-10-21 18:03:44.573780750 +0200
+@@ -0,0 +1,59 @@
++#ifndef __LED_APP__
++#define __LED_APP__
++
++#define CONF_FILE "/etc/led.conf"
++#define LED_PROC_FILE "/proc/led_mod/led"
++
++#define CONFIG_LED_MODULE
++
++#define MAX_MOD_ID 25
++#define MAX_STATE_ID 25
++#define MAX_LED_ID 25
++
++#define MOD_ADSL 1
++#define DEF_ADSL_IDLE 1
++#define DEF_ADSL_TRAINING 2
++#define DEF_ADSL_SYNC 3
++#define DEF_ADSL_ACTIVITY 4
++
++#define MOD_WAN 2
++#define DEF_WAN_IDLE 1
++#define DEF_WAN_NEGOTIATE 2
++#define DEF_WAN_SESSION 3
++
++#define MOD_LAN 3
++#define DEF_LAN_IDLE 1
++#define DEF_LAN_LINK_UP 2
++#define DEF_LAN_ACTIVITY 3
++
++#define MOD_WLAN 4
++#define DEF_WLAN_IDLE 1
++#define DEF_WLAN_LINK_UP 2
++#define DEF_WLAN_ACTIVITY 3
++
++#define MOD_USB 5
++#define DEF_USB_IDLE 1
++#define DEF_USB_LINK_UP 2
++#define DEF_USB_ACTIVITY 3
++
++#define MOD_ETH 6
++#define DEF_ETH_IDLE 1
++#define DEF_ETH_LINK_UP 2
++#define DEF_ETH_ACTIVITY 3
++
++typedef struct config_elem{
++ unsigned char name;
++ unsigned char state;
++ unsigned char mode;
++ unsigned char led;
++ int param;
++}config_elem_t;
++
++typedef struct led_reg{
++ unsigned int param;
++ void (*init)(unsigned long param);
++ void (*onfunc)(unsigned long param);
++ void (*offfunc)(unsigned long param);
++}led_reg_t;
++
++#endif
diff --git a/openwrt/target/linux/ar7-2.4/patches/003-net_driver_cpmac.patch b/openwrt/target/linux/ar7-2.4/patches/003-net_driver_cpmac.patch
new file mode 100644
index 0000000000..42b64584da
--- /dev/null
+++ b/openwrt/target/linux/ar7-2.4/patches/003-net_driver_cpmac.patch
@@ -0,0 +1,13341 @@
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpcommon_cpmac.c linux.dev/drivers/net/avalanche_cpmac/cpcommon_cpmac.c
+--- linux.old/drivers/net/avalanche_cpmac/cpcommon_cpmac.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpcommon_cpmac.c 2005-07-12 02:48:41.996601000 +0200
+@@ -0,0 +1,728 @@
++#ifndef _INC_CPCOMMON_C
++#define _INC_CPCOMMON_C
++
++#ifdef _CPHAL_CPMAC
++#include "cpremap_cpmac.c"
++#endif
++
++#ifdef _CPHAL_AAL5
++#include "cpremap_cpaal5.c"
++#endif
++
++#ifdef _CPHAL_CPSAR
++#include "cpremap_cpsar.c"
++#endif
++
++#ifdef _CPHAL_AAL2
++#include "cpremap_cpaal2.c"
++#endif
++
++/**
++@defgroup Common_Config_Params Common Configuration Parameters
++
++This section documents the configuration parameters that are valid across
++all CPHAL devices.
++@{
++*/
++/** This is the debug level. The field is bit defined, such that the user
++should set to 1 all the bits corresponding to desired debug outputs. The following
++are the meanings for each debug bit:
++- bit0 (LSB): CPHAL Function Trace
++- b1 : OS Function call trace
++- b2 : Critical section entry/exit
++- b3 : Memory allocation/destruction
++- b4 : Detailed information in Rx path
++- b5 : Detailed information in Tx path
++- b6 : Extended error information
++- b7 : General info
++*/
++static const char pszDebug[] = "debug";
++/** CPU Frequency. */
++/*static const char pszCpuFreq[] = "CpuFreq";*/ /*MJH-030403*/
++/** Base address for the module. */
++static const char pszBase[] = "base";
++/** Reset bit for the module. */
++static const char pszResetBit[] = "reset_bit";
++/** Reset base address for the module. */
++static const char pszResetBase[] = "ResetBase";
++/** Interrupt line for the module. */
++static const char pszIntLine[] = "int_line";
++/** VLYNQ offset for the module. Disregard if not using VLYNQ. */
++static const char pszOffset[] = "offset";
++/** The OS may "Get" this parameter, which is a pointer
++ to a character string that indicates the version of CPHAL. */
++static const char pszVer[] = "Version";
++/*@}*/
++
++/**
++@defgroup Common_Control_Params Common Keys for [os]Control()
++
++This section documents the keys used with the OS @c Control() interface that
++are required by CPHAL devices.
++
++@{
++*/
++/** Used to wait for an integer number of clock ticks, given as an integer
++ pointer in the @p Value parameter. No actions are defined. */
++static const char pszSleep[] = "Sleep";
++/** Requests the OS to flush it's IO buffers. No actions are defined. */
++static const char pszSioFlush[] = "SioFlush";
++/*@}*/
++
++static const char pszStateChange[] = "StateChange";
++static const char pszStatus[] = "Status";
++
++static const char pszGET[] = "Get";
++static const char pszSET[] = "Set";
++static const char pszCLEAR[] = "Clear";
++static const char pszNULL[] = "";
++static const char pszLocator[] = "Locator";
++static const char pszOff[] = "Off";
++static const char pszOn[] = "On";
++static const char hcMaxFrags[] = "MaxFrags";
++
++#ifdef _CPHAL_CPMAC
++
++/* New method for string constants */
++const char hcClear[] = "Clear";
++const char hcGet[] = "Get";
++const char hcSet[] = "Set";
++
++const char hcTick[] = "Tick";
++
++static const CONTROL_KEY KeyCommon[] =
++ {
++ {"" , enCommonStart},
++ {pszStatus , enStatus},
++ {pszOff , enOff},
++ {pszOn , enOn},
++ {pszDebug , enDebug},
++ {hcCpuFrequency , enCpuFreq}, /*MJH~030403*/
++ {"" , enCommonEnd}
++ };
++#endif
++
++/**
++@defgroup Common_Statistics Statistics
++
++A broad array of module statistics is available. Statistics values are accessed
++through the @c Control() interface of the CPHAL. There are 5 different levels
++of statistics, each of which correspond to a unique set of data. Furthermore,
++certain statistics data is indexed by using a channel number and Tx queue number.
++The following is a brief description of each statistics level, along with the
++indexes used for the level:
++
++- Level 0: Hardware Statistics (index with channel)
++- Level 1: CPHAL Software Statistics (channel, queue)
++- Level 2: CPHAL Flags (channel, queue)
++- Level 3: CPHAL Channel Configuration (channel)
++- Level 4: CPHAL General Configuration (no index)
++
++The caller requests statistics information by providing a Key string to the
++@c Control() API in the following format: "Stats;[Level #];[Ch #];[Queue #]".
++The only valid Action parameter for statistics usage is "Get".
++
++Code Examples:
++@code
++unsigned int *StatsData;
++
++# Get Level 0 stats for Channel 1
++HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
++
++# Get Level 2 stats for Channel 0, Queue 0
++HalFunc->Control(OsDev->HalDev, "Stats;2;0;0", "Get", &StatsData);
++
++# Get Level 4 stats
++HalFunc->Control(OsDev->HalDev, "Stats;4", "Get", &StatsData);
++@endcode
++
++The information returned in the Value parameter of @c Control() is an
++array of pointers to strings. The pointers are arranged in pairs.
++The first pointer is a pointer to a name string for a particular statistic.
++The next pointer is a pointer to a string containing the representation of
++the integer statistic value corresponding to the first pointer. This is followed
++by another pair of pointers, and so on, until a NULL pointer is encountered. The
++following is example code for processing the statistics data. Note that the OS
++is responsible for freeing the memory passed back through the Value parameter of
++@c Control().
++
++@code
++unsigned int *StatsData;
++
++# Get Level 0 stats for Channel 1
++HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
++
++# output Statistics data
++PrintStats(StatsData);
++
++# the upper layer is responsible for freeing stats info
++free(&StatsPtr);
++
++...
++
++void PrintStats(unsigned int *StatsPtr)
++ {
++ while(*StatsPtr)
++ {
++ printf("%20s:", (char *)*StatsPtr);
++ StatsPtr++;
++ printf("%11s\n", (char *)*StatsPtr);
++ StatsPtr++;
++ }
++ MySioFlush();
++ }
++@endcode
++
++Within each statistics level, there are several statistics defined. The statistics that
++are common to every CPPI module are listed below. In addition, each module may define
++extra statistics in each level, which will be documented within the module-specific
++documentation appendices.
++
++- Level 0 Statistics
++ - All level 0 statistics are module-specific.
++- Level 1 Statistics (CPHAL Software Statistics)
++ - DmaLenErrors: Incremented when the port DMA's more data than expected (per channel). (AAL5 Only)
++ - TxMisQCnt: Incremented when host queues a packet for transmission as the port finishes
++transmitting the previous last packet in the queue (per channel and queue).
++ - RxMisQCnt: Incremented when host queues adds buffers to a queue as the port finished the
++reception of the previous last packet in the queue (per channel).
++ - TxEOQCnt: Number of times the port has reached the end of the transmit queue (per channel and queue).
++ - RxEOQCnt: Number of times the port has reached the end of the receive queue (per channel).
++ - RxPacketsServiced: Number of received packets (per channel).
++ - TxPacketsServiced: Number of transmitted packets (per channel and queue).
++ - RxMaxServiced: Maximum number of packets that the CPHAL receive interrupt has serviced at a time (per channel).
++ - TxMaxServiced: Maximum number of packets that the CPHAL transmit interrupt has serviced at a time (per channel and queue).
++ - RxTotal: Total number of received packets, all channels.
++ - TxTotal: Total number of transmitted packets, all channels and queues.
++- Level 2 Statistics (CPHAL Flags)
++ - RcbPool: Pointer to receive descriptor pool (per channel).
++ - RxActQueueCount: Number of buffers currently available for receive (per channel).
++ - RxActQueueHead: Pointer to first buffer in receive queue (per channel).
++ - RxActQueueTail: Pointer to last buffer in receive queue (per channel).
++ - RxActive: 0 if inactive (no buffers available), or 1 if active (buffers available).
++ - RcbStart: Pointer to block of receive descriptors.
++ - RxTeardownPending: 1 if Rx teardown is pending but incomplete, 0 otherwise.
++ - TcbPool: Pointer to transmit descriptor pool (per channel and queue).
++ - TxActQueueCount: Number of buffers currently queued to be transmitted (per channel and queue).
++ - TxActQueueHead: Pointer to first buffer in transmit queue (per channel and queue).
++ - TxActQueueTail: Pointer to last buffer in transmit queue (per channel and queue).
++ - TxActive: 0 if inactive (no buffers to send), or 1 if active (buffers queued to send).
++ - TcbStart: Pointer to block of transmit descriptors.
++ - TxTeardownPending: 1 if Tx teardown is pending but incomplete, 0 otherwise.
++- Level 3 Statistics (CPHAL Channel Configuration)
++ - RxBufSize: Rx buffer size.
++ - RxBufferOffset: Rx buffer offset.
++ - RxNumBuffers: Number of Rx buffers.
++ - RxServiceMax: Maximum number of receive packets to service at a time.
++ - TxNumBuffers: Number of Tx buffer descriptors.
++ - TxNumQueues: Number of Tx queues to use.
++ - TxServiceMax: Maximum number of transmit packets to service at a time.
++- Level 4 Statistics (CPHAL General Configuration)
++ - Base Address: Base address of the module.
++ - Offset (VLYNQ): VLYNQ relative module offset.
++ - Interrupt Line: Interrupt number.
++ - Debug: Debug flag, 1 to enable debug.
++ - Inst: Instance number.
++*/
++
++/*
++ Data Type 0 = int display
++ Data Type 1 = hex display
++ Data Type 2 = channel structure, int display
++ Data Type 3 = queue index and int display
++ Data Type 4 = queue index and hex display
++*/
++#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC)) /* +GSG 030307 */
++static STATS_TABLE StatsTable0[] =
++ {
++#ifdef _CPHAL_AAL5
++ /* Name , Data Ptr, Data Type */
++ {"Crc Errors", 0, 0},
++ {"Len Errors", 0, 0},
++ {"Abort Errors", 0, 0},
++ {"Starv Errors", 0, 0}
++#endif
++#ifdef _CPHAL_CPMAC
++ {"Rx Good Frames", 0, 0}
++#endif
++ };
++
++static STATS_TABLE StatsTable1[] =
++ {
++ /* Name , Data Ptr, Data Type */
++ {"DmaLenErrors", 0, 0},
++ {"TxMisQCnt", 0, 3},
++ {"RxMisQCnt", 0, 0},
++ {"TxEOQCnt", 0, 3},
++ {"RxEOQCnt", 0, 0},
++ {"RxPacketsServiced", 0, 0},
++ {"TxPacketsServiced", 0, 3},
++ {"RxMaxServiced", 0, 0},
++ {"TxMaxServiced", 0, 3},
++ {"RxTotal", 0, 0},
++ {"TxTotal", 0, 0},
++ };
++
++static STATS_TABLE StatsTable2[] =
++ {
++ /* Name , Data Ptr, Data Type */
++ {"RcbPool", 0, 1},
++ {"RxActQueueCount", 0, 0},
++ {"RxActQueueHead", 0, 1},
++ {"RxActQueueTail", 0, 1},
++ {"RxActive", 0, 0},
++ {"RcbStart", 0, 1},
++ {"RxTeardownPending", 0, 0},
++ {"TcbPool", 0, 4},
++ {"TxActQueueCount", 0, 3},
++ {"TxActQueueHead", 0, 4},
++ {"TxActQueueTail", 0, 4},
++ {"TxActive", 0, 3},
++ {"TcbStart", 0, 4},
++ {"TxTeardownPending", 0, 0}
++ };
++
++static STATS_TABLE StatsTable3[] =
++ {
++ /* Name , Data Ptr, Data Type */
++ {"RxBufSize", 0, 2},
++ {"RxBufferOffset", 0, 2},
++ {"RxNumBuffers", 0, 2},
++ {"RxServiceMax", 0, 2},
++ {"TxNumBuffers", 0, 2},
++ {"TxNumQueues", 0, 2},
++ {"TxServiceMax", 0, 2},
++#ifdef _CPHAL_AAL5
++ {"CpcsUU", 0, 2},
++ {"Gfc", 0, 2},
++ {"Clp", 0, 2},
++ {"Pti", 0, 2},
++ {"DaMask", 0, 2},
++ {"Priority", 0, 2},
++ {"PktType", 0, 2},
++ {"Vci", 0, 2},
++ {"Vpi", 0, 2},
++ {"CellRate", 0, 2},
++ {"QosType", 0, 2},
++ {"Mbs", 0, 2},
++ {"Pcr", 0, 2}
++#endif
++ };
++
++static STATS_TABLE StatsTable4[] =
++ {
++ {"Base Address", 0, 1},
++ {"Offset (VLYNQ)", 0, 0},
++ {"Interrupt Line", 0, 0},
++ {"Debug", 0, 0},
++ {"Instance", 0, 0},
++#ifdef _CPHAL_AAL5
++ {"UniNni", 0, 0}
++#endif
++ };
++
++static STATS_DB StatsDb[] =
++ {
++ {(sizeof(StatsTable0)/sizeof(STATS_TABLE)), StatsTable0},
++ {(sizeof(StatsTable1)/sizeof(STATS_TABLE)), StatsTable1},
++ {(sizeof(StatsTable2)/sizeof(STATS_TABLE)), StatsTable2},
++ {(sizeof(StatsTable3)/sizeof(STATS_TABLE)), StatsTable3},
++ {(sizeof(StatsTable4)/sizeof(STATS_TABLE)), StatsTable4}
++ };
++#endif /* +GSG 030307 */
++
++#ifdef _CPHAL_CPMAC /* +RC 3.02 */
++static void resetWait(HAL_DEVICE *HalDev)
++ { /*+RC3.02*/
++ const int TickReset=64;
++ osfuncSleep((int*)&TickReset);
++ } /*+RC3.02*/
++#endif /* +RC 3.02 */
++
++/* I only define the reset base function for the modules
++ that can perform a reset. The AAL5 and AAL2 modules
++ do not perform a reset, that is done by the shared module
++ CPSAR */
++#if defined(_CPHAL_CPSAR) || defined(_CPHAL_CPMAC) || defined(_CPHAL_VDMAVT)
++/*
++ * Determines the reset register address to be used for a particular device.
++ * It will search the current device entry for Locator information. If the
++ * device is a root device, there will be no Locator information, and the
++ * function will find and return the root reset register. If a Locator value
++ * is found, the function will search each VLYNQ device entry in the system
++ * looking for a matching Locator. Once it finds a VLYNQ device entry with
++ * a matching Locator, it will extract the "ResetBase" parameter from that
++ * VLYNQ device entry (thus every VLYNQ entry must have the ResetBase parameter).
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param ResetBase Pointer to integer address of reset register.
++ *
++ * @return 0 OK, Non-zero not OK
++ */
++static int ResetBaseGet(HAL_DEVICE *HalDev, bit32u *ResetBase)
++ {
++ char *DeviceInfo = HalDev->DeviceInfo;
++ char *MyLocator, *NextLocator;
++ int Inst=1;
++ bit32u error_code;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpcommon]ResetBaseGet(HalDev:%08x, ResetBase:%08x)\n", (bit32u)HalDev, ResetBase);
++ osfuncSioFlush();
++ }
++#endif
++
++ error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &MyLocator);
++ if (error_code)
++ {
++ /* if no Locator value, device is on the root, so get the "reset" device */
++ error_code = HalDev->OsFunc->DeviceFindInfo(0, "reset", &DeviceInfo);
++ if (error_code)
++ {
++ return(EC_VAL_DEVICE_NOT_FOUND);
++ }
++
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "base", ResetBase);
++ if (error_code)
++ {
++ return(EC_VAL_BASE_ADDR_NOT_FOUND);
++ }
++
++ *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
++
++ /* found base address for root device, so we're done */
++ return (EC_NO_ERRORS);
++ }
++ else
++ {
++ /* we have a Locator value, so the device is remote */
++
++ /* Find a vlynq device with a matching locator value */
++ while ((HalDev->OsFunc->DeviceFindInfo(Inst, "vlynq", &DeviceInfo)) == EC_NO_ERRORS)
++ {
++ error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &NextLocator);
++ if (error_code)
++ {
++ /* no Locator value for this VLYNQ, so move on */
++ continue;
++ }
++ if (HalDev->OsFunc->Strcmpi(MyLocator, NextLocator)==0)
++ {
++ /* we have found a VLYNQ with a matching Locator, so extract the ResetBase */
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "ResetBase", ResetBase);
++ if (error_code)
++ {
++ return(EC_VAL_BASE_ADDR_NOT_FOUND);
++ }
++ *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
++
++ /* found base address for root device, so we're done */
++ return (EC_NO_ERRORS);
++ }
++ Inst++;
++ } /* while */
++ } /* else */
++
++ return (EC_NO_ERRORS);
++ }
++#endif
++
++#ifndef _CPHAL_AAL2 /* + RC 3.02 */
++static bit32u ConfigGetCommon(HAL_DEVICE *HalDev)
++ {
++ bit32u ParmValue;
++ bit32 error_code;
++ char *DeviceInfo = HalDev->DeviceInfo;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpcommon]ConfigGetCommon(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszBase, &ParmValue);
++ if (error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_BASE_ADDR_NOT_FOUND);
++ }
++ HalDev->dev_base = ((bit32u)PhysToVirtNoCache(ParmValue));
++
++#ifndef _CPHAL_AAL5
++#ifndef _CPHAL_AAL2
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszResetBit, &ParmValue);
++ if(error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BIT_NOT_FOUND);
++ }
++ HalDev->ResetBit = ParmValue;
++
++ /* Get reset base address */
++ error_code = ResetBaseGet(HalDev, &ParmValue);
++ if (error_code)
++ return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BASE_NOT_FOUND);
++ HalDev->ResetBase = ParmValue;
++#endif
++#endif
++
++#ifndef _CPHAL_CPSAR
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszIntLine,&ParmValue);
++ if (error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_INTERRUPT_NOT_FOUND);
++ }
++ HalDev->interrupt = ParmValue;
++#endif
++
++ /* only look for the offset if there is a Locator field, which indicates that
++ the module is a VLYNQ module */
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszLocator,&ParmValue);
++ if (!error_code)
++ {
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszOffset,&ParmValue);
++ if (error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_OFFSET_NOT_FOUND);
++ }
++ HalDev->offset = ParmValue;
++ }
++ else
++ HalDev->offset = 0;
++
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszDebug, &ParmValue);
++ if (!error_code) HalDev->debug = ParmValue;
++
++ return (EC_NO_ERRORS);
++ }
++#endif /* +RC 3.02 */
++
++#ifdef _CPHAL_CPMAC /* +RC 3.02 */
++static void StatsInit(HAL_DEVICE *HalDev) /* +() RC3.02 */
++ {
++ /* even though these statistics may be for multiple channels and
++ queues, i need only configure the pointer to the beginning
++ of the array, and I can index from there if necessary */
++
++#ifdef _CPHAL_AAL5
++ StatsTable0[0].StatPtr = &HalDev->Stats.CrcErrors[0];
++ StatsTable0[1].StatPtr = &HalDev->Stats.LenErrors[0];
++ StatsTable0[2].StatPtr = &HalDev->Stats.AbortErrors[0];
++ StatsTable0[3].StatPtr = &HalDev->Stats.StarvErrors[0];
++
++ StatsTable1[0].StatPtr = &HalDev->Stats.DmaLenErrors[0];
++ StatsTable1[1].StatPtr = &HalDev->Stats.TxMisQCnt[0][0];
++ StatsTable1[2].StatPtr = &HalDev->Stats.RxMisQCnt[0];
++ StatsTable1[3].StatPtr = &HalDev->Stats.TxEOQCnt[0][0];
++ StatsTable1[4].StatPtr = &HalDev->Stats.RxEOQCnt[0];
++ StatsTable1[5].StatPtr = &HalDev->Stats.RxPacketsServiced[0];
++ StatsTable1[6].StatPtr = &HalDev->Stats.TxPacketsServiced[0][0];
++ StatsTable1[7].StatPtr = &HalDev->Stats.RxMaxServiced;
++ StatsTable1[8].StatPtr = &HalDev->Stats.TxMaxServiced[0][0];
++ StatsTable1[9].StatPtr = &HalDev->Stats.RxTotal;
++ StatsTable1[10].StatPtr = &HalDev->Stats.TxTotal;
++#endif
++
++#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC))
++ StatsTable2[0].StatPtr = (bit32u *)&HalDev->RcbPool[0];
++ StatsTable2[1].StatPtr = &HalDev->RxActQueueCount[0];
++ StatsTable2[2].StatPtr = (bit32u *)&HalDev->RxActQueueHead[0];
++ StatsTable2[3].StatPtr = (bit32u *)&HalDev->RxActQueueTail[0];
++ StatsTable2[4].StatPtr = &HalDev->RxActive[0];
++ StatsTable2[5].StatPtr = (bit32u *)&HalDev->RcbStart[0];
++ StatsTable2[6].StatPtr = &HalDev->RxTeardownPending[0];
++ StatsTable2[7].StatPtr = (bit32u *)&HalDev->TcbPool[0][0];
++ StatsTable2[8].StatPtr = &HalDev->TxActQueueCount[0][0];
++ StatsTable2[9].StatPtr = (bit32u *)&HalDev->TxActQueueHead[0][0];
++ StatsTable2[10].StatPtr = (bit32u *)&HalDev->TxActQueueTail[0][0];
++ StatsTable2[11].StatPtr = &HalDev->TxActive[0][0];
++ StatsTable2[12].StatPtr = (bit32u *)&HalDev->TcbStart[0][0];
++ StatsTable2[13].StatPtr = &HalDev->TxTeardownPending[0];
++
++ StatsTable3[0].StatPtr = &HalDev->ChData[0].RxBufSize;
++ StatsTable3[1].StatPtr = &HalDev->ChData[0].RxBufferOffset;
++ StatsTable3[2].StatPtr = &HalDev->ChData[0].RxNumBuffers;
++ StatsTable3[3].StatPtr = &HalDev->ChData[0].RxServiceMax;
++ StatsTable3[4].StatPtr = &HalDev->ChData[0].TxNumBuffers;
++ StatsTable3[5].StatPtr = &HalDev->ChData[0].TxNumQueues;
++ StatsTable3[6].StatPtr = &HalDev->ChData[0].TxServiceMax;
++#ifdef _CPHAL_AAL5
++ StatsTable3[7].StatPtr = &HalDev->ChData[0].CpcsUU;
++ StatsTable3[8].StatPtr = &HalDev->ChData[0].Gfc;
++ StatsTable3[9].StatPtr = &HalDev->ChData[0].Clp;
++ StatsTable3[10].StatPtr = &HalDev->ChData[0].Pti;
++ StatsTable3[11].StatPtr = &HalDev->ChData[0].DaMask;
++ StatsTable3[12].StatPtr = &HalDev->ChData[0].Priority;
++ StatsTable3[13].StatPtr = &HalDev->ChData[0].PktType;
++ StatsTable3[14].StatPtr = &HalDev->ChData[0].Vci;
++ StatsTable3[15].StatPtr = &HalDev->ChData[0].Vpi;
++ StatsTable3[16].StatPtr = &HalDev->ChData[0].TxVc_CellRate;
++ StatsTable3[17].StatPtr = &HalDev->ChData[0].TxVc_QosType;
++ StatsTable3[18].StatPtr = &HalDev->ChData[0].TxVc_Mbs;
++ StatsTable3[19].StatPtr = &HalDev->ChData[0].TxVc_Pcr;
++#endif
++#endif
++
++ StatsTable4[0].StatPtr = &HalDev->dev_base;
++ StatsTable4[1].StatPtr = &HalDev->offset;
++ StatsTable4[2].StatPtr = &HalDev->interrupt;
++ StatsTable4[3].StatPtr = &HalDev->debug;
++ StatsTable4[4].StatPtr = &HalDev->Inst;
++ }
++#endif /* +RC 3.02 */
++
++#ifndef _CPHAL_CPSAR /* +RC 3.02 */
++#ifndef _CPHAL_AAL2 /* +RC 3.02 */
++/*
++ * Returns statistics information.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return 0
++ */
++static int StatsGet(HAL_DEVICE *HalDev, void **StatPtr, int Index, int Ch, int Queue)
++ {
++ int Size;
++ bit32u *AddrPtr;
++ char *DataPtr;
++ STATS_TABLE *StatsTable;
++ int i, NumberOfStats;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpcommon]StatsGet(HalDev:%08x, StatPtr:%08x)\n",
++ (bit32u)HalDev, (bit32u)StatPtr);
++ osfuncSioFlush();
++ }
++#endif
++
++ StatsTable = StatsDb[Index].StatTable;
++ NumberOfStats = StatsDb[Index].NumberOfStats;
++
++ Size = sizeof(bit32u)*((NumberOfStats*2)+1);
++ Size += (NumberOfStats*11);
++ *StatPtr = (bit32u *)HalDev->OsFunc->Malloc(Size);
++
++ AddrPtr = (bit32u *) *StatPtr;
++ DataPtr = (char *)AddrPtr;
++ DataPtr += sizeof(bit32u)*((NumberOfStats*2)+1);
++
++ for (i=0; i<NumberOfStats; i++)
++ {
++ *AddrPtr++ = (bit32u)StatsTable[i].StatName;
++ *AddrPtr++ = (bit32u)DataPtr;
++ if (&StatsTable[i].StatPtr[Ch] != 0)
++ {
++ switch(StatsTable[i].DataType)
++ {
++ case 0:
++ HalDev->OsFunc->Sprintf(DataPtr, "%d", (bit32u *)StatsTable[i].StatPtr[Ch]);
++ break;
++ case 1:
++ HalDev->OsFunc->Sprintf(DataPtr, "0x%x", (bit32u *)StatsTable[i].StatPtr[Ch]);
++ break;
++ case 2:
++ HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch * (sizeof(CHANNEL_INFO)/4))));
++ break;
++ case 3:
++ HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
++ break;
++ case 4:
++ HalDev->OsFunc->Sprintf(DataPtr, "0x%x", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
++ break;
++ default:
++ /* invalid data type, due to CPHAL programming error */
++ break;
++ }
++ }
++ else
++ {
++ /* invalid statistics pointer, probably was not initialized */
++ }
++ DataPtr += HalDev->OsFunc->Strlen(DataPtr) + 1;
++ }
++
++ *AddrPtr = (bit32u) 0;
++
++ return (EC_NO_ERRORS);
++ }
++#endif /* +RC 3.02 */
++#endif /* +RC 3.02 */
++
++#ifdef _CPHAL_CPMAC
++static void gpioFunctional(int base, int bit)
++ { /*+RC3.02*/
++ bit32u GpioEnr = base + 0xC;
++ /* To make functional, set to zero */
++ *(volatile bit32u *)(GpioEnr) &= ~(1 << bit); /*+RC3.02*/
++ } /*+RC3.02*/
++
++
++/*+RC3.02*/
++/* Common function, Checks to see if GPIO should be in functional mode */
++static void gpioCheck(HAL_DEVICE *HalDev, void *moduleDeviceInfo)
++ { /*+RC3.02*/
++ int rc;
++ void *DeviceInfo;
++ char *pszMuxBits;
++ char pszMuxBit[20];
++ char *pszTmp;
++ char szMuxBit[20];
++ char *ptr;
++ int base;
++ int reset_bit;
++ int bit;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++
++ rc = OsFunc->DeviceFindParmValue(moduleDeviceInfo, "gpio_mux",&pszTmp);
++ if(rc) return;
++ /* gpio entry found, get GPIO register info and make functional */
++
++ /* temp copy until FinParmValue fixed */
++ ptr = &szMuxBit[0];
++ while ((*ptr++ = *pszTmp++));
++
++ pszMuxBits = &szMuxBit[0];
++
++ rc = OsFunc->DeviceFindInfo(0,"gpio",&DeviceInfo);
++ if(rc) return;
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "base",&base);
++ if(rc) return;
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",&reset_bit);
++ if(rc) return;
++
++ /* If GPIO still in reset, then exit */
++ if((VOLATILE32(HalDev->ResetBase) & (1 << reset_bit)) == 0)
++ return;
++ /* format for gpio_mux is gpio_mux = <int>;<int>;<int>...*/
++ while (*pszMuxBits)
++ {
++ pszTmp = &pszMuxBit[0];
++ if(*pszMuxBits == ';') pszMuxBits++;
++ while ((*pszMuxBits != ';') && (*pszMuxBits != '\0'))
++ {
++ osfuncSioFlush();
++ /*If value not a number, skip */
++ if((*pszMuxBits < '0') || (*pszMuxBits > '9'))
++ pszMuxBits++;
++ else
++ *pszTmp++ = *pszMuxBits++;
++ }
++ *pszTmp = '\0';
++ bit = OsFunc->Strtoul(pszMuxBit, &pszTmp, 10);
++ gpioFunctional(base, bit);
++ resetWait(HalDev); /* not sure if this is needed */
++ }
++ } /*+RC3.02*/
++#endif /* CPMAC */
++
++#ifdef _CPHAL_AAL5
++const char hcSarFrequency[] = "SarFreq";
++#endif
++
++#endif /* _INC */
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpcommon_cpmac.h linux.dev/drivers/net/avalanche_cpmac/cpcommon_cpmac.h
+--- linux.old/drivers/net/avalanche_cpmac/cpcommon_cpmac.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpcommon_cpmac.h 2005-07-12 02:48:41.996601000 +0200
+@@ -0,0 +1,79 @@
++#ifndef _INC_CPCOMMON_H
++#define _INC_CPCOMMON_H
++
++#define VOLATILE32(addr) (*(volatile bit32u *)(addr))
++#ifndef dbgPrintf
++#define dbgPrintf HalDev->OsFunc->Printf
++#endif
++
++#define ChannelUpdate(Field) if(HalChn->Field != 0xFFFFFFFF) HalDev->ChData[Ch].Field = HalChn->Field
++
++#define DBG(level) (HalDev->debug & (1<<(level)))
++/*
++#define DBG0() DBG(0)
++#define DBG1() DBG(1)
++#define DBG2() DBG(2)
++#define DBG3() DBG(3)
++#define DBG4() DBG(4)
++#define DBG5() DBG(5)
++#define DBG6() DBG(6)
++#define DBG7() DBG(7)
++*/
++
++/*
++ * List of defined actions for use with Control().
++ */
++typedef enum
++ {
++ enGET=0, /**< Get the value associated with a key */
++ enSET, /**< Set the value associates with a key */
++ enCLEAR, /**<Clear the value */
++ enNULL /**< No data action, used to initiate a service or send a message */
++ }ACTION;
++
++/*
++ * Enumerated hardware states.
++ */
++typedef enum
++ {
++ enConnected=1, enDevFound, enInitialized, enOpened
++ }DEVICE_STATE;
++
++typedef enum
++ {
++ enCommonStart=0,
++ /* General */
++ enOff, enOn, enDebug,
++ /* Module General */
++ enCpuFreq,
++ enStatus,
++ enCommonEnd
++ }COMMON_KEY;
++
++typedef struct
++ {
++ const char *strKey;
++ int enKey;
++ }CONTROL_KEY;
++
++typedef struct
++ {
++ char *StatName;
++ unsigned int *StatPtr;
++ int DataType; /* 0: int, 1: hex int, 2:channel data */
++ }STATS_TABLE;
++
++typedef struct
++ {
++ int NumberOfStats;
++ STATS_TABLE *StatTable;
++ }STATS_DB;
++
++#define osfuncSioFlush() HalDev->OsFunc->Control(HalDev->OsDev,"SioFlush",pszNULL,0)
++#define osfuncSleep(Ticks) HalDev->OsFunc->Control(HalDev->OsDev,pszSleep,pszNULL,Ticks)
++#define osfuncStateChange() HalDev->OsFunc->Control(HalDev->OsDev,pszStateChange,pszNULL,0)
++
++#define CHANNEL_NAMES {"Ch0","Ch1","Ch2","Ch3","Ch4","Ch5","Ch6","Ch7","Ch8","Ch9","Ch10","Ch11","Ch12","Ch13","Ch14","Ch15"}
++
++#endif
++
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpmac.c linux.dev/drivers/net/avalanche_cpmac/cpmac.c
+--- linux.old/drivers/net/avalanche_cpmac/cpmac.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpmac.c 2005-07-22 01:03:12.609318544 +0200
+@@ -0,0 +1,2504 @@
++/******************************************************************************
++ * FILE PURPOSE: CPMAC Linux Network Device Driver Source
++ ******************************************************************************
++ * FILE NAME: cpmac.c
++ *
++ * DESCRIPTION: CPMAC Network Device Driver Source
++ *
++ * REVISION HISTORY:
++ *
++ * Date Description Author
++ *-----------------------------------------------------------------------------
++ * 27 Nov 2002 Initial Creation Suraj S Iyer
++ * 09 Jun 2003 Updates for GA Suraj S Iyer
++ * 30 Sep 2003 Updates for LED, Reset stats Suraj S Iyer
++ *
++ * (C) Copyright 2003, Texas Instruments, Inc
++ *******************************************************************************/
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/spinlock.h>
++#include <linux/proc_fs.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++
++#include <linux/skbuff.h>
++
++#include <asm/mips-boards/prom.h>
++#include <linux/string.h>
++#include <asm/uaccess.h>
++#include <linux/config.h>
++#include <asm/ar7/if_port.h>
++
++extern void build_psp_config(void);
++extern void psp_config_cleanup(void);
++
++#include "cpmacHalLx.h"
++#include "cpmac.h"
++
++static struct net_device *last_cpmac_device = NULL;
++static int cpmac_devices_installed = 0;
++
++void xdump( u_char* cp, int length, char* prefix );
++
++unsigned int cpmac_cpu_freq = 0;
++
++char cpmac_version[] = "1.5";
++
++char l3_align_array[] = {0x02, 0x01, 0x00, 0x03};
++#define L3_ALIGN(i) l3_align_array[i]
++
++char add_for_4byte_align[] = {0x04, 0x03, 0x02, 0x05};
++#define ADD_FOR_4BYTE_ALIGN(i) add_for_4byte_align[i]
++
++
++#define TPID 0x8100
++#define IS_802_1Q_FRAME(byte_ptr) (*(unsigned short*)byte_ptr == TPID)
++#define TPID_START_OFFSET 12
++#define TCI_START_OFFSET 14
++#define TCI_LENGTH 2
++#define TPID_LENGTH 2
++#define TPID_END_OFFSET (TPID_START_OFFSET + TPID_LENGTH)
++#define TCI_END_OFFSET (TCI_START_OFFSET + TCI_LENGTH)
++#define IS_VALID_VLAN_ID(byte_ptr) ((*(unsigned short*)byte_ptr) && 0xfff != 0)
++#define MAX_CLASSES 8
++#define MAX_USER_PRIORITY 8
++#define CONTROL_802_1Q_SIZE (TCI_LENGTH + TPID_LENGTH)
++
++unsigned char user_priority_to_traffic_class_map[MAX_CLASSES][MAX_USER_PRIORITY] =
++{
++ {0, 0, 0, 1, 1, 1, 1, 2},
++ {0, 0, 0, 0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0, 0, 0, 1},
++ {0, 0, 0, 1, 1, 2, 2, 3},
++ {0, 1, 1, 2, 2, 3, 3, 4},
++ {0, 1, 1, 2, 3, 4, 4, 5},
++ {0, 1, 2, 3, 4, 5, 5, 6},
++ {0, 1, 2, 3, 4, 5, 6, 7}
++};
++
++#define GET_802_1P_CHAN(x,y) user_priority_to_traffic_class_map[x][(y & 0xe0)]
++
++#if defined(CONFIG_MIPS_SEAD2)
++unsigned long temp_base_address[2] = {0xa8610000, 0xa8612800};
++unsigned long temp_reset_value[2] = { 1<< 17,1<<21};
++#define RESET_REG_PRCR (*(volatile unsigned int *)((0xa8611600 + 0x0)))
++#define VERSION(base) (*(volatile unsigned int *)(((base)|0xa0000000) + 0x0))
++#endif
++
++MODULE_AUTHOR("Maintainer: Suraj S Iyer <ssiyer@ti.com>");
++MODULE_DESCRIPTION("Driver for TI CPMAC");
++
++static int cfg_link_speed = 0;
++MODULE_PARM(cfg_link_speed, "i");
++MODULE_PARM_DESC(cfg_link_speed, "Fixed speed of the Link: <100/10>");
++
++static char *cfg_link_mode = NULL;
++MODULE_PARM(cfg_link_mode, "1-3s");
++MODULE_PARM_DESC(cfg_link_mode, "Fixed mode of the Link: <fd/hd>");
++
++int cpmac_debug_mode = 0;
++MODULE_PARM(debug_mode, "i");
++MODULE_PARM_DESC(debug_mode, "Turn on the debug info: <0/1>. Default is 0 (off)");
++
++#define dbgPrint if (cpmac_debug_mode) printk
++#define errPrint printk
++
++static int g_cfg_start_link_params = CFG_START_LINK_SPEED;
++static int g_init_enable_flag = 0;
++static int cfg_start_link_speed;
++static int cpmac_max_frame_size;
++
++static struct net_device *g_dev_array[2];
++static struct proc_dir_entry *gp_stats_file = NULL;
++
++//-----------------------------------------------------------------------------
++// Statistics related private functions.
++//-----------------------------------------------------------------------------
++static int cpmac_p_update_statistics(struct net_device *p_dev, char *buf, int limit, int *len);
++static int cpmac_p_read_rfc2665_stats(char *buf, char **start, off_t offset, int count, int *eof, void *data);
++static int cpmac_p_read_link(char *buf, char **start, off_t offset, int count, int *eof, void *data);
++static int cpmac_p_read_stats(char* buf, char **start, off_t offset, int count, int *eof, void *data);
++static int cpmac_p_write_stats (struct file *fp, const char * buf, unsigned long count, void * data);
++static int cpmac_p_reset_statistics (struct net_device *p_dev);
++static int cpmac_p_get_version(char *buf, char **start, off_t offset, int count, int *eof, void *data);
++
++static int cpmac_p_detect_manual_cfg(int, char*, int);
++static int cpmac_p_process_status_ind(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
++
++//-----------------------------------------------------------------------------
++// Timer related private functions.
++//-----------------------------------------------------------------------------
++static int cpmac_p_timer_init(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
++// static int cpmac_timer_cleanup(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
++static void cpmac_p_tick_timer_expiry(unsigned long p_cb_param);
++inline static int cpmac_p_start_timer(struct timer_list *p_timer, unsigned int delay_ticks);
++static int cpmac_p_stop_timer(struct timer_list *p_timer);
++
++//------------------------------------------------------------------------------
++// Device configuration and setup related private functions.
++//------------------------------------------------------------------------------
++static int cpmac_p_probe_and_setup_device(CPMAC_PRIVATE_INFO_T *p_cpmac_priv, unsigned long *p_dev_flags);
++static int cpmac_p_setup_driver_params(CPMAC_PRIVATE_INFO_T *p_cpmac_priv);
++inline static int cpmac_p_rx_buf_setup(CPMAC_RX_CHAN_INFO_T *p_rx_chan);
++
++//-----------------------------------------------------------------------------
++// Net device related private functions.
++//-----------------------------------------------------------------------------
++static int cpmac_dev_init(struct net_device *p_dev);
++static int cpmac_dev_open( struct net_device *dev );
++static int cpmac_dev_close(struct net_device *p_dev);
++static void cpmac_dev_mcast_set(struct net_device *p_dev);
++static int cpmac_dev_set_mac_addr(struct net_device *p_dev,void * addr);
++static int cpmac_dev_tx( struct sk_buff *skb, struct net_device *p_dev);
++static struct net_device_stats *cpmac_dev_get_net_stats (struct net_device *dev);
++
++static int cpmac_p_dev_enable( struct net_device *p_dev);
++
++
++
++/* Max. Reserved headroom in front of each packet so that the headers can be added to
++ * a packet. Worst case scenario would be PPPoE + 2684 LLC Encapsulation + Ethernet
++ * header. */
++#define MAX_RESERVED_HEADROOM 20
++
++/* This is the MAX size of the static buffer for pure data. */
++#define MAX_SIZE_STATIC_BUFFER 1600
++
++typedef struct DRIVER_BUFFER
++{
++ /* Pointer to the allocated data buffer. This is the static data buffer
++ * allocated for the TI-Cache. 60 bytes out of the below buffer are required
++ * by the SKB shared info. We always reserve at least MAX_RESERVED_HEADROOM bytes
++ * so that the packets always have sufficient headroom. */
++ char ptr_buffer[MAX_SIZE_STATIC_BUFFER + MAX_RESERVED_HEADROOM + 60];
++
++ /* List of the driver buffers. */
++ struct DRIVER_BUFFER* ptr_next;
++}DRIVER_BUFFER;
++
++typedef struct DRIVER_BUFFER_MCB
++{
++ /* List of the driver buffers. */
++ DRIVER_BUFFER* ptr_available_driver_buffers;
++
++ /* The number of available buffers. */
++ int num_available_buffers;
++}DRIVER_BUFFER_MCB;
++
++DRIVER_BUFFER_MCB driver_mcb;
++int hybrid_mode = 0;
++
++static union {
++ struct sk_buff_head list;
++ char pad[SMP_CACHE_BYTES];
++} skb_head_pool[NR_CPUS];
++
++/**************************************************************************
++ * FUNCTION NAME : ti_release_skb
++ **************************************************************************
++ * DESCRIPTION :
++ * This function is called from the ti_alloc_skb when there were no more
++ * data buffers available. The allocated SKB had to released back to the
++ * data pool. The reason why this function was moved from the fast path
++ * below was because '__skb_queue_head' is an inline function which adds
++ * a large code chunk on the fast path.
++ *
++ * NOTES :
++ * This function is called with interrupts disabled.
++ **************************************************************************/
++static void ti_release_skb (struct sk_buff_head* list, struct sk_buff* skb)
++{
++ __skb_queue_head(list, skb);
++ return;
++}
++
++/**************************************************************************
++ * FUNCTION NAME : ti_alloc_skb
++ **************************************************************************
++ * DESCRIPTION :
++ * The function is called to allocate memory from the static allocated
++ * TI-Cached memory pool.
++ *
++ * RETURNS :
++ * Allocated static memory buffer - Success
++ * NULL - Error.
++ **************************************************************************/
++struct sk_buff *ti_alloc_skb(unsigned int size,int gfp_mask)
++{
++ register struct sk_buff* skb;
++ unsigned long flags;
++ struct sk_buff_head* list;
++ DRIVER_BUFFER* ptr_node = NULL;
++
++ /* Critical Section Begin: Lock out interrupts. */
++ local_irq_save(flags);
++
++ /* Get the SKB Pool list associated with the processor and dequeue the head. */
++ list = &skb_head_pool[smp_processor_id()].list;
++ skb = __skb_dequeue(list);
++
++ /* Align the data size. */
++ size = SKB_DATA_ALIGN(size);
++
++ /* Did we get one. */
++ if (skb != NULL)
++ {
++ /* YES. Now get a data block from the head of statically allocated block. */
++ ptr_node = driver_mcb.ptr_available_driver_buffers;
++ if (ptr_node != NULL)
++ {
++ /* YES. Got a data block. Advance the free list pointer to the next available buffer. */
++ driver_mcb.ptr_available_driver_buffers = ptr_node->ptr_next;
++ ptr_node->ptr_next = NULL;
++
++ /* Decrement the number of available data buffers. */
++ driver_mcb.num_available_buffers = driver_mcb.num_available_buffers - 1;
++ }
++ else
++ {
++ /* NO. Was unable to get a data block. So put the SKB back on the free list.
++ * This is slow path. */
++#ifdef DEBUG_SKB
++ printk ("DEBUG: No Buffer memory available: Number of free buffer:%d.\n",
++ driver_mcb.num_available_buffers);
++#endif
++ ti_release_skb (list, skb);
++ }
++ }
++
++ /* Critical Section End: Unlock interrupts. */
++ local_irq_restore(flags);
++
++ /* Did we get an SKB and data buffer. Proceed only if we were succesful in getting both else drop */
++ if (skb != NULL && ptr_node != NULL)
++ {
++ /* XXX: does not include slab overhead */
++ skb->truesize = size + sizeof(struct sk_buff);
++
++ /* Load the data pointers. */
++ skb->head = ptr_node->ptr_buffer;
++ skb->data = ptr_node->ptr_buffer + MAX_RESERVED_HEADROOM;
++ skb->tail = ptr_node->ptr_buffer + MAX_RESERVED_HEADROOM;
++ skb->end = ptr_node->ptr_buffer + size + MAX_RESERVED_HEADROOM;
++
++ /* Set up other state */
++ skb->len = 0;
++ skb->cloned = 0;
++ skb->data_len = 0;
++
++ /* Mark the SKB indicating that the SKB is from the TI cache. */
++ skb->cb[45] = 1;
++
++ atomic_set(&skb->users, 1);
++ atomic_set(&(skb_shinfo(skb)->dataref), 1);
++ skb_shinfo(skb)->nr_frags = 0;
++ skb_shinfo(skb)->frag_list = NULL;
++ return skb;
++ }
++ else
++ {
++ /* Control comes here only when there is no statically allocated data buffers
++ * available. This case is handled using the mode selected
++ *
++ * 1. Hybrid Mode.
++ * In that case lets jump to the old allocation code. This way we
++ * can allocate a small number of data buffers upfront and the rest will hit
++ * this portion of the code, which is slow path. Note the number of hits here
++ * should be kept as low as possible to satisfy performance requirements.
++ *
++ * 2. Pure Static Mode.
++ * Return NULL the user should have tuned the number of static buffers for
++ * worst case scenario. So return NULL and let the drivers handle the error. */
++ if (hybrid_mode == 1)
++ {
++ /* Hybrid Mode: Old allocation. */
++ return dev_alloc_skb(size);
++ }
++ else
++ {
++ /* Pure Static Mode: No buffers available. */
++ return NULL;
++ }
++ }
++}
++
++/**************************************************************************
++ * FUNCTION NAME : ti_skb_release_fragment
++ **************************************************************************
++ * DESCRIPTION :
++ * This function is called to release fragmented packets. This is NOT in
++ * the fast path and this function requires some work.
++ **************************************************************************/
++static void ti_skb_release_fragment(struct sk_buff *skb)
++{
++ if (skb_shinfo(skb)->nr_frags)
++ {
++ /* PANKAJ TODO: This portion has not been tested. */
++ int i;
++#ifdef DEBUG_SKB
++ printk ("DEBUG: Releasing fragments in TI-Cached code.\n");
++#endif
++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
++ printk ("DEBUG: Fragmented Page = 0x%p.\n", skb_shinfo(skb)->frags[i].page);
++ }
++
++ /* Check if there were any fragments present and if so clean all the SKB's.
++ * This is required to recursivly clean the SKB's. */
++ if (skb_shinfo(skb)->frag_list)
++ skb_drop_fraglist(skb);
++
++ return;
++}
++
++/**************************************************************************
++ * FUNCTION NAME : ti_skb_release_data
++ **************************************************************************
++ * DESCRIPTION :
++ * The function is called to release the SKB back into the TI-Cached static
++ * memory pool.
++ **************************************************************************/
++static void ti_skb_release_data(struct sk_buff *skb)
++{
++ DRIVER_BUFFER* ptr_node;
++ unsigned long flags;
++
++ /* The SKB data can be cleaned only if the packet has not been cloned and we
++ * are the only one holding a reference to the data. */
++ if (!skb->cloned || atomic_dec_and_test(&(skb_shinfo(skb)->dataref)))
++ {
++ /* Are there any fragments associated with the SKB ?*/
++ if ((skb_shinfo(skb)->nr_frags != 0) || (skb_shinfo(skb)->frag_list != NULL))
++ {
++ /* Slow Path: Try and clean up the fragments. */
++ ti_skb_release_fragment (skb);
++ }
++
++ /* Cleanup the SKB data memory. This is fast path. */
++ ptr_node = (DRIVER_BUFFER *)skb->head;
++
++ /* Critical Section: Lock out interrupts. */
++ local_irq_save(flags);
++
++ /* Add the data buffer to the list of available buffers. */
++ ptr_node->ptr_next = driver_mcb.ptr_available_driver_buffers;
++ driver_mcb.ptr_available_driver_buffers = ptr_node;
++
++ /* Increment the number of available data buffers. */
++ driver_mcb.num_available_buffers = driver_mcb.num_available_buffers + 1;
++
++ /* Criticial Section: Unlock interrupts. */
++ local_irq_restore(flags);
++ }
++ return;
++}
++
++
++
++
++static unsigned char str2hexnum(unsigned char c)
++{
++ if(c >= '0' && c <= '9')
++ return c - '0';
++ if(c >= 'a' && c <= 'f')
++ return c - 'a' + 10;
++ if(c >= 'A' && c <= 'F')
++ return c - 'A' + 10;
++ return 0;
++}
++
++static void str2eaddr(unsigned char *ea, unsigned char *str)
++{
++ int i;
++ unsigned char num;
++ for(i = 0; i < 6; i++) {
++ if((*str == '.') || (*str == ':'))
++ str++;
++ num = str2hexnum(*str++) << 4;
++ num |= (str2hexnum(*str++));
++ ea[i] = num;
++ }
++}
++
++//-----------------------------------------------------------------------------
++// Statistics related private functions.
++//-----------------------------------------------------------------------------
++static int cpmac_p_update_statistics(struct net_device *p_dev, char *buf, int limit, int *p_len)
++{
++ int ret_val = -1;
++ unsigned long rx_hal_errors = 0;
++ unsigned long rx_hal_discards = 0;
++ unsigned long tx_hal_errors = 0;
++ unsigned long ifOutDiscards = 0;
++ unsigned long ifInDiscards = 0;
++ unsigned long ifOutErrors = 0;
++ unsigned long ifInErrors = 0;
++
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ CPMAC_DEVICE_MIB_T *p_device_mib = p_cpmac_priv->device_mib;
++ CPMAC_DRV_STATS_T *p_stats = p_cpmac_priv->stats;
++ CPMAC_DEVICE_MIB_T local_mib;
++ CPMAC_DEVICE_MIB_T *p_local_mib = &local_mib;
++
++ struct net_device_stats *p_net_dev_stats = &p_cpmac_priv->net_dev_stats;
++
++ int len = 0;
++ int dev_mib_elem_count = 0;
++
++ /* do not access the hardware if it is in the reset state. */
++ if(!test_bit(0, &p_cpmac_priv->set_to_close))
++ {
++ if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "StatsDump", "Get",
++ p_local_mib) != 0)
++ {
++ errPrint("The stats dump for %s is failing.\n", p_dev->name);
++ return(ret_val);
++ }
++
++ p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "StatsClear", "Set", NULL);
++
++ dev_mib_elem_count = sizeof(CPMAC_DEVICE_MIB_T)/sizeof(unsigned long);
++
++ /* Update the history of the stats. This takes care of any reset of the
++ * device and stats that might have taken place during the life time of
++ * the driver.
++ */
++ while(dev_mib_elem_count--)
++ {
++ *((unsigned long*) p_device_mib + dev_mib_elem_count) +=
++ *((unsigned long*) p_local_mib + dev_mib_elem_count);
++ }
++ }
++
++ /* RFC2665, section 3.2.7, page 9 */
++ rx_hal_errors = p_device_mib->ifInFragments +
++ p_device_mib->ifInCRCErrors +
++ p_device_mib->ifInAlignCodeErrors +
++ p_device_mib->ifInJabberFrames;
++
++ /* RFC2233 */
++ rx_hal_discards = p_device_mib->ifRxDMAOverruns;
++
++ /* RFC2665, section 3.2.7, page 9 */
++ tx_hal_errors = p_device_mib->ifExcessiveCollisionFrames +
++ p_device_mib->ifLateCollisions +
++ p_device_mib->ifCarrierSenseErrors +
++ p_device_mib->ifOutUnderrun;
++
++ /* if not set, the short frames (< 64 bytes) are considered as errors */
++ if(!p_cpmac_priv->flags & IFF_PRIV_SHORT_FRAMES)
++ rx_hal_errors += p_device_mib->ifInUndersizedFrames;
++
++ /* if not set, the long frames ( > 1518) are considered as errors
++ * RFC2665, section 3.2.7, page 9. */
++ if(!p_cpmac_priv->flags & IFF_PRIV_JUMBO_FRAMES)
++ rx_hal_errors += p_device_mib->ifInOversizedFrames;
++
++ /* if not in promiscous, then non addr matching frames are discarded */
++ /* CPMAC 2.0 Manual Section 2.8.1.14 */
++ if(!p_dev->flags & IFF_PROMISC)
++ {
++ ifInDiscards += p_device_mib->ifInFilteredFrames;
++ }
++
++ /* total rx discards = hal discards + driver discards. */
++ ifInDiscards = rx_hal_discards + p_net_dev_stats->rx_dropped;
++ ifInErrors = rx_hal_errors;
++
++ ifOutErrors = tx_hal_errors;
++ ifOutDiscards = p_net_dev_stats->tx_dropped;
++
++ /* Let us update the net device stats struct. To be updated in the later releases.*/
++ p_cpmac_priv->net_dev_stats.rx_errors = ifInErrors;
++ p_cpmac_priv->net_dev_stats.collisions = p_device_mib->ifCollisionFrames;
++
++ if(buf == NULL || limit == 0)
++ {
++ return(0);
++ }
++
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %ld\n", "ifSpeed", (long)p_cpmac_priv->link_speed);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "dot3StatsDuplexStatus", (long)p_cpmac_priv->link_mode);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifAdminStatus", (long)(p_dev->flags & IFF_UP ? 1:2));
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifOperStatus", (long)(((p_dev->flags & IFF_UP) && netif_carrier_ok(p_dev)) ? 1:2));
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifLastChange", p_stats->start_tick);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInDiscards", ifInDiscards);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInErrors", ifInErrors);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutDiscards", ifOutDiscards);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutErrors", ifOutErrors);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInGoodFrames", p_device_mib->ifInGoodFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInBroadcasts", p_device_mib->ifInBroadcasts);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInMulticasts", p_device_mib->ifInMulticasts);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInPauseFrames", p_device_mib->ifInPauseFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInCRCErrors", p_device_mib->ifInCRCErrors);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInAlignCodeErrors", p_device_mib->ifInAlignCodeErrors);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInOversizedFrames", p_device_mib->ifInOversizedFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInJabberFrames", p_device_mib->ifInJabberFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInUndersizedFrames", p_device_mib->ifInUndersizedFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInFragments", p_device_mib->ifInFragments);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInFilteredFrames", p_device_mib->ifInFilteredFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInQosFilteredFrames", p_device_mib->ifInQosFilteredFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifInOctets", p_device_mib->ifInOctets);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutGoodFrames", p_device_mib->ifOutGoodFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutBroadcasts", p_device_mib->ifOutBroadcasts);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutMulticasts", p_device_mib->ifOutMulticasts);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutPauseFrames", p_device_mib->ifOutPauseFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifDeferredTransmissions", p_device_mib->ifDeferredTransmissions);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifCollisionFrames", p_device_mib->ifCollisionFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifSingleCollisionFrames", p_device_mib->ifSingleCollisionFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifMultipleCollisionFrames", p_device_mib->ifMultipleCollisionFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifExcessiveCollisionFrames", p_device_mib->ifExcessiveCollisionFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifLateCollisions", p_device_mib->ifLateCollisions);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutUnderrun", p_device_mib->ifOutUnderrun);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifCarrierSenseErrors", p_device_mib->ifCarrierSenseErrors);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifOutOctets", p_device_mib->ifOutOctets);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "if64OctetFrames", p_device_mib->if64OctetFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "if65To127POctetFrames", p_device_mib->if65To127OctetFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "if128To255OctetFrames", p_device_mib->if128To255OctetFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "if256To511OctetFrames", p_device_mib->if256To511OctetFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "if512To1023OctetFrames", p_device_mib->if512To1023OctetFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "if1024ToUpOctetFrames", p_device_mib->if1024ToUPOctetFrames);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifNetOctets", p_device_mib->ifNetOctets);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifRxSofOverruns", p_device_mib->ifRxSofOverruns);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifRxMofOverruns", p_device_mib->ifRxMofOverruns);
++ if(len <= limit)
++ len+= sprintf(buf + len, "%-35s: %lu\n", "ifRxDMAOverruns", p_device_mib->ifRxDMAOverruns);
++
++ *p_len = len;
++
++ return(0);
++}
++
++
++static int cpmac_p_read_rfc2665_stats(char* buf, char **start, off_t offset,
++ int count, int *eof, void *data)
++{
++ int limit = count - 80;
++ int len = 0;
++ struct net_device *p_dev = (struct net_device*)data;
++
++ cpmac_p_update_statistics(p_dev, buf, limit, &len);
++
++ *eof = 1;
++
++ return len;
++}
++
++static int cpmac_p_read_link(char *buf, char **start, off_t offset, int count,
++ int *eof, void *data)
++{
++ int len = 0;
++
++ struct net_device *p_dev;
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
++ struct net_device *cpmac_dev_list[cpmac_devices_installed];
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal;
++
++ int i;
++ int phy; /* what phy are we using? */
++
++ len += sprintf(buf+len, "CPMAC devices = %d\n",cpmac_devices_installed);
++
++ p_dev = last_cpmac_device;
++
++ /* Reverse the the device link list to list eth0,eth1...in correct order */
++ for(i=0; i< cpmac_devices_installed; i++)
++ {
++ cpmac_dev_list[cpmac_devices_installed -(i+1)] = p_dev;
++ p_cpmac_priv = p_dev->priv;
++ p_dev = p_cpmac_priv->next_device;
++ }
++
++ for(i=0; i< cpmac_devices_installed; i++)
++ {
++ p_dev = cpmac_dev_list[i];
++ p_cpmac_priv = p_dev->priv;
++ p_drv_hal = p_cpmac_priv->drv_hal;
++
++ /* This prints them out from high to low because of how the devices are linked */
++ if(netif_carrier_ok(p_dev))
++ {
++ p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "PhyNum", "Get", &phy);
++
++
++ len += sprintf(buf+len,"eth%d: Link State: %s Phy:0x%x, Speed = %s, Duplex = %s\n",
++ p_cpmac_priv->instance_num, "UP", phy,
++ (p_cpmac_priv->link_speed == 100000000) ? "100":"10",
++ (p_cpmac_priv->link_mode == 2) ? "Half":"Full");
++
++ }
++ else
++ len += sprintf(buf+len,"eth%d: Link State: DOWN\n",p_cpmac_priv->instance_num);
++
++ p_dev = p_cpmac_priv->next_device;
++ }
++
++ return len;
++
++}
++
++static int cpmac_p_read_stats(char* buf, char **start, off_t offset, int count,
++ int *eof, void *data)
++{
++ struct net_device *p_dev = last_cpmac_device;
++ int len = 0;
++ int limit = count - 80;
++ int i;
++ struct net_device *cpmac_dev_list[cpmac_devices_installed];
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
++ CPMAC_DEVICE_MIB_T *p_device_mib;
++
++ /* Reverse the the device link list to list eth0,eth1...in correct order */
++ for(i=0; i< cpmac_devices_installed; i++)
++ {
++ cpmac_dev_list[cpmac_devices_installed - (i+1)] = p_dev;
++ p_cpmac_priv = p_dev->priv;
++ p_dev = p_cpmac_priv->next_device;
++ }
++
++ for(i=0; i< cpmac_devices_installed; i++)
++ {
++ p_dev = cpmac_dev_list[i];
++
++ if(!p_dev)
++ goto proc_error;
++
++ /* Get Stats */
++ cpmac_p_update_statistics(p_dev, NULL, 0, NULL);
++
++ p_cpmac_priv = p_dev->priv;
++ p_device_mib = p_cpmac_priv->device_mib;
++
++ /* Transmit stats */
++ if(len<=limit)
++ len+= sprintf(buf+len, "\nCpmac %d, Address %lx\n",i+1, p_dev->base_addr);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Transmit Stats\n");
++ if(len<=limit)
++ len+= sprintf(buf+len, " Tx Valid Bytes Sent :%lu\n",p_device_mib->ifOutOctets);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Good Tx Frames (Hardware) :%lu\n",p_device_mib->ifOutGoodFrames);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Good Tx Frames (Software) :%lu\n",p_cpmac_priv->net_dev_stats.tx_packets);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Good Tx Broadcast Frames :%lu\n",p_device_mib->ifOutBroadcasts);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Good Tx Multicast Frames :%lu\n",p_device_mib->ifOutMulticasts);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Pause Frames Sent :%lu\n",p_device_mib->ifOutPauseFrames);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Collisions :%lu\n",p_device_mib->ifCollisionFrames);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Tx Error Frames :%lu\n",p_cpmac_priv->net_dev_stats.tx_errors);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Carrier Sense Errors :%lu\n",p_device_mib->ifCarrierSenseErrors);
++ if(len<=limit)
++ len+= sprintf(buf+len, "\n");
++
++
++ /* Receive Stats */
++ if(len<=limit)
++ len+= sprintf(buf+len, "\nCpmac %d, Address %lx\n",i+1,p_dev->base_addr);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Receive Stats\n");
++ if(len<=limit)
++ len+= sprintf(buf+len, " Rx Valid Bytes Received :%lu\n",p_device_mib->ifInOctets);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Good Rx Frames (Hardware) :%lu\n",p_device_mib->ifInGoodFrames);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Good Rx Frames (Software) :%lu\n",p_cpmac_priv->net_dev_stats.rx_packets);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Good Rx Broadcast Frames :%lu\n",p_device_mib->ifInBroadcasts);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Good Rx Multicast Frames :%lu\n",p_device_mib->ifInMulticasts);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Pause Frames Received :%lu\n",p_device_mib->ifInPauseFrames);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Rx CRC Errors :%lu\n",p_device_mib->ifInCRCErrors);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Rx Align/Code Errors :%lu\n",p_device_mib->ifInAlignCodeErrors);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Rx Jabbers :%lu\n",p_device_mib->ifInOversizedFrames);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Rx Filtered Frames :%lu\n",p_device_mib->ifInFilteredFrames);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Rx Fragments :%lu\n",p_device_mib->ifInFragments);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Rx Undersized Frames :%lu\n",p_device_mib->ifInUndersizedFrames);
++ if(len<=limit)
++ len+= sprintf(buf+len, " Rx Overruns :%lu\n",p_device_mib->ifRxDMAOverruns);
++ }
++
++
++ return len;
++
++ proc_error:
++ *eof=1;
++ return len;
++}
++
++static int cpmac_p_write_stats (struct file *fp, const char * buf, unsigned long count, void * data)
++{
++ char local_buf[31];
++ int ret_val = 0;
++
++ if(count > 30)
++ {
++ printk("Error : Buffer Overflow\n");
++ printk("Use \"echo 0 > cpmac_stat\" to reset the statistics\n");
++ return -EFAULT;
++ }
++
++ copy_from_user(local_buf,buf,count);
++ local_buf[count-1]='\0'; /* Ignoring last \n char */
++ ret_val = count;
++
++ if(strcmp("0",local_buf)==0)
++ {
++ struct net_device *p_dev = last_cpmac_device;
++ int i;
++ struct net_device *cpmac_dev_list[cpmac_devices_installed];
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
++
++ /* Valid command */
++ printk("Resetting statistics for CPMAC interface.\n");
++
++ /* Reverse the the device link list to list eth0,eth1...in correct order */
++ for(i=0; i< cpmac_devices_installed; i++)
++ {
++ cpmac_dev_list[cpmac_devices_installed - (i+1)] = p_dev;
++ p_cpmac_priv = p_dev->priv;
++ p_dev = p_cpmac_priv->next_device;
++ }
++
++ for(i=0; i< cpmac_devices_installed; i++)
++ {
++ p_dev = cpmac_dev_list[i];
++ if(!p_dev)
++ {
++ ret_val = -EFAULT;
++ break;
++ }
++
++ cpmac_p_reset_statistics(p_dev);
++ }
++ }
++ else
++ {
++ printk("Error: Unknown operation on cpmac statistics\n");
++ printk("Use \"echo 0 > cpmac_stats\" to reset the statistics\n");
++ return -EFAULT;
++ }
++
++ return ret_val;
++}
++
++static int cpmac_p_reset_statistics(struct net_device *p_dev)
++{
++ int ret_val = 0;
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++
++ memset(p_cpmac_priv->device_mib, 0, sizeof(CPMAC_DEVICE_MIB_T));
++ memset(p_cpmac_priv->stats, 0, sizeof(CPMAC_DRV_STATS_T));
++ memset(&p_cpmac_priv->net_dev_stats, 0, sizeof(struct net_device_stats));
++
++ p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "StatsClear", "Set", NULL);
++
++ return(ret_val);
++}
++
++static int cpmac_p_get_version(char* buf, char **start, off_t offset, int count,int *eof, void *data)
++{
++ int len = 0;
++ int limit = count - 80;
++ char *hal_version = NULL;
++ struct net_device *p_dev = last_cpmac_device;
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++
++ p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "Version", "Get", &hal_version);
++
++ len += sprintf(buf+len, "Texas Instruments CPMAC driver version: %s\n", cpmac_version);
++
++ if(len <= limit && hal_version)
++ len += sprintf(buf+len, "Texas Instruments CPMAC HAL version: %s\n", hal_version);
++
++ return len;
++}
++
++static struct net_device_stats *cpmac_dev_get_net_stats (struct net_device *p_dev)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = (CPMAC_PRIVATE_INFO_T *) p_dev->priv;
++
++ cpmac_p_update_statistics(p_dev, NULL, 0, NULL);
++
++ return &p_cpmac_priv->net_dev_stats;
++}
++
++static int cpmac_p_detect_manual_cfg(int link_speed, char* link_mode, int debug)
++{
++ char *pSpeed = NULL;
++
++ if(debug == 1)
++ {
++ cpmac_debug_mode = 1;
++ dbgPrint("Enabled the debug print.\n");
++ }
++
++ if(!link_speed && !link_mode)
++ {
++ dbgPrint("No manual link params, defaulting to auto negotiation.\n");
++ return (0);
++ }
++
++ if(!link_speed || (link_speed != 10 && link_speed != 100))
++ {
++ dbgPrint("Invalid or No value of link speed specified, defaulting to auto speed.\n");
++ pSpeed = "auto";
++ }
++ else if(link_speed == 10)
++ {
++ g_cfg_start_link_params &= ~(_CPMDIO_100);
++ pSpeed = "10 Mbps";
++ }
++ else
++ {
++ g_cfg_start_link_params &= ~(_CPMDIO_10);
++ pSpeed = "100 Mbps";
++ }
++
++ if(!link_mode || (!strcmp(link_mode, "fd") && !strcmp(link_mode, "hd")))
++ {
++ dbgPrint("Invalid or No value of link mode specified, defaulting to auto mode.\n");
++ }
++ else if(!strcmp(link_mode, "hd"))
++ {
++ g_cfg_start_link_params &= ~(_CPMDIO_FD);
++ }
++ else
++ {
++ g_cfg_start_link_params &= ~(_CPMDIO_HD);
++ }
++
++ dbgPrint("Link is manually set to the speed of %s speed and %s mode.\n",
++ pSpeed, link_mode ? link_mode : "auto");
++
++ return(0);
++}
++
++//------------------------------------------------------------------------------
++// Call back from the HAL.
++//------------------------------------------------------------------------------
++static int cpmac_p_process_status_ind(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
++{
++ struct net_device *p_dev = p_cpmac_priv->owner;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ int status;
++
++ p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "Status", "Get", &status);
++
++ /* We do not reflect the real link status if in loopback.
++ * After all, we want the packets to reach the hardware so
++ * that Send() should work. */
++ if(p_dev->flags & IFF_LOOPBACK)
++ {
++ dbgPrint("Maintaining the link up loopback for %s.\n", p_dev->name);
++ netif_carrier_on(p_dev);
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_ON);
++//#endif
++
++ return(0);
++ }
++
++ if(status & CPMAC_STATUS_ADAPTER_CHECK) /* ???? */
++ {
++ ; /* what to do ? */
++ }
++ else if(status)
++ {
++ if(!netif_carrier_ok(p_dev))
++ {
++ netif_carrier_on(p_cpmac_priv->owner);
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_ON);
++//#endif
++ dbgPrint("Found the Link for the CPMAC instance %s.\n", p_dev->name);
++ }
++
++ if(netif_running(p_dev) & netif_queue_stopped(p_dev))
++ {
++ netif_wake_queue(p_dev);
++ }
++
++ p_cpmac_priv->link_speed = status & CPMAC_STATUS_LINK_SPEED ? 100000000:10000000;
++ p_cpmac_priv->link_mode = status & CPMAC_STATUS_LINK_DUPLEX? 3:2;
++
++ }
++ else
++ {
++ if(netif_carrier_ok(p_dev))
++ {
++ /* do we need to register synchronization issues with stats here. */
++ p_cpmac_priv->link_speed = 100000000;
++ p_cpmac_priv->link_mode = 1;
++
++ netif_carrier_off(p_dev);
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_OFF);
++//#endif
++
++ dbgPrint("Lost the Link for the CPMAC for %s.\n", p_dev->name);
++ }
++
++ if(!netif_queue_stopped(p_dev))
++ {
++ netif_stop_queue(p_dev); /* So that kernel does not keep on xmiting pkts. */
++ }
++ }
++
++ return(0);
++}
++
++//-----------------------------------------------------------------------------
++// Timer related private functions.
++//-----------------------------------------------------------------------------
++static int cpmac_p_timer_init(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
++{
++ struct timer_list *p_timer = p_cpmac_priv->timer;
++
++ init_timer(p_timer);
++
++ p_timer = p_cpmac_priv->timer + TICK_TIMER;
++ p_timer->expires = 0;
++ p_timer->data = (unsigned long)p_cpmac_priv;
++ p_timer->function = cpmac_p_tick_timer_expiry;
++
++ return(0);
++}
++
++#if 0
++static int cpmac_timer_cleanup(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
++{
++ struct timer_list *p_timer;
++
++ p_timer = p_cpmac_priv->timer + TICK_TIMER;
++
++ /* use spin lock to establish synchronization with the dispatch */
++ if(p_timer->function) del_timer_sync(p_timer);
++ p_timer->function = NULL;
++
++ return (0);
++}
++#endif
++
++static int cpmac_p_start_timer(struct timer_list *p_timer, unsigned int delay_ticks)
++{
++ p_timer->expires = jiffies + delay_ticks;
++
++ if(p_timer->function)
++ {
++ add_timer(p_timer);
++ }
++
++ return(0);
++}
++
++static void cpmac_p_tick_timer_expiry(unsigned long p_cb_param)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = (CPMAC_PRIVATE_INFO_T*) p_cb_param;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ struct timer_list *p_timer = p_cpmac_priv->timer + TICK_TIMER;
++
++ if(test_bit(0, &p_cpmac_priv->set_to_close))
++ {
++ return;
++ }
++
++ p_drv_hal->hal_funcs->Tick(p_drv_hal->hal_dev);
++
++ cpmac_p_start_timer(p_timer, p_cpmac_priv->delay_ticks);
++}
++
++static int cpmac_p_stop_timer(struct timer_list *p_timer)
++{
++ /* Ideally we need to a set flag indicating not to start the timer again
++ before del_timer_sync() is called up. But here we assume that the
++ caller has set the p_cpmac_priv->set_to_close (ok for now). */
++ del_timer_sync(p_timer);
++
++ return(0);
++}
++
++//------------------------------------------------------------------------------
++// Device configuration and setup related private functions.
++//------------------------------------------------------------------------------
++static int cpmac_p_probe_and_setup_device(CPMAC_PRIVATE_INFO_T *p_cpmac_priv,
++ unsigned long *p_dev_flags)
++{
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
++ HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
++ CPMAC_ABILITY_INFO_T *p_capability= p_cpmac_priv->ability_info;
++ unsigned int val = 0;
++ int channel = 0;
++
++ p_cpmac_priv->flags = 0;
++
++ p_capability->promiscous = CFG_PROMISCOUS;
++ p_capability->broadcast = CFG_BROADCAST;
++ p_capability->multicast = CFG_MULTICAST;
++ p_capability->all_multi = CFG_ALL_MULTI;
++ p_capability->jumbo_frames = CFG_JUMBO_FRAMES;
++ p_capability->short_frames = CFG_SHORT_FRAMES;
++ p_capability->auto_negotiation = CFG_AUTO_NEGOTIATION;
++ p_capability->link_speed = cfg_start_link_speed;
++ p_capability->loop_back = CFG_LOOP_BACK;
++ p_capability->tx_flow_control = CFG_TX_FLOW_CNTL;
++ p_capability->rx_flow_control = CFG_RX_FLOW_CNTL;
++ p_capability->tx_pacing = CFG_TX_PACING;
++ p_capability->rx_pass_crc = CFG_RX_PASS_CRC;
++ p_capability->qos_802_1q = CFG_QOS_802_1Q;
++ p_capability->tx_num_chan = CFG_TX_NUM_CHAN;
++
++ /* Lets probe the device for the configured capabilities (netdev specific).*/
++
++ /* Following are set in the set_multi_list, when indicated by the kernel
++ * Promiscous and all multi.
++ */
++
++ if(p_capability->broadcast)
++ {
++ channel = 0;
++ val = 1;
++ if((p_hal_funcs->Control(p_hal_dev, pszRX_BROAD_EN, pszSet, &val) == 0) &&
++ (p_hal_funcs->Control(p_hal_dev, pszRX_BROAD_CH, pszSet, &channel) == 0))
++ *p_dev_flags |= IFF_BROADCAST;
++ else
++ p_capability->broadcast = 0; /* no broadcast capabilities */
++ }
++
++ if(p_capability->multicast)
++ {
++ val = 1;
++ channel = 0;
++ if((p_hal_funcs->Control(p_hal_dev, pszRX_MULT_EN, pszSet, &val) == 0) &&
++ (p_hal_funcs->Control(p_hal_dev, pszRX_MULT_CH, pszSet, &channel) == 0))
++ *p_dev_flags |= IFF_MULTICAST;
++ else
++ {
++ p_capability->multicast = 0;
++ p_capability->all_multi = 0; /* no multicast, no all-multi. */
++ }
++ }
++
++ if(p_capability->loop_back)
++ {
++ ; /* We do not put the device in loopback, if required use ioctl */
++ }
++
++ /* Lets probe the device for the configured capabilities (Non net device specific).*/
++
++ if(p_capability->jumbo_frames)
++ {
++ val = 0;
++ if(p_hal_funcs->Control(p_hal_dev, pszRX_NO_CHAIN, pszSet, &val) == 0)
++ p_cpmac_priv->flags |= IFF_PRIV_JUMBO_FRAMES;
++ else
++ p_capability->jumbo_frames = 0;
++ }
++
++ if(p_capability->short_frames)
++ {
++ val = 1;
++ if(p_hal_funcs->Control(p_hal_dev, pszRX_CSF_EN, pszSet, &val) == 0)
++ p_cpmac_priv->flags |= IFF_PRIV_SHORT_FRAMES;
++ else
++ p_capability->short_frames = 0;
++ }
++
++ val = g_cfg_start_link_params;
++
++#ifdef CONFIG_AR7_MDIX
++ if( avalanche_is_mdix_on_chip() )
++ {
++ val |= _CPMDIO_AUTOMDIX;
++ }
++#endif
++
++ if(p_hal_funcs->Control(p_hal_dev,pszMdioConnect,pszSet, &val) !=0)
++ {
++ p_capability->link_speed = 0;
++ }
++ else
++ {
++ if(g_cfg_start_link_params & (_CPMDIO_100 | _CPMDIO_HD | _CPMDIO_FD | _CPMDIO_10))
++ p_cpmac_priv->flags |= IFF_PRIV_AUTOSPEED;
++ else if(g_cfg_start_link_params & (_CPMDIO_100 | _CPMDIO_HD))
++ p_cpmac_priv->flags |= IFF_PRIV_LINK100_HD;
++ else if(g_cfg_start_link_params & (_CPMDIO_100 | _CPMDIO_FD))
++ p_cpmac_priv->flags |= IFF_PRIV_LINK100_FD;
++ else if(g_cfg_start_link_params & (_CPMDIO_10 | _CPMDIO_HD))
++ p_cpmac_priv->flags |= IFF_PRIV_LINK10_HD;
++ else if(g_cfg_start_link_params & (_CPMDIO_10 | _CPMDIO_FD))
++ p_cpmac_priv->flags |= IFF_PRIV_LINK10_FD;
++ else
++ ;
++ }
++
++ if(p_capability->tx_flow_control)
++ {
++ val = 1;
++ if(p_hal_funcs->Control(p_hal_dev,pszTX_FLOW_EN, pszSet, &val) ==0)
++ p_cpmac_priv->flags |= IFF_PRIV_TX_FLOW_CNTL;
++ else
++ p_capability->tx_flow_control = 0;
++ }
++
++ if(p_capability->rx_flow_control)
++ {
++ val = 1;
++ if(p_hal_funcs->Control(p_hal_dev, pszRX_FLOW_EN, pszSet, &val) ==0)
++ p_cpmac_priv->flags |= IFF_PRIV_RX_FLOW_CNTL;
++ else
++ p_capability->rx_flow_control = 0;
++ }
++
++ if(p_capability->tx_pacing)
++ {
++ val = 1;
++ if(p_hal_funcs->Control(p_hal_dev, pszTX_PACE, pszSet, &val) ==0)
++ p_cpmac_priv->flags |= IFF_PRIV_TX_PACING;
++ else
++ p_capability->tx_pacing = 0;
++ }
++
++ if(p_capability->rx_pass_crc)
++ {
++ val = 1;
++ if(p_hal_funcs->Control(p_hal_dev, pszRX_PASS_CRC, pszSet, &val) == 0)
++ p_cpmac_priv->flags |= IFF_PRIV_RX_PASS_CRC;
++ else
++ p_capability->rx_pass_crc = 0;
++ }
++
++ if(p_capability->qos_802_1q)
++ {
++ val = 1;
++ if(p_hal_funcs->Control(p_hal_dev, pszRX_QOS_EN, pszSet, &val) == 0)
++ p_cpmac_priv->flags |= IFF_PRIV_8021Q_EN;
++ else
++ {
++ p_capability->qos_802_1q = 0;
++ p_capability->tx_num_chan= 1;
++ }
++ }
++
++ if(p_capability->tx_num_chan > 1)
++ {
++ int cfg_tx_num_chan = p_capability->tx_num_chan;
++ val = 0;
++#ifdef TEST
++ if(p_hal_funcs->Control(p_hal_dev, pszTX_NUM_CH, pszGet, &val) == 0)
++ cfg_tx_num_chan = cfg_tx_num_chan > val ? val : cfg_tx_num_chan;
++ else
++ cfg_tx_num_chan = 1;
++#endif
++ p_capability->tx_num_chan = cfg_tx_num_chan;
++ }
++
++ return(0);
++}
++
++static int cpmac_p_setup_driver_params(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
++{
++ int i=0;
++ int threshold = CFG_TX_NUM_BUF_SERVICE;
++
++ char *tx_threshold_ptr = prom_getenv("threshold");
++
++ CPMAC_TX_CHAN_INFO_T *p_tx_chan_info = p_cpmac_priv->tx_chan_info;
++ CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = p_cpmac_priv->rx_chan_info;
++ CPMAC_ABILITY_INFO_T *p_capability = p_cpmac_priv->ability_info;
++
++ /* Timer stuff */
++ p_cpmac_priv->timer_count = 1; /* should be < or = the MAX TIMER */
++ p_cpmac_priv->timer_created = 0;
++ p_cpmac_priv->timer_access_hal = 1;
++
++ for(i=0; i < MAX_TIMER; i++)
++ p_cpmac_priv->timer[i].function = NULL;
++
++ p_cpmac_priv->enable_802_1q = p_capability->qos_802_1q;
++
++ /* Tx channel related.*/
++ p_tx_chan_info->cfg_chan = p_capability->tx_num_chan;
++ p_tx_chan_info->opened_chan = 0;
++
++ if(tx_threshold_ptr)
++ threshold = simple_strtol(tx_threshold_ptr, (char **)NULL, 10);
++
++ if((threshold <= 0) && tx_threshold_ptr) /* If threshold set to 0 then Enable the TX interrupt */
++ {
++ threshold = CFG_TX_NUM_BUF_SERVICE;
++ p_tx_chan_info->tx_int_disable = 0;
++
++ }
++ else
++ {
++ p_tx_chan_info->tx_int_disable = CFG_TX_INT_DISABLE;
++ }
++
++ for(i=0; i < MAX_TX_CHAN; i++)
++ {
++
++
++
++ p_tx_chan_info->chan[i].state = CHAN_CLOSE;
++ p_tx_chan_info->chan[i].num_BD = CFG_TX_NUM_BUF_DESC;
++ p_tx_chan_info->chan[i].buffer_size = cpmac_max_frame_size;
++ p_tx_chan_info->chan[i].buffer_offset = CFG_TX_BUF_OFFSET;
++
++
++
++ p_tx_chan_info->chan[i].service_max = threshold;
++ }
++
++ if (p_tx_chan_info->tx_int_disable)
++ printk("Cpmac driver Disable TX complete interrupt setting threshold to %d.\n",threshold);
++ else
++ printk("Cpmac driver Enable TX complete interrupt\n");
++
++
++ /* Assuming just one rx channel for now */
++ p_rx_chan_info->cfg_chan = 1;
++ p_rx_chan_info->opened_chan = 0;
++ p_rx_chan_info->chan->state = CHAN_CLOSE;
++ p_rx_chan_info->chan->num_BD = CFG_RX_NUM_BUF_DESC;
++ p_rx_chan_info->chan->buffer_size = cpmac_max_frame_size;
++ p_rx_chan_info->chan->buffer_offset = CFG_RX_BUF_OFFSET;
++ p_rx_chan_info->chan->service_max = CFG_RX_NUM_BUF_SERVICE;
++
++ /* Set as per RFC 2665 */
++ p_cpmac_priv->link_speed = 100000000;
++ p_cpmac_priv->link_mode = 1;
++
++ p_cpmac_priv->loop_back = 0;
++
++ return(0);
++}
++
++inline static int cpmac_p_rx_buf_setup(CPMAC_RX_CHAN_INFO_T *p_rx_chan)
++{
++ /* Number of ethernet packets & max pkt length */
++ p_rx_chan->chan->tot_buf_size = p_rx_chan->chan->buffer_size +
++ 2*(CONTROL_802_1Q_SIZE) +
++ p_rx_chan->chan->buffer_offset +
++ ADD_FOR_4BYTE_ALIGN(p_rx_chan->chan->buffer_offset & 0x3);
++
++ p_rx_chan->chan->tot_reserve_bytes = CONTROL_802_1Q_SIZE +
++ p_rx_chan->chan->buffer_offset +
++ L3_ALIGN(p_rx_chan->chan->buffer_offset & 0x3);
++
++ return(0);
++}
++
++//-----------------------------------------------------------------------------
++// Net device related private functions.
++//-----------------------------------------------------------------------------
++
++/***************************************************************
++ * cpmac_dev_init
++ *
++ * Returns:
++ * 0 on success, error code otherwise.
++ * Parms:
++ * dev The structure of the device to be
++ * init'ed.
++ *
++ * This function completes the initialization of the
++ * device structure and driver. It reserves the IO
++ * addresses and assignes the device's methods.
++ *
++ *
++ **************************************************************/
++
++static int cpmac_dev_init(struct net_device *p_dev)
++{
++ int retVal = -1;
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ int instance_num = p_cpmac_priv->instance_num;
++ unsigned long net_flags = 0;
++ char *mac_name = NULL;
++ char *mac_string = NULL;
++
++ CPMAC_TX_CHAN_INFO_T *p_tx_chan_info;
++ CPMAC_RX_CHAN_INFO_T *p_rx_chan_info;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal;
++ int i;
++
++ int mem_size = sizeof(CPMAC_DRV_HAL_INFO_T)
++ + sizeof(CPMAC_TX_CHAN_INFO_T)
++ + sizeof(CPMAC_RX_CHAN_INFO_T)
++ + sizeof(CPMAC_ABILITY_INFO_T)
++ + sizeof(CPMAC_DEVICE_MIB_T)
++ + sizeof(CPMAC_DRV_STATS_T);
++
++
++#if defined(CONFIG_MIPS_SEAD2)
++ int prev_reset_val = RESET_REG_PRCR;
++ /* Bring the module out of reset */
++ RESET_REG_PRCR |= temp_reset_value[p_cpmac_priv->instance_num];
++
++ /* Read the version id of the device to check if the device really exists */
++ if( VERSION(temp_base_address[p_cpmac_priv->instance_num]) == 0)
++ {
++ printk(" CPMAC:Device not found\n");
++ RESET_REG_PRCR = prev_reset_val;
++ return -ENODEV;
++ }
++
++ RESET_REG_PRCR = prev_reset_val;
++#endif
++
++
++ if((p_drv_hal = kmalloc(mem_size, GFP_KERNEL)) == NULL)
++ {
++ errPrint("Failed to allocate memory; rewinding.\n");
++ return(-1);
++ }
++
++ memset(p_drv_hal, 0, mem_size);
++
++ /* build the cpmac private object */
++ p_cpmac_priv->drv_hal = p_drv_hal;
++ p_cpmac_priv->tx_chan_info = p_tx_chan_info
++ = (CPMAC_TX_CHAN_INFO_T*)((char*)p_drv_hal
++ + sizeof(CPMAC_DRV_HAL_INFO_T));
++ p_cpmac_priv->rx_chan_info = p_rx_chan_info
++ = (CPMAC_RX_CHAN_INFO_T*)((char *)p_tx_chan_info
++ + sizeof(CPMAC_TX_CHAN_INFO_T));
++ p_cpmac_priv->ability_info = (CPMAC_ABILITY_INFO_T *)((char *)p_rx_chan_info
++ + sizeof(CPMAC_RX_CHAN_INFO_T));
++ p_cpmac_priv->device_mib = (CPMAC_DEVICE_MIB_T *)((char *)p_cpmac_priv->ability_info
++ + sizeof(CPMAC_ABILITY_INFO_T));
++ p_cpmac_priv->stats = (CPMAC_DRV_STATS_T *)((char *)p_cpmac_priv->device_mib
++ + sizeof(CPMAC_DEVICE_MIB_T));
++
++ p_drv_hal->owner = p_cpmac_priv;
++
++
++ switch(instance_num)
++ {
++
++ case 0:
++ mac_name="maca";
++
++ /* Also setting port information */
++ p_dev->if_port = AVALANCHE_CPMAC_LOW_PORT_ID;
++
++ break;
++
++ case 1:
++ mac_name="macb";
++
++ /* Also setting port information */
++ p_dev->if_port = AVALANCHE_CPMAC_HIGH_PORT_ID;
++
++ break;
++ }
++
++ if(mac_name)
++ mac_string=prom_getenv(mac_name);
++
++ if(!mac_string)
++ {
++ mac_string="08.00.28.32.06.02";
++ printk("Error getting mac from Boot enviroment for %s\n",p_dev->name);
++ printk("Using default mac address: %s\n",mac_string);
++ if(mac_name)
++ {
++ printk("Use Bootloader command:\n");
++ printk(" setenv %s xx.xx.xx.xx.xx.xx\n","<env_name>");
++ printk("to set mac address\n");
++ }
++ }
++
++ str2eaddr(p_cpmac_priv->mac_addr,mac_string);
++
++ for (i=0; i <= ETH_ALEN; i++)
++ {
++ /* This sets the hardware address */
++ p_dev->dev_addr[i] = p_cpmac_priv->mac_addr[i];
++ }
++
++ p_cpmac_priv->set_to_close = 1;
++ p_cpmac_priv->non_data_irq_expected = 0;
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// if((p_cpmac_priv->led_handle = avalanche_led_register("cpmac", instance_num)) == NULL)
++// {
++// errPrint("Could not allocate handle for CPMAC[%d] LED.\n", instance_num);
++// goto cpmac_init_mod_error;
++// }
++//#endif
++
++ if(cpmac_drv_init_module(p_drv_hal, p_dev, instance_num) != 0)
++ {
++ errPrint("Could not initialize the HAL for %s.\n", p_dev->name);
++ goto cpmac_init_mod_error;
++ }
++
++ /* initialize the CPMAC device */
++ if (cpmac_drv_init(p_drv_hal) == -1)
++ {
++ errPrint("HAL init failed for %s.\n", p_dev->name);
++ goto cpmac_init_device_error;
++ }
++
++ if(cpmac_p_probe_and_setup_device(p_cpmac_priv, &net_flags) == -1)
++ {
++ errPrint("Failed to configure up %s.\n", p_dev->name);
++ goto cpmac_init_device_error;
++ }
++
++ if(cpmac_p_setup_driver_params(p_cpmac_priv) == -1)
++ {
++ errPrint("Failed to set driver parameters for %s.\n", p_dev->name);
++ goto cpmac_init_device_error;
++ }
++
++ cpmac_p_rx_buf_setup(p_rx_chan_info);
++
++ /* initialize the timers for the net device */
++ if(cpmac_p_timer_init(p_cpmac_priv) == -1)
++ {
++ errPrint("Failed to set timer(s) for %s.\n", p_dev->name);
++ goto cpmac_timer_init_error;
++ }
++
++ p_dev->addr_len = 6;
++
++ p_dev->open = &cpmac_dev_open; /* i.e. Start Device */
++ p_dev->hard_start_xmit = &cpmac_dev_tx;
++ p_dev->stop = &cpmac_dev_close;
++ p_dev->get_stats = &cpmac_dev_get_net_stats;
++
++ p_dev->set_multicast_list = &cpmac_dev_mcast_set;
++ p_dev->set_mac_address = cpmac_dev_set_mac_addr;
++ /* Knocking off the default broadcast and multicast flags. Allowing the
++ device configuration to control the flags. */
++ p_dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST);
++ p_dev->flags |= net_flags;
++
++ netif_carrier_off(p_dev);
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_OFF);
++//#endif
++
++ /* Tasklet is initialized at the isr registeration time. */
++ p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "CpmacBase", "Get", &p_dev->base_addr);
++ p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "CpmacSize", "Get", &p_cpmac_priv->dev_size);
++
++ request_mem_region(p_dev->base_addr, p_cpmac_priv->dev_size, p_dev->name);
++
++ retVal = 0;
++
++ if(g_init_enable_flag)
++ cpmac_p_dev_enable(p_dev);
++
++ return(retVal);
++
++cpmac_timer_init_error:
++cpmac_init_device_error :
++ cpmac_drv_cleanup(p_drv_hal);
++
++cpmac_init_mod_error:
++ kfree(p_drv_hal);
++
++ return (retVal);
++
++} /* cpmac_dev_init */
++
++
++/***************************************************************
++ * cpmac_p_dev_enable
++ *
++ * Returns:
++ * 0 on success, error code otherwise.
++ * Parms:
++ * dev Structure of device to be opened.
++ *
++ * This routine puts the driver and CPMAC adapter in a
++ * state where it is ready to send and receive packets.
++ *
++ *
++ **************************************************************/
++int cpmac_p_dev_enable( struct net_device *p_dev)
++{
++ int ret_val = 0;
++ int channel = 0;
++
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = p_cpmac_priv->rx_chan_info;
++ int max_length = p_rx_chan_info->chan->tot_buf_size;
++
++ p_cpmac_priv->set_to_close = 0;
++
++ if((ret_val = cpmac_drv_start(p_drv_hal, p_cpmac_priv->tx_chan_info,
++ p_cpmac_priv->rx_chan_info, CHAN_SETUP))==-1)
++ {
++ errPrint("%s error: failed to start the device.\n", p_dev->name);
++ ret_val = -1;
++ }
++ else if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev,"RX_UNICAST_SET",
++ "Set", &channel)!=0)
++ {
++ errPrint("%s error: device chan 0 could not be enabled.\n", p_dev->name);
++ ret_val = -1;
++ }
++ else if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, pszRX_MAXLEN, pszSet, &max_length) != 0)
++ {
++ errPrint(" CPMAC registers can't be written \n");
++ ret_val = -1;
++ }
++ else if(p_drv_hal->hal_funcs->Control(p_drv_hal->hal_dev, "TxIntDisable", "Set",
++ &p_cpmac_priv->tx_chan_info->tx_int_disable) != 0)
++ {
++ errPrint(" CPMAC registers can't be written \n");
++ ret_val = -1;
++ }
++ else
++ {
++ ; // Every thing went OK.
++ }
++
++ return(ret_val);
++} /* cpmac_dev_enable */
++
++
++static int cpmac_dev_open(struct net_device *p_dev)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_ISR_INFO_T *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
++
++ if(!g_init_enable_flag)
++ cpmac_p_dev_enable(p_dev);
++
++ if(request_irq(p_isr_cb_param->intr, cpmac_hal_isr, SA_INTERRUPT,
++ "Cpmac Driver", p_isr_cb_param))
++ {
++ errPrint("Failed to register the irq %d for Cpmac %s.\n",
++ p_isr_cb_param->intr, p_dev->name);
++ return (-1);
++ }
++
++ netif_start_queue(p_dev);
++
++ MOD_INC_USE_COUNT;
++ p_cpmac_priv->stats->start_tick = jiffies;
++ dbgPrint("Started the network queue for %s.\n", p_dev->name);
++ return(0);
++}
++
++/***************************************************************
++ * cpmac_p_dev_disable
++ *
++ * Returns:
++ * An error code.
++ * Parms:
++ * dev The device structure of the device to
++ * close.
++ *
++ * This function shuts down the adapter.
++ *
++ **************************************************************/
++int cpmac_p_dev_disable(struct net_device *p_dev)
++{
++ int ret_val = 0;
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++
++ set_bit(0, &p_cpmac_priv->set_to_close);
++ set_bit(0, &p_cpmac_priv->non_data_irq_expected);
++
++ /* The driver does not re-schedule the tasklet after kill is called. So, this
++ should take care of the bug in the kernel. */
++ tasklet_kill(&p_cpmac_priv->cpmac_isr.tasklet);
++
++ if(cpmac_drv_stop(p_drv_hal, p_cpmac_priv->tx_chan_info,
++ p_cpmac_priv->rx_chan_info,
++ CHAN_TEARDOWN | FREE_BUFFER | BLOCKING | COMPLETE) == -1)
++ {
++ ret_val = -1;
++ }
++ else
++ {
++ /* hope that the HAL closes down the tick timer.*/
++
++ dbgPrint("Device %s Closed.\n", p_dev->name);
++ p_cpmac_priv->stats->start_tick = jiffies;
++
++ p_cpmac_priv->link_speed = 100000000;
++ p_cpmac_priv->link_mode = 1;
++ netif_carrier_off(p_dev);
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_OFF);
++//#endif
++
++ clear_bit(0, &p_cpmac_priv->non_data_irq_expected);
++
++ }
++
++ return (ret_val);
++
++} /* cpmac_dev_close */
++
++
++/***************************************************************
++ * cpmac_dev_close
++ *
++ * Returns:
++ * An error code.
++ * Parms:
++ * dev The device structure of the device to
++ * close.
++ *
++ * This function shuts down the adapter.
++ *
++ **************************************************************/
++static int cpmac_dev_close(struct net_device *p_dev)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_ISR_INFO_T *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
++
++ /* inform the upper layers. */
++ netif_stop_queue(p_dev);
++
++ if(!g_init_enable_flag)
++ cpmac_p_dev_disable(p_dev);
++ else
++ free_irq(p_isr_cb_param->intr, p_isr_cb_param);
++
++ MOD_DEC_USE_COUNT;
++
++ return(0);
++}
++
++static void cpmac_dev_mcast_set(struct net_device *p_dev)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ CPMAC_ABILITY_INFO_T *p_capability = p_cpmac_priv->ability_info;
++ HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
++ HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
++ int val = 1;
++ int channel = 0;
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// if(netif_carrier_ok(p_dev))
++// avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_LINK_ON);
++//#endif
++
++ if(p_dev->flags & IFF_PROMISC)
++ {
++ if(p_capability->promiscous)
++ {
++ /* multi mode in the HAL, check this */
++ val = 0;
++ p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, "Clear", &val);
++
++ val = 1;
++ /* set the promiscous mode in the HAL */
++ p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, pszSet, &val);
++ p_hal_funcs->Control(p_hal_dev, pszRX_PROM_CH, pszSet, &channel);
++
++ dbgPrint("%s set in the Promisc mode.\n", p_dev->name);
++ }
++ else
++ {
++ errPrint("%s not configured for Promisc mode.\n", p_dev->name);
++ }
++ }
++ else if(p_dev->flags & IFF_ALLMULTI)
++ {
++ if(p_capability->all_multi)
++ {
++ val = 0;
++ /* disable the promiscous mode in the HAL */
++ p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, "Clear", &val);
++
++ val = 1;
++ /* set the all multi mode in the HAL */
++ p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, pszSet, &val);
++ p_hal_funcs->Control(p_hal_dev, pszRX_MULT_CH, pszSet, &channel);
++
++ dbgPrint("%s has been set to the ALL_MULTI mode.\n", p_dev->name);
++ }
++ else
++ {
++ errPrint("%s not configured for ALL MULTI mode.\n", p_dev->name);
++ }
++ }
++ else if(p_dev->mc_count)
++ {
++ if(p_capability->multicast)
++ {
++ struct dev_mc_list *p_dmi = p_dev->mc_list;
++ int count;
++
++ val = 0;
++ /* clear all the previous data, we are going to populate new ones.*/
++ p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, "Clear", &val);
++ /* disable the promiscous mode in the HAL */
++ p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, pszSet, &val);
++
++ for(count = 0; count < p_dev->mc_count; count++, p_dmi = p_dmi->next)
++ {
++ p_hal_funcs->Control(p_hal_dev, "RX_MULTI_SINGLE", "Set", p_dmi->dmi_addr);
++ }
++
++ dbgPrint("%s configured for %d multicast addresses.\n", p_dev->name, p_dev->mc_count);
++ }
++ else
++ {
++ errPrint("%s has not been configuted for multicast handling.\n", p_dev->name);
++ }
++ }
++ else
++ {
++ val = 0;
++ /* clear all the previous data, we are going to populate new ones.*/
++ p_hal_funcs->Control(p_hal_dev, pszRX_MULTI_ALL, "Clear", &val);
++ /* disable the promiscous mode in the HAL */
++ p_hal_funcs->Control(p_hal_dev, pszRX_CAF_EN, pszSet, &val);
++ dbgPrint("Dev set to Unicast mode.\n");
++ }
++}
++
++static int cpmac_dev_set_mac_addr(struct net_device *p_dev,void * addr)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
++ HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
++ struct sockaddr *sa = addr;
++
++ memcpy(p_cpmac_priv->mac_addr,sa->sa_data,p_dev->addr_len);
++ memcpy(p_dev->dev_addr,sa->sa_data,p_dev->addr_len);
++ p_hal_funcs->Control(p_hal_dev, pszMacAddr, pszSet, p_cpmac_priv->mac_addr);
++
++ return 0;
++
++}
++
++/* VLAN is handled by vlan/vconfig support. Here, we just check for the
++ * 802.1q configuration of the device and en-queue the packet accordingly.
++ * We do not do any 802.1q processing here.
++ */
++static int cpmac_dev_tx( struct sk_buff *skb, struct net_device *p_dev)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ int channel = 0;
++ int ret_val = 0;
++ FRAGLIST send_frag_list[1];
++
++#ifdef CPMAC_8021Q_SUPPORT
++ if(skb->len < TCI_END_OFFSET)
++ {
++ /* Whee, frame shorter than 14 bytes !! We need to copy
++ * fragments to understand the frame. Too much work.
++ * Hmm, dump it. */
++
++ /* Free the buffer */
++ goto cpmac_dev_tx_drop_pkt;
++ }
++
++ /* 802.1p/q stuff */
++ if(IS_802_1Q_FRAME(skb->data + TPID_START_OFFSET))
++ {
++ /* IEEE 802.1q, section 8.8 and section 8.11.9 */
++ if(!p_cpmac_priv->enable_802_1q)
++ {
++ /* free the buffer */
++ goto cpmac_dev_tx_drop_pkt;
++ }
++
++ channel = GET_802_1P_CHAN(p_cpmac_priv->tx_chan_info->opened_chan,
++ skb->data[TCI_START_OFFSET]);
++
++ }
++ /* sending a non 802.1q frame, when configured for 802.1q: dump it.*/
++ else if(p_cpmac_priv->enable_802_1q)
++ {
++ /* free the buffer */
++ goto cpmac_dev_tx_drop_pkt;
++ }
++ else
++ {
++ ;/* it is the good old non 802.1q */
++ }
++#endif
++
++ send_frag_list->len = skb->len;
++ send_frag_list->data = skb->data;
++
++#ifdef CPMAC_TEST
++ xdump(skb->data, skb->len, "send");
++#endif
++
++ dma_cache_wback_inv((unsigned long)skb->data, skb->len);
++
++ if(p_drv_hal->hal_funcs->Send(p_drv_hal->hal_dev, send_frag_list, 1,
++ skb->len, skb, channel) != 0)
++ {
++ /* code here to stop the queue, when allowing tx timeout, perhaps next release.*/
++ p_cpmac_priv->net_dev_stats.tx_errors++;
++#ifndef TI_SLOW_PATH
++ /* Free the skb in case of Send return error */
++ dev_kfree_skb_any(skb);
++ p_cpmac_priv->net_dev_stats.tx_dropped++;
++ return 0;
++#endif
++ goto cpmac_dev_tx_drop_pkt;
++ }
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_TX_ACTIVITY);
++//#endif
++
++ return(ret_val);
++
++cpmac_dev_tx_drop_pkt:
++
++ p_cpmac_priv->net_dev_stats.tx_dropped++;
++ ret_val = -1;
++ return (ret_val);
++
++} /*cpmac_dev_tx */
++
++
++//------------------------------------------------------------------------------
++// Public functions : Called by outsiders to this file.
++//------------------------------------------------------------------------------
++
++
++void *cpmac_hal_malloc_buffer(unsigned int size, void* mem_base, unsigned int mem_range,
++ OS_SETUP *p_os_setup, HAL_RECEIVEINFO *HalReceiveInfo,
++ OS_RECEIVEINFO **osReceiveInfo, OS_DEVICE *p_dev)
++{
++ CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = (CPMAC_RX_CHAN_INFO_T *)p_os_setup;
++ int tot_buf_size = p_rx_chan_info->chan->tot_buf_size;
++ int tot_reserve_bytes = p_rx_chan_info->chan->tot_reserve_bytes;
++ struct sk_buff *p_skb;
++ void *ret_ptr;
++
++ /* use TI SKB private pool */
++ p_skb = dev_alloc_skb(tot_buf_size);
++
++ if(p_skb == NULL)
++ {
++ errPrint("Failed to allocate skb for %s.\n", ((struct net_device*)p_dev)->name);
++ return (NULL);
++ }
++
++ p_skb->dev = p_dev;
++ skb_reserve(p_skb, tot_reserve_bytes);
++
++ *osReceiveInfo = p_skb;
++
++ ret_ptr = skb_put(p_skb, p_rx_chan_info->chan->buffer_size);
++
++ return(ret_ptr);
++}
++
++void cpmac_hal_isr(int irq, void *p_param, struct pt_regs *regs)
++{
++ CPMAC_ISR_INFO_T *p_cb_param = (CPMAC_ISR_INFO_T*) p_param;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cb_param->owner;
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_drv_hal->owner;
++ int pkts_to_handle = 0;
++
++ if(p_cpmac_priv->non_data_irq_expected)
++ {
++ p_cb_param->hal_isr(p_drv_hal->hal_dev, &pkts_to_handle);
++ p_drv_hal->hal_funcs->PacketProcessEnd(p_drv_hal->hal_dev);
++ }
++ else if(!p_cpmac_priv->set_to_close)
++ tasklet_schedule(&((CPMAC_ISR_INFO_T*) p_param)->tasklet);
++ else
++ ; // back off from doing anything more. We are closing down.
++}
++
++void cpmac_handle_tasklet(unsigned long data)
++{
++ CPMAC_ISR_INFO_T *p_cb_param = (CPMAC_ISR_INFO_T*) data;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cb_param->owner;
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_drv_hal->owner;
++ int pkts_to_handle;
++
++ p_cb_param->hal_isr(p_drv_hal->hal_dev, &pkts_to_handle);
++
++ if(test_bit(0, &p_cpmac_priv->non_data_irq_expected) || !pkts_to_handle)
++ p_drv_hal->hal_funcs->PacketProcessEnd(p_drv_hal->hal_dev);
++ else if(!test_bit(0, &p_cpmac_priv->set_to_close))
++ tasklet_schedule(&p_cb_param->tasklet);
++ else
++ ; // Back off from processing packets we are closing down.
++}
++
++int cpmac_hal_control(OS_DEVICE *p_dev, const char *key,
++ const char *action, void *value)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ int ret_val = -1;
++
++ if(key == NULL)
++ {
++ dbgPrint("Encountered NULL key.\n");
++ return (-1);
++ }
++
++ if(cpmac_ci_strcmp(key, "Sleep") == 0 && value != NULL)
++ {
++ unsigned int clocks_per_tick = cpmac_cpu_freq/HZ;
++ unsigned int requested_clocks = *(unsigned int*)value;
++ unsigned int requested_ticks = (requested_clocks + clocks_per_tick - 1)/clocks_per_tick;
++ mdelay(requested_ticks);
++ ret_val = 0;
++ }
++ else if(cpmac_ci_strcmp(key, "StateChange") == 0)
++ {
++ ret_val = cpmac_p_process_status_ind(p_cpmac_priv);
++ }
++ else if(cpmac_ci_strcmp(key, "Tick") == 0 && action != NULL)
++ {
++ if(cpmac_ci_strcmp(action, "Set") == 0 && value != NULL)
++ {
++ if(*(unsigned int*)value == 0)
++ {
++ cpmac_p_stop_timer(p_cpmac_priv->timer + TICK_TIMER);
++ ret_val = 0;
++ }
++ else
++ {
++ unsigned int clocks_per_tick = cpmac_cpu_freq/HZ;
++ unsigned int requested_clocks = *(unsigned int*)value;
++ unsigned int requested_ticks = (requested_clocks + clocks_per_tick - 1)/clocks_per_tick;
++
++ p_cpmac_priv->delay_ticks = requested_ticks; /* save it for re-triggering */
++ ret_val = cpmac_p_start_timer(p_cpmac_priv->timer + TICK_TIMER,
++ p_cpmac_priv->delay_ticks);
++ }
++ }
++ else if(cpmac_ci_strcmp(action, "Clear") == 0)
++ {
++ ret_val = cpmac_p_stop_timer(p_cpmac_priv->timer + TICK_TIMER);
++ }
++ else
++ ;
++ }
++ else if(cpmac_ci_strcmp(key, "MacAddr") == 0 && action != NULL)
++ {
++ if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
++ {
++ *(char **)value = p_cpmac_priv->mac_addr;
++ ret_val = 0;
++ }
++ }
++ else if(cpmac_ci_strcmp(key, "CpuFreq") == 0)
++ {
++ if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
++ {
++ *(unsigned int *)value = cpmac_cpu_freq;
++ dbgPrint("Cpu frequency for cpmacs is %u\n",cpmac_cpu_freq);
++ ret_val = 0;
++ }
++ }
++ else if(cpmac_ci_strcmp(key, "SioFlush") == 0)
++ {
++ ret_val = 0;
++ dbgPrint("\n");
++ }
++ else if(cpmac_ci_strcmp(key, "CpmacFrequency") == 0)
++ {
++ /* For Sangam cpmac clock is off the PBUS */
++ /* OS Needs to supply CORRECT frequency */
++ if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
++ {
++ *(unsigned int *)value = CONFIG_AR7_SYS * 1000 * 1000;
++ ret_val = 0;
++ }
++ }
++ /* For now, providing back the default values. */
++ else if(cpmac_ci_strcmp(key, "MdioClockFrequency") == 0)
++ {
++ if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
++ {
++ *(unsigned int *)value = 2200000; /*DEFAULT */
++ ret_val = 0;
++ }
++ }
++ /* For now, providing back the default values. */
++ else if(cpmac_ci_strcmp(key, "MdioBusFrequency") == 0)
++ {
++ /* For Sangam MdioBusFreq is off the PBUS */
++ if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
++ {
++ *(unsigned int *)value = CONFIG_AR7_SYS * 1000 * 1000;
++ ret_val = 0;
++ }
++ }
++
++#if 0
++#if defined(CONFIG_AVALANCHE_AUTO_MDIX)
++ /* supporting Mdio Mdix switching */
++ else if(cpmac_ci_strcmp(key, hcMdioMdixSwitch) == 0)
++ {
++ /* For Sangam Mdio-switching action should be always "set"*/
++ if(cpmac_ci_strcmp(action, hcSet) == 0 && value != NULL )
++ {
++ unsigned int mdix = *((unsigned int *) value) ;
++
++ if(mdix)
++ avalanche_set_phy_into_mdix_mode();
++
++ else
++ avalanche_set_phy_into_mdi_mode();
++
++ ret_val = 0;
++ }
++
++ }
++#endif
++#endif
++ else if(cpmac_ci_strcmp(key, hcMdioMdixSwitch) == 0)
++ {
++ /* For Sangam Mdio-switching action should be always "set"*/
++ if(cpmac_ci_strcmp(action, hcSet) == 0 && value != NULL )
++ {
++ unsigned int mdix = *((unsigned int *) value) ;
++
++#ifdef CONFIG_AR7_MDIX
++ avalanche_set_mdix_on_chip(0xa8610000 , mdix ? 1: 0);
++#endif
++
++ ret_val = 0;
++ }
++
++ }
++
++ return(ret_val);
++}
++
++
++int cpmac_hal_receive(OS_DEVICE *p_dev, FRAGLIST *fragList,
++ unsigned int fragCount,
++ unsigned int packet_size,
++ HAL_RECEIVEINFO *hal_receive_info,
++ unsigned int mode)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ struct sk_buff *p_skb = fragList[0].OsInfo;
++ p_skb->len = fragList[0].len;
++
++ /* invalidate the cache. */
++ dma_cache_inv((unsigned long)p_skb->data, fragList[0].len);
++#ifdef CPMAC_TEST
++ xdump(p_skb->data, p_skb->len, "recv");
++#endif
++#ifdef CPMAC_8021Q_SUPPORT
++ /* 802.1q stuff, just does the basic checking here. */
++ if(!p_cpmac_priv->enable_802_1q &&
++ p_skb->len > TCI_END_OFFSET &&
++ IS_802_1Q_FRAME(p_skb->data + TPID_START_OFFSET))
++ {
++ goto cpmac_hal_recv_frame_mismatch;
++ }
++#endif
++ if(fragCount > 1)
++ {
++ int len;
++ struct sk_buff *p_temp_skb;
++ CPMAC_RX_CHAN_INFO_T *p_rx_chan_info = p_cpmac_priv->rx_chan_info;
++ int count;
++
++ dbgPrint("Recv: It is multifragment for %s.\n", p_dev->name);
++
++ p_skb = dev_alloc_skb(packet_size +
++ p_rx_chan_info->chan->tot_reserve_bytes);
++ if(p_skb == NULL)
++ {
++ p_cpmac_priv->net_dev_stats.rx_errors++;
++ goto cpmac_hal_recv_alloc_failed;
++ }
++
++ p_skb->dev = p_dev;
++ skb_reserve(p_skb, p_rx_chan_info->chan->tot_reserve_bytes);
++
++ for(count = 0; count < fragCount; count++)
++ {
++ p_temp_skb = fragList[count].OsInfo;
++ len = fragList[count].len;
++
++ dma_cache_inv((unsigned long)p_temp_skb->data, len);
++
++ memcpy(skb_put(p_skb, len), p_temp_skb->data, len);
++ dev_kfree_skb_any(p_temp_skb);
++ }
++ }
++
++
++#if defined(CONFIG_MIPS_AVALANCHE_MARVELL)
++ /* Fetch the receiving port information from EGRESS TRAILOR Bytes*/
++ p_dev->if_port = (unsigned char)p_skb->data[packet_size -(EGRESS_TRAILOR_LEN-1)] + AVALANCHE_MARVELL_BASE_PORT_ID;
++ skb_trim(p_skb, packet_size - EGRESS_TRAILOR_LEN);
++#else
++ /* set length & tail */
++ skb_trim(p_skb, packet_size);
++#endif
++
++ p_skb->protocol = eth_type_trans(p_skb, p_dev);
++
++ netif_rx(p_skb);
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// avalanche_led_action(p_cpmac_priv->led_handle, CPMAC_RX_ACTIVITY);
++//#endif
++
++ p_cpmac_priv->net_dev_stats.rx_packets++;
++ p_cpmac_priv->net_dev_stats.rx_bytes += packet_size;
++
++ p_drv_hal->hal_funcs->RxReturn(hal_receive_info,1);
++
++ return(0);
++
++cpmac_hal_recv_alloc_failed:
++
++#ifdef CPMAC_8021Q_SUPPORT
++cpmac_hal_recv_frame_mismatch:
++#endif
++
++ fragCount--;
++
++ do
++ {
++ dev_kfree_skb_any(fragList[fragCount].OsInfo);
++ }
++ while(fragCount--);
++
++ p_cpmac_priv->net_dev_stats.rx_dropped++;
++
++ return(-1);
++} /*cpmac_receive*/
++
++
++void cpmac_hal_tear_down_complete(OS_DEVICE*a, int b, int ch)
++{
++ dbgPrint("what to do with this.\n");
++}
++
++
++int cpmac_hal_send_complete(OS_SENDINFO *p_skb)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_skb->dev->priv;
++
++ p_cpmac_priv->net_dev_stats.tx_packets++;
++ p_cpmac_priv->net_dev_stats.tx_bytes += p_skb->len;
++
++ dev_kfree_skb_any(p_skb);
++
++ return(0);
++}
++
++
++int cpmac_reset(CPMAC_PRIVATE_INFO_T *p_cpmac_priv)
++{
++ // code here to reset the device/hal. Not now.
++
++ netif_wake_queue(p_cpmac_priv->owner);
++ return(0);
++}
++
++#ifdef CPMAC_TEST
++
++#define isprint(a) ((a >=' ')&&(a<= '~'))
++void xdump( u_char* cp, int length, char* prefix )
++{
++ int col, count;
++ u_char prntBuf[120];
++ u_char* pBuf = prntBuf;
++ count = 0;
++ while(count < length){
++ pBuf += sprintf( pBuf, "%s", prefix );
++ for(col = 0;count + col < length && col < 16; col++){
++ if (col != 0 && (col % 4) == 0)
++ pBuf += sprintf( pBuf, " " );
++ pBuf += sprintf( pBuf, "%02X ", cp[count + col] );
++ }
++ while(col++ < 16){ /* pad end of buffer with blanks */
++ if ((col % 4) == 0)
++ sprintf( pBuf, " " );
++ pBuf += sprintf( pBuf, " " );
++ }
++ pBuf += sprintf( pBuf, " " );
++ for(col = 0;count + col < length && col < 16; col++){
++ if (isprint((int)cp[count + col]))
++ pBuf += sprintf( pBuf, "%c", cp[count + col] );
++ else
++ pBuf += sprintf( pBuf, "." );
++ }
++ sprintf( pBuf, "\n" );
++ // SPrint(prntBuf);
++ printk(prntBuf);
++ count += col;
++ pBuf = prntBuf;
++ }
++
++} /* close xdump(... */
++#endif
++
++
++static int __init cpmac_dev_probe(void)
++{
++ int retVal = 0;
++ int unit;
++ int instance_count = CONFIG_MIPS_CPMAC_PORTS;
++
++ //cpmac_cpu_freq = avalanche_clkc_get_freq(CLKC_MIPS);
++ cpmac_cpu_freq = CONFIG_AR7_CPU * 1000 * 1000;
++
++ build_psp_config();
++
++ for(unit = 0; unit < instance_count; unit++)
++ {
++ struct net_device *p_dev;
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
++ size_t dev_size;
++ int failed;
++
++ dev_size = sizeof(struct net_device)
++ + sizeof(CPMAC_PRIVATE_INFO_T);
++
++
++ if((p_dev = (struct net_device *) kmalloc(dev_size, GFP_KERNEL)) == NULL)
++ {
++ dbgPrint( "Could not allocate memory for device.\n" );
++ retVal = -ENOMEM;
++ break;
++ }
++
++ memset(p_dev, 0, dev_size );
++
++ p_dev->priv = p_cpmac_priv
++ = (CPMAC_PRIVATE_INFO_T*)(((char *) p_dev) + sizeof(struct net_device));
++ p_cpmac_priv->owner = p_dev;
++
++ ether_setup(p_dev);
++
++ p_cpmac_priv->instance_num = unit;
++ p_dev->init = cpmac_dev_init;
++
++ g_dev_array[p_cpmac_priv->instance_num] = p_dev;
++
++#if defined CONFIG_MIPS_CPMAC_INIT_BUF_MALLOC
++ g_init_enable_flag = 1;
++ printk("Cpmac driver is allocating buffer memory at init time.\n");
++#endif
++
++ /* This section gives a default value by the number of PHY in order to
++ * replace the default MACRO. */
++ {
++ char *mac_port = prom_getenv("MAC_PORT"); /* Internal: 0, External: 1 */
++ if(!mac_port || (0 != strcmp(mac_port, "0"))) {
++ printk("Using the MAC with external PHY\n");
++ cfg_start_link_speed = _CPMDIO_NOPHY;
++ cpmac_max_frame_size = CPMAC_MAX_FRAME_SIZE + 4;
++ }
++ else {
++ printk("Using the MAC with internal PHY\n");
++ cfg_start_link_speed = CFG_START_LINK_SPEED;
++ cpmac_max_frame_size = CPMAC_MAX_FRAME_SIZE;
++ }
++ g_cfg_start_link_params = cfg_start_link_speed;
++ }
++
++ cpmac_p_detect_manual_cfg(cfg_link_speed, cfg_link_mode, cpmac_debug_mode);
++
++ failed = register_netdev(p_dev);
++ if (failed)
++ {
++ dbgPrint("Could not register device for inst %d because of reason \
++ code %d.\n", unit, failed);
++ retVal = -1;
++ kfree(p_dev);
++ break;
++ }
++ else
++ {
++
++ char proc_name[100];
++ int proc_category_name_len = 0;
++
++ p_cpmac_priv->next_device = last_cpmac_device;
++ last_cpmac_device = p_dev;
++
++ dbgPrint(" %s irq=%2d io=%04x\n",p_dev->name, (int) p_dev->irq,
++ (int) p_dev->base_addr);
++
++ strcpy(proc_name, "avalanche/");
++ strcat(proc_name, p_dev->name);
++ proc_category_name_len = strlen(proc_name);
++
++ strcpy(proc_name + proc_category_name_len, "_rfc2665_stats");
++ create_proc_read_entry(proc_name,0,NULL,cpmac_p_read_rfc2665_stats, p_dev);
++
++ }
++ }
++
++ if(retVal == 0)
++ {
++ /* To maintain backward compatibility with NSP. */
++ gp_stats_file = create_proc_entry("avalanche/cpmac_stats", 0644, NULL);
++ if(gp_stats_file)
++ {
++ gp_stats_file->read_proc = cpmac_p_read_stats;
++ gp_stats_file->write_proc = cpmac_p_write_stats;
++ }
++ create_proc_read_entry("avalanche/cpmac_link", 0, NULL, cpmac_p_read_link, NULL);
++ create_proc_read_entry("avalanche/cpmac_ver", 0, NULL, cpmac_p_get_version, NULL);
++
++ }
++
++ cpmac_devices_installed = unit;
++ dbgPrint("Installed %d cpmac instances.\n", unit);
++ return ( (unit >= 0 ) ? 0 : -ENODEV );
++
++} /* init_module */
++
++
++/***************************************************************
++ * cleanup_module
++ *
++ * Returns:
++ * Nothing
++ * Parms:
++ * None
++ *
++ * Goes through the CpmacDevices list and frees the device
++ * structs and memory associated with each device (lists
++ * and buffers). It also ureserves the IO port regions
++ * associated with this device.
++ *
++ **************************************************************/
++
++void cpmac_exit(void)
++{
++ struct net_device *p_dev;
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv;
++
++ while (cpmac_devices_installed)
++ {
++ char proc_name[100];
++ int proc_category_name_len = 0;
++
++ p_dev = last_cpmac_device;
++ p_cpmac_priv = (CPMAC_PRIVATE_INFO_T *) p_dev->priv;
++
++ dbgPrint("Unloading %s irq=%2d io=%04x\n",p_dev->name, (int) p_dev->irq, (int) p_dev->base_addr);
++
++ if(g_init_enable_flag)
++ cpmac_p_dev_disable(p_dev);
++
++ cpmac_drv_cleanup(p_cpmac_priv->drv_hal);
++
++//#if defined (CONFIG_MIPS_AVALANCHE_LED)
++// avalanche_led_unregister(p_cpmac_priv->led_handle);
++//#endif
++ strcpy(proc_name, "avalanche/");
++ strcat(proc_name, p_dev->name);
++ proc_category_name_len = strlen(proc_name);
++
++ strcpy(proc_name + proc_category_name_len, "_rfc2665_stats");
++ remove_proc_entry(proc_name, NULL);
++
++ release_mem_region(p_dev->base_addr, p_cpmac_priv->dev_size);
++ unregister_netdev(p_dev);
++ last_cpmac_device = p_cpmac_priv->next_device;
++
++ kfree(p_cpmac_priv->drv_hal);
++ kfree(p_dev);
++
++ cpmac_devices_installed--;
++ }
++
++ if(gp_stats_file)
++ remove_proc_entry("avalanche/cpmac_stats", NULL);
++
++ remove_proc_entry("avalanche/cpmac_link", NULL);
++ remove_proc_entry("avalanche/cpmac_ver", NULL);
++
++ psp_config_cleanup();
++}
++
++
++module_init(cpmac_dev_probe);
++module_exit(cpmac_exit);
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpmac.h linux.dev/drivers/net/avalanche_cpmac/cpmac.h
+--- linux.old/drivers/net/avalanche_cpmac/cpmac.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpmac.h 2005-07-12 02:48:42.043594000 +0200
+@@ -0,0 +1,379 @@
++/******************************************************************************
++ * FILE PURPOSE: CPMAC Linux Network Device Driver Header
++ ******************************************************************************
++ * FILE NAME: cpmac.h
++ *
++ * DESCRIPTION: CPMAC Network Device Driver Header
++ *
++ * REVISION HISTORY:
++ * Date Name Details
++ *-----------------------------------------------------------------------------
++ * 27 Nov 2002 Suraj S Iyer Initial Create.
++ * 09 Jun 2003 Suraj S Iyer Preparing for GA.
++ *
++ * (C) Copyright 2003, Texas Instruments, Inc
++ *******************************************************************************/
++
++#ifndef CPMAC_H
++#define CPMAC_H
++
++#include <linux/timer.h>
++#include <linux/netdevice.h>
++#include <asm/semaphore.h>
++#include <linux/ctype.h>
++#include <linux/interrupt.h>
++
++#include "cpmacHalLx.h"
++/*-----------------------------------------------------------------------------
++ * Config macros. Use these to config the driver.
++ *---------------------------------------------------------------------------*/
++#define CPMAC_MAX_FRAME_SIZE 1518
++
++#if defined(CONFIG_AR7WRD) || defined(CONFIG_AR7WI) || defined(CONFIG_AR7VWI)|| defined(CONFIG_AR7VW)
++#define CFG_RX_NUM_BUF_DESC 64
++#define CFG_RX_NUM_BUF_SERVICE 32
++#else
++#define CFG_RX_NUM_BUF_DESC 16
++#define CFG_RX_NUM_BUF_SERVICE 8
++#endif
++
++#define CFG_RX_BUF_OFFSET 0
++
++#define CFG_TX_NUM_BUF_DESC 128
++#define CFG_TX_NUM_BUF_SERVICE 20
++#define CFG_TX_BUF_OFFSET 0 /* Lets not change this. */
++#define CFG_TX_TIMEOUT 2000 /* ticks*/
++#define CFG_TX_INT_DISABLE 1 /* Disable the Tx Complete interrupt */
++
++#define CFG_JUMBO_FRAMES 1
++#define CFG_SHORT_FRAMES 1
++#define CFG_PROMISCOUS 1
++#define CFG_BROADCAST 1
++#define CFG_MULTICAST 1
++#define CFG_ALL_MULTI (1*(CFG_MULTICAST))
++#define CFG_AUTO_NEGOTIATION 1
++
++#if defined (CONFIG_MIPS_AVALANCHE_MARVELL)
++#define EGRESS_TRAILOR_LEN 4
++#define CFG_START_LINK_SPEED (_CPMDIO_NOPHY)
++#undef CPMAC_MAX_FRAME_SIZE
++#define CPMAC_MAX_FRAME_SIZE (1518 + EGRESS_TRAILOR_LEN)
++#else
++#define CFG_START_LINK_SPEED (_CPMDIO_10 | _CPMDIO_100 | _CPMDIO_HD | _CPMDIO_FD) /* auto nego */
++#endif
++
++#define CFG_LOOP_BACK 1
++#define CFG_TX_FLOW_CNTL 0
++#define CFG_RX_FLOW_CNTL 0
++#define CFG_TX_PACING 0
++#define CFG_RX_PASS_CRC 0
++#define CFG_QOS_802_1Q 0
++#define CFG_TX_NUM_CHAN 1
++
++
++/*-----------------------------------------------------------------------------
++ * Private macros.
++ *---------------------------------------------------------------------------*/
++#define MAX_TIMER 2
++#define TX_TIMER 0
++#define TICK_TIMER 0
++#define MAX_TX_CHAN 8
++
++#define CPMAC_LINK_OFF 0
++#define CPMAC_LINK_ON 1
++/*#define CPMAC_SPEED_100 2
++#define CPMAC_SPEED_10 3
++#define CPMAC_FULL_DPLX 4
++#define CPMAC_HALF_DPLX 5*/
++#define CPMAC_RX_ACTIVITY 2
++#define CPMAC_TX_ACTIVITY 3
++
++struct cpmac_timer_info;
++
++typedef int (*CPMAC_HAL_ISR_FUNC_T)(HAL_DEVICE*, int*);
++typedef int (*CPMAC_TIMEOUT_CB_T)(struct cpmac_timer_info*);
++
++typedef struct cpmac_ability_info
++{
++ int promiscous;
++ int broadcast;
++ int multicast;
++ int all_multi;
++ int loop_back;
++ int jumbo_frames;
++ int short_frames;
++ int auto_negotiation;
++ int tx_flow_control;
++ int rx_flow_control;
++ int tx_pacing;
++ int link_speed;
++ int rx_pass_crc;
++ int qos_802_1q;
++ int tx_num_chan;
++}
++CPMAC_ABILITY_INFO_T;
++
++#ifdef DEBUG
++typedef struct cpmac_timer_info
++{
++ void *owner;
++ UINT32 delay_ticks;
++ WDOG_ID timer_id;
++ UINT32 is_running;
++ UINT32 timer_set_at;
++ CPMAC_TIMEOUT_CB_T timeout_CB;
++} CPMAC_TIMER_INFO_T;
++
++typedef struct
++{
++ void *owner;
++ unsigned int num_cl_desc;
++ CL_DESC *cl_desc_tbl;
++ M_CL_CONFIG *m_cl_blk_config;
++ NET_POOL *net_pool;
++ CL_POOL_ID clPoolId;
++
++} CPMAC_NET_MEM_INFO_T;
++
++#endif
++
++typedef struct
++{
++ void *owner;
++ CPMAC_HAL_ISR_FUNC_T hal_isr;
++ struct tasklet_struct tasklet;
++ int intr;
++
++} CPMAC_ISR_INFO_T;
++
++typedef struct cpmac_chan
++{
++ int num_BD;
++ int buffer_size;
++ int buffer_offset;
++ int service_max;
++ int state;
++ int tot_buf_size;
++ int tot_reserve_bytes;
++
++} CPMAC_CHAN_T;
++
++#define CHAN_CLOSE 0
++#define CHAN_OPENED 1
++
++typedef struct
++{
++ int cfg_chan;
++ int dev_chan;
++ int opened_chan;
++ CPMAC_CHAN_T chan[1];
++ int enable_802_1q;
++
++} CPMAC_RX_CHAN_INFO_T;
++
++typedef struct
++{
++ int cfg_chan;
++ int dev_chan;
++ int opened_chan;
++ int tx_int_disable;
++ CPMAC_CHAN_T chan[MAX_TX_CHAN];
++
++} CPMAC_TX_CHAN_INFO_T;
++
++
++
++typedef struct
++{
++ void *owner;
++ HAL_FUNCTIONS *hal_funcs;
++ HAL_DEVICE *hal_dev;
++ OS_FUNCTIONS *os_funcs;
++// SEM_ID chan_teardown_sem;
++ int non_data_irq_expected;
++} CPMAC_DRV_HAL_INFO_T;
++
++
++typedef struct
++{
++ unsigned long tx_discards;
++ unsigned long rx_discards;
++ unsigned long start_tick;
++
++} CPMAC_DRV_STATS_T;
++
++typedef struct
++{
++ unsigned long ifInGoodFrames;
++ unsigned long ifInBroadcasts;
++ unsigned long ifInMulticasts;
++ unsigned long ifInPauseFrames;
++ unsigned long ifInCRCErrors;
++ unsigned long ifInAlignCodeErrors;
++ unsigned long ifInOversizedFrames;
++ unsigned long ifInJabberFrames;
++ unsigned long ifInUndersizedFrames;
++ unsigned long ifInFragments;
++ unsigned long ifInFilteredFrames;
++ unsigned long ifInQosFilteredFrames;
++ unsigned long ifInOctets;
++ unsigned long ifOutGoodFrames;
++ unsigned long ifOutBroadcasts;
++ unsigned long ifOutMulticasts;
++ unsigned long ifOutPauseFrames;
++ unsigned long ifDeferredTransmissions;
++ unsigned long ifCollisionFrames;
++ unsigned long ifSingleCollisionFrames;
++ unsigned long ifMultipleCollisionFrames;
++ unsigned long ifExcessiveCollisionFrames;
++ unsigned long ifLateCollisions;
++ unsigned long ifOutUnderrun;
++ unsigned long ifCarrierSenseErrors;
++ unsigned long ifOutOctets;
++ unsigned long if64OctetFrames;
++ unsigned long if65To127OctetFrames;
++ unsigned long if128To255OctetFrames;
++ unsigned long if256To511OctetFrames;
++ unsigned long if512To1023OctetFrames;
++ unsigned long if1024ToUPOctetFrames;
++ unsigned long ifNetOctets;
++ unsigned long ifRxSofOverruns;
++ unsigned long ifRxMofOverruns;
++ unsigned long ifRxDMAOverruns;
++
++} CPMAC_DEVICE_MIB_T;
++
++
++typedef struct
++{
++ void *owner;
++ int timer_count;
++ int timer_created;
++ struct timer_list timer[1];
++ CPMAC_DRV_HAL_INFO_T *drv_hal;
++ unsigned int num_of_intr;
++ CPMAC_ISR_INFO_T cpmac_isr;
++ unsigned int link_speed;
++ unsigned int link_mode;
++ unsigned int enable_802_1q;
++ unsigned int timer_access_hal;
++ unsigned int loop_back;
++ CPMAC_RX_CHAN_INFO_T *rx_chan_info;
++ CPMAC_TX_CHAN_INFO_T *tx_chan_info;
++ CPMAC_ABILITY_INFO_T *ability_info;
++ CPMAC_DEVICE_MIB_T *device_mib;
++ CPMAC_DRV_STATS_T *stats;
++ unsigned int flags;
++ unsigned int delay_ticks;
++ char mac_addr[6];
++ struct net_device_stats net_dev_stats;
++// rwlock_t rw_lock;
++ int set_to_close;
++ struct net_device *next_device;
++ unsigned int instance_num;
++ unsigned int non_data_irq_expected;
++ unsigned long dev_size;
++ void* led_handle;
++} CPMAC_PRIVATE_INFO_T;
++
++
++/* Private flags */
++
++/* bit 0 to 31, bit 32 is used to indicate set or reset */
++
++#define IFF_PRIV_SHORT_FRAMES 0x00010000
++#define IFF_PRIV_JUMBO_FRAMES 0x00020000
++#define IFF_PRIV_AUTOSPEED 0x00080000
++#define IFF_PRIV_LINK10_HD 0x00100000
++#define IFF_PRIV_LINK10_FD 0x00200000
++#define IFF_PRIV_LINK100_HD 0x00400000
++#define IFF_PRIV_LINK100_FD 0x00800000
++#define IFF_PRIV_8021Q_EN 0x01000000
++#define IFF_PRIV_NUM_TX_CHAN 0x02000000
++#define IFF_PRIV_TX_FLOW_CNTL 0x04000000
++#define IFF_PRIV_RX_FLOW_CNTL 0x08000000
++#define IFF_PRIV_TX_PACING 0x10000000
++#define IFF_PRIV_RX_PASS_CRC 0x20000000
++
++#define PRIVCSFLAGS 0x200
++#define PRIVCGFLAGS 0x201
++
++
++#define BLOCKING 1
++#define CHAN_TEARDOWN 2
++#define CHAN_SETUP 4
++#define COMPLETE 8
++#define FREE_BUFFER 16
++
++
++static const char pszStats0[] = "Stats0";
++static const char pszStats1[] = "Stats1";
++static const char pszStats2[] = "Stats2";
++static const char pszStats3[] = "Stats3";
++static const char pszStats4[] = "Stats4";
++static const char pszStatsDump[] = "StatsDump";
++static const char pszStatsClear[] = "StatsClear";
++static const char pszRX_PASS_CRC[] = "RX_PASS_CRC";
++static const char pszRX_QOS_EN[] = "RX_QOS_EN";
++static const char pszRX_NO_CHAIN[] = "RX_NO_CHAIN";
++static const char pszRX_CMF_EN[] = "RX_CMF_EN";
++static const char pszRX_CSF_EN[] = "RX_CSF_EN";
++static const char pszRX_CEF_EN[] = "RX_CEF_EN";
++static const char pszRX_CAF_EN[] = "RX_CAF_EN";
++static const char pszRX_PROM_CH[] = "RX_PROM_CH";
++static const char pszRX_BROAD_EN[] = "RX_BROAD_EN";
++static const char pszRX_BROAD_CH[] = "RX_BROAD_CH";
++static const char pszRX_MULT_EN[] = "RX_MULT_EN";
++static const char pszRX_MULT_CH[] = "RX_MULT_CH";
++static const char pszTX_PTYPE[] = "TX_PTYPE";
++static const char pszTX_PACE[] = "TX_PACE";
++static const char pszMII_EN[] = "MII_EN";
++static const char pszTX_FLOW_EN[] = "TX_FLOW_EN";
++static const char pszRX_FLOW_EN[] = "RX_FLOW_EN";
++static const char pszRX_MAXLEN[] = "RX_MAXLEN";
++static const char pszRX_FILTERLOWTHRESH[] = "RX_FILTERLOWTHRESH";
++static const char pszRX0_FLOWTHRESH[] = "RX0_FLOWTHRESH";
++static const char pszRX_UNICAST_SET[] = "RX_UNICAST_SET";
++static const char pszRX_UNICAST_CLEAR[] = "RX_UNICAST_CLEAR";
++static const char pszMdioConnect[] = "MdioConnect";
++static const char pszMacAddr[] = "MacAddr";
++static const char pszTick[] = "Tick";
++static const char pszRX_MULTICAST[] = "RX_MULTICAST";
++static const char pszRX_MULTI_ALL[] = "RX_MULTI_ALL";
++static const char pszRX_MULTI_SINGLE[] = "RX_MULTI_SINGLE";
++
++static const char pszSet[] = "Set";
++static const char pszGet[] = "Get";
++static const char pszClear[] = "Clear";
++
++
++void *cpmac_hal_malloc_buffer(unsigned int size, void *MemBase, unsigned int MemRange,
++ HAL_DEVICE *HalDev, HAL_RECEIVEINFO *HalReceiveInfo,
++ OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev);
++
++void cpmac_hal_tear_down_complete(OS_DEVICE*, int, int);
++int cpmac_hal_control(OS_DEVICE *p_END_obj, const char *key,
++ const char *action, void *value);
++int cpmac_hal_receive(OS_DEVICE *p_END_obj, FRAGLIST *fragList,
++ unsigned int FragCount, unsigned int pkt_len,
++ HAL_RECEIVEINFO *halReceiveInfo,
++ unsigned int mode);
++int cpmac_hal_send_complete(OS_SENDINFO*);
++
++void cpmac_hal_isr(int irq, void *p_param, struct pt_regs *p_cb_param);
++void cpmac_handle_tasklet(unsigned long data);
++
++inline static int cpmac_ci_strcmp(const char *s1, const char *s2)
++{
++ while(*s1 && *s2)
++ {
++ if(tolower(*s1) != tolower(*s2))
++ break;
++ s1++;
++ s2++;
++ }
++
++ return(tolower(*s1) - tolower(*s2));
++}
++
++#endif
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpmacHalLx.c linux.dev/drivers/net/avalanche_cpmac/cpmacHalLx.c
+--- linux.old/drivers/net/avalanche_cpmac/cpmacHalLx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpmacHalLx.c 2005-07-12 02:48:42.044593000 +0200
+@@ -0,0 +1,492 @@
++/******************************************************************************
++ * FILE PURPOSE: CPMAC Net Driver HAL support Source
++ ******************************************************************************
++ * FILE NAME: cpmacHalLx.c
++ *
++ * DESCRIPTION: CPMAC Network Device Driver Source
++ *
++ * REVISION HISTORY:
++ *
++ * Date Description Author
++ *-----------------------------------------------------------------------------
++ * 27 Nov 2002 Initial Creation Suraj S Iyer
++ * 09 Jun 2003 Updates for GA Suraj S Iyer
++ * 18 Dec 2003 Updated for 5.7 Suraj S Iyer
++ *
++ * (C) Copyright 2003, Texas Instruments, Inc
++ *******************************************************************************/
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/spinlock.h>
++#include <linux/proc_fs.h>
++#include <asm/io.h>
++#include <linux/string.h>
++
++#include <asm/ar7/avalanche_intc.h>
++
++#include "cpmacHalLx.h"
++#include "cpmac.h"
++
++/* PSP config headers */
++#include "psp_config_parse.h"
++#include "psp_config_mgr.h"
++
++/* debug */
++extern int cpmac_debug_mode;
++#define dbgPrint if (cpmac_debug_mode) printk
++#define errPrint printk
++
++char CpmacSignature[] = "Cpmac driver";
++static unsigned long irq_flags = 0;
++OS_SETUP *p_os_setup = NULL;
++
++extern int avalanche_request_intr_pacing(int, unsigned int, unsigned int);
++extern int avalanche_free_intr_pacing(unsigned int blk_num);
++
++/*----------------------------------------------------------------------------
++ * Parameter extracting functionalities.
++ *--------------------------------------------------------------------------*/
++static int os_find_parm_u_int(void *info_ptr, const char *param, unsigned int *val)
++{
++ int ret_val = 0;
++
++ if((ret_val = psp_config_get_param_uint(info_ptr, param, val)) == -1)
++ {
++ dbgPrint("Error: could not locate the requested \"%s\" param.\n",param);
++ ret_val = -1;
++ }
++
++ return(ret_val);
++}
++
++static int os_find_parm_val(void *info_ptr, const char *param, void *val)
++{
++ int ret_val = 0;
++
++ if(psp_config_get_param_string(info_ptr, param, val) == -1)
++ {
++ dbgPrint("Error: could not locate the requested \"%s\" param.\n",param);
++ ret_val = -1;
++ }
++
++ return(ret_val);
++}
++
++static int os_find_device(int unit, const char *find_name, void *device_info)
++{
++ int ret_val = 0;
++
++ if(psp_config_get((char *)find_name, unit, device_info) == -1)
++ {
++ dbgPrint("Error: could not locate the requested \"%s\" param.\n", find_name);
++ ret_val = -1;
++ }
++
++ return(ret_val);
++}
++
++/*---------------------------------------------------------------------------
++ * Memory related OS abstraction.
++ *--------------------------------------------------------------------------*/
++void os_free(void *mem_ptr)
++{
++ kfree(mem_ptr);
++}
++
++void os_free_buffer(OS_RECEIVEINFO *osReceiveInfo, void *mem_ptr)
++{
++ dev_kfree_skb_any(osReceiveInfo);
++}
++
++void os_free_dev(void *mem_ptr)
++{
++ kfree(mem_ptr);
++}
++
++void os_free_dma_xfer(void *mem_ptr)
++{
++ kfree(mem_ptr);
++}
++
++static void *os_malloc(unsigned int size)
++{
++ return(kmalloc(size, GFP_KERNEL));
++}
++
++static void *os_malloc_dma_xfer(unsigned int size,
++ void *mem_base,
++ unsigned int mem_range)
++{
++ return(kmalloc(size, GFP_KERNEL));
++}
++
++static void *os_malloc_dev(unsigned int size)
++{
++ return(kmalloc(size, GFP_KERNEL));
++}
++
++
++/*----------------------------------------------------------------------------
++ * CRITICAL SECTION ENABLING/DISABLING.
++ *--------------------------------------------------------------------------*/
++static void os_critical_on(void)
++{
++ save_and_cli(irq_flags);
++}
++
++static void os_critical_off(void)
++{
++ restore_flags(irq_flags);
++}
++
++/*----------------------------------------------------------------------------
++ * Cache related abstraction
++ *--------------------------------------------------------------------------*/
++static void os_cache_invalidate(void *mem_ptr, int size)
++{
++ dma_cache_inv((unsigned long)mem_ptr, size);
++}
++
++static void os_cache_writeback(void *mem_ptr, int size)
++{
++ dma_cache_wback_inv((unsigned long)mem_ptr, size);
++}
++
++/*-----------------------------------------------------------------------------
++ * Support functions.
++ *---------------------------------------------------------------------------*/
++
++static void hal_drv_unregister_isr(OS_DEVICE *p_dev, int intr)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_ISR_INFO_T *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
++ intr = LNXINTNUM(intr);
++
++ free_irq(p_isr_cb_param->intr, p_isr_cb_param);
++
++ dbgPrint("cpmac_hal_unregister called for the intr %d for unit %x and isr_cb_param %x.\n",
++ intr, p_cpmac_priv->instance_num, (unsigned int )&p_cpmac_priv->cpmac_isr);
++}
++
++
++static void hal_drv_register_isr(OS_DEVICE *p_dev,
++ CPMAC_HAL_ISR_FUNC_T hal_isr, int intr)
++{
++ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
++ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
++ CPMAC_ISR_INFO_T *p_isr_cb_param = &p_cpmac_priv->cpmac_isr;
++ intr = LNXINTNUM(intr);
++
++ dbgPrint("osRegister called for the intr %d for device %x and p_isr_cb_param %x.\n",
++ intr, (bit32u)p_dev, (bit32u)p_isr_cb_param);
++
++ p_isr_cb_param->owner = p_drv_hal;
++ p_isr_cb_param->hal_isr = hal_isr;
++ p_isr_cb_param->intr = intr;
++
++ tasklet_init(&p_isr_cb_param->tasklet, cpmac_handle_tasklet, (unsigned long)p_isr_cb_param);
++ dbgPrint("Success in registering irq %d for Cpmac unit# %d.\n", intr, p_cpmac_priv->instance_num);
++}
++
++/*---------------------------------------------------------------------------
++ * FUNCTIONS called by the CPMAC Net Device.
++ *-------------------------------------------------------------------------*/
++static int load_os_funcs(OS_FUNCTIONS *os_func)
++{
++ dbgPrint("os_init_module: Start\n");
++ if( os_func == 0 )
++ {
++ return(sizeof(OS_FUNCTIONS));
++ }
++
++ os_func->Control = cpmac_hal_control;
++ os_func->CriticalOn = os_critical_on;
++ os_func->CriticalOff = os_critical_off;
++ os_func->DataCacheHitInvalidate = os_cache_invalidate;
++ os_func->DataCacheHitWriteback = os_cache_writeback;
++ os_func->DeviceFindInfo = os_find_device;
++ os_func->DeviceFindParmUint = os_find_parm_u_int;
++ os_func->DeviceFindParmValue= os_find_parm_val;
++ os_func->Free = os_free;
++ os_func->FreeRxBuffer = os_free_buffer;
++ os_func->FreeDev = os_free_dev;
++ os_func->FreeDmaXfer = os_free_dma_xfer;
++ os_func->IsrRegister = hal_drv_register_isr;
++ os_func->IsrUnRegister = hal_drv_unregister_isr;
++ os_func->Malloc = os_malloc;
++ os_func->MallocDev = os_malloc_dev;
++ os_func->MallocDmaXfer = os_malloc_dma_xfer;
++ os_func->MallocRxBuffer = cpmac_hal_malloc_buffer;
++ os_func->Memset = memset;
++ os_func->Printf = printk;
++ os_func->Receive = cpmac_hal_receive;
++ os_func->SendComplete = cpmac_hal_send_complete;
++ os_func->Strcmpi = cpmac_ci_strcmp;
++ os_func->TeardownComplete = cpmac_hal_tear_down_complete;
++ os_func->Strstr = strstr;
++ os_func->Strtoul = simple_strtol;
++ os_func->Sprintf = sprintf;
++ os_func->Strlen = strlen;
++
++ dbgPrint("os_init_module: Leave\n");
++
++ return(0);
++}
++
++
++int cpmac_drv_init(CPMAC_DRV_HAL_INFO_T *p_drv_hal)
++{
++ HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
++ HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
++
++ return(p_hal_funcs->Init(p_hal_dev));
++}
++
++int cpmac_drv_cleanup(CPMAC_DRV_HAL_INFO_T *p_drv_hal)
++{
++ HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
++ HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
++
++ int ret_val = p_hal_funcs->Shutdown(p_hal_dev);
++
++#if 0
++ if(ret_val == 0)
++ kfree(p_hal_funcs);
++ else
++ ret_val = -1;
++#endif
++
++ kfree(p_drv_hal->os_funcs);
++
++ return (ret_val);
++}
++
++int cpmac_drv_tx_setup(HAL_FUNCTIONS *p_hal_funcs,
++ HAL_DEVICE *p_hal_dev,
++ CPMAC_TX_CHAN_INFO_T *p_tx_chan_info)
++{
++ int ret_val = 0;
++ int count = 0;
++ CHANNEL_INFO chan_info;
++
++ /* Let's setup the TX Channels. */
++ for(count=0; count < p_tx_chan_info->cfg_chan; count++)
++ {
++ chan_info.Channel = count;
++ chan_info.Direction = DIRECTION_TX;
++ chan_info.TxNumBuffers = p_tx_chan_info->chan[count].num_BD;
++ chan_info.TxServiceMax = p_tx_chan_info->chan[count].service_max;
++ chan_info.TxNumQueues = 0;
++
++ if((ret_val = p_hal_funcs->ChannelSetup(p_hal_dev, &chan_info,
++ NULL)) != 0)
++ {
++ errPrint("Error in opening channel %d for TX.\n", count);
++ ret_val = -1;
++ break;
++ }
++
++ p_tx_chan_info->opened_chan++;
++ }
++
++ return(ret_val);
++}
++
++int cpmac_drv_rx_setup(HAL_FUNCTIONS *p_hal_funcs,
++ HAL_DEVICE *p_hal_dev,
++ CPMAC_RX_CHAN_INFO_T *p_rx_chan_info)
++{
++ int ret_val = 0;
++ CHANNEL_INFO chan_info;
++
++ chan_info.Channel = 0;
++ chan_info.Direction = DIRECTION_RX;
++ chan_info.RxBufSize = p_rx_chan_info->chan[0].buffer_size;
++ chan_info.RxBufferOffset= p_rx_chan_info->chan[0].buffer_offset;
++ chan_info.RxNumBuffers = p_rx_chan_info->chan[0].num_BD;
++ chan_info.RxServiceMax = p_rx_chan_info->chan[0].service_max;
++
++ if(p_hal_funcs->ChannelSetup(p_hal_dev, &chan_info, p_rx_chan_info) != 0)
++ {
++ errPrint("Error in opening channel %d for RX.\n", 0);
++ ret_val = -1;
++ }
++
++ return(ret_val);
++}
++
++int cpmac_drv_start(CPMAC_DRV_HAL_INFO_T *p_drv_hal,
++ CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
++ CPMAC_RX_CHAN_INFO_T *p_rx_chan_info,
++ unsigned int flags)
++{
++ int ret_val = 0;
++ HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
++ HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
++
++ dbgPrint("It is in cpmac_drv_start for %x.\n", (unsigned int)p_drv_hal);
++
++ if(flags & CHAN_SETUP)
++ {
++ if(cpmac_drv_tx_setup(p_hal_funcs, p_hal_dev,
++ p_tx_chan_info)!=0)
++ {
++ errPrint("Failed to set up tx channel(s).\n");
++ ret_val = -1;
++ }
++ else if(cpmac_drv_rx_setup(p_hal_funcs, p_hal_dev,
++ p_rx_chan_info)!=0)
++ {
++ errPrint("Failed to set up rx channel.\n");
++ ret_val = -1;
++ }
++ else
++ {
++ ret_val = 0;
++ }
++ }
++
++ /* Error in setting up the Channels, quit. */
++ if((ret_val == 0) && (ret_val = p_hal_funcs->Open(p_hal_dev)) != 0)
++ {
++ errPrint("failed to open the HAL!!!.\n");
++ ret_val = -1;
++ }
++
++ return (ret_val);
++} /* cpmac_drv_start */
++
++
++
++int cpmac_drv_tx_teardown(HAL_FUNCTIONS *p_hal_funcs,
++ HAL_DEVICE *p_hal_dev,
++ CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
++ unsigned int flags)
++{
++ int ret_val = 0;
++ int count = 0;
++
++ /* Let's setup the TX Channels. */
++ for(; p_tx_chan_info->opened_chan > 0;
++ p_tx_chan_info->opened_chan--, count++)
++ {
++ if(p_hal_funcs->ChannelTeardown(p_hal_dev, count, flags) != 0)
++ {
++ errPrint("Error in tearing down channel %d for TX.\n", count);
++ ret_val = -1;
++ break;
++ }
++ }
++
++ return(ret_val);
++}
++
++
++int cpmac_drv_rx_teardown(HAL_FUNCTIONS *p_hal_funcs,
++ HAL_DEVICE *p_hal_dev,
++ unsigned int flags)
++{
++ int ret_val = 0;
++
++ if(p_hal_funcs->ChannelTeardown(p_hal_dev, 0, flags) != 0)
++ {
++ errPrint("Error in tearing down channel %d for RX.\n", 0);
++ ret_val = -1;
++ }
++
++ return(ret_val);
++}
++
++int cpmac_drv_stop(CPMAC_DRV_HAL_INFO_T *p_drv_hal,
++ CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
++ CPMAC_RX_CHAN_INFO_T *p_rx_chan_info,
++ unsigned int flags)
++{
++ HAL_DEVICE *p_hal_dev = p_drv_hal->hal_dev;
++ HAL_FUNCTIONS *p_hal_funcs = p_drv_hal->hal_funcs;
++ int ret_val = 0;
++
++ if(flags & CHAN_TEARDOWN)
++ {
++ unsigned int chan_flags = 0;
++
++ if(flags & FREE_BUFFER) chan_flags |= 0x4; /* full tear down */
++ if(flags & BLOCKING) chan_flags |= 0x8; /* blocking call */
++
++ dbgPrint("The teardown flags are %d.\n", flags);
++ dbgPrint("The teardown chan flags are %d.\n", chan_flags);
++
++ if(cpmac_drv_tx_teardown(p_hal_funcs, p_hal_dev,
++ p_tx_chan_info, chan_flags | 0x1) != 0)
++ {
++ ret_val = -1;
++ errPrint("The tx channel teardown failed.\n");
++ }
++ else if(cpmac_drv_rx_teardown(p_hal_funcs, p_hal_dev, chan_flags | 0x2) != 0)
++ {
++ ret_val = -1;
++ errPrint("The rx channel teardown failed.\n");
++ }
++ else
++ {
++ ;
++ }
++ }
++
++ if(ret_val == 0)
++ {
++ int close_flags = 1;
++
++ if(flags & FREE_BUFFER) close_flags = 2;
++// if(flags & COMPLETE) close_flags = 3;
++
++ if(p_hal_funcs->Close(p_hal_dev, close_flags) != 0)
++ {
++ ret_val = -1;
++ }
++ }
++
++ return(ret_val);
++}
++
++int cpmac_drv_init_module(CPMAC_DRV_HAL_INFO_T *p_drv_hal, OS_DEVICE *p_os_dev, int inst)
++{
++ int ret_val = -1;
++ int hal_func_size;
++
++ dbgPrint("Entering the CpmacInitModule for the inst %d \n", inst);
++
++ if((p_drv_hal->os_funcs = kmalloc(sizeof(OS_FUNCTIONS), GFP_KERNEL)) == NULL)
++ {
++ errPrint("Failed to allocate memory for OS_FUNCTIONS.\n");
++ }
++ else if(load_os_funcs(p_drv_hal->os_funcs) != 0)
++ {
++ errPrint("Failed to load OS funcs.\n");
++ os_free(p_drv_hal->os_funcs);
++ }
++ else if(halCpmacInitModule(&p_drv_hal->hal_dev, p_os_dev,
++ &p_drv_hal->hal_funcs, p_drv_hal->os_funcs,
++ sizeof(*p_drv_hal->os_funcs),
++ &hal_func_size, inst) != 0)
++ {
++ errPrint("halCpmacInitModule failed for inst %d \n", inst);
++ os_free(p_drv_hal->os_funcs);
++ }
++ else if(p_drv_hal->hal_funcs->Probe(p_drv_hal->hal_dev) != 0)
++ {
++ errPrint("halCpmacProbe failed for inst %d \n", inst);
++ os_free(p_drv_hal->os_funcs);
++ }
++ else
++ {
++ /* every thing went well. */
++ ret_val = 0;
++ }
++
++ return (ret_val);
++}
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpmacHalLx.h linux.dev/drivers/net/avalanche_cpmac/cpmacHalLx.h
+--- linux.old/drivers/net/avalanche_cpmac/cpmacHalLx.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpmacHalLx.h 2005-07-12 02:48:42.044593000 +0200
+@@ -0,0 +1,51 @@
++/******************************************************************************
++ * FILE PURPOSE: CPMAC Linux Device Driver HAL support Header
++ ******************************************************************************
++ * FILE NAME: cpmacHalVx.h
++ *
++ * DESCRIPTION: CPMAC Linux Device Driver Header
++ *
++ * REVISION HISTORY:
++ *
++ * Date Description Author
++ *-----------------------------------------------------------------------------
++ * 27 Nov 2002 Initial Creation Suraj S Iyer
++ * 09 Jun 2003 Updates for GA Suraj S Iyer
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++#ifndef __CPMAC_HAL_LX_H
++#define __CPMAC_HAL_LX_H
++
++
++typedef struct net_device OS_DEVICE;
++typedef struct sk_buff OS_RECEIVEINFO;
++typedef struct sk_buff OS_SENDINFO;
++
++#ifdef DEBUG
++typedef void HAL_RECEIVEINFO;
++typedef void HAL_DEVICE;
++typedef void OS_SETUP;
++#endif
++
++#define OS_SETUP void
++#define HAL_DEVICE void
++#define HAL_RECEIVEINFO void
++
++#define _CPHAL_CPMAC
++
++#include "cpswhal_cpmac.h"
++#include "cpmac.h"
++
++int cpmac_drv_start(CPMAC_DRV_HAL_INFO_T *, CPMAC_TX_CHAN_INFO_T*,
++ CPMAC_RX_CHAN_INFO_T *, unsigned int);
++int cpmac_drv_cleanup(CPMAC_DRV_HAL_INFO_T *);
++int cpmac_drv_init(CPMAC_DRV_HAL_INFO_T*);
++int cpmac_drv_close(CPMAC_DRV_HAL_INFO_T*);
++int cpmac_drv_open(CPMAC_DRV_HAL_INFO_T*);
++int cpmac_drv_init_module(CPMAC_DRV_HAL_INFO_T*, OS_DEVICE*, int);
++int cpmac_drv_stop(CPMAC_DRV_HAL_INFO_T *p_drv_hal,CPMAC_TX_CHAN_INFO_T *p_tx_chan_info,
++ CPMAC_RX_CHAN_INFO_T *p_rx_chan_info,unsigned int flags);
++
++#endif
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpmac_reg.h linux.dev/drivers/net/avalanche_cpmac/cpmac_reg.h
+--- linux.old/drivers/net/avalanche_cpmac/cpmac_reg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpmac_reg.h 2005-07-12 02:48:42.045593000 +0200
+@@ -0,0 +1,406 @@
++/****************************************************************************
++ TNETD73xx Software Support
++ Copyright(c) 2000, Texas Instruments Incorporated. All Rights Reserved.
++
++ FILE: cpmac_reg.h Register definitions for the CPMAC module
++
++ DESCRIPTION:
++ This include file contains register definitions for the
++ CPMAC module.
++
++ HISTORY:
++ 15Nov00 BEGR Original version written
++ 30May02 MICK Added bits for Int Vector
++ 19Sep02 MICK Added INT_ACK per Channel
++ 08Nov02 GDUN Updated to use base
++ 12Nov02 MICK Incorporated into CPHAL
++*****************************************************************************/
++#ifndef _INC_CPMAC_REG
++#define _INC_CPMAC_REG
++
++#ifndef MEM_PTR
++#define MEM_PTR volatile bit32u *
++#endif
++
++/***************************************************************************
++ *
++ * C P M A C M E M O R Y M A P
++ *
++ **************************************************************************/
++
++#define pCPMAC_TX_IDVER(base) ((MEM_PTR)(base+0x000))
++#define CPMAC_TX_IDVER(base) (*pCPMAC_TX_IDVER(base))
++#define pCPMAC_TX_CONTROL(base) ((MEM_PTR)(base+0x004))
++#define CPMAC_TX_CONTROL(base) (*pCPMAC_TX_CONTROL(base))
++#define pCPMAC_TX_TEARDOWN(base) ((MEM_PTR)(base+0x008))
++#define CPMAC_TX_TEARDOWN(base) (*pCPMAC_TX_TEARDOWN(base))
++#define pCPMAC_RX_IDVER(base) ((MEM_PTR)(base+0x010))
++#define CPMAC_RX_IDVER(base) (*pCPMAC_RX_IDVER(base))
++#define pCPMAC_RX_CONTROL(base) ((MEM_PTR)(base+0x014))
++#define CPMAC_RX_CONTROL(base) (*pCPMAC_RX_CONTROL(base))
++#define pCPMAC_RX_TEARDOWN(base) ((MEM_PTR)(base+0x018))
++#define CPMAC_RX_TEARDOWN(base) (*pCPMAC_RX_TEARDOWN(base))
++#define pCPMAC_RX_MBP_ENABLE(base) ((MEM_PTR)(base+0x100))
++#define CPMAC_RX_MBP_ENABLE(base) (*pCPMAC_RX_MBP_ENABLE(base))
++#define pCPMAC_RX_UNICAST_SET(base) ((MEM_PTR)(base+0x104))
++#define CPMAC_RX_UNICAST_SET(base) (*pCPMAC_RX_UNICAST_SET(base))
++#define pCPMAC_RX_UNICAST_CLEAR(base) ((MEM_PTR)(base+0x108))
++#define CPMAC_RX_UNICAST_CLEAR(base) (*pCPMAC_RX_UNICAST_CLEAR(base))
++#define pCPMAC_RX_MAXLEN(base) ((MEM_PTR)(base+0x10C))
++#define CPMAC_RX_MAXLEN(base) (*pCPMAC_RX_MAXLEN(base))
++#define pCPMAC_RX_BUFFER_OFFSET(base) ((MEM_PTR)(base+0x110))
++#define CPMAC_RX_BUFFER_OFFSET(base) (*pCPMAC_RX_BUFFER_OFFSET(base))
++#define pCPMAC_RX_FILTERLOWTHRESH(base) ((MEM_PTR)(base+0x114))
++#define CPMAC_RX_FILTERLOWTHRESH(base) (*pCPMAC_RX_FILTERLOWTHRESH(base))
++#define pCPMAC_RX0_FLOWTHRESH(base) ((MEM_PTR)(base+0x120))
++#define CPMAC_RX0_FLOWTHRESH(base) (*pCPMAC_RX0_FLOWTHRESH(base))
++#define pCPMAC_RX1_FLOWTHRESH(base) ((MEM_PTR)(base+0x124))
++#define CPMAC_RX1_FLOWTHRESH(base) (*pCPMAC_RX1_FLOWTHRESH(base))
++#define pCPMAC_RX2_FLOWTHRESH(base) ((MEM_PTR)(base+0x128))
++#define CPMAC_RX2_FLOWTHRESH(base) (*pCPMAC_RX2_FLOWTHRESH(base))
++#define pCPMAC_RX3_FLOWTHRESH(base) ((MEM_PTR)(base+0x12C))
++#define CPMAC_RX3_FLOWTHRESH(base) (*pCPMAC_RX3_FLOWTHRESH(base))
++#define pCPMAC_RX4_FLOWTHRESH(base) ((MEM_PTR)(base+0x130))
++#define CPMAC_RX4_FLOWTHRESH(base) (*pCPMAC_RX4_FLOWTHRESH(base))
++#define pCPMAC_RX5_FLOWTHRESH(base) ((MEM_PTR)(base+0x134))
++#define CPMAC_RX5_FLOWTHRESH(base) (*pCPMAC_RX5_FLOWTHRESH(base))
++#define pCPMAC_RX6_FLOWTHRESH(base) ((MEM_PTR)(base+0x138))
++#define CPMAC_RX6_FLOWTHRESH(base) (*pCPMAC_RX6_FLOWTHRESH(base))
++#define pCPMAC_RX7_FLOWTHRESH(base) ((MEM_PTR)(base+0x13C))
++#define CPMAC_RX7_FLOWTHRESH(base) (*pCPMAC_RX7_FLOWTHRESH(base))
++#define pCPMAC_RX0_FREEBUFFER(base) ((MEM_PTR)(base+0x140))
++#define CPMAC_RX0_FREEBUFFER(base) (*pCPMAC_RX0_FREEBUFFER(base))
++#define pCPMAC_RX1_FREEBUFFER(base) ((MEM_PTR)(base+0x144))
++#define CPMAC_RX1_FREEBUFFER(base) (*pCPMAC_RX1_FREEBUFFER(base))
++#define pCPMAC_RX2_FREEBUFFER(base) ((MEM_PTR)(base+0x148))
++#define CPMAC_RX2_FREEBUFFER(base) (*pCPMAC_RX2_FREEBUFFER(base))
++#define pCPMAC_RX3_FREEBUFFER(base) ((MEM_PTR)(base+0x14C))
++#define CPMAC_RX3_FREEBUFFER(base) (*pCPMAC_RX3_FREEBUFFER(base))
++#define pCPMAC_RX4_FREEBUFFER(base) ((MEM_PTR)(base+0x150))
++#define CPMAC_RX4_FREEBUFFER(base) (*pCPMAC_RX4_FREEBUFFER(base))
++#define pCPMAC_RX5_FREEBUFFER(base) ((MEM_PTR)(base+0x154))
++#define CPMAC_RX5_FREEBUFFER(base) (*pCPMAC_RX5_FREEBUFFER(base))
++#define pCPMAC_RX6_FREEBUFFER(base) ((MEM_PTR)(base+0x158))
++#define CPMAC_RX6_FREEBUFFER(base) (*pCPMAC_RX6_FREEBUFFER(base))
++#define pCPMAC_RX7_FREEBUFFER(base) ((MEM_PTR)(base+0x15C))
++#define CPMAC_RX7_FREEBUFFER(base) (*pCPMAC_RX7_FREEBUFFER(base))
++#define pCPMAC_MACCONTROL(base) ((MEM_PTR)(base+0x160))
++#define CPMAC_MACCONTROL(base) (*pCPMAC_MACCONTROL(base))
++#define pCPMAC_MACSTATUS(base) ((MEM_PTR)(base+0x164))
++#define CPMAC_MACSTATUS(base) (*pCPMAC_MACSTATUS(base))
++#define pCPMAC_EMCONTROL(base) ((MEM_PTR)(base+0x168))
++#define CPMAC_EMCONTROL(base) (*pCPMAC_EMCONTROL(base))
++#define pCPMAC_TX_INTSTAT_RAW(base) ((MEM_PTR)(base+0x170))
++#define CPMAC_TX_INTSTAT_RAW(base) (*pCPMAC_TX_INTSTAT_RAW(base))
++#define pCPMAC_TX_INTSTAT_MASKED(base) ((MEM_PTR)(base+0x174))
++#define CPMAC_TX_INTSTAT_MASKED(base) (*pCPMAC_TX_INTSTAT_MASKED(base))
++#define pCPMAC_TX_INTMASK_SET(base) ((MEM_PTR)(base+0x178))
++#define CPMAC_TX_INTMASK_SET(base) (*pCPMAC_TX_INTMASK_SET(base))
++#define pCPMAC_TX_INTMASK_CLEAR(base) ((MEM_PTR)(base+0x17C))
++#define CPMAC_TX_INTMASK_CLEAR(base) (*pCPMAC_TX_INTMASK_CLEAR(base))
++#define pCPMAC_MAC_IN_VECTOR(base) ((MEM_PTR)(base+0x180))
++#define CPMAC_MAC_IN_VECTOR(base) (*pCPMAC_MAC_IN_VECTOR(base))
++#define pCPMAC_MAC_EOI_VECTOR(base) ((MEM_PTR)(base+0x184))
++#define CPMAC_MAC_EOI_VECTOR(base) (*pCPMAC_MAC_EOI_VECTOR(base))
++#define pCPMAC_RX_INTSTAT_RAW(base) ((MEM_PTR)(base+0x190))
++#define CPMAC_RX_INTSTAT_RAW(base) (*pCPMAC_RX_INTSTAT_RAW(base))
++#define pCPMAC_RX_INTSTAT_MASKED(base) ((MEM_PTR)(base+0x194))
++#define CPMAC_RX_INTSTAT_MASKED(base) (*pCPMAC_RX_INTSTAT_MASKED(base))
++#define pCPMAC_RX_INTMASK_SET(base) ((MEM_PTR)(base+0x198))
++#define CPMAC_RX_INTMASK_SET(base) (*pCPMAC_RX_INTMASK_SET(base))
++#define pCPMAC_RX_INTMASK_CLEAR(base) ((MEM_PTR)(base+0x19C))
++#define CPMAC_RX_INTMASK_CLEAR(base) (*pCPMAC_RX_INTMASK_CLEAR(base))
++#define pCPMAC_MAC_INTSTAT_RAW(base) ((MEM_PTR)(base+0x1A0))
++#define CPMAC_MAC_INTSTAT_RAW(base) (*pCPMAC_MAC_INTSTAT_RAW(base))
++#define pCPMAC_MAC_INTSTAT_MASKED(base) ((MEM_PTR)(base+0x1A4))
++#define CPMAC_MAC_INTSTAT_MASKED(base) (*pCPMAC_MAC_INTSTAT_MASKED(base))
++#define pCPMAC_MAC_INTMASK_SET(base) ((MEM_PTR)(base+0x1A8))
++#define CPMAC_MAC_INTMASK_SET(base) (*pCPMAC_MAC_INTMASK_SET(base))
++#define pCPMAC_MAC_INTMASK_CLEAR(base) ((MEM_PTR)(base+0x1AC))
++#define CPMAC_MAC_INTMASK_CLEAR(base) (*pCPMAC_MAC_INTMASK_CLEAR(base))
++#define pCPMAC_MACADDRLO_0(base) ((MEM_PTR)(base+0x1B0))
++#define CPMAC_MACADDRLO_0(base) (*pCPMAC_MACADDRLO_0(base))
++#define pCPMAC_MACADDRLO_1(base) ((MEM_PTR)(base+0x1B4))
++#define CPMAC_MACADDRLO_1(base) (*pCPMAC_MACADDRLO_1(base))
++#define pCPMAC_MACADDRLO_2(base) ((MEM_PTR)(base+0x1B8))
++#define CPMAC_MACADDRLO_2(base) (*pCPMAC_MACADDRLO_2(base))
++#define pCPMAC_MACADDRLO_3(base) ((MEM_PTR)(base+0x1BC))
++#define CPMAC_MACADDRLO_3(base) (*pCPMAC_MACADDRLO_3(base))
++#define pCPMAC_MACADDRLO_4(base) ((MEM_PTR)(base+0x1C0))
++#define CPMAC_MACADDRLO_4(base) (*pCPMAC_MACADDRLO_4(base))
++#define pCPMAC_MACADDRLO_5(base) ((MEM_PTR)(base+0x1C4))
++#define CPMAC_MACADDRLO_5(base) (*pCPMAC_MACADDRLO_5(base))
++#define pCPMAC_MACADDRLO_6(base) ((MEM_PTR)(base+0x1C8))
++#define CPMAC_MACADDRLO_6(base) (*pCPMAC_MACADDRLO_6(base))
++#define pCPMAC_MACADDRLO_7(base) ((MEM_PTR)(base+0x1CC))
++#define CPMAC_MACADDRLO_7(base) (*pCPMAC_MACADDRLO_7(base))
++#define pCPMAC_MACADDRMID(base) ((MEM_PTR)(base+0x1D0))
++#define CPMAC_MACADDRMID(base) (*pCPMAC_MACADDRMID(base))
++#define pCPMAC_MACADDRHI(base) ((MEM_PTR)(base+0x1D4))
++#define CPMAC_MACADDRHI(base) (*pCPMAC_MACADDRHI(base))
++#define pCPMAC_MACHASH1(base) ((MEM_PTR)(base+0x1D8))
++#define CPMAC_MACHASH1(base) (*pCPMAC_MACHASH1(base))
++#define pCPMAC_MACHASH2(base) ((MEM_PTR)(base+0x1DC))
++#define CPMAC_MACHASH2(base) (*pCPMAC_MACHASH2(base))
++#define pCPMAC_BOFFTEST(base) ((MEM_PTR)(base+0x1E0))
++#define CPMAC_BOFFTEST(base) (*pCPMAC_BOFFTEST(base))
++#define pCPMAC_PACTEST(base) ((MEM_PTR)(base+0x1E4))
++#define CPMAC_PACTEST(base) (*pCPMAC_PACTEST(base))
++#define pCPMAC_RXPAUSE(base) ((MEM_PTR)(base+0x1E8))
++#define CPMAC_RXPAUSE(base) (*pCPMAC_RXPAUSE(base))
++#define pCPMAC_TXPAUSE(base) ((MEM_PTR)(base+0x1EC))
++#define CPMAC_TXPAUSE(base) (*pCPMAC_TXPAUSE(base))
++/* STATISTICS */
++#define pCPMAC_RXGOODFRAMES(base) ((MEM_PTR)(base+0x200))
++#define CPMAC_RXGOODFRAMES(base) (*pCPMAC_RXGOODFRAMES(base))
++#define pCPMAC_RXBROADCASTFRAMES(base) ((MEM_PTR)(base+0x204))
++#define CPMAC_RXBROADCASTFRAMES(base) (*pCPMAC_RXBROADCASTFRAMES(base))
++#define pCPMAC_RXMULTICASTFRAMES(base) ((MEM_PTR)(base+0x208))
++#define CPMAC_RXMULTICASTFRAMES(base) (*pCPMAC_RXMULTICASTFRAMES(base))
++#define pCPMAC_RXPAUSEFRAMES(base) ((MEM_PTR)(base+0x20C))
++#define CPMAC_RXPAUSEFRAMES(base) (*pCPMAC_RXPAUSEFRAMES(base))
++#define pCPMAC_RXCRCERRORS(base) ((MEM_PTR)(base+0x210))
++#define CPMAC_RXCRCERRORS(base) (*pCPMAC_RXCRCERRORS(base))
++#define pCPMAC_RXALIGNCODEERRORS(base) ((MEM_PTR)(base+0x214))
++#define CPMAC_RXALIGNCODEERRORS(base) (*pCPMAC_RXALIGNCODEERRORS(base))
++#define pCPMAC_RXOVERSIZEDFRAMES(base) ((MEM_PTR)(base+0x218))
++#define CPMAC_RXOVERSIZEDFRAMES(base) (*pCPMAC_RXOVERSIZEDFRAMES(base))
++#define pCPMAC_RXJABBERFRAMES(base) ((MEM_PTR)(base+0x21C))
++#define CPMAC_RXJABBERFRAMES(base) (*pCPMAC_RXJABBERFRAMES(base))
++#define pCPMAC_RXUNDERSIZEDFRAMES(base) ((MEM_PTR)(base+0x220))
++#define CPMAC_RXUNDERSIZEDFRAMES(base) (*pCPMAC_RXUNDERSIZEDFRAMES(base))
++#define pCPMAC_RXFRAGMENTS(base) ((MEM_PTR)(base+0x224))
++#define CPMAC_RXFRAGMENTS(base) (*pCPMAC_RXFRAGMENTS(base))
++#define pCPMAC_RXFILTEREDFRAMES(base) ((MEM_PTR)(base+0x228))
++#define CPMAC_RXFILTEREDFRAMES(base) (*pCPMAC_RXFILTEREDFRAMES(base))
++#define pCPMAC_RXQOSFILTEREDFRAMES(base) ((MEM_PTR)(base+0x22C))
++#define CPMAC_RXQOSFILTEREDFRAMES(base) (*pCPMAC_RXQOSFILTEREDFRAMES(base))
++#define pCPMAC_RXOCTETS(base) ((MEM_PTR)(base+0x230))
++#define CPMAC_RXOCTETS(base) (*pCPMAC_RXOCTETS(base))
++#define pCPMAC_TXGOODFRAMES(base) ((MEM_PTR)(base+0x234))
++#define CPMAC_TXGOODFRAMES(base) (*pCPMAC_TXGOODFRAMES(base))
++#define pCPMAC_TXBROADCASTFRAMES(base) ((MEM_PTR)(base+0x238))
++#define CPMAC_TXBROADCASTFRAMES(base) (*pCPMAC_TXBROADCASTFRAMES(base))
++#define pCPMAC_TXMULTICASTFRAMES(base) ((MEM_PTR)(base+0x23C))
++#define CPMAC_TXMULTICASTFRAMES(base) (*pCPMAC_TXMULTICASTFRAMES(base))
++#define pCPMAC_TXPAUSEFRAMES(base) ((MEM_PTR)(base+0x240))
++#define CPMAC_TXPAUSEFRAMES(base) (*pCPMAC_TXPAUSEFRAMES(base))
++#define pCPMAC_TXDEFERREDFRAMES(base) ((MEM_PTR)(base+0x244))
++#define CPMAC_TXDEFERREDFRAMES(base) (*pCPMAC_TXDEFERREDFRAMES(base))
++#define pCPMAC_TXCOLLISIONFRAMES(base) ((MEM_PTR)(base+0x248))
++#define CPMAC_TXCOLLISIONFRAMES(base) (*pCPMAC_TXCOLLISIONFRAMES(base))
++#define pCPMAC_TXSINGLECOLLFRAMES(base) ((MEM_PTR)(base+0x24C))
++#define CPMAC_TXSINGLECOLLFRAMES(base) (*pCPMAC_TXSINGLECOLLFRAMES(base))
++#define pCPMAC_TXMULTCOLLFRAMES(base) ((MEM_PTR)(base+0x250))
++#define CPMAC_TXMULTCOLLFRAMES(base) (*pCPMAC_TXMULTCOLLFRAMES(base))
++#define pCPMAC_TXEXCESSIVECOLLISIONS(base) ((MEM_PTR)(base+0x254))
++#define CPMAC_TXEXCESSIVECOLLISIONS(base) (*pCPMAC_TXEXCESSIVECOLLISIONS(base))
++#define pCPMAC_TXLATECOLLISIONS(base) ((MEM_PTR)(base+0x258))
++#define CPMAC_TXLATECOLLISIONS(base) (*pCPMAC_TXLATECOLLISIONS(base))
++#define pCPMAC_TXUNDERRUN(base) ((MEM_PTR)(base+0x25C))
++#define CPMAC_TXUNDERRUN(base) (*pCPMAC_TXUNDERRUN(base))
++#define pCPMAC_TXCARRIERSENSEERRORS(base) ((MEM_PTR)(base+0x260))
++#define CPMAC_TXCARRIERSENSEERRORS(base) (*pCPMAC_TXCARRIERSENSEERRORS(base))
++#define pCPMAC_TXOCTETS(base) ((MEM_PTR)(base+0x264))
++#define CPMAC_TXOCTETS(base) (*pCPMAC_TXOCTETS(base))
++#define pCPMAC_64OCTETFRAMES(base) ((MEM_PTR)(base+0x268))
++#define CPMAC_64OCTETFRAMES(base) (*pCPMAC_64OCTETFRAMES(base))
++#define pCPMAC_65T127OCTETFRAMES(base) ((MEM_PTR)(base+0x26C))
++#define CPMAC_65T127OCTETFRAMES(base) (*pCPMAC_65T127OCTETFRAMES(base))
++#define pCPMAC_128T255OCTETFRAMES(base) ((MEM_PTR)(base+0x270))
++#define CPMAC_128T255OCTETFRAMES(base) (*pCPMAC_128T255OCTETFRAMES(base))
++#define pCPMAC_256T511OCTETFRAMES(base) ((MEM_PTR)(base+0x274))
++#define CPMAC_256T511OCTETFRAMES(base) (*pCPMAC_256T511OCTETFRAMES(base))
++#define pCPMAC_512T1023OCTETFRAMES(base) ((MEM_PTR)(base+0x278))
++#define CPMAC_512T1023OCTETFRAMES(base) (*pCPMAC_512T1023OCTETFRAMES(base))
++#define pCPMAC_1024TUPOCTETFRAMES(base) ((MEM_PTR)(base+0x27C))
++#define CPMAC_1024TUPOCTETFRAMES(base) (*pCPMAC_1024TUPOCTETFRAMES(base))
++#define pCPMAC_NETOCTETS(base) ((MEM_PTR)(base+0x280))
++#define CPMAC_NETOCTETS(base) (*pCPMAC_NETOCTETS(base))
++#define pCPMAC_RXSOFOVERRUNS(base) ((MEM_PTR)(base+0x284))
++#define CPMAC_RXSOFOVERRUNS(base) (*pCPMAC_RXSOFOVERRUNS(base))
++#define pCPMAC_RXMOFOVERRUNS(base) ((MEM_PTR)(base+0x288))
++#define CPMAC_RXMOFOVERRUNS(base) (*pCPMAC_RXMOFOVERRUNS(base))
++#define pCPMAC_RXDMAOVERRUNS(base) ((MEM_PTR)(base+0x28C))
++#define CPMAC_RXDMAOVERRUNS(base) (*pCPMAC_RXDMAOVERRUNS(base))
++
++#define CPMAC_TX_HDP(base,ch) (*(MEM_PTR)(base+0x600+(4*ch)))
++#define pCPMAC_TX0_HDP(base) ((MEM_PTR)(base+0x600))
++#define CPMAC_TX0_HDP(base) (*pCPMAC_TX0_HDP(base))
++#define pCPMAC_TX1_HDP(base) ((MEM_PTR)(base+0x604))
++#define CPMAC_TX1_HDP(base) (*pCPMAC_TX1_HDP(base))
++#define pCPMAC_TX2_HDP(base) ((MEM_PTR)(base+0x608))
++#define CPMAC_TX2_HDP(base) (*pCPMAC_TX2_HDP(base))
++#define pCPMAC_TX3_HDP(base) ((MEM_PTR)(base+0x60C))
++#define CPMAC_TX3_HDP(base) (*pCPMAC_TX3_HDP(base))
++#define pCPMAC_TX4_HDP(base) ((MEM_PTR)(base+0x610))
++#define CPMAC_TX4_HDP(base) (*pCPMAC_TX4_HDP(base))
++#define pCPMAC_TX5_HDP(base) ((MEM_PTR)(base+0x614))
++#define CPMAC_TX5_HDP(base) (*pCPMAC_TX5_HDP(base))
++#define pCPMAC_TX6_HDP(base) ((MEM_PTR)(base+0x618))
++#define CPMAC_TX6_HDP(base) (*pCPMAC_TX6_HDP(base))
++#define pCPMAC_TX7_HDP(base) ((MEM_PTR)(base+0x61C))
++#define CPMAC_TX7_HDP(base) (*pCPMAC_TX7_HDP(base))
++#define CPMAC_RX_HDP(base,ch) (*(MEM_PTR)(base+0x620+(4*ch)))
++#define pCPMAC_RX0_HDP(base) ((MEM_PTR)(base+0x620))
++#define CPMAC_RX0_HDP(base) (*pCPMAC_RX0_HDP(base))
++#define pCPMAC_RX1_HDP(base) ((MEM_PTR)(base+0x624))
++#define CPMAC_RX1_HDP(base) (*pCPMAC_RX1_HDP(base))
++#define pCPMAC_RX2_HDP(base) ((MEM_PTR)(base+0x628))
++#define CPMAC_RX2_HDP(base) (*pCPMAC_RX2_HDP(base))
++#define pCPMAC_RX3_HDP(base) ((MEM_PTR)(base+0x62C))
++#define CPMAC_RX3_HDP(base) (*pCPMAC_RX3_HDP(base))
++#define pCPMAC_RX4_HDP(base) ((MEM_PTR)(base+0x630))
++#define CPMAC_RX4_HDP(base) (*pCPMAC_RX4_HDP(base))
++#define pCPMAC_RX5_HDP(base) ((MEM_PTR)(base+0x634))
++#define CPMAC_RX5_HDP(base) (*pCPMAC_RX5_HDP(base))
++#define pCPMAC_RX6_HDP(base) ((MEM_PTR)(base+0x638))
++#define CPMAC_RX6_HDP(base) (*pCPMAC_RX6_HDP(base))
++#define pCPMAC_RX7_HDP(base) ((MEM_PTR)(base+0x63C))
++#define CPMAC_RX7_HDP(base) (*pCPMAC_RX7_HDP(base))
++
++
++#define CPMAC_TX_INT_ACK(base,ch) (*(MEM_PTR)(base+0x640+(4*ch)))
++
++#define pCPMAC_TX0_INT_ACK(base) ((MEM_PTR)(base+0x640))
++#define CPMAC_TX0_INT_ACK(base) (*pCPMAC_TX0_INT_ACK(base))
++#define pCPMAC_TX1_INT_ACK(base) ((MEM_PTR)(base+0x644))
++#define CPMAC_TX1_INT_ACK(base) (*pCPMAC_TX1_INT_ACK(base))
++#define pCPMAC_TX2_INT_ACK(base) ((MEM_PTR)(base+0x648))
++#define CPMAC_TX2_INT_ACK(base) (*pCPMAC_TX2_INT_ACK(base))
++#define pCPMAC_TX3_INT_ACK(base) ((MEM_PTR)(base+0x64C))
++#define CPMAC_TX3_INT_ACK(base) (*pCPMAC_TX3_INT_ACK(base))
++#define pCPMAC_TX4_INT_ACK(base) ((MEM_PTR)(base+0x650))
++#define CPMAC_TX4_INT_ACK(base) (*pCPMAC_TX4_INT_ACK(base))
++#define pCPMAC_TX5_INT_ACK(base) ((MEM_PTR)(base+0x654))
++#define CPMAC_TX5_INT_ACK(base) (*pCPMAC_TX5_INT_ACK(base))
++#define pCPMAC_TX6_INT_ACK(base) ((MEM_PTR)(base+0x658))
++#define CPMAC_TX6_INT_ACK(base) (*pCPMAC_TX6_INT_ACK(base))
++#define pCPMAC_TX7_INT_ACK(base) ((MEM_PTR)(base+0x65C))
++#define CPMAC_TX7_INT_ACK(base) (*pCPMAC_TX7_INT_ACK(base))
++#define CPMAC_RX_INT_ACK(base,ch) (*(MEM_PTR)(base+0x660+(4*ch)))
++
++#define pCPMAC_RX0_INT_ACK(base) ((MEM_PTR)(base+0x660))
++#define CPMAC_RX0_INT_ACK(base) (*pCPMAC_RX0_INT_ACK(base))
++#define pCPMAC_RX1_INT_ACK(base) ((MEM_PTR)(base+0x664))
++#define CPMAC_RX1_INT_ACK(base) (*pCPMAC_RX1_INT_ACK(base))
++#define pCPMAC_RX2_INT_ACK(base) ((MEM_PTR)(base+0x668))
++#define CPMAC_RX2_INT_ACK(base) (*pCPMAC_RX2_INT_ACK(base))
++#define pCPMAC_RX3_INT_ACK(base) ((MEM_PTR)(base+0x66C))
++#define CPMAC_RX3_INT_ACK(base) (*pCPMAC_RX3_INT_ACK(base))
++#define pCPMAC_RX4_INT_ACK(base) ((MEM_PTR)(base+0x670))
++#define CPMAC_RX4_INT_ACK(base) (*pCPMAC_RX4_INT_ACK(base))
++#define pCPMAC_RX5_INT_ACK(base) ((MEM_PTR)(base+0x674))
++#define CPMAC_RX5_INT_ACK(base) (*pCPMAC_RX5_INT_ACK(base))
++#define pCPMAC_RX6_INT_ACK(base) ((MEM_PTR)(base+0x678))
++#define CPMAC_RX6_INT_ACK(base) (*pCPMAC_RX6_INT_ACK(base))
++#define pCPMAC_RX7_INT_ACK(base) ((MEM_PTR)(base+0x67C))
++#define CPMAC_RX7_INT_ACK(base) (*pCPMAC_RX7_INT_ACK(base))
++
++/****************************************************************************/
++/* */
++/* R E G I S T E R B I T D E F I N I T I O N S */
++/* */
++/****************************************************************************/
++
++/* TX_CONTROL */
++
++#define TX_EN (1 << 0)
++
++/* RX_CONTROL */
++
++#define RX_EN (1 << 0)
++
++/* RX_MBP_ENABLE */
++
++#define RX_PASS_CRC (1 << 30)
++#define RX_QOS_EN (1 << 29)
++#define RX_NO_CHAIN (1 << 28)
++
++#define RX_CMF_EN (1 << 24)
++#define RX_CSF_EN (1 << 23)
++#define RX_CEF_EN (1 << 22)
++#define RX_CAF_EN (1 << 21)
++
++#define RX_PROM_CH(n) (n << 16)
++#define RX_PROM_CH_MASK RX_PROM_CH(7)
++#define RX_PROM_CH_7 RX_PROM_CH(7)
++#define RX_PROM_CH_6 RX_PROM_CH(6)
++#define RX_PROM_CH_5 RX_PROM_CH(5)
++#define RX_PROM_CH_4 RX_PROM_CH(4)
++#define RX_PROM_CH_3 RX_PROM_CH(3)
++#define RX_PROM_CH_2 RX_PROM_CH(2)
++#define RX_PROM_CH_1 RX_PROM_CH(1)
++#define RX_PROM_CH_0 RX_PROM_CH(0)
++
++#define RX_BROAD_EN (1 << 13)
++
++#define RX_BROAD_CH(n) (n << 8)
++#define RX_BROAD_CH_MASK RX_BROAD_CH(7)
++#define RX_BROAD_CH_7 RX_BROAD_CH(7)
++#define RX_BROAD_CH_6 RX_BROAD_CH(6)
++#define RX_BROAD_CH_5 RX_BROAD_CH(5)
++#define RX_BROAD_CH_4 RX_BROAD_CH(4)
++#define RX_BROAD_CH_3 RX_BROAD_CH(3)
++#define RX_BROAD_CH_2 RX_BROAD_CH(2)
++#define RX_BROAD_CH_1 RX_BROAD_CH(1)
++#define RX_BROAD_CH_0 RX_BROAD_CH(0)
++
++#define RX_MULT_EN (1 << 5)
++
++#define RX_MULT_CH(n) (n << 0)
++#define RX_MULT_CH_MASK RX_MULT_CH(7)
++#define RX_MULT_CH_7 RX_MULT_CH(7)
++#define RX_MULT_CH_6 RX_MULT_CH(6)
++#define RX_MULT_CH_5 RX_MULT_CH(5)
++#define RX_MULT_CH_4 RX_MULT_CH(4)
++#define RX_MULT_CH_3 RX_MULT_CH(3)
++#define RX_MULT_CH_2 RX_MULT_CH(2)
++#define RX_MULT_CH_1 RX_MULT_CH(1)
++#define RX_MULT_CH_0 RX_MULT_CH(0)
++
++
++
++/* RX_UNICAST_SET */
++
++#define RX_CH7_EN (1 << 7)
++#define RX_CH6_EN (1 << 6)
++#define RX_CH5_EN (1 << 5)
++#define RX_CH4_EN (1 << 4)
++#define RX_CH3_EN (1 << 3)
++#define RX_CH2_EN (1 << 2)
++#define RX_CH1_EN (1 << 1)
++#define RX_CH0_EN (1 << 0)
++
++
++
++/* MAC control */
++#define TX_PTYPE (1 << 9)
++#define TX_PACE (1 << 6)
++#define MII_EN (1 << 5)
++#define TX_FLOW_EN (1 << 4)
++#define RX_FLOW_EN (1 << 3)
++#define MTEST (1 << 2)
++#define CTRL_LOOPBACK (1 << 1)
++#define FULLDUPLEX (1 << 0)
++
++
++/* IntVec definitions */
++#define MAC_IN_VECTOR_STATUS_INT (1 << 19)
++#define MAC_IN_VECTOR_HOST_INT (1 << 18)
++#define MAC_IN_VECTOR_RX_INT_OR (1 << 17)
++#define MAC_IN_VECTOR_TX_INT_OR (1 << 16)
++#define MAC_IN_VECTOR_RX_INT_VEC (7 << 8)
++#define MAC_IN_VECTOR_TX_INT_VEC (7)
++
++
++/* MacStatus */
++
++#define TX_HOST_ERR_CODE (0xF << 20)
++#define TX_ERR_CH (0x7 << 16)
++#define RX_HOST_ERR_CODE (0xF << 12)
++#define RX_ERR_CH (0x7 << 8)
++#define RX_QOS_ACT (1 << 2)
++#define RX_FLOW_ACT (1 << 1)
++#define TX_FLOW_ACT (1 << 0)
++#endif _INC_CPMAC_REG
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpmdio.c linux.dev/drivers/net/avalanche_cpmac/cpmdio.c
+--- linux.old/drivers/net/avalanche_cpmac/cpmdio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpmdio.c 2005-07-12 02:48:42.046593000 +0200
+@@ -0,0 +1,960 @@
++/***************************************************************************
++** TNETD53xx Software Support
++** Copyright(c) 2002, Texas Instruments Incorporated. All Rights Reserved.
++**
++** FILE: cpmdio.c
++**
++** DESCRIPTION:
++** MDIO Polling State Machine API. Functions will enable mii-Phy
++** negotiation.
++**
++** HISTORY:
++** 01Jan01 Denis, Bill Original
++** 27Mar02 Michael Hanrahan (modified from emacmdio.c)
++** 07May02 Michael Hanrahan replaced clockwait for code delay
++** 10Jul02 Michael Hanrahan more debug, if fallback link is selected
++*****************************************************************************/
++#define __CPHAL_CPMDIO
++
++#include "mdio_reg.h"
++
++#ifdef _CPHAL_CPMAC
++#define mdioPrintf PhyDev->HalDev->OsFunc->Printf
++#else
++#define mdioPrintf printf
++#endif
++
++typedef struct _phy_device
++{
++ bit32u miibase;
++ bit32u inst;
++ bit32u PhyState;
++ bit32u MdixMask;
++ bit32u PhyMask;
++ bit32u MLinkMask;
++ bit32u PhyMode;
++#ifdef _CPHAL_CPMAC
++ HAL_DEVICE *HalDev;
++#endif
++} _PHY_DEVICE;
++
++static void _mdioDelayEmulate(PHY_DEVICE *PhyDev, int ClockWait);
++static void _mdioWaitForAccessComplete(PHY_DEVICE *PhyDev);
++static void _mdioUserAccess(PHY_DEVICE *PhyDev, bit32u method, bit32u regadr, bit32u phyadr, bit32u data);
++static bit32u _mdioUserAccessRead(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr);
++static void _mdioUserAccessWrite(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr, bit32u data);
++
++static void _mdioDisablePhy(PHY_DEVICE *PhyDev,bit32u PhyNum);
++static void _mdioPhyTimeOut(PHY_DEVICE *PhyDev);
++static void _mdioResetPhy(PHY_DEVICE *PhyDev,bit32u PhyNum);
++
++static void _mdioDumpPhy(PHY_DEVICE *PhyDev, bit32u p);
++static void _mdioDumpState(PHY_DEVICE *PhyDev);
++
++/* Auto Mdix */
++static void _mdioMdixDelay(PHY_DEVICE *PhyDev);
++static int _mdioMdixSupported(PHY_DEVICE *PhyDev);
++
++static void _MdioDefaultState (PHY_DEVICE *PhyDev);
++static void _MdioFindingState (PHY_DEVICE *PhyDev);
++static void _MdioFoundState (PHY_DEVICE *PhyDev);
++static void _MdioInitState (PHY_DEVICE *PhyDev);
++static void _MdioLinkedState (PHY_DEVICE *PhyDev);
++static void _MdioLinkWaitState (PHY_DEVICE *PhyDev);
++static void _MdioLoopbackState (PHY_DEVICE *PhyDev);
++static void _MdioNwayStartState(PHY_DEVICE *PhyDev);
++static void _MdioNwayWaitState (PHY_DEVICE *PhyDev);
++
++
++
++#ifndef TRUE
++#define TRUE (1==1)
++#endif
++
++#ifndef FALSE
++#define FALSE (1==2)
++#endif
++
++#define PHY_NOT_FOUND 0xFFFF /* Used in Phy Detection */
++
++/*PhyState breakout */
++
++#define PHY_DEV_OFFSET (0)
++#define PHY_DEV_SIZE (5) /* 5 Bits used */
++#define PHY_DEV_MASK (0x1f<<PHY_DEV_OFFSET)
++
++#define PHY_STATE_OFFSET (PHY_DEV_SIZE+PHY_DEV_OFFSET)
++#define PHY_STATE_SIZE (5) /* 10 Bits used */
++#define PHY_STATE_MASK (0x1f<<PHY_STATE_OFFSET)
++ #define INIT (1<<PHY_STATE_OFFSET)
++ #define FINDING (2<<PHY_STATE_OFFSET)
++ #define FOUND (3<<PHY_STATE_OFFSET)
++ #define NWAY_START (4<<PHY_STATE_OFFSET)
++ #define NWAY_WAIT (5<<PHY_STATE_OFFSET)
++ #define LINK_WAIT (6<<PHY_STATE_OFFSET)
++ #define LINKED (7<<PHY_STATE_OFFSET)
++ #define LOOPBACK (8<<PHY_STATE_OFFSET)
++
++#define PHY_SPEED_OFFSET (PHY_STATE_OFFSET+PHY_STATE_SIZE)
++#define PHY_SPEED_SIZE (1) /* 11 Bits used */
++#define PHY_SPEED_MASK (1<<PHY_SPEED_OFFSET)
++
++#define PHY_DUPLEX_OFFSET (PHY_SPEED_OFFSET+PHY_SPEED_SIZE)
++#define PHY_DUPLEX_SIZE (1) /* 12 Bits used */
++#define PHY_DUPLEX_MASK (1<<PHY_DUPLEX_OFFSET)
++
++#define PHY_TIM_OFFSET (PHY_DUPLEX_OFFSET+PHY_DUPLEX_SIZE)
++#define PHY_TIM_SIZE (10) /* 22 Bits used */
++#define PHY_TIM_MASK (0x3ff<<PHY_TIM_OFFSET)
++ #define PHY_FIND_TO ( 2<<PHY_TIM_OFFSET)
++ #define PHY_RECK_TO (200<<PHY_TIM_OFFSET)
++ #define PHY_LINK_TO (500<<PHY_TIM_OFFSET)
++ #define PHY_NWST_TO (500<<PHY_TIM_OFFSET)
++ #define PHY_NWDN_TO (800<<PHY_TIM_OFFSET)
++ #define PHY_MDIX_TO (274<<PHY_TIM_OFFSET) /* 2.74 Seconds <--Spec and empirical */
++
++#define PHY_SMODE_OFFSET (PHY_TIM_OFFSET+PHY_TIM_SIZE)
++#define PHY_SMODE_SIZE (5) /* 27 Bits used */
++#define PHY_SMODE_MASK (0x1f<<PHY_SMODE_OFFSET)
++ #define SMODE_AUTO (0x10<<PHY_SMODE_OFFSET)
++ #define SMODE_FD100 (0x08<<PHY_SMODE_OFFSET)
++ #define SMODE_HD100 (0x04<<PHY_SMODE_OFFSET)
++ #define SMODE_FD10 (0x02<<PHY_SMODE_OFFSET)
++ #define SMODE_HD10 (0x01<<PHY_SMODE_OFFSET)
++ #define SMODE_ALL (0x1f<<PHY_SMODE_OFFSET)
++
++#define PHY_CHNG_OFFSET (PHY_SMODE_OFFSET+PHY_SMODE_SIZE)
++#define PHY_CHNG_SIZE (1) /* 28 Bits used */
++#define PHY_CHNG_MASK (1<<PHY_CHNG_OFFSET)
++ #define PHY_CHANGE (1<<PHY_CHNG_OFFSET)
++
++#define PHY_TIMEDOUT_OFFSET (PHY_CHNG_OFFSET+PHY_CHNG_SIZE)
++#define PHY_TIMEDOUT_SIZE (1) /* 29 Bits used */
++#define PHY_TIMEDOUT_MASK (1<<PHY_TIMEDOUT_OFFSET)
++ #define PHY_MDIX_SWITCH (1<<PHY_TIMEDOUT_OFFSET)
++
++#define PHY_MDIX_OFFSET (PHY_TIMEDOUT_OFFSET+PHY_TIMEDOUT_SIZE)
++#define PHY_MDIX_SIZE (1) /* 30 Bits used */
++#define PHY_MDIX_MASK (1<<PHY_MDIX_OFFSET)
++ #define PHY_MDIX (1<<PHY_MDIX_OFFSET)
++
++static char *lstate[]={"NULL","INIT","FINDING","FOUND","NWAY_START","NWAY_WAIT","LINK_WAIT","LINKED", "LOOPBACK"};
++static int cpMacDebug;
++
++/* Local MDIO Register Macros */
++
++#define myMDIO_ALIVE MDIO_ALIVE (PhyDev->miibase)
++#define myMDIO_CONTROL MDIO_CONTROL (PhyDev->miibase)
++#define myMDIO_LINK MDIO_LINK (PhyDev->miibase)
++#define myMDIO_LINKINT MDIO_LINKINT (PhyDev->miibase)
++#define myMDIO_USERACCESS MDIO_USERACCESS(PhyDev->miibase, PhyDev->inst)
++#define myMDIO_USERPHYSEL MDIO_USERPHYSEL(PhyDev->miibase, PhyDev->inst)
++#define myMDIO_VER MDIO_VER (PhyDev->miibase)
++
++#ifndef VOLATILE32
++#define VOLATILE32(addr) (*((volatile bit32u *)(addr)))
++#endif
++
++/************************************
++***
++*** Delays at least ClockWait cylces
++*** before returning
++***
++**************************************/
++void _mdioDelayEmulate(PHY_DEVICE *PhyDev, int ClockWait)
++ {
++#ifdef _CPHAL_CPMAC /*+RC3.02*/
++ HAL_DEVICE *HalDev = PhyDev->HalDev; /*+RC3.02*/
++ osfuncSleep((int*)&ClockWait); /*+RC3.02*/
++#else /*+RC3.02*/
++ volatile bit32u i=0;
++ while(ClockWait--)
++ {
++ i |= myMDIO_LINK; /* MDIO register access to burn cycles */
++ }
++#endif
++ }
++
++void _mdioWaitForAccessComplete(PHY_DEVICE *PhyDev)
++ {
++ while((myMDIO_USERACCESS & MDIO_USERACCESS_GO)!=0)
++ {
++ }
++ }
++
++void _mdioUserAccess(PHY_DEVICE *PhyDev, bit32u method, bit32u regadr, bit32u phyadr, bit32u data)
++ {
++ bit32u control;
++
++ control = MDIO_USERACCESS_GO |
++ (method) |
++ (((regadr) << 21) & MDIO_USERACCESS_REGADR) |
++ (((phyadr) << 16) & MDIO_USERACCESS_PHYADR) |
++ ((data) & MDIO_USERACCESS_DATA);
++
++ myMDIO_USERACCESS = control;
++ }
++
++
++
++/************************************
++***
++*** Waits for MDIO_USERACCESS to be ready and reads data
++*** If 'WaitForData' set, waits for read to complete and returns Data,
++*** otherwise returns 0
++*** Note: 'data' is 16 bits but we use 32 bits
++*** to be consistent with rest of the code.
++***
++**************************************/
++bit32u _mdioUserAccessRead(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr)
++ {
++
++ _mdioWaitForAccessComplete(PhyDev); /* Wait until UserAccess ready */
++ _mdioUserAccess(PhyDev, MDIO_USERACCESS_READ, regadr, phyadr, 0);
++ _mdioWaitForAccessComplete(PhyDev); /* Wait for Read to complete */
++
++ return(myMDIO_USERACCESS & MDIO_USERACCESS_DATA);
++ }
++
++
++/************************************
++***
++*** Waits for MDIO_USERACCESS to be ready and writes data
++***
++**************************************/
++void _mdioUserAccessWrite(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr, bit32u data)
++ {
++ _mdioWaitForAccessComplete(PhyDev); /* Wait until UserAccess ready */
++ _mdioUserAccess(PhyDev, MDIO_USERACCESS_WRITE, regadr, phyadr, data);
++ }
++
++void _mdioDumpPhyDetailed(PHY_DEVICE *PhyDev)
++{
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u PhyNum;
++ int RegData;
++
++ PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
++
++ RegData = _mdioUserAccessRead(PhyDev, 0, PhyNum);
++ mdioPrintf("PhyControl: %04X, Lookback=%s, Speed=%s, Duplex=%s\n",
++ RegData,
++ RegData&PHY_LOOP?"On":"Off",
++ RegData&PHY_100?"100":"10",
++ RegData&PHY_FD?"Full":"Half");
++ RegData = _mdioUserAccessRead(PhyDev, 1, PhyNum);
++ mdioPrintf("PhyStatus: %04X, AutoNeg=%s, Link=%s\n",
++ RegData,
++ RegData&NWAY_COMPLETE?"Complete":"NotComplete",
++ RegData&PHY_LINKED?"Up":"Down");
++ RegData = _mdioUserAccessRead(PhyDev, 4, PhyNum);
++ mdioPrintf("PhyMyCapability: %04X, 100FD=%s, 100HD=%s, 10FD=%s, 10HD=%s\n",
++ RegData,
++ RegData&NWAY_FD100?"Yes":"No",
++ RegData&NWAY_HD100?"Yes":"No",
++ RegData&NWAY_FD10?"Yes":"No",
++ RegData&NWAY_HD10?"Yes":"No");
++
++ RegData = _mdioUserAccessRead(PhyDev, 5, PhyNum);
++ mdioPrintf("PhyPartnerCapability: %04X, 100FD=%s, 100HD=%s, 10FD=%s, 10HD=%s\n",
++ RegData,
++ RegData&NWAY_FD100?"Yes":"No",
++ RegData&NWAY_HD100?"Yes":"No",
++ RegData&NWAY_FD10?"Yes":"No",
++ RegData&NWAY_HD10?"Yes":"No");
++}
++void _mdioDumpPhy(PHY_DEVICE *PhyDev, bit32u p)
++ {
++ bit32u j,n,PhyAcks;
++ bit32u PhyRegAddr;
++ bit32u phy_num;
++ bit32u PhyMask = PhyDev->PhyMask;
++
++ PhyAcks=myMDIO_ALIVE;
++ PhyAcks&=PhyMask; /* Only interested in 'our' Phys */
++
++ for(phy_num=0,j=1;phy_num<32;phy_num++,j<<=1)
++ {
++ if (PhyAcks&j)
++ {
++ mdioPrintf("%2d%s:",phy_num,(phy_num==p)?">":" ");
++ for(PhyRegAddr=0;PhyRegAddr<6;PhyRegAddr++)
++ {
++ n = _mdioUserAccessRead(PhyDev, PhyRegAddr, phy_num);
++ mdioPrintf(" %04x",n&0x0ffff);
++ }
++ mdioPrintf("\n");
++ }
++ }
++ _mdioDumpPhyDetailed(PhyDev);
++ }
++
++void _mdioDumpState(PHY_DEVICE *PhyDev)
++ {
++ bit32u state = PhyDev->PhyState;
++
++ if (!cpMacDebug) return;
++
++ mdioPrintf("Phy: %d, ",(state&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
++ mdioPrintf("State: %d/%s, ",(state&PHY_STATE_MASK)>>PHY_STATE_OFFSET,lstate[(state&PHY_STATE_MASK)>>PHY_STATE_OFFSET]);
++ mdioPrintf("Speed: %d, ",(state&PHY_SPEED_MASK)>>PHY_SPEED_OFFSET);
++ mdioPrintf("Dup: %d, ",(state&PHY_DUPLEX_MASK)>>PHY_DUPLEX_OFFSET);
++ mdioPrintf("Tim: %d, ",(state&PHY_TIM_MASK)>>PHY_TIM_OFFSET);
++ mdioPrintf("SMode: %d, ",(state&PHY_SMODE_MASK)>>PHY_SMODE_OFFSET);
++ mdioPrintf("Chng: %d",(state&PHY_CHNG_MASK)>>PHY_CHNG_OFFSET);
++ mdioPrintf("\n");
++
++ if (((state&PHY_STATE_MASK)!=FINDING)&&((state&PHY_STATE_MASK)!=INIT))
++ _mdioDumpPhy(PhyDev, (state&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
++ }
++
++
++void _mdioResetPhy(PHY_DEVICE *PhyDev,bit32u PhyNum)
++ {
++ bit16u PhyControlReg;
++
++ _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, PHY_RESET);
++ if (cpMacDebug)
++ mdioPrintf("cpMacMdioPhYReset(%d)\n",PhyNum);
++
++ /* Read control register until Phy Reset is complete */
++ do
++ {
++ PhyControlReg = _mdioUserAccessRead(PhyDev, PHY_CONTROL_REG, PhyNum);
++ }
++ while (PhyControlReg & PHY_RESET); /* Wait for Reset to clear */
++ }
++
++void _mdioDisablePhy(PHY_DEVICE *PhyDev,bit32u PhyNum)
++ {
++ _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, PHY_ISOLATE|PHY_PDOWN);
++
++ if (cpMacDebug)
++ mdioPrintf("cpMacMdioDisablePhy(%d)\n",PhyNum);
++
++ }
++
++void _MdioInitState(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u CurrentState;
++
++ CurrentState=*PhyState;
++ CurrentState=(CurrentState&~PHY_TIM_MASK)|(PHY_FIND_TO);
++ CurrentState=(CurrentState&~PHY_STATE_MASK)|(FINDING);
++ CurrentState=(CurrentState&~PHY_SPEED_MASK);
++ CurrentState=(CurrentState&~PHY_DUPLEX_MASK);
++ CurrentState|=PHY_CHANGE;
++
++ *PhyState=CurrentState;
++
++ }
++
++void _MdioFindingState(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u PhyMask = PhyDev->PhyMask;
++ bit32u PhyNum,i,j,PhyAcks;
++
++
++ PhyNum=PHY_NOT_FOUND;
++
++ if (*PhyState&PHY_TIM_MASK)
++ {
++ *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
++ }
++ else
++ {
++ PhyAcks=myMDIO_ALIVE;
++ PhyAcks&=PhyMask; /* Only interested in 'our' Phys */
++
++ for(i=0,j=1;(i<32)&&((j&PhyAcks)==0);i++,j<<=1);
++
++ if ((PhyAcks)&&(i<32)) PhyNum=i;
++ if (PhyNum!=PHY_NOT_FOUND)
++ {
++ /* Phy Found! */
++ *PhyState=(*PhyState&~PHY_DEV_MASK)|((PhyNum&PHY_DEV_MASK)<<PHY_DEV_OFFSET);
++ *PhyState=(*PhyState&~PHY_STATE_MASK)|(FOUND);
++ *PhyState|=PHY_CHANGE;
++ if (cpMacDebug)
++ mdioPrintf("cpMacMdioFindingState: PhyNum: %d\n",PhyNum);
++ }
++ else
++ {
++ if (cpMacDebug)
++ mdioPrintf("cpMacMdioFindingState: Timed Out looking for a Phy!\n");
++ *PhyState|=PHY_RECK_TO; /* This state currently has no support?*/
++ }
++ }
++ }
++
++void _MdioFoundState(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u PhyMask = PhyDev->PhyMask;
++ bit32u MLinkMask = PhyDev->MLinkMask;
++ bit32u PhyNum,PhyStatus,NWAYadvertise,m,phynum,i,j,PhyAcks;
++ bit32u PhySel;
++
++ if ((*PhyState&PHY_SMODE_MASK)==0) return;
++
++ PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
++
++ PhyAcks=myMDIO_ALIVE;
++ PhyAcks&=PhyMask; /* Only interested in 'our' Phys */
++
++ /* Will now isolate all our Phys, except the one we have decided to use */
++ for(phynum=0,j=1;phynum<32;phynum++,j<<=1)
++ {
++ if (PhyAcks&j)
++ {
++ if (phynum!=PhyNum) /* Do not disabled Found Phy */
++ _mdioDisablePhy(PhyDev,phynum);
++ }
++ }
++
++ /* Reset the Phy and proceed with auto-negotiation */
++ _mdioResetPhy(PhyDev,PhyNum);
++
++ /* Now setup the MDIOUserPhySel register */
++
++ PhySel=PhyNum; /* Set the phy address */
++
++ /* Set the way Link will be Monitored */
++ /* Check the Link Selection Method */
++ if ((1 << PhyNum) & MLinkMask)
++ PhySel |= MDIO_USERPHYSEL_LINKSEL;
++
++ myMDIO_USERPHYSEL = PhySel; /* update PHYSEL */
++
++ /* Get the Phy Status */
++ PhyStatus = _mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
++
++
++#ifdef _CPHAL_CPMAC
++ /* For Phy Internal loopback test, need to wait until Phy
++ found, then set Loopback */
++ if (PhyDev->HalDev->MdioConnect & _CPMDIO_LOOPBK)
++ {
++ /* Set Phy in Loopback */
++ _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, PHY_LOOP|PHY_FD);
++ /* Do a read to ensure PHY_LOOP has completed */
++ _mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
++ *PhyState=(*PhyState&~PHY_STATE_MASK)|(LOOPBACK);
++ *PhyState|=PHY_CHANGE;
++ return;
++ }
++#endif
++
++
++ if (cpMacDebug)
++ mdioPrintf("Enable Phy to negotiate external connection\n");
++
++ NWAYadvertise=NWAY_SEL;
++ if (*PhyState&SMODE_FD100) NWAYadvertise|=NWAY_FD100;
++ if (*PhyState&SMODE_HD100) NWAYadvertise|=NWAY_HD100;
++ if (*PhyState&SMODE_FD10) NWAYadvertise|=NWAY_FD10;
++ if (*PhyState&SMODE_HD10) NWAYadvertise|=NWAY_HD10;
++
++ *PhyState&=~(PHY_TIM_MASK|PHY_STATE_MASK);
++ if ((PhyStatus&NWAY_CAPABLE)&&(*PhyState&SMODE_AUTO)) /*NWAY Phy Detected*/
++ {
++ /*For NWAY compliant Phys */
++
++ _mdioUserAccessWrite(PhyDev, NWAY_ADVERTIZE_REG, PhyNum, NWAYadvertise);
++
++ if (cpMacDebug)
++ {
++ mdioPrintf("NWAY Advertising: ");
++ if (NWAYadvertise&NWAY_FD100) mdioPrintf("FullDuplex-100 ");
++ if (NWAYadvertise&NWAY_HD100) mdioPrintf("HalfDuplex-100 ");
++ if (NWAYadvertise&NWAY_FD10) mdioPrintf("FullDuplex-10 ");
++ if (NWAYadvertise&NWAY_HD10) mdioPrintf("HalfDuplex-10 ");
++ mdioPrintf("\n");
++ }
++
++ _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, AUTO_NEGOTIATE_EN);
++
++ _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, AUTO_NEGOTIATE_EN|RENEGOTIATE);
++
++ *PhyState|=PHY_CHANGE|PHY_NWST_TO|NWAY_START;
++ }
++ else
++ {
++ *PhyState&=~SMODE_AUTO; /*The Phy is not capable of auto negotiation! */
++ m=NWAYadvertise;
++ for(j=0x8000,i=0;(i<16)&&((j&m)==0);i++,j>>=1);
++ m=j;
++ j=0;
++ if (m&(NWAY_FD100|NWAY_HD100))
++ {
++ j=PHY_100;
++ m&=(NWAY_FD100|NWAY_HD100);
++ }
++ if (m&(NWAY_FD100|NWAY_FD10))
++ j |= PHY_FD;
++ if (cpMacDebug)
++ mdioPrintf("Requested PHY mode %s Duplex %s Mbps\n",(j&PHY_FD)?"Full":"Half",(j&PHY_100)?"100":"10");
++ _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, j);
++ *PhyState&=~PHY_SPEED_MASK;
++ if (j&PHY_100)
++ *PhyState|=(1<<PHY_SPEED_OFFSET);
++ *PhyState&=~PHY_DUPLEX_MASK;
++ if (j&PHY_FD)
++ *PhyState|=(1<<PHY_DUPLEX_OFFSET);
++ *PhyState|=PHY_CHANGE|PHY_LINK_TO|LINK_WAIT;
++ }
++ _mdioMdixDelay(PhyDev); /* If AutoMdix add delay */
++ }
++
++void _MdioNwayStartState(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u PhyNum,PhyMode;
++
++ PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
++
++ /*Wait for Negotiation to start */
++
++ PhyMode=_mdioUserAccessRead(PhyDev, PHY_CONTROL_REG, PhyNum);
++
++ if((PhyMode&RENEGOTIATE)==0)
++ {
++ _mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum); /*Flush pending latch bits*/
++ *PhyState&=~(PHY_STATE_MASK|PHY_TIM_MASK);
++ *PhyState|=PHY_CHANGE|NWAY_WAIT|PHY_NWDN_TO;
++ _mdioMdixDelay(PhyDev); /* If AutoMdix add delay */
++ }
++ else
++ {
++ if (*PhyState&PHY_TIM_MASK)
++ *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
++ else
++ _mdioPhyTimeOut(PhyDev);
++ }
++ }
++
++void _MdioNwayWaitState(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u PhyNum,PhyStatus,NWAYadvertise,NWAYREadvertise,NegMode,i,j;
++
++ PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
++
++ PhyStatus=_mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
++
++ if (PhyStatus&NWAY_COMPLETE)
++ {
++ *PhyState|=PHY_CHANGE;
++ *PhyState&=~PHY_SPEED_MASK;
++ *PhyState&=~PHY_DUPLEX_MASK;
++
++ NWAYadvertise =_mdioUserAccessRead(PhyDev, NWAY_ADVERTIZE_REG, PhyNum);
++ NWAYREadvertise =_mdioUserAccessRead(PhyDev, NWAY_REMADVERTISE_REG, PhyNum);
++
++ /* Negotiated mode is we and the remote have in common */
++ NegMode = NWAYadvertise & NWAYREadvertise;
++
++ if (cpMacDebug)
++ {
++ mdioPrintf("Phy: %d, ",(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
++ mdioPrintf("NegMode %04X, NWAYadvertise %04X, NWAYREadvertise %04X\n",
++ NegMode, NWAYadvertise, NWAYREadvertise);
++ }
++
++ /* Limit negotiation to fields below */
++ NegMode &= (NWAY_FD100|NWAY_HD100|NWAY_FD10|NWAY_HD10);
++
++ if (NegMode==0)
++ {
++ NegMode=(NWAY_HD100|NWAY_HD10)&NWAYadvertise; /*or 10 ?? who knows, Phy is not MII compliant*/
++ if(cpMacDebug)
++ {
++ mdioPrintf("Mdio:WARNING: Negotiation complete but NO agreement, default is HD\n");
++ _mdioDumpPhyDetailed(PhyDev);
++ }
++ }
++ for(j=0x8000,i=0;(i<16)&&((j&NegMode)==0);i++,j>>=1);
++
++
++ NegMode=j;
++ if (cpMacDebug)
++ {
++ mdioPrintf("Negotiated connection: ");
++ if (NegMode&NWAY_FD100) mdioPrintf("FullDuplex 100 Mbs\n");
++ if (NegMode&NWAY_HD100) mdioPrintf("HalfDuplex 100 Mbs\n");
++ if (NegMode&NWAY_FD10) mdioPrintf("FullDuplex 10 Mbs\n");
++ if (NegMode&NWAY_HD10) mdioPrintf("HalfDuplex 10 Mbs\n");
++ }
++ if (NegMode!=0)
++ {
++ if (PhyStatus&PHY_LINKED)
++ *PhyState=(*PhyState&~PHY_STATE_MASK)|LINKED;
++ else
++ *PhyState=(*PhyState&~PHY_STATE_MASK)|LINK_WAIT;
++ if (NegMode&(NWAY_FD100|NWAY_HD100))
++ *PhyState=(*PhyState&~PHY_SPEED_MASK)|(1<<PHY_SPEED_OFFSET);
++ if (NegMode&(NWAY_FD100|NWAY_FD10))
++ *PhyState=(*PhyState&~PHY_DUPLEX_MASK)|(1<<PHY_DUPLEX_OFFSET);
++ }
++ }
++ else
++ {
++ if (*PhyState&PHY_TIM_MASK)
++ *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
++ else
++ _mdioPhyTimeOut(PhyDev);
++ }
++ }
++
++void _MdioLinkWaitState(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u PhyStatus;
++ bit32u PhyNum;
++
++ PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
++
++ PhyStatus=_mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
++
++ if (PhyStatus&PHY_LINKED)
++ {
++ *PhyState=(*PhyState&~PHY_STATE_MASK)|LINKED;
++ *PhyState|=PHY_CHANGE;
++ }
++ else
++ {
++ if (*PhyState&PHY_TIM_MASK)
++ *PhyState=(*PhyState&~PHY_TIM_MASK)|((*PhyState&PHY_TIM_MASK)-(1<<PHY_TIM_OFFSET));
++ else
++ _mdioPhyTimeOut(PhyDev);
++ }
++ }
++
++void _mdioPhyTimeOut(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState;
++
++ if(_mdioMdixSupported(PhyDev) == 0)
++ return; /* AutoMdix not supported */
++
++ PhyState = &PhyDev->PhyState;
++
++ /* Indicate MDI/MDIX mode switch is needed */
++ *PhyState|=PHY_MDIX_SWITCH;
++
++ /* Toggle the MDIX mode indicatir */
++ if(*PhyState & PHY_MDIX)
++ *PhyState &= ~PHY_MDIX_MASK; /* Current State is MDIX, set to MDI */
++ else
++ *PhyState |= PHY_MDIX_MASK; /* Current State is MDI, set to MDIX */
++
++ /* Reset state machine to FOUND */
++ *PhyState=(*PhyState&~PHY_STATE_MASK)|(FOUND);
++ }
++
++void _MdioLoopbackState(PHY_DEVICE *PhyDev)
++ {
++ return;
++ }
++
++void _MdioLinkedState(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u PhyNum = (*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
++
++ if (myMDIO_LINK&(1<<PhyNum)) return; /* if still Linked, exit*/
++
++ /* Not Linked */
++ *PhyState&=~(PHY_STATE_MASK|PHY_TIM_MASK);
++ if (*PhyState&SMODE_AUTO)
++ *PhyState|=PHY_CHANGE|NWAY_WAIT|PHY_NWDN_TO;
++ else
++ *PhyState|=PHY_CHANGE|PHY_LINK_TO|LINK_WAIT;
++
++ _mdioMdixDelay(PhyDev); /* If AutoMdix add delay */
++ }
++
++void _MdioDefaultState(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ /*Awaiting a cpMacMdioInit call */
++ *PhyState|=PHY_CHANGE;
++ }
++
++
++/*User Calls********************************************************* */
++
++void cpMacMdioClose(PHY_DEVICE *PhyDev, int Full)
++ {
++ }
++
++
++int cpMacMdioInit(PHY_DEVICE *PhyDev, bit32u miibase, bit32u inst, bit32u PhyMask, bit32u MLinkMask, bit32u MdixMask, bit32u ResetReg, bit32u ResetBit, bit32u MdioBusFreq, bit32u MdioClockFreq, int verbose, void *Info)
++ {
++ bit32u HighestChannel;
++ bit32u ControlState;
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u clkdiv; /*MJH+030328*/
++
++ cpMacDebug=verbose;
++
++ PhyDev->miibase = miibase;
++ PhyDev->inst = inst;
++ PhyDev->PhyMask = PhyMask;
++ PhyDev->MLinkMask = MLinkMask;
++ PhyDev->MdixMask = MdixMask;
++#ifdef _CPHAL_CPMAC
++ PhyDev->HalDev = (HAL_DEVICE*) Info;
++#endif
++
++ *PhyState &= ~PHY_MDIX_MASK; /* Set initial State to MDI */
++
++ /* Check that the channel supplied is within range */
++ HighestChannel = (myMDIO_CONTROL & MDIO_CONTROL_HIGHEST_USER_CHANNEL) > 8;
++ if(inst > HighestChannel)
++ return(HighestChannel);
++
++ /*Setup MII MDIO access regs */
++
++ /* Calculate the correct value for the mclkdiv */
++ /* See PITS #14 */
++ if (MdioClockFreq) /*MJH+030402*/
++ clkdiv = (MdioBusFreq / MdioClockFreq) - 1; /*MJH+030402*/
++ else /*MJH+030402*/
++ clkdiv = 0xFF; /*MJH+030402*/
++
++ ControlState = MDIO_CONTROL_ENABLE;
++ ControlState |= (clkdiv & MDIO_CONTROL_CLKDIV); /*MJH+030328*/
++
++ /*
++ If mii is not out of reset or if the Control Register is not set correctly
++ then initalize
++ */
++ if( !(VOLATILE32(ResetReg) & (1 << ResetBit)) ||
++ ((myMDIO_CONTROL & (MDIO_CONTROL_CLKDIV | MDIO_CONTROL_ENABLE)) != ControlState) )/*GSG~030404*/
++ {
++ /* MII not setup, Setup initial condition */
++ VOLATILE32(ResetReg) &= ~(1 << ResetBit);
++ _mdioDelayEmulate(PhyDev, 64);
++ VOLATILE32(ResetReg) |= (1 << ResetBit); /* take mii out of reset */
++ _mdioDelayEmulate(PhyDev, 64);
++ myMDIO_CONTROL = ControlState; /* Enable MDIO */
++ }
++
++ *PhyState=INIT;
++
++ if (cpMacDebug)
++ mdioPrintf("cpMacMdioInit\n");
++ _mdioDumpState(PhyDev);
++ return(0);
++ }
++
++void cpMacMdioSetPhyMode(PHY_DEVICE *PhyDev,bit32u PhyMode)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u CurrentState;
++
++ PhyDev->PhyMode = PhyMode; /* used for AUTOMIDX, planned to replace PhyState fields */
++
++ *PhyState&=~PHY_SMODE_MASK;
++
++ if (PhyMode&NWAY_AUTO) *PhyState|=SMODE_AUTO;
++ if (PhyMode&NWAY_FD100) *PhyState|=SMODE_FD100;
++ if (PhyMode&NWAY_HD100) *PhyState|=SMODE_HD100;
++ if (PhyMode&NWAY_FD10) *PhyState|=SMODE_FD10;
++ if (PhyMode&NWAY_HD10) *PhyState|=SMODE_HD10;
++
++ CurrentState=*PhyState&PHY_STATE_MASK;
++ if ((CurrentState==NWAY_START)||
++ (CurrentState==NWAY_WAIT) ||
++ (CurrentState==LINK_WAIT) ||
++ (CurrentState==LINKED) )
++ *PhyState=(*PhyState&~PHY_STATE_MASK)|FOUND|PHY_CHANGE;
++ if (cpMacDebug)
++ mdioPrintf("cpMacMdioSetPhyMode:%08X Auto:%d, FD10:%d, HD10:%d, FD100:%d, HD100:%d\n", PhyMode,
++ PhyMode&NWAY_AUTO, PhyMode&NWAY_FD10, PhyMode&NWAY_HD10, PhyMode&NWAY_FD100,
++ PhyMode&NWAY_HD100);
++ _mdioDumpState(PhyDev);
++ }
++
++/* cpMacMdioTic is called every 10 mili seconds to process Phy states */
++
++int cpMacMdioTic(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u CurrentState;
++
++ /*Act on current state of the Phy */
++
++ CurrentState=*PhyState;
++ switch(CurrentState&PHY_STATE_MASK)
++ {
++ case INIT: _MdioInitState(PhyDev); break;
++ case FINDING: _MdioFindingState(PhyDev); break;
++ case FOUND: _MdioFoundState(PhyDev); break;
++ case NWAY_START: _MdioNwayStartState(PhyDev); break;
++ case NWAY_WAIT: _MdioNwayWaitState(PhyDev); break;
++ case LINK_WAIT: _MdioLinkWaitState(PhyDev); break;
++ case LINKED: _MdioLinkedState(PhyDev); break;
++ case LOOPBACK: _MdioLoopbackState(PhyDev); break;
++ default: _MdioDefaultState(PhyDev); break;
++ }
++
++ /*Dump state info if a change has been detected */
++
++ if ((CurrentState&~PHY_TIM_MASK)!=(*PhyState&~PHY_TIM_MASK))
++ _mdioDumpState(PhyDev);
++
++ /* Check is MDI/MDIX mode switch is needed */
++ if(*PhyState & PHY_MDIX_SWITCH)
++ {
++ bit32u Mdix;
++
++ *PhyState &= ~PHY_MDIX_SWITCH; /* Clear Mdix Flip indicator */
++
++ if(*PhyState & PHY_MDIX)
++ Mdix = 1;
++ else
++ Mdix = 0;
++ return(_MIIMDIO_MDIXFLIP|Mdix);
++ }
++
++ /*Return state change to user */
++
++ if (*PhyState&PHY_CHNG_MASK)
++ {
++ *PhyState&=~PHY_CHNG_MASK;
++ return(1);
++ }
++ else
++ return(0);
++ }
++
++/* cpMacMdioGetDuplex is called to retrieve the Duplex info */
++
++int cpMacMdioGetDuplex(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ return((*PhyState&PHY_DUPLEX_MASK)?1:0); /* return 0 or a 1 */
++ }
++
++/* cpMacMdioGetSpeed is called to retreive the Speed info */
++
++int cpMacMdioGetSpeed(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ return(*PhyState&PHY_SPEED_MASK);
++ }
++
++/* cpMacMdioGetPhyNum is called to retreive the Phy Device Adr info */
++
++int cpMacMdioGetPhyNum(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ return((*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET);
++ }
++
++/* cpMacMdioGetLoopback is called to Determine if the LOOPBACK state has been reached*/
++
++int cpMacMdioGetLoopback(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ return((*PhyState&PHY_STATE_MASK)==LOOPBACK);
++ }
++/* cpMacMdioGetLinked is called to Determine if the LINKED state has been reached*/
++
++int cpMacMdioGetLinked(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ return((*PhyState&PHY_STATE_MASK)==LINKED);
++ }
++
++void cpMacMdioLinkChange(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u PhyNum,PhyStatus;
++
++ PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
++
++ if (cpMacMdioGetLinked(PhyDev))
++ {
++ PhyStatus=_mdioUserAccessRead(PhyDev, PHY_STATUS_REG, PhyNum);
++
++ if ((PhyStatus&PHY_LINKED)==0)
++ {
++ *PhyState&=~(PHY_TIM_MASK|PHY_STATE_MASK);
++ if (*PhyState&SMODE_AUTO)
++ {
++ _mdioUserAccessWrite(PhyDev, PHY_CONTROL_REG, PhyNum, AUTO_NEGOTIATE_EN|RENEGOTIATE);
++ *PhyState|=PHY_CHANGE|PHY_NWST_TO|NWAY_START;
++ }
++ else
++ {
++ *PhyState|=PHY_CHANGE|PHY_LINK_TO|LINK_WAIT;
++ }
++ }
++ }
++ }
++
++void cpMacMdioGetVer(bit32u miibase, bit32u *ModID, bit32u *RevMaj, bit32u *RevMin)
++ {
++ bit32u Ver;
++
++ Ver = MDIO_VER(miibase);
++
++ *ModID = (Ver & MDIO_VER_MODID) >> 16;
++ *RevMaj = (Ver & MDIO_VER_REVMAJ) >> 8;
++ *RevMin = (Ver & MDIO_VER_REVMIN);
++ }
++
++int cpMacMdioGetPhyDevSize(void)
++ {
++ return(sizeof(PHY_DEVICE));
++ }
++
++ /* returns 0 if current Phy has AutoMdix support, otherwise 0 */
++int _mdioMdixSupported(PHY_DEVICE *PhyDev)
++ {
++ bit32u *PhyState = &PhyDev->PhyState;
++ bit32u PhyNum;
++
++ if((PhyDev->PhyMode & NWAY_AUTOMDIX) == 0)
++ return(0); /* AutoMdix not turned on */
++
++ PhyNum=(*PhyState&PHY_DEV_MASK)>>PHY_DEV_OFFSET;
++ if( ((1<<PhyNum) & PhyDev->MdixMask) == 0)
++ return(0); /* Phy does not support AutoMdix*/
++
++ return(1);
++ }
++
++/* If current Phy has AutoMdix support add Mdix Delay to the Timer State Value */
++void _mdioMdixDelay(PHY_DEVICE *PhyDev)
++ {
++ int Delay;
++ bit32u *PhyState = &PhyDev->PhyState;
++#ifdef _CPHAL_CPMAC
++ HAL_DEVICE *HalDev = PhyDev->HalDev;
++#endif
++
++ if(_mdioMdixSupported(PhyDev) == 0)
++ return; /* AutoMdix not supported */
++/* Currently only supported when used with the CPMAC */
++#ifdef _CPHAL_CPMAC
++ /* Get the Delay value in milli-seconds and convert to ten-milli second value */
++ Delay = cpmacRandomRange(HalDev, _AUTOMDIX_DELAY_MIN, _AUTOMDIX_DELAY_MAX);
++ Delay /= 10;
++
++ /* Add AutoMidx Random Switch Delay to AutoMdix Link Delay */
++
++ Delay += (PHY_MDIX_TO>>PHY_TIM_OFFSET);
++
++ /* Change Timeout value to AutoMdix standard */
++ *PhyState &= ~(PHY_TIM_MASK); /* Clear current Time out value */
++ *PhyState |= (Delay<<PHY_TIM_OFFSET); /* Set new value */
++#endif
++ }
++
++
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpmdio.h linux.dev/drivers/net/avalanche_cpmac/cpmdio.h
+--- linux.old/drivers/net/avalanche_cpmac/cpmdio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpmdio.h 2005-07-12 02:48:42.047593000 +0200
+@@ -0,0 +1,73 @@
++/*****************************************************************************
++** TNETD53xx Software Support
++** Copyright(c) 2002, Texas Instruments Incorporated. All Rights Reserved.
++**
++** FILE: cpmdio.h User Include for MDIO API Access
++**
++** DESCRIPTION:
++** This include file contains definitions for the the MDIO API
++**
++** HISTORY:
++** 27Mar02 Michael Hanrahan Original (modified from emacmdio.h)
++** 04Apr02 Michael Hanrahan Added Interrupt Support
++*****************************************************************************/
++#ifndef _INC_CPMDIO
++#define _INC_CPMDIO
++
++
++#ifndef __CPHAL_CPMDIO
++typedef void PHY_DEVICE;
++#endif
++
++
++/*Version Information */
++
++void cpMacMdioGetVer(bit32u miiBase, bit32u *ModID, bit32u *RevMaj, bit32u *RevMin);
++
++/*Called once at the begining of time */
++
++int cpMacMdioInit(PHY_DEVICE *PhyDev, bit32u miibase, bit32u inst, bit32u PhyMask, bit32u MLinkMask, bit32u MdixMask, bit32u ResetBase, bit32u ResetBit, bit32u MdioBusFreq, bit32u MdioClockFreq, int verbose, void *Info);
++int cpMacMdioGetPhyDevSize(void);
++
++
++/*Called every 10 mili Seconds, returns TRUE if there has been a mode change */
++
++int cpMacMdioTic(PHY_DEVICE *PhyDev);
++
++/*Called to set Phy mode */
++
++void cpMacMdioSetPhyMode(PHY_DEVICE *PhyDev,bit32u PhyMode);
++
++/*Calls to retreive info after a mode change! */
++
++int cpMacMdioGetDuplex(PHY_DEVICE *PhyDev);
++int cpMacMdioGetSpeed(PHY_DEVICE *PhyDev);
++int cpMacMdioGetPhyNum(PHY_DEVICE *PhyDev);
++int cpMacMdioGetLinked(PHY_DEVICE *PhyDev);
++void cpMacMdioLinkChange(PHY_DEVICE *PhyDev);
++
++/* Shot Down */
++
++void cpMacMdioClose(PHY_DEVICE *PhyDev, int Full);
++
++
++/* Phy Mode Values */
++#define NWAY_AUTOMDIX (1<<16)
++#define NWAY_FD100 (1<<8)
++#define NWAY_HD100 (1<<7)
++#define NWAY_FD10 (1<<6)
++#define NWAY_HD10 (1<<5)
++#define NWAY_AUTO (1<<0)
++
++/*
++ *
++ * Tic() return values
++ *
++ */
++
++#define _MIIMDIO_MDIXFLIP (1<<28)
++
++#define _AUTOMDIX_DELAY_MIN 80 /* milli-seconds*/
++#define _AUTOMDIX_DELAY_MAX 200 /* milli-seconds*/
++
++#endif /* _INC_CPMDIO */
+diff -urN linux.old/drivers/net/avalanche_cpmac/cppi_cpmac.c linux.dev/drivers/net/avalanche_cpmac/cppi_cpmac.c
+--- linux.old/drivers/net/avalanche_cpmac/cppi_cpmac.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cppi_cpmac.c 2005-07-12 02:48:42.048593000 +0200
+@@ -0,0 +1,1345 @@
++/*************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002,2003 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE: cppi.c
++ *
++ * DESCRIPTION:
++ * This file contains shared code for all CPPI modules.
++ *
++ * HISTORY:
++ * 7Aug02 Greg RC1.00 Original Version created.
++ * 27Sep02 Mick RC1.01 Merged for use by CPMAC/CPSAR
++ * 16Oct02 Mick RC1.02 Performance Tweaks (see cppihist.txt)
++ * 12Nov02 Mick RC1.02 Updated to use cpmac_reg.h
++ * 09Jan03 Mick RC3.01 Removed modification to RxBuffer ptr
++ * 28Mar03 Mick 1.03 RxReturn now returns error if Malloc Fails
++ * 10Apr03 Mick 1.03.02 Added Needs Buffer Support
++ * 11Jun03 Mick 1.06.02 halSend() errors corrected
++ * 23Aug04 Mick 1.07.08 cpmac only - Send: bypass threshold check if TxInts re-enabled
++ *
++ * @author Greg Guyotte
++ * @version 1.00
++ * @date 7-Aug-2002
++ *****************************************************************************/
++/* each CPPI module must modify this file, the rest of the
++ code in cppi.c should be totally shared *//* Each CPPI module MUST properly define all constants shown below */
++
++/* CPPI registers */
++
++/* the following defines are not CPPI specific */
++
++static int TxInt(HAL_DEVICE *HalDev, int Ch, int Queue, int *MoreWork);
++
++static void FreeRx(HAL_DEVICE *HalDev, int Ch)
++ {
++ HAL_RCB *rcb_ptr; /*+GSG 030303*/
++ int rcbSize = (sizeof(HAL_RCB)+0xf)&~0xf; /*+GSG 030303*/
++ int Num = HalDev->ChData[Ch].RxNumBuffers, i; /*+GSG 030303*/
++
++ /* Free Rx data buffers attached to descriptors, if necessary */
++ if (HalDev->RcbStart[Ch] != 0) /*+GSG 030303*/
++ { /*+GSG 030303*/
++ for(i=0;i<Num;i++) /*+GSG 030303*/
++ { /*+GSG 030303*/
++ rcb_ptr = (HAL_RCB *)(HalDev->RcbStart[Ch] + (i*rcbSize)); /*+GSG 030303*/
++
++ /* free the data buffer */
++ if (rcb_ptr->DatPtr != 0)
++ {
++
++ HalDev->OsFunc->FreeRxBuffer((void *)rcb_ptr->OsInfo, (void *)rcb_ptr->DatPtr);
++ rcb_ptr->OsInfo=0; /*MJH+030522*/
++ rcb_ptr->DatPtr=0; /*MJH+030522*/
++ }
++ } /*+GSG 030303*/
++ } /*+GSG 030303*/
++
++ /* free up all desciptors at once */
++ HalDev->OsFunc->FreeDmaXfer(HalDev->RcbStart[Ch]);
++
++ /* mark buffers as freed */
++ HalDev->RcbStart[Ch] = 0;
++ }
++
++static void FreeTx(HAL_DEVICE *HalDev, int Ch, int Queue)
++ {
++
++/*+GSG 030303*/
++
++ /* free all descriptors at once */
++ HalDev->OsFunc->FreeDmaXfer(HalDev->TcbStart[Ch][Queue]);
++
++ HalDev->TcbStart[Ch][Queue] = 0;
++ }
++
++/* return of 0 means that this code executed, -1 means the interrupt was not
++ a teardown interrupt */
++static int RxTeardownInt(HAL_DEVICE *HalDev, int Ch)
++ {
++ bit32u base = HalDev->dev_base;
++
++ /* check to see if the interrupt is a teardown interrupt */
++ if (((CPMAC_RX_INT_ACK( base , Ch )) & TEARDOWN_VAL) == TEARDOWN_VAL)
++ {
++ /* finish channel teardown */
++
++ /* Free channel resources on a FULL teardown */
++ if (HalDev->RxTeardownPending[Ch] & FULL_TEARDOWN)
++ {
++ FreeRx(HalDev, Ch);
++ }
++
++ /* bug fix - clear Rx channel pointers on teardown */
++ HalDev->RcbPool[Ch] = 0;
++ HalDev->RxActQueueHead[Ch] = 0;
++ HalDev->RxActQueueCount[Ch] = 0;
++ HalDev->RxActive[Ch] = FALSE;
++
++ /* write completion pointer */
++ (CPMAC_RX_INT_ACK( base , Ch )) = TEARDOWN_VAL;
++
++ /* use direction bit as a teardown pending bit! May be able to
++ use only one teardown pending integer in HalDev */
++
++ HalDev->RxTeardownPending[Ch] &= ~RX_TEARDOWN;
++
++ HalDev->ChIsOpen[Ch][DIRECTION_RX] = 0;
++
++ HalDev->ChIsOpen[Ch][DIRECTION_RX] = 0;
++ CPMAC_RX_INTMASK_CLEAR(HalDev->dev_base) = (1<<Ch);
++ if ((HalDev->RxTeardownPending[Ch] & BLOCKING_TEARDOWN) == 0)
++ {
++
++ HalDev->OsFunc->TeardownComplete(HalDev->OsDev, Ch, DIRECTION_RX);
++ }
++ HalDev->RxTeardownPending[Ch] = 0;
++
++ return (EC_NO_ERRORS);
++ }
++ return (-1);
++ }
++
++/* return of 0 means that this code executed, -1 means the interrupt was not
++ a teardown interrupt. Note: this code is always called with Queue == 0 (hi priority). */
++static int TxTeardownInt(HAL_DEVICE *HalDev, int Ch, int Queue)
++ {
++ bit32u base = HalDev->dev_base;
++ HAL_TCB *Last, *Curr, *First; /*+GSG 030303*/
++ int i;
++
++ if (((CPMAC_TX_INT_ACK( base , Ch )) & TEARDOWN_VAL) == TEARDOWN_VAL)
++ {
++ /* perform all actions for both queues (+GSG 040212) */
++ for (i=0; i<HalDev->ChData[Ch].TxNumQueues; i++)
++ {
++ /* return outstanding buffers to OS +RC3.02*/
++ Curr = HalDev->TxActQueueHead[Ch][i]; /*+GSG 030303*/
++ First = Curr; /*+GSG 030303*/
++ while (Curr) /*+GSG 030303*/
++ { /*+GSG 030303*/
++ /* Pop TCB(s) for packet from the stack */ /*+GSG 030303*/
++ Last = Curr->Eop; /*+GSG 030303*/
++ HalDev->TxActQueueHead[Ch][i] = Last->Next; /*+GSG 030303*/
++ /*+GSG 030303*/
++ /* return to OS */ /*+GSG 030303*/
++ HalDev->OsFunc->SendComplete(Curr->OsInfo); /*+GSG 030303*/
++ /*+GSG 030303*/
++ /* Push Tcb(s) back onto the stack */ /*+GSG 030303*/
++ Curr = Last->Next; /*+GSG 030303*/
++ Last->Next = HalDev->TcbPool[Ch][i]; /*+GSG 030303*/
++ HalDev->TcbPool[Ch][i] = First; /*+GSG 030303*/
++ /*+GSG 030303*/
++ /* set the first(SOP) pointer for the next packet */ /*+GSG 030303*/
++ First = Curr; /*+GSG 030303*/
++ } /*+GSG 030303*/
++ }
++
++ /* finish channel teardown */
++
++ if (HalDev->TxTeardownPending[Ch] & FULL_TEARDOWN)
++ {
++ FreeTx(HalDev, Ch, 0);
++
++ if (HalDev->ChData[Ch].TxNumQueues == 2)
++ FreeTx(HalDev, Ch, 1);
++ } /* if FULL teardown */
++
++ /* perform all actions for both queues (+GSG 040212) */
++ for (i=0; i<HalDev->ChData[Ch].TxNumQueues; i++)
++ {
++ /* bug fix - clear Tx channel pointers on teardown */
++ HalDev->TcbPool[Ch][i] = 0;
++ HalDev->TxActQueueHead[Ch][i] = 0;
++ HalDev->TxActQueueCount[Ch][i] = 0;
++ HalDev->TxActive[Ch][i] = FALSE;
++ }
++
++ /* write completion pointer, only needed for the high priority queue */
++ (CPMAC_TX_INT_ACK( base , Ch )) = TEARDOWN_VAL;
++
++ /* no longer pending teardown */
++ HalDev->TxTeardownPending[Ch] &= ~TX_TEARDOWN;
++
++ HalDev->ChIsOpen[Ch][DIRECTION_TX] = 0;
++
++ HalDev->ChIsOpen[Ch][DIRECTION_TX] = 0;
++ CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = (1<<Ch);
++ if ((HalDev->TxTeardownPending[Ch] & BLOCKING_TEARDOWN) == 0)
++ {
++
++ HalDev->OsFunc->TeardownComplete(HalDev->OsDev, Ch, DIRECTION_TX);
++ }
++ HalDev->TxTeardownPending[Ch] = 0;
++
++ return (EC_NO_ERRORS);
++ }
++ return (-1);
++ }
++
++/* +GSG 030421 */
++static void AddToRxQueue(HAL_DEVICE *HalDev, HAL_RCB *FirstRcb, HAL_RCB *LastRcb, int FragCount, int Ch)
++ {
++ if (HalDev->RxActQueueHead[Ch]==0)
++ {
++
++ HalDev->RxActQueueHead[Ch]=FirstRcb;
++ HalDev->RxActQueueTail[Ch]=LastRcb;
++ if (!HalDev->RxActive[Ch])
++ {
++ /* write Rx Queue Head Descriptor Pointer */
++ ((CPMAC_RX_HDP( HalDev->dev_base , Ch )) ) = VirtToPhys(FirstRcb) - HalDev->offset;
++ HalDev->RxActive[Ch]=TRUE;
++ }
++ }
++ else
++ {
++ register HAL_RCB *OldTailRcb;
++ register bit32u rmode;
++
++ HalDev->OsFunc->CriticalOn();
++ OldTailRcb=HalDev->RxActQueueTail[Ch];
++ OldTailRcb->Next=(void *)FirstRcb;
++ OldTailRcb=VirtToVirtNoCache(OldTailRcb);
++ OldTailRcb->HNext=VirtToPhys(FirstRcb) - HalDev->offset;
++ HalDev->RxActQueueTail[Ch]=LastRcb;
++ rmode=OldTailRcb->mode;
++ if (rmode&CB_EOQ_BIT)
++ {
++ rmode&=~CB_EOQ_BIT;
++ ((CPMAC_RX_HDP( HalDev->dev_base , Ch )) ) = VirtToPhys(FirstRcb) - HalDev->offset;
++ OldTailRcb->mode=rmode;
++ }
++ HalDev->OsFunc->CriticalOff();
++ }
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function is called to indicate to the CPHAL that the upper layer
++ * software has finished processing the receive data (given to it by
++ * osReceive()). The CPHAL will then return the appropriate receive buffers
++ * and buffer descriptors to the available pool.
++ *
++ * @param HalReceiveInfo Start of receive buffer descriptor chain returned to
++ * CPHAL.
++ * @param StripFlag Flag indicating whether the upper layer software has
++ * retained ownership of the receive data buffers.
++ *<BR>
++ * 'FALSE' means that the CPHAL can reuse the receive data buffers.
++ *<BR>
++ * 'TRUE' : indicates the data buffers were retained by the OS
++ *<BR>
++ * NOTE: If StripFlag is TRUE, it is the responsibility of the upper layer software to free the buffers when they are no longer needed.
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_RCB_NEEDS_BUFFER "EC_VAL_RCB_NEEDS_BUFFER"<BR>
++ * @ref EC_VAL_RCB_DROPPED "EC_VAL_RCB_DROPPED"<BR>
++ */
++static int halRxReturn(HAL_RECEIVEINFO *HalReceiveInfo,
++ int StripFlag)
++ {
++ int Ch, i;
++ HAL_RCB *LastRcb;
++ HAL_DEVICE *HalDev;
++ int RcbSize;
++ int FragCount;
++
++ Ch = HalReceiveInfo->mode&0x0ff;
++ HalDev = (HAL_DEVICE *)HalReceiveInfo->Off_BLen;
++ FragCount = HalReceiveInfo->mode>>8;
++
++ if (HalDev->State != enOpened)
++ return(EC_CPMAC |EC_FUNC_RXRETURN|EC_VAL_INVALID_STATE);
++
++ LastRcb=(HAL_RCB *)HalReceiveInfo->Eop;
++ LastRcb->HNext=0;
++ LastRcb->Next=0;
++ RcbSize = HalDev->ChData[Ch].RxBufSize;
++
++ if (FragCount>1)
++ {
++ LastRcb->Off_BLen=RcbSize;
++ LastRcb->mode=CB_OWNERSHIP_BIT;
++ }
++
++ HalReceiveInfo->Off_BLen=RcbSize;
++ HalReceiveInfo->mode=CB_OWNERSHIP_BIT;
++
++ /* If OS has kept the buffers for this packet, attempt to alloc new buffers */
++ if (StripFlag)
++ {
++ int rc=0; /*MJH+030417*/
++ int GoodCount=0; /*GSG+030421*/
++ HAL_RCB *TempRcb;
++ char *pBuf;
++ HAL_RCB *CurrHeadRcb = HalReceiveInfo, *LastGoodRcb=0; /* +GSG 030421 */
++
++ TempRcb = HalReceiveInfo;
++ for (i=0; i<FragCount; i++)
++ {
++ if (TempRcb == 0)
++ {
++ dbgPrintf("Rx Return error while allocating new buffers\n");
++ dbgPrintf("Rcb = %08x, Rcb->Eop = %08x, FragCount = %d:%d\n",
++ (bit32u)HalReceiveInfo, (bit32u)HalReceiveInfo->Eop, FragCount,i);
++ osfuncSioFlush();
++
++ return(EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_CORRUPT_RCB_CHAIN);
++ }
++
++ pBuf= (char *) HalDev->OsFunc->MallocRxBuffer(RcbSize,0,
++ 0xF,HalDev->ChData[Ch].OsSetup,
++ (void *)TempRcb,
++ (void *)&TempRcb->OsInfo,
++ (void *) HalDev->OsDev);
++ if (!pBuf)
++ {
++ /* malloc failed, add this RCB to Needs Buffer List */
++ (HAL_RCB *)TempRcb->Eop = TempRcb; /* GSG +030430 */
++ TempRcb->mode=1<<8|Ch;
++ TempRcb->Off_BLen=(bit32u)HalDev;
++
++ if(HalDev->NeedsCount < MAX_NEEDS) /* +MJH 030410 */
++ { /* +MJH 030410 */
++ HalDev->Needs[HalDev->NeedsCount] = (HAL_RECEIVEINFO *) TempRcb; /* +MJH 030410 */
++ HalDev->NeedsCount++; /* +MJH 030410 */
++ rc = (EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_RCB_NEEDS_BUFFER); /* ~MJH 030417 */
++ } /* +MJH 030410 */
++ else /* +MJH 030410 */
++ rc = (EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_RCB_DROPPED); /* ~MJH 030417 */
++
++ /* requeue any previous RCB's that were ready to go before this one */
++ if (GoodCount > 0) /* +GSG 030421 */
++ { /* +GSG 030421 */
++ LastGoodRcb->HNext=0; /* +GSG 030430 */
++ LastGoodRcb->Next=0; /* +GSG 030430 */
++ osfuncDataCacheHitWritebackAndInvalidate((void *)LastGoodRcb, 16); /* +GSG 030430 */
++
++ AddToRxQueue(HalDev, CurrHeadRcb, LastGoodRcb, GoodCount, Ch); /* +GSG 030421 */
++ GoodCount = 0; /* +GSG 030421 */
++ } /* +GSG 030421 */
++
++ CurrHeadRcb = TempRcb->Next; /* +GSG 030421 */
++ }
++ else /* +GSG 030421 */
++ { /* +GSG 030421 */
++ /* malloc succeeded, requeue the RCB to the hardware */
++ TempRcb->BufPtr=VirtToPhys(pBuf) - HalDev->offset;
++ TempRcb->DatPtr=pBuf;
++ /* Emerald fix 10/29 */
++ osfuncDataCacheHitWritebackAndInvalidate((void *)TempRcb, 16);
++
++ /* i store the last good RCB in case the malloc fails for the
++ next fragment. This ensures that I can go ahead and return
++ a partial chain of RCB's to the hardware */
++ LastGoodRcb = TempRcb; /* +GSG 030421 */
++ GoodCount++; /* +GSG 030421 */
++ } /* +GSG 030421 */
++ TempRcb = TempRcb->Next;
++ } /* end of Frag loop */
++ /* if there any good RCB's to requeue, do so here */
++ if (GoodCount > 0) /* +GSG 030421 */
++ {
++ AddToRxQueue(HalDev, CurrHeadRcb, LastGoodRcb, GoodCount, Ch); /* +GSG 030421 */
++ }
++ return(rc); /* ~GSG 030421 */
++ }
++ else
++ {
++ /* Not Stripping */
++ /* Emerald */
++ /* Write Back SOP and last RCB */
++ osfuncDataCacheHitWritebackAndInvalidate((void *)HalReceiveInfo, 16);
++
++ if (FragCount > 1)
++ {
++ osfuncDataCacheHitWritebackAndInvalidate((void *)LastRcb, 16);
++ }
++ /* if not stripping buffers, always add to queue */
++ AddToRxQueue(HalDev, HalReceiveInfo, LastRcb, FragCount, Ch); /*MJH~030520*/
++ }
++
++ return(EC_NO_ERRORS);
++ }
++
++/* +MJH 030410
++ Trys to liberate an RCB until liberation fails.
++ Note: If liberation fails then RxReturn will re-add the RCB to the
++ Needs list.
++*/
++static void NeedsCheck(HAL_DEVICE *HalDev)
++{
++ HAL_RECEIVEINFO* HalRcb;
++ int rc;
++ HalDev->OsFunc->CriticalOn();
++ while(HalDev->NeedsCount)
++ {
++ HalDev->NeedsCount--;
++ HalRcb = HalDev->Needs[HalDev->NeedsCount];
++ rc = halRxReturn(HalRcb, 1);
++ /* short circuit if RxReturn starts to fail */
++ if (rc != 0)
++ break;
++ }
++ HalDev->OsFunc->CriticalOff();
++}
++
++/*
++ * This function allocates transmit buffer descriptors (internal CPHAL function).
++ * It creates a high priority transmit queue by default for a single Tx
++ * channel. If QoS is enabled for the given CPHAL device, this function
++ * will also allocate a low priority transmit queue.
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param Ch Channel number.
++ *
++ * @return 0 OK, Non-Zero Not OK
++ */
++static int InitTcb(HAL_DEVICE *HalDev, int Ch)
++ {
++ int i, Num = HalDev->ChData[Ch].TxNumBuffers;
++ HAL_TCB *pTcb=0;
++ char *AllTcb;
++ int tcbSize, Queue;
++ int SizeMalloc;
++
++ tcbSize = (sizeof(HAL_TCB)+0xf)&~0xf;
++ SizeMalloc = (tcbSize*Num)+0xf;
++
++ for (Queue=0; Queue < HalDev->ChData[Ch].TxNumQueues; Queue++)
++ {
++ if (HalDev->TcbStart[Ch][Queue] == 0)
++ {
++
++ /* malloc all TCBs at once */
++ AllTcb = (char *)HalDev->OsFunc->MallocDmaXfer(SizeMalloc,0,0xffffffff);
++ if (!AllTcb)
++ {
++ return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_TCB_MALLOC_FAILED);
++ }
++
++ HalDev->OsFunc->Memset(AllTcb, 0, SizeMalloc);
++
++ /* keep this address for freeing later */
++ HalDev->TcbStart[Ch][Queue] = AllTcb;
++ }
++ else
++ {
++ /* if the memory has already been allocated, simply reuse it! */
++ AllTcb = HalDev->TcbStart[Ch][Queue];
++ }
++
++ /* align to cache line */
++ AllTcb = (char *)(((bit32u)AllTcb + 0xf) &~ 0xf); /*PITS #143 MJH~030522*/
++
++ /* default High priority transmit queue */
++ HalDev->TcbPool[Ch][Queue]=0;
++ for(i=0;i<Num;i++)
++ {
++ /*pTcb=(HAL_TCB *) OsFunc->MallocDmaXfer(sizeof(HAL_TCB),0,0xffffffff); */
++ pTcb= (HAL_TCB *)(AllTcb + (i*tcbSize));
++ pTcb->mode=0;
++ pTcb->BufPtr=0;
++ pTcb->Next=HalDev->TcbPool[Ch][Queue];
++ pTcb->Off_BLen=0;
++ HalDev->TcbPool[Ch][Queue]=pTcb;
++ }
++ /*HalDev->TcbEnd = pTcb;*/
++ }
++
++ return(EC_NO_ERRORS);
++ }
++
++/*
++ * This function allocates receive buffer descriptors (internal CPHAL function).
++ * After allocation, the function 'queues' (gives to the hardware) the newly
++ * created receive buffers to enable packet reception.
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param Ch Channel number.
++ *
++ * @return 0 OK, Non-Zero Not OK
++ */
++static int InitRcb(HAL_DEVICE *HalDev, int Ch)
++ {
++ int i, Num = HalDev->ChData[Ch].RxNumBuffers;
++ int Size = HalDev->ChData[Ch].RxBufSize;
++ HAL_RCB *pRcb;
++ char *pBuf;
++ char *AllRcb;
++ int rcbSize;
++ int DoMalloc = 0;
++ int SizeMalloc;
++ int MallocSize;
++
++ rcbSize = (sizeof(HAL_RCB)+0xf)&~0xf;
++ SizeMalloc = (rcbSize*Num)+0xf;
++
++ if (HalDev->RcbStart[Ch] == 0)
++ {
++ DoMalloc = 1;
++
++ /* malloc all RCBs at once */
++ AllRcb= (char *)HalDev->OsFunc->MallocDmaXfer(SizeMalloc,0,0xffffffff);
++ if (!AllRcb)
++ {
++ return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_RCB_MALLOC_FAILED);
++ }
++
++ HalDev->OsFunc->Memset(AllRcb, 0, SizeMalloc);
++
++ /* keep this address for freeing later */
++ HalDev->RcbStart[Ch] = AllRcb;
++ }
++ else
++ {
++ /* if the memory has already been allocated, simply reuse it! */
++ AllRcb = HalDev->RcbStart[Ch];
++ }
++
++ /* align to cache line */
++ AllRcb = (char *)(((bit32u)AllRcb + 0xf)&~0xf); /*PITS #143 MJH~030522*/
++
++ HalDev->RcbPool[Ch]=0;
++ for(i=0;i<Num;i++)
++ {
++ pRcb = (HAL_RCB *)(AllRcb + (i*rcbSize));
++
++ if (DoMalloc == 1)
++ {
++
++ MallocSize = Size; /*~3.01 */
++ pBuf= (char *) HalDev->OsFunc->MallocRxBuffer(MallocSize,0,0xF,HalDev->ChData[Ch].OsSetup, (void *)pRcb, (void *)&pRcb->OsInfo, (void *) HalDev->OsDev);
++ if(!pBuf)
++ {
++ return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_RX_BUFFER_MALLOC_FAILED);
++ }
++ /* -RC3.01 pBuf = (char *)(((bit32u)pBuf+0xF) & ~0xF); */
++ pRcb->BufPtr=VirtToPhys(pBuf) - HalDev->offset;
++ pRcb->DatPtr=pBuf;
++ }
++ pRcb->mode=(1<<8)|Ch; /* One Frag for Ch */
++ pRcb->Next=(void *)HalDev->RcbPool[Ch];
++ pRcb->Off_BLen=(bit32u)HalDev;
++ HalDev->RcbPool[Ch]=pRcb;
++ }
++
++ /* Give all of the Rx buffers to hardware */
++
++ while(HalDev->RcbPool[Ch])
++ {
++ pRcb=HalDev->RcbPool[Ch];
++ HalDev->RcbPool[Ch]=pRcb->Next;
++ pRcb->Eop=(void*)pRcb;
++ pRcb->mode=(1<<8)|Ch;
++ halRxReturn((HAL_RECEIVEINFO *)pRcb, 0);
++ }
++
++ return(EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function transmits the data in FragList using available transmit
++ * buffer descriptors. More information on the use of the Mode parameter
++ * is available in the module-specific appendices. Note: The OS should
++ * not call Send() for a channel that has been requested to be torndown.
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param FragList Fragment List structure.
++ * @param FragCount Number of fragments in FragList.
++ * @param PacketSize Number of bytes to transmit.
++ * @param OsSendInfo OS Send Information structure. <BR>
++ * @param Mode 32-bit value with the following bit fields: <BR>
++ * 31-16: Mode (used for module specific data). <BR>
++ * 15-08: Queue (transmit queue to send on). <BR>
++ * 07-00: Channel (channel number to send on).
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_NOT_LINKED "EC_VAL_NOT_LINKED"<BR>
++ * @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
++ * @ref EC_VAL_OUT_OF_TCBS "EC_VAL_OUT_OF_TCBS"<BR>
++ * @ref EC_VAL_NO_TCBS "EC_VAL_NO_TCBS"<BR>
++ */
++static int halSend(HAL_DEVICE *HalDev,FRAGLIST *FragList,
++ int FragCount,int PacketSize, OS_SENDINFO *OsSendInfo,
++ bit32u Mode)
++ {
++ HAL_TCB *tcb_ptr, *head;
++ int i;
++ int rc = EC_NO_ERRORS;
++ int Ch = Mode & 0xFF;
++ int Queue = (Mode>>8)&0xFF;
++ /*int DoThresholdCheck=1; */ /* Used when TxIntDisable is set and TxInts are re-enabled */
++
++ if (HalDev->State != enOpened)
++ return(EC_CPPI|EC_FUNC_SEND|EC_VAL_INVALID_STATE);
++
++ if (!HalDev->Linked)
++ {
++ rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_NOT_LINKED;
++ return(rc);
++ }
++
++ if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == 0) /*MJH~030611*/ /*PITS 148*/
++ return(EC_CPMAC |EC_FUNC_SEND|EC_VAL_INVALID_CH); /*+GSG 030303*/
++
++ HalDev->OsFunc->CriticalOn();
++
++ /* Setup Tx mode and size */
++ if (PacketSize<60)
++ {
++ FragList[FragCount-1].len += (60 - PacketSize); /*MJH~030506*//*PITS 132*/
++ PacketSize = 60; /*MJH~030506*/
++ }
++ Mode &= CB_PASSCRC_BIT;
++
++ tcb_ptr = head = HalDev->TcbPool[Ch][Queue];
++
++ if (tcb_ptr)
++ {
++
++ Mode|=PacketSize|CB_SOF_BIT|CB_OWNERSHIP_BIT;
++
++ for (i=0; i<FragCount; i++)
++
++ {
++ /* Setup Tx mode and size */
++ tcb_ptr->Off_BLen = FragList[i].len;
++
++ tcb_ptr->mode = Mode;
++ tcb_ptr->BufPtr = VirtToPhys((bit32 *)FragList[i].data) - HalDev->offset;
++ tcb_ptr->OsInfo = OsSendInfo;
++
++ if (i == (FragCount - 1))
++ {
++ /* last fragment */
++ tcb_ptr->mode |= CB_EOF_BIT;
++
++ /* since this is the last fragment, set the TcbPool pointer before
++ nulling out the Next pointers */
++
++ HalDev->TcbPool[Ch][Queue] = tcb_ptr->Next;
++
++ tcb_ptr->Next = 0;
++ tcb_ptr->HNext = 0;
++
++ /* In the Tx Interrupt handler, we will need to know which TCB is EOP,
++ so we can save that information in the SOP */
++ head->Eop = tcb_ptr;
++
++ /* Emerald fix 10/29 */
++ osfuncDataCacheHitWritebackAndInvalidate((void *)tcb_ptr, 16);
++
++ }
++ else
++ {
++ Mode=CB_OWNERSHIP_BIT;
++ tcb_ptr->HNext = VirtToPhys((bit32 *)tcb_ptr->Next) - HalDev->offset;
++
++ /* Emerald fix 10/29 */
++ osfuncDataCacheHitWritebackAndInvalidate((void *)tcb_ptr, 16);
++
++ tcb_ptr = tcb_ptr->Next; /* what about the end of TCB list?? */
++
++ if (tcb_ptr == 0)
++ {
++ rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_OUT_OF_TCBS;
++ goto ExitSend;
++ }
++ }
++ } /* for */
++
++ /* put it on the high priority queue */
++ if (HalDev->TxActQueueHead[Ch][Queue] == 0)
++ {
++ HalDev->TxActQueueHead[Ch][Queue]=head;
++ HalDev->TxActQueueTail[Ch][Queue]=tcb_ptr;
++/*+GSG 030303*//*+GSG 030303*/
++ if (!HalDev->TxActive[Ch][Queue])
++ {
++
++ bit32u base = HalDev->dev_base;
++
++ /* write CPPI TX HDP */
++ (CPMAC_TX_HDP( base , Ch )) = VirtToPhys(head) - HalDev->offset;
++ HalDev->TxActive[Ch][Queue]=TRUE;
++
++ }
++ }
++ else
++ {
++ register volatile HAL_TCB *pTailTcb;
++ register bit32u tmode;
++ register bit32u pCurrentTcb;
++
++ HalDev->TxActQueueTail[Ch][Queue]->Next=head;
++ /* Emerald fix 10/29 */
++
++ pTailTcb=(HAL_TCB *)VirtToVirtNoCache(&HalDev->TxActQueueTail[Ch][Queue]->HNext);
++ pCurrentTcb=VirtToPhys(head) - HalDev->offset;
++ pTailTcb->HNext=pCurrentTcb;
++ HalDev->TxActQueueTail[Ch][Queue]=tcb_ptr;
++/*+GSG 030303*/
++ tmode=pTailTcb->mode;
++ if (tmode&CB_EOQ_BIT)
++ {
++ bit32u base = HalDev->dev_base;
++
++ tmode&=~CB_EOQ_BIT;
++ pTailTcb->mode=tmode;
++ ((CPMAC_TX_HDP( base , Ch )) ) = pCurrentTcb;
++ }
++
++ else
++ {
++ if(HalDev->TxIntDisable)
++ {
++ /* Enable Interrupts, to ensure packet goes out on wire */
++ CPMAC_TX_INTMASK_SET(HalDev->dev_base) = (1<<Ch);
++ halPacketProcessEnd(HalDev); /* Allow Interrupt to be seen at the OS */
++ /*DoThresholdCheck = 0; */ /* Disable Threshold Check */
++
++ }
++ }
++
++ }
++ rc = EC_NO_ERRORS;
++ goto ExitSend;
++ } /* if (tcb_ptr) */
++ else
++ {
++ rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_NO_TCBS;
++ goto ExitSend;
++ }
++ExitSend:
++
++/* 15 June 2004 - NSP Performance Update : If Tx Ints are disabled then process them here */
++/* 29 June 2004 - NSP Performance Update : Moved to end at request of BCIL */
++/* 23 Aug 2004 - NSP Performance Update : If Tx Ints are re-enabled do not do Threshold check */
++
++ if(HalDev->TxIntDisable /*&& DoThresholdCheck*/)
++ {
++ if(--HalDev->TxIntThreshold[Ch] <= 0)
++ {
++ int MoreWork;
++ TxInt(HalDev, Ch, 0, &MoreWork);
++ HalDev->TxIntThreshold[Ch] = HalDev->TxIntThresholdMaster[Ch];
++ }
++ }
++ HalDev->OsFunc->CriticalOff();
++
++ return(rc);
++ }
++
++/*
++ * This function processes receive interrupts. It traverses the receive
++ * buffer queue, extracting the data and passing it to the upper layer software via
++ * osReceive(). It handles all error conditions and fragments without valid data by
++ * immediately returning the RCB's to the RCB pool.
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param Ch Channel Number.
++ * @param MoreWork Flag that indicates that there is more work to do when set to 1.
++ *
++ * @return 0 if OK, non-zero otherwise.
++ */
++static int RxInt(HAL_DEVICE *HalDev, int Ch, int *MoreWork)
++ {
++ HAL_RCB *CurrentRcb, *SopRcb, *EofRcb, *EopRcb;
++ bit32u RxBufStatus,PacketsServiced, RxPktLen = 0, RxSopStatus,
++ FrmFrags, TotalFrags, FrmLen;
++ int base = HalDev->dev_base, Ret;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++ int RxServiceMax = HalDev->ChData[Ch].RxServiceMax;
++ int FragIndex; /* +GSG 030508 */
++
++ if(HalDev->NeedsCount) /* +MJH 030410 */
++ NeedsCheck(HalDev); /* +MJH 030410 */
++
++ /* Handle case of teardown interrupt */
++ if (HalDev->RxTeardownPending[Ch] != 0)
++ {
++ Ret = RxTeardownInt(HalDev, Ch);
++ if (Ret == 0)
++ { /*+GSG 030303*/
++ *MoreWork = 0;
++ return (EC_NO_ERRORS);
++ } /*+GSG 030303*/
++ }
++
++ /* Examine first RCB on the software active queue */
++ CurrentRcb=HalDev->RxActQueueHead[Ch];
++ osfuncDataCacheHitInvalidate((void*)CurrentRcb, 16);
++ RxBufStatus=CurrentRcb->mode;
++ PacketsServiced=0;
++
++ /* Process received packets until we find hardware owned descriptors
++ or until we hit RxServiceMax */
++ while((CurrentRcb)&&((RxBufStatus&CB_OWNERSHIP_BIT)==0)&&
++ (PacketsServiced<RxServiceMax)) /* ~GSG 030307 */
++ {
++
++ PacketsServiced++; /* ~GSG 030307 */
++ SopRcb=CurrentRcb;
++ RxSopStatus=RxBufStatus;
++ RxPktLen = RxSopStatus&CB_SIZE_MASK;
++
++ FrmFrags=0;
++ TotalFrags=0;
++ FragIndex=0;
++ FrmLen=0;
++ EofRcb=0;
++
++/* +GSG 030508 *//* +GSG 030508 */
++
++ /* Loop through all fragments that comprise current packet. Build
++ fraglist and exit when the end of the packet is reached, or the
++ end of the descriptor list is reached. */
++ do
++ {
++ bit32u DmaLen;
++
++
++ DmaLen=CurrentRcb->Off_BLen;
++
++ FrmLen+=DmaLen;
++ TotalFrags++;
++ if (!EofRcb)
++ {
++ HalDev->fraglist[FragIndex].data=((char *)CurrentRcb->DatPtr); /* ~GSG 030508 */
++
++ HalDev->fraglist[FragIndex].len=DmaLen; /* ~GSG 030508 */
++
++ /* GSG 12/9 */
++ HalDev->fraglist[FragIndex].OsInfo = CurrentRcb->OsInfo; /* ~GSG 030508 */
++
++ /* Upper layer must do the data invalidate */
++
++ FrmFrags++;
++ FragIndex++; /* ~GSG 030508 */
++ if (FrmLen>=RxPktLen)
++ EofRcb=CurrentRcb;
++ }
++ EopRcb=CurrentRcb;
++ CurrentRcb=EopRcb->Next;
++ if (CurrentRcb)
++ {
++ osfuncDataCacheHitInvalidate((void*)CurrentRcb,16);
++ }
++ }while(((EopRcb->mode&CB_EOF_BIT)==0)&&(CurrentRcb));
++
++ /* Write the completion pointer for interrupt acknowledgement*/
++ (CPMAC_RX_INT_ACK( base , Ch )) = VirtToPhys(EopRcb) - HalDev->offset;
++
++ EopRcb->Next=0;
++
++ if (CurrentRcb == 0)
++ {
++ /* If we are out of RCB's we must not send this packet
++ to the OS. */
++ int RcbSize = HalDev->ChData[Ch].RxBufSize;
++
++ if (TotalFrags>1)
++ {
++ EopRcb->Off_BLen=RcbSize;
++ EopRcb->mode=CB_OWNERSHIP_BIT;
++ osfuncDataCacheHitWritebackAndInvalidate((void *)EopRcb, 16);
++ }
++
++ SopRcb->Off_BLen=RcbSize;
++ SopRcb->mode=CB_OWNERSHIP_BIT;
++ osfuncDataCacheHitWritebackAndInvalidate((void *)SopRcb, 16);
++
++ ((CPMAC_RX_HDP( base , Ch )) ) = VirtToPhys(SopRcb);
++ }
++ else
++ {
++ /* Dequeue packet and send to OS */
++ int mode;
++
++ /* setup SopRcb for the packet */
++ SopRcb->Eop=(void*)EopRcb;
++
++ /* dequeue packet */
++ HalDev->RxActQueueHead[Ch]=CurrentRcb;
++
++ if (EopRcb->mode&CB_EOQ_BIT)
++ {
++ /* Next pointer is non-null and EOQ bit is set, which
++ indicates misqueue packet in CPPI protocol. */
++
++ ((CPMAC_RX_HDP( base , Ch )) ) = EopRcb->HNext;
++ }
++
++ mode = (SopRcb->mode & 0xFFFF0000) | Ch;
++
++ SopRcb->mode=(FrmFrags<<8)|Ch;
++ SopRcb->Off_BLen=(bit32u)HalDev;
++
++ /* send packet up the higher layer driver */
++ OsFunc->Receive(HalDev->OsDev,HalDev->fraglist,FragIndex,RxPktLen, /* ~GSG 030508 */
++ (HAL_RECEIVEINFO *)SopRcb,mode);
++
++ RxBufStatus=CurrentRcb->mode;
++ }
++ } /* while loop */
++
++ if ((CurrentRcb)&&((RxBufStatus&CB_OWNERSHIP_BIT)==0)) /*~GSG 030307*/
++ {
++ *MoreWork = 1;
++ }
++ else
++ {
++ *MoreWork = 0;
++ }
++
++ return (EC_NO_ERRORS);
++}
++
++/*
++ * This function processes transmit interrupts. It traverses the
++ * transmit buffer queue, detecting sent data buffers and notifying the upper
++ * layer software via osSendComplete(). (for SAR, i originally had this split
++ * into two functions, one for each queue, but joined them on 8/8/02)
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param Queue Queue number to service (always 0 for MAC, Choose 1 for SAR to service low priority queue)
++ * @param MoreWork Flag that indicates that there is more work to do when set to 1.
++ *
++ * @return 0 if OK, non-zero otherwise.
++ */
++int TxInt(HAL_DEVICE *HalDev, int Ch, int Queue, int *MoreWork)
++ {
++ HAL_TCB *CurrentTcb,*LastTcbProcessed,*FirstTcbProcessed;
++ int PacketsServiced;
++ bit32u TxFrameStatus;
++ int base;
++ int TxServiceMax = HalDev->ChData[Ch].TxServiceMax;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++
++/*+GSG 030303*//*+GSG 030303*/
++
++ /* load the module base address */
++ base = HalDev->dev_base;
++
++ /* Handle case of teardown interrupt. This must be checked at
++ the top of the function rather than the bottom, because
++ the normal data processing can wipe out the completion
++ pointer which is used to determine teardown complete. */
++ if (HalDev->TxTeardownPending[Ch] != 0)
++ {
++ int Ret;
++
++ Ret = TxTeardownInt(HalDev, Ch, Queue);
++ if (Ret == 0)
++ { /*+GSG 030303*/
++ *MoreWork = 0; /* bug fix 1/6 */ /*+GSG 030303*/
++ return (EC_NO_ERRORS);
++ } /*+GSG 030303*/
++ }
++
++ OsFunc->CriticalOn(); /* 240904 */
++
++ CurrentTcb = HalDev->TxActQueueHead[Ch][Queue];
++ FirstTcbProcessed=CurrentTcb;
++
++ if (CurrentTcb==0)
++ {
++ /* I saw this error a couple of times when multi-channels were added */
++ dbgPrintf("[cppi TxInt()]TxH int with no TCB in queue!\n");
++ dbgPrintf(" Ch=%d, CurrentTcb = 0x%08x\n", Ch, (bit32u)CurrentTcb);
++ dbgPrintf(" HalDev = 0x%08x\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ OsFunc->CriticalOff();
++ return(EC_CPPI|EC_FUNC_TXINT|EC_VAL_NULL_TCB);
++ }
++
++ osfuncDataCacheHitInvalidate((void *)CurrentTcb, 16);
++ TxFrameStatus=CurrentTcb->mode;
++ PacketsServiced=0;
++
++ /* should the ownership bit check be inside of the loop?? could make it a
++ while-do loop and take this check away */
++ if ((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
++ {
++ do
++ {
++ /* Pop TCB(s) for packet from the stack */
++ LastTcbProcessed=CurrentTcb->Eop;
++
++ /* new location for acknowledge */
++ /* Write the completion pointer */
++ (CPMAC_TX_INT_ACK( base , Ch )) = VirtToPhys(LastTcbProcessed) - HalDev->offset;
++
++ HalDev->TxActQueueHead[Ch][Queue] = LastTcbProcessed->Next;
++
++/*+GSG 030303*//*+GSG 030303*/
++
++ osfuncDataCacheHitInvalidate((void *)LastTcbProcessed, 16);
++
++ if (LastTcbProcessed->mode&CB_EOQ_BIT)
++ {
++ if (LastTcbProcessed->Next)
++ {
++ /* Misqueued packet */
++
++ (CPMAC_TX_HDP( base , Ch )) = LastTcbProcessed->HNext;
++
++ }
++ else
++ {
++ /* Tx End of Queue */
++
++ HalDev->TxActive[Ch][Queue]=FALSE;
++ }
++ }
++
++ OsFunc->SendComplete(CurrentTcb->OsInfo);
++
++ /* Push Tcb(s) back onto the stack */
++ CurrentTcb = LastTcbProcessed->Next;
++
++ LastTcbProcessed->Next=HalDev->TcbPool[Ch][Queue];
++
++ HalDev->TcbPool[Ch][Queue]=FirstTcbProcessed;
++
++ PacketsServiced++;
++
++ TxFrameStatus=CB_OWNERSHIP_BIT;
++ /* set the first(SOP) pointer for the next packet */
++ FirstTcbProcessed = CurrentTcb;
++ if (CurrentTcb)
++ {
++ osfuncDataCacheHitInvalidate((void *)CurrentTcb, 16);
++ TxFrameStatus=CurrentTcb->mode;
++ }
++
++ }while(((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
++ &&(PacketsServiced<TxServiceMax));
++
++ if (((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
++ &&(PacketsServiced==TxServiceMax))
++ {
++ *MoreWork = 1;
++ }
++ else
++ {
++ *MoreWork = 0;
++ }
++ }
++ OsFunc->CriticalOff();
++
++ return(EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function performs a teardown for the given channel. The value of the
++ * Mode parameter controls the operation of the function, as documented below.
++ *
++ * Note: If bit 3 of Mode is set, this call is blocking, and will not return
++ * until the teardown interrupt has occurred and been processed. While waiting
++ * for a blocking teardown to complete, ChannelTeardown() will signal the OS
++ * (via Control(.."Sleep"..)) to allow the OS to perform other tasks if
++ * necessary. If and only if bit 3 of Mode is clear, the CPHAL will call the
++ * OS TeardownComplete() function to indicate that the teardown has completed.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param Ch Channel number.
++ * @param Mode Bit 0 (LSB): Perform Tx teardown (if set).<BR>
++ * Bit 1: Perform Rx teardown (if set). <BR>
++ * Bit 2: If set, perform full teardown (free buffers/descriptors).
++ * If clear, perform partial teardown (keep buffers). <BR>
++ * Bit 3 (MSB): If set, call is blocking.
++ * If clear, call is non-blocking.
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
++ * @ref EC_VAL_TX_TEARDOWN_ALREADY_PEND "EC_VAL_TX_TEARDOWN_ALREADY_PEND"<BR>
++ * @ref EC_VAL_RX_TEARDOWN_ALREADY_PEND "EC_VAL_RX_TEARDOWN_ALREADY_PEND"<BR>
++ * @ref EC_VAL_TX_CH_ALREADY_TORNDOWN "EC_VAL_TX_CH_ALREADY_TORNDOWN"<BR>
++ * @ref EC_VAL_RX_CH_ALREADY_TORNDOWN "EC_VAL_RX_CH_ALREADY_TORNDOWN"<BR>
++ * @ref EC_VAL_TX_TEARDOWN_TIMEOUT "EC_VAL_TX_TEARDOWN_TIMEOUT"<BR>
++ * @ref EC_VAL_RX_TEARDOWN_TIMEOUT "EC_VAL_RX_TEARDOWN_TIMEOUT"<BR>
++ * @ref EC_VAL_LUT_NOT_READY "EC_VAL_LUT_NOT_READY"<BR>
++ */
++static int halChannelTeardown(HAL_DEVICE *HalDev, int Ch, bit32 Mode)
++ {
++ int DoTx, DoRx, Sleep=2048, timeout=0; /*MJH~030306*/
++ bit32u base = HalDev->dev_base;
++
++/* Set the module, used for error returns */
++
++ DoTx = (Mode & TX_TEARDOWN);
++ DoRx = (Mode & RX_TEARDOWN);
++
++ if (HalDev->State < enInitialized)
++ return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_INVALID_STATE);
++
++ if ((Ch < 0) || (Ch > (MAX_CHAN-1) ))
++ {
++ return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_INVALID_CH);
++ }
++
++ /* set teardown pending bits before performing the teardown, because they
++ will be used in the int handler (this is done for AAL5) */
++ if (DoTx)
++ {
++ if (HalDev->TxTeardownPending[Ch] != 0)
++ return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_TX_TEARDOWN_ALREADY_PEND);
++
++ /* If a full teardown, this also means that the user must
++ setup all channels again to use them */
++ if (Mode & FULL_TEARDOWN)
++ HalDev->ChIsSetup[Ch][DIRECTION_TX] = 0;
++
++ if (HalDev->State < enOpened)
++ {
++ /* if the hardware has never been opened, the channel has never actually
++ been setup in the hardware, so I just need to reset the software flag
++ and leave */
++ HalDev->ChIsSetup[Ch][DIRECTION_TX] = 0;
++ return (EC_NO_ERRORS);
++ }
++ else
++ {
++ if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == 0)
++ {
++ return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_TX_CH_ALREADY_TORNDOWN);
++ }
++
++ /* set teardown flag */
++ HalDev->TxTeardownPending[Ch] = Mode;
++ }
++ }
++
++ if (DoRx)
++ {
++ if (HalDev->RxTeardownPending[Ch] != 0)
++ return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_RX_TEARDOWN_ALREADY_PEND);
++
++ if (Mode & FULL_TEARDOWN)
++ HalDev->ChIsSetup[Ch][DIRECTION_RX] = 0;
++
++ if (HalDev->State < enOpened)
++ {
++ HalDev->ChIsSetup[Ch][DIRECTION_RX] = 0;
++ return (EC_NO_ERRORS);
++ }
++ else
++ {
++ if (HalDev->ChIsOpen[Ch][DIRECTION_RX] == 0)
++ return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_RX_CH_ALREADY_TORNDOWN);
++
++ HalDev->RxTeardownPending[Ch] = Mode;
++ }
++ }
++
++ /* Perform Tx Teardown Duties */
++ if ((DoTx) && (HalDev->State == enOpened))
++ {
++ /* Request TX channel teardown */
++ (CPMAC_TX_TEARDOWN( base )) = Ch;
++
++ /* wait until teardown has completed */
++ if (Mode & BLOCKING_TEARDOWN)
++ {
++ timeout = 0;
++ while (HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE)
++ {
++ osfuncSleep(&Sleep);
++
++ timeout++;
++ if (timeout > 100000)
++ {
++ return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_TX_TEARDOWN_TIMEOUT);
++ }
++ }
++ }
++ } /* if DoTx */
++
++ /* Perform Rx Teardown Duties */
++ if ((DoRx) && (HalDev->State == enOpened))
++ {
++
++ /* perform CPMAC specific RX channel teardown */
++ CPMAC_RX_TEARDOWN(base) = Ch;
++
++ if (Mode & BLOCKING_TEARDOWN)
++ {
++ timeout = 0;
++ while (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE)
++ {
++ osfuncSleep(&Sleep);
++
++ timeout++;
++ if (timeout > 100000)
++ {
++ return(EC_CPMAC |EC_FUNC_CHTEARDOWN|EC_VAL_RX_TEARDOWN_TIMEOUT);
++ }
++ }
++ }
++ } /* if DoRx */
++
++ return (EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function closes the CPHAL module. The module will be reset.
++ * The Mode parameter should be used to determine the actions taken by
++ * Close().
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param Mode Indicates actions to take on close. The following integer
++ * values are valid: <BR>
++ * 1: Does not free buffer resources, init parameters remain
++ * intact. User can then call Open() without calling Init()
++ * to attempt to reset the device and bring it back to the
++ * last known state.<BR>
++ * 2: Frees the buffer resources, but keeps init parameters. This
++ * option is a more aggressive means of attempting a device reset.
++ * 3: Frees the buffer resources, and clears all init parameters. <BR>
++ * At this point, the caller would have to call to completely
++ * reinitialize the device (Init()) before being able to call
++ * Open(). Use this mode if you are shutting down the module
++ * and do not plan to restart.
++ *
++ * @return EC_NO_ERRORS (ok).<BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * Any error code from halChannelTeardown().<BR>
++ */
++static int halClose(HAL_DEVICE *HalDev, bit32 Mode)
++ {
++ int Ch, Inst, Ret;
++ OS_DEVICE *TmpOsDev;
++ OS_FUNCTIONS *TmpOsFunc;
++ HAL_FUNCTIONS *TmpHalFunc;
++ char *TmpDeviceInfo;
++
++ int Ticks; /*MJH~030306*/
++
++ /* Verify proper device state */
++ if (HalDev->State != enOpened)
++ return (EC_CPMAC | EC_FUNC_CLOSE|EC_VAL_INVALID_STATE);
++
++ /* Teardown all open channels */
++ for (Ch = 0; Ch <= (MAX_CHAN-1) ; Ch++)
++ {
++ if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE)
++ {
++ if (Mode == 1)
++ {
++ Ret = halChannelTeardown(HalDev, Ch, TX_TEARDOWN | PARTIAL_TEARDOWN | BLOCKING_TEARDOWN);
++ if (Ret) return (Ret);
++ }
++ else
++ {
++ Ret = halChannelTeardown(HalDev, Ch, TX_TEARDOWN | FULL_TEARDOWN | BLOCKING_TEARDOWN);
++ if (Ret) return (Ret);
++ }
++ }
++
++ if (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE)
++ {
++ if (Mode == 1)
++ {
++ Ret = halChannelTeardown(HalDev, Ch, RX_TEARDOWN | PARTIAL_TEARDOWN | BLOCKING_TEARDOWN);
++ if (Ret) return (Ret);
++ }
++ else
++ {
++ Ret = halChannelTeardown(HalDev, Ch, RX_TEARDOWN | FULL_TEARDOWN | BLOCKING_TEARDOWN);
++ if (Ret) return (Ret);
++ }
++ }
++ }
++
++ /* free fraglist in HalDev */
++ HalDev->OsFunc->Free(HalDev->fraglist);
++ HalDev->fraglist = 0;
++
++ /* unregister the interrupt */
++ HalDev->OsFunc->IsrUnRegister(HalDev->OsDev, HalDev->interrupt);
++
++ Ticks = 0; /* Disable Tick Timer */ /*MJH+030306*/
++ HalDev->OsFunc->Control(HalDev->OsDev, hcTick, hcClear, &Ticks); /*MJH+030306*/
++
++ /* Free the Phy Information Structure */
++ if(HalDev->PhyDev)
++ {
++ HalDev->OsFunc->Free(HalDev->PhyDev); /*MJH+030513*/
++ HalDev->PhyDev = 0; /*MJH+030522*/
++ }
++
++ /* Perform CPMAC specific closing functions */
++ CPMAC_MACCONTROL(HalDev->dev_base) &= ~MII_EN;
++ CPMAC_TX_CONTROL(HalDev->dev_base) &= ~TX_EN;
++ CPMAC_RX_CONTROL(HalDev->dev_base) &= ~RX_EN;
++
++ /* put device back into reset */
++ (*(volatile bit32u *)(HalDev->ResetBase)) &=~ (1<<HalDev->ResetBit);
++ Ticks = 64; /*MJH~030306*/
++ osfuncSleep(&Ticks);
++
++ /* If mode is 3, than clear the HalDev and set next state to DevFound*/
++ if (Mode == 3)
++ {
++ /* I need to keep the HalDev parameters that were setup in InitModule */
++ TmpOsDev = HalDev->OsDev;
++ TmpOsFunc = HalDev->OsFunc;
++ TmpDeviceInfo = HalDev->DeviceInfo;
++
++ TmpHalFunc = HalDev->HalFuncPtr;
++ Inst = HalDev->Inst;
++
++ /* Clear HalDev */
++
++ HalDev->OsFunc->Memset(HalDev, 0, sizeof(HAL_DEVICE));
++
++ /* Restore key parameters */
++ HalDev->OsDev = TmpOsDev;
++ HalDev->OsFunc = TmpOsFunc;
++ HalDev->DeviceInfo = TmpDeviceInfo;
++
++ HalDev->HalFuncPtr = TmpHalFunc;
++ HalDev->Inst = Inst;
++
++ HalDev->State = enDevFound;
++ }
++ else
++ {
++ HalDev->State = enInitialized;
++ }
++
++ return(EC_NO_ERRORS);
++ }
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpremap_cpmac.c linux.dev/drivers/net/avalanche_cpmac/cpremap_cpmac.c
+--- linux.old/drivers/net/avalanche_cpmac/cpremap_cpmac.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpremap_cpmac.c 2005-07-12 02:48:42.049593000 +0200
+@@ -0,0 +1,28 @@
++#ifndef _INC_CPREMAP_C
++#define _INC_CPREMAP_C
++
++#ifdef __ADAM2
++static inline void osfuncDataCacheHitInvalidate(void *ptr, int Size)
++ {
++ asm(" cache 17, (%0)" : : "r" (ptr));
++ }
++
++static inline void osfuncDataCacheHitWriteback(void *ptr, int Size)
++ {
++ asm(" cache 25, (%0)" : : "r" (ptr));
++ }
++
++static inline void osfuncDataCacheHitWritebackAndInvalidate(void *ptr, int Size)
++ {
++ asm(" cache 21, (%0)" : : "r" (ptr));
++ }
++
++#else
++
++#define osfuncDataCacheHitInvalidate(MemPtr, Size) __asm__(" .set mips3; cache 17, (%0); .set mips0" : : "r" (MemPtr))
++#define osfuncDataCacheHitWritebackAndInvalidate(MemPtr, Size) __asm__(" .set mips3; cache 21, (%0); .set mips0" : : "r" (MemPtr))
++#define osfuncDataCacheHitWriteback(MemPtr, Size) __asm__(" .set mips3; cache 25, (%0); .set mips0" : : "r" (MemPtr))
++
++#endif
++
++#endif
+diff -urN linux.old/drivers/net/avalanche_cpmac/cpswhal_cpmac.h linux.dev/drivers/net/avalanche_cpmac/cpswhal_cpmac.h
+--- linux.old/drivers/net/avalanche_cpmac/cpswhal_cpmac.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/cpswhal_cpmac.h 2005-07-12 02:48:42.050593000 +0200
+@@ -0,0 +1,632 @@
++/************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE: cphal.h
++ *
++ * DESCRIPTION:
++ * User include file, contains data definitions shared between the CPHAL
++ * and the upper-layer software.
++ *
++ * HISTORY:
++ * Date Modifier Ver Notes
++ * 28Feb02 Greg 1.00 Original
++ * 06Mar02 Greg 1.01 Documentation enhanced
++ * 18Jul02 Greg 1.02 Many updates (OAM additions, general reorg)
++ * 22Nov02 Mick RC2 Additions from Denis' input on Control
++ *
++ * author Greg Guyotte
++ * version 1.02
++ * date 18-Jul-2002
++ *****************************************************************************/
++#ifndef _INC_CPHAL_H
++#define _INC_CPHAL_H
++
++#ifdef _CPHAL_CPMAC
++#include "ec_errors_cpmac.h"
++#endif
++
++#ifdef _CPHAL_AAL5
++#include "ec_errors_cpaal5.h"
++#endif
++
++#ifdef _CPHAL_CPSAR
++#include "ec_errors_cpsar.h"
++#endif
++
++#ifdef _CPHAL_AAL2
++#include "ec_errors_cpaal2.h"
++#endif
++
++#ifndef __ADAM2
++typedef char bit8;
++typedef short bit16;
++typedef int bit32;
++
++typedef unsigned char bit8u;
++typedef unsigned short bit16u;
++typedef unsigned int bit32u;
++
++/*
++typedef char INT8;
++typedef short INT16;
++typedef int INT32;
++typedef unsigned char UINT8;
++typedef unsigned short UINT16;
++typedef unsigned int UINT32;
++*/
++/*typedef unsigned int size_t;*/
++#endif
++
++#ifdef _CPHAL
++
++#ifndef TRUE
++#define TRUE (1==1)
++#endif
++
++#ifndef FALSE
++#define FALSE (1==2)
++#endif
++
++#ifndef NULL
++#define NULL 0
++#endif
++
++#endif
++
++#define VirtToPhys(a) (((int)a)&~0xe0000000)
++#define VirtToVirtNoCache(a) ((void*)((VirtToPhys(a))|0xa0000000))
++#define VirtToVirtCache(a) ((void*)((VirtToPhys(a))|0x80000000))
++#define PhysToVirtNoCache(a) ((void*)(((int)a)|0xa0000000))
++#define PhysToVirtCache(a) ((void*)(((int)a)|0x80000000))
++/*
++#define DataCacheHitInvalidate(a) {__asm__(" cache 17, (%0)" : : "r" (a));}
++#define DataCacheHitWriteback(a) {__asm__(" cache 25, (%0)" : : "r" (a));}
++*/
++
++#define PARTIAL 1 /**< Used in @c Close() and @c ChannelTeardown() */
++#define FULL 2 /**< Used in @c Close() and @c ChannelTeardown() */
++
++/* Channel Teardown Defines */
++#define RX_TEARDOWN 2
++#define TX_TEARDOWN 1
++#define BLOCKING_TEARDOWN 8
++#define FULL_TEARDOWN 4
++#define PARTIAL_TEARDOWN 0
++
++#define MAX_DIR 2
++#define DIRECTION_TX 0
++#define DIRECTION_RX 1
++#define TX_CH 0
++#define RX_CH 1
++#define HAL_ERROR_DEVICE_NOT_FOUND 1
++#define HAL_ERROR_FAILED_MALLOC 2
++#define HAL_ERROR_OSFUNC_SIZE 3
++#define HAL_DEFAULT 0xFFFFFFFF
++#define VALID(val) (val!=HAL_DEFAULT)
++
++/*
++ERROR REPORTING
++
++HAL Module Codes. Each HAL module reporting an error code
++should OR the error code with the respective Module error code
++from the list below.
++*/
++#define EC_AAL5 EC_HAL|EC_DEV_AAL5
++#define EC_AAL2 EC_HAL|EC_DEV_AAL2
++#define EC_CPSAR EC_HAL|EC_DEV_CPSAR
++#define EC_CPMAC EC_HAL|EC_DEV_CPMAC
++#define EC_VDMA EC_HAL|EC_DEV_VDMA
++#define EC_VLYNQ EC_HAL|EC_DEV_VLYNQ
++#define EC_CPPI EC_HAL|EC_DEV_CPPI
++
++/*
++HAL Function Codes. Each HAL module reporting an error code
++should OR the error code with one of the function codes from
++the list below.
++*/
++#define EC_FUNC_HAL_INIT EC_FUNC(1)
++#define EC_FUNC_CHSETUP EC_FUNC(2)
++#define EC_FUNC_CHTEARDOWN EC_FUNC(3)
++#define EC_FUNC_RXRETURN EC_FUNC(4)
++#define EC_FUNC_SEND EC_FUNC(5)
++#define EC_FUNC_RXINT EC_FUNC(6)
++#define EC_FUNC_TXINT EC_FUNC(7)
++#define EC_FUNC_AAL2_VDMA EC_FUNC(8)
++#define EC_FUNC_OPTIONS EC_FUNC(9)
++#define EC_FUNC_PROBE EC_FUNC(10)
++#define EC_FUNC_OPEN EC_FUNC(11)
++#define EC_FUNC_CONTROL EC_FUNC(12)
++#define EC_FUNC_DEVICE_INT EC_FUNC(13)
++#define EC_FUNC_STATUS EC_FUNC(14)
++#define EC_FUNC_TICK EC_FUNC(15)
++#define EC_FUNC_CLOSE EC_FUNC(16)
++#define EC_FUNC_SHUTDOWN EC_FUNC(17)
++#define EC_FUNC_DEVICE_INT_ALT EC_FUNC(18) /* +GSG 030306 */
++
++/*
++HAL Error Codes. The list below defines every type of error
++used in all HAL modules. DO NOT CHANGE THESE VALUES! Add new
++values in integer order to the bottom of the list.
++*/
++#define EC_VAL_PDSP_LOAD_FAIL EC_ERR(0x01)|EC_CRITICAL
++#define EC_VAL_FIRMWARE_TOO_LARGE EC_ERR(0x02)|EC_CRITICAL
++#define EC_VAL_DEVICE_NOT_FOUND EC_ERR(0x03)|EC_CRITICAL
++#define EC_VAL_BASE_ADDR_NOT_FOUND EC_ERR(0x04)|EC_CRITICAL
++#define EC_VAL_RESET_BIT_NOT_FOUND EC_ERR(0x05)|EC_CRITICAL
++#define EC_VAL_CH_INFO_NOT_FOUND EC_ERR(0x06)
++#define EC_VAL_RX_STATE_RAM_NOT_CLEARED EC_ERR(0x07)|EC_CRITICAL
++#define EC_VAL_TX_STATE_RAM_NOT_CLEARED EC_ERR(0x08)|EC_CRITICAL
++#define EC_VAL_MALLOC_DEV_FAILED EC_ERR(0x09)
++#define EC_VAL_OS_VERSION_NOT_SUPPORTED EC_ERR(0x0A)|EC_CRITICAL
++#define EC_VAL_CPSAR_VERSION_NOT_SUPPORTED EC_ERR(0x0B)|EC_CRITICAL
++#define EC_VAL_NULL_CPSAR_DEV EC_ERR(0x0C)|EC_CRITICAL
++
++#define EC_VAL_LUT_NOT_READY EC_ERR(0x0D)
++#define EC_VAL_INVALID_CH EC_ERR(0x0E)
++#define EC_VAL_NULL_CH_STRUCT EC_ERR(0x0F)
++#define EC_VAL_RX_TEARDOWN_ALREADY_PEND EC_ERR(0x10)
++#define EC_VAL_TX_TEARDOWN_ALREADY_PEND EC_ERR(0x11)
++#define EC_VAL_RX_CH_ALREADY_TORNDOWN EC_ERR(0x12)
++#define EC_VAL_TX_CH_ALREADY_TORNDOWN EC_ERR(0x13)
++#define EC_VAL_TX_TEARDOWN_TIMEOUT EC_ERR(0x14)
++#define EC_VAL_RX_TEARDOWN_TIMEOUT EC_ERR(0x15)
++#define EC_VAL_CH_ALREADY_TORNDOWN EC_ERR(0x16)
++#define EC_VAL_VC_SETUP_NOT_READY EC_ERR(0x17)
++#define EC_VAL_VC_TEARDOWN_NOT_READY EC_ERR(0x18)
++#define EC_VAL_INVALID_VC EC_ERR(0x19)
++#define EC_VAL_INVALID_LC EC_ERR(0x20)
++#define EC_VAL_INVALID_VDMA_CH EC_ERR(0x21)
++#define EC_VAL_INVALID_CID EC_ERR(0x22)
++#define EC_VAL_INVALID_UUI EC_ERR(0x23)
++#define EC_VAL_INVALID_UUI_DISCARD EC_ERR(0x24)
++#define EC_VAL_CH_ALREADY_OPEN EC_ERR(0x25)
++
++#define EC_VAL_RCB_MALLOC_FAILED EC_ERR(0x26)
++#define EC_VAL_RX_BUFFER_MALLOC_FAILED EC_ERR(0x27)
++#define EC_VAL_OUT_OF_TCBS EC_ERR(0x28)
++#define EC_VAL_NO_TCBS EC_ERR(0x29)
++#define EC_VAL_NULL_RCB EC_ERR(0x30)|EC_CRITICAL
++#define EC_VAL_SOP_ERROR EC_ERR(0x31)|EC_CRITICAL
++#define EC_VAL_EOP_ERROR EC_ERR(0x32)|EC_CRITICAL
++#define EC_VAL_NULL_TCB EC_ERR(0x33)|EC_CRITICAL
++#define EC_VAL_CORRUPT_RCB_CHAIN EC_ERR(0x34)|EC_CRITICAL
++#define EC_VAL_TCB_MALLOC_FAILED EC_ERR(0x35)
++
++#define EC_VAL_DISABLE_POLLING_FAILED EC_ERR(0x36)
++#define EC_VAL_KEY_NOT_FOUND EC_ERR(0x37)
++#define EC_VAL_MALLOC_FAILED EC_ERR(0x38)
++#define EC_VAL_RESET_BASE_NOT_FOUND EC_ERR(0x39)|EC_CRITICAL
++#define EC_VAL_INVALID_STATE EC_ERR(0x40)
++#define EC_VAL_NO_TXH_WORK_TO_DO EC_ERR(0x41)
++#define EC_VAL_NO_TXL_WORK_TO_DO EC_ERR(0x42)
++#define EC_VAL_NO_RX_WORK_TO_DO EC_ERR(0x43)
++#define EC_VAL_NOT_LINKED EC_ERR(0x44)
++#define EC_VAL_INTERRUPT_NOT_FOUND EC_ERR(0x45)
++#define EC_VAL_OFFSET_NOT_FOUND EC_ERR(0x46)
++#define EC_VAL_MODULE_ALREADY_CLOSED EC_ERR(0x47)
++#define EC_VAL_MODULE_ALREADY_SHUTDOWN EC_ERR(0x48)
++#define EC_VAL_ACTION_NOT_FOUND EC_ERR(0x49)
++#define EC_VAL_RX_CH_ALREADY_SETUP EC_ERR(0x50)
++#define EC_VAL_TX_CH_ALREADY_SETUP EC_ERR(0x51)
++#define EC_VAL_RX_CH_ALREADY_OPEN EC_ERR(0x52)
++#define EC_VAL_TX_CH_ALREADY_OPEN EC_ERR(0x53)
++#define EC_VAL_CH_ALREADY_SETUP EC_ERR(0x54)
++#define EC_VAL_RCB_NEEDS_BUFFER EC_ERR(0x55) /* +GSG 030410 */
++#define EC_VAL_RCB_DROPPED EC_ERR(0x56) /* +GSG 030410 */
++#define EC_VAL_INVALID_VALUE EC_ERR(0x57)
++
++/**
++@defgroup shared_data Shared Data Structures
++
++The data structures documented here are shared by all modules.
++*/
++
++/**
++ * @ingroup shared_data
++ * This is the fragment list structure. Each fragment list entry contains a
++ * length and a data buffer.
++ */
++typedef struct
++ {
++ bit32u len; /**< Length of the fragment in bytes (lower 16 bits are valid). For SOP, upper 16 bits is the buffer offset. */
++ void *data; /**< Pointer to fragment data. */
++ void *OsInfo; /**< Pointer to OS defined data. */
++ }FRAGLIST;
++
++#if defined (_CPHAL_CPMAC)
++#define CB_PASSCRC_BIT (1<<26)
++
++/* CPMAC CPHAL STATUS */
++#define CPMAC_STATUS_LINK (1 << 0)
++#define CPMAC_STATUS_LINK_DUPLEX (1 << 1) /* 0 - HD, 1 - FD */
++#define CPMAC_STATUS_LINK_SPEED (1 << 2) /* 0 - 10, 1 - 100 */
++
++/* ADAPTER CHECK Codes */
++
++#define CPMAC_STATUS_ADAPTER_CHECK (1 << 7)
++#define CPMAC_STATUS_HOST_ERR_DIRECTION (1 << 8)
++#define CPMAC_STATUS_HOST_ERR_CODE (0xF << 9)
++#define CPMAC_STATUS_HOST_ERR_CH (0x7 << 13)
++
++#define _CPMDIO_DISABLE (1 << 0)
++#define _CPMDIO_HD (1 << 1)
++#define _CPMDIO_FD (1 << 2)
++#define _CPMDIO_10 (1 << 3)
++#define _CPMDIO_100 (1 << 4)
++#define _CPMDIO_NEG_OFF (1 << 5)
++#define _CPMDIO_LOOPBK (1 << 16)
++#define _CPMDIO_AUTOMDIX (1 << 17) /* Bit 16 and above not used by MII register */
++#define _CPMDIO_NOPHY (1 << 20)
++#endif
++
++/**
++ * @ingroup shared_data
++ * Channel specific configuration information. This structure should be
++ * populated by upper-layer software prior to calling @c ChannelSetup(). Any
++ * configuration item that can be changed on a per channel basis should
++ * be represented here. Each module may define this structure with additional
++ * module-specific members.
++ */
++typedef struct
++ {
++ int Channel; /**< Channel number. */
++ int Direction; /**< DIRECTION_RX(1) or DIRECTION_TX(0). */
++ OS_SETUP *OsSetup; /**< OS defined information associated with this channel. */
++
++#if defined(_CPHAL_AAL5) || defined (_CPHAL_CPSAR) || defined (_CPHAL_CPMAC)
++ int RxBufSize; /**< Size (in bytes) for each Rx buffer.*/
++ int RxBufferOffset; /**< Number of bytes to offset rx data from start of buffer (must be less than buffer size). */
++ int RxNumBuffers; /**< The number of Rx buffer descriptors to allocate for Ch. */
++ int RxServiceMax; /**< Maximum number of packets to service at one time. */
++
++ int TxNumBuffers; /**< The number of Tx buffer descriptors to allocate for Ch. */
++ int TxNumQueues; /**< Number of Tx queues for this channel (1-2). Choosing 2 enables a low priority SAR queue. */
++ int TxServiceMax; /**< Maximum number of packets to service at one time. */
++#endif
++
++#if defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
++ int CpcsUU; /**< The 2-byte CPCS UU and CPI information. */
++ int Gfc; /**< Generic Flow Control. */
++ int Clp; /**< Cell Loss Priority. */
++ int Pti; /**< Payload Type Indication. */
++#endif
++
++#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
++ int DaMask; /**< Specifies whether credit issuance is paused when Tx data not available. */
++ int Priority; /**< Priority bin this channel will be scheduled within. */
++ int PktType; /**< 0=AAL5,1=Null AAL,2=OAM,3=Transparent,4=AAL2. */
++ int Vci; /**< Virtual Channel Identifier. */
++ int Vpi; /**< Virtual Path Identifier. */
++ int FwdUnkVc; /**< Enables forwarding of unknown VCI/VPI cells to host. 1=enable, 0=disable. */
++
++ /* Tx VC State */
++ int TxVc_CellRate; /**< Tx rate, set as clock ticks between transmissions (SCR for VBR, CBR for CBR). */
++ int TxVc_QosType; /**< 0=CBR,1=VBR,2=UBR,3=UBRmcr. */
++ int TxVc_Mbs; /**< Min Burst Size in cells.*/
++ int TxVc_Pcr; /**< Peak Cell Rate for VBR in clock ticks between transmissions. */
++
++ bit32 TxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Tx Ch (must be big endian with 0 PTI). */
++ int TxVc_OamTc; /**< TC Path to transmit OAM cells for TX connection (0,1). */
++ int TxVc_VpOffset; /**< Offset to the OAM VP state table. */
++ /* Rx VC State */
++ int RxVc_OamCh; /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
++ int RxVc_OamToHost; /**< 0=do not pass, 1=pass. */
++ bit32 RxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx conn (must be big endian with 0 PTI). */
++ int RxVc_OamTc; /**< TC Path to transmit OAM cells for RX connection (0,1). */
++ int RxVc_VpOffset; /**< Offset to the OAM VP state table. */
++ /* Tx VP State */
++ int TxVp_OamTc; /**< TC Path to transmit OAM cells for TX VP connection (0,1). */
++ bit32 TxVp_AtmHeader; /**< ATM Header placed on firmware gen'd VP OAM cells for this Tx VP conn (must be big endian with 0 VCI). */
++ /* Rx VP State */
++ int RxVp_OamCh; /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
++ int RxVp_OamToHost; /**< 0=do not pass, 1=pass. */
++ bit32 RxVp_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx VP conn (must be big endian with 0 VCI). */
++ int RxVp_OamTc; /**< TC Path to transmit OAM cells for RX VP connection (0,1). */
++ int RxVp_OamVcList; /**< Indicates all VC channels associated with this VP channel (one-hot encoded). */
++#endif
++
++
++#ifdef _CPHAL_VDMAVT
++ bit32u RemFifoAddr; /* Mirror mode only. */
++ bit32u FifoAddr;
++ bit32 PollInt;
++ bit32 FifoSize;
++ int Ready;
++#endif
++
++ }CHANNEL_INFO;
++
++/*
++ * This structure contains each statistic value gathered by the CPHAL.
++ * Applications may access statistics data by using the @c StatsGet() routine.
++ */
++/* STATS */
++#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
++typedef struct
++ {
++ bit32u CrcErrors[16];
++ bit32u LenErrors[16];
++ bit32u DmaLenErrors[16];
++ bit32u AbortErrors[16];
++ bit32u StarvErrors[16];
++ bit32u TxMisQCnt[16][2];
++ bit32u RxMisQCnt[16];
++ bit32u RxEOQCnt[16];
++ bit32u TxEOQCnt[16][2];
++ bit32u RxPacketsServiced[16];
++ bit32u TxPacketsServiced[16][2];
++ bit32u RxMaxServiced;
++ bit32u TxMaxServiced[16][2];
++ bit32u RxTotal;
++ bit32u TxTotal;
++ } STAT_INFO;
++#endif
++
++/*
++ * VDMA Channel specific configuration information
++ */
++#ifdef _CPHAL_AAL2
++typedef struct
++ {
++ int Ch; /**< Channel Number */
++ int RemoteEndian; /**< Endianness of remote VDMA-VT device */
++ int CpsSwap; /**< When 0, octet 0 in CPS pkt located in LS byte of 16-bit word sent to rem VDMA device. When 1, in MS byte. */
++ }VdmaChInfo;
++#endif
++
++#ifndef _CPHAL
++ typedef void HAL_DEVICE;
++ typedef void HAL_PRIVATE;
++ typedef void HAL_RCB;
++ typedef void HAL_RECEIVEINFO;
++#endif
++
++/**
++ * @ingroup shared_data
++ * The HAL_FUNCTIONS struct defines the function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to xxxInitModule().
++ */
++typedef struct
++ {
++ int (*ChannelSetup) (HAL_DEVICE *HalDev, CHANNEL_INFO *Channel, OS_SETUP *OsSetup);
++ int (*ChannelTeardown) (HAL_DEVICE *HalDev, int Channel, int Mode);
++ int (*Close) (HAL_DEVICE *HalDev, int Mode);
++ int (*Control) (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
++ int (*Init) (HAL_DEVICE *HalDev);
++ int (*Open) (HAL_DEVICE *HalDev);
++ int (*PacketProcessEnd) (HAL_DEVICE *HalDev);
++ int (*Probe) (HAL_DEVICE *HalDev);
++ int (*RxReturn) (HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
++ int (*Send) (HAL_DEVICE *HalDev, FRAGLIST *FragList, int FragCount, int PacketSize, OS_SENDINFO *OsSendInfo, bit32u Mode);
++ int (*Shutdown) (HAL_DEVICE *HalDev);
++ int (*Tick) (HAL_DEVICE *HalDev);
++
++#ifdef _CPHAL_AAL5
++ int (*Kick) (HAL_DEVICE *HalDev, int Queue);
++ void (*OamFuncConfig) (HAL_DEVICE *HalDev, unsigned int OamConfig);
++ void (*OamLoopbackConfig) (HAL_DEVICE *HalDev, unsigned int OamConfig, unsigned int *LLID, unsigned int CorrelationTag);
++ volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
++ STAT_INFO* (*StatsGetOld)(HAL_DEVICE *HalDev);
++#endif
++ } HAL_FUNCTIONS;
++
++/**
++ * @ingroup shared_data
++ * The OS_FUNCTIONS struct defines the function pointers for all upper layer
++ * functions accessible to the CPHAL. The upper layer software is responsible
++ * for providing the correct OS-specific implementations for the following
++ * functions. It is populated by calling InitModule() (done by the CPHAL in
++ * xxxInitModule().
++ */
++typedef struct
++ {
++ int (*Control)(OS_DEVICE *OsDev, const char *Key, const char *Action, void *Value);
++ void (*CriticalOn)(void);
++ void (*CriticalOff)(void);
++ void (*DataCacheHitInvalidate)(void *MemPtr, int Size);
++ void (*DataCacheHitWriteback)(void *MemPtr, int Size);
++ int (*DeviceFindInfo)(int Inst, const char *DeviceName, void *DeviceInfo);
++ int (*DeviceFindParmUint)(void *DeviceInfo, const char *Parm, bit32u *Value);
++ int (*DeviceFindParmValue)(void *DeviceInfo, const char *Parm, void *Value);
++ void (*Free)(void *MemPtr);
++ void (*FreeRxBuffer)(OS_RECEIVEINFO *OsReceiveInfo, void *MemPtr);
++ void (*FreeDev)(void *MemPtr);
++ void (*FreeDmaXfer)(void *MemPtr);
++ void (*IsrRegister)(OS_DEVICE *OsDev, int (*halISR)(HAL_DEVICE*, int*), int InterruptBit);
++ void (*IsrUnRegister)(OS_DEVICE *OsDev, int InterruptBit);
++ void* (*Malloc)(bit32u size);
++ void* (*MallocDev)(bit32u Size);
++ void* (*MallocDmaXfer)(bit32u size, void *MemBase, bit32u MemRange);
++ void* (*MallocRxBuffer)(bit32u size, void *MemBase, bit32u MemRange,
++ OS_SETUP *OsSetup, HAL_RECEIVEINFO *HalReceiveInfo,
++ OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev);
++ void* (*Memset)(void *Dest, int C, bit32u N);
++ int (*Printf)(const char *Format, ...);
++ int (*Receive)(OS_DEVICE *OsDev,FRAGLIST *FragList,bit32u FragCount,
++ bit32u PacketSize,HAL_RECEIVEINFO *HalReceiveInfo, bit32u Mode);
++ int (*SendComplete)(OS_SENDINFO *OsSendInfo);
++ int (*Sprintf)(char *S, const char *Format, ...);
++ int (*Strcmpi)(const char *Str1, const char *Str2);
++ unsigned int (*Strlen)(const char *S);
++ char* (*Strstr)(const char *S1, const char *S2);
++ unsigned long (*Strtoul)(const char *Str, char **Endptr, int Base);
++ void (*TeardownComplete)(OS_DEVICE *OsDev, int Ch, int Direction);
++ } OS_FUNCTIONS;
++
++/************** MODULE SPECIFIC STUFF BELOW **************/
++
++#ifdef _CPHAL_CPMAC
++
++/*
++int halCpmacInitModule(HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc, int (*osBridgeInitModule)(OS_FUNCTIONS *), void* (*osMallocDev) (bit32u), int *Size, int inst);
++*/
++
++int halCpmacInitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ HAL_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++#ifdef _CPHAL_AAL5
++/*
++ * @ingroup shared_data
++ * The AAL5_FUNCTIONS struct defines the AAL5 function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to cphalInitModule().
++ */
++/*
++typedef struct
++ {
++ int (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
++ int (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
++ int (*Close)(HAL_DEVICE *HalDev, int Mode);
++ int (*Init)(HAL_DEVICE *HalDev);
++ int (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
++ int (*Open)(HAL_DEVICE *HalDev);
++ int (*InfoGet)(HAL_DEVICE *HalDev, int Key, void *Value);
++ int (*Probe)(HAL_DEVICE *HalDev);
++ int (*RxReturn)(HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
++ int (*Send)(HAL_DEVICE *HalDev,FRAGLIST *FragList,int FragCount,
++ int PacketSize,OS_SENDINFO *OsSendInfo,int Ch, int Queue,
++ bit32u Mode);
++ int (*StatsClear)(HAL_DEVICE *HalDev);
++ STAT_INFO* (*StatsGet)(HAL_DEVICE *HalDev);
++ int (*Status)(HAL_DEVICE *HalDev);
++ void (*Tick)(HAL_DEVICE *HalDev);
++ int (*Kick)(HAL_DEVICE *HalDev, int Queue);
++ volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
++ } AAL5_FUNCTIONS;
++*/
++
++int cpaal5InitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ HAL_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++#ifdef _CPHAL_AAL2
++/**
++ * @ingroup shared_data
++ * The AAL2_FUNCTIONS struct defines the AAL2 function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to cphalInitModule().
++ */
++typedef struct
++ {
++ int (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
++ int (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
++ int (*Close)(HAL_DEVICE *HalDev, int Mode);
++ int (*Init)(HAL_DEVICE *HalDev);
++ int (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
++ int (*Open)(HAL_DEVICE *HalDev);
++ int (*OptionsGet)(HAL_DEVICE *HalDev, char *Key, bit32u *Value);
++ int (*Probe)(HAL_DEVICE *HalDev);
++
++ int (*StatsClear)(HAL_DEVICE *HalDev);
++ STAT_INFO* (*StatsGet)(HAL_DEVICE *HalDev);
++ int (*Status)(HAL_DEVICE *HalDev);
++ void (*Tick)(HAL_DEVICE *HalDev);
++ int (*Aal2UuiMappingSetup)(HAL_DEVICE *HalDev, int VC, int UUI,
++ int VdmaCh, int UUIDiscard);
++ int (*Aal2RxMappingSetup)(HAL_DEVICE *HalDev, int VC, int CID,
++ int LC);
++ int (*Aal2TxMappingSetup)(HAL_DEVICE *HalDev, int VC, int LC, int VdmaCh);
++ int (*Aal2VdmaChSetup)(HAL_DEVICE *HalDev, bit32u RemVdmaVtAddr,
++ VdmaChInfo *VdmaCh);
++ volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
++ int (*Aal2ModeChange)(HAL_DEVICE *HalDev, int Vc, int RxCrossMode,
++ int RxMultiMode, int TxMultiMode, int SchedMode,
++ int TcCh);
++ void (*Aal2VdmaEnable)(HAL_DEVICE *HalDev, int Ch);
++ int (*Aal2VdmaDisable)(HAL_DEVICE *HalDev, int Ch);
++ } AAL2_FUNCTIONS;
++
++int cpaal2InitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ AAL2_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++#ifdef _CPHAL_VDMAVT
++/**
++ * @ingroup shared_data
++ * The VDMA_FUNCTIONS struct defines the HAL function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to InitModule().
++ *
++ * Note that this list is still under definition.
++ */
++typedef struct
++ {
++ bit32 (*Init)( HAL_DEVICE *VdmaVtDev);
++ /* bit32 (*SetupTxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
++ bit32u Addr, bit32u Size, bit32u PollInt);
++ bit32 (*SetupRxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
++ bit32u Addr, bit32u Size, bit32u PollInt); */
++ bit32 (*Tx)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*Rx)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*SetRemoteChannel)(HAL_DEVICE *VdmaVtDev, bit32u RemAddr,
++ bit32u RemDevID);
++ bit32 (*ClearRxInt)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*ClearTxInt)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*Open)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*Close)(HAL_DEVICE *VdmaVtDev);
++ int (*Control) (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
++ int (*ChannelSetup)(HAL_DEVICE *VdmaVtDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
++ int (*ChannelTeardown)(HAL_DEVICE *VdmaVtDev, int Ch, int Mode);
++ int (*Send)(HAL_DEVICE *VdmaVtDev,FRAGLIST *FragList,int FragCount,
++ int PacketSize,OS_SENDINFO *OsSendInfo,bit32u Mode);
++ } VDMA_FUNCTIONS;
++
++int VdmaInitModule(HAL_DEVICE **VdmaVt,
++ OS_DEVICE *OsDev,
++ VDMA_FUNCTIONS **VdmaVtFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++/*
++extern int cphalInitModule(MODULE_TYPE ModuleType, HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc,
++ int (*osInitModule)(OS_FUNCTIONS *), void* (*osMallocDev)(bit32u),
++ int *Size, int Inst);
++*/
++
++
++#ifdef _CPHAL_AAL5
++extern const char hcSarFrequency[];
++#endif
++
++#ifdef _CPHAL_CPMAC
++/* following will be common, once 'utl' added */
++extern const char hcClear[];
++extern const char hcGet[];
++extern const char hcSet[];
++extern const char hcTick[];
++
++extern const char hcCpuFrequency[];
++extern const char hcCpmacFrequency[];
++extern const char hcMdioBusFrequency[];
++extern const char hcMdioClockFrequency[];
++extern const char hcCpmacBase[];
++extern const char hcPhyNum[];
++extern const char hcSize[];
++extern const char hcCpmacSize[];
++extern const char hcPhyAccess[];
++extern const char hcMdixMask[];
++extern const char hcMdioMdixSwitch[];
++#endif
++
++#endif /* end of _INC_ */
+diff -urN linux.old/drivers/net/avalanche_cpmac/dox_cpmac.h linux.dev/drivers/net/avalanche_cpmac/dox_cpmac.h
+--- linux.old/drivers/net/avalanche_cpmac/dox_cpmac.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/dox_cpmac.h 2005-07-12 02:48:42.050593000 +0200
+@@ -0,0 +1,842 @@
++/*****************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002,2003 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE:
++ *
++ * DESCRIPTION:
++ * This file contains documentation for the CPMAC
++ *
++ * HISTORY:
++ * @author Michael Hanrahan/Greg Guyotte
++ * @version 1.00
++ * @date 03-Dec-2002
++ *****************************************************************************/
++#ifndef _DOX_CPMAC_H
++#define _DOX_CPMAC_H
++/**
++@page CPMAC_Implementation_Details Version
++
++@copydoc CPMAC_Version
++*/
++
++/**
++@page cpmac_intro Introduction
++
++The CPMAC implementation will support 8 channels for transmit and 8 channel for
++receive. Each of the 8 transmit channels has 1 queue associated with it. It is
++recommended that only 1 channel is used for @c Receive() per processor.
++*/
++
++/**
++@page cpmac_details API Implementation Details
++@par osReceive
++@p Mode parameter
++- The Upper 16 bits of Mode match Word 3 of the Rx Buffer Descriptor
++
++@par halSend
++@p Mode parameter
++- Bits 0-7 contain the Channel Number
++- Bits 8-25 are reserved
++- Bit 26 - if 0, the CRC will be calculated, if 1 the CRC will be Passed
++- Bits 27-31 : reserved
++@section cpmac_keys Control Keys
++
++@par StateChange
++CPHAL calls the OS when a state change is detected.
++OS should check the CPMAC Status. See the Control Key 'Status' for more details.
++
++@par Status
++OS calls the CPHAL to obtain Status information. The Returned status is as follows
++
++@par MaxFrags
++The OS may "Set" or "Get" this value. This defines the maximum
++number of fragments that can be received by the CPMAC Rx port. The default
++value for CPMAC is 2. This provides enough space to receive a maximum
++length packet (1,518 bytes) with the default buffer size of 1518 and any
++amount of RxBufferOffset. If the buffer size is configured to be smaller,
++the OS *MUST* modify this parameter according to the following formula:
++((System Max packet length)/(RxBufSize)) + 1. (The extra 1 fragment is to
++allow for RxBufferOffset)
++
++@code
++// Following defined in "cpswhal_cpmac.h"
++// CPMAC CPHAL STATUS
++#define CPMAC_STATUS_LINK (1 << 0)
++#define CPMAC_STATUS_LINK_DUPLEX (1 << 1) // 0 - HD, 1 - FD
++#define CPMAC_STATUS_LINK_SPEED (1 << 2) // 0 - 10, 1 - 100
++
++// ADAPTER CHECK Codes
++#define CPMAC_STATUS_ADAPTER_CHECK (1 << 7)
++#define CPMAC_STATUS_HOST_ERR_DIRECTION (1 << 8) // 0 - Tx, 1 - Rx
++#define CPMAC_STATUS_HOST_ERR_CODE (0xF << 9) See CPMAC Guide
++#define CPMAC_STATUS_HOST_ERR_CH (0x7 << 13) See CPMAC Guide
++@endcode
++
++@code
++void osStateChange(OS_DEVICE *OsDev)
++ {
++ int status;
++ OsDev->HalFunc->Control(OsDev->HalDev, "Status", hcGet, &status);
++ if(status & CPMAC_STATUS_ADAPTER_CHECK)
++ {
++ printf("[osStateChange[%d]] HAL notified OS of AdapterCheck (Link Status 0x%08X)\n", OsDev->port, status);
++ adaptercheck(OsDev->port);
++ }
++ else
++ {
++ printf("[osStateChange[%d]] HAL notified OS of State Change (Link Status %s)\n", OsDev->port, (status & CPMAC_STATUS_LINK) ? "Up" : "Down");
++ if(status & CPMAC_STATUS_LINK)
++ {
++ printf("Speed %s, Duplex %s\n",
++ status & CPMAC_STATUS_LINK_SPEED ? "100" : "10",
++ status & CPMAC_STATUS_LINK_DUPLEX ? "FD" : "HD");
++ }
++ }
++@endcode
++
++@par Tick
++ The CPHAL calls the OS to set the interval for calling halTick()<BR>
++ Note: Predefined value hcTick now recommended for use.
++@code
++*** Example Code ***
++
++*** CPHAL code ***
++int Ticks;
++HalDev->OsFunc->Control(HalDev->OsDev, hcTick, hcSet, &Ticks);
++
++*** OS code ***
++ ..
++ if(osStrcmpi(pszKey, hcTick) == 0)
++ {
++ if(osStrcmpi(pszAction, hcSet) == 0)
++ {
++ // Enable the Tick Interval
++ if(*(unsigned int *) ParmValue)
++ printf("osTickSet: Interval = %d ticks\n", Interval);
++ }
++ else
++ if(osStrcmpi(pszAction, hcClear) == 0)
++ {
++ // Request disabling of the Tick Timer, ParmValue is ignored
++ }
++ }
++@endcode
++
++@par The following information can be obtained by the OS via 'Get'
++
++- StatsDump : OS supplies pointer to an 36 element unsigned int array
++CPHAL will populate the array with the current Statistics values.<BR>
++Note: all hcXXXX values are predefined and should be used by the OS.
++
++- hcPhyNum : Returns the PHY number.
++- hcCpmacBase : Returns the base-address of the CPMAC device
++- hcCpmacSize : Returns size of the CPMAC memory map
++
++
++@par Phy Register Communication
++
++halControl() is used to read and write the Phy Registers via the key hcPhyAccess
++
++Both reading and writing the Phy registers involve setting the Value parameter of halControl()
++<BR>
++Value is a 32-bit value with bits partioned as follows
++<BR>
++
++ 0 - 4 Phy Number <BR>
++ 5 - 9 Phy Register <BR>
++ 10 - 15 reserved <BR>
++ 16 - 31 Data (write only)
++<BR>
++
++
++<B>Reading the Phy register</B>
++
++@code
++ bit32u Value;
++ bit32u RegAddr;
++ bit32u PhyNum;
++ bit32u PhyRegisterData;
++
++ // Read Phy 31, register 20
++
++ PhyNum = 31;
++ RegAddr = 20;
++
++ Value = (RegAddr << 5);
++ Value |= (PhyNum & 0x1F);
++
++ rc = HalFunc->Control(HalDev, hcPhyAccess, hcGet, (bit32u *) &Value)
++ If(rc == 0)
++ {
++ // Value is overwriten with the value in Register 20 of Phy number 31.
++ PhyRegisterData = Value;
++ }
++@endcode
++
++<B>Writing the Phy register</B>
++@code
++ bit32u Value;
++ bit32u RegAddr;
++ bit32u PhyNum;
++ bit32u PhyRegisterData;
++
++ // Reset Phy 23
++
++ PhyNum = 23;
++ RegAddr = 0;
++ PhyRegisterData = 0x8000; // Reset bit set
++
++ Value = (RegAddr << 5);
++ Value |= (PhyNum & 0x1F);
++ Value |= (PhyRegisterData << 16);
++
++ rc = HalFunc->Control(HalDev, hcPhyAccess, hcSet, (bit32u *) &Value)
++
++ // Check is reset if done
++
++ PhyNum = 23;
++ RegAddr = 0;
++
++ Value = (RegAddr << 5);
++ Value |= (PhyNum & 0x1F);
++
++ rc = HalFunc->Control(HalDev, hcPhyAccess, hcGet, (bit32u *) &Value)
++
++ If(rc == 0)
++ {
++ // Value is overwriten with the value in Register 0 of Phy number 23.
++ PhyRegisterData = Value;
++ if((PhyRegisterData & 0x8000) == 0)
++ ResetIsComplete;
++ }
++
++@endcode
++<B>
++*** Example Showing turning values off/on ***
++<BR>
++</B>
++
++@code
++
++int On=1;
++int Off=0;
++ # Turn On loopback
++ OsDev->HalFunc->Control(OsDev->HalDev, "CTRL_LOOPBACK", hcSet, (int*) &On);
++
++ # Turn off RX Flow
++ OsDev->HalFunc->Control(OsDev->HalDev, "RX_FLOW_EN", hcSet, (int*) &Off);
++@endcode
++
++@par CPMAC Configurable Parameters
++
++- RX_PASS_CRC : See MBP_Enable description
++- RX_QOS_EN : See MBP_Enable description
++- RX_NO_CHAIN : See MBP_Enable description
++- RX_CMF_EN : See MBP_Enable description
++- RX_CSF_EN : See MBP_Enable description
++- RX_CEF_EN : See MBP_Enable description
++- RX_CAF_EN : See MBP_Enable description
++- RX_PROM_CH : See MBP_Enable description
++- RX_BROAD_EN : See MBP_Enable description
++- RX_BROAD_CH : See MBP_Enable description
++- RX_MULT_EN : See MBP_Enable description
++- RX_MULT_CH : See MBP_Enable description
++
++- TX_PTYPE : See MacControl description
++- TX_PACE : See MacControl description
++- TX_FLOW_EN : See MacControl description
++- RX_FLOW_EN : See MacControl description
++- CTRL_LOOPBACK : See MacControl description
++
++- RX_MAXLEN : See CPMAC Guide
++- RX_FILTERLOWTHRESH : See CPMAC Guide
++- RX0_FLOWTHRESH : See CPMAC Guide
++- RX_UNICAST_SET : See CPMAC Guide
++- RX_UNICAST_CLEAR : See CPMAC Guide
++
++@par Multicast Support
++- RX_MULTI_ALL : When used with hcSet, sets all the Hash Bits. When used
++with hcClear clears all the Hash Bits.
++- RX_MULTI_SINGLE : When used with hcSet, adds the Hashed Mac Address. When used
++with hcClear deletes the Hashed Mac Address.
++Note: Support will be added to keep track of Single additions and deletions.
++
++@code
++*** Example Code ***
++
++*** OS code ***
++ bit8u MacAddress[6];
++ MacAddress[0] = 0x80;
++ MacAddress[1] = 0x12;
++ MacAddress[2] = 0x34;
++ MacAddress[3] = 0x56;
++ MacAddress[4] = 0x78;
++ MacAddress[5] = 0x78;
++ OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_SINGLE", hcSet, (bit8u*) &MacAddress);
++ OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_SINGLE", hcClear, (bit8u*) &MacAddress);
++ OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_ALL", hcSet, NULL);
++ OsDev->HalFunc->Control(OsDev->HalDev, "RX_MULTI_ALL", hcClear, NULL);
++@endcode
++@par MdioConnect Fields
++<BR>
++- "MdioConnect" : The OS can set the Phy connection using this key. The default connection is Auto-Negotiation ON, All modes possible.
++
++
++- _CPMDIO_HD <----- Allow Half Duplex, default is 1 (On)
++- _CPMDIO_FD <----- Allow Full Duplex, default is 1 (On)
++- _CPMDIO_10 <----- Allow 10 Mbs, default is 1 (On)
++- _CPMDIO_100 <----- Allow 100 Mbs, default is 1 (On)
++- _CPMDIO_NEG_OFF <----- Turn off Auto Negotiation, default is 0 (Auto Neg is on)
++- _CPMDIO_NOPHY <----- Set for use with Marvel-type switch, default is 0 (Phy present)
++- _CPMDIO_AUTOMDIX <---- Enables Auto Mdix (in conjunction with MdixMask), default is 1 (On)
++
++Note: When _CPMDIO_NOPHY is set, CPMAC will report being linked at 100/FD. Reported PhyNum will be 0xFFFFFFFF
++
++@par Setting CPMAC for use with a Marvel-type Switch
++@code
++ bit32u MdioConnect;
++
++ MdioConnect = _CPMDIO_NOPHY;
++ OsDev->HalFunc->Control(OsDev->HalDev, "MdioConnect", hcSet, (bit32u*) &MdioConnect);
++@endcode
++
++@par OS Support for MDIO
++@p The OS will need to supply the following values which the CPHAL will request via halControl()
++<BR>
++- MdioBusFrequency : The frequency of the BUS that MDIO is on (requested via hcMdioBusFrequency)
++<BR>
++- MdioClockFrequency : The desired Clock Frequency that MDIO qill operate at (requested via hcMdioClockFrequency)
++*/
++
++/**
++@page cpmac_conf DeviceFindxxx() Parameters
++
++These are some of the parameters that the CPMAC will request via the DeviceFindxxx() functions -
++<BR>
++- "Mlink" : bit mask indicating what link status method Phy is using. Default is MDIO state machine (0x0)
++- "PhyMask" : bit mask indicating PhyNums used by this CPMAC (e.g 0x8000000, PhyNum is 31)
++- "MdixMask" : bit mask indicating which Phys support AutoMdix. Default is 0x0 (None)
++<BR>
++@par Example cpmac definition from the options.conf for the Sangam VDB
++<BR>
++- cpmac( id=eth0, base=0xA8610000, size=0x800, reset_bit=17, int_line=19, PhyMask=0x80000000, MLink=0, MdixMask=0 )
++*/
++
++/**
++@page auto_mdix Auto Mdix Support
++
++Auto Mdix selection is controlled by two elements in the CPMAC. First the OS can turn Auto Midx On or Off by the use of the
++MdioConnect field, _CPMDIO_AUTOMDIX. This is defaulted ON. For actual Auto Mdix operation the Phy must also be Auto Mdix capable.
++This is specified by the DeviceFindxxx() field, "MdixMask" (supplied as the variable hcMdixMask).
++If both these fields are set then the CPMDIO state machine will be enabled for Auto Mdix checking.
++If a switch to MDI or MDIX mode is needed, the CPMAC will signal this to the OS via Control() using
++the hcMdioMdixSwitch key.
++
++@par OS example for responding to a Mdix Switch Request
++<BR>
++@code
++if(osStrcmpi(pszKey, hcMdioMdixSwitch) == 0) // See if key is Mdix Switch Request
++ {
++ if(osStrcmpi(pszAction, hcSet) == 0) // Only respond to Set requests
++ {
++
++ bit32u Mdix;
++
++ Mdix = *(bit32u *) ParmValue; // Extract requested Mode
++ // 0 : MDI
++ // 1 : MDIX
++ if(Mdix)
++ osSetPhyIntoMdixMode(); // Device specific logic
++ else
++ osSetPhyIntoMdiMode(); // Device specific logic
++ rc = 0; // Set return code as Successfull
++ }
++@endcode
++*/
++
++/**
++@page cpmac_stats CPMAC Specific Statistics
++
++Statistics level '0' contains all CPMAC specific statistics.
++
++
++*/
++
++/**
++@page Example_Driver_Code
++
++@section example_intro Introduction
++This section provides an in-depth code example for driver implementations. The code
++below illustrates the use of the CPMAC HAL, but is equally applicable to any CPHAL
++implementation. Note: the CPHAl constants hcGet, hcSet etc., are currently available for use with teh CPMAC module.
++Other modules should continue to use pszGET, etc. until these are made generally available.
++
++@par Pull Model Example
++
++@code
++
++#define _CPHAL_CPMAC
++
++typedef struct _os_device_s OS_DEVICE;
++typedef struct _os_receive_s OS_RECEIVEINFO;
++typedef struct _os_send_s OS_SENDINFO;
++typedef struct _os_setup_s OS_SETUP;
++
++#include "cpswhal_cpmac.h"
++
++#define dbgPrintf printf
++
++typedef struct _os_device_s
++{
++ HAL_DEVICE *HalDev;
++ HAL_FUNCTIONS *HalFunc;
++ OS_FUNCTIONS *OsFunc;
++ OS_SETUP *OsSetup;
++ bit32u Interrupt;
++ int (*halIsr)(HAL_DEVICE *HalDev, int*);
++ int ModulePort;
++ int Protocol;
++ int LinkStatus; // 0-> down, otherwise up
++}os_device_s;
++
++typedef struct _os_receive_s
++{
++ HAL_RECEIVEINFO *HalReceiveInfo;
++ char *ReceiveBuffer;
++ OS_DEVICE *OsDev;
++}os_receive_s;
++
++typedef struct _os_send_s
++{
++ OS_DEVICE *OsDev;
++}os_send_s;
++
++typedef struct _os_setup_s
++{
++ OS_DEVICE *OsDev;
++}os_setup_s;
++
++
++
++void FlowForCphal(OS_DEVICE *OsDev)
++{
++ CHANNEL_INFO ChannelInfo;
++ int nChannels = 200;
++ int halFuncSize;
++ int rc;
++
++ // Populate OsFunc structure
++ rc = osInitModule(OsDev);
++
++ if(rc)
++ {
++ sprintf(bufTmp, "%s: return code from osInitModule:'0x%08X'", __FUNCTION__, rc);
++ errorout(bufTmp);
++ }
++
++
++ // OS-Cphal handshake
++ rc = halCpmacInitModule(&OsDev->HalDev, OsDev, &OsDev->HalFunc, OsDev->OsFunc,
++ sizeof(OS_FUNCTIONS), &halFuncSize, OsDev->ModulePort);
++
++ if(rc)
++ {
++ sprintf(bufTmp, "%s: return code from halCpmacInitModule:'0x%08X'", __FUNCTION__, rc);
++ errorout(bufTmp);
++ }
++
++ // See if hardware module exists
++ rc = OsDev->HalFunc->Probe(OsDev->HalDev);
++
++ if(rc)
++ {
++ sprintf(bufTmp, "%s: return code from Probe:'0x%08X'", __FUNCTION__, rc);
++ errorout(bufTmp);
++ }
++
++ // Initialize hardware module
++ rc = OsDev->HalFunc->Init(OsDev->HalDev);
++
++ if(rc)
++ {
++ sprintf(bufTmp, "%s: return code from Init:'0x%08X'", __FUNCTION__, rc);
++ errorout(bufTmp);
++ }
++
++ // Setup Channel Information (Tranmsit, channel 0)
++ ChannelInfo.Channel = 0;
++ ChannelInfo.Direction = DIRECTION_TX;
++ ChannelInfo.TxNumBuffers = nChannels;
++ ChannelInfo.TxNumQueues = 1;
++ ChannelInfo.TxServiceMax = nChannels/3;
++
++ rc = OsDev->HalFunc->ChannelSetup(OsDev->HalDev, &ChannelInfo, OsDev->OsSetup);
++
++ // Setup Channel Information (Receive, channel 0)
++ ChannelInfo.Channel = 0;
++ ChannelInfo.Direction = DIRECTION_RX;
++ ChannelInfo.RxBufSize = 1518;
++ ChannelInfo.RxBufferOffset = 0;
++ ChannelInfo.RxNumBuffers = 2*nChannels;
++ ChannelInfo.RxServiceMax = nChannels/3;
++
++ rc = OsDev->HalFunc->ChannelSetup(OsDev->HalDev, &ChannelInfo, OsDev->OsSetup);
++
++ // Open the hardware module
++ rc = OsDev->HalFunc->Open(OsDev->HalDev);
++
++ // Module now ready to Send/Receive data
++}
++
++
++int osInitModule(OS_FUNCTIONS **pOsFunc)
++ {
++ OS_FUNCTIONS *OsFunc;
++
++ OsFunc = (OS_FUNCTIONS *) malloc(sizeof(OS_FUNCTIONS));
++ if (!OsFunc)
++ return (-1);
++
++ *pOsFunc = OsFunc;
++
++ OsFunc->CriticalOff = osCriticalOff;
++ OsFunc->CriticalOn = osCriticalOn;
++ OsFunc->DataCacheHitInvalidate = osDataCacheHitInvalidate;
++ OsFunc->DataCacheHitWriteback = osDataCacheHitWriteback;
++ OsFunc->DeviceFindInfo = osDeviceFindInfo;
++ OsFunc->DeviceFindParmUint = osDeviceFindParmUint;
++ OsFunc->DeviceFindParmValue = osDeviceFindParmValue;
++ OsFunc->Free = osFree;
++ OsFunc->FreeDev = osFreeDev;
++ OsFunc->FreeDmaXfer = osFreeDmaXfer;
++ OsFunc->FreeRxBuffer = osFreeRxBuffer;
++ OsFunc->IsrRegister = osIsrRegister;
++ OsFunc->IsrUnRegister = osIsrUnRegister;
++ OsFunc->Malloc = osMalloc;
++ OsFunc->MallocDev = osMallocDev;
++ OsFunc->MallocDmaXfer = osMallocDmaXfer;
++ OsFunc->MallocRxBuffer = osMallocRxBuffer;
++
++
++ OsFunc->Memset = memset;
++ OsFunc->Printf = printf;
++ OsFunc->Sprintf = sprintf;
++ OsFunc->Strcmpi = osStrcmpi;
++ OsFunc->Strlen = strlen;
++ OsFunc->Strstr = strstr;
++ OsFunc->Strtoul = strtoul;
++
++ OsFunc->Control = osControl;
++ OsFunc->Receive = osReceive;
++ OsFunc->SendComplete = osSendComplete;
++ OsFunc->TeardownComplete = osTearDownComplete;
++
++ return(0);
++ }
++
++
++int osReceive(OS_DEVICE *OsDev,FRAGLIST *Fraglist,bit32u FragCount,bit32u PacketSize,HAL_RECEIVEINFO *halInfo, bit32u mode)
++ {
++ OS_RECEIVEINFO *skb = (OS_RECEIVEINFO *)Fraglist[0].OsInfo;
++ dcache_i((char *)Fraglist->data, Fraglist->len);
++ OsDev->HalFunc->RxReturn(halInfo,0);
++ return(0);
++ }
++
++int osSendComplete(OS_SENDINFO *skb)
++ {
++ return(0);
++ }
++
++
++static void *osMallocRxBuffer(bit32u Size,void *MemBase, bit32u MemRange,
++ OS_SETUP *OsSetup, HAL_RECEIVEINFO *HalReceiveInfo,
++ OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev )
++ {
++ void *HalBuffer;
++ OS_RECEIVEINFO *OsPriv;
++
++ HalBuffer=malloc(Size);
++ if (!HalBuffer)
++ {
++ return(0);
++ }
++
++ // Malloc the OS block
++ *OsReceiveInfo = malloc(sizeof(OS_RECEIVEINFO));
++ if (!*OsReceiveInfo)
++ {
++ free(HalBuffer);
++ return(0);
++ }
++
++ // Initialize the new buffer descriptor
++ OsPriv = *OsReceiveInfo;
++ OsPriv->OsDev = OsDev;
++ OsPriv->ReceiveBuffer = HalBuffer;
++ OsPriv->HalReceiveInfo = HalReceiveInfo;
++
++ return(HalBuffer);
++ }
++
++
++void SendBuffer(OS_DEVICE *OsDev, char *Buffer, int Size)
++{
++ FRAGLIST Fraglist;
++ bit32u FragCount;
++
++ tcb_pending++;
++ Fraglist.len = Size;
++ Fraglist.data = (unsigned *) Buffer;
++ FragCount = 1;
++ mode = 0; // Channel 0
++
++ dcache_wb(Fraglist.data, Fraglist.len);
++ OsDev->HalFunc->Send(OsDev->HalDev, &Fraglist, FragCount, Size, (OS_SENDINFO *) Buffer, mode);
++}
++
++
++void osStateChange(OS_DEVICE *OsDev)
++ {
++ int status;
++ int LinkStatus;
++ OsDev->HalFunc->Control(OsDev->HalDev, "Status", hcGet, &status);
++ if(status & CPMAC_STATUS_ADAPTER_CHECK)
++ {
++ // Adapter Check, take appropiate action
++ }
++ else
++ {
++ LinkStatus = status & CPMAC_STATUS_LINK;
++ if(LinkStatus != OsDev->LinkStatus)
++ {
++ dbgPrintf("\n%s:Link %s for inst %d Speed %s, Duplex %s\n",
++ __FUNCTION__,
++ LinkStatus ? "up" : "down",
++ OsDev->ModulePort,
++ status & CPMAC_STATUS_LINK_SPEED ? "100" : "10",
++ status & CPMAC_STATUS_LINK_DUPLEX ? "FD" : "HD");
++ OsDev->LinkStatus = LinkStatus;
++ }
++ }
++ }
++
++
++int osControl(OS_DEVICE *OsDev, const char *pszKey, const char* pszAction, void *ParmValue)
++ {
++ int rc=-1;
++
++ if (osStrcmpi(pszKey, hcCpuFrequency) == 0)
++ {
++ if(osStrcmpi(pszAction, hcGet) == 0)
++ {
++ *(bit32u*) ParmValue = cpufreq;
++ rc = 0;
++ }
++ }
++ if (osStrcmpi(pszKey, hcMdioBusFrequency) == 0)
++ {
++ if(osStrcmpi(pszAction, hcGet) == 0)
++ {
++ *(bit32u *)ParmValue = MdioBusFrequency;
++ rc = 0;
++ }
++ }
++if (osStrcmpi(pszKey, hcMdioClockFrequency) == 0)
++ {
++ if(osStrcmpi(pszAction, hcGet) == 0)
++ {
++ *(bit32u *)ParmValue = MdioClockFrequency;
++ rc = 0;
++ }
++ }
++
++ if (osStrcmpi(pszKey, hcTick) == 0)
++ {
++ if(osStrcmpi(pszAction, hcSet) == 0)
++ {
++ osTickSetInterval(OsDev, *(unsigned int *) ParmValue);
++ rc = 0;
++ }
++ else
++ if(osStrcmpi(pszAction, hcClear) == 0)
++ {
++ osTickDisable(OsDev);
++ rc = 0;
++ }
++ }
++
++ if (osStrcmpi(pszKey, "SioFlush") == 0)
++ {
++ MySioFlush();
++ rc = 0;
++ }
++
++ if (osStrcmpi(pszKey, "StateChange") == 0)
++ {
++ osStateChange(OsDev);
++ rc = 0;
++ }
++
++ if (osStrcmpi(pszKey, "Sleep") == 0)
++ {
++ osSleep(*(int *)ParmValue);
++ rc = 0;
++ }
++ return(rc);
++ }
++
++@endcode
++
++
++@par Push Model Example (Currently Eswitch ONLY)
++
++@code
++
++typedef struct _os_device_s OS_DEVICE;
++typedef struct _os_receive_s OS_RECEIVEINFO;
++typedef struct _os_send_s OS_SENDINFO;
++typedef struct _os_setup_s OS_SETUP;
++
++#include "cpswhal.h" //Get glogal HAL stuff
++#include "cpswhaleswitch.h" //Get device specific hal stuff
++
++
++typedef struct _os_device_s
++{
++ HAL_DEVICE *HalDev;
++ HAL_FUNCTIONS *HalFunc;
++ OS_FUNCTIONS *OsFunc;
++ OS_SETUP *OsSetup;
++ bit32u Interrupt;
++ int (*halIsr)(HAL_DEVICE *HalDev, int*);
++ int ModulePort;
++ int Protocol;
++ int LinkStatus; // 0-> down, otherwise up
++}os_device_s;
++
++typedef struct _os_receive_s
++{
++ HAL_RECEIVEINFO *HalReceiveInfo;
++ char *ReceiveBuffer;
++ OS_DEVICE *OsDev;
++}os_receive_s;
++
++typedef struct _os_send_s
++{
++ OS_DEVICE *OsDev;
++}os_send_s;
++
++typedef struct _os_setup_s
++{
++ OS_DEVICE *OsDev;
++}os_setup_s;
++
++
++
++void FlowForCphal(OS_DEVICE *OsDev)
++{
++CHANNEL_INFO ChannelInfo;
++ int nChannels = 200;
++ int halFuncSize;
++ int rc;
++
++ // Populate OsFunc structure
++ rc = osInitModule(OsDev);
++
++ if(rc)
++ {
++ sprintf(bufTmp, "%s: return code from osInitModule:'0x%08X'", __FUNCTION__, rc);
++ errorout(bufTmp);
++ }
++
++
++ // OS-Cphal handshake
++ rc = cpswHalEswitchInitModule(&OsDev->HalDev, OsDev, &OsDev->HalFunc, OsDev->OsFunc,
++ sizeof(OS_FUNCTIONS), &halFuncSize, OsDev->ModulePort);
++
++ if(rc)
++ {
++ sprintf(bufTmp, "%s: return code from cpswHalEswitchInitModule:'0x%08X'", __FUNCTION__, rc);
++ errorout(bufTmp);
++ }
++
++
++ ChannelInfo.Channel = 7;
++ ChannelInfo.Direction = DIRECTION_RX;
++ ChanInfo.Receive = osReceiveSS; // Specify function to receive data for this channel
++
++ rc = OsDev->HalFunc->ChannelSetup(OsDev->HalDev, &ChannelInfo, OsDev->OsSetup);
++
++ MyConfig.debug=0;
++ MyConfig.CpuFrequency = CpuFreq;
++ MyConfig.EswitchFrequency = EswitchFreq;
++ MyConfig.ResetBase = 0xa8611600;
++ MyConfig.MacAddress = MacAddr;
++
++ MyConfig.EswitchResetBit= 27;
++ MyConfig.Cpmac0ResetBit = 17;
++ MyConfig.Cpmac1ResetBit = 21;
++ MyConfig.MdioResetBit = 22;
++ MyConfig.Phy0ResetBit = 26;
++ MyConfig.Phy1ResetBit = 28;
++ MyConfig.HdmaResetBit = 13;
++ MyConfig.Cpmac0IntBit = 19;
++ MyConfig.Cpmac1IntBit = 33;
++ MyConfig.EswitchIntBit = 27;
++ MyConfig.EswitchBase = 0xa8640000;
++ MyConfig.EswitchBufferSize = 64;
++ MyConfig.EswitchHostBufCount = 0;
++ MyConfig.EswitchDefaultCamSize = 64;
++ MyConfig.EswitchOverFlowCount = 200;
++ MyConfig.EswitchOverFlowSize = 256;
++
++
++
++
++ rc=EswitchConfig(HalDev,HalFunc,&MyConfig);
++
++
++ // Open the hardware module
++ rc = OsDev->HalFunc->Open(OsDev->HalDev);
++
++ // Module now ready to Send/Receive data
++}
++
++
++int EswitchConfig(HAL_DEVICE *HalDev, HAL_FUNCTIONS *HalFunc, ESWITCH_CONFIG *Config)
++{
++ bit32u sts;
++ sts = 0;
++
++ sts |= cpswhalPushBin(hcdebug, Config->debug);
++ sts |= cpswhalPushBin(hcCpuFrequency , Config->CpuFrequency );
++ sts |= cpswhalPushBin(hcEswitchFrequency , Config->EswitchFrequency );
++ sts |= cpswhalPushBin(hcResetBase , Config->ResetBase );
++ sts |= cpswhalPushBin(hcMacAddress , Config->MacAddress );
++ sts |= cpswhalPushBin(hcEswitchResetBit, Config->EswitchResetBit);
++ sts |= cpswhalPushBin(hcCpmac0ResetBit , Config->Cpmac0ResetBit );
++ sts |= cpswhalPushBin(hcCpmac1ResetBit , Config->Cpmac1ResetBit );
++ sts |= cpswhalPushBin(hcMdioResetBit , Config->MdioResetBit );
++ sts |= cpswhalPushBin(hcPhy0ResetBit , Config->Phy0ResetBit );
++ sts |= cpswhalPushBin(hcPhy1ResetBit , Config->Phy1ResetBit );
++ sts |= cpswhalPushBin(hcHdmaResetBit , Config->HdmaResetBit );
++ sts |= cpswhalPushBin(hcCpmac0IntBit , Config->Cpmac0IntBit );
++ sts |= cpswhalPushBin(hcCpmac1IntBit , Config->Cpmac1IntBit );
++ sts |= cpswhalPushBin(hcEswitchIntBit , Config->EswitchIntBit );
++ sts |= cpswhalPushBin(hcEswitchBase , Config->EswitchBase );
++ sts |= cpswhalPushBin(hcEswitchBufferSize , Config->EswitchBufferSize );
++ sts |= cpswhalPushBin(hcEswitchHostBufCount , Config->EswitchHostBufCount );
++ sts |= cpswhalPushBin(hcEswitchDefaultCamSize , Config->EswitchDefaultCamSize );
++ sts |= cpswhalPushBin(hcEswitchOverFlowCount , Config->EswitchOverFlowCount );
++ sts |= cpswhalPushBin(hcEswitchOverFlowSize , Config->EswitchOverFlowSize );
++ return(sts);
++}
++
++
++
++@endcode
++*/
++
++#endif
+diff -urN linux.old/drivers/net/avalanche_cpmac/ec_errors_cpmac.h linux.dev/drivers/net/avalanche_cpmac/ec_errors_cpmac.h
+--- linux.old/drivers/net/avalanche_cpmac/ec_errors_cpmac.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/ec_errors_cpmac.h 2005-07-12 02:48:42.051592000 +0200
+@@ -0,0 +1,118 @@
++/***************************************************************************
++ Copyright(c) 2001, Texas Instruments Incorporated. All Rights Reserved.
++
++ FILE: ec_errors.h
++
++ DESCRIPTION:
++ This file contains definitions and function declarations for
++ error code support.
++
++ HISTORY:
++ 14Dec00 MJH Added masking to EC_CLASS etc macros
++ 17Sep02 GSG Added HAL support (new class&devices)
++ 03Oct02 GSG Removed C++ style comments
++***************************************************************************/
++#ifndef _INC_EC_ERRORS
++#define _INC_EC_ERRORS
++
++/*
++ 31 - CRITICAL
++ 30-28 - CLASS (ie. DIAG, KERNEL, FLASH, etc)
++ 27-24 - INSTANCE (ie. 1, 2, 3, etc )
++ 23-16 - DEVICE (ie. EMAC, IIC, etc)
++ 15-08 - FUNCTION (ie. RX, TX, INIT, etc)
++ 07-00 - ERROR CODE (ie. NO_BASE, FILE_NOT_FOUND, etc )
++*/
++
++/*---------------------------------------------------------------------------
++ Useful defines for accessing fields within error code
++---------------------------------------------------------------------------*/
++#define CRITICAL_SHIFT 31
++#define CLASS_SHIFT 28
++#define INST_SHIFT 24
++#define DEVICE_SHIFT 16
++#define FUNCTION_SHIFT 8
++#define ERROR_CODE_SHIFT 0
++
++#define CRITICAL_MASK 1
++#define CLASS_MASK 0x07
++#define DEVICE_MASK 0xFF
++#define INST_MASK 0x0F
++#define FUNCTION_MASK 0xFF
++#define ERROR_CODE_MASK 0xFF
++
++#define EC_CLASS(val) ((val&CLASS_MASK) << CLASS_SHIFT)
++#define EC_DEVICE(val) ((val&DEVICE_MASK) << DEVICE_SHIFT)
++#define EC_INST(val) ((val&INST_MASK) << INST_SHIFT)
++#define EC_FUNC(val) ((val&FUNCTION_MASK) << FUNCTION_SHIFT)
++#define EC_ERR(val) ((val&ERROR_CODE_MASK) << ERROR_CODE_SHIFT)
++
++/*---------------------------------------------------------------------------
++ Operation classes
++---------------------------------------------------------------------------*/
++#define EC_HAL EC_CLASS(0)
++#define EC_DIAG EC_CLASS(8)
++
++/*---------------------------------------------------------------------------
++ Device types
++---------------------------------------------------------------------------*/
++#define EC_DEV_EMAC EC_DEVICE(1)
++#define EC_DEV_IIC EC_DEVICE(2)
++#define EC_DEV_RESET EC_DEVICE(3)
++#define EC_DEV_ATMSAR EC_DEVICE(4)
++#define EC_DEV_MEM EC_DEVICE(5)
++#define EC_DEV_DES EC_DEVICE(6)
++#define EC_DEV_DMA EC_DEVICE(7)
++#define EC_DEV_DSP EC_DEVICE(8)
++#define EC_DEV_TMR EC_DEVICE(9)
++#define EC_DEV_WDT EC_DEVICE(10)
++#define EC_DEV_DCL EC_DEVICE(11)
++#define EC_DEV_BBIF EC_DEVICE(12)
++#define EC_DEV_PCI EC_DEVICE(13)
++#define EC_DEV_XBUS EC_DEVICE(14)
++#define EC_DEV_DSLIF EC_DEVICE(15)
++#define EC_DEV_USB EC_DEVICE(16)
++#define EC_DEV_CLKC EC_DEVICE(17)
++#define EC_DEV_RAPTOR EC_DEVICE(18)
++#define EC_DEV_DSPC EC_DEVICE(19)
++#define EC_DEV_INTC EC_DEVICE(20)
++#define EC_DEV_GPIO EC_DEVICE(21)
++#define EC_DEV_BIST EC_DEVICE(22)
++#define EC_DEV_HDLC EC_DEVICE(23)
++#define EC_DEV_UART EC_DEVICE(24)
++#define EC_DEV_VOIC EC_DEVICE(25)
++/* 9.17.02 (new HAL modules) */
++#define EC_DEV_CPSAR EC_DEVICE(0x1A)
++#define EC_DEV_AAL5 EC_DEVICE(0x1B)
++#define EC_DEV_AAL2 EC_DEVICE(0x1C)
++#define EC_DEV_CPMAC EC_DEVICE(0x1D)
++#define EC_DEV_VDMA EC_DEVICE(0x1E)
++#define EC_DEV_VLYNQ EC_DEVICE(0x1F)
++#define EC_DEV_CPPI EC_DEVICE(0x20)
++#define EC_DEV_CPMDIO EC_DEVICE(0x21)
++
++/*---------------------------------------------------------------------------
++ Function types
++---------------------------------------------------------------------------*/
++#define EC_FUNC_READ_CONF EC_FUNC(1)
++#define EC_FUNC_INIT EC_FUNC(2)
++
++/*---------------------------------------------------------------------------
++ Error codes
++---------------------------------------------------------------------------*/
++#define EC_CRITICAL (1<<CRITICAL_SHIFT)
++#define EC_NO_ERRORS 0
++#define EC_VAL_NO_BASE EC_ERR(1)
++#define EC_VAL_NO_RESET_BIT EC_ERR(2)
++#define EC_VAL_NO_RESET EC_ERR(3)
++#define EC_VAL_BAD_BASE EC_ERR(4)
++#define EC_VAL_MALLOCFAILED EC_ERR(5)
++#define EC_VAL_NO_RESETBASE EC_ERR(6)
++#define EC_DEVICE_NOT_FOUND EC_ERR(7)
++
++/*---------------------------------------------------------------------------
++ Function declarations
++---------------------------------------------------------------------------*/
++extern void ec_log_error( unsigned int );
++
++#endif /* _INC_EC_ERRORS */
+diff -urN linux.old/drivers/net/avalanche_cpmac/hcpmac.c linux.dev/drivers/net/avalanche_cpmac/hcpmac.c
+--- linux.old/drivers/net/avalanche_cpmac/hcpmac.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/hcpmac.c 2005-07-12 02:48:42.174574000 +0200
+@@ -0,0 +1,1878 @@
++/******************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002-2004 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE:
++ *
++ * DESCRIPTION:
++ * This file contains the code for the HAL EMAC Bridge Test
++ *
++ * HISTORY:
++ * xxXxx01 Denis RC1.00 Original Version created.
++ * 22Jan02 Denis/Mick RC1.01 Modified for HAL EMAC API
++ * 24Jan02 Denis/Mick RC1.02 Speed Improvements
++ * 28Jan02 Denis/Mick RC1.16 Made function calls pointers
++ * 28Jan02 Mick RC1.18 Split into separate modules
++ * 29Jan02 Mick RC1.19 Hal include file cleaned up
++ * 15Jul02 Michael Hanrahan RC1.20 Synch'd with Linux Version
++ * 23Sep02 Michael Hanrahan RC1.21 Added CPPI.C
++ * 16Oct02 Michael Hanrahan RC1.22 Added CAF etc to Options.Conf
++ * 09Jan03 Michael Hanrahan RC3.01 Fixed incorrect MDIO check
++ * 01Feb03 Michael Hanrahan RC3.02 Updated for GPIO/PBUSFREQ
++ * 29Mar03 Michael Hanrahan 1.03 Corrected ChannelConfigGet
++ * 29Mar03 Michael Hanrahan 1.03 Removed user setting of TxNumQueues
++ * 23Aug04 Michael Hanrahan 1.7.8 Support for Setting Mac Address
++ * @author Michael Hanrahan
++ * @version 1.02
++ * @date 24-Jan-2002
++ *****************************************************************************/
++#define _HAL_CPMAC
++#define _CPHAL_CPMAC
++#define _CPHAL
++#define __CPHAL_CPMDIO
++
++#include "dox_cpmac.h" /* Documentation information */
++
++/* OS Data Structure definitions */
++
++typedef void OS_PRIVATE;
++typedef void OS_DEVICE;
++typedef void OS_SENDINFO;
++typedef void OS_RECEIVEINFO;
++typedef void OS_SETUP;
++
++/* HAL Data Structure definitions */
++
++typedef struct _phy_device PHY_DEVICE;
++typedef struct hal_device HAL_DEVICE;
++typedef struct hal_private HAL_PRIVATE;
++typedef struct hal_private HAL_RECEIVEINFO;
++
++#include "cpcommon_cpmac.h"
++#include "cpswhal_cpmac.h"
++#include "cpmdio.h"
++#include "hcpmac.h"
++#include "cpmac_reg.h"
++
++
++#define EC_MODULE
++
++/* MDIO Clock Frequency Default Value */
++
++/* Rcb/Tcb Constants */
++
++#define CB_SOF_BIT (1<<31)
++#define CB_EOF_BIT (1<<30)
++#define CB_SOF_AND_EOF_BIT (CB_SOF_BIT|CB_EOF_BIT)
++#define CB_OWNERSHIP_BIT (1<<29)
++#define CB_EOQ_BIT (1<<28)
++#define CB_SIZE_MASK 0x0000ffff
++#define RCB_ERRORS_MASK 0x03fe0000
++
++static char *channel_names[] = CHANNEL_NAMES; /* GSG 11/22 (may change this implementation) */
++
++#define scFound(Module) if (HalDev->State != enDevFound) return (Module|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE)
++#define scInit(Module) if (HalDev->State < enInitialized) return (Module|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE)
++#define scOpen(Module) if (HalDev->State < enOpened) return (Module|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE)
++
++
++
++/********************************************************************
++**
++** L O C A L F U N C T I O N S
++**
++********************************************************************/
++static int halIsr(HAL_DEVICE *HalDev, int *MorePackets);
++static int cpmacRandom(HAL_DEVICE *HalDev);
++static int cpmacRandomRange(HAL_DEVICE *HalDev, int min, int max);
++static int halPacketProcessEnd(HAL_DEVICE *HalDev);
++
++#include "cpcommon_cpmac.c" /*~RC3.02*/
++#include "cppi_cpmac.c"
++#include "cpmdio.c" /*~RC3.02*/
++
++static int MacAddressSave(HAL_DEVICE *HalDev, unsigned char *MacAddr)
++ {
++ int i;
++ int inst = HalDev->inst;
++
++ HalDev->MacAddr = MacAddr;
++
++ if(HalDev->debug)
++ {
++ dbgPrintf("MacAddrSave[%d]: ", inst);
++ for (i=0;i<6;i++)
++ dbgPrintf("%X", HalDev->MacAddr[i]);
++ dbgPrintf("\n");
++ osfuncSioFlush();
++ }
++ return(EC_NO_ERRORS);
++ }
++static int MacAddressSet(HAL_DEVICE *HalDev)
++ {
++ unsigned char *macadr = &HalDev->MacAddr[0];
++ int base = HalDev->dev_base;
++
++ scOpen(EC_CPMAC);
++ CPMAC_MACADDRLO_0(base) = macadr[5];
++ CPMAC_MACADDRMID(base) = macadr[4];
++ CPMAC_MACADDRHI(base) = (macadr[0])|(macadr[1]<<8)|(macadr[2]<<16)|(macadr[3]<<24);
++ if(HalDev->debug)
++ {
++ dbgPrintf("MacAddrSet: MacAddr(%d) %X %X %X\n", HalDev->inst, CPMAC_MACADDRLO_0(base),
++ CPMAC_MACADDRMID(base),
++ CPMAC_MACADDRHI(base));
++
++ dbgPrintf("Start MAC: %d\n",HalDev->dev_base);
++ osfuncSioFlush();
++ }
++ return(EC_NO_ERRORS);
++ }
++
++
++/*
++ Updates the MacHash registers
++*/
++static void MacHashSet(HAL_DEVICE *HalDev)
++ {
++ if(HalDev->State < enOpened)
++ return;
++
++ CPMAC_MACHASH1(HalDev->dev_base) = HalDev->MacHash1;
++ CPMAC_MACHASH2(HalDev->dev_base) = HalDev->MacHash2;
++ if (DBG(11))
++ dbgPrintf("CPMAC[%X]: MacHash1 0x%08X, MacHash2 0x%08X\n", HalDev->dev_base, CPMAC_MACHASH1(HalDev->dev_base), CPMAC_MACHASH2(HalDev->dev_base));
++ }
++
++/*
++ Reads the MacControl register and updates
++ the changable bits. (See MACCONTROL_MASK)
++*/
++static void RxMBP_EnableSet(HAL_DEVICE *HalDev)
++ {
++ bit32u RxMbpEnable;
++ if(HalDev->State < enOpened)
++ return;
++ RxMbpEnable = CPMAC_RX_MBP_ENABLE(HalDev->dev_base);
++ RxMbpEnable &= ~RX_MBP_ENABLE_MASK; /* Clear out updatable bits */
++ RxMbpEnable |= HalDev->RxMbpEnable;
++ CPMAC_RX_MBP_ENABLE(HalDev->dev_base) = RxMbpEnable;
++ }
++/*
++ Reads the MacControl register and updates
++ the changable bits. (See MACCONTROL_MASK)
++*/
++static void MacControlSet(HAL_DEVICE *HalDev)
++ {
++ bit32u MacControl;
++ if(HalDev->State < enOpened)
++ return;
++ MacControl = CPMAC_MACCONTROL(HalDev->dev_base);
++ MacControl &= ~MACCONTROL_MASK; /* Clear out updatable bits */
++ MacControl |= HalDev->MacControl;
++ if(!(MacControl & MII_EN)) /* If Enable is not set just update register */
++ CPMAC_MACCONTROL(HalDev->dev_base) = MacControl;
++ else
++ {
++ if(MacControl & CTRL_LOOPBACK) /* Loopback Set */
++ {
++ /* mii_en is set and loopback is needed,
++ clear mii_en, set loopback, then set mii_en
++ */
++ MacControl &= ~MII_EN; /* Clear MII_EN */
++ CPMAC_MACCONTROL(HalDev->dev_base) = MacControl;
++ CPMAC_MACCONTROL(HalDev->dev_base) |= MII_EN; /* Set MII_EN */
++ HalDev->Linked = 1; /* if in loopback the logically linked */
++ }
++ else /* If Loopback not set just update */
++ {
++ CPMAC_MACCONTROL(HalDev->dev_base) = MacControl;
++ }
++ }
++ if(DBG(0))
++ dbgPrintf("[halMacControlSet]MacControl:%08X\n", CPMAC_MACCONTROL(HalDev->dev_base));
++ }
++static int UnicastSet(HAL_DEVICE *HalDev)
++ {
++ CPMAC_RX_UNICAST_SET(HalDev->dev_base) = HalDev->RxUnicastSet;
++ CPMAC_RX_UNICAST_CLEAR(HalDev->dev_base) = HalDev->RxUnicastClear;
++ return(EC_NO_ERRORS);
++ }
++
++
++static bit32u HashGet(bit8u *Address)
++ {
++ bit32u hash;
++ bit8u tmpval;
++ int i;
++
++ hash = 0;
++ for( i=0; i<2; i++ )
++ {
++ tmpval = *Address++;
++ hash ^= (tmpval>>2)^(tmpval<<4);
++ tmpval = *Address++;
++ hash ^= (tmpval>>4)^(tmpval<<2);
++ tmpval = *Address++;
++ hash ^= (tmpval>>6)^(tmpval);
++ }
++
++ return( hash & 0x3F );
++ }
++
++static void HashAdd(HAL_DEVICE *HalDev, bit8u *MacAddress)
++{
++ bit32u HashValue;
++ bit32u HashBit;
++
++ HashValue = HashGet(MacAddress);
++
++ if(HashValue < 32)
++ {
++ HashBit = (1 << HashValue);
++ HalDev->MacHash1 |= HashBit;
++ }
++ else
++ {
++ HashBit = (1 << (HashValue-32));
++ HalDev->MacHash2 |= HashBit;
++ }
++}
++
++static void HashDel(HAL_DEVICE *HalDev, bit8u *MacAddress)
++{
++ bit32u HashValue;
++ bit32u HashBit;
++
++ HashValue = HashGet(MacAddress);
++
++ if(HashValue < 32)
++ {
++ HashBit = (1 << HashValue);
++ HalDev->MacHash1 &= ~HashBit;
++ }
++ else
++ {
++ HashBit = (1 << (HashValue-32));
++ HalDev->MacHash2 &= ~HashBit;
++ }
++}
++
++/* Replace with an array based on key, with a ptr to the code to do */
++/* e.g. [enRX_PASS_CRC] = {Set, MBP_UPDATE() } */
++static void DuplexUpdate(HAL_DEVICE *HalDev)
++{
++ int base = HalDev->dev_base;
++ PHY_DEVICE *PhyDev = HalDev->PhyDev;
++
++ if(HalDev->State < enOpened)
++ return;
++
++ /* No Phy Condition */
++ if(HalDev->MdioConnect & _CPMDIO_NOPHY) /*MJH+030805*/
++ {
++ /* No Phy condition, always linked */
++ HalDev->Linked = 1;
++ HalDev->EmacSpeed = 1;
++ HalDev->EmacDuplex = 1;
++ HalDev->PhyNum = 0xFFFFFFFF; /* No Phy Num */
++ CPMAC_MACCONTROL(base) |= FULLDUPLEX; /*MJH+030909*/
++ osfuncStateChange();
++ return;
++ }
++
++ if(HalDev->MacControl & CTRL_LOOPBACK) /* Loopback Set */
++ {
++ HalDev->Linked = 1;
++ return;
++ }
++
++ if (HalDev->MdioConnect & _CPMDIO_LOOPBK)
++ {
++ HalDev->Linked = cpMacMdioGetLoopback(HalDev->PhyDev);
++ }
++ else
++ {
++ HalDev->Linked = cpMacMdioGetLinked(HalDev->PhyDev);
++ }
++ if (HalDev->Linked)
++ {
++ /* Retreive Duplex and Speed and the Phy Number */
++ if(HalDev->MdioConnect & _CPMDIO_LOOPBK)
++ HalDev->EmacDuplex = 1;
++ else
++ HalDev->EmacDuplex = cpMacMdioGetDuplex(PhyDev);
++ HalDev->EmacSpeed = cpMacMdioGetSpeed(PhyDev);
++ HalDev->PhyNum = cpMacMdioGetPhyNum(PhyDev);
++
++ if(HalDev->EmacDuplex)
++ CPMAC_MACCONTROL(base) |= FULLDUPLEX;
++ else
++ CPMAC_MACCONTROL(base) &= ~FULLDUPLEX;
++ if(HalDev->debug)
++ dbgPrintf("%d: Phy= %d, Speed=%s, Duplex=%s\n",HalDev->inst,HalDev->PhyNum,(HalDev->EmacSpeed)?"100":"10",(HalDev->EmacDuplex)?"Full":"Half");
++ }
++ if(HalDev->debug)
++ dbgPrintf("DuplexUpdate[%d]: MACCONTROL 0x%08X, %s\n", HalDev->inst, CPMAC_MACCONTROL(base),(HalDev->Linked)?"Linked":"Not Linked");
++}
++static void MdioSetPhyMode(HAL_DEVICE *HalDev)
++ {
++ unsigned int PhyMode;
++ /* Verify proper device state */
++ if (HalDev->State < enOpened)
++ return;
++
++ PhyMode = NWAY_AUTO|NWAY_FD100|NWAY_HD100|NWAY_FD10|NWAY_HD10;
++ if(DBG(0))
++ {
++ dbgPrintf("halSetPhyMode1: MdioConnect:%08X ,", HalDev->MdioConnect);
++ dbgPrintf("PhyMode:%08X Auto:%d, FD10:%d, HD10:%d, FD100:%d, HD100:%d\n", PhyMode,
++ PhyMode&NWAY_AUTO, PhyMode&NWAY_FD10, PhyMode&NWAY_HD10, PhyMode&NWAY_FD100,
++ PhyMode&NWAY_HD100);
++ }
++
++
++ if ( HalDev->MdioConnect & _CPMDIO_NEG_OFF) /* ~RC3.01 */
++ PhyMode &= ~(NWAY_AUTO); /* Disable Auto Neg */
++ if (!(HalDev->MdioConnect & _CPMDIO_HD))
++ PhyMode &= ~(NWAY_HD100|NWAY_HD10); /* Cannot support HD */
++ if (!(HalDev->MdioConnect & _CPMDIO_FD))
++ PhyMode &= ~(NWAY_FD100|NWAY_FD10); /* Cannot support FD */
++ if (!(HalDev->MdioConnect & _CPMDIO_10))
++ PhyMode &= ~(NWAY_HD10|NWAY_FD10); /* Cannot support 10 Mbs */
++ if (!(HalDev->MdioConnect & _CPMDIO_100))
++ PhyMode &= ~(NWAY_HD100|NWAY_FD100); /* Cannot support 100 Mbs */
++
++ if(HalDev->MdioConnect & _CPMDIO_AUTOMDIX) PhyMode |= NWAY_AUTOMDIX; /* Set AutoMdix */
++
++ if (HalDev->CpmacFrequency <= 50000000)
++ PhyMode &= ~(NWAY_FD100|NWAY_HD100); /* Cannot support 100 MBS */
++ if(DBG(7))
++ dbgPrintf("halNeg: PhyMode[0x%08X] %d\n", HalDev->dev_base, PhyMode);
++
++ if(DBG(0))
++ {
++ dbgPrintf("halSetPhyMode2: MdioConnect:%08X ,", HalDev->MdioConnect);
++ dbgPrintf("PhyMode:%08X Auto:%d, FD10:%d, HD10:%d, FD100:%d, HD100:%d\n", PhyMode,
++ PhyMode&NWAY_AUTO, PhyMode&NWAY_FD10, PhyMode&NWAY_HD10, PhyMode&NWAY_FD100,
++ PhyMode&NWAY_HD100);
++ }
++
++
++ cpMacMdioSetPhyMode(HalDev->PhyDev,PhyMode);
++ DuplexUpdate(HalDev);
++ }
++static int StatsClear(HAL_DEVICE *HalDev)
++{
++ int i;
++ MEM_PTR pStats;
++
++ scOpen(EC_CPMAC);
++
++ pStats = pCPMAC_RXGOODFRAMES(HalDev->dev_base);
++ for (i=0;i<STATS_MAX;i++)
++ {
++ *(MEM_PTR)(pStats) = 0xFFFFFFFF;
++ pStats++;
++ }
++
++ return(EC_NO_ERRORS);
++}
++static void StatsDump(HAL_DEVICE *HalDev, void *Value)
++ {
++ MEM_PTR ptrStats;
++ MEM_PTR ptrValue;
++ int i;
++ ptrStats = pCPMAC_RXGOODFRAMES(HalDev->dev_base);
++ ptrValue = (bit32u*) Value;
++ for (i=0; i<STATS_MAX; i++)
++ {
++ *ptrValue = *ptrStats;
++ if(DBG(4))
++ {
++ dbgPrintf("halStatsDump: Stat[%d:0x%08X] %d 0x%08X %d\n", i, ptrStats, *ptrStats, ptrValue, *ptrValue);
++ osfuncSioFlush();
++ }
++ ptrStats++;
++ ptrValue++;
++ }
++ }
++static void ConfigApply(HAL_DEVICE *HalDev)
++ {
++ CPMAC_RX_MAXLEN(HalDev->dev_base) = HalDev->RxMaxLen;
++ CPMAC_RX_FILTERLOWTHRESH(HalDev->dev_base) = HalDev->RxFilterLowThresh;
++ CPMAC_RX0_FLOWTHRESH(HalDev->dev_base) = HalDev->Rx0FlowThresh;
++ UnicastSet(HalDev);
++ MacAddressSet(HalDev);
++ RxMBP_EnableSet(HalDev);
++ MacHashSet(HalDev);
++ MacControlSet(HalDev);
++ if(DBG(0))
++ dbgPrintf("ValuesUpdate[%d]: MBP_ENABLE 0x%08X\n", HalDev->inst, CPMAC_RX_MBP_ENABLE(HalDev->dev_base));
++ }
++static int halStatus(HAL_DEVICE *HalDev)
++{
++ int status;
++
++ if(HalDev->State < enOpened)
++ return (EC_CPMAC|EC_FUNC_STATUS|EC_VAL_INVALID_STATE); /*MJH+030805*/
++
++ /* No Phy Condition */
++ if(HalDev->MdioConnect & _CPMDIO_NOPHY) /*MJH+030805*/
++ {
++ /* No Phy condition, always linked */
++ status = HalDev->Linked;
++ status |= CPMAC_STATUS_LINK_DUPLEX;
++ status |= CPMAC_STATUS_LINK_SPEED;
++ return(status);
++ }
++
++
++ if (HalDev->HostErr) /* Adapter Check */
++ {
++ bit32u tmp;
++ status = CPMAC_STATUS_ADAPTER_CHECK;
++ if(HalDev->MacStatus & RX_HOST_ERR_CODE)
++ {
++ status |= CPMAC_STATUS_HOST_ERR_DIRECTION;
++ tmp = (HalDev->MacStatus & RX_HOST_ERR_CODE) >> 12; /* Code */
++ status |= (tmp << 9); /* Code */
++ tmp = (HalDev->MacStatus & RX_ERR_CH) >> 8; /* Channel */
++ status |= (tmp << 13);
++ }
++ else
++ if(HalDev->MacStatus & TX_HOST_ERR_CODE)
++ {
++ status |= CPMAC_STATUS_HOST_ERR_DIRECTION;
++ tmp = (HalDev->MacStatus & TX_HOST_ERR_CODE) >> 20; /* Code */
++ status |= (tmp << 9); /* Code */
++ tmp = (HalDev->MacStatus & TX_ERR_CH) >> 16; /* Channel */
++ status |= (tmp << 13);
++ }
++ }
++ else
++ {
++ status = HalDev->Linked;
++ if(status)
++ {
++ status = CPMAC_STATUS_LINK;
++ if(cpMacMdioGetDuplex(HalDev->PhyDev))
++ status |= CPMAC_STATUS_LINK_DUPLEX;
++ if(cpMacMdioGetSpeed(HalDev->PhyDev))
++ status |= CPMAC_STATUS_LINK_SPEED;
++ }
++ }
++ if(HalDev->debug)
++ dbgPrintf("[halStatus] Link Status is %d for 0x%X\n", status, HalDev->dev_base);
++ return(status);
++}
++static int InfoAccess(HAL_DEVICE *HalDev, int Key, int Action, void *ParmValue)
++ {
++ int rc = 0;
++ int Update=0;
++
++ switch (Key)
++ {
++ /********************************************************************/
++ /* */
++ /* GENERAL */
++ /* */
++ /********************************************************************/
++
++ case enVersion :
++ if(Action==enGET)
++ {
++ *(const char **)ParmValue = pszVersion_CPMAC;
++ }
++ break;
++ case enDebug :
++ if(Action==enSET)
++ {
++ HalDev->debug = *(unsigned int *)ParmValue;
++ }
++ break;
++
++ case enStatus :
++ if(Action==enGET)
++ {
++ int status;
++ status = halStatus(HalDev);
++ *(int *)ParmValue = status;
++ }
++ break;
++ /********************************************************************/
++ /* */
++ /* RX_MBP_ENABLE */
++ /* */
++ /********************************************************************/
++
++ case enRX_PASS_CRC :
++ if(Action==enSET)
++ {
++ UPDATE_RX_PASS_CRC(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_QOS_EN :
++ if(Action==enSET)
++ {
++ UPDATE_RX_QOS_EN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_NO_CHAIN :
++ if(Action==enSET)
++ {
++ UPDATE_RX_NO_CHAIN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_CMF_EN :
++ if(Action==enSET)
++ {
++ UPDATE_RX_CMF_EN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_CSF_EN :
++ if(Action==enSET)
++ {
++ UPDATE_RX_CSF_EN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_CEF_EN :
++ if(Action==enSET)
++ {
++ UPDATE_RX_CEF_EN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_CAF_EN :
++ if(Action==enSET)
++ {
++ UPDATE_RX_CAF_EN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_PROM_CH :
++ if(Action==enSET)
++ {
++ UPDATE_RX_PROM_CH(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_BROAD_EN :
++ if(Action==enSET)
++ {
++ UPDATE_RX_BROAD_EN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_BROAD_CH :
++ if(Action==enSET)
++ {
++ UPDATE_RX_BROAD_CH(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_MULT_EN :
++ if(Action==enSET)
++ {
++ UPDATE_RX_MULT_EN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_MULT_CH :
++ if(Action==enSET)
++ {
++ UPDATE_RX_MULT_CH(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++
++ /********************************************************************/
++ /* */
++ /* MAC_CONTROL */
++ /* */
++ /********************************************************************/
++
++ case enTX_PTYPE :
++ if(Action==enSET)
++ {
++ UPDATE_TX_PTYPE(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enTX_PACE :
++ if(Action==enSET)
++ {
++ UPDATE_TX_PACE(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enTX_FLOW_EN :
++ if(Action==enSET)
++ {
++ UPDATE_TX_FLOW_EN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_FLOW_EN :
++ if(Action==enSET)
++ {
++ UPDATE_RX_FLOW_EN(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++
++ case enCTRL_LOOPBACK :
++ if(Action==enSET)
++ {
++ UPDATE_CTRL_LOOPBACK(*(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ /********************************************************************/
++ /* */
++ /* RX_UNICAST_SET */
++ /* */
++ /********************************************************************/
++
++ case enRX_UNICAST_SET :
++ if(Action==enSET)
++ {
++ HalDev->RxUnicastSet |= (1 << *(unsigned int *)ParmValue);
++ HalDev->RxUnicastClear &= ~(1 << *(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_UNICAST_CLEAR :
++ if(Action==enSET)
++ {
++ HalDev->RxUnicastClear |= (1 << *(unsigned int *)ParmValue);
++ HalDev->RxUnicastSet &= ~(1 << *(unsigned int *)ParmValue);
++ Update=1;
++ }
++ break;
++
++ case enRX_MAXLEN :
++ if(Action==enSET)
++ {
++ HalDev->RxMaxLen = *(unsigned int *)ParmValue;
++ Update=1;
++ }
++ break;
++
++ case enRX_FILTERLOWTHRESH :
++ if(Action==enSET)
++ {
++ HalDev->RxFilterLowThresh = *(unsigned int *)ParmValue;
++ Update=1;
++ }
++ break;
++ case enRX0_FLOWTHRESH :
++ if(Action==enSET)
++ {
++ HalDev->Rx0FlowThresh = *(unsigned int *)ParmValue;
++ Update=1;
++ }
++ break;
++ /********************************************************************/
++ /* */
++ /* RX_MULTICAST */
++ /* */
++ /********************************************************************/
++
++ case enRX_MULTICAST :
++ break;
++ case enRX_MULTI_SINGLE :
++ if(DBG(11))
++ {
++ int tmpi;
++ bit8u *MacAddress;
++ MacAddress = (bit8u *) ParmValue;
++ dbgPrintf("CPMAC[%X]: MacAddress '", HalDev->dev_base);
++ for (tmpi=0; tmpi<6; tmpi++)
++ dbgPrintf("%02X:", MacAddress[tmpi]);
++ dbgPrintf("\n");
++ }
++ if(Action==enCLEAR)
++ {
++ HashDel(HalDev, ParmValue);
++ Update=1;
++ }
++ else
++ if(Action==enSET)
++ {
++ HashAdd(HalDev, ParmValue);
++ Update=1;
++ }
++ break;
++ case enRX_MULTI_ALL :
++ if(Action==enCLEAR)
++ {
++ HalDev->MacHash1 = 0;
++ HalDev->MacHash2 = 0;
++ Update=1;
++ }
++ else
++ if(Action==enSET)
++ {
++ HalDev->MacHash1 = 0xFFFFFFFF;
++ HalDev->MacHash2 = 0xFFFFFFFF;
++ Update=1;
++ }
++ break;
++
++ /********************************************************************/
++ /* */
++ /* MDIO */
++ /* */
++ /********************************************************************/
++
++ case enMdioConnect :
++ if(Action==enSET)
++ {
++ HalDev->MdioConnect = *(unsigned int *)ParmValue;
++ MdioSetPhyMode(HalDev);
++ }
++ if(Action==enGET)
++ {
++ *(unsigned int *)ParmValue = HalDev->MdioConnect;
++ }
++ break;
++
++
++ /********************************************************************/
++ /* */
++ /* STATISTICS */
++ /* */
++ /********************************************************************/
++ case enStatsClear :
++ StatsClear(HalDev);
++ break;
++ case enStatsDump :
++ if(Action==enGET)
++ {
++ StatsDump(HalDev, ParmValue);
++ }
++ break;
++
++/* Not implemented
++ case enStats1 :
++ if(Action==enGET)
++ {
++ StatsGet(HalDev, ParmValue, 1);
++ }
++ break;
++
++ case enStats2 :
++ if(Action==enGET)
++ {
++ StatsGet(HalDev, ParmValue, 2);
++ }
++ break;
++ case enStats3 :
++ if(Action==enGET)
++ {
++ StatsGet(HalDev, ParmValue, 3);
++ }
++ break;
++ case enStats4 :
++ if(Action==enGET)
++ {
++ StatsGet(HalDev, ParmValue, 4);
++ }
++ break;
++
++*/
++
++ default:
++ rc = EC_CPMAC|EC_FUNC_OPTIONS|EC_VAL_KEY_NOT_FOUND;
++ break;
++ }
++
++ /* Verify proper device state */
++ if (HalDev->State == enOpened)
++ switch (Update)
++ {
++ case 1 :
++ ConfigApply(HalDev);
++ break;
++ default:
++ break;
++ }
++
++ return (rc);
++ }
++static const char pszStats[] = "Stats;";
++
++static int halControl(HAL_DEVICE *HalDev, const char *pszKey, const char *pszAction, void *Value)
++ {
++ int i;
++ int rc=0;
++ int Action;
++ int ActionFound;
++ int KeyFound;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(1))
++ {
++ dbgPrintf("\nhalControl-HalDev:%08X,Action:%s,Key:%s\n", (bit32u)HalDev, pszAction, pszKey);
++ }
++#endif
++
++ /* 23Aug04 - BCIL needs to set Mac Address */
++ if(HalDev->OsFunc->Strcmpi(pszKey, pszMacAddr) == 0)
++ {
++ KeyFound=1;
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
++ {
++ unsigned char *MacAddr;
++ MacAddr = (unsigned char *) Value;
++ MacAddressSave(HalDev, MacAddr);
++ MacAddressSet(HalDev);
++ return(0);
++ }
++ else
++ {
++ return(-1);
++ }
++ }
++
++ if(HalDev->OsFunc->Strcmpi(pszKey, hcLinked) == 0)
++ {
++ KeyFound=1;
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
++ {
++ HalDev->Linked = *(int *)Value;
++ return(0);
++ }
++ else
++ {
++ return(-1);
++ }
++ }
++
++ if(HalDev->OsFunc->Strcmpi(pszKey, "TxIntDisable") == 0)
++ {
++ KeyFound=1;
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
++ {
++ HalDev->TxIntDisable = *(int *)Value;
++ if(HalDev->TxIntDisable && (HalDev->State == enOpened))
++ {
++ /* if Opened and need TxIntDisabled, clear Ints for Channel 0 */
++ CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = 1;
++ }
++ return(0);
++ }
++ else
++ {
++ return(-1);
++ }
++ }
++
++ if(HalDev->OsFunc->Strcmpi(pszKey, hcPhyAccess) == 0)
++ {
++ bit32u RegAddr;
++ bit32u PhyNum;
++ bit32u Data;
++ bit32u ValueIn;
++
++ ValueIn = *(bit32u*) Value;
++
++ KeyFound=1;
++ /* Cannot access MII if not opended */
++
++ if(HalDev->State < enOpened)
++ return(-1);
++
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
++ {
++
++ PhyNum = (ValueIn & 0x1F); /* Phynum 0-32 */
++ RegAddr = (ValueIn >> 5) & 0xFF; /* RegAddr in upper 11 bits */
++
++ *(bit32u*)Value = _mdioUserAccessRead(HalDev->PhyDev, RegAddr, PhyNum);
++
++ return(0);
++ } /* end of hcGet */
++
++
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
++ {
++ PhyNum = (ValueIn & 0x1F); /* Phynum 0-32 */
++ RegAddr = (ValueIn >> 5) & 0xFF; /* RegAddr in upper 11 bits of lower 16 */
++
++ Data = ValueIn >> 16; /* Data store in upper 16 bits */
++
++ _mdioUserAccessWrite(HalDev->PhyDev, RegAddr, PhyNum, Data);
++ return(0);
++ }
++ } /* End of hcPhyAccess */
++
++ if(HalDev->OsFunc->Strcmpi(pszKey, hcPhyNum) == 0)
++ {
++ KeyFound=1;
++ if(!HalDev->Linked)
++ return(-1); /* if not linked the no Phy Connected */
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
++ {
++ *(int *)Value = HalDev->PhyNum;
++ return(0);
++ }
++ }
++
++ if(HalDev->OsFunc->Strcmpi(pszKey, hcCpmacSize) == 0)
++ {
++ KeyFound=1;
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
++ {
++ *(bit32u *)Value = HalDev->CpmacSize;
++ return(0);
++ }
++ }
++
++ if(HalDev->OsFunc->Strcmpi(pszKey, hcCpmacBase) == 0)
++ {
++ KeyFound=1;
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
++ {
++ *(int *)Value = HalDev->dev_base;
++ return(0);
++ }
++ }
++
++ if(HalDev->OsFunc->Strcmpi(pszKey, hcFullDuplex) == 0)
++ {
++ KeyFound=1;
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
++ {
++ UPDATE_FULLDUPLEX(*(unsigned int *)Value);
++ if(HalDev->State == enOpened)
++ ConfigApply(HalDev);
++ return(0);
++ }
++ else
++ return(-1);
++ }
++
++ if(HalDev->OsFunc->Strcmpi(pszKey, pszDebug) == 0)
++ {
++ KeyFound=1;
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
++ {
++ ActionFound=1;
++ HalDev->debug = *(int *)Value;
++ }
++ }
++
++ if(HalDev->OsFunc->Strcmpi(pszKey, hcMaxFrags) == 0)
++ {
++ KeyFound=1;
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
++ {
++ ActionFound=1;
++
++ if ((*(int *)Value) > 0)
++ HalDev->MaxFrags = *(int *)Value;
++ else
++ rc = (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_INVALID_VALUE);
++ }
++
++ if (HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
++ {
++ ActionFound=1;
++
++ *(int *)Value = HalDev->MaxFrags;
++ }
++ }
++
++ if(HalDev->OsFunc->Strstr(pszKey, pszStats) != 0)
++ {
++ KeyFound=1;
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
++ {
++ int Level;
++ int Ch;
++ char *TmpKey = (char *)pszKey;
++ ActionFound=1;
++ TmpKey += HalDev->OsFunc->Strlen(pszStats);
++ Level = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++ TmpKey++;
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++ TmpKey++;
++ osfuncSioFlush();
++#ifdef __CPHAL_DEBUG
++ if (DBG(1))
++ {
++ dbgPrintf("\nhalControl-HalDev:%08X, Level:%d, Ch:%d\n", (bit32u)HalDev, Level, Ch);
++ }
++#endif
++ StatsGet(HalDev, (void **)Value, Level, Ch, 0);
++ osfuncSioFlush();
++ }
++ }
++
++
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcSet) == 0)
++ Action = enSET;
++ else
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcClear) == 0)
++ Action = enCLEAR;
++ else
++ if(HalDev->OsFunc->Strcmpi(pszAction, hcGet) == 0)
++ Action = enGET;
++ else
++ Action = enNULL;
++
++
++
++ for(i=enCommonStart+1;i<enCommonEnd;i++)
++ {
++ if(HalDev->OsFunc->Strcmpi(KeyCommon[i].strKey, pszKey)==0)
++ {
++ rc = InfoAccess(HalDev, KeyCommon[i].enKey, Action, Value);
++ }
++ }
++ for(i=enCpmacStart+1;i<enCpmacEnd;i++)
++ {
++ if(HalDev->OsFunc->Strcmpi(KeyCpmac[i].strKey, pszKey)==0)
++ {
++ rc = InfoAccess(HalDev, KeyCpmac[i].enKey, Action, Value);
++ }
++ }
++/*
++ if (KeyFound == 0)
++ rc = (EC_MODULE|EC_FUNC_CONTROL|EC_VAL_KEY_NOT_FOUND);
++
++ if (ActionFound == 0)
++ rc = (EC_MODULE|EC_FUNC_CONTROL|EC_VAL_ACTION_NOT_FOUND);
++*/
++
++ return(rc);
++ }
++static bit32u ConfigGet(HAL_DEVICE *HalDev)
++ {
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++ char *DeviceInfo = HalDev->DeviceInfo;
++ int i = HalDev->inst;
++ bit32u Value;
++ int Error;
++
++ /* get the configuration parameters common to all modules */
++ Error = ConfigGetCommon(HalDev);
++ if (Error) return (EC_CPMAC|Error);
++
++ if (HalDev->debug)
++ {
++ dbgPrintf("ConfigGet: haldev:0x%08X inst:%d base:0x%08X reset:%d\n", (bit32u) &HalDev, HalDev->inst, HalDev->dev_base, HalDev->ResetBit);
++ osfuncSioFlush();
++ }
++
++ Error = OsFunc->DeviceFindParmUint(DeviceInfo, pszMdioConnect,&Value); /*MJH+030805*/
++ if(!Error) HalDev->MdioConnect = Value;
++
++ Error = OsFunc->DeviceFindParmUint(DeviceInfo, "PhyMask",&Value);
++ if(!Error) HalDev->PhyMask = Value;
++
++ Error = OsFunc->DeviceFindParmUint(DeviceInfo, "MLink",&Value);
++ if(!Error) HalDev->MLinkMask = Value;
++
++ Error = OsFunc->DeviceFindParmUint(DeviceInfo, hcMdixMask, &Value);
++ if(!Error)
++ HalDev->MdixMask = Value;
++ else
++ HalDev->MdixMask = 0;
++
++ Error = OsFunc->DeviceFindParmUint(DeviceInfo, hcSize, &Value); /*MJH+030425*/
++ if(!Error) HalDev->CpmacSize = Value;
++
++ for(i=enCommonStart+1;i<enCommonEnd;i++)
++ {
++ Error = OsFunc->DeviceFindParmUint(DeviceInfo, KeyCommon[i].strKey, (bit32u*)&Value);
++ if(!Error)
++ {
++ InfoAccess(HalDev, KeyCommon[i].enKey, enSET, (bit32u*)&Value);
++ }
++ }
++ for(i=enCpmacStart+1;i<enCpmacEnd;i++)
++ {
++ Error = OsFunc->DeviceFindParmUint(DeviceInfo, KeyCpmac[i].strKey, (bit32u*)&Value);
++ if(!Error)
++ {
++ InfoAccess(HalDev, KeyCpmac[i].enKey, enSET, (bit32u*)&Value);
++ }
++ }
++ return (EC_NO_ERRORS);
++ }
++
++
++static void ConfigInit(HAL_DEVICE *HalDev)
++ {
++ if(HalDev->inst == 0)
++ {
++ HalDev->dev_base = 0xA8610000;
++ HalDev->ResetBit = 17;
++ HalDev->interrupt = 19;
++ HalDev->MLinkMask = 0;
++ HalDev->PhyMask = 0xAAAAAAAA;
++ }
++ else
++ {
++ HalDev->dev_base = 0xA8612800;
++ HalDev->ResetBit = 21;
++ HalDev->interrupt = 33; /*~RC3.02*/
++ HalDev->MLinkMask = 0;
++ HalDev->PhyMask = 0x55555555;
++ }
++ HalDev->RxMaxLen = 1518;
++ HalDev->MaxFrags = 2;
++ HalDev->MdioConnect = _CPMDIO_HD|_CPMDIO_FD|_CPMDIO_10|_CPMDIO_100|_CPMDIO_AUTOMDIX;
++ HalDev->debug=0xFFFFFFFF;
++ HalDev->debug=0;
++ }
++/* Shuts down the EMAC device
++ *
++ *@param HalDev EMAC instance. This was returned by halOpen()
++ *@param mode Indicates actions to tak on close.
++ <br>
++ *PARTIAL - Disable EMAC
++ <br>
++ *FULL - Disable EMAC and call OS to free all allocated memory
++ *
++ *@retval
++ * 0 OK
++ <br>
++ * Non-Zero Not OK
++ *
++ */
++static int halInit( HAL_DEVICE *HalDev)
++ {
++ int rc;
++
++ /* Verify proper device state */
++ if (HalDev->State != enDevFound)
++ return(EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_INVALID_STATE);
++
++ /* Configure HAL defaults */
++ ConfigInit(HalDev);
++
++ /* Retrieve HAL configuration parameters from data store */
++ rc = ConfigGet(HalDev);
++ if (rc) return (rc);
++
++ /* Updated 030403*/
++ rc = HalDev->OsFunc->Control(HalDev->OsDev, hcCpuFrequency, hcGet, &HalDev->CpuFrequency); /*MJH+030403*/
++ if(rc)
++ HalDev->CpuFrequency = 20000000; /*20 Mhz default */ /*MJH+030403*/
++
++ rc = HalDev->OsFunc->Control(HalDev->OsDev, hcCpmacFrequency, hcGet, &HalDev->CpmacFrequency); /*MJH+030331*/
++ if(rc)
++ HalDev->CpmacFrequency = HalDev->CpuFrequency/2; /*MJH~030404*/
++
++ rc = HalDev->OsFunc->Control(HalDev->OsDev, hcMdioBusFrequency, hcGet, &HalDev->MdioBusFrequency); /*MJH+030402*/
++ if(rc)
++ HalDev->MdioBusFrequency = HalDev->CpmacFrequency;
++
++ rc = HalDev->OsFunc->Control(HalDev->OsDev, hcMdioClockFrequency, hcGet, &HalDev->MdioClockFrequency); /*MJH+030402*/
++ if(rc)
++ HalDev->MdioClockFrequency = 2200000; /* 2.2 Mhz PITS #14 */
++
++
++ /* update device state */
++ HalDev->State = enInitialized;
++
++ /* initialize statistics */
++ StatsInit(HalDev); /* +RC3.02 */
++
++ /* -RC3.02
++ StatsTable3[0].StatPtr = &HalDev->ChData[0].RxBufSize;
++ StatsTable3[1].StatPtr = &HalDev->ChData[0].RxBufferOffset;
++ StatsTable3[2].StatPtr = &HalDev->ChData[0].RxNumBuffers;
++ StatsTable3[3].StatPtr = &HalDev->ChData[0].RxServiceMax;
++ StatsTable3[4].StatPtr = &HalDev->ChData[0].TxNumBuffers;
++ StatsTable3[5].StatPtr = &HalDev->ChData[0].TxNumQueues;
++ StatsTable3[6].StatPtr = &HalDev->ChData[0].TxServiceMax;
++ */
++
++ return(EC_NO_ERRORS);
++ }
++static int halProbe(HAL_DEVICE *HalDev)
++ {
++ int inst = HalDev->inst;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++ int error_code;
++
++ if (HalDev->State != enConnected)
++ return (EC_CPMAC|EC_FUNC_PROBE|EC_VAL_INVALID_STATE);
++
++ if(HalDev->debug) dbgPrintf("halProbe: %d ",inst);
++
++ error_code = OsFunc->DeviceFindInfo(inst,"cpmac",&HalDev->DeviceInfo);
++
++ if(error_code)
++ return (EC_CPMAC|EC_FUNC_PROBE|EC_VAL_DEVICE_NOT_FOUND );
++
++ /* Set device state to DevFound */
++ HalDev->State = enDevFound;
++ return(EC_NO_ERRORS);
++ }
++static void ChannelConfigInit(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
++ {
++ int Ch = HalChn->Channel;
++ int Direction = HalChn->Direction;
++ int nTxBuffers = 256;
++
++ if (Direction == DIRECTION_TX)
++ {
++ HalDev->ChData[Ch].TxNumBuffers = nTxBuffers;
++ HalDev->ChData[Ch].TxNumQueues = 1;
++ HalDev->ChData[Ch].TxServiceMax = nTxBuffers/3;
++ HalDev->TxIntThreshold[Ch] = HalDev->ChData[Ch].TxServiceMax;
++ HalDev->TxIntThresholdMaster[Ch] = HalDev->TxIntThreshold[Ch];
++ }
++
++ if (Direction == DIRECTION_RX)
++ {
++ HalDev->ChData[Ch].RxNumBuffers = nTxBuffers*2;
++ HalDev->ChData[Ch].RxBufferOffset = 0;
++ HalDev->ChData[Ch].RxBufSize = 1518;
++ HalDev->ChData[Ch].RxServiceMax = nTxBuffers/3; /*Not a typo*/
++ }
++ }
++static int ChannelConfigApply(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
++ {
++ int Ch = HalChn->Channel;
++ int Direction = HalChn->Direction;
++
++ if (DBG(11))
++ {
++ dbgPrintf("halChannelConfigApply[%d:%d] haldev:0x%08X inst:%d base:0x%08X reset:%d\n", Ch, Direction, (bit32u) &HalDev, HalDev->inst, HalDev->dev_base, HalDev->ResetBit);
++ osfuncSioFlush();
++ }
++
++ if (Direction == DIRECTION_TX)
++ {
++ if (HalDev->ChIsOpen[Ch][Direction] == TRUE)
++ {
++ return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_TX_CH_ALREADY_OPEN);
++ }
++
++ /* Initialize Queue Data */
++ HalDev->TxActQueueHead[Ch][0] = 0;
++ HalDev->TxActQueueCount[Ch][0] = 0;
++ HalDev->TxActive[Ch][0] = FALSE;
++
++ /* Need to use a macro that takes channel as input */
++ CPMAC_TX0_HDP(HalDev->dev_base)=0;
++
++ /* Initialize buffer memory for the channel */
++ InitTcb(HalDev, Ch);
++
++ if(!HalDev->TxIntDisable)
++ CPMAC_TX_INTMASK_SET(HalDev->dev_base) = (1<<Ch); /* GSG 11/22 */
++ }
++ else
++ {
++ if (HalDev->ChIsOpen[Ch][Direction] == TRUE)
++ {
++ return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_RX_CH_ALREADY_OPEN);
++ }
++
++ /* Initialize Queue Data */
++ HalDev->RxActQueueHead[Ch] = 0;
++ HalDev->RxActQueueCount[Ch] = 0;
++
++ HalDev->RxActive[Ch] = FALSE;
++
++ /* Need to use a macro that takes channel as input */
++ CPMAC_RX0_HDP(HalDev->dev_base)=0;
++
++ /* Initialize buffer memory for the channel */
++ InitRcb(HalDev, Ch);
++
++ CPMAC_RX_INTMASK_SET(HalDev->dev_base) = (1<<Ch); /* GSG 11/22 */
++ }
++
++ HalDev->ChIsOpen[Ch][Direction] = TRUE; /* channel is open */
++
++ return (EC_NO_ERRORS);
++ }
++
++/* GSG 11/22
++ * Retrieves channel parameters from configuration file. Any parameters
++ * which are not found are ignored, and the HAL default value will apply,
++ * unless a new value is given through the channel structure in the call
++ * to ChannelSetup.
++ */
++static int ChannelConfigGet(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
++ {
++ int Ch = HalChn->Channel;
++ int Direction = HalChn->Direction;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++ unsigned int rc, Value;
++ void *ChInfo;
++
++ rc=OsFunc->DeviceFindParmValue(HalDev->DeviceInfo, channel_names[Ch], &ChInfo);
++ /* Do not fail if Channel Info not available for RC2 */
++ if (rc) return(0);
++/* if (rc) return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_CH_INFO_NOT_FOUND);*/
++
++ /* i don't care if a value is not found because they are optional */
++ if(Direction == DIRECTION_TX)
++ {
++ rc=OsFunc->DeviceFindParmUint(ChInfo, "TxNumBuffers", &Value);
++ if (!rc) HalDev->ChData[Ch].TxNumBuffers = Value;
++
++ /*rc=OsFunc->DeviceFindParmUint(ChInfo, "TxNumQueues", &Value);*/ /*MJH-030329*/
++ /*if (!rc) HalDev->ChData[Ch].TxNumQueues = Value;*/ /*MJH-030329*/
++
++ rc=OsFunc->DeviceFindParmUint(ChInfo, "TxServiceMax", &Value);
++ if (!rc)
++ {
++ HalDev->ChData[Ch].TxServiceMax = Value;
++ HalDev->TxIntThreshold[Ch] = HalDev->ChData[Ch].TxServiceMax;
++ HalDev->TxIntThresholdMaster[Ch] = HalDev->TxIntThreshold[Ch];
++ }
++ }
++ if(Direction == DIRECTION_RX)
++ {
++ rc=OsFunc->DeviceFindParmUint(ChInfo, "RxNumBuffers", &Value);
++ if (!rc) HalDev->ChData[Ch].RxNumBuffers = Value;
++
++ rc=OsFunc->DeviceFindParmUint(ChInfo, "RxBufferOffset", &Value);
++ if (!rc) HalDev->ChData[Ch].RxBufferOffset = Value;
++
++ rc=OsFunc->DeviceFindParmUint(ChInfo, "RxBufSize", &Value);
++ if (!rc) HalDev->ChData[Ch].RxBufSize = Value;
++
++ rc=OsFunc->DeviceFindParmUint(ChInfo, "RxServiceMax", &Value);
++ if (!rc) HalDev->ChData[Ch].RxServiceMax = Value;
++ }
++ return (EC_NO_ERRORS);
++ }
++#define ChannelUpdate(Field) if(HalChn->Field != 0xFFFFFFFF) HalDev->ChData[Ch].Field = HalChn->Field
++
++static void ChannelConfigUpdate(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
++ {
++ int Ch = HalChn->Channel;
++ int Direction = HalChn->Direction;
++#ifdef __CPHAL_DEBUG
++ if (DBG(1))
++ {
++ dbgPrintf("\nChnUpd-HalDev:%08X,Chn:%d:%d\n", (bit32u)HalDev, Ch, Direction); osfuncSioFlush();
++ }
++#endif
++ if (Direction == DIRECTION_TX)
++ {
++ ChannelUpdate(TxNumBuffers);
++ /*ChannelUpdate(TxNumQueues);*/ /*MJH~030329*/
++ ChannelUpdate(TxServiceMax);
++ HalDev->TxIntThreshold[Ch] = HalDev->ChData[Ch].TxServiceMax;
++ HalDev->TxIntThresholdMaster[Ch] = HalDev->TxIntThreshold[Ch];
++ }
++ else
++ if (Direction == DIRECTION_RX)
++ {
++ ChannelUpdate(RxBufferOffset);
++ ChannelUpdate(RxBufSize);
++ ChannelUpdate(RxNumBuffers);
++ ChannelUpdate(RxServiceMax);
++#ifdef __CPHAL_DEBUG
++ if (DBG(1))
++ {
++ dbgPrintf("\nRxNumBuffers %d\n",HalChn->RxNumBuffers); osfuncSioFlush();
++ }
++#endif
++ }
++ }
++static int halChannelSetup(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn, OS_SETUP *OsSetup)
++ {
++ int Direction;
++ int Ch;
++ int rc;
++
++ /* Verify proper device state */
++ if (HalDev->State < enInitialized)
++ return (EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE);
++
++ /* We require the channel structure to be passed, even if it only contains
++ the channel number */
++ if (HalChn == NULL)
++ {
++ return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_NULL_CH_STRUCT);
++ }
++
++ Ch = HalChn->Channel;
++ Direction = HalChn->Direction;
++
++ /* This should check on Maximum Channels for RX or TX,
++ they might be different Mick 021124 */
++ if ((Ch < 0) || (Ch > (MAX_CHAN-1)))
++ {
++ return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_INVALID_CH);
++ }
++
++ /* if channel is already open, this call is invalid */
++ if (HalDev->ChIsOpen[Ch][Direction] == TRUE)
++ {
++ return(EC_CPMAC|EC_FUNC_CHSETUP|EC_VAL_CH_ALREADY_OPEN);
++ }
++
++ /* channel is closed, but might be setup. If so, reopen the hardware channel. */
++ if (HalDev->ChIsSetup[Ch][Direction] == FALSE)
++ {
++ /* Setup channel configuration */
++ HalDev->ChData[Ch].Channel = Ch;
++
++ /* Store OS_SETUP */
++ HalDev->ChData[Ch].OsSetup = OsSetup;
++
++ /* Framework :
++ Set Default Values
++ Update with options.conf
++ Apply driver updates
++ */
++ ChannelConfigInit(HalDev, HalChn);
++ ChannelConfigGet(HalDev, HalChn);
++ ChannelConfigUpdate(HalDev, HalChn);
++
++ /* cppi.c needs to use Rx/TxServiceMax */
++ HalDev->BuffersServicedMax = 169; /* TEMP */
++
++ HalDev->ChIsSetup[Ch][Direction] = TRUE;
++ }
++
++ rc = EC_NO_ERRORS;
++
++ /* If the hardware has been opened (is out of reset), then configure the channel
++ in the hardware. NOTE: ChannelConfigApply calls the CPSAR ChannelSetup()! */
++ if (HalDev->State == enOpened)
++ {
++ rc = ChannelConfigApply(HalDev, HalChn);
++ }
++
++ return (rc);
++ }
++
++
++static int miiInfoGet(HAL_DEVICE *HalDev, bit32u *miiBaseAddress, bit32u *miiResetBit)
++ {
++ int rc;
++ void *DeviceInfo;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++
++ /* Only one instance of cpmdio */
++ rc = OsFunc->DeviceFindInfo(0,"cpmdio",&DeviceInfo); /*~RC3.02*/
++
++ if(rc)
++ return (EC_DEV_CPMDIO|EC_FUNC_OPEN|EC_VAL_DEVICE_NOT_FOUND );
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "base",miiBaseAddress);
++ if(rc)
++ rc=EC_DEV_CPMDIO|EC_FUNC_OPEN|EC_VAL_NO_BASE;
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",miiResetBit);
++ if(rc)
++ rc=EC_DEV_CPMDIO|EC_FUNC_OPEN|EC_VAL_NO_BASE;
++
++
++ /* See if need to make mdio functional in GPIO */
++ gpioCheck(HalDev, DeviceInfo);
++
++ if(DBG(0))
++ dbgPrintf("miiBase: 0x%08X %u\n", *miiBaseAddress, *miiResetBit);
++ return(rc);
++ }
++static void ephyCheck(HAL_DEVICE *HalDev)
++ { /*+RC3.02*/
++ int rc;
++ void *DeviceInfo;
++ int mii_phy;
++ int reset_bit;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++
++ rc = OsFunc->DeviceFindInfo(0,"ephy",&DeviceInfo);
++ if(rc) return;
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "mii_phy",&mii_phy);
++ if(rc) return;
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",&reset_bit);
++ if(rc) return;
++
++ if (HalDev->PhyMask & (1 << mii_phy))
++ {
++ *(volatile bit32u *)(HalDev->ResetBase) |= (1 << reset_bit); /*+RC3.02*/
++ resetWait(HalDev);
++ }
++ } /*+RC3.02*/
++static void AutoNegotiate(HAL_DEVICE *HalDev)
++ {
++ int size;
++ bit32u ModID, RevMaj, RevMin;
++ PHY_DEVICE *PhyDev;
++ bit32u miiBaseAddress;
++ bit32u miiResetBit;
++
++ /* Verify proper device state */
++ if (HalDev->State < enOpened)
++ return;
++
++ miiInfoGet(HalDev, &miiBaseAddress, &miiResetBit);
++
++ cpMacMdioGetVer(miiBaseAddress, &ModID, &RevMaj, &RevMin);
++ if(HalDev->debug)
++ dbgPrintf("Mdio Module Id %d, Version %d.%d\n", ModID, RevMaj, RevMin);
++
++ size = cpMacMdioGetPhyDevSize();
++ PhyDev = (PHY_DEVICE *) HalDev->OsFunc->Malloc( size );
++
++ HalDev->PhyDev = PhyDev;
++
++ ephyCheck(HalDev);
++
++ cpMacMdioInit( PhyDev, miiBaseAddress, HalDev->inst, HalDev->PhyMask, HalDev->MLinkMask, HalDev->MdixMask, HalDev->ResetBase, miiResetBit, HalDev->MdioBusFrequency, HalDev->MdioClockFrequency, HalDev->debug, HalDev); /*MJH~030402*/
++ MdioSetPhyMode(HalDev);
++
++ return;
++ }
++static int halOpen(HAL_DEVICE *HalDev)
++ {
++ unsigned char *MacAddr;
++ int i;
++ int j;
++ int rc, Ticks;
++
++ if (HalDev->debug)
++ {
++ dbgPrintf("halOpen: haldev:0x%08X inst:%d base:0x%08X reset:%d\n", (bit32u) &HalDev, HalDev->inst, HalDev->dev_base, HalDev->ResetBit);
++ osfuncSioFlush();
++ }
++
++ /* Verify proper device state */
++ if (HalDev->State < enInitialized)
++ return (EC_CPMAC|EC_FUNC_OPEN|EC_VAL_INVALID_STATE);
++
++
++ /* take CPMAC out of reset - GSG 11/20*/
++ if ((VOLATILE32(HalDev->ResetBase) & (1 << HalDev->ResetBit)) != 0)
++ {
++ /* perform normal close duties */
++ CPMAC_MACCONTROL(HalDev->dev_base) &= ~MII_EN;
++ CPMAC_TX_CONTROL(HalDev->dev_base) &= ~TX_EN;
++ CPMAC_RX_CONTROL(HalDev->dev_base) &= ~RX_EN;
++
++ /* disable interrupt masks */
++ CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = 0xFF;
++ CPMAC_RX_INTMASK_CLEAR(HalDev->dev_base) = 0xFF;
++ }
++
++ /* take CPMAC out of reset */
++ *(volatile bit32u *)(HalDev->ResetBase) &= ~(1 << HalDev->ResetBit);
++ resetWait(HalDev);
++ *(volatile bit32u *)(HalDev->ResetBase) |= (1 << HalDev->ResetBit);
++ resetWait(HalDev);
++
++ /* After Reset clear the Transmit and Receive DMA Head Descriptor Pointers */
++
++ CPMAC_TX0_HDP(HalDev->dev_base)=0;
++ CPMAC_TX1_HDP(HalDev->dev_base)=0;
++ CPMAC_TX2_HDP(HalDev->dev_base)=0;
++ CPMAC_TX3_HDP(HalDev->dev_base)=0;
++ CPMAC_TX4_HDP(HalDev->dev_base)=0;
++ CPMAC_TX5_HDP(HalDev->dev_base)=0;
++ CPMAC_TX6_HDP(HalDev->dev_base)=0;
++ CPMAC_TX7_HDP(HalDev->dev_base)=0;
++
++ /* Rx Init */
++
++ CPMAC_RX0_HDP(HalDev->dev_base) = 0;
++ CPMAC_RX1_HDP(HalDev->dev_base) = 0;
++ CPMAC_RX2_HDP(HalDev->dev_base) = 0;
++ CPMAC_RX3_HDP(HalDev->dev_base) = 0;
++ CPMAC_RX4_HDP(HalDev->dev_base) = 0;
++ CPMAC_RX5_HDP(HalDev->dev_base) = 0;
++ CPMAC_RX6_HDP(HalDev->dev_base) = 0;
++ CPMAC_RX7_HDP(HalDev->dev_base) = 0;
++
++ CPMAC_RX_BUFFER_OFFSET(HalDev->dev_base) = 0;
++
++ /* Init Tx and Rx DMA */
++
++ CPMAC_TX_CONTROL(HalDev->dev_base) |= TX_EN;
++ CPMAC_RX_CONTROL(HalDev->dev_base) |= RX_EN;
++
++ CPMAC_MAC_INTMASK_SET(HalDev->dev_base) |=2; /* Enable Adaptercheck Ints */
++ HalDev->OsFunc->Control(HalDev->OsDev, pszMacAddr, hcGet, &MacAddr); /* GSG 11/22 */
++ MacAddressSave(HalDev, MacAddr);
++
++ HalDev->HostErr = 0; /* Clear Adapter Check indicator */
++ HalDev->State = enOpened; /* Change device state */
++
++ /* Start MDIO Negotiation */
++ AutoNegotiate(HalDev);
++
++ /* Enable the Os Timer */
++ Ticks = HalDev->CpuFrequency / 100; /* 10 milli-secs */ /*MJH~030402*/
++ HalDev->OsFunc->Control(HalDev->OsDev, pszTick, hcSet, &Ticks); /* GSG 11/22 */
++ HalDev->OsFunc->IsrRegister(HalDev->OsDev, halIsr, HalDev->interrupt);
++
++ /* GSG +030523 Malloc space for the Rx fraglist */
++ HalDev->fraglist = HalDev->OsFunc->Malloc(HalDev->MaxFrags * sizeof(FRAGLIST));
++
++ /* Any pre-open configuration */
++
++ /* For any channels that have been pre-initialized, set them up now */
++ /* Note : This loop should not use MAX_CHN, it should only
++ loop through Channels Setup, memory should not be reserved
++ until Channel is Setup
++ */
++ for(i=0; i<MAX_CHAN; i++) /* i loops through Channels */
++ for(j=0; j<2; j++) /* j loops through DIRECTION values, 0 and 1 */
++ {
++ if(HalDev->ChIsSetup[i][j]==TRUE) /* If the Channel and Direction have been Setup */
++ if(HalDev->ChIsOpen[i][j]==FALSE) /* but not opened, then Apply Values now */
++ {
++ CHANNEL_INFO HalChn;
++ HalChn.Channel = i;
++ HalChn.Direction = j;
++ rc = ChannelConfigApply(HalDev, &HalChn);
++ if(rc != EC_NO_ERRORS)
++ return(rc);
++ }
++ } /* End of looping through Channel/Direction */
++
++ ConfigApply(HalDev); /* Apply Configuration Values to Device */
++ CPMAC_MACCONTROL(HalDev->dev_base) |= MII_EN; /* MAC_EN */
++ if(DBG(0))
++ dbgPrintf("[halOpen]MacControl:%08X\n", CPMAC_MACCONTROL(HalDev->dev_base));
++ return(EC_NO_ERRORS);
++ }
++
++#define INT_PENDING (MAC_IN_VECTOR_TX_INT_OR | MAC_IN_VECTOR_RX_INT_OR | MAC_IN_VECTOR_HOST_INT)
++static int halShutdown(HAL_DEVICE *HalDev)
++ {
++ int Ch, Queue; /*GSG+030514*/
++
++ /* Verify proper device state */
++ if (HalDev->State == enOpened)
++ halClose(HalDev, 3); /* GSG ~030429 */
++
++ /* Buffer/descriptor resources may still need to be freed if a Close
++ Mode 1 was performed prior to Shutdown - clean up here */ /*GSG+030514*/
++ for (Ch=0; Ch<MAX_CHAN; Ch++)
++ {
++ if (HalDev->RcbStart[Ch] != 0)
++ FreeRx(HalDev,Ch);
++
++ for(Queue=0; Queue<MAX_QUEUE; Queue++)
++ {
++ if (HalDev->TcbStart[Ch][Queue] != 0)
++ FreeTx(HalDev,Ch,Queue);
++ }
++ }
++
++ /* free the HalFunc */
++ HalDev->OsFunc->Free(HalDev->HalFuncPtr);
++
++ /* free the HAL device */
++ HalDev->OsFunc->Free(HalDev);
++
++ return(EC_NO_ERRORS);
++ }
++int halIsr(HAL_DEVICE *HalDev, int *MorePackets)
++{
++ bit32u IntVec;
++ int Serviced;
++ int PacketsServiced=0;
++ int Channel;
++ int TxMorePackets=0;
++ int RxMorePackets=0;
++
++ /* Verify proper device state - important because a call prior to Open would
++ result in a lockup */
++ if (HalDev->State != enOpened)
++ return(EC_CPMAC|EC_FUNC_DEVICE_INT|EC_VAL_INVALID_STATE);
++
++ IntVec = CPMAC_MAC_IN_VECTOR(HalDev->dev_base);
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("\nhalIsr: inst %d, IntVec 0x%X\n", HalDev->inst, IntVec); osfuncSioFlush();/* GSG 11/22 */
++ }
++#endif
++
++ HalDev->IntVec = IntVec;
++ if (IntVec & MAC_IN_VECTOR_TX_INT_OR)
++ {
++ int TxServiceMax=0; /* Compiler complains if not initialized */
++
++ Channel = (IntVec & 0x7);
++
++ if(HalDev->TxIntDisable)
++ {
++ CPMAC_TX_INTMASK_CLEAR(HalDev->dev_base) = (1<<Channel); /* Disable Interrupt for Channel */
++ TxServiceMax = HalDev->ChData[Channel].TxServiceMax;
++ HalDev->ChData[Channel].TxServiceMax = 10000; /* Need to service all packets in the Queue */
++ }
++
++ PacketsServiced |= TxInt(HalDev, Channel, 0, &TxMorePackets);
++
++ if(HalDev->TxIntDisable)
++ HalDev->ChData[Channel].TxServiceMax = TxServiceMax;
++ }
++
++ if (IntVec & MAC_IN_VECTOR_RX_INT_OR)
++ {
++ Channel = (IntVec >> 8) & 0x7;
++ Serviced = RxInt(HalDev, Channel, &RxMorePackets);
++ PacketsServiced |= (Serviced<<16);
++ }
++
++ if (IntVec & MAC_IN_VECTOR_HOST_INT)
++ {
++ /* Adaptercheck */
++ HalDev->HostErr = 1;
++ HalDev->MacStatus = CPMAC_MACSTATUS(HalDev->dev_base);
++ osfuncStateChange(); /*MJH+030328*/
++ if(DBG(0))
++ {
++ dbgPrintf("Adaptercheck: %08x for base:%X\n",HalDev->MacStatus, (bit32u)HalDev->dev_base);
++ osfuncSioFlush();
++ }
++ }
++ *MorePackets = (TxMorePackets | RxMorePackets);
++ return (PacketsServiced);
++}
++
++int halPacketProcessEnd(HAL_DEVICE *HalDev)
++{
++ int base = HalDev->dev_base;
++ CPMAC_MAC_EOI_VECTOR(base) = 0;
++ return(0);
++}
++
++
++
++static int PhyCheck(HAL_DEVICE *HalDev)
++ {
++ return(cpMacMdioTic(HalDev->PhyDev));
++ }
++static int halTick(HAL_DEVICE *HalDev)
++{
++ int TickChange;
++
++ if(HalDev->State < enOpened)
++ return (EC_CPMAC|EC_FUNC_TICK|EC_VAL_INVALID_STATE);
++
++ /* if NO Phy no need to check Link */
++ if(HalDev->MdioConnect & _CPMDIO_NOPHY)
++ return(EC_NO_ERRORS); /* No change in Phy State detected */
++
++ TickChange = PhyCheck(HalDev);
++ /* Phy State Change Detected */
++ if(TickChange == 1)
++ {
++ /* MDIO indicated a change */
++ DuplexUpdate(HalDev);
++ osfuncStateChange();
++ return(EC_NO_ERRORS);
++ }
++
++ /* if in AutoMdix mode, and Flip request received, inform OS */
++ if( (HalDev->MdioConnect & _CPMDIO_AUTOMDIX) &&
++ (TickChange & _MIIMDIO_MDIXFLIP))
++ {
++ bit32u Mdix;
++ Mdix = TickChange & 0x1; /* Mdix mode stored in bit 0 */
++ HalDev->OsFunc->Control(HalDev->OsDev, hcMdioMdixSwitch, hcSet, &Mdix);
++ return(EC_NO_ERRORS);
++ }
++
++ return(EC_NO_ERRORS);
++}
++
++int halCpmacInitModule(HAL_DEVICE **pHalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS **pHalFunc,
++ OS_FUNCTIONS *OsFunc, int OsFuncSize, int *HalFuncSize, int Inst)
++ {
++ HAL_DEVICE *HalDev;
++ HAL_FUNCTIONS *HalFunc;
++
++ if (OsFuncSize < sizeof(OS_FUNCTIONS))
++ return (EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_OS_VERSION_NOT_SUPPORTED);
++
++ HalDev = (HAL_DEVICE *) OsFunc->MallocDev(sizeof(HAL_DEVICE));
++ if (!HalDev)
++ return (EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_DEV_FAILED);
++
++ /* clear the HalDev area */
++ OsFunc->Memset(HalDev, 0, sizeof(HAL_DEVICE));
++
++ /* Initialize the size of hal functions */
++ *HalFuncSize = sizeof (HAL_FUNCTIONS);
++
++ HalFunc = (HAL_FUNCTIONS *) OsFunc->Malloc(sizeof(HAL_FUNCTIONS));
++ if (!HalFunc)
++ return (EC_CPMAC|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_FAILED);
++
++ /* clear the function pointers */
++ OsFunc->Memset(HalFunc, 0, sizeof(HAL_FUNCTIONS));
++
++ HalDev->OsDev = OsDev;
++ HalDev->OsOpen = OsDev;
++ HalDev->inst = Inst;
++ HalDev->OsFunc = OsFunc;
++ HalDev->HalFunc = HalFunc;
++ /* Remove the following from cppi, replace with HalFunc */
++ HalDev->HalFuncPtr = HalFunc; /* GSG 11/20 changed name to match cppi */
++
++ /****************************************************************/
++ /* POPULATE HALFUNC */
++ /****************************************************************/
++ HalFunc->ChannelSetup = halChannelSetup;
++ HalFunc->ChannelTeardown = halChannelTeardown; /* GSG 11/20 */
++ HalFunc->Close = halClose; /* GSG 11/20 */
++ HalFunc->Control = halControl; /* GSG 11/22 */
++ HalFunc->Init = halInit;
++ HalFunc->Open = halOpen;
++ HalFunc->PacketProcessEnd = halPacketProcessEnd;
++ HalFunc->Probe = halProbe;
++ HalFunc->RxReturn = halRxReturn;
++ HalFunc->Send = halSend;
++ HalFunc->Shutdown = halShutdown;
++ HalFunc->Tick = halTick;
++
++ /* HalFunc->Status = halStatus;*/ /* GSG 11/22 */
++ /* pass the HalDev and HalFunc back to the caller */
++
++ *pHalDev = HalDev;
++ *pHalFunc = HalFunc;
++
++ HalDev->State = enConnected; /* Initialize the hardware state */
++
++ if (HalDev->debug) HalDev->OsFunc->Printf("halCpmacInitModule: Leave\n");
++ return(0);
++ }
++
++int cpmacRandomRange(HAL_DEVICE *HalDev, int min, int max)
++{
++ int iTmp;
++ iTmp = cpmacRandom(HalDev);
++ iTmp %= ((max-min)+1);
++ iTmp += min;
++ return(iTmp);
++}
++
++int cpmacRandom(HAL_DEVICE *HalDev)
++{
++ int iTmp;
++ iTmp = CPMAC_BOFFTEST(HalDev->dev_base);
++ iTmp >>= 16; /* get rndnum field */
++ iTmp &= (0x3FF); /* field is 10 bits wide */
++ return(iTmp);
++}
+diff -urN linux.old/drivers/net/avalanche_cpmac/hcpmac.h linux.dev/drivers/net/avalanche_cpmac/hcpmac.h
+--- linux.old/drivers/net/avalanche_cpmac/hcpmac.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/hcpmac.h 2005-07-12 02:48:42.175574000 +0200
+@@ -0,0 +1,383 @@
++/** @file***********************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE:
++ *
++ * DESCRIPTION:
++ * This file contains definitions for the HAL EMAC API
++ *
++ * HISTORY:
++ * xxXxx01 Denis 1.00 Original Version created.
++ * 22Jan02 Denis/Mick 1.01 Modified for HAL EMAC API
++ * 24Jan02 Denis/Mick 1.02 Speed Improvements
++ * 28Jan02 Denis/Mick 1.16 Made function calls pointers
++ * 28Jan02 Mick 1.18 Split into separate modules
++ * @author Michael Hanrahan
++ * @version 1.02
++ * @date 24-Jan-2002
++ *****************************************************************************/
++#ifndef _INC_HCPMAC
++#define _INC_HCPMAC
++
++/** \namespace CPMAC_Version
++This documents version 01.07.04 of the CPMAC CPHAL.
++*/
++const char *pszVersion_CPMAC="CPMAC 01.07.08 "__DATE__" "__TIME__;
++
++/* CHECK THESE LOCATIONS */
++#define TEARDOWN_VAL 0xfffffffc
++#define CB_OFFSET_MASK 0xFFFF0000
++
++
++#define MAX_CHAN 8
++#define MAX_QUEUE 1
++
++typedef struct
++ {
++ bit32 HNext; /*< Hardware's pointer to next buffer descriptor */
++ bit32 BufPtr; /*< Pointer to the data buffer */
++ bit32 Off_BLen; /*< Contains buffer offset and buffer length */
++ bit32 mode; /*< SOP, EOP, Ownership, EOQ, Teardown, Q Starv, Length */
++ void *Next;
++ void *OsInfo;
++ void *Eop;
++#ifdef __CPHAL_DEBUG
++ bit32 DbgSop;
++ bit32 DbgData;
++ bit32 DbgFraglist;
++#endif
++ }HAL_TCB;
++
++typedef volatile struct hal_private
++ {
++ bit32 HNext; /*< Hardware's pointer to next buffer descriptor */
++ bit32 BufPtr; /*< Pointer to the data buffer */
++ bit32 Off_BLen; /*< Contains buffer offset and buffer length */
++ bit32 mode; /*< SOP, EOP, Ownership, EOQ, Teardown Complete bits */
++ void *DatPtr;
++ void *Next;
++ void *OsInfo;
++ void *Eop;
++ }HAL_RCB;
++
++#define MAX_NEEDS 512 /*MJH+030409*/
++/* HAL */
++
++typedef struct hal_device
++ {
++ OS_DEVICE *OsDev;
++ OS_FUNCTIONS *OsFunc;
++ /*OS_SETUP *OsSetup;*/ /* -GSG 030508 */
++ int inst;
++ bit32u rxbufseq;
++
++
++ bit32 dev_base;
++ bit32 offset;
++
++ bit32u ResetBase; /* GSG 10/20 */
++ int ResetBit;
++ void *OsOpen;
++ bit32u IntVec;
++ PHY_DEVICE *PhyDev;
++ bit32u EmacDuplex;
++ bit32u EmacSpeed;
++ bit32u PhyNum;
++ bit32u MLinkMask;
++ bit32u PhyMask;
++ bit32u MdixMask;
++
++ bit32u Linked;
++ DEVICE_STATE State;
++ unsigned char *MacAddr;
++ HAL_FUNCTIONS *HalFuncPtr; /* GSG 11/20 changed name to match cppi */
++ HAL_FUNCTIONS *HalFunc;
++/* unsigned int CpuFreq;*/ /*MJH-030402*/
++ unsigned int MdioConnect;
++ unsigned int HostErr;
++
++/************************************************************************/
++/* */
++/* R E G I S T E R S */
++/* */
++/************************************************************************/
++
++ bit32u RxMbpEnable;
++ bit32u RxUnicastSet;
++ bit32u RxUnicastClear;
++ bit32u RxMaxLen;
++ bit32u RxFilterLowThresh;
++ bit32u Rx0FlowThresh;
++ bit32u MacControl;
++ bit32u MacStatus;
++ bit32u MacHash1;
++ bit32u MacHash2;
++
++/************************************************************************/
++/* */
++/* O P T I O N S */
++/* */
++/************************************************************************/
++
++ char *DeviceInfo;
++ bit32u interrupt;
++
++
++ bit32u RxPassCrc;
++ bit32u RxCaf;
++ bit32u RxCef;
++ bit32u RxBcast;
++ bit32u RxBcastCh;
++ HAL_RCB *RcbPool[MAX_CHAN];
++ bit32 RxActQueueCount[MAX_CHAN];
++ HAL_RCB *RxActQueueHead[MAX_CHAN];
++ HAL_RCB *RxActQueueTail[MAX_CHAN];
++ bit32 RxActive[MAX_CHAN];
++ HAL_TCB *TcbPool[MAX_CHAN][MAX_QUEUE];
++ bit32 TxActQueueCount[MAX_CHAN][MAX_QUEUE];
++ HAL_TCB *TxActQueueHead[MAX_CHAN][MAX_QUEUE];
++ HAL_TCB *TxActQueueTail[MAX_CHAN][MAX_QUEUE];
++ bit32 TxActive[MAX_CHAN][MAX_QUEUE];
++ bit32 TxTeardownPending[MAX_CHAN];
++ bit32 RxTeardownPending[MAX_CHAN];
++ bit32 ChIsOpen[MAX_CHAN][2];
++ bit32 ChIsSetup[MAX_CHAN][2];
++ FRAGLIST *fraglist;
++ char *TcbStart[MAX_CHAN][MAX_QUEUE];
++ char *RcbStart[MAX_CHAN];
++ bit32 RcbSize[MAX_CHAN];
++/* STAT_INFO Stats; */
++ bit32 Inst;
++ bit32u BuffersServicedMax;
++ CHANNEL_INFO ChData[MAX_CHAN];
++ bit32u MdioClockFrequency; /*MJH+030402*/
++ bit32u MdioBusFrequency; /*MJH+030402*/
++ bit32u CpuFrequency; /*MJH+030402*/
++ bit32u CpmacFrequency; /*MJH+030403*/
++ bit32u CpmacSize; /*MJH+030425*/
++ int debug;
++ bit32u NeedsCount; /*MJH+030409*/
++ HAL_RECEIVEINFO *Needs[MAX_NEEDS]; /*MJH+030409*/
++ int MaxFrags;
++ int TxIntThreshold[MAX_CHAN]; /* MJH 040621 NSP Performance Update */
++ int TxIntThresholdMaster[MAX_CHAN]; /* MJH 040827 NSP Performance Update */
++ int TxIntDisable; /* MJH 040621 NSP Performance Update */
++ }HALDEVICE;
++
++#define STATS_MAX 36
++
++#define MACCONTROL_MASK (TX_PTYPE|TX_PACE|TX_FLOW_EN|RX_FLOW_EN|CTRL_LOOPBACK)
++#define RX_MBP_ENABLE_MASK \
++ (RX_PASS_CRC|RX_QOS_EN|RX_NO_CHAIN| \
++ RX_CMF_EN|RX_CSF_EN|RX_CEF_EN|RX_CAF_EN|RX_PROM_CH_MASK| \
++ RX_BROAD_EN|RX_BROAD_CH_MASK|RX_MULT_EN|RX_MULT_CH_MASK)
++
++
++#define MBP_UPDATE(Mask, On) \
++ if(On) HalDev->RxMbpEnable |= Mask; \
++ else HalDev->RxMbpEnable &= ~Mask
++
++#define CONTROL_UPDATE(Mask, On) \
++ if(On) HalDev->MacControl |= Mask; \
++ else HalDev->MacControl &= ~Mask
++
++
++#define UPDATE_TX_PTYPE(Value) CONTROL_UPDATE(TX_PTYPE,Value)
++#define UPDATE_TX_PACE(Value) CONTROL_UPDATE(TX_PACE,Value)
++#define UPDATE_MII_EN(Value) CONTROL_UPDATE(MII_EN,Value)
++#define UPDATE_TX_FLOW_EN(Value) CONTROL_UPDATE(TX_FLOW_EN,Value)
++#define UPDATE_RX_FLOW_EN(Value) CONTROL_UPDATE(RX_FLOW_EN,Value)
++#define UPDATE_CTRL_LOOPBACK(Value) CONTROL_UPDATE(CTRL_LOOPBACK,Value)
++#define UPDATE_FULLDUPLEX(Value) CONTROL_UPDATE(FULLDUPLEX,(Value))
++
++#define UPDATE_RX_PASS_CRC(Value) MBP_UPDATE(RX_PASS_CRC, Value)
++#define UPDATE_RX_QOS_EN(Value) MBP_UPDATE(RX_QOS_EN, Value)
++#define UPDATE_RX_NO_CHAIN(Value) MBP_UPDATE(RX_NO_CHAIN, Value)
++#define UPDATE_RX_CMF_EN(Value) MBP_UPDATE(RX_CMF_EN, Value)
++#define UPDATE_RX_CSF_EN(Value) MBP_UPDATE(RX_CSF_EN, Value)
++#define UPDATE_RX_CEF_EN(Value) MBP_UPDATE(RX_CEF_EN, Value)
++#define UPDATE_RX_CAF_EN(Value) MBP_UPDATE(RX_CAF_EN, Value)
++#define UPDATE_RX_BROAD_EN(Value) MBP_UPDATE(RX_BROAD_EN, Value)
++#define UPDATE_RX_MULT_EN(Value) MBP_UPDATE(RX_MULT_EN, Value)
++
++#define UPDATE_RX_PROM_CH(Value) \
++ HalDev->RxMbpEnable &= ~RX_PROM_CH_MASK; \
++ HalDev->RxMbpEnable |= RX_PROM_CH(Value)
++
++#define UPDATE_RX_BROAD_CH(Value) \
++ HalDev->RxMbpEnable &= ~RX_BROAD_CH_MASK; \
++ HalDev->RxMbpEnable |= RX_BROAD_CH(Value)
++
++#define UPDATE_RX_MULT_CH(Value) \
++ HalDev->RxMbpEnable &= ~RX_MULT_CH_MASK; \
++ HalDev->RxMbpEnable |= RX_MULT_CH(Value)
++
++
++
++typedef enum
++ {
++ /* CPMAC */
++ enCpmacStart=0,
++ enStats0,
++ enStats1,
++ enStats2,
++ enStats3,
++ enStats4,
++ enStatsDump,
++ enStatsClear,
++ enRX_PASS_CRC,
++ enRX_QOS_EN,
++ enRX_NO_CHAIN,
++ enRX_CMF_EN,
++ enRX_CSF_EN,
++ enRX_CEF_EN,
++ enRX_CAF_EN,
++ enRX_PROM_CH,
++ enRX_BROAD_EN,
++ enRX_BROAD_CH,
++ enRX_MULT_EN,
++ enRX_MULT_CH,
++
++ enTX_PTYPE,
++ enTX_PACE,
++ enMII_EN,
++ enTX_FLOW_EN,
++ enRX_FLOW_EN,
++ enCTRL_LOOPBACK,
++
++ enRX_MAXLEN,
++ enRX_FILTERLOWTHRESH,
++ enRX0_FLOWTHRESH,
++ enRX_UNICAST_SET,
++ enRX_UNICAST_CLEAR,
++ enMdioConnect,
++ enMAC_ADDR_GET,
++ enTick,
++ enRX_MULTICAST,
++ enRX_MULTI_ALL,
++ enRX_MULTI_SINGLE,
++ enVersion,
++ enCpmacEnd /* Last entry */
++ }INFO_KEY_CPMAC;
++
++static const char pszVersion[] = "Version";
++static const char pszStats0[] = "Stats0";
++static const char pszStats1[] = "Stats1";
++static const char pszStats2[] = "Stats2";
++static const char pszStats3[] = "Stats3";
++static const char pszStats4[] = "Stats4";
++static const char pszStatsDump[] = "StatsDump";
++static const char pszStatsClear[] = "StatsClear";
++
++/********************************************************************
++**
++** RX MBP ENABLE
++**
++********************************************************************/
++static const char pszRX_PASS_CRC[] = "RX_PASS_CRC";
++static const char pszRX_QOS_EN[] = "RX_QOS_EN";
++static const char pszRX_NO_CHAIN[] = "RX_NO_CHAIN";
++static const char pszRX_CMF_EN[] = "RX_CMF_EN";
++static const char pszRX_CSF_EN[] = "RX_CSF_EN";
++static const char pszRX_CEF_EN[] = "RX_CEF_EN";
++static const char pszRX_CAF_EN[] = "RX_CAF_EN";
++static const char pszRX_PROM_CH[] = "RX_PROM_CH";
++static const char pszRX_BROAD_EN[] = "RX_BROAD_EN";
++static const char pszRX_BROAD_CH[] = "RX_BROAD_CH";
++static const char pszRX_MULT_EN[] = "RX_MULT_EN";
++static const char pszRX_MULT_CH[] = "RX_MULT_CH";
++
++
++/********************************************************************
++**
++** MAC CONTROL
++**
++********************************************************************/
++static const char pszTX_PTYPE[] = "TX_PTYPE";
++static const char pszTX_PACE[] = "TX_PACE";
++static const char pszMII_EN[] = "MII_EN";
++static const char pszTX_FLOW_EN[] = "TX_FLOW_EN";
++static const char pszRX_FLOW_EN[] = "RX_FLOW_EN";
++static const char pszCTRL_LOOPBACK[] = "CTRL_LOOPBACK";
++
++static const char pszRX_MAXLEN[] = "RX_MAXLEN";
++static const char pszRX_FILTERLOWTHRESH[] = "RX_FILTERLOWTHRESH";
++static const char pszRX0_FLOWTHRESH[] = "RX0_FLOWTHRESH";
++static const char pszRX_UNICAST_SET[] = "RX_UNICAST_SET";
++static const char pszRX_UNICAST_CLEAR[] = "RX_UNICAST_CLEAR";
++static const char pszMdioConnect[] = "MdioConnect";
++static const char pszMacAddr[] = "MacAddr";
++static const char pszTick[] = "Tick";
++
++/********************************************************************
++**
++** MULTICAST
++**
++********************************************************************/
++
++static const char pszRX_MULTICAST[] = "RX_MULTICAST";
++static const char pszRX_MULTI_ALL[] = "RX_MULTI_ALL";
++static const char pszRX_MULTI_SINGLE[] = "RX_MULTI_SINGLE";
++
++/*
++static const char* pszGFHN = "GFHN";
++*/
++
++static const CONTROL_KEY KeyCpmac[] =
++ {
++ {"" , enCpmacStart},
++ {pszStats0 , enStats0},
++ {pszStats1 , enStats1},
++ {pszStats2 , enStats2},
++ {pszStats3 , enStats3},
++ {pszStats4 , enStats4},
++ {pszStatsClear , enStatsClear},
++ {pszStatsDump , enStatsDump},
++ {pszRX_PASS_CRC , enRX_PASS_CRC},
++ {pszRX_QOS_EN , enRX_QOS_EN},
++ {pszRX_NO_CHAIN , enRX_NO_CHAIN},
++ {pszRX_CMF_EN , enRX_CMF_EN},
++ {pszRX_CSF_EN , enRX_CSF_EN},
++ {pszRX_CEF_EN , enRX_CEF_EN},
++ {pszRX_CAF_EN , enRX_CAF_EN},
++ {pszRX_PROM_CH , enRX_PROM_CH},
++ {pszRX_BROAD_EN , enRX_BROAD_EN},
++ {pszRX_BROAD_CH , enRX_BROAD_CH},
++ {pszRX_MULT_EN , enRX_MULT_EN},
++ {pszRX_MULT_CH , enRX_MULT_CH},
++
++ {pszTX_PTYPE , enTX_PTYPE},
++ {pszTX_PACE , enTX_PACE},
++ {pszMII_EN , enMII_EN},
++ {pszTX_FLOW_EN , enTX_FLOW_EN},
++ {pszRX_FLOW_EN , enRX_FLOW_EN},
++ {pszCTRL_LOOPBACK , enCTRL_LOOPBACK},
++ {pszRX_MAXLEN , enRX_MAXLEN},
++ {pszRX_FILTERLOWTHRESH , enRX_FILTERLOWTHRESH},
++ {pszRX0_FLOWTHRESH , enRX0_FLOWTHRESH},
++ {pszRX_UNICAST_SET , enRX_UNICAST_SET},
++ {pszRX_UNICAST_CLEAR , enRX_UNICAST_CLEAR},
++ {pszMdioConnect , enMdioConnect},
++ {pszRX_MULTICAST , enRX_MULTICAST},
++ {pszRX_MULTI_ALL , enRX_MULTI_ALL},
++ {pszRX_MULTI_SINGLE , enRX_MULTI_SINGLE},
++ {pszTick , enTick},
++ {pszVersion , enVersion},
++ {"" , enCpmacEnd}
++ };
++
++const char hcCpuFrequency[] = "CpuFreq";
++const char hcCpmacFrequency[] = "CpmacFrequency";
++const char hcMdioBusFrequency[] = "MdioBusFrequency";
++const char hcMdioClockFrequency[] = "MdioClockFrequency";
++const char hcCpmacBase[] = "CpmacBase";
++const char hcPhyNum[] = "PhyNum";
++const char hcSize[] = "size";
++const char hcCpmacSize[] = "CpmacSize";
++const char hcPhyAccess[] = "PhyAccess";
++const char hcLinked[] = "Linked";
++const char hcFullDuplex[] = "FullDuplex";
++const char hcMdixMask[] = "MdixMask";
++const char hcMdioMdixSwitch[] = "MdixSet";
++#endif
+diff -urN linux.old/drivers/net/avalanche_cpmac/Makefile linux.dev/drivers/net/avalanche_cpmac/Makefile
+--- linux.old/drivers/net/avalanche_cpmac/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/Makefile 2005-07-12 02:48:42.175574000 +0200
+@@ -0,0 +1,26 @@
++# File: drivers/net/avalanche_cpmac/Makefile
++#
++# Makefile for the Linux network (CPMAC) device drivers.
++#
++
++O_TARGET := avalanche_cpmac.o
++
++
++list-multi := avalanche_cpmac.o
++obj-$(CONFIG_MIPS_AVALANCHE_CPMAC) := avalanche_cpmac.o
++
++avalanche_cpmac-objs += cpmac.o cpmacHalLx.o hcpmac.o \
++ psp_config_build.o psp_config_mgr.o \
++ psp_config_parse.o psp_config_util.o
++
++
++include $(TOPDIR)/Rules.make
++
++
++avalanche_cpmac.o: $(avalanche_cpmac-objs)
++ $(LD) -r -o $@ $(avalanche_cpmac-objs)
++
++
++
++clean:
++ rm -f core *.o *.a *.s
+diff -urN linux.old/drivers/net/avalanche_cpmac/mdio_reg.h linux.dev/drivers/net/avalanche_cpmac/mdio_reg.h
+--- linux.old/drivers/net/avalanche_cpmac/mdio_reg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/mdio_reg.h 2005-07-12 02:48:42.176573000 +0200
+@@ -0,0 +1,121 @@
++/****************************************************************************
++** TNETD53xx Software Support
++** Copyright(c) 2002, Texas Instruments Incorporated. All Rights Reserved.
++**
++** FILE: mdio_reg.h Register definitions for the VBUS MII module
++**
++** DESCRIPTION:
++** This include file contains register definitions for the
++** VBUS MII module.
++**
++** HISTORY:
++** 27Mar02 Michael Hanrahan Original (modified from emacmdio.h)
++** 01Apr02 Michael Hanrahan Modified to include all regs. in spec
++** 03Apr02 Michael Hanrahan Updated to Version 0.6 of spec
++** 05Apr02 Michael Hanrahan Moved Phy Mode values into here
++** 30Apr02 Michael Hanrahan Updated to Version 0.8 of spec
++** 30Apr02 Michael Hanrahan Updated to recommended format
++** 10May02 Michael Hanrahan Updated to Version 0.9 of spec
++*****************************************************************************/
++#ifndef _INC_MDIO_REG
++#define _INC_MDIO_REG
++
++/***************************************************************************
++**
++** M D I O M E M O R Y M A P
++**
++***************************************************************************/
++
++
++#define pMDIO_VER(base) ((volatile bit32u *)(base+0x00))
++#define pMDIO_CONTROL(base) ((volatile bit32u *)(base+0x04))
++#define pMDIO_ALIVE(base) ((volatile bit32u *)(base+0x08))
++#define pMDIO_LINK(base) ((volatile bit32u *)(base+0x0C))
++#define pMDIO_LINKINTRAW(base) ((volatile bit32u *)(base+0x10))
++#define pMDIO_LINKINTMASKED(base) ((volatile bit32u *)(base+0x14))
++#define pMDIO_USERINTRAW(base) ((volatile bit32u *)(base+0x20))
++#define pMDIO_USERINTMASKED(base) ((volatile bit32u *)(base+0x24))
++#define pMDIO_USERINTMASKED_SET(base) ((volatile bit32u *)(base+0x28))
++#define pMDIO_USERINTMASKED_CLR(base) ((volatile bit32u *)(base+0x2C))
++#define pMDIO_USERACCESS(base, channel) ((volatile bit32u *)(base+(0x80+(channel*8))))
++#define pMDIO_USERPHYSEL(base, channel) ((volatile bit32u *)(base+(0x84+(channel*8))))
++
++
++/***************************************************************************
++**
++** M D I O R E G I S T E R A C C E S S M A C R O S
++**
++***************************************************************************/
++
++
++#define MDIO_ALIVE(base) (*(pMDIO_ALIVE(base)))
++#define MDIO_CONTROL(base) (*(pMDIO_CONTROL(base)))
++#define MDIO_CONTROL_IDLE (1 << 31)
++#define MDIO_CONTROL_ENABLE (1 << 30)
++#define MDIO_CONTROL_PREAMBLE (1 << 20)
++#define MDIO_CONTROL_FAULT (1 << 19)
++#define MDIO_CONTROL_FAULT_DETECT_ENABLE (1 << 18)
++#define MDIO_CONTROL_INT_TEST_ENABLE (1 << 17)
++#define MDIO_CONTROL_HIGHEST_USER_CHANNEL (0x1F << 8)
++#define MDIO_CONTROL_CLKDIV (0xFF)
++#define MDIO_LINK(base) (*(pMDIO_LINK(base)))
++#define MDIO_LINKINTRAW(base) (*(pMDIO_LINKINTRAW(base)))
++#define MDIO_LINKINTMASKED(base) (*(pMDIO_LINKINTMASKED(base)))
++#define MDIO_USERINTRAW(base) (*(pMDIO_USERINTRAW(base)))
++#define MDIO_USERINTMASKED(base) (*(pMDIO_USERINTMASKED(base)))
++#define MDIO_USERINTMASKED_CLR(base) (*(pMDIO_USERINTMASKED_CLR(base)))
++#define MDIO_USERINTMASKED_SET(base) (*(pMDIO_USERINTMASKED_SET(base)))
++#define MDIO_USERINTRAW(base) (*(pMDIO_USERINTRAW(base)))
++#define MDIO_USERACCESS(base, channel) (*(pMDIO_USERACCESS(base, channel)))
++#define MDIO_USERACCESS_GO (1 << 31)
++#define MDIO_USERACCESS_WRITE (1 << 30)
++#define MDIO_USERACCESS_READ (0 << 30)
++#define MDIO_USERACCESS_ACK (1 << 29)
++#define MDIO_USERACCESS_REGADR (0x1F << 21)
++#define MDIO_USERACCESS_PHYADR (0x1F << 16)
++#define MDIO_USERACCESS_DATA (0xFFFF)
++#define MDIO_USERPHYSEL(base, channel) (*(pMDIO_USERPHYSEL(base, channel)))
++#define MDIO_USERPHYSEL_LINKSEL (1 << 7)
++#define MDIO_USERPHYSEL_LINKINT_ENABLE (1 << 6)
++#define MDIO_USERPHYSEL_PHYADR_MON (0x1F)
++#define MDIO_VER(base) (*(pMDIO_VER(base)))
++#define MDIO_VER_MODID (0xFFFF << 16)
++#define MDIO_VER_REVMAJ (0xFF << 8)
++#define MDIO_VER_REVMIN (0xFF)
++
++
++
++
++/****************************************************************************/
++/* */
++/* P H Y R E G I S T E R D E F I N I T I O N S */
++/* */
++/****************************************************************************/
++
++
++#define PHY_CONTROL_REG 0
++ #define PHY_RESET (1<<15)
++ #define PHY_LOOP (1<<14)
++ #define PHY_100 (1<<13)
++ #define AUTO_NEGOTIATE_EN (1<<12)
++ #define PHY_PDOWN (1<<11)
++ #define PHY_ISOLATE (1<<10)
++ #define RENEGOTIATE (1<<9)
++ #define PHY_FD (1<<8)
++
++#define PHY_STATUS_REG 1
++ #define NWAY_COMPLETE (1<<5)
++ #define NWAY_CAPABLE (1<<3)
++ #define PHY_LINKED (1<<2)
++
++#define NWAY_ADVERTIZE_REG 4
++#define NWAY_REMADVERTISE_REG 5
++ #define NWAY_FD100 (1<<8)
++ #define NWAY_HD100 (1<<7)
++ #define NWAY_FD10 (1<<6)
++ #define NWAY_HD10 (1<<5)
++ #define NWAY_SEL (1<<0)
++ #define NWAY_AUTO (1<<0)
++
++
++#endif _INC_MDIO_REG
+diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_build.c linux.dev/drivers/net/avalanche_cpmac/psp_config_build.c
+--- linux.old/drivers/net/avalanche_cpmac/psp_config_build.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/psp_config_build.c 2005-07-12 02:48:42.176573000 +0200
+@@ -0,0 +1,335 @@
++/******************************************************************************
++ * FILE PURPOSE: PSP Config Manager - Configuration Build Source
++ ******************************************************************************
++ * FILE NAME: psp_config_build.c
++ *
++ * DESCRIPTION: Configuration Build API Implementation
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++#ifdef INCLUDE_FFS
++#include "ffs.h"
++#endif /* INCLUDE_FFS */
++
++#include "psp_config_mgr.h"
++#include "psp_config_build.h"
++#include "psp_config_util.h"
++
++#define MAX_DEVICE_NAME_LEN 16
++#define MAX_DEVICE_STR_LEN 512
++
++#ifndef NULL
++#define NULL (char *)0
++#endif
++
++#include <asm/ar7/sangam.h>
++#include <linux/slab.h>
++#include <linux/config.h>
++
++
++#define os_malloc(size) kmalloc(size, GFP_KERNEL)
++
++int psp_run_enumerator(void)
++{
++ return(0);
++}
++
++#if defined (CONFIG_AVALANCHE_CPMAC_AUTO)
++
++static int auto_detect_cpmac_phy(void)
++{
++
++#define SELECT_INT_PHY_MAC 0
++#define SELECT_EXT_PHY_MAC 1
++
++ volatile unsigned long *reset_cntl = AVALANCHE_RESET_CONTROL_BASE, *mdio_cntl = ((int)AVALANCHE_MDIO_BASE + 0x4);
++ unsigned int j= 0, detected_phy_map = 0, auto_select = SELECT_INT_PHY_MAC;
++
++ *reset_cntl |= (1 << AVALANCHE_MDIO_RESET_BIT) | (1 << AVALANCHE_LOW_CPMAC_RESET_BIT) | (1 << AVALANCHE_HIGH_CPMAC_RESET_BIT) | (1 << AVALANCHE_LOW_EPHY_RESET_BIT);
++ *mdio_cntl = (1 << 30) | ((CONFIG_AR7_SYS * 1000)/2200);
++
++ for(j=0;j < 300000; j++)
++ {
++ if(j%100000) continue;
++
++ detected_phy_map = *(mdio_cntl + 1);
++ if(detected_phy_map)
++ {
++ detected_phy_map &= ~AVALANCHE_LOW_CPMAC_PHY_MASK;
++
++ if(detected_phy_map && !(detected_phy_map & (detected_phy_map - 1)))
++ {
++ auto_select = SELECT_EXT_PHY_MAC;
++ break;
++ }
++ }
++ }
++
++ return(auto_select);
++
++}
++
++#endif
++
++
++#ifndef AVALANCHE_LOW_CPMAC_MDIX_MASK
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
++#endif
++
++void psp_load_default_static_cfg(void)
++{
++ char s2[100], s3[100];
++ char s4[2000], s6[2000];
++ int threshold = 20;
++ char *tx_threshold_ptr = prom_getenv("threshold");
++
++ if(tx_threshold_ptr)
++ threshold = simple_strtol(tx_threshold_ptr, (char **)NULL, 10);
++
++ /* Static configuration if options.conf not present */
++ sprintf(s3,"cpmdio(id=mii, base=%u, reset_bit=%d)", AVALANCHE_MDIO_BASE, 22);
++ sprintf(s2, "reset( id=[ResetRegister], base=%u)", AVALANCHE_RESET_CONTROL_BASE);
++
++ sprintf(s4, "cpmac(id=[cpmac], unit=0, base=%u, size=0x800, reset_bit=%d, PhyMask=%u, MdixMask=%u, MLink=0, int_line=%d, memory_offset=0, RX_CAF=1, RX_PASSCRC=0, RX_CEF=1, RX_BCAST=0, RX_BCASTCH=0, Ch0=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch1=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch2=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128])", AVALANCHE_LOW_CPMAC_BASE, AVALANCHE_LOW_CPMAC_RESET_BIT, AVALANCHE_LOW_CPMAC_PHY_MASK, AVALANCHE_LOW_CPMAC_MDIX_MASK, AVALANCHE_LOW_CPMAC_INT,threshold,threshold,threshold);
++
++ sprintf(s6, "cpmac(id=[cpmac], unit=1, base=%u, size=0x800, reset_bit=%d, PhyMask=%u, MLink=0, int_line=%d, memory_offset=0, RX_CAF=1, RX_PASSCRC=0, RX_CEF=1, RX_BCAST=0, RX_BCASTCH=0, Ch0=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch1=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128], Ch2=[TxNumBuffers=256, TxNumQueues=1, TxServiceMax=%d, RxNumBuffers=256, RxBufferOffset=0, RxBufSize=1000, RxServiceMax=128])", AVALANCHE_HIGH_CPMAC_BASE, AVALANCHE_HIGH_CPMAC_RESET_BIT, AVALANCHE_HIGH_CPMAC_PHY_MASK, AVALANCHE_HIGH_CPMAC_INT,threshold,threshold,threshold);
++
++ psp_config_add("reset", s2, psp_config_strlen(s2), en_compile);
++
++
++#if defined (CONFIG_AVALANCHE_LOW_CPMAC)
++
++ psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
++ psp_config_add("cpmac", s4, psp_config_strlen(s4), en_compile);
++
++#endif
++
++
++#if defined (CONFIG_AVALANCHE_HIGH_CPMAC)
++
++ psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
++ psp_config_add("cpmac", s6, psp_config_strlen(s6), en_compile);
++
++#endif
++
++#if defined (CONFIG_AVALANCHE_CPMAC_AUTO)
++ {
++ char *phy_sel_ptr = prom_getenv("mac_phy_sel");
++ int phy_sel = SELECT_EXT_PHY_MAC;
++ char *mac_port = prom_getenv("MAC_PORT"); /* Internal: 0, External: 1 */
++
++ if(phy_sel_ptr && (0 == strcmp(phy_sel_ptr, "int")))
++ {
++ phy_sel = SELECT_INT_PHY_MAC;
++ }
++
++ //if(phy_sel == auto_detect_cpmac_phy())
++ if(!mac_port || (0 != strcmp(mac_port, "0")))
++ {
++ printk("Using the MAC with external PHY\n");
++ psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
++ psp_config_add("cpmac", s6, psp_config_strlen(s6), en_compile);
++ }
++ else
++ {
++ printk("Using the MAC with internal PHY\n");
++ psp_config_add("cpmdio", s3, psp_config_strlen(s3), en_compile);
++ psp_config_add("cpmac", s4, psp_config_strlen(s4), en_compile);
++ }
++ }
++
++#endif
++
++}
++
++char* psp_conf_read_file(char *p_file_name)
++{
++#ifdef INCLUDE_FFS
++
++ char *p_file_data = NULL;
++ unsigned int file_size;
++ FFS_FILE *p_file = NULL;
++
++ if(p_file_name == NULL)
++ {
++ return (NULL);
++ }
++
++ if(!(p_file = ffs_fopen(p_file_name, "r")))
++ {
++ return(NULL);
++ }
++
++ file_size = p_file->_AvailableBytes;
++
++ p_file_data = os_malloc(file_size + 1);
++
++ if(ffs_fread(p_file_data, file_size, 1, p_file) == 0)
++ {
++ kfree(p_file_data);
++ return(NULL);
++ }
++
++ ffs_fclose(p_file);
++
++ p_file_data[file_size] = '\0';
++
++ return(p_file_data);
++
++#else /* NO FFS */
++ return(NULL);
++#endif /* INCLUDE_FFS */
++}
++
++int psp_conf_get_line(char *p_in_data, char **next_line)
++{
++ char *p = p_in_data;
++
++ while(*p && *p++ != '\n')
++ {
++
++ }
++
++ *next_line = p;
++
++ return(p - 1 - p_in_data);
++}
++
++
++int psp_conf_is_data_line(char *line)
++{
++ int ret_val = 1;
++
++ if(*line == '\0' || *line == '\n' || *line == '#')
++ ret_val = 0;
++
++ return(ret_val);
++}
++
++int psp_conf_get_key_size(char *data)
++{
++ char *p = data;
++
++ while(*p && *p != '\n' && *p != '(' && *p != ' ')
++ p++;
++
++ return(p - data);
++}
++
++char* psp_conf_eat_white_spaces(char *p)
++{
++ while(*p && *p != '\n' && *p == ' ')
++ p++;
++
++ return (p);
++}
++
++int psp_build_from_opt_conf(void)
++{
++ char *data = NULL;
++ char *data_hold = NULL;
++ char *next_line = NULL;
++ int line_size = 0;
++
++ if((data = psp_conf_read_file("/etc/options.conf")) == NULL)
++ return(-1);
++
++ data_hold = data;
++
++ while((line_size=psp_conf_get_line(data, &next_line)) != -1)
++ {
++
++ char *name = NULL;
++ int name_size;
++
++ data = psp_conf_eat_white_spaces(data);
++
++ if(psp_conf_is_data_line(data))
++ {
++ data[line_size] = '\0';
++
++ name_size = psp_conf_get_key_size(data);
++
++ if(name_size > 0)
++ {
++ name = (char *) os_malloc(name_size + 1);
++ if(name == NULL) break;
++
++ psp_config_memcpy(name, data, name_size);
++ name[name_size] = '\0';
++
++ psp_config_add(name, data, line_size, en_opt_conf);
++
++ kfree(name);
++ }
++
++ data[line_size] = '\n';
++ }
++
++ data = next_line;
++ }
++
++ kfree(data_hold);
++ return (0);
++}
++
++
++int psp_write_conf_file(char *p_write_file, char * dev_cfg_string)
++{
++#ifdef INCLUDE_FFS
++ int bytes_written=0;
++ FFS_FILE *file_ptr=NULL;
++
++ /*
++ * NOTE: In current implementation of FFS in ADAM2 if the file exists beforehand, it
++ * can't be opened for write.
++ */
++ if(!(file_ptr=ffs_fopen(p_write_file, "w"))) {
++ return(-1);
++ }
++
++ /* Write into the file "output.con" the character string */
++ /* write a \n before a writing a line */
++ if(!(bytes_written = ffs_fwrite("\n", 1, sizeof(char), file_ptr))) {
++ return (-1);
++ }
++
++ if(!(bytes_written = ffs_fwrite(dev_cfg_string, psp_config_strlen(dev_cfg_string), sizeof(char), file_ptr))) {
++ return (-1);
++ }
++ ffs_fclose(file_ptr);
++ return (bytes_written+1);
++#else /* NO FFS */
++ return(-1);
++#endif /* INCLUDE_FFS */
++}
++
++void build_psp_config(void)
++{
++
++ /* initialize the repository. */
++ psp_config_init();
++
++#ifdef INCLUDE_FFS
++ ffs_init();
++#endif /* INCLUDE_FFS */
++
++ /* read the configuration from the options.conf to override default ones */
++ psp_build_from_opt_conf();
++
++ /* read the configuration which were not over ridden in options.conf */
++ psp_load_default_static_cfg();
++
++ /* let the vlynq be enumerated. Enumerator will add cfg info
++ of the discovered device instances to the repository.*/
++ psp_run_enumerator();
++
++ /* dump the repository*/
++ dump_device_cfg_pool();
++
++}
++
+diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_build.h linux.dev/drivers/net/avalanche_cpmac/psp_config_build.h
+--- linux.old/drivers/net/avalanche_cpmac/psp_config_build.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/psp_config_build.h 2005-07-12 02:48:42.176573000 +0200
+@@ -0,0 +1,138 @@
++/******************************************************************************
++ * FILE PURPOSE: PSP Config Manager - Configuration Build Header
++ ******************************************************************************
++ * FILE NAME: psp_config_build.h
++ *
++ * DESCRIPTION: Configuration Build API's.
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++#ifndef __PSP_CONF_BUILD_H__
++#define __PSP_CONF_BUILD_H__
++
++/*------------------------------------------------------------------------------
++ * Name: psp_conf_read_file
++ *
++ * Parameters:
++ * in: p_file_name - the name of the file to read from.
++ *
++ * Description:
++ * Reads the entire file in one shot. This function opens the
++ * file, determines the size of the data to be read, allocates
++ * the required memory, NULL terminates the data and closes the
++ * file.
++ *
++ * It is responsibily of the callee to free the memory after it is
++ * done with that data.
++ *
++ *
++ * Returns:
++ * A NULL pointer, if failed to read the data otherwise, a valid
++ * pointer referring to the data read from the file.
++ *
++ * Example:
++ *
++ * psp_conf_read_file("/etc/options.conf");
++ *---------------------------------------------------------------------------*/
++ char *psp_conf_read_file(char *p_file_name);
++
++ /*----------------------------------------------------------------------------
++ * Function : psp_conf_write_file
++ *
++ * Parameters:
++ * in: p_file_name - the file to which data is to be written.
++ * in: data - the NULL terminated data string.
++ *
++ * Description:
++ * Write the indicated data into the file. This function opens the file,
++ * appends the data to end of the file, closes the file.
++ *
++ * Returns:
++ *
++ * The number of bytes on success.
++ * 0 on failure.
++ *
++ * Example:
++ *
++ * psp_conf_write_file("/etc/outcon.conf", data);
++ *--------------------------------------------------------------------------*/
++ int psp_conf_write_file(char *p_file_name, char *data);
++
++ /*----------------------------------------------------------------------------
++ * Function: psp_conf_get_line
++ *
++ * Parameters:
++ * in: data - the data from which the line is to identified.
++ * out: next_line - the pointer to start of the next line.
++ *
++ * Description:
++ * Expects the data to be '\n' separated segments and data is NULL
++ * terminated. Parses the given data for '\n' or '\0'. Provides a pointer
++ * to the start of next line in the next_line.
++ *
++ * Returns:
++ * -1 on error.
++ * 0 or more to indicate the number of bytes in the line starting at
++ * data.
++ *--------------------------------------------------------------------------*/
++ int psp_get_conf_line(char *p_in_data, char **next_line);
++
++ /*----------------------------------------------------------------------------
++ * Function: psp_conf_is_data_line
++ *
++ * Parameters:
++ * in: line - the array of bytes.
++ *
++ * Description:
++ * Tests the first byte in the array for '\0' or '\n' or '#'. Lines
++ * starting with these characters are not considered data.
++ *
++ * Returns:
++ * 1 if the line has data.
++ * 0 otherwise.
++ *
++ *--------------------------------------------------------------------------*/
++ int psp_conf_is_data_line(char *line);
++
++ /*----------------------------------------------------------------------------
++ * Function: psp_conf_eat_white_spaces
++ *
++ * Parameters:
++ * in: line - the array of bytes.
++ *
++ * Description:
++ * Eats white spaces at the begining of the line while looking out for
++ * '\0' or '\n' or ' '.
++ *
++ * Returns:
++ * Pointer to the begining of the non white space character.
++ * NULL if '\0' or '\n' is found.
++ *
++ *--------------------------------------------------------------------------*/
++ char *psp_conf_eat_white_spaces(char *line);
++
++ /*---------------------------------------------------------------------------
++ * Function: psp_conf_get_key_size
++ *
++ * Parameters:
++ * in: line - the array of bytes.
++ *
++ * Description:
++ * Identifies the size of the 'key' in array formatted as
++ * key(id=[key1]....). This function also checks out for '\0' and '\n'.
++ *
++ * Returns:
++ * On success, The number of bytes that forms the key.
++ * 0 otherwise.
++ *
++ *-------------------------------------------------------------------------*/
++ int psp_conf_get_key_size(char *line);
++
++
++
++#endif /* __PSP_CONF_BUILD_H__ */
++
+diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_mgr.c linux.dev/drivers/net/avalanche_cpmac/psp_config_mgr.c
+--- linux.old/drivers/net/avalanche_cpmac/psp_config_mgr.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/psp_config_mgr.c 2005-07-12 02:48:42.177573000 +0200
+@@ -0,0 +1,464 @@
++/******************************************************************************
++ * FILE PURPOSE: PSP Config Manager Source
++ ******************************************************************************
++ * FILE NAME: psp_config_mgr.c
++ *
++ * DESCRIPTION:
++ *
++ * Manages configuration information. The repository is managed on the basis of
++ * <key, info> pair. It is possible to have multiple occurrence of the same key.
++ * Multiple occurences of the same keys are referred to as 'instances'.
++ * 'instances' are assigned in the order of configuration arrival. The first
++ * config for a 'key' added to the repository would be treated as instance 0 and
++ * next config to arrive for the same key would be treated as instance '1' and
++ * so on.
++ *
++ * Info is retrieved from the repository based on the 'key' and 'instance' value.
++ *
++ * No assumption is made about the format of the information that is put in the
++ * repository. The only requirement is that 'key' should be NULL terminated
++ * string.
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++//#include <stdio.h>
++//#include <stdlib.h>
++#include "psp_config_mgr.h"
++#include "psp_config_util.h"
++
++#include <linux/slab.h>
++
++/*-----------------------------------------------------------
++ Implemented elsewhere
++ -----------------------------------------------------------*/
++extern int sys_read_options_conf(void);
++extern int sys_write_options_conf(char *cfg_info);
++extern int sys_load_default_static_cfg(void);
++extern int sys_run_enumerator(void);
++
++#define os_malloc(size) kmalloc(size, GFP_KERNEL)
++
++/*---------------------------------------------------------
++ * Data structures.
++ *--------------------------------------------------------*/
++struct device_cfg_data;
++
++typedef struct device_instance_cfg_data
++{
++ struct device_instance_cfg_data *next;
++ char locale[100];
++ unsigned int data_size;
++ char *data;
++
++} DEV_INSTANCE_CFG_DATA_T;
++
++struct device_cfg_collection;
++
++typedef struct device_cfg_collection
++{
++ struct device_cfg_collection *next;
++ char *device_name;
++ CFG_TYPE_T cfg_type;
++ int count;
++ DEV_INSTANCE_CFG_DATA_T *dev_inst_list_begin;
++ DEV_INSTANCE_CFG_DATA_T *dev_inst_list_end;
++} DEVICE_CFG_T;
++
++
++typedef struct device_cfg_list
++{
++ DEVICE_CFG_T *device_cfg_begin;
++ int count;
++} DEVICE_CFG_LIST_T;
++
++/*-----------------------------------------------------------------------------
++ * Functions used locally with in the file.
++ *---------------------------------------------------------------------------*/
++static void p_init_device_cfg_list(void);
++static int p_add_instance_cfg_data(DEVICE_CFG_T *p_dev_cfg,
++ DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data);
++static DEVICE_CFG_T* p_create_dev_cfg(char *device_name);
++static DEVICE_CFG_T* p_get_dev_cfg(char *device_name);
++static int p_set_device_cfg_type(DEVICE_CFG_T *p_dev_cfg,
++ CFG_TYPE_T cfg_type);
++
++/* PSP Config manager debug */
++#define PSP_CFG_MGR_DEBUG 0
++
++#define dbgPrint if (PSP_CFG_MGR_DEBUG) printk
++
++/*-----------------------------------------------------------------------------
++ * The repository.
++ *---------------------------------------------------------------------------*/
++static DEVICE_CFG_LIST_T g_device_cfg_list;
++
++/*---------------------------------------------
++ * Initialize the device collection pool.
++ *--------------------------------------------*/
++void p_init_device_cfg_list(void)
++{
++ g_device_cfg_list.count = 0;
++ g_device_cfg_list.device_cfg_begin = NULL;
++}
++
++/*----------------------------------------------------------------------
++ * Add the device cfg into the device linked list.
++ *---------------------------------------------------------------------*/
++int p_add_dev_cfg_to_list(DEVICE_CFG_LIST_T *p_dev_list,
++ DEVICE_CFG_T *p_dev_cfg)
++{
++ if(p_dev_list->count != 0)
++ p_dev_cfg->next = p_dev_list->device_cfg_begin;
++
++ p_dev_list->device_cfg_begin = p_dev_cfg;
++
++ p_dev_list->count++;
++
++ return (0);
++}
++
++/*------------------------------------------------------------------
++ * Add the cfg data into the cfg data linked list of the collection.
++ *------------------------------------------------------------------*/
++int p_add_instance_cfg_data(DEVICE_CFG_T *p_dev_cfg,
++ DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data)
++{
++ if(p_dev_cfg->count == 0)
++ p_dev_cfg->dev_inst_list_begin = p_dev_inst_data;
++ else
++ p_dev_cfg->dev_inst_list_end->next = p_dev_inst_data;
++
++ p_dev_cfg->dev_inst_list_end = p_dev_inst_data;
++
++ p_dev_cfg->count++;
++
++ return (0);
++}
++
++/*-----------------------------------------------------------------------------
++ * Create the device cfg.
++ *---------------------------------------------------------------------------*/
++DEVICE_CFG_T *p_create_dev_cfg(char *device_name)
++{
++ DEVICE_CFG_T *p_dev_cfg = NULL;
++
++ if((p_dev_cfg = os_malloc(sizeof(DEVICE_CFG_T))) == NULL)
++ {
++ dbgPrint("Failed to allocate memory for DEVICE_CFG_T.\n");
++ }
++ else if((p_dev_cfg->device_name = os_malloc(psp_config_strlen(device_name) + 1))==NULL)
++ {
++ dbgPrint("Failed to allocate memory for device name.\n");
++ }
++ else
++ {
++ psp_config_strcpy(p_dev_cfg->device_name, device_name);
++ p_dev_cfg->cfg_type = en_raw;
++ p_dev_cfg->count = 0;
++ p_dev_cfg->dev_inst_list_begin = NULL;
++ p_dev_cfg->dev_inst_list_end = NULL;
++ p_dev_cfg->next = NULL;
++ }
++
++ return(p_dev_cfg);
++}
++
++/*------------------------------------------------------------------------------
++ * Get the device cfg collection.
++ *-----------------------------------------------------------------------------*/
++DEVICE_CFG_T *p_get_dev_cfg(char *device_name)
++{
++ int count = 0;
++ DEVICE_CFG_T *p_dev_cfg = g_device_cfg_list.device_cfg_begin;
++
++ for(count=0; count < g_device_cfg_list.count; count++)
++ {
++ if(psp_config_strcmp(device_name, p_dev_cfg->device_name) == 0)
++ {
++ break;
++ }
++
++ p_dev_cfg = p_dev_cfg->next;
++ }
++
++ return(p_dev_cfg);
++}
++
++/*-------------------------------------------------------------------------
++ * Gets the name for the static cfg type. Utility function. Debug purposes.
++ *-------------------------------------------------------------------------*/
++char *p_get_cfg_type_name_for_en(CFG_TYPE_T cfg_type)
++{
++ static char raw_str [] = "still raw";
++ static char compile_str [] = "configured at compile time";
++ static char optconf_str [] = "configured by options.conf";
++ static char vlynq_str [] = "configured by VLYNQ";
++ static char no_static_str[] = "no static configuration";
++
++ if(cfg_type == en_raw)
++ return (raw_str);
++ else if(cfg_type == en_compile)
++ return (compile_str);
++ else if(cfg_type == en_opt_conf)
++ return (optconf_str);
++ else if(cfg_type == en_vlynq)
++ return (vlynq_str);
++ else
++ return (no_static_str);
++
++}
++
++/*-----------------------------------------------------------------------------
++ * Sets the static cfg status of the device collection.
++ *
++ * If the collection is en_virgin then, the collection is assigned to cfg_type.
++ * If the cfg_type is en_vlynq then, the old cfg_type is retained.
++ * en_compile and en_opt_conf are mutually exclusive. One of these can be
++ * accomodated.
++ *
++ *---------------------------------------------------------------------------*/
++int p_set_device_cfg_type(DEVICE_CFG_T *p_dev_cfg,
++ CFG_TYPE_T cfg_type)
++{
++ int ret_val = 0;
++
++ if(p_dev_cfg->cfg_type == en_raw)
++ p_dev_cfg->cfg_type = cfg_type;
++ else if((cfg_type == en_vlynq) || (p_dev_cfg->cfg_type == cfg_type))
++ ;
++ else
++ {
++ dbgPrint("Device %s has been %s which overrides %s.\n",
++ p_dev_cfg->device_name,
++ p_get_cfg_type_name_for_en(p_dev_cfg->cfg_type),
++ p_get_cfg_type_name_for_en(cfg_type));
++ ret_val = -1;
++ }
++
++ return(ret_val);
++}
++
++/*------------------------------------------------------------------------
++ * Add the config str into the repository. The cfg type indicates
++ * whether the device has been configured statically, from options.conf or
++ * by vlynq enumeration.
++ *------------------------------------------------------------------------*/
++int psp_config_add(char *key, void *p_cfg_str, unsigned int cfg_len,
++ CFG_TYPE_T cfg_type)
++{
++ int ret_val = -1;
++ DEVICE_CFG_T *p_dev_cfg = NULL;
++ DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data = NULL;
++
++ if(p_cfg_str == NULL || key == NULL)
++ {
++ dbgPrint("Null input pointer(s).\n");
++ }
++ /* check if there exist a dev_cfg for the given key, if not,
++ then create one and add it to the device list. */
++ else if(((p_dev_cfg = p_get_dev_cfg(key)) == NULL) &&
++ (((p_dev_cfg = p_create_dev_cfg(key)) == NULL) ||
++ p_add_dev_cfg_to_list(&g_device_cfg_list, p_dev_cfg) != 0))
++ {
++ dbgPrint("Failed to allocate mem or add dev cfg for %s.\n", key);
++ }
++ /* make sure that we can add this cfg type to the repository */
++ else if(p_set_device_cfg_type(p_dev_cfg, cfg_type) == -1)
++ {
++ dbgPrint("Ignoring \"%s\" for device \"%s\".\n",
++ p_get_cfg_type_name_for_en(cfg_type),
++ p_dev_cfg->device_name);
++ }
++ else if((p_dev_inst_data = os_malloc(sizeof(DEV_INSTANCE_CFG_DATA_T)))== NULL)
++ {
++ dbgPrint("Failed to allocate memory for DEV_INSTANCE_CFG_DATA_T.\n");
++ }
++ else if((p_dev_inst_data->data = os_malloc(cfg_len) + 1) == NULL)
++ {
++ dbgPrint("Failed to allocate memory for the config data.\n");
++ }
++ else
++ {
++ p_dev_inst_data->next = NULL;
++
++ if(cfg_type == en_opt_conf || cfg_type == en_compile)
++ psp_config_strcpy(p_dev_inst_data->locale, "dev on chip ");
++ else if(cfg_type == en_vlynq)
++ psp_config_strcpy(p_dev_inst_data->locale, "dev on vlynq");
++ else
++ psp_config_strcpy(p_dev_inst_data->locale, "dev locale ?");
++
++ psp_config_memcpy(p_dev_inst_data->data, p_cfg_str, cfg_len);
++ p_dev_inst_data->data_size = cfg_len;
++ *(p_dev_inst_data->data + cfg_len) = '\0';
++
++ ret_val = p_add_instance_cfg_data(p_dev_cfg, p_dev_inst_data);
++ }
++
++ return(ret_val);
++}
++
++/*-------------------------------------------------------------
++ * Get the total number of device instances in the repository
++ *------------------------------------------------------------*/
++int psp_config_get_num_keys(void)
++{
++ return(g_device_cfg_list.count);
++}
++
++
++/*--------------------------------------------------------------------
++ * Get the device configuration info from the repository.
++ *-------------------------------------------------------------------*/
++int psp_config_get(char *key, int instance, char **cfg_data_out)
++{
++ int ret_val = -1;
++ DEVICE_CFG_T *p_dev_cfg = NULL;
++ *cfg_data_out = NULL;
++
++ if(key == NULL && cfg_data_out == NULL)
++ {
++ dbgPrint("Key has a NULL value.\n");
++ }
++ else if((p_dev_cfg = p_get_dev_cfg(key)) == NULL)
++ {
++ dbgPrint("cfg information for %s could not be found.\n", key);
++ }
++ else if(p_dev_cfg->count)
++ {
++ DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data =
++ p_dev_cfg->dev_inst_list_begin;
++ int index = 0;
++ for(index = 0;
++ index != instance && index < p_dev_cfg->count;
++ index++)
++ {
++ p_dev_inst_data = p_dev_inst_data->next;
++ }
++
++ if(p_dev_inst_data != NULL && p_dev_inst_data->data != NULL)
++ {
++ *cfg_data_out = p_dev_inst_data->data;
++ ret_val = p_dev_inst_data->data_size;
++ }
++ }
++
++ return (ret_val);
++}
++
++/*----------------------------------------------------------------
++ * Returns the number of instances found in the repository for the
++ * specified key.
++ *---------------------------------------------------------------*/
++int psp_config_get_num_instances(char *key)
++{
++ int ret_val = 0;
++ DEVICE_CFG_T *p_dev_cfg = NULL;
++
++ if(key == NULL)
++ {
++ dbgPrint("Key has a NULL value.\n");
++ }
++ else if((p_dev_cfg = p_get_dev_cfg(key)) == NULL)
++ {
++ dbgPrint("cfg information for %s could not be found.\n", key);
++ }
++ else
++ {
++ ret_val = p_dev_cfg->count;
++ }
++
++ return (ret_val);
++}
++
++/*------------------------------------------------------------------
++ * Dump the configuration repository.
++ * Caution: DO NOT USE THIS FOR ANY NON NBU specified config format.
++ *-----------------------------------------------------------------*/
++void psp_config_print(char *key)
++{
++ DEVICE_CFG_T *p_dev_cfg = NULL;
++
++ if(key == NULL)
++ {
++ dbgPrint("Key has a NULL value.\n");
++ }
++ else if((p_dev_cfg = p_get_dev_cfg(key)) == NULL)
++ {
++ dbgPrint("cfg information for %s could not be found.\n", key);
++ }
++ else if(p_dev_cfg && p_dev_cfg->count)
++ {
++ DEV_INSTANCE_CFG_DATA_T *p_dev_inst_data;
++
++ p_dev_inst_data = p_dev_cfg->dev_inst_list_begin;
++
++ do
++ {
++ dbgPrint("%s : %s\n", p_dev_inst_data->locale,
++ p_dev_inst_data->data);
++ p_dev_inst_data = p_dev_inst_data->next;
++
++ } while(p_dev_inst_data);
++ }
++ else
++ {
++ dbgPrint("Nothing was found for %s.\n", key);
++ }
++}
++
++void dump_device_cfg_pool(void)
++{
++ DEVICE_CFG_T *p_dev_cfg = g_device_cfg_list.device_cfg_begin;
++
++ if(p_dev_cfg != NULL && g_device_cfg_list.count)
++ {
++ int index=0;
++
++ for(index=0; index < g_device_cfg_list.count; index++)
++ {
++ psp_config_print(p_dev_cfg->device_name);
++ p_dev_cfg = p_dev_cfg->next;
++ }
++ }
++ else
++ {
++ dbgPrint("repository is empty.\n");
++ }
++}
++
++void psp_config_init(void)
++{
++ p_init_device_cfg_list();
++}
++
++void psp_config_cleanup()
++{
++ int dev_count = 0;
++ int inst_count = 0;
++ DEVICE_CFG_T *p = g_device_cfg_list.device_cfg_begin;
++ DEV_INSTANCE_CFG_DATA_T *q = NULL;
++
++ for(dev_count = 0; dev_count < g_device_cfg_list.count; dev_count++)
++ {
++ DEVICE_CFG_T *p_temp = NULL;
++ if(p) q = p->dev_inst_list_begin;
++
++ for(inst_count = 0; inst_count < p->count && q != NULL; inst_count++)
++ {
++ DEV_INSTANCE_CFG_DATA_T *q_temp = q;
++ q_temp = q->next;
++ kfree(q->data);
++ kfree(q);
++ q = q_temp;
++ }
++
++ p_temp = p->next;
++ kfree(p);
++ p = p_temp;
++ }
++}
+diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_mgr.h linux.dev/drivers/net/avalanche_cpmac/psp_config_mgr.h
+--- linux.old/drivers/net/avalanche_cpmac/psp_config_mgr.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/psp_config_mgr.h 2005-07-12 02:48:42.177573000 +0200
+@@ -0,0 +1,110 @@
++/******************************************************************************
++ * FILE PURPOSE: PSP Config Manager Header
++ ******************************************************************************
++ * FILE NAME: psp_config_mgr.h
++ *
++ * DESCRIPTION: Storing and retrieving the configuration based on key
++ * A set of APIs to be used by one and sundry (including drivers and enumerator) to build
++ * and read cfg information of the devices for an avalanche SOC.
++ *
++ * This set of APIs isolates the configuration management from the world and provides simple
++ * access convinience.
++ *
++ * Device in this set refers to the peripherals that can be found on the SOC or on VLYNQ.
++ * The configuration is stored in the form of string and drivers can use these APIs to get
++ * a particular parameter value.
++ *
++ * The memory allocation for the pass back parameters is done by the caller.
++ *
++ * 0 is returned for SUCCESS or TRUE.
++ * -1 is returned for FAILURE or FALSE.
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++#ifndef __PSP_CONFIG_MGR_H__
++#define __PSP_CONFIG_MGR_H__
++
++typedef enum cfg_type
++{
++ en_raw = 0,
++ en_compile,
++ en_opt_conf,
++ en_vlynq
++} CFG_TYPE_T;
++
++/* Build psp configuration */
++void build_psp_config(void);
++
++/********************************************************
++ * Access Operations.
++ ********************************************************/
++
++/*-------------------------------------------------------------------------
++ initializes the configuration repository.
++ -------------------------------------------------------------------------*/
++void psp_config_init(void);
++
++/*--------------------------------------------------------------------------
++ Adds the configuration information into the repository. 'key' is required
++ to be NULL terminated string. 'cfg_ptr' points to the configuration data.
++ 'cfg_len' is the length of the data pointed to by 'cfg_ptr' in bytes.
++ 'cfg_type' indicates the type of config information.
++
++ psp_config_mgr copies the 'cfg_len' bytes of data pointed to by 'cfg_ptr'
++ into its internal repository.
++
++ Returns: 0 on success, -1 on failure.
++ -------------------------------------------------------------------------*/
++int psp_config_add(char *key, void *cfg_ptr,
++ unsigned int cfg_len, CFG_TYPE_T cfg_type);
++
++
++/* --------------------------------------------------------------------------
++ Passes back, in "*cfg_out_val" a pointer to the config data in the repository
++ for the specified 'key' and 'instance'. It returns the size of the config
++ info
++
++ psp_config_mgr passes back a pointer in '*cfg_out_val' which refers to
++ some location in its internal repository. It is strongly recommended that
++ if the user intends to modify the contents of the config info for reasons
++ whatsoever, then, user should allocate memory of size returned by this
++ routine and copy the contents from '*cfg_out_val'.
++
++ Any, modification carried out on the repository would lead to un-expected
++ results.
++
++ Returns: 0 or more for the size of config info, -1 on error.
++ --------------------------------------------------------------------------*/
++int psp_config_get(char *key, int instance, char **cfg_out_val);
++
++
++/*--------------------------------------------------------------------------
++ Get the number of keys that have been added in the repository so far.
++
++ Returns: 0 or more for the num of keys, -1 on error.
++ -------------------------------------------------------------------------*/
++int psp_config_get_num_keys(void);
++
++
++/*--------------------------------------------------------------------------
++ Get the number of instances that are present in the repository for the
++ given 'key'.
++
++ Returns: 0 or more for the num of instances, -1 on error.
++ -------------------------------------------------------------------------*/
++int psp_config_get_num_instances(char *key);
++
++
++/*--------------------------------------------------------------------------
++ Prints the config data for all instances associated with the specified
++ 'key'.
++ -------------------------------------------------------------------------*/
++void psp_config_print(char *key);
++
++void dump_device_cfg_pool(void);
++
++#endif /* __PSP_CONFIG_MGR_H__ */
+diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_parse.c linux.dev/drivers/net/avalanche_cpmac/psp_config_parse.c
+--- linux.old/drivers/net/avalanche_cpmac/psp_config_parse.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/psp_config_parse.c 2005-07-12 02:48:42.178573000 +0200
+@@ -0,0 +1,362 @@
++/******************************************************************************
++ * FILE PURPOSE: PSP Config Manager - Parse API Source
++ ******************************************************************************
++ * FILE NAME: psp_config_parse.c
++ *
++ * DESCRIPTION: These APIs should be used only for scanvenging parameters which
++ * are stored in the following format.
++ *
++ * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++//#include <stdio.h>
++#include <linux/stddef.h>
++
++/*--------------------------------------------------
++ * MACROS.
++ *-------------------------------------------------*/
++#define my_isdigit(c) (c >= '0' && c <= '9')
++#define my_isoct(c) (c >= '0' && c <= '7')
++#define my_xtod(c) ((c) <= '9' ? (c) - '0' : (c) - 'a' + 10)
++#define my_ifupper(c) (c >= 'A' && c <= 'F')
++#define XTOD(c) ((c) - 'A' + 10)
++#define my_ishex(c) ((c >= 'a' && c <='f') || (c >= 'A' && c<='F') || my_isdigit(c) )
++
++/*---------------------------------------------------
++ * Local Functions.
++ *--------------------------------------------------*/
++static int p_get_substr_from_str(char *p_in_str, char begin_delimiter,
++ char end_delimiter, int pair_flag,
++ char **p_out_str);
++static int p_get_u_int_from_str(char *p_in_str, char begin_delimiter,
++ char end_delimiter, unsigned long *out_val);
++
++/*---------------------------------------------------
++ * Return pointer to first instance of the char.
++ *--------------------------------------------------*/
++static char* psp_config_strchr(char *str, char chr)
++{
++ while(*str)
++ {
++ if(*str == chr)
++ break;
++ str++;
++ }
++
++ return((*str) ? str : NULL);
++}
++
++/*------------------------------------------------------------------------
++ * Convert the string upto delimiter to unsigned long.
++ *-----------------------------------------------------------------------*/
++unsigned long my_atoul(char *p, char end_delimiter, unsigned long *out_val)
++{
++ unsigned long n;
++ int c;
++
++ /* check the for null input */
++ if (!p)
++ return -1;
++
++ c = *p;
++
++ /* pass through the leading spaces */
++ if (!my_isdigit(c))
++ {
++ while ( c == ' ')
++ c = *++p;
++
++ }
++
++ if (c == '0')
++ {
++ if(*(p + 1) == 'x' || *(p+1) == 'X' )
++ {
++ /* string is in hex format */
++
++ p += 2;
++ c = *p;
++
++ if(my_ishex(c))
++ {
++ if(my_ifupper(c))
++ n = XTOD(c);
++ else
++ n = my_xtod(c);
++ }
++ else
++ return -1; /* invalid hex string format */
++
++ while ((c = *++p) && my_ishex(c))
++ {
++ n *= 16;
++ if(my_ifupper(c))
++ n += XTOD(c);
++ else
++ n += my_xtod(c);
++ }
++ }
++ else
++ {
++ /* string is in octal format */
++
++ if( my_isoct(c) )
++ n = c - '0';
++ else
++ return -1; /* invalid octal string format */
++
++ while ((c = *++p) && my_isoct(c))
++ {
++ n *= 8;
++ n += c - '0';
++ }
++ }
++
++ }
++ else
++ {
++ /* string is in decimal format */
++
++ if( my_isdigit(c) )
++ n = c - '0';
++ else
++ return -1; /* invalid decimal string format */
++
++ while ((c = *++p) && my_isdigit(c))
++ {
++ n *= 10;
++ n += c - '0';
++ }
++ }
++
++ /* move through the trailing spaces */
++ while(*p == ' ')
++ p++;
++
++ if(*p == end_delimiter)
++ {
++ *out_val = n;
++ return 0;
++ }
++
++ else
++ return -1; /* invalid string format */
++}
++
++/*---------------------------------------------------------------------------------
++ * Gets the substring de-limited by the 'begin_delimiter' and 'end_delimiter'.
++ * and returns the size of the substring.
++ *
++ * Parses the NULL terminated p_in_str for a character array delimited by
++ * begin_delimiter and end_delimiter, passes back the pointer to the character
++ * array in ' *p_out_str '. The passed pointer ' *p_out_str ' should point to
++ * the location next (byte) to the begin_delimiter. The function routine returns
++ * the number of characters excluding the begin_delimiter and end_delimiter,
++ * found in the array delimited by the said delimiters.
++ *
++ * If the pair_flag is set to 1, then, number of begin_delimiter and end_delimiter
++ * found in the parsing should match (equal) and this routine passes back the
++ * pointer to the character array, starting at a location next (byte) to the
++ * first begin_delimiter, inclusive of all intermediate matching delimiter
++ * characters found between outer delimiters. If the pair flag is set and if
++ * begin_delimiter and end_delimiter happens to be same, then error (-1) is
++ * returned.
++ *
++ * Return: 0 or more to indicate the size of the substring, -1 on error.
++ *-------------------------------------------------------------------------------*/
++int p_get_substr_from_str(char *p_in_str, char begin_delimiter,
++ char end_delimiter, int pair_flag,
++ char **p_out_str)
++{
++ int cnt,pos;
++
++ if(pair_flag && begin_delimiter == end_delimiter)
++ return -1;
++
++ if((p_in_str = psp_config_strchr(p_in_str, begin_delimiter)) == 0)
++ return -1; /* no start delimiter found */
++
++ p_in_str++;
++ *p_out_str = p_in_str;
++
++ for(pos = 0,cnt =1; cnt && p_in_str[pos] ; pos++)
++ {
++ if(p_in_str[pos] == end_delimiter)
++ {
++ if(pair_flag == 0)
++ return pos;
++
++ cnt--;
++ }
++ else if(p_in_str[pos] == begin_delimiter)
++ cnt++;
++ else
++ ; /* We do nothing */
++
++ }
++
++ if( cnt == 0)
++ return pos - 1;
++ else
++ return -1; /* no corresponding end delimiter found */
++}
++
++/*--------------------------------------------------------------------------
++ * Parses the NULL terminated p_in_str for unsigned long value delimited by
++ * begin_delimiter and end_delimiter, passes back the found in ' *out_val '.
++ * The function routine returns 0 on success and returns -1 on failure.
++ * The first instance of the de-limiter should be accounted for the parsing.
++ *
++ * The base for unsigned value would 10, octal and hex. The value passed back
++ * would be of the base 10. Spaces at the begining of the byte array are valid
++ * and should be ingnored in the calculation of the value. Space character in
++ * the middle of the byte array or any character other than the valid ones
++ * (based on base type) should return error. The octal value begins with '0',
++ * the hex value begins with "0x" or "0X", the base value can begin with
++ * '1' to '9'.
++ *
++ * Returns: 0 on success, -1 on failure.
++ *-------------------------------------------------------------------------*/
++int p_get_u_int_from_str(char *p_in_str, char begin_delimiter,
++ char end_delimiter, unsigned long *out_val)
++{
++ char *start;
++ unsigned long num;
++
++ num = p_get_substr_from_str(p_in_str, begin_delimiter, end_delimiter,
++ 0, &start);
++
++ if(num == (unsigned long)-1)
++ return -1;
++
++ return my_atoul(start,end_delimiter,out_val);
++}
++
++/*--------------------------------------------------------------------------
++ * Finds the first occurrence of the substring p_find_str in the string
++ * p_in_str.
++ *-------------------------------------------------------------------------*/
++char *my_strstr(char *p_in_str, const char *p_find_str)
++{
++ char *p = (char *)p_find_str;
++ char *ret = NULL;
++
++ while(*p_in_str)
++ {
++ if(!(*p))
++ return (ret);
++ else if(*p_in_str == *p)
++ {
++ if(!ret) ret = p_in_str;
++ p++;
++ p_in_str++;
++ }
++ else if(ret)
++ {
++ p = (char *)p_find_str;
++ p_in_str = ret + 1;
++ ret = NULL;
++ }
++ else
++ p_in_str++;
++ }
++
++ if(*p_in_str != *p) ret = NULL;
++
++ return (ret);
++
++}
++
++/*------------------------------------------------------------------------------
++ * Gets the value of the config param in the unsigned int format. The value is
++ * stored in the following format in the string.
++ * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
++ *-----------------------------------------------------------------------------*/
++int psp_config_get_param_uint(char *p_in_str, const char *param, unsigned int *out_val)
++{
++ int ret_val = -1;
++ char *p_strstr;
++
++ if(!p_in_str || !param || !out_val)
++ {
++ ;
++ }
++ else if((p_strstr = my_strstr(p_in_str, param)) == NULL)
++ {
++ ;
++ }
++ else if(p_get_u_int_from_str(p_strstr, '=', ',', (unsigned long *)out_val) == 0)
++ {
++ ret_val = 0;
++ }
++ else if(p_get_u_int_from_str(p_strstr, '=', ']', (unsigned long*)out_val) == 0)
++ {
++ ret_val = 0;
++ }
++ else if(p_get_u_int_from_str(p_strstr, '=', ')', (unsigned long*)out_val) == 0)
++ {
++ ret_val = 0;
++ }
++ else
++ {
++ /* we failed */
++ }
++
++ return (ret_val);
++}
++
++/*------------------------------------------------------------------------------
++ * Gets the value of the config param in the Non NULL terminated format. The value
++ * is stored in the following format in the string.
++ * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
++ *-----------------------------------------------------------------------------*/
++int psp_config_get_param_string(char *p_in_str, const char *param, char **out_val)
++{
++ int ret_val = -1;
++ char *p_strstr;
++
++ if(!p_in_str || !param || !(out_val))
++ ;
++ else if((p_strstr = my_strstr(p_in_str, param)) == NULL)
++ {
++ ;
++ }
++ else if((ret_val = p_get_substr_from_str(p_strstr, '[', ']', 1, out_val)) == -1)
++ {
++ ;
++ }
++ else
++ {
++ ; /* we got the value */
++ }
++
++ return (ret_val);
++}
++
++#ifdef PSP_CONFIG_MGR_DEBUG_TEST
++main()
++{
++ unsigned long num =999;
++ int ret = 0;
++ char *val1 = NULL;
++ char val[30];
++ char str1[] = "cpmac(id=[cpmac], k0=[a1=[a2=[test], a3=2], k1=100, k2=[k3=300, k4=200], k7=722)";
++
++ psp_config_get_param_uint(str1, "k7", &num);
++ printf("%u.\n", num);
++ ret = psp_config_get_param_string(str1, "a1", &val1);
++ if(ret >= 0) { printf("%d.\n", ret); strncpy(val, val1, ret); val[ret] = '\0';}
++
++ printf("val = \"%s\", and size = %d \n", val, ret);
++
++ if(val[ret]) ; else printf("jeee.\n");
++}
++#endif /* PSP_CONFIG_MGR_DEBUG_TEST */
++
++
++
+diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_parse.h linux.dev/drivers/net/avalanche_cpmac/psp_config_parse.h
+--- linux.old/drivers/net/avalanche_cpmac/psp_config_parse.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/psp_config_parse.h 2005-07-12 02:48:42.178573000 +0200
+@@ -0,0 +1,32 @@
++/******************************************************************************
++ * FILE PURPOSE: PSP Config Manager - Parse API Header
++ ******************************************************************************
++ * FILE NAME: psp_config_parse.h
++ *
++ * DESCRIPTION: Parsing for params from string available in the NBU format.
++ * These APIs should be used only for scanvenging parameters which
++ * are stored in the following format.
++ *
++ * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++#ifndef __PSP_CONFIG_PARSER_H__
++#define __PSP_CONFIG_PARSER_H__
++
++/*------------------------------------------------------------------
++ * These APIs should be used only for scanvenging parameters which
++ * are stored in the following format.
++ *
++ * str[] = "module(id=[module], k1=v1, k2=[k3=v3, k4=v4], k5=v5)"
++ *-----------------------------------------------------------------*/
++int psp_config_get_param_uint(char *p_in_str, const char *param,
++ unsigned int *out_val);
++int psp_config_get_param_string(char *p_in_str, const char *param,
++ char **out_val);
++
++#endif /* __PSP_CONFIG_PARSER_H__ */
+diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_util.c linux.dev/drivers/net/avalanche_cpmac/psp_config_util.c
+--- linux.old/drivers/net/avalanche_cpmac/psp_config_util.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/psp_config_util.c 2005-07-12 02:48:42.178573000 +0200
+@@ -0,0 +1,106 @@
++/******************************************************************************
++ * FILE PURPOSE: PSP Config Manager - Utilities API Source
++ ******************************************************************************
++ * FILE NAME: psp_config_util.c
++ *
++ * DESCRIPTION: These APIs provide the standard "C" string interfaces.
++ * Provided here to reduce dependencies on the standard libraries
++ * and for cases where psp_config would required to run before
++ * the whole system is loaded or outside the scope of the OS.
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++//#include <stdio.h>
++#include "psp_config_util.h"
++#include <linux/stddef.h>
++
++/*---------------------------------------------
++ * strlen.
++ *-------------------------------------------*/
++int psp_config_strlen(char *p)
++{
++ char *p_orig = p;
++ while(*p)
++ p++;
++ return(p - p_orig);
++}
++
++/*--------------------------------------------
++ * strcmp.
++ *-------------------------------------------*/
++int psp_config_strcmp(char *s1, char *s2)
++{
++ while(*s1 && *s2)
++ {
++ if(*s1 != *s2)
++ break;
++ s1++;
++ s2++;
++ }
++
++ return(*s1 - *s2);
++}
++
++/*--------------------------------------------
++ * strcpy.
++ *------------------------------------------*/
++char* psp_config_strcpy(char *dest, char *src)
++{
++ char *dest_orig = dest;
++
++ while(*src)
++ {
++ *dest++ = *src++;
++ }
++
++ *dest = '\0';
++
++ return(dest_orig);
++}
++
++/*----------------------------------------------
++ * psp_config_memcpy.
++ *--------------------------------------------*/
++void* psp_config_memcpy(void* dest, void* src, unsigned int n)
++{
++ void *dest_orig = dest;
++
++ while(n)
++ {
++ *(char *)dest++ = *(char *)src++;
++ n--;
++ }
++
++ return (dest_orig);
++}
++
++/*---------------------------------------------------
++ * Return pointer to first instance of the char.
++ *--------------------------------------------------*/
++char* psp_config_strchr(char *str, char chr)
++{
++ while(*str)
++ {
++ if(*str == chr)
++ break;
++ str++;
++ }
++
++ return((*str) ? str : NULL);
++}
++
++#ifdef PSP_CONFIG_MGR_DEBUG_TEST
++
++int main( )
++{
++ char s[] = "hello ";
++ printf("%d.\n", psp_config_strlen("hello\n"));
++ printf("%d.\n", psp_config_strcmp("hells", "hellq"));
++ printf("%s %s.\n", psp_config_strcpy(s + 6, "test1"), s);
++}
++
++#endif /* PSP_CONFIG_MGR_DEBUG_TEST */
+diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_util.h linux.dev/drivers/net/avalanche_cpmac/psp_config_util.h
+--- linux.old/drivers/net/avalanche_cpmac/psp_config_util.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/psp_config_util.h 2005-07-12 02:48:42.179573000 +0200
+@@ -0,0 +1,26 @@
++/******************************************************************************
++ * FILE PURPOSE: PSP Config Manager - Utilities API Header
++ ******************************************************************************
++ * FILE NAME: psp_config_util.h
++ *
++ * DESCRIPTION: These APIs provide the standard "C" string interfaces.
++ * Provided here to reduce dependencies on the standard libraries
++ * and for cases where psp_config would required to run before
++ * the whole system is loaded or outside the scope of the OS.
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++#ifndef __PSP_CONFIG_UTIL_H__
++#define __PSP_CONFIG_UTIL_H__
++
++extern int psp_config_strlen(char*);
++extern int psp_config_strcmp(char*, char*);
++extern char* psp_config_strcpy(char*, char*);
++extern void* psp_config_memcpy(void*, void*, unsigned int n);
++extern char* psp_config_strchr(char*, char);
++
++#endif /* __PSP_CONFIG_UTIL_H__ */
+diff -urN linux.old/drivers/net/avalanche_cpmac/readme.txt linux.dev/drivers/net/avalanche_cpmac/readme.txt
+--- linux.old/drivers/net/avalanche_cpmac/readme.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/avalanche_cpmac/readme.txt 2005-07-12 02:48:42.179573000 +0200
+@@ -0,0 +1,545 @@
++23 August 2004 CPMAC 1.7.8 (NSP Performance Team Release)
++
++CC Labels: REL_20040823_HALdallas_cpmac_01.07.08
++
++New features: Key "MacAddr" can now be used to set the Mac Address after Open.
++
++ unsigned char MacAddr[6];
++
++ // Set Mac Address to "00.B0.D0.10.80.C1"
++ MacAddr[0] = 0x00;
++ MacAddr[1] = 0xB0;
++ MacAddr[2] = 0xD0;
++ MacAddr[3] = 0x10;
++ MacAddr[4] = 0x80;
++ MacAddr[5] = 0xC1;
++
++ HalFunc->Control(HalDev, "MacAddr", hcSet, &MacAddr);
++
++Bug fixes: in Send(), Threshold is not checked if Tx Ints are re-enabled.
++
++Modules affected: hcpmac.c, hcpmac.h, cppi_cpmac.c
++
++22 June 2004 CPMAC 1.7.6 (NSP Performance Team Release)
++
++CC Labels: REL_20040622_HALdallas_cpmac_01.07.06
++
++New features: Key "TxIntDisable" used to disable Tx Interrupts. If it is set, then Tx Interrupts will be processed on Send() controlled by Tx ServiceMax Setting.
++
++ int On = 1;
++ HalFunc->Control(HalDev, "TxIntDisable", "Set", &On);
++
++Bug fixes: NTR
++
++10 June 2004 CPMAC 1.7.5 (external release)
++
++CC Labels: REL_20040610_HALdallas_cpmac_01.07.05
++
++New features: NTR
++
++Bug fixes: Fixed an issue with calculation for the multicast hash.
++
++27 May 2004 CPSAR 1.7.4, CPMAC 1.7.4 (external release)
++
++CC Labels: REL_20040527_HALdallas_cpsar_01.07.04
++ REL_20040527_HALdallas_cpmac_01.07.04
++
++New features: NTR
++
++Bug fixes: A flaw was fixed in the critical sectioning of the CPPI file, affecting both
++ the MAC and the SAR releases. This flaw was detected on Titan PSP 4.7 BFT2.
++
++05 May 2004 CPSAR 1.7.3, CPMAC 1.7.3 (external release)
++
++CC Labels: REL_20040505_HALdallas_cpsar_01.07.03
++ REL_20040505_HALdallas_cpmac_01.07.03
++
++New features: NTR
++
++Bug fixes: 1) Firmware has been updated to fix a problem with Host OAM mode operation.
++ 2) Cache macros have been fixed.
++
++Notes: This release contains all performance enhancements currently available for CPHAL 1.x.
++
++19 April 2004 CPSAR 1.7.2, CPMAC 1.7.2 (external release)
++
++CC Labels: REL_20040419_HALdallas_cpsar_01.07.02
++ REL_20040419_HALdallas_cpmac_01.07.02
++
++New features: NTR
++
++Bug fixes: Fixes merge problem in 1.7.1.
++
++Notes: This is a branch release which contains only a subset of the performance improvements.
++ The remaining performance improvements are stiill being qualified at this time.
++
++1 April 2004 CPSAR 1.7.1, CPMAC 1.7.1 (external release)
++
++NOTICE: DO NOT USE 1.7.1. It has a known problem (see 1.7.2 notes)
++
++CC Labels: REL_20040401_HALdallas_cpsar_01.07.01
++ REL_20040401_HALdallas_cpmac_01.07.01
++
++New features: Performance improvement in CPPI layer, affecting both CPSAR and CPMAC.
++
++Bug fixes: NTR
++
++17 Februrary 2004 CPSAR 1.7.0 (external release)
++
++CC Labels: REL_20040217_HALdallas_cpsar_01.07.00
++
++New features: Added support for "TxFlush" feature. This allows the upper
++ layer to flush all or part of a given Tx queue for a given
++ channel. This is to be used during call setup for a voice
++ connection.
++
++30 January 2004 CPMAC 1.7.0 (external release)
++
++CC Labels: REL_20040130_HALdallas_cpmac_01.07.00
++
++Bug fixes: CPMDIO - When in manual negotiate mode and linked, dropping link would move into NWAY state rather than manual state.
++ CPMDIO - Extraneous debug message corrected
++New features: CPMDIO - Support for AutoMdix usage added.
++
++25 September 2003 CPSAR 1.6.6 (external release)
++
++CC Labels: REL_20030925_HALdallas_cpsar_01.06.06
++
++Bug fixes: PDSP firmware has been updated to fix the OAM padding problem. It previously
++ wrote pad bytes into a reserved field of the OAM cell. There is a small
++ change to the CPSAR configuration code which corresponds to the PDSP spec
++ change.
++
++New features: NTR
++
++09 September 2003 CPMAC 1.6.6 (external release)
++
++CC Labels: REL_20030909_HALdallas_cpmac_01.06.06
++
++Bug fixes: CPMAC : When _CPMDIO_NOPHY is set, Cpmac COntrol is set to Full Duplex
++ Bridge loopback test does not show a problem using 1.6.5 if packet rate is
++ below 50,000 pbs. Now testing with a 100% send from Ixia.
++
++New features: NTR
++
++05 August 2003 CPHAL 1.6.5 (external release)
++
++CC Labels: REL_20030805_HALdallas_cpmac_01.06.05
++
++Bug fixes: NTR
++
++New features: CPMAC : Added support for CPMAC modules that do not have a Phy connected.
++ The CPMAC is informed of this by the MdioConnect option
++ _CPMDIO_NOPHY. This is the only driver change needed to
++ receive and transmit packets through the Marvel switch.
++ Note In this mode Link status will reported linked at 100/FD to
++ PhyNum 0xFFFFFFFF.
++
++ ALL: Cleaned up some Vlynq support logic.
++
++16 July 2003 CPSAR 1.6.3 (external release), no CPMAC release
++
++CC Labels: REL_20030716_HALdallas_cpsar_01.06.03
++
++Bug fixes: 1) Changed default value of CPCS_UU from 0x5aa5 to 0. The old default value caused
++ problems with Cisco routers.
++
++New features: NTR
++
++Known issues not addressed in this release: NTR.
++
++01 July 2003 CPHAL 1.6.2 (external release)
++
++CC Labels: REL_20030701_HALdallas_cpmac_01.06.02
++ REL_20030701_HALdallas_cpsar_01.06.02
++
++Bug fixes: 1) A previous firmware upgrade caused firmware OAM loopback cells to only work on every other
++ command. This has been fixed in the new firmware version (0.47).
++ 2) Problem with PTI values changing on transparent mode packets has been resolved.
++ 3) Previously, successful firmware OAM loopback cells waited 5 seconds before notifying the
++ OS of success, rather that notifying immediately. This has been resolved in firmware.
++ 4) PITS #148 (MAC and SAR), #149 (MAC) have been fixed.
++
++New features: 1) AAL5 HAL now capable of receiving unknown VCI/VPI cells on a single transparent channel.
++ See updated HAL document (AAL5 appendix) for implementation details.
++ 2) AAL5 HAL now allows OS to modify the OAM loopback timeout window. Previously, failed
++ OAM loopback attempts timed out after a nominal 5 seconds (based on the SAR frequency
++ provided by the OS). Now, the default is 5 seconds, but the OS may change the
++ value via halControl() to any integer number of milliseconds. See updated HAL document
++ (AAL5 appendix) for implementation details.
++ 3) MAC (cpmdio): added loopback to Istate. Used for debug.
++
++Known issues not addressed in this release: NTR.
++
++09 June 2003 CPSAR 1.6.1 (external release), CPMAC 1.6.1 (internal release - no functional change)
++
++Note: This is the same set of fixes being applied to 1.6.0 that were applied to 1.5.3. The only difference
++ between 1.6.1 and 1.5.4 is that 1.6.1 has the TurboDSL fix.
++
++CC Labels: REL_20030609_HALdallas_cpmac_01.06.01
++ REL_20030609_HALdallas_cpsar_01.06.01
++
++Bug fixes: 1) Bug in OamLoopbackConfig fixed.
++ 2) New firmware version (.43) to fix Westell issue of dropped downstream packets in
++ presence of OAM traffic when operating at or near line rate.
++
++New features: NTR.
++
++09 June 2003 CPSAR 1.5.4 (external release), CPMAC 1.5.4 (internal release - no functional change)
++
++Note: This is a branch release from 1.5.3. This does not contain anything from 1.6.0. The CPMAC is
++only being labeled to keep the release flow consistent.
++
++CC Labels: REL_20030609_HALdallas_cpmac_01.05.04
++ REL_20030609_HALdallas_cpsar_01.05.04
++
++Bug fixes: 1) Bug in OamLoopbackConfig fixed.
++ 2) New firmware version (.43) to fix Westell issue of dropped downstream packets in
++ presence of OAM traffic when operating at or near line rate.
++
++New features: NTR.
++
++30 May 2003 CPSAR 1.6.0 (external release), CPMAC 1.6.0 (internal release - no functional change)
++
++CC Labels: REL_20030530_HALdallas_cpmac_01.06.00
++ REL_20030530_HALdallas_cpsar_01.06.00
++
++Bug fixes: 1) TurboDSL issue has been fixed with a software workaround in TxInt. This workaround
++ has been verified under Adam2 ONLY at this point. Testing remains to be done on
++ Linux and VxWorks.
++
++New features: NTR.
++
++Known issues not addressed in this release: NTR.
++
++30 May 2003 CPSAR 1.5.3 (external release), CPMAC 1.5.3 (internal release - no functional change)
++
++CC Labels: REL_20030530_HALdallas_cpmac_01.05.03
++ REL_20030530_HALdallas_cpsar_01.05.03
++
++Bug fixes: NTR.
++
++New features: 1) AAL5 Send() has been modified to accept an ATM Header either in the first
++ fragment by itself, or in the first fragment directly in front of payload data.
++ The API() does not change.
++ 2) Documentation updates throughout, reflected in latest version of CPHAL user's
++ guide.
++ 3) AAL5 MaxFrags default value is now 46. This is based upon the default AAL5
++ RxBufSize of 1518 (MaxFrags = (65568/1518) + 2). IF THE OS CHOOSES A SMALLER
++ RxBufSize, IT MUST INCREASE THE VALUE OF MaxFrags ACCORDINGLY. This is done
++ via halControl(), prior to Open().
++
++Known issues not addressed in this release:
++ 1) The Linux SAR driver is seeing an issue in which it cannot
++ reliably send traffic simultaneously on both the high and
++ low priority queues of a single AAL5 channel. (TurboDSL)
++
++23 May 2003 CPHAL 1.5.2 (external release)
++
++CC Labels: REL_20030523_HALdallas_cpmac_01.05.02
++ REL_20030523_HALdallas_cpsar_01.05.02
++
++Bug fixes: 1) PITS #138: CPMAC flooding issue resolved.
++ 2) PITS #142: OS may now set "MaxFrags" via Control(). This controls the
++ maximum number of fragments expected by the CPHAL. The default value is 2 for
++ CPMAC and 1028 for AAL5. If the OS chooses a RxBufSize that will cause more
++ fragments than the defaults, the OS must set "MaxFrags" to a correct value
++ ((maximum packet length / RxBufSize) + 2).
++ 3) PITS #143: Fixed.
++ 4) Firmware OAM bug fixed. (new firmware release in this version)
++
++New features: NTR.
++
++Known issues not addressed in this release:
++ 1) The Linux SAR driver is seeing an issue in which it cannot
++ reliably send traffic simultaneously on both the high and
++ low priority queues of a single AAL5 channel. (TurboDSL)
++
++14 May 2003 CPHAL 1.5.1 (external release)
++
++CC Labels: REL_20030514_HALdallas_cpmac_01.05.01
++ REL_20030514_HALdallas_cpsar_01.05.01
++
++Bug fixes: 1) PITS 132 - (CPMAC) Frames < 60 bytes and split into
++ multi-fragments.
++ 2) BCIL MR PSP00000353 - (CPMAC) PhyDev not free'd on halClose()
++ 3) PITS 113 - OsSetup bug in ChannelSetup fixed.
++ 4) Fixed AAL5 to check return values of InitTcb/InitRcb.
++ 5) Fixed Shutdown to properly free resources in the case of a Close
++ mode 1 followed by Shutdown. Previously, buffer and descriptor
++ resources were left unfreed in this case.
++
++New features: 1) AAL5 Send() modified to be capable of accepting ATM header as first four
++ bytes of first fragment. This allows the OS to "override" the
++ default ATM header which is constructed from preconfigured channel
++ parameters.
++ 2) AAL5 Receive() modified to be capable of passing the received ATM header (4 bytes, no HEC)
++ in the first fragment (by itself). It also passes up the OS an indication
++ of what the received packet type was. For Host OAM and transparent mode
++ packets, the ATM header is passed in this manner, and for other types of packets
++ (AAL5, NULL AAL) no ATM header is passed currently.
++
++Known issues not addressed in this release:
++ 1) The Linux SAR driver is seeing an issue in which it cannot
++ reliably send traffic simultaneously on both the high and
++ low priority queues of a single AAL5 channel.
++
++30 April 2003 CPHAL 1.5.0 (external release)
++
++CC Labels: REL_20030430_HALdallas_cpmac_01.05.00
++ REL_20030430_HALdallas_cpsar_01.05.00
++
++Bug fixes: 1) Fixed AAL5 bug that rendered the low priority queue
++ unusable.
++ 2) Fixed a bug in AAL5's Oam Rate calculations.
++ 3) Fixed use of "DeviceCPID" key in AAL5's halControl().
++ 4) Fixed RxReturn logic in HAL. The HAL now can handle
++ failing MallocRxBuffer calls when multiple fragments
++ are being used.
++
++New features: 1) AAL5 Stats now available on a per queue basis.
++ 2) AAL5 adds two new keys to halControl() for "Set" actions:
++ RxVc_OamCh and RxVp_OamCh.
++ 3) Shutdown() has been modified for both AAL5 and CPMAC to
++ call Close() if the module is still in the Open state.
++ 4) CPMAC adds the following access keys to halControl():
++ hcPhyAccess,hcPhyNum,hcCpmacBase,hcSize,and hcCpmacSize.
++ 5) CPHAL no longer requests an extra 15 bytes on data buffer
++ mallocs.
++
++Known issues not addressed in this release:
++ 1) The Linux SAR driver is seeing an issue in which it cannot
++ reliably send traffic simultaneously on both the high and
++ low priority queues of a single AAL5 channel.
++
++21 April 2003 CPHAL 1.4.1 (external release)
++
++CC Labels: REL_20030421_HALdallas_cpmac_01.04.01
++ REL_20030421_HALdallas_cpsar_01.04.01
++
++Bug fixes: 1) Fixed OAM logic in SAR portion of CPHAL.
++
++New features: 1) OAM loopback counters exposed through halControl.
++ 2) Host OAM Send() can now use a single channel to send
++ OAM cells on unlimited number of VP's/VC's.
++ 3) CPHAL now requests "SarFreq" through osControl.
++ 4) CPHAL now calculates all OAM function rates based on
++ "SarFreq"; function OamRateConfig removed for API.
++ 5) New OAM function OamLoopbackConfig, used for configuring
++ loopback functions in firmware OAM mode.
++
++Known issues not addressed in this release: Bug fix 1) in release 1.4
++ (see below) does not work properly for multiple fragments.
++
++10 April 2003 CPHAL 1.4 (external release)
++
++CC Labels: REL_20030410_HALdallas_cpmac_01.04.00
++ REL_20030410_HALdallas_cpsar_01.04.00
++
++This release is for SAR and MAC.
++
++ Bug fixes: 1) Implemented logic in HAL to re-request buffer mallocs
++ in the case of MallocRxBuffer failing. The HAL now maintains
++ a NeedsBuffer queue of all RCB's that are without buffers.
++ On interrupts, or on Send(), the HAL checks to see if any
++ RCB's are on the queue, and if so, calls MallocRxBuffer
++ to attempt to get a new buffer and return the RCB to
++ circulation.
++ 2) SAR now properly returns all error codes from halOpen and
++ halChannelSetup.
++
++ New features: NTR
++
++ Known issues not addressed in this release: NTR
++
++08 April 2003 CPHAL 1.3.1 (internal release - SAR only)
++
++ CC Labels: REL_20030408_HALdallas_cpsar_01.03.01
++
++ This is a SAR only release. The current CPMAC release is still 1.3.
++
++ Bug fixes: 1) PDSP State RAM / Scratchpad RAM is now completely cleared after reset.
++ This resolves a stability issue.
++
++ New features: 1) OamMode is now a parameter in halControl(). Both "Set" and "Get"
++ actions are available. The value may be "0" (Host OAM), or "1"
++ (Firmware OAM).
++
++ Known issues not addressed in this release:
++ 1) Appropriate action for HAL in the case of MallocRxBuffer failing. We
++ are investigating whether the HAL should implement a needs buffer
++ queue.
++
++04 April 2003 CPHAL 1.3 (external release)
++
++ CC Labels: REL_20030404_HALdallas_cpmac_01.03.00
++ REL_20030404_HALdallas_cpsar_01.03.00
++ REL_20030404_HALdallas_cpaal5_01.03.00
++ REL_20030404_HALdallas_cpaal2_01.03.00
++
++ This release requires no changes for the ethernet end driver. The changes necessary
++ for the sar driver (firmware file name changes) have already been implemented.
++
++ Bug fixes: 1) RxReturn now returns an error if MallocRxBuffer fails. On RxReturn error, the driver should
++ call RxReturn again at a later time (when the malloc may succeed) in order for the CPHAL
++ to maintain a full complement of Rx buffers. We recommend holding off making this driver
++ change until we verify that this condition occurs.
++
++ New features: 1) Removed benign compiler warnings.
++ 2) PITS 122: http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=122
++ 3) Cpsar label (above) now is applied to everything
++ beneath /cpsar.
++ 4) PITS 14: http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=14
++ Transferred to MR PSP 00000089.
++ 5) PITS 120: http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=120
++
++ Known issues not addressed in this release:
++ 1) PITS 102 (as relating to OamMode configuration):
++ http://www.nbu.sc.ti.com/cgi-bin/pits/redisplay_archive?product=cphal_dev&report=102
++ Future release will make OamMode configurable
++ through halControl(), not on per channel basis.
++
++20 March 2003 CPHAL 1.2.1 (internal release)
++
++ CC Labels: REL_20030320_HALdallas_cpmac_01.02.01
++ REL_20030320_HALdallas_cpsar_01.02.01
++ REL_20030320_HALdallas_cpaal5_01.02.01
++ REL_20030320_HALdallas_cpaal2_01.02.01
++
++ Bug fixes: 1. Fixed modification of buffer pointer following
++ MallocRxBuffer in cppi.c.
++ 2. Removed extra firmware files from /cpsar.
++
++ New features: NTR.
++
++ Known issues not addressed in this release: NTR.
++
++07 March 2003 CPHAL 1.2 (external release)
++
++ CPMAC/CPSAR feature complete release. SAR added
++ several features including full OAM support and various
++ other features and bug fixes to address PITS 99-106, and
++ 114. CPMAC cleaned up details raised by India PSP
++ team.
++
++29 January 2003 CPHAL RC 3.01a (external release)
++
++ Corrects non-static functions to be static in cppi.c.
++
++09 Janurary 2003 CPHAL RC 3.01 (external release)
++
++ PITS 88: Fixed MDIO re-connection problem (hcpmac.c)
++ PITS 90: Corrected Rx Buffer Pointer modification (cppi.c)
++
++ Corrected error in cpremap.c
++
++20 December 2002 CPHAL RC 3 (external release)
++
++ Statistics support via halControl(). See Appendix A of guide.
++ Fixed errors in ChannelTeardown/ChannelSetup CPHAL logic.
++ Added multicast support as requested.
++ Several new OS string functions added to OS_FUNCTIONS.
++ "DebugLevel" configuration parameter changed to "Debug".
++ "Stats0" changed to "StatsDump" for CPMAC.
++
++13 December 2002 CPHAL RC 2.03 (internal release)
++
++ Performance improvements.
++ More debug statements implemented (esp AAL5).
++ Updated makefile with "make debug" option.
++ Hbridge performance: [debug library] 15774 tps (53% line rate)
++ [non-debug library] 13700 tps (46%)
++
++10 December 2002 CPHAL Release Candidate 2.02 (internal release)
++
++ Much of the configuration code internal to CPMAC and AAL5 has been made common.
++ [os]Receive API had been modified to remove OsReceiveInfo. This information is now
++ available as third member of the FRAGLIST structure, on a per buffer basis.
++ Successfully tested multi-fragment support on CPMAC, using 32 byte buffers.
++ Code is now Emerald compliant - all buffer descriptors now aligned to cache-line
++ boundaries.
++
++2 December 2002 CPHAL Release Candidate 2.01
++
++ Updates to comments in hcpmac.c, cpmdio.c, hcpmac.h
++ Nested comment in hcpmac.c in RC2 can cause compile errors.
++
++25 November 2002 CPHAL Release Candidate 2
++
++Project Items not completed for RC2
++#6 Ship as Library - Once under CC. Moved to RC3
++#8 Under Clearcase - Moved to RC3
++#25 Emerald compliant - Moved to RC3
++#26 Statistics support - Moved to RC3 (some support in RC2)
++#36 Debug scheme implemented - Moved to RC3 (some support in RC2)
++
++8 November 2002 CPHAL Release Candidate 1
++
++Notes:
++
++Project Items not completed for RC1
++
++#8 Under Clearcase - Clearcase server failure this week. Moved to RC2
++#6 Ship as Library - Once under CC. Moved to RC2
++#13 Verify Datatypes. Moved to RC2
++#14 Review APIs. Moved to RC2
++
++APIs under review for RC2
++
++halIsr()
++hslRxReturn()
++halSend()
++osSendComplete()
++osReceive()
++
++
++CPMAC Build Instructions
++
++Compile the file 'hcpmac.c'.
++
++
++AAL5 Build Instructions
++
++The AAL5 build is composed of the source files aal5sar.c and cpsar.c.
++Refer to the provided makefile for an example of compiling these files
++into a library.
++
++Example CPHAL Code
++
++CPMAC:
++
++Example CPMAC code is provided in the file hbridge.c.
++This program is provided simply as an example of using the CPHAL API.
++It is not intended to be compiled and executed in your environment.
++
++AAL5:
++
++Example AAL5 code is provided in the file loopback.c. This program
++is provided simply as an example of using the CPHAL API. It is not
++intended to be compiled and executed in your environment.
++
++
++Performance Baseline
++
++
++Cpmac
++
++RC1: hbridge.bin, running with IXIA cpahl_1.cfg.
++ This sends 64-byte packets from each Ixia port, with mac destination the other Ixia port.
++ MIPS core 4Kc.
++
++RC2: hbridge.bin, running with IXIA cpahl_1.cfg.
++ This sends 64-byte packets from each Ixia port, with mac destination the other Ixia port.
++ MIPS core 4Ke.
++ CPHAL now includes Emerald support, but this has been disabled by using 'cache -wt' to emulate 4Kc.
++
++RC3: hbridge.bin, running with IXIA cpahl_1.cfg.
++ This sends 64-byte packets from each Ixia port, with mac destination the other Ixia port.
++ MIPS core 4Ke.
++ Running as Emerald processor.
++
++Release Total Receive Rate Throughput Setting
++
++RC1 11300 38%
++RC2 9524 32%
++RC3 15190 51%
+diff -urN linux.old/drivers/net/Config.in linux.dev/drivers/net/Config.in
+--- linux.old/drivers/net/Config.in 2005-07-12 03:20:45.726149872 +0200
++++ linux.dev/drivers/net/Config.in 2005-07-12 02:48:42.180573000 +0200
+@@ -25,6 +25,24 @@
+ comment 'Ethernet (10 or 100Mbit)'
+ bool 'Ethernet (10 or 100Mbit)' CONFIG_NET_ETHERNET
+ if [ "$CONFIG_NET_ETHERNET" = "y" ]; then
++ if [ "$CONFIG_MIPS_TITAN" = "y" -o "$CONFIG_AR7" = "y" ]; then
++ tristate ' Texas Instruments Avalanche CPMAC support' CONFIG_MIPS_AVALANCHE_CPMAC
++ fi
++ if [ "$CONFIG_MIPS_AVALANCHE_CPMAC" != "n" ]; then
++ if [ "$CONFIG_AR7WRD" = "y" -o "$CONFIG_AR7VWI" = "y" -o "$CONFIG_AR7VW" = "y" ]; then
++ define_bool CONFIG_MIPS_CPMAC_INIT_BUF_MALLOC y
++ define_int CONFIG_MIPS_CPMAC_PORTS 1
++ if [ "$CONFIG_MIPS_AVALANCHE_MARVELL" = "y" ]; then
++ define_bool CONFIG_AVALANCHE_LOW_CPMAC n
++ define_bool CONFIG_AVALANCHE_HIGH_CPMAC y
++ else
++ define_bool CONFIG_AVALANCHE_CPMAC_AUTO y
++ define_bool CONFIG_AVALANCHE_LOW_CPMAC n
++ define_bool CONFIG_AVALANCHE_HIGH_CPMAC n
++ fi
++ fi
++ fi
++
+ if [ "$CONFIG_ARM" = "y" ]; then
+ dep_bool ' ARM EBSA110 AM79C961A support' CONFIG_ARM_AM79C961A $CONFIG_ARCH_EBSA110
+ tristate ' Cirrus Logic CS8900A support' CONFIG_ARM_CIRRUS
+diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
+--- linux.old/drivers/net/Makefile 2005-07-12 03:20:45.726149872 +0200
++++ linux.dev/drivers/net/Makefile 2005-07-12 02:48:42.181573000 +0200
+@@ -56,6 +56,16 @@
+ subdir-$(CONFIG_BONDING) += bonding
+
+ #
++# Texas Instruments AVALANCHE CPMAC driver
++#
++
++subdir-$(CONFIG_MIPS_AVALANCHE_CPMAC) += avalanche_cpmac
++#obj-$(CONFIG_MIPS_AVALANCHE_CPMAC) += avalanche_cpmac/avalanche_cpmac.o
++ifeq ($(CONFIG_MIPS_AVALANCHE_CPMAC),y)
++ obj-y += avalanche_cpmac/avalanche_cpmac.o
++endif
++
++#
+ # link order important here
+ #
+ obj-$(CONFIG_PLIP) += plip.o
+--- linux.old/drivers/net/avalanche_cpmac/cpmac.c 2005-08-25 10:56:33.702931008 +0200
++++ linux.dev/drivers/net/avalanche_cpmac/cpmac.c 2005-08-25 11:08:45.027451520 +0200
+@@ -2158,17 +2158,16 @@
+ CPMAC_PRIVATE_INFO_T *p_cpmac_priv = p_dev->priv;
+ CPMAC_DRV_HAL_INFO_T *p_drv_hal = p_cpmac_priv->drv_hal;
+ struct sk_buff *p_skb = fragList[0].OsInfo;
+- p_skb->len = fragList[0].len;
+
+ /* invalidate the cache. */
+ dma_cache_inv((unsigned long)p_skb->data, fragList[0].len);
+ #ifdef CPMAC_TEST
+- xdump(p_skb->data, p_skb->len, "recv");
++ xdump(p_skb->data, fragList[0].len, "recv");
+ #endif
+ #ifdef CPMAC_8021Q_SUPPORT
+ /* 802.1q stuff, just does the basic checking here. */
+ if(!p_cpmac_priv->enable_802_1q &&
+- p_skb->len > TCI_END_OFFSET &&
++ fragList[0].len > TCI_END_OFFSET &&
+ IS_802_1Q_FRAME(p_skb->data + TPID_START_OFFSET))
+ {
+ goto cpmac_hal_recv_frame_mismatch;
diff --git a/openwrt/target/linux/ar7-2.4/patches/004-atm_driver.patch b/openwrt/target/linux/ar7-2.4/patches/004-atm_driver.patch
new file mode 100644
index 0000000000..f6a920853a
--- /dev/null
+++ b/openwrt/target/linux/ar7-2.4/patches/004-atm_driver.patch
@@ -0,0 +1,27232 @@
+diff -urN linux.old/drivers/atm/Config.in linux.dev/drivers/atm/Config.in
+--- linux.old/drivers/atm/Config.in 2005-08-22 23:18:37.773532032 +0200
++++ linux.dev/drivers/atm/Config.in 2005-08-23 04:46:50.076846888 +0200
+@@ -99,4 +99,10 @@
+ bool 'Use S/UNI PHY driver' CONFIG_ATM_HE_USE_SUNI
+ fi
+ fi
++#
++# Texas Instruments SANGAM ADSL/ATM support
++#
++if [ "$CONFIG_AR7" = "y" ]; then
++ tristate 'Texas Instruments SANGAM ATM/ADSL support' CONFIG_MIPS_SANGAM_ATM
++fi
+ endmenu
+diff -urN linux.old/drivers/atm/Makefile linux.dev/drivers/atm/Makefile
+--- linux.old/drivers/atm/Makefile 2005-08-22 23:18:37.773532032 +0200
++++ linux.dev/drivers/atm/Makefile 2005-08-23 04:46:50.077846736 +0200
+@@ -14,6 +14,32 @@
+ obj-$(CONFIG_ATM_NICSTAR) += nicstar.o
+ obj-$(CONFIG_ATM_IDT77252) += idt77252.o
+
++ifeq ($(CONFIG_AR7),y)
++
++subdir-$(CONFIG_MIPS_SANGAM_ATM) += sangam_atm
++
++EXTRA_CFLAGS += -DEL -I$(TOPDIR)/drivers/atm/sangam_atm -DPOST_SILICON -DCOMMON_NSP -DCONFIG_LED_MODULE -DDEREGISTER_LED -DNO_ACT
++#EXTRA_CFLAGS += -DEL -I$(TOPDIR)/drivers/atm/sangam_atm -DPOST_SILICON -DCOMMON_NSP
++
++ifeq ($(ANNEX),B)
++EXTRA_CFLAGS += -DANNEX_B -DB
++else
++ifeq ($(ANNEX),C)
++EXTRA_CFLAGS += -DANNEX_C -DC
++else
++EXTRA_CFLAGS += -DANNEX_A -DP
++endif
++endif
++
++list-multi := tiatm.o
++tiatm-objs := sangam_atm/tn7atm.o sangam_atm/tn7dsl.o sangam_atm/tn7sar.o \
++ sangam_atm/dsl_hal_api.o sangam_atm/dsl_hal_support.o sangam_atm/cpsar.o \
++ sangam_atm/aal5sar.o
++
++obj-$(CONFIG_MIPS_SANGAM_ATM) += sangam_atm/tiatm.o
++
++endif
++
+ ifeq ($(CONFIG_ATM_NICSTAR_USE_SUNI),y)
+ obj-$(CONFIG_ATM_NICSTAR) += suni.o
+ endif
+diff -urN linux.old/drivers/atm/sangam_atm/aal5sar.c linux.dev/drivers/atm/sangam_atm/aal5sar.c
+--- linux.old/drivers/atm/sangam_atm/aal5sar.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/aal5sar.c 2005-08-23 04:46:50.080846280 +0200
+@@ -0,0 +1,2962 @@
++
++/**
++ *
++ * aal5sar.c
++ *
++ * TNETDxxxx Software Support\n
++ * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * version
++ * 28Feb02 Greg 1.00 Original Version created.\n
++ * 06Mar02 Greg 1.01 Documentation (Doxygen-style) enhanced
++ * 06May02 Greg 1.02 AAL2 added
++ * 06Jun02 Greg 1.03 Multiple API and bug fixes from emulation
++ * 12Jul02 Greg 1.04 API Update
++ */
++
++/**
++@defgroup CPHAL_Functions CPHAL Functions
++
++These are the CPHAL Functions.
++*/
++
++/**
++@page CPHAL_Implementation_Details
++
++@section cphal_intro Introduction
++
++The CPHAL API described above is generally applicable to all modules. Any
++implementation differences will be described in the following module-specific
++appendix sections.
++
++Included for your reference is a diagram showing the internal architecture
++of the CPHAL:
++
++@image html SangamSoftware.jpg "HAL Architecture"
++@image latex SangamSoftware.jpg "HAL Architecture" height=2.8in
++
++*/
++
++/**
++@defgroup AAL5_Functions Additional Functions for AAL5 Implementation
++
++These functions are used only by the AAL5 module.
++*/
++
++/*
++@defgroup CPMAC_Functions Additional Functions for CPMAC Implementation
++
++No additional functions currently defined.
++*/
++
++/**
++@page VDMA_Implementation_Details
++
++@section vdma_intro Introduction
++
++The VDMA-VT module facilitates efficient transfer of data (especially voice)
++between two devices, as shown in the figure below.
++
++@image html vdma.jpg "VDMA System Block Diagram"
++@image latex vdma.jpg "VDMA System Block Diagram" height=1in
++
++The VDMA-VT module supports two modes of operation: mirror mode and credit mode.
++Mirror mode is intended for systems in which the remote device does not have a
++VDMA-based module. Credit mode is intended for highest performance when VDMA-based
++modules exist on both ends of an interface.
++
++For more detailed information on the operation of the VDMA module, please
++reference the VDMA Module Guide.
++
++@section vdma_channels VDMA Channels
++
++The VDMA-VT module is a single channel, single transmit queue device. Therefore,
++when using the CHANNEL_INFO structure, the correct value for @c Ch is always 0.
++Correspondingly, the correct value for the @c Ch parameter in @c ChannelTeardown() is
++always 0. Further, when calling @c Send(), the driver should always supply the value
++of 0 for both the @c Ch and @c Queue parameters.
++
++For the VDMA-VT, configuring the channel requires the configuration of either 2 FIFO
++elements (in credit mode) or 4 FIFO elements (in mirror mode). For credit mode, the
++driver must configure just the local Tx and Rx FIFOs. For mirror mode, the driver must
++configure the Tx and Rx FIFOs for both the remote and local ends of the interface.
++
++This channel configuration is accomplished through multiple calls to @c ChannelSetup().
++Each call configures a single FIFO, according to the parameters in the CHANNEL_INFO
++structure. The members of VDMA-VT's CHANNEL_INFO structure are defined below.
++
++
++- int RemFifoAddr; Address of remote FIFO (mirror mode only). Set to 0 for credit mode.
++- int FifoAddr; Address of the local FIFO. If 0, the CPHAL will allocate the FIFO.
++- int FifoSize; Size of the FIFO.
++- int PollInt; Polling interval for the FIFO.
++- int Endianness; Endianness of the FIFO. If 1, big endian. If 0, little endian.
++- int RemAddr; Used only in credit mode. This is the base address of the remote
++ remote VDMA-based device (VDMA-VT or AAL2)
++- int RemDevID; Used only in credit mode. Identifies the type of remote VDMA-based device.
++ 0=VDMAVT, 1=AAL2 Ch0, 2=AAL2 Ch1, 3=AAL2 Ch2, 4= AAL2 Ch3.
++
++For the VDMA-VT module, the driver must make all calls to @c ChannelSetup() prior to calling
++@c Open(). This is because several of the channel specific parameters may not be changed
++while the VDMA-VT module is operational.
++
++@section vdma_params VDMA Parameters
++
++Defined here are the set of parameters for the VDMA-VT module. Default settings for
++each parameter should be represented in the device configuration file (options.conf).
++During @c Init(), the CPHAL will reference the device configuration file and load all
++default settings. The @c Control() interface gives the driver an opportunity to
++modify any default settings before the module becomes operational during the @c Open()
++call.
++
++@param NoTxIndication If 1, the CPHAL will not call @c SendComplete(). 0 is default.
++@param NoRxIndication If 1, the CPHAL will not call @c Receive(). 0 is default.
++@param RemoteCPU If 1, the CPHAL will not directly manipulate data in FIFO's, leaving
++ that task for a remote CPU. 0 is default.
++@param RxIntEn If 1, enables Rx interrupts. 0 is default.
++@param TxIntEn If 1, enables Tx interrupts. 0 is default.
++@param Mirror If 1, enables mirror mode. 0 selects credit mode (default).
++@param RxIntCtl Valid only in mirror mode. If 1, interrupts will occur when the Rx FIFO
++ RdIndex is updated. If 0, interrupts occur when the Rx FIFO WrIndex
++ is updated.
++@param TxIntCtl Valid only in mirror mode. If 1, interrupts will occur when the Rx FIFO
++ RdIndex is updated. If 0, interrupts occur when the Rx FIFO WrIndex
++ is updated.
++@param RBigEn Remote big endian mode. If 1, remote is big endian.
++@param LBigEn Local big endian mode. If 1, local is big endian.
++
++@section vdma_polling Using VDMA-VT without interrupts
++
++If your system configuration does not utilize VDMA interrupts, the ability to process the
++Tx and Rx FIFOs is supported. To process the Tx FIFO, call @c CheckTx(). If the CPHAL is
++able to process any complete data transmissions, it will call @c SendComplete() as usual.
++To process the Rx FIFO, call @c CheckRx(). If the CPHAL has received any data, it will
++call @c Receive() to pass the driver the data. Please reference @ref VDMA_Functions for more
++information on these interfaces.
++
++@section vdma_details VDMA Implementation Details
++
++The following functions are not defined for use with VDMA: @c Status(), @c Tick(), @c StatsGet(),
++and @c StatsClear().
++
++*/
++
++/**
++@page AAL5_Implementation_Details
++
++@section aal5_ver Version
++
++@copydoc AAL5_Version
++
++@section aal5_intro Introduction
++
++The AAL5 implementation will support 16 channels for transmit and 16 channels for
++receive. Each of the transmit channels may have up to two transmit queues
++associated with it. If two queues are used, Queue 0 is the high priority queue,
++and Queue 1 is the low priority queue.
++
++@section aal5_params AAL5 Configuration Parameters
++
++AAL5 requires two device entries to be available in the configuration repository, named
++@p "aal5" and @p "sar". The @p aal5 device entry must contain @p base (base address)
++and @p int_line (interrupt number). The @p sar device entry must have both @p base
++(base address) and @p reset_bit (reset bit).
++
++@par Device Level Configuration Parameters
++
++The following parameters are device-level parameters, which apply across all
++channels. The value for these parameters may be modified by changing the value in the
++configuration repository.
++
++- "UniNni":
++AAL5 network setting. 0 = UNI (default), 1 = NNI.
++
++@par Channel Configuration Parameters
++
++All AAL5 channel parameters may also be configured through the @c ChannelSetup() interface.
++Following is the list of @p CHANNEL_INFO members that may be modified by the driver when
++calling @c ChannelSetup(). The driver may provide a value of 0xFFFFFFFF for any channel
++parameter to select a default value for the parameter. The driver should at a minimum
++configure @p Vci and @p Vpi. The usage of all parameters beginning with TxVc_,
++TxVp_, RxVc_, RxVp_ is described in greater detail in the SAR Firmware Spec.
++These parameters are mainly associated with QoS and OAM functionality.
++
++- "RxNumBuffers":
++The number of Rx buffer descriptors to allocate for Ch.
++- "RxBufSize":
++Size (in bytes) for each Rx buffer.
++- "RxBufferOffset":
++Number of bytes to offset rx data from start of buffer (must be less than buffer size).
++- "RxServiceMax":
++Maximum number of packets to service at one time.
++- "TxNumBuffers":
++The number of Tx buffer descriptors to allocate for Ch.
++- "TxNumQueues":
++Number of Tx queues for this channel (1-2). Choosing 2 enables a low priority SAR queue.
++- "TxServiceMax":
++Maximum number of packets to service at one time.
++- "CpcsUU":
++The 2-byte CPCS UU and CPI information.
++- "Gfc":
++Generic Flow Control. Used in ATM header of Tx packets.
++- "Clp":
++Cell Loss Priority. Used in ATM header of Tx packets.
++- "Pti":
++Payload Type Indication. Used in ATM header of Tx packets.
++- "DaMask":
++Specifies whether credit issuance is paused when Tx data not available.
++- "Priority":
++Priority bin this channel will be scheduled within.
++- "PktType":
++0=AAL5,1=Null AAL,2=OAM,3=Transparent,4=AAL2.
++- "Vci":
++Virtual Channel Identifier.
++- "Vpi":
++Virtual Path Identifier.
++- "TxVc_AtmHeader":
++In firmware OAM mode, this
++is the ATM header to be appended to front of firmware generated VC OAM cells for
++this channel. Note: To generate host OAM cells, call @c Send() with
++the appropriate mode.
++- "TxVc_CellRate":
++Tx rate, set as clock ticks between transmissions (SCR for VBR, CBR for CBR).
++- "TxVc_QosType":
++0=CBR,1=VBR,2=UBR,3=UBRmcr.
++- "TxVc_Mbs":
++Min Burst Size in cells.
++- "TxVc_Pcr":
++Peak Cell Rate for VBR in clock ticks between transmissions.
++- "TxVc_OamTc":
++TC Path to transmit OAM cells for TX connections (0,1).
++- "TxVc_VpOffset":
++Offset to the OAM VP state table for TX connections. Channels with the same
++VPI must have the same VpOffset value. Channels with different VPIs
++must have unique VpOffset values.
++- "RxVc_OamCh":
++Channel to which to terminate received OAM cells to be forwarded to the Host
++for either Host OAM mode, or when RxVc_OamToHost is enabled during Firmware
++OAM mode.
++- "RxVc_OamToHost":
++Indicates whether to pass received unmatched OAM loopback cells to the host;
++0=do not pass, 1=pass.
++- "RxVc_AtmHeader":
++ATM Header placed on firmware gen'd OAM cells for this channel on a Rx
++connection (must be big endian with 0 PTI).
++- "RxVc_OamTc":
++TC Path to transmit OAM cells for RX connections (0,1).
++- "RxVc_VpOffset":
++Offset to the OAM VP state table for RX connections. Channels with the same
++VPI must have the same VpOffset value. Channels with different VPIs
++must have unique VpOffset values.
++- "TxVp_OamTc":
++TC Path to transmit OAM cells for TX VP connections (0,1).
++- "TxVp_AtmHeader":
++ATM Header placed on firmware gen'd VP OAM cells for this channel on a Tx VP
++connection (must be big endian with 0 VCI).
++- "RxVp_OamCh":
++Channel to which to terminate received OAM cells to be forwarded to the Host
++for either Host OAM mode, or when RxVc_OamToHost is enabled during Firmware
++OAM mode.
++- "RxVp_OamToHost":
++Indicates whether to pass received unmatched OAM loopback cells to the host;
++0=do not pass, 1=pass.
++- "RxVp_AtmHeader":
++In firmware OAM mode, this
++is the ATM header to be appended to front of firmware generated VP OAM cells for
++this channel. Note: To generate host OAM cells, call @c Send() with
++the appropriate mode.
++- "RxVp_OamTc":
++TC Path to transmit OAM cells for RX VP connections (0,1).
++- "RxVp_OamVcList":
++This 32-bit field is one-hot encoded to indicate all the VC channels that are
++associated with this VP channel. A value of 21 will indicate that VC
++channels 0, 2, and 4 are associated with this VP channel.
++- "FwdUnkVc":
++Indicates whether or not to forward unknown VCI/VPI cells to the host. This
++parameter only takes effect if the channel's PktType is Transparent(3).
++1=forwarding enabled, 0=forwarding disabled.
++
++@section aal5_details API Implementation Details
++
++ATTENTION: Documentation given here supplements the documentation given in the general
++CPHAL API section. The following details are crucial to correct usage of the
++AAL5 CPHAL.
++
++@par Receive()
++The least significant byte of @p Mode contains the channel number. Bit 31
++indicates whether or not the ATM header is present in the first fragment of
++the packet. If bit 31 is set, the 4 byte ATM header (minus HEC) will be provided
++in the first fragment, with the payload beginning in the second fragment. Currently,
++this is the default behavior for host OAM and transparent mode packets.
++Bits 17-16 indicate the packet type that is being received.
++Mode Parameter Breakdown: <BR>
++- 31 ATM Header In First Fragment (1=true, 0=false) <BR>
++- 30-18 Unused. <BR>
++- 17-16 Pkt Type. <BR>
++ - 0=AAL5 <BR>
++ - 1=PTI Based Null AAL <BR>
++ - 2=OAM <BR>
++ - 3=Transparent <BR>
++- 15-08 Unused. <BR>
++- 07-00 Channel Number.
++
++@par Send()
++The most significant 16 bits of the first fragment 'len' is used as the Offset
++to be added to the packet. @c Send() will reserve this many bytes at the
++beginning of the transmit buffer prior to the first byte of valid data.
++For the @p Mode parameter, Bit 31 must be set if the user has sent a packet with
++the ATM Header (minus HEC) embedded in the first 4 bytes of the first fragment data buffer.
++The OS has the option of using a 4 byte first fragment containing only ATM header,
++or concatenating the ATM Header in front of the data payload.
++If Bit 31 is set, the ATM Header in the buffer is preserved and sent with
++each cell of the packet. Otherwise, Send() will build the ATM header based on the
++values of the Pti, Gfc, Clp, Vpi, and Vci parameters for the given channel.
++Bits 17-16 are defined as the packet type. Bits 15-08 may be used to specify the
++transmit queue to send the packet on. Only values 0 (high priority) and 1 (low
++priority) are accepted. Bits 07-00 should be used to indicate the channel number
++for the @c Send() operation. Valid channel numbers are 0-15.
++Mode Parameter Breakdown: <BR>
++- 31 ATM Header In Packet (1=true, 0=false) <BR>
++- 30-18 Unused. <BR>
++- 17-16 Pkt Type. <BR>
++ - 0=AAL5 <BR>
++ - 1=PTI Based Null AAL <BR>
++ - 2=OAM <BR>
++ - 3=Transparent <BR>
++- 15-08 Transmit Queue. <BR>
++- 07-00 Channel Number.
++
++@par ChannelSetup()
++The AAL5 @c ChannelSetup() always configures both the Tx and Rx side of the channel
++connection in the same call.
++
++@par ChannelTeardown()
++Regardless of the channel teardown direction selected, the AAL5 CPHAL will always
++teardown both the Tx and Rx side of the channel connection.
++
++@par TeardownComplete()
++The value for the @p Direction parameter should be ignored for the AAL5 implementation,
++since both directions (Tx and Rx) are always torndown in response to a @c ChannelTeardown()
++command.
++
++@par Control() (HAL version)
++Defined keys and actions. Unless otherwise stated, the data type
++for Value is pointer to unsigned integer. The list is broken into
++three groups, one group which can be used anytime, one group that should
++be used before halOpen(), and one group which can only be used after
++halOpen() (but before halClose()). For channelized parameters, replace
++'Ch' with the integer number of a channel (ex. "Gfc.4" can be used to set
++Gfc for channel 4).
++
++MAY USE ANYTIME AFTER INIT (after halInit() is called):
++
++- "Gfc.Ch". The OS may "Set" this value. Changing this value causes
++the Gfc in each Tx ATM header for this channel to take on the new Gfc value.
++
++- "Clp.Ch". The OS may "Set" this value. Changing this value causes
++the Clp in each Tx ATM header for this channel to take on the new Clp value.
++
++- "Pti.Ch". The OS may "Set" this value. Changing this value causes
++the Pti in each Tx ATM header for this channel to take on the new Pti value.
++
++- "CpcsUU.Ch". The OS may "Set" this value. Changing this value causes
++the CpcsUU in each Tx ATM header for this channel to take on the new CpcsUU value.
++
++- "OamMode". Specifies if host or firmware is performing OAM functions; 0 = Host OAM,
++1 = Firmware OAM. When set, all SAR channels will be configured for
++the selection, including AAL2 channels.
++
++- "OamLbTimeout". Specifies the firmware OAM loopback timeout, in milliseconds.
++
++- "DeviceCPID". The OS may "Set" this value. This is the OAM connection
++point identifier. The OS should provide a pointer to an array of 4 32-bit
++integers. Each word must be configured in big endian format.
++
++- "FwdUnkVc.Ch". Indicates whether or not to forward unknown VCI/VPI cells to the host.
++This parameter only takes effect if the channel's PktType is Transparent(3).
++1=forwarding enabled, 0=forwarding disabled.
++
++MAY USE ONLY BEFORE HAL IS OPEN (before halOpen() call):
++- "StrictPriority". The OS may "Set" this value. Setting to 1 causes
++a different interrupt processing routine to be used, which gives strict
++priority to channels with lower numbers (channel 0 has highest priority).
++The default handler gives equal priority to all channels.
++
++- "MaxFrags". The OS may "Set" or "Get" this value. This defines the maximum
++number of fragments that can be received by the AAL5 Rx port. The default
++value for AAL5 is 46. This provides enough space to receive a maximum
++length AAL5 packet (65,568 bytes) with the default buffer size of 1518 bytes, and
++any amount of RxBufferOffset. If the buffer size is configured to be smaller,
++the OS *MUST* modify this parameter according to the following formula:
++((System Max AAL5 packet length)/(RxBufSize)) + 2. (The extra two fragments in
++the formula allow for RxBufferOffset and one fragment for the ATM Header, used
++when receiving host OAM or transparent mode packets)
++
++MAY USE ONLY AFTER HAL IS 'OPEN' (after halOpen() call):
++- "Stats;Level;Ch;Queue". The OS may "Get" Stats groups with this key, where
++'Level' is an integer from 0-4, Ch is an integer from 0-15, and Queue is
++an integer from 0-1. Note that Ch is not required for Level 4 stats, and Queue
++is not required for Level 0, 3, and 4. The statistics functionality and return
++value is described in the appendix entitled "Configuration and Control".
++
++- "TxVc_CellRate.Ch". The OS may "Set" this value. Can be used to modify
++CellRate for a channel on the fly.
++
++- "TxVc_Mbs.Ch". The OS may "Set" this value. Can be used to modify
++Mbs for a channel on the fly.
++
++- "TxVc_Pcr.Ch". The OS may "Set" this value. Can be used to modify
++Pcr for a channel on the fly.
++
++- "PdspEnable". The OS may "Set" this value. Value 0 disables the PDSP.
++Value 1 enables to PDSP.
++
++- "DeviceCPID". The OS may "Set" this value. The Value should be an array
++of 4 32-bit integers that comprise the CPID.
++
++- "RxVc_RDICount.Ch". The OS may "Get" or "Set" this value. Get returns
++the current RDI count for the VC channel. Set clears the counter, and the Value
++is ignored.
++
++- "RxVp_RDICount.Ch". The OS may "Get" or "Set" this value. Get returns
++the current RDI count for the VP channel. Set clears the counter, and the Value
++is ignored.
++
++- "RxVc_AISseg.Ch". The OS may "Get" this value. This is an indication of
++AIS segment error for the VC channel.
++
++- "RxVp_AISseg.Ch". The OS may "Get" this value. This is an indication of
++AIS segment error for the VP channel.
++
++- "RxVc_AISetoe.Ch". The OS may "Get" this value. This is an indication of
++AIS end-to-end error for the VC channel.
++
++- "RxVp_AISetoe.Ch". The OS may "Get" this value. This is an indication of
++AIS end-to-end error for the VP channel.
++
++- "RxVc_OamCh.Ch". The OS may "Set" this value. Channel to which to terminate
++received OAM cells to be forwarded to the Host for either Host OAM mode, or when
++RxVc_OamToHost is enabled during Firmware OAM mode.
++
++- "RxVp_OamCh.Ch". The OS may "Set" this value. Channel to which to terminate
++received OAM cells to be forwarded to the Host for either Host OAM mode, or when
++RxVp_OamToHost is enabled during Firmware OAM mode.
++
++- "F4_LB_Counter". The OS may "Get" this value. This is a count of the number
++ of near-end F4 loopbacks performed by the PDSP in firmware OAM mode.
++
++- "F5_LB_Counter". The OS may "Get" this value. This is a count of the number
++ of near-end F5 loopbacks performed by the PDSP in firmware OAM mode.
++
++- "TxVc_AtmHeader.Ch". The OS may "Set" this value. In firmware OAM mode, this
++is the ATM header to be appended to front of firmware generated VC OAM cells for
++this channel. In host OAM mode, this is used as the ATM header to be appended
++to front of host generated VC OAM cells for this channel. It must be configured
++as big endian with PTI=0. Note: To generate host OAM cells, call @c Send() with
++the appropriate mode.
++
++- "TxVp_AtmHeader.Ch". The OS may "Set" this value. In firmware OAM mode, this
++is the ATM header to be appended to front of firmware generated VP OAM cells for
++this channel. In host OAM mode, this is used as the ATM header to be appended
++to front of host generated VP OAM cells for this channel. It must be configured
++as big endian with VCI=0. Note: To generate host OAM cells, call @c Send() with
++the appropriate mode.
++
++- "PdspEnable". The OS may "Set" this value. Controls whether or not the PDSP is
++allowed to fetch new instructions. The PDSP is enabled by the CPHAL during Open(),
++and disabled during Close(). 0 = disabled, 1 = enabled.
++
++@par Control() (OS version)
++Defined keys and actions:
++
++- "Firmware". The CPHAL will perform a "Get" action for the key "Firmware". A pointer
++to a pointer is passed in @p Value. The OS must modify the referenced pointer to point
++to the firmware.
++
++- "FirmwareSize". The CPHAL will perform a "Get" action for the key "FirmwareSize".
++The OS must place the firmware size in the memory pointed at by @p Value.
++
++- "OamLbResult". When a channel that is in firmware OAM mode is commanded to perform
++a loopback function, the result of the loopback generates an interrupt that is handled
++by the OS like any other interrupt. The CPHAL, upon servicing the interrupt, will call
++osControl with this key, and an action of "Set". The @p Value parameter will be a
++pointer to the integer result. 1 = pass, 0 = fail.
++
++- "SarFreq". The CPHAL will perform a "Get" action for this key. The OS should place
++the SAR frequency (in Hz) in the memory pointed at by @p Value.
++
++@section aal5_stats AAL5 Specific Statistics
++
++Statistics level '0' contains all AAL5 specific statistics. The following values will
++be obtained when requesting stats level 0:
++
++- "Crc Errors". Number of CRC errors reported by SAR hardware. Incremented for received
++packets that contain CRC errors.
++
++- "Len Errors". Number of length errors reported by SAR hardware. Incremented for received
++packets that are in excess of 1366 cells.
++
++- "Abort Errors". Number of abort errors reported by SAR hardware.
++
++- "Starv Errors". Number of buffer starvation errors reported by SAR hardware. Incremented
++when a part or all of a buffer cannot be received due to lack of RX buffer resources. The SAR
++drops all cells associated with the packet for each buffer starvation error that occurs.
++
++*/
++
++/* register files */
++#include "cp_sar_reg.h"
++
++#define _CPHAL_AAL5
++#define _CPHAL
++#define _CPPI_TEST /** @todo remove for release */
++#define __CPHAL_CPPI_OFFSET /* support use of offset */
++
++/* OS Data Structure definitions */
++
++typedef void OS_PRIVATE;
++typedef void OS_DEVICE;
++typedef void OS_SENDINFO;
++typedef void OS_RECEIVEINFO;
++typedef void OS_SETUP;
++
++/* CPHAL Data Structure definitions */
++
++typedef struct hal_device HAL_DEVICE;
++typedef struct hal_private HAL_PRIVATE;
++typedef struct hal_private HAL_RECEIVEINFO;
++
++/* include CPHAL header files here */
++#include "cpcommon_cpaal5.h"
++#include "cpswhal_cpaal5.h"
++#include "aal5sar.h"
++#include "cpcommon_cpaal5.c"
++
++#define CR_SERVICE (170-1)
++#define UTOPIA_PAUSE_REG (*(volatile bit32u *)0xa4000000)
++
++/*
++these masks are for the mode parameter used in halSend/OsReceive
++(may move these elsewhere)
++*/
++#define CH_MASK 0xff
++#define PRI_MASK 0x10000
++
++/* Rcb/Tcb Constants */
++#define CB_SOF_BIT (1<<31)
++#define CB_EOF_BIT (1<<30)
++#define CB_SOF_AND_EOF_BIT (CB_SOF_BIT|CB_EOF_BIT)
++#define CB_OWNERSHIP_BIT (1<<29)
++#define CB_EOQ_BIT (1<<28)
++#define CB_SIZE_MASK 0x0000ffff
++#define CB_OFFSET_MASK 0xffff0000
++#define RCB_ERRORS_MASK 0x03fe0000
++#define RX_ERROR_MASK 0x000f0000
++#define CRC_ERROR_MASK 0x00010000
++#define LENGTH_ERROR_MASK 0x00020000
++#define ABORT_ERROR_MASK 0x00040000
++#define STARV_ERROR_MASK 0x00080000
++#define TEARDOWN_VAL 0xfffffffc
++
++/* interrupt vector masks */
++#define TXH_PEND 0x01000000
++#define TXL_PEND 0x02000000
++#define RX_PEND 0x04000000
++#define STS_PEND 0x08000000
++#define AAL2_PEND 0x10000000
++#define INT_PENDING (TXH_PEND | TXL_PEND | RX_PEND | STS_PEND | AAL2_PEND)
++#define STS_PEND_INVEC 0x0001F000
++#define RX_PEND_INVEC 0x00000F00
++#define TXL_PEND_INVEC 0x000000F0
++#define TXH_PEND_INVEC 0x0000000F
++#define AIS_SEG_MASK 0x1 /* +01.02.00 */
++#define AIS_SEG_SHIFT 0 /* +01.02.00 */
++#define AIS_ETOE_MASK 0x20000 /* +01.02.00 */
++#define AIS_ETOE_SHIFT 17 /* +01.02.00 */
++#define RDI_CNT_MASK 0xffff0000 /* +01.02.00 */
++#define RDI_CNT_SHIFT 16 /* +01.02.00 */
++
++/*
++ * This function takes a vpi/vci pair and computes the 4 byte atm header
++ * (minus the HEC).
++ *
++ * @param vpi Virtual Path Identifier.
++ * @param vci Virtual Channel Identifier.
++ *
++ * @return A properly formatted ATM header, without the HEC.
++ */
++static int atmheader(int gfc, int vpi, int vci, int pti, int clp)
++ {
++ int itmp;
++
++ itmp=0;
++
++ /* UNI Mode uses the GFC field */
++ itmp |= ((gfc & 0xF) << 28);
++ itmp |= ((vpi & 0xFF) << 20);
++
++ /* if NNI Mode, no gfc and larger VPI */
++ /*itmp |= ((vpi & 0xFFF) << 20);*/
++
++ itmp|=((vci & 0xFFFF) << 4);
++ itmp|=((pti & 0x7) << 1);
++ itmp|=(clp & 0x1);
++ return(itmp);
++ }
++
++#include "cppi_cpaal5.c"
++
++/*
++ * Re-entrancy Issues
++ * In order to ensure successful re-entrancy certain sections of the
++ * CPHAL code will be bracketed as Critical.
++ * The OS will provide the function Os.CriticalSection(BOOL), which
++ * will be passed a TRUE to enter the Critical Section and FALSE to exit.
++ */
++
++/*
++ * @ingroup CPHAL_Functions
++ * Clears the statistics information.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return 0 OK, Non-zero not OK
++ */
++static int StatsClear(HAL_DEVICE *HalDev)
++ {
++ int i;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]StatsClear(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* clear stats */
++ for (i=0; i<NUM_AAL5_CHAN; i++)
++ {
++ HalDev->Stats.CrcErrors[i]=0;
++ HalDev->Stats.LenErrors[i]=0;
++ HalDev->Stats.DmaLenErrors[i]=0;
++ HalDev->Stats.AbortErrors[i]=0;
++ HalDev->Stats.StarvErrors[i]=0;
++ HalDev->Stats.TxMisQCnt[i][0]=0;
++ HalDev->Stats.TxMisQCnt[i][1]=0;
++ HalDev->Stats.RxMisQCnt[i]=0;
++ HalDev->Stats.RxEOQCnt[i]=0;
++ HalDev->Stats.TxEOQCnt[i][0]=0;
++ HalDev->Stats.TxEOQCnt[i][1]=0;
++ HalDev->Stats.RxPacketsServiced[i]=0;
++ HalDev->Stats.TxPacketsServiced[i][0]=0;
++ HalDev->Stats.TxPacketsServiced[i][1]=0;
++ HalDev->Stats.TxMaxServiced[i][0]=0;
++ HalDev->Stats.TxMaxServiced[i][1]=0;
++ }
++ HalDev->Stats.RxTotal=0;
++ HalDev->Stats.TxTotal=0;
++ HalDev->Stats.RxMaxServiced=0;
++ return (EC_NO_ERRORS);
++ }
++
++/*
++ * Returns statistics information.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return 0
++ */
++/*
++static STAT_INFO* StatsGet(HAL_DEVICE *HalDev)
++ {
++ STAT_INFO* MyStats = &HalDev->Stats;
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]StatsGet(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ dbgPrintf("HAL Stats:\n");
++ DispStat(HalDev, "Rx Total",MyStats->RxTotal);
++ DispStat(HalDev, "Tx Total",MyStats->TxTotal);
++ DispStat(HalDev, "Rx Peak",MyStats->RxMaxServiced);
++ DispStat(HalDev, "TxH Peak",MyStats->TxMaxServiced[0][0]);
++ DispStat(HalDev, "TxL Peak",MyStats->TxMaxServiced[0][1]);
++ DispChStat(HalDev, "CrcErr",&MyStats->CrcErrors[0],1);
++ DispChStat(HalDev, "LenErr",&MyStats->LenErrors[0],1);
++ DispChStat(HalDev, "DmaLenErr",&MyStats->DmaLenErrors[0],1);
++ DispChStat(HalDev, "AbortErr",&MyStats->AbortErrors[0],1);
++ DispChStat(HalDev, "StarvErr",&MyStats->StarvErrors[0],1);
++ DispChStat(HalDev, "TxH MisQ Cnt",&MyStats->TxMisQCnt[0][0],2);
++ DispChStat(HalDev, "TxL MisQ Cnt",&MyStats->TxMisQCnt[0][1],2);
++ DispChStat(HalDev, "Rx MisQ Cnt",&MyStats->RxMisQCnt[0],1);
++ DispChStat(HalDev, "Rx EOQ Cnt",&MyStats->RxEOQCnt[0],1);
++ DispChStat(HalDev, "TxH EOQ Cnt",&MyStats->TxEOQCnt[0][0],2);
++ DispChStat(HalDev, "TxL EOQ Cnt",&MyStats->TxEOQCnt[0][1],2);
++ DispChStat(HalDev, "Rx Pkts",&MyStats->RxPacketsServiced[0],1);
++ DispChStat(HalDev, "TxH Pkts",&MyStats->TxPacketsServiced[0][0],2);
++ DispChStat(HalDev, "TxL Pkts",&MyStats->TxPacketsServiced[0][1],2);
++
++ return (&HalDev->Stats);
++ }
++*/
++
++#ifdef __CPHAL_DEBUG
++void dbgChannelConfigDump(HAL_DEVICE *HalDev, int Ch)
++ {
++ CHANNEL_INFO *HalCh = &HalDev->ChData[Ch];
++ dbgPrintf(" [aal5 Inst %d, Ch %d] Config Dump:\n", HalDev->Inst, Ch);
++ dbgPrintf(" TxNumBuffers :%08d, TxNumQueues :%08d\n",
++ HalCh->TxNumBuffers, HalCh->TxNumQueues);
++ dbgPrintf(" RxNumBuffers :%08d, RxBufSize :%08d\n",
++ HalCh->RxNumBuffers, HalCh->RxBufSize);
++ dbgPrintf(" TxServiceMax :%08d, RxServiceMax:%08d\n",
++ HalCh->TxServiceMax, HalCh->RxServiceMax);
++ dbgPrintf(" RxBufferOffset:%08d, DaMask :%08d\n",
++ HalCh->RxBufferOffset, HalCh->DaMask);
++ dbgPrintf(" CpcsUU :%08d, Gfc :%08d\n",
++ HalCh->CpcsUU, HalCh->Gfc);
++ dbgPrintf(" Clp :%08d, Pti :%08d\n",
++ HalCh->Clp, HalCh->Pti);
++ dbgPrintf(" Priority :%08d, PktType :%08d\n",
++ HalCh->Priority, HalCh->PktType);
++ dbgPrintf(" Vci :%08d, Vpi :%08d\n",
++ HalCh->Vci, HalCh->Vpi);
++ dbgPrintf(" TxVc_CellRate :%08d, TxVc_QosType:%08d\n",
++ HalCh->TxVc_CellRate, HalCh->TxVc_QosType);
++ dbgPrintf(" TxVc_Mbs :%08d, TxVc_Pcr :%08d\n",
++ HalCh->TxVc_Mbs, HalCh->TxVc_Pcr);
++ dbgPrintf(" TxVc_AtmHeader:%08d\n",
++ HalCh->TxVc_AtmHeader);
++ osfuncSioFlush();
++ }
++#endif
++
++/*
++ * Retrieves channel parameters from configuration file. Any parameters
++ * which are not found are ignored, and the HAL default value will apply,
++ * unless a new value is given through the channel structure in the call
++ * to ChannelSetup.
++ */
++static int ChannelConfigGet(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
++ {
++ unsigned int Ret, Value, Ch = HalChn->Channel;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++ void *ChInfo;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]ChannelConfigGet(HalDev:%08x, HalChn:%08x)\n", (bit32u)HalDev,
++ (bit32u)HalChn);
++ osfuncSioFlush();
++ }
++#endif
++
++ Ret=OsFunc->DeviceFindParmValue(HalDev->DeviceInfo, channel_names[Ch], &ChInfo);
++ if (Ret) return (EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_CH_INFO_NOT_FOUND);
++
++ /* i don't care if a value is not found because they are optional */
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxNumBuffers", &Value);
++ if (!Ret) HalDev->ChData[Ch].TxNumBuffers = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxNumQueues", &Value);
++ if (!Ret) HalDev->ChData[Ch].TxNumQueues = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxServiceMax", &Value);
++ if (!Ret) HalDev->ChData[Ch].TxServiceMax = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxNumBuffers", &Value);
++ if (!Ret) HalDev->ChData[Ch].RxNumBuffers = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxBufferOffset", &Value);
++ if (!Ret) HalDev->ChData[Ch].RxBufferOffset = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxBufSize", &Value);
++ if (!Ret) HalDev->ChData[Ch].RxBufSize = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxServiceMax", &Value);
++ if (!Ret) HalDev->ChData[Ch].RxServiceMax = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "CpcsUU", &Value);
++ if (!Ret) HalDev->ChData[Ch].CpcsUU = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "Gfc", &Value);
++ if (!Ret) HalDev->ChData[Ch].Gfc = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "Clp", &Value);
++ if (!Ret) HalDev->ChData[Ch].Clp = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "Pti", &Value);
++ if (!Ret) HalDev->ChData[Ch].Pti = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "DaMask", &Value);
++ if (!Ret) HalDev->ChData[Ch].DaMask = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "Priority", &Value);
++ if (!Ret) HalDev->ChData[Ch].Priority = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "PktType", &Value);
++ if (!Ret) HalDev->ChData[Ch].PktType = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "Vci", &Value);
++ if (!Ret) HalDev->ChData[Ch].Vci = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "Vpi", &Value);
++ if (!Ret) HalDev->ChData[Ch].Vpi = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_CellRate", &Value);
++ if (!Ret) HalDev->ChData[Ch].TxVc_CellRate = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_QosType", &Value);
++ if (!Ret) HalDev->ChData[Ch].TxVc_QosType = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_Mbs", &Value);
++ if (!Ret) HalDev->ChData[Ch].TxVc_Mbs = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_Pcr", &Value);
++ if (!Ret) HalDev->ChData[Ch].TxVc_Pcr = Value;
++
++ Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_AtmHeader", &Value);
++ if (!Ret) HalDev->ChData[Ch].TxVc_AtmHeader = Value;
++
++ return (EC_NO_ERRORS);
++ }
++
++/*
++ * Sets up channel parameters in the hardware, and initializes the CPPI
++ * TX and RX buffer descriptors and buffers.
++ */
++static int ChannelConfigApply(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
++ {
++ int j, Ch = HalChn->Channel;
++ volatile bit32u *pTmp;
++ int Ret; /* +GSG 030410 */
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]ChannelConfigApply(HalDev:%08x, HalChn:%08x)\n", (bit32u)HalDev,
++ (bit32u)HalChn);
++ osfuncSioFlush();
++ }
++#endif
++
++ if ((HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE) || (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE))
++ {
++ return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_CH_ALREADY_OPEN);
++ }
++
++ HalDev->InRxInt[Ch]=FALSE;
++
++ /* Initialize Queue Data */
++ HalDev->RxActQueueHead[Ch]=0;
++ HalDev->RxActQueueCount[Ch]=0;
++ HalDev->TxActQueueHead[Ch][0]=0;
++ HalDev->TxActQueueHead[Ch][1]=0;
++ HalDev->TxActQueueCount[Ch][0]=0;
++ HalDev->TxActQueueCount[Ch][1]=0;
++ HalDev->RxActive[Ch] = FALSE;
++ HalDev->TxActive[Ch][0] = FALSE;
++ HalDev->TxActive[Ch][1] = FALSE;
++
++ /* Clear Rx State RAM */
++ pTmp = pRX_DMA_STATE_WORD_0(HalDev->dev_base) + (Ch*64);
++ for (j=0; j<NUM_RX_STATE_WORDS; j++)
++ *pTmp++ = 0;
++
++ /* Check that Rx DMA State RAM was cleared */
++ pTmp -= NUM_RX_STATE_WORDS;
++ for (j=0; j<NUM_RX_STATE_WORDS; j++)
++ {
++ if (*pTmp++ != 0)
++ {
++ return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_RX_STATE_RAM_NOT_CLEARED);
++ }
++ }
++
++ /* Clear Tx State RAM */
++ pTmp = pTX_DMA_STATE_WORD_0(HalDev->dev_base) + (Ch*64);
++ for (j=0; j<NUM_TX_STATE_WORDS; j++)
++ *pTmp++ = 0;
++
++ /* Check that Tx DMA State RAM was cleared */
++ pTmp -= NUM_TX_STATE_WORDS;
++ for (j=0; j<NUM_TX_STATE_WORDS; j++)
++ {
++ if (*pTmp++ != 0)
++ {
++ return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_TX_STATE_RAM_NOT_CLEARED);
++ }
++ }
++
++ /* Initialize Tx State RAM (Nothing to do) */
++
++ /* Initialize Rx State RAM */
++ /* Configure the Rx buffer offset */
++ pTmp=(pRX_DMA_STATE_WORD_0(HalDev->dev_base) + (Ch*64));
++ *pTmp |= (HalDev->ChData[Ch].RxBufferOffset & 0xFF);
++
++ /* Initialize buffer memory for the channel */
++ Ret = InitTcb(HalDev, Ch);
++ if (Ret) return (Ret);
++
++ Ret = InitRcb(HalDev, Ch);
++ if (Ret) return (Ret);
++
++ /* setup interrupt mask/enable for the channel */
++ SAR_TX_MASK_SET(HalDev->dev_base) = (1<<Ch);
++
++ /* if using the low priority queue, set up mask for it */
++ if (HalDev->ChData[Ch].TxNumQueues == 2) /* +GSG 030421 */
++ SAR_TX_MASK_SET(HalDev->dev_base) = (1<<Ch)<<16; /* +GSG 030421 */
++
++ SAR_RX_MASK_SET(HalDev->dev_base) = (1<<Ch);
++
++ /* call SAR layer to complete the channel setup - hardware configuration of ch */
++ Ret = HalDev->SarFunc->ChannelSetup(HalDev->SarDev, &HalDev->ChData[Ch]); /* ~GSG 030410 */
++ if (Ret) /* +GSG 030410 */
++ return (Ret); /* +GSG 030410 */
++
++ /* channel officially open for business */
++ HalDev->ChIsOpen[Ch][DIRECTION_TX] = TRUE;
++ HalDev->ChIsOpen[Ch][DIRECTION_RX] = TRUE;
++
++ return (EC_NO_ERRORS);
++ }
++
++/*
++ * Sets up HAL default channel configuration parameter values.
++ */
++static void ChannelConfigInit(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
++ {
++ int Ch = HalChn->Channel;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]ChannelConfigInit(HalDev:%08x, HalChn:%08x)\n", (bit32u)HalDev,
++ (bit32u)HalChn);
++ osfuncSioFlush();
++ }
++#endif
++
++ HalDev->ChData[Ch].Channel = Ch;
++ HalDev->ChData[Ch].TxNumBuffers = cfg_tx_num_bufs[Ch];
++ HalDev->ChData[Ch].RxNumBuffers = cfg_rx_num_bufs[Ch];
++ HalDev->ChData[Ch].RxBufSize = cfg_rx_buf_size[Ch];
++ HalDev->ChData[Ch].RxBufferOffset = cfg_rx_buf_offset[Ch];
++ HalDev->ChData[Ch].TxNumQueues = cfg_tx_num_queues[Ch];
++ HalDev->ChData[Ch].CpcsUU = cfg_cpcs_uu[Ch];
++ HalDev->ChData[Ch].DaMask = cfg_da_mask[Ch];
++ HalDev->ChData[Ch].Priority = cfg_priority[Ch];
++ HalDev->ChData[Ch].PktType = cfg_pkt_type[Ch];
++ HalDev->ChData[Ch].Vci = cfg_vci[Ch];
++ HalDev->ChData[Ch].Vpi = cfg_vpi[Ch];
++ HalDev->ChData[Ch].TxVc_CellRate = cfg_cell_rate[Ch];
++ HalDev->ChData[Ch].TxVc_QosType = cfg_qos_type[Ch];
++ HalDev->ChData[Ch].TxVc_Mbs = cfg_mbs[Ch];
++ HalDev->ChData[Ch].TxVc_Pcr = cfg_pcr[Ch];
++ HalDev->ChData[Ch].Gfc = cfg_gfc[Ch];
++ HalDev->ChData[Ch].Clp = cfg_clp[Ch];
++ HalDev->ChData[Ch].Pti = cfg_pti[Ch];
++ HalDev->ChData[Ch].RxServiceMax = cfg_rx_max_service[Ch];
++ HalDev->ChData[Ch].TxServiceMax = cfg_tx_max_service[Ch];
++ }
++
++/*
++ * Update per channel data in the HalDev based channel structure.
++ * If a certain channel parameter has been passed with the HAL_DEFAULT
++ * value (0xFFFFFFFF), then do not copy it.
++ */
++static void ChannelConfigUpdate(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
++ {
++ int Ch = HalChn->Channel;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]ChannelConfigUpdate(HalDev:%08x, HalChn:%08x)\n", (bit32u)HalDev,
++ (bit32u)HalChn);
++ osfuncSioFlush();
++ }
++#endif
++
++ HalDev->ChData[Ch].Channel = Ch;
++
++ /* ChannelUpdate is a macro defined in cpcommon.h. It requires
++ the presence of the variables named 'Ch' and 'HalChn'.*/
++ ChannelUpdate(DaMask);
++ ChannelUpdate(Priority);
++ ChannelUpdate(PktType);
++ ChannelUpdate(Vci);
++ ChannelUpdate(Vpi);
++ ChannelUpdate(CpcsUU);
++ ChannelUpdate(Gfc);
++ ChannelUpdate(Clp);
++ ChannelUpdate(Pti);
++ /* AAL5 Stuff */
++ ChannelUpdate(TxNumBuffers);
++ ChannelUpdate(RxNumBuffers);
++ ChannelUpdate(RxBufSize);
++ ChannelUpdate(RxBufferOffset);
++ ChannelUpdate(TxNumQueues);
++ ChannelUpdate(TxServiceMax);
++ ChannelUpdate(RxServiceMax);
++ /* PDSP STATE RAM */
++ ChannelUpdate(TxVc_CellRate);
++ ChannelUpdate(TxVc_QosType);
++ ChannelUpdate(TxVc_Mbs);
++ ChannelUpdate(TxVc_Pcr);
++ /* OAM */
++ ChannelUpdate(TxVc_AtmHeader);
++ ChannelUpdate(TxVc_OamTc);
++ ChannelUpdate(TxVc_VpOffset);
++ ChannelUpdate(RxVc_OamCh);
++ ChannelUpdate(RxVc_OamToHost);
++ ChannelUpdate(RxVc_AtmHeader);
++ ChannelUpdate(RxVc_VpOffset);
++ ChannelUpdate(RxVc_OamTc);
++ ChannelUpdate(TxVp_AtmHeader);
++ ChannelUpdate(TxVp_OamTc);
++ ChannelUpdate(RxVp_AtmHeader);
++ ChannelUpdate(RxVp_OamCh);
++ ChannelUpdate(RxVp_OamTc);
++ ChannelUpdate(RxVp_OamToHost);
++ ChannelUpdate(RxVp_OamVcList);
++ ChannelUpdate(FwdUnkVc);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function opens the specified channel. The caller must populate
++ * the @p HalCh structure. CPHAL default values may be requested for any or all
++ * members of the @p HalCh structure by supplying a value of 0xFFFFFFFF for the
++ * given member. The @p OsSetup parameter is a pointer to an OS defined
++ * data structure. If the CPHAL later calls @c MallocRxBuffer(), this pointer
++ * is returned in that call.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param HalCh Per channel information structure. Implementation specific.
++ * @param OsSetup Pointer to an OS-defined data structure.
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_NULL_CH_STRUCT "EC_VAL_NULL_CH_STRUCT"<BR>
++ * @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
++ * @ref EC_VAL_CH_ALREADY_OPEN "EC_VAL_CH_ALREADY_OPEN"<BR>
++ * @ref EC_VAL_RX_STATE_RAM_NOT_CLEARED "EC_VAL_RX_STATE_RAM_NOT_CLEARED"<BR>
++ * @ref EC_VAL_TX_STATE_RAM_NOT_CLEARED "EC_VAL_TX_STATE_RAM_NOT_CLEARED"<BR>
++ * @ref EC_VAL_TCB_MALLOC_FAILED "EC_VAL_TCB_MALLOC_FAILED"<BR>
++ * @ref EC_VAL_RCB_MALLOC_FAILED "EC_VAL_RCB_MALLOC_FAILED"<BR>
++ * @ref EC_VAL_RX_BUFFER_MALLOC_FAILED "EC_VAL_RX_BUFFER_MALLOC_FAILED"<BR>
++ * @ref EC_VAL_LUT_NOT_READY "EC_VAL_LUT_NOT_READY"<BR>
++ */
++static int halChannelSetup(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup)
++ {
++ int Ch, Ret;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]halChannelSetup(HalDev:%08x, HalCh:%08x, OsSetup:%08x)\n", (bit32u)HalDev,
++ (bit32u)HalCh, (bit32u)OsSetup);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Verify proper device state */
++ if (HalDev->State < enInitialized)
++ return (EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE);
++
++ /* We require the channel structure to be passed, even if it only contains
++ the channel number */
++ if (HalCh == NULL)
++ {
++ return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_NULL_CH_STRUCT);
++ }
++
++ Ch = HalCh->Channel;
++
++ if ((Ch < 0) || (Ch > MAX_AAL5_CHAN))
++ {
++ return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_INVALID_CH);
++ }
++
++ /* if channel is already open, this call is invalid */
++ if ((HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE) || (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE))
++ {
++ return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_CH_ALREADY_OPEN);
++ }
++
++ /* channel is closed, but might be setup. If so, reopen the hardware channel. */
++ if ((HalDev->ChIsSetup[Ch][DIRECTION_TX] == FALSE) && (HalDev->ChIsSetup[Ch][DIRECTION_RX] == FALSE))
++ {
++ /* Setup channel configuration */
++ /* Store OS_SETUP */
++ HalDev->ChData[Ch].OsSetup = OsSetup; /* ~GSG 030508 */
++
++ /* setup HAL default values for this channel first */
++ ChannelConfigInit(HalDev, HalCh);
++
++ /* retrieve options.conf channel parameters */
++ /* currently ignoring return value, making the choice that it's okay if
++ the user does not supply channel configuration in the data store */
++ ChannelConfigGet(HalDev, HalCh);
++
++ /* update HalDev with data given in HalCh */
++ ChannelConfigUpdate(HalDev, HalCh);
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(8))
++ {
++ dbgChannelConfigDump(HalDev, Ch);
++ }
++#endif
++
++ /* HalDev->ChIsSetup[Ch][0] = TRUE; */
++ HalDev->ChIsSetup[Ch][DIRECTION_TX] = TRUE;
++ HalDev->ChIsSetup[Ch][DIRECTION_RX] = TRUE;
++
++ /* I don't initialize RcbStart or TcbStart here because their values may be
++ reused across several Setup/Teardown calls */
++ }
++
++ /* If the hardware has been opened (is out of reset), then configure the channel
++ in the hardware. NOTE: ChannelConfigApply calls the CPSAR ChannelSetup()! */
++ if (HalDev->State == enOpened)
++ {
++ Ret = ChannelConfigApply(HalDev, HalCh);
++ if (Ret) return (Ret);
++ }
++
++ return (EC_NO_ERRORS);
++ }
++
++/*
++ * This function configures the rate at which the OAM timer scheduler
++ * channels will be scheduled. The value of OamRate is the number of
++ * clock ticks between cell transmissions (if OAM function is sourcing
++ * cells), or the number of clock ticks between events or absence of events
++ * (if OAM function is sinking cells). The value of i indicates
++ * which OAM function to apply the rate to. A list is given below.
++ *
++ * @par Oam Function Values
++ * - 0 : Loopback source
++ * - 1 : F4 CC source
++ * - 2 : F5 CC source
++ * - 3 : F4 CC sink
++ * - 4 : F5 CC sink
++ * - 5 : F4 TX AIS source
++ * - 6 : F5 TX AIS source
++ * - 7 : F4 RX RDI source
++ * - 8 : F5 RX RDI source
++ * - 9 : F4 AIS monitor
++ * - 10 : F5 AIS monitor
++ *
++ * The following is information on how to calculate the OAM rate. There
++ * is only one OAM timer that is shared among all channels. Therefore, if
++ * you wanted an OAM source function (ex. F4 CC source) to generate 1 cell/sec
++ * across 8 channels, you would need to configure the OAM timer to schedule 8
++ * cells/sec. In addition, the credits are shared between segment and end-to-end
++ * type OAM cells, so if you were sending both types of cells, you would
++ * need to configure the OAM timer for 16 cells/sec. However, the clock
++ * rate must be specified in clock ticks between events. Using an example
++ * clock rate of 125 MHz, the rate in clock ticks can be calculated by
++ * dividing 125 Mhz by 16 cells/sec. The results is 7812500 ticks. Thus,
++ * every 7812500 clock cycles, an OAM cell will be generated for the F4 CC
++ * Source function.
++ */
++static void OamRateConfig(HAL_DEVICE *HalDev)
++ {
++ int i;
++ bit32u OamRate, Freq = HalDev->SarFrequency;
++
++ /* Configure OAM Timer State Block */
++ for (i=0; i<NUM_OAM_RATES; i++)
++ {
++ switch(i)
++ {
++ case 0: OamRate = ((Freq/1000)*HalDev->OamLbTimeout);
++ break;
++ case 1:
++ case 2:
++ case 5:
++ case 6:
++ case 7:
++ case 8: OamRate = (Freq/38);
++ break;
++ case 3:
++ case 4: OamRate = ((Freq*3) + (Freq/2))/38;
++ break;
++ case 9:
++ case 10: OamRate = ((Freq*2) + (Freq/2))/38;
++ break;
++ default: OamRate = (Freq*5);
++ break;
++ }
++
++ *(pOAM_TIMER_STATE_WORD_0(HalDev->dev_base) + (i*64) + 1) = OamRate;
++ }
++ }
++
++/**
++ * @ingroup AAL5_Functions
++ * This function is used to enable OAM functions (other than loopback) for a
++ * particular channel. The channel (embedded within OamConfig - see below) must
++ * have been configured for firmware OAM (not host OAM) for these configurations
++ * to take effect. More than one function may be enabled at one time.
++ * If more than one function is enabled, they must all be of the same level, all
++ * F4(VP) or all F5(VC).
++ *
++ * The usage of the OamConfig parameter is described through the table below. To
++ * initiate firmware OAM, set one or more bits in OamConfig corresponding to the
++ * various OAM functions. To disable firmware OAM functions, set bit 30 along
++ * with any other combination of bits to shutdown various OAM functions at once.
++ *
++ * Acronyms:
++ * e2e - end to end, seg - segment, CC - continuity check,
++ * AIS - Alarm Indication Signal
++ *
++ * @par Bit: Function: Description
++ * - 31: Reserved:
++ * - 30: Setup/Teardown: 0 - enable, 1 - disable (Note 1)
++ * - 29: F4 CC Source seg: 0 - no action, 1 - configure
++ * - 28: F4 CC Source e2e: 0 - no action, 1 - configure
++ * - 27: F4 AIS Source seg: 0 - no action, 1 - configure
++ * - 26: F4 AIS Source e2e: 0 - no action, 1 - configure
++ * - 25: F5 CC Source seg: 0 - no action, 1 - configure
++ * - 24: F5 CC Source e2e: 0 - no action, 1 - configure
++ * - 23: F5 AIS Source seg: 0 - no action, 1 - configure
++ * - 22: F5 AIS Source e2e: 0 - no action, 1 - configure
++ * - 21: F4 CC Sink seg: 0 - no action, 1 - configure
++ * - 20: F4 CC Sink e2e: 0 - no action, 1 - configure
++ * - 19: F5 CC Sink seg: 0 - no action, 1 - configure
++ * - 18: F5 CC Sink e2e: 0 - no action, 1 - configure
++ * - 17:8: Reserved:
++ * - 7:0: Channel: AAL5/AAL2 VC/VP channel (Note 2)
++ *
++ *
++ * Note 1: This bit must be clear to enable the specified OAM function.
++ * Note 2: This must specify the VC channel for F5 functions, and the VP
++ * channel for F4 functions.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param OamConfig A 32-bit integer field defined as follows:
++ */
++static void halOamFuncConfig(HAL_DEVICE *HalDev, unsigned int OamConfig)
++ {
++ /* GPR 0 */
++ SAR_PDSP_HOST_OAM_CONFIG_REG(HalDev->dev_base) = OamConfig;
++ }
++
++/**
++ * @ingroup AAL5_Functions
++ * This function is used to enable OAM loopback functions for a particular
++ * channel. The channel (embedded within OamConfig - see below) must have been
++ * configured for firmware OAM (not host OAM) for these configurations to take
++ * effect. Only one loopback function can be enabled at a time.
++ *
++ * The LLID is inserted into to the OAM cell's LLID field, and it specifies the
++ * LLID of the connection point in the network where the generated loopback cell
++ * should be turned around. The LLID is composed of 4 32-bit words, and this
++ * function expects the caller to pass an array of 4 words in the LLID field.
++ * The CorrelationTag is a 32-bit word that the PDSP uses to correlate loopback
++ * commands with loopback responses. It should simply be changed for each
++ * call, and there is no restriction on the value used for CorrelationTag.
++ *
++ * The usage of the OamConfig parameter is described through the table below. To
++ * initiate firmware OAM, set one of the bits corresponding to the
++ * various loopback OAM functions. Note that only one loopback source may be
++ * commanded at a time.
++ *
++ * Acronyms:
++ * e2e - end to end, seg - segment, LB - loopback
++ *
++ * @par Bit: Function: Description
++ * - 31:16: Reserved:
++ * - 15: F4 LB Source seg: 0 - no action, 1 - configure (Note 1)
++ * - 14: F4 LB Source seg: 0 - no action, 1 - configure (Note 1)
++ * - 13: F4 LB Source e2e: 0 - no action, 1 - configure (Note 1)
++ * - 12: F4 LB Source e2e: 0 - no action, 1 - configure (Note 1)
++ * - 11:8: Reserved:
++ * - 7:0: Channel: AAL5/AAL2 VC/VP channel (Note 2)
++ *
++ *
++ * Note 1: Only one LB function may be enabled at one time. Once enabled,
++ * the PDSP will time out after 5 seconds. The host must wait until it
++ * has received the result of the current LB request before initiating
++ * a new request. <BR>
++ * Note 2: This must specify the VC channel for F5 functions, and the VP
++ * channel for F4 functions.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param OamConfig A 32-bit integer field defined as follows:
++ * @param LLID Loopback Location Identifier (passed as 4 word array).
++ * Must be configured in big endian format.
++ * @param CorrelationTag 32-bit tag correlates loopback commands with loopback
++ * responses. Must be configured in big endian format.
++ *
++ */
++static void halOamLoopbackConfig(HAL_DEVICE *HalDev, unsigned int OamConfig, unsigned int *LLID, unsigned int CorrelationTag)
++ {
++ volatile bit32u *tmp;
++
++ /* test to see if this is a loopback command */
++ if (OamConfig & 0xf000)
++ {
++ /* write the OAM correlation tag (GPR 1) */
++ SAR_PDSP_OAM_CORR_REG(HalDev->dev_base) = CorrelationTag;
++
++ /* write the LLID */
++ tmp = pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base);
++
++ /* advance past the CPID */
++ tmp += 4;
++
++ *tmp++ = LLID[0];
++ *tmp++ = LLID[1];
++ *tmp++ = LLID[2];
++ *tmp = LLID[3];
++
++ /* GPR 0 */
++ SAR_PDSP_HOST_OAM_CONFIG_REG(HalDev->dev_base) = OamConfig;
++ }
++ }
++
++/*
++ * This function allows the host software to access any register directly.
++ * Primarily used for debug.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param RegOffset Hexadecimal offset to desired register (from device base addr)
++ *
++ * @return Volatile pointer to desired register.
++ */
++static volatile bit32u* halRegAccess(HAL_DEVICE *HalDev, bit32u RegOffset)
++ {
++ /* compute the register address */
++ return ((volatile bit32u *)(HalDev->dev_base + RegOffset));
++ }
++
++#ifdef __CPHAL_DEBUG
++static void dbgConfigDump(HAL_DEVICE *HalDev)
++ {
++ dbgPrintf(" AAL5 Inst %d Config Dump:\n", HalDev->Inst);
++ dbgPrintf(" Base :%08x, offset:%08d\n",
++ HalDev->dev_base, HalDev->offset);
++ dbgPrintf(" Interrupt:%08d, debug :%08d\n",
++ HalDev->interrupt, HalDev->debug);
++ osfuncSioFlush();
++ }
++#endif
++
++/**
++ * @ingroup CPHAL_Functions
++ * Performs a variety of control functions on the CPHAL module. It is used to
++ * modify/read configuration parameters and to initiate internal functions.
++ * The @p Key indicates the function to perform or the parameter to access (note
++ * that these Keys are identical to those used in accessing the configuration data
++ * store). @p Action is applicable to parameters only, and indicates what the
++ * CPHAL should do with the parameter (i.e. "Set", "Get", etc..). The actions
++ * for each parameter are defined in the module specific documentation.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param Key Key specifying the parameter to change or internal function to initiate. See module specific documentation for available keys.
++ * @param Action Specifies the action to take. See module specific documentation for available actions.
++ * @param Value Pointer to new value for given @p Key parameter ("Set"), or returned value of Key ("Get").
++ *
++ * @return EC_NO_ERRORS (ok).<BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_KEY_NOT_FOUND "EC_VAL_KEY_NOT_FOUND"<BR>
++ * @ref EC_VAL_ACTION_NOT_FOUND "EC_VAL_ACTION_NOT_FOUND"<BR>
++ */
++static int halControl(HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value)
++ {
++ int Level, Ch, KeyFound=0, ActionFound=0, rc=EC_NO_ERRORS, Queue;
++ char *TmpKey = (char *)Key;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]halControl(HalDev:%08x, Key:%s, Action:%s, Value:%08x)\n", (bit32u)HalDev,
++ Key, Action, (bit32u)Value);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Verify proper device state */
++ if (HalDev->State < enInitialized)
++ return (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_INVALID_STATE);
++
++ if (HalDev->OsFunc->Strcmpi(Key, "Debug") == 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ HalDev->debug = *(int *)Value;
++ /* also setup debug variable in CPSAR module */
++ rc = HalDev->SarFunc->Control(HalDev->SarDev, "Debug", "Set", Value);
++ }
++ }
++
++ if (HalDev->OsFunc->Strstr(Key, "FwdUnkVc.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("FwdUnkVc.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ HalDev->ChData[Ch].FwdUnkVc = *(int *)Value;
++
++ if ((HalDev->State == enOpened) && (HalDev->ChData[Ch].PktType == 3))
++ rc = HalDev->SarFunc->Control(HalDev->SarDev, Key, Action, Value);
++ }
++ }
++
++ /* +GSG 030407 */
++ if (HalDev->OsFunc->Strcmpi(Key, "OamMode") == 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ rc = HalDev->SarFunc->Control(HalDev->SarDev, Key, Action, Value);
++ }
++
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++ rc = HalDev->SarFunc->Control(HalDev->SarDev, Key, Action, Value);
++ }
++ }
++
++ /* +GSG 030307 */
++ if (HalDev->OsFunc->Strcmpi(Key, "Version") == 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++ *(const char **)Value = pszVersion_CPAAL5;
++ }
++ }
++
++ /* +GSG 030529 */
++ if (HalDev->OsFunc->Strcmpi(Key, "TurboDslErrors") == 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++ *(int *)Value = HalDev->TurboDslErrors;
++ }
++ }
++
++ /* +GSG 030416 */
++ if (HalDev->OsFunc->Strcmpi(Key, "F4_LB_Counter") == 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++ *(int *)Value = SAR_PDSP_OAM_F4_LB_COUNT_REG(HalDev->dev_base);
++ }
++ }
++
++ /* +GSG 030416 */
++ if (HalDev->OsFunc->Strcmpi(Key, "F5_LB_Counter") == 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++ *(int *)Value = SAR_PDSP_OAM_F5_LB_COUNT_REG(HalDev->dev_base);
++ }
++ }
++
++ if (HalDev->OsFunc->Strstr(Key, "Stats;") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++ TmpKey += HalDev->OsFunc->Strlen("Stats;");
++ Level = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++ TmpKey++;
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++ TmpKey++;
++ Queue = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++ TmpKey++;
++ StatsGet(HalDev, (void **)Value, Level, Ch, Queue);
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #100 */
++ if (HalDev->OsFunc->Strstr(Key, "Gfc.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("Gfc.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].Gfc = *(int *)Value;
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #100 */
++ if (HalDev->OsFunc->Strstr(Key, "Clp.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("Clp.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].Clp = *(int *)Value;
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #100 */
++ if (HalDev->OsFunc->Strstr(Key, "Pti.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("Pti.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].Pti = *(int *)Value;
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #100 */
++ if (HalDev->OsFunc->Strstr(Key, "CpcsUU.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("CpcsUU.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].CpcsUU = *(int *)Value;
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #100 */
++ if (HalDev->OsFunc->Strstr(Key, "TxVc_CellRate.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("TxVc_CellRate.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].TxVc_CellRate = *(int *)Value;
++
++ /* now, apply to PDSP state RAM */
++ if (HalDev->State == enOpened)
++ *(pPDSP_AAL5_TX_STATE_WORD_0(HalDev->dev_base)+(Ch*64))= HalDev->ChData[Ch].TxVc_CellRate;
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #100 */
++ if (HalDev->OsFunc->Strstr(Key, "TxVc_Mbs.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("TxVc_Mbs.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].TxVc_Mbs = *(int *)Value;
++
++ /* now, apply to PDSP state RAM */
++ if (HalDev->State == enOpened)
++ *(pPDSP_AAL5_TX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+2)= HalDev->ChData[Ch].TxVc_Mbs;
++ }
++ }
++
++ if (HalDev->OsFunc->Strstr(Key, "TxVc_AtmHeader.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("TxVc_AtmHeader.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].TxVc_AtmHeader = *(int *)Value;
++
++ /* now, apply to PDSP state RAM */
++ if (HalDev->State == enOpened)
++ *(pPDSP_AAL5_TX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+6)= HalDev->ChData[Ch].TxVc_AtmHeader;
++ }
++ }
++
++ if (HalDev->OsFunc->Strstr(Key, "TxVp_AtmHeader.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("TxVp_AtmHeader.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].TxVp_AtmHeader = *(int *)Value;
++
++ /* now, apply to PDSP state RAM */
++ if (HalDev->State == enOpened)
++ *(pPDSP_AAL5_TX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64))= HalDev->ChData[Ch].TxVp_AtmHeader;
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #100 */
++ if (HalDev->OsFunc->Strstr(Key, "TxVc_Pcr.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("TxVc_Pcr.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].TxVc_Pcr = *(int *)Value;
++
++ /* now, apply to PDSP state RAM */
++ if (HalDev->State == enOpened)
++ *(pPDSP_AAL5_TX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+4)= HalDev->ChData[Ch].TxVc_Pcr;
++ }
++ }
++
++ /* +GSG 030428 */
++ if (HalDev->OsFunc->Strstr(Key, "RxVc_OamCh.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVc_OamCh.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].RxVc_OamCh = (*(int *)Value) & 0xff;
++
++ /* now, apply to PDSP state RAM */
++ if (HalDev->State == enOpened)
++ *(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)) |= HalDev->ChData[Ch].RxVc_OamCh;
++ }
++ }
++
++ /* +GSG 030428 */
++ if (HalDev->OsFunc->Strstr(Key, "RxVp_OamCh.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVp_OamCh.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* first, store new value in our channel structure */
++ HalDev->ChData[Ch].RxVp_OamCh = (*(int *)Value) & 0xff;
++
++ /* now, apply to PDSP state RAM */
++ if (HalDev->State == enOpened)
++ *(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+1) |= HalDev->ChData[Ch].RxVp_OamCh;
++ }
++ }
++
++ /* +GSG 030304 */
++ /* Fixes PITS #98 */
++ if (HalDev->OsFunc->Strstr(Key, "PdspEnable") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++
++ /* this variable is controlled by the CPSAR module */
++ if (HalDev->State == enOpened)
++ {
++ rc=HalDev->SarFunc->Control(HalDev->SarDev, "PdspEnable", "Set", Value);
++ }
++ }
++ }
++
++ if (HalDev->OsFunc->Strstr(Key, "OamLbTimeout") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++
++ HalDev->OamLbTimeout = *(int *)Value;
++ /* this variable is controlled by the CPSAR module */
++ if (HalDev->State == enOpened)
++ {
++ *(pOAM_TIMER_STATE_WORD_0(HalDev->dev_base) + 1) =
++ ((HalDev->SarFrequency/1000) * HalDev->OamLbTimeout);
++ }
++ }
++ }
++
++ /* +GSG 030306 (PITS #114) */
++ if (HalDev->OsFunc->Strstr(Key, "DeviceCPID") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ unsigned int* local = (unsigned int *)Value;
++ ActionFound=1;
++ /* first, store new value in our hal structure */
++ HalDev->DeviceCPID[0] = local[0];
++ HalDev->DeviceCPID[1] = local[1];
++ HalDev->DeviceCPID[2] = local[2];
++ HalDev->DeviceCPID[3] = local[3];
++
++ /* now, apply to PDSP state RAM */
++ if (HalDev->State == enOpened)
++ {
++ *(bit32u *)(pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base) + 0) = HalDev->DeviceCPID[0];
++ *(bit32u *)(pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base) + 1) = HalDev->DeviceCPID[1];
++ *(bit32u *)(pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base) + 2) = HalDev->DeviceCPID[2];
++ *(bit32u *)(pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base) + 3) = HalDev->DeviceCPID[3];
++ }
++ }
++ }
++
++ /* +GSG 030304 */
++ /* Fixes PITS #99 */
++ if (HalDev->OsFunc->Strstr(Key, "StrictPriority") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++
++ /* used in halOpen to decide which interrupt handler to use */
++ HalDev->StrictPriority = *(int *)Value;
++ }
++ }
++
++ if (HalDev->OsFunc->Strstr(Key, hcMaxFrags) != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++
++ if ((*(int *)Value) > 0)
++ HalDev->MaxFrags = *(int *)Value;
++ else
++ rc = (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_INVALID_VALUE);
++ }
++
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++
++ *(int *)Value = HalDev->MaxFrags;
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #103 */
++ if (HalDev->OsFunc->Strstr(Key, "RxVc_RDICount.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVc_RDICount.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* PDSP's Rx VC State word 3 contains the value */
++ if (HalDev->State == enOpened)
++ {
++ *(int *)Value = (((*(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64))) & RDI_CNT_MASK)>>RDI_CNT_SHIFT);
++ }
++ }
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVc_RDICount.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* All sets write 0, this action is a clear only */
++ if (HalDev->State == enOpened)
++ {
++ (*(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64))) &=~ RDI_CNT_MASK;
++ }
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #103 */
++ if (HalDev->OsFunc->Strstr(Key, "RxVc_AISseg.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVc_AISseg.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* PDSP's Rx VC State word 3 contains the value */
++ if (HalDev->State == enOpened)
++ {
++ *(int *)Value = (((*(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+3)) & AIS_SEG_MASK)>>AIS_SEG_SHIFT);
++ }
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #103 */
++ if (HalDev->OsFunc->Strstr(Key, "RxVc_AISetoe.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVc_AISetoe.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* PDSP's Rx VC State word 3 contains the value */
++ if (HalDev->State == enOpened)
++ {
++ *(int *)Value = (((*(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+3)) & AIS_ETOE_MASK)>>AIS_ETOE_SHIFT);
++ }
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #103 */
++ if (HalDev->OsFunc->Strstr(Key, "RxVp_RDICount.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVp_RDICount.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* PDSP's Rx VC State word 3 contains the value */
++ if (HalDev->State == enOpened)
++ {
++ *(int *)Value = (((*(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+1)) & RDI_CNT_MASK)>>RDI_CNT_SHIFT);
++ }
++ }
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVp_RDICount.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* All sets write 0, this action is a clear only */
++ if (HalDev->State == enOpened)
++ {
++ (*(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+1)) &=~ RDI_CNT_MASK;
++ }
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #103 */
++ if (HalDev->OsFunc->Strstr(Key, "RxVp_AISseg.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVp_AISseg.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* PDSP's Rx VC State word 3 contains the value */
++ if (HalDev->State == enOpened)
++ {
++ *(int *)Value = (((*(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+2)) & AIS_SEG_MASK)>>AIS_SEG_SHIFT);
++ }
++ }
++ }
++
++ /* +GSG 030306 */
++ /* Fixes PITS #103 */
++ if (HalDev->OsFunc->Strstr(Key, "RxVp_AISetoe.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("RxVp_AISetoe.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* PDSP's Rx VC State word 3 contains the value */
++ if (HalDev->State == enOpened)
++ {
++ *(int *)Value = (((*(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+2)) & AIS_ETOE_MASK)>>AIS_ETOE_SHIFT);
++ }
++ }
++ }
++
++ if (KeyFound == 0)
++ rc = (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_KEY_NOT_FOUND);
++
++ if (ActionFound == 0)
++ rc = (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_ACTION_NOT_FOUND);
++
++ return(rc);
++ }
++
++/*
++ * Sets up HAL default configuration parameter values.
++ */
++static void ConfigInit(HAL_DEVICE *HalDev)
++ {
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]ConfigInit(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* configure some defaults with tnetx7300 values */
++ HalDev->dev_base = 0xa3000000;
++ HalDev->offset = 0;
++ HalDev->interrupt = 15;
++ HalDev->debug = 0;
++ HalDev->MaxFrags = 46;
++ HalDev->OamLbTimeout = 5000;
++ }
++
++/*
++ * Retrieve HAL configuration parameter values.
++ */
++static bit32u ConfigGet(HAL_DEVICE *HalDev)
++ {
++ bit32u Ret;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]ConfigGet(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* get the configuration parameters common to all modules */
++ Ret = ConfigGetCommon(HalDev);
++ if (Ret) return (EC_AAL5|Ret);
++
++ /* get AAL5 specific configuration parameters here */
++ Ret = HalDev->OsFunc->Control(HalDev->OsDev, hcSarFrequency, pszGET, &HalDev->SarFrequency); /* GSG +030416*/
++ if (Ret) /* GSG +030416*/
++ HalDev->SarFrequency = 200000000; /* 200 Mhz default */ /* GSG +030416*/
++
++ return (EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function initializes the CPHAL module. It gathers all
++ * necessary global configuration info from the configuration file, and
++ * performs initialization and configuration of the device. Note that
++ * the device operation is not started until the OS calls @c Open().
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_BASE_ADDR_NOT_FOUND "EC_VAL_BASE_ADDR_NOT_FOUND"<BR>
++ * @ref EC_VAL_RESET_BIT_NOT_FOUND "EC_VAL_RESET_BIT_NOT_FOUND"<BR>
++ * @ref EC_VAL_INTERRUPT_NOT_FOUND "EC_VAL_INTERRUPT_NOT_FOUND"<BR>
++ * @ref EC_VAL_OFFSET_NOT_FOUND "EC_VAL_OFFSET_NOT_FOUND"<BR>
++ */
++static int halInit(HAL_DEVICE *HalDev)
++ {
++ int i;
++ bit32u error_code;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]halInit(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Verify proper device state */
++ if (HalDev->State != enDevFound)
++ return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_INVALID_STATE);
++
++ /* Configure HAL defaults */
++ ConfigInit(HalDev);
++
++ /* Retrieve HAL configuration parameters from data store */
++ error_code = ConfigGet(HalDev);
++ if (error_code) return (error_code);
++
++ /* Other items (OAM related) that need to be passed in somehow */
++ HalDev->DeviceCPID[0] = 0xffffffff;
++ HalDev->DeviceCPID[1] = 0xffffffff;
++ HalDev->DeviceCPID[2] = 0xffffffff;
++ HalDev->DeviceCPID[3] = 0xffffffff;
++ HalDev->LBSourceLLID[0] = 0xffffffff;
++ HalDev->LBSourceLLID[1] = 0xffffffff;
++ HalDev->LBSourceLLID[2] = 0xffffffff;
++ HalDev->LBSourceLLID[3] = 0xffffffff;
++
++ /* Initialize SAR layer*/
++ error_code = HalDev->SarFunc->Init(HalDev->SarDev);
++ if (error_code) return (error_code);
++
++ /* Initialize various HalDev members. This is probably overkill, since these
++ are initialized in ChannelSetup() and HalDev is cleared in InitModule(). */
++ for (i=0; i<NUM_AAL5_CHAN; i++)
++ {
++ HalDev->InRxInt[i]=FALSE;
++ HalDev->ChIsOpen[i][DIRECTION_TX] = FALSE;
++ HalDev->ChIsOpen[i][DIRECTION_RX] = FALSE;
++ HalDev->TcbStart[i][0] = 0;
++ HalDev->TcbStart[i][1] = 0;
++ HalDev->RcbStart[i] = 0;
++ }
++
++ /* initialize SAR stats */
++ StatsClear(HalDev);
++
++ /* init Stat pointers */
++
++ /* even though these statistics may be for multiple channels/queues, i need
++ only configure the pointer to the beginning of the array, and I can index
++ from there if necessary */
++ StatsTable0[0].StatPtr = &HalDev->Stats.CrcErrors[0];
++ StatsTable0[1].StatPtr = &HalDev->Stats.LenErrors[0];
++ StatsTable0[2].StatPtr = &HalDev->Stats.AbortErrors[0];
++ StatsTable0[3].StatPtr = &HalDev->Stats.StarvErrors[0];
++
++ StatsTable1[0].StatPtr = &HalDev->Stats.DmaLenErrors[0];
++ StatsTable1[1].StatPtr = &HalDev->Stats.TxMisQCnt[0][0];
++ StatsTable1[2].StatPtr = &HalDev->Stats.RxMisQCnt[0];
++ StatsTable1[3].StatPtr = &HalDev->Stats.TxEOQCnt[0][0];
++ StatsTable1[4].StatPtr = &HalDev->Stats.RxEOQCnt[0];
++ StatsTable1[5].StatPtr = &HalDev->Stats.RxPacketsServiced[0];
++ StatsTable1[6].StatPtr = &HalDev->Stats.TxPacketsServiced[0][0];
++ StatsTable1[7].StatPtr = &HalDev->Stats.RxMaxServiced;
++ StatsTable1[8].StatPtr = &HalDev->Stats.TxMaxServiced[0][0];
++ StatsTable1[9].StatPtr = &HalDev->Stats.RxTotal;
++ StatsTable1[10].StatPtr = &HalDev->Stats.TxTotal;
++
++ StatsTable2[0].StatPtr = (bit32u *)&HalDev->RcbPool[0];
++ StatsTable2[1].StatPtr = &HalDev->RxActQueueCount[0];
++ StatsTable2[2].StatPtr = (bit32u *)&HalDev->RxActQueueHead[0];
++ StatsTable2[3].StatPtr = (bit32u *)&HalDev->RxActQueueTail[0];
++ StatsTable2[4].StatPtr = &HalDev->RxActive[0];
++ StatsTable2[5].StatPtr = (bit32u *)&HalDev->RcbStart[0];
++ StatsTable2[6].StatPtr = &HalDev->RxTeardownPending[0];
++ StatsTable2[7].StatPtr = (bit32u *)&HalDev->TcbPool[0][0];
++ StatsTable2[8].StatPtr = &HalDev->TxActQueueCount[0][0];
++ StatsTable2[9].StatPtr = (bit32u *)&HalDev->TxActQueueHead[0][0];
++ StatsTable2[10].StatPtr = (bit32u *)&HalDev->TxActQueueTail[0][0];
++ StatsTable2[11].StatPtr = &HalDev->TxActive[0][0];
++ StatsTable2[12].StatPtr = (bit32u *)&HalDev->TcbStart[0][0];
++ StatsTable2[13].StatPtr = &HalDev->TxTeardownPending[0];
++
++ StatsTable4[0].StatPtr = &HalDev->dev_base;
++ StatsTable4[1].StatPtr = &HalDev->offset;
++ StatsTable4[2].StatPtr = &HalDev->interrupt;
++ StatsTable4[3].StatPtr = &HalDev->debug;
++ StatsTable4[4].StatPtr = &HalDev->Inst;
++
++ StatsTable3[0].StatPtr = &HalDev->ChData[0].RxBufSize;
++ StatsTable3[1].StatPtr = &HalDev->ChData[0].RxBufferOffset;
++ StatsTable3[2].StatPtr = &HalDev->ChData[0].RxNumBuffers;
++ StatsTable3[3].StatPtr = &HalDev->ChData[0].RxServiceMax;
++ StatsTable3[4].StatPtr = &HalDev->ChData[0].TxNumBuffers;
++ StatsTable3[5].StatPtr = &HalDev->ChData[0].TxNumQueues;
++ StatsTable3[6].StatPtr = &HalDev->ChData[0].TxServiceMax;
++ StatsTable3[7].StatPtr = &HalDev->ChData[0].CpcsUU;
++ StatsTable3[8].StatPtr = &HalDev->ChData[0].Gfc;
++ StatsTable3[9].StatPtr = &HalDev->ChData[0].Clp;
++ StatsTable3[10].StatPtr = &HalDev->ChData[0].Pti;
++ StatsTable3[11].StatPtr = &HalDev->ChData[0].DaMask;
++ StatsTable3[12].StatPtr = &HalDev->ChData[0].Priority;
++ StatsTable3[13].StatPtr = &HalDev->ChData[0].PktType;
++ StatsTable3[14].StatPtr = &HalDev->ChData[0].Vci;
++ StatsTable3[15].StatPtr = &HalDev->ChData[0].Vpi;
++ StatsTable3[16].StatPtr = &HalDev->ChData[0].TxVc_CellRate;
++ StatsTable3[17].StatPtr = &HalDev->ChData[0].TxVc_QosType;
++ StatsTable3[18].StatPtr = &HalDev->ChData[0].TxVc_Mbs;
++ StatsTable3[19].StatPtr = &HalDev->ChData[0].TxVc_Pcr;
++
++ /* update device state */
++ HalDev->State = enInitialized;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(9))
++ dbgConfigDump(HalDev);
++#endif
++
++ return(EC_NO_ERRORS);
++ }
++
++/*
++ * Use this function to actually send after queuing multiple packets using
++ * Send(). This is a debug only function that should be removed - it was
++ * necessary to properly implement my loopback tests.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param Queue Queue number to kick.
++ *
++ * @return 0 OK, Non-Zero Not OK
++ */
++static int halKick(HAL_DEVICE *HalDev, int Queue)
++ {
++ int Ch;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]halKick(HalDev:%08x. Queue:%d)\n", (bit32u)HalDev, Queue);
++ osfuncSioFlush();
++ }
++#endif
++
++ for (Ch = 0; Ch < 16; Ch ++)
++ {
++ if ((!HalDev->TxActive[Ch][Queue]) && (HalDev->TxActQueueHead[Ch][Queue] != 0))
++ {
++ *(pTX_DMA_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+Queue)=
++ VirtToPhys(HalDev->TxActQueueHead[Ch][Queue]);
++ HalDev->TxActive[Ch][Queue]=TRUE;
++ }
++ }
++
++ return (EC_NO_ERRORS);
++ }
++
++/* +GSG 030305 For PITS #99
++ * Alternate interrupt handler that uses the INT_VECTOR in order to
++ * provide strict priority handling among channels, beginning with Ch 0.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param MoreWork (Output) When set to 1, indicates that there is more work to do.
++ * Caller should ensure that the value pointed at is set to 0
++ * prior to the call.
++ * @return 0 OK, non-zero error.
++ */
++static int DeviceIntAlt(HAL_DEVICE *HalDev, int *MoreWork)
++ {
++ int tmp, Ch, WorkFlag;
++ bit32u rc;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]DeviceIntAlt(HalDev:%08x, MoreWork:%08x)\n", (bit32u)HalDev, (bit32u)MoreWork);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Verify proper device state - important because a call prior to Open would
++ result in a lockup */
++ if (HalDev->State != enOpened)
++ return(EC_AAL5|EC_FUNC_DEVICE_INT_ALT|EC_VAL_INVALID_STATE);
++
++ if ((tmp=SAR_INTR_VECTOR(HalDev->dev_base))&INT_PENDING)
++ {
++ /*printf("\015 %d RxQ",HalDev->RxActQueueCount[0]);
++ HalDev->OsFunc->Control(HalDev->OsDev, enSIO_FLUSH, enNULL, 0); */
++
++ if (tmp&TXH_PEND)
++ {
++ /* decide which channel to service */
++ Ch = (SAR_INTR_VECTOR(HalDev->dev_base) & TXH_PEND_INVEC);
++
++ rc = TxInt(HalDev,Ch,0,&WorkFlag);
++ if (rc) return (rc);
++
++ if (WorkFlag == 1)
++ *MoreWork = 1;
++ }
++
++ if (tmp&TXL_PEND)
++ {
++ /* decide which channel to service */
++ Ch = ((SAR_INTR_VECTOR(HalDev->dev_base) & TXL_PEND_INVEC) >> 4);
++
++ rc = TxInt(HalDev,Ch,1,&WorkFlag);
++ if (rc) return (rc);
++
++ if (WorkFlag == 1)
++ *MoreWork = 1;
++ }
++
++ if (tmp&RX_PEND)
++ {
++ /* decide which channel to service */
++ Ch = ((SAR_INTR_VECTOR(HalDev->dev_base) & RX_PEND_INVEC) >> 8);
++
++ rc = RxInt(HalDev,Ch,&WorkFlag);
++ if (rc) return (rc);
++
++ if (WorkFlag == 1)
++ *MoreWork = 1;
++ }
++
++ if (tmp&STS_PEND)
++ {
++ /* GPR 2 code added for PITS 103 */
++ /* determine interrupt source */
++ Ch = ((SAR_INTR_VECTOR(HalDev->dev_base) & STS_PEND_INVEC) >> 12);
++
++ /* only if this is GPR 2 interrupt do we take action */
++ if (Ch == 26)
++ {
++ /* pass loopback result back to OS */
++ HalDev->OsFunc->Control(HalDev->OsDev, "OamLbResult", "Set",
++ (bit32u *)pSAR_PDSP_OAM_LB_RESULT_REG(HalDev->dev_base));
++ }
++
++ /* clear the interrupt */
++ SAR_STATUS_CLR_REG(HalDev->dev_base) |= 0x04000000;
++ }
++
++ if (tmp&AAL2_PEND)
++ {
++ /* no action defined */
++ }
++
++ SAR_INTR_VECTOR(HalDev->dev_base) = 0;
++ }
++
++ return (EC_NO_ERRORS);
++ }
++
++/*
++ * Called to service a module interrupt. This function determines
++ * what type of interrupt occurred and dispatches the correct handler.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param MoreWork (Output) When set to 1, indicates that there is more work to do.
++ * Caller should ensure that the value pointed at is set to 0
++ * prior to the call.
++ * @return 0 OK, non-zero error.
++ */
++static int DeviceInt(HAL_DEVICE *HalDev, int *MoreWork)
++ {
++ /*static int NextRxCh=0;
++ static int NextTxCh[2]={0,0};*/
++
++ int tmp, Ch, FirstCh, WorkFlag;
++ int NextTxLCh, NextTxHCh, NextRxCh;
++ bit32u rc;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]DeviceInt(HalDev:%08x, MoreWork:%08x)\n", (bit32u)HalDev, (bit32u)MoreWork);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Verify proper device state - important because a call prior to Open would
++ result in a lockup */
++ if (HalDev->State != enOpened)
++ return(EC_AAL5|EC_FUNC_DEVICE_INT|EC_VAL_INVALID_STATE);
++
++ NextTxHCh = HalDev->NextTxCh[0];
++ NextTxLCh = HalDev->NextTxCh[1];
++ NextRxCh = HalDev->NextRxCh;
++
++ /* service interrupts while there is more work to do */
++ /*while (((tmp=SAR_INTR_VECTOR(HalDev->dev_base))&INT_PENDING) && (TotalPkts < 500))*/
++ if ((tmp=SAR_INTR_VECTOR(HalDev->dev_base))&INT_PENDING)
++ {
++ /*printf("\015 %d RxQ",HalDev->RxActQueueCount[0]);
++ HalDev->OsFunc->Control(HalDev->OsDev, enSIO_FLUSH, enNULL, 0); */
++
++ if (tmp&TXH_PEND)
++ {
++ /* decide which channel to service */
++ FirstCh = NextTxHCh;
++ while (1)
++ {
++ Ch = NextTxHCh++;
++ if (NextTxHCh == 16)
++ NextTxHCh = 0;
++ if (SAR_TX_MASKED_STATUS(HalDev->dev_base) & (1<<Ch))
++ break;
++ if (FirstCh == NextTxHCh)
++ {
++ /* we checked every channel and still haven't found anything to do */
++ return (EC_AAL5|EC_FUNC_DEVICE_INT|EC_VAL_NO_TXH_WORK_TO_DO);
++ }
++ }
++
++ rc = TxInt(HalDev,Ch,0,&WorkFlag);
++ if (rc) return (rc);
++
++ if (WorkFlag == 1)
++ *MoreWork = 1;
++ }
++
++ if (tmp&TXL_PEND)
++ {
++ /* decide which channel to service */
++ FirstCh = NextTxLCh;
++ while (1)
++ {
++ Ch = NextTxLCh++;
++ if (NextTxLCh == 16)
++ NextTxLCh = 0;
++ if (SAR_TX_MASKED_STATUS(HalDev->dev_base) & (1<<(Ch+16)))
++ break;
++ if (FirstCh == NextTxLCh)
++ {
++ /* we checked every channel and still haven't found anything to do */
++ return (EC_AAL5|EC_FUNC_DEVICE_INT|EC_VAL_NO_TXL_WORK_TO_DO);
++ }
++ }
++
++ rc = TxInt(HalDev,Ch,1,&WorkFlag);
++ if (rc) return (rc);
++
++ if (WorkFlag == 1)
++ *MoreWork = 1;
++ }
++
++ if (tmp&RX_PEND)
++ {
++ FirstCh = NextRxCh;
++ while (1)
++ {
++ Ch = NextRxCh++;
++ if (NextRxCh == 16)
++ NextRxCh = 0;
++ if (SAR_RX_MASKED_STATUS(HalDev->dev_base) & (1 << Ch))
++ break; /* found a channel to service */
++ if (FirstCh == NextRxCh)
++ {
++ /* we checked every channel and still haven't found anything to do */
++ return (EC_AAL5|EC_FUNC_DEVICE_INT|EC_VAL_NO_RX_WORK_TO_DO);
++ }
++ }
++
++ rc = RxInt(HalDev,Ch, &WorkFlag);
++ if (rc) return (rc);
++
++ if (WorkFlag == 1)
++ *MoreWork = 1;
++ }
++
++ if (tmp&STS_PEND)
++ {
++ /* +GSG 030305 */
++ /* GPR 2 code added for PITS 103 */
++ /* determine interrupt source */
++ Ch = ((SAR_INTR_VECTOR(HalDev->dev_base) & STS_PEND_INVEC) >> 12);
++
++ /* only if this is GPR 2 interrupt do we take action */
++ if (Ch == 26)
++ {
++ /* pass loopback result back to OS */
++ HalDev->OsFunc->Control(HalDev->OsDev, "OamLbResult", "Set",
++ (bit32u *)pSAR_PDSP_OAM_LB_RESULT_REG(HalDev->dev_base));
++ }
++
++ /* clear the interrupt */
++ SAR_STATUS_CLR_REG(HalDev->dev_base) |= 0x04000000;
++ }
++
++ if (tmp&AAL2_PEND)
++ {
++ /* no action defined */
++ }
++
++ SAR_INTR_VECTOR(HalDev->dev_base) = 0;
++ }
++
++ HalDev->NextTxCh[0] = NextTxHCh;
++ HalDev->NextTxCh[1] = NextTxLCh;
++ HalDev->NextRxCh = NextRxCh;
++
++ /* This must be done by the upper layer */
++ /* SAR_EOI(HalDev->dev_base) = 0; */
++
++ return (EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function starts the operation of the CPHAL device. It takes the device
++ * out of reset, and calls @c IsrRegister(). This function should be called after
++ * calling the @c Init() function.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return EC_NO_ERRORS (ok).<BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_KEY_NOT_FOUND "EC_VAL_KEY_NOT_FOUND"<BR>
++ * @ref EC_VAL_FIRMWARE_TOO_LARGE "EC_VAL_FIRMWARE_TOO_LARGE"<BR>
++ * @ref EC_VAL_PDSP_LOAD_FAIL "EC_VAL_PDSP_LOAD_FAIL"<BR>
++ * @ref EC_VAL_RX_STATE_RAM_NOT_CLEARED "EC_VAL_RX_STATE_RAM_NOT_CLEARED"<BR>
++ * @ref EC_VAL_TX_STATE_RAM_NOT_CLEARED "EC_VAL_TX_STATE_RAM_NOT_CLEARED"<BR>
++ * @ref EC_VAL_TCB_MALLOC_FAILED "EC_VAL_TCB_MALLOC_FAILED"<BR>
++ * @ref EC_VAL_RCB_MALLOC_FAILED "EC_VAL_RCB_MALLOC_FAILED"<BR>
++ * @ref EC_VAL_RX_BUFFER_MALLOC_FAILED "EC_VAL_RX_BUFFER_MALLOC_FAILED"<BR>
++ * @ref EC_VAL_LUT_NOT_READY "EC_VAL_LUT_NOT_READY"<BR>
++ */
++static int halOpen(HAL_DEVICE *HalDev)
++ {
++ int i,Ret;
++ bit32 SarBase = HalDev->dev_base;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]halOpen(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Verify proper device state */
++ if (HalDev->State < enInitialized)
++ return (EC_AAL5|EC_FUNC_OPEN|EC_VAL_INVALID_STATE);
++
++ /* Open the SAR (this brings the whole device out of reset */
++ Ret = HalDev->SarFunc->Open(HalDev->SarDev); /* ~GSG 030410 */
++ if (Ret) /* +GSG 030410 */
++ return (Ret); /* +GSG 030410 */
++
++ /* Change device state */
++ HalDev->State = enOpened;
++
++
++#ifdef __CPHAL_DEBUG
++ /* print out the version information */
++ if (DBG(7))
++ {
++ dbgPrintf("[aal5 halOpen()]Module ID(AAL5-CPSAR):%d, Version:%2d.%02d\n",
++ (SAR_ID_REG(SarBase)&0xffff0000)>>16,
++ (SAR_ID_REG(SarBase)&0xff00)>>8,
++ SAR_ID_REG(SarBase)&0xff);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* GREG 11/1/02: The State RAM clearing code was previously in cpsar.c,
++ directly after device reset. I moved it here because I believe it is
++ AAL5 specific code. Also the MAX_CHAN was set to 19 in cpsar.c, which
++ would have caused this code to clear too much memory! */
++
++ /* NOTE: State RAM must be cleared prior to initializing the PDSP!! */
++
++ /* GSG 030416: Removed all of this. All PDSP State RAM is cleared
++ in CPSAR Open(). On Close(), all channels are torndown, thus all
++ AAL5 channel state RAM is cleared. */
++
++ /* Clear Rx State RAM */
++ /*for (i=0; i<NUM_AAL5_CHAN; i++)
++ for (j=0; j<NUM_RX_STATE_WORDS; j++)
++ *(pRX_DMA_STATE_WORD_0(SarBase) + (i*64) + j) = 0; */
++
++ /* Check that Rx DMA State RAM was cleared */
++ /*for (i=0; i<NUM_AAL5_CHAN; i++)
++ for (j=0; j<NUM_RX_STATE_WORDS; j++)
++ {
++ if (*(pRX_DMA_STATE_WORD_0(SarBase) + (i*64) + j) != 0)
++ {
++ return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_RX_STATE_RAM_NOT_CLEARED);
++ }
++ }*/
++
++ /* Clear Tx State RAM */
++ /*for (i=0; i<NUM_AAL5_CHAN; i++)
++ for (j=0; j<NUM_TX_STATE_WORDS; j++)
++ {
++ *(pTX_DMA_STATE_WORD_0(SarBase) + (i*64) + j) = 0;
++ }*/
++
++ /* Check that Tx DMA State RAM was cleared */
++ /*for (i=0; i<NUM_AAL5_CHAN; i++)
++ for (j=0; j<NUM_TX_STATE_WORDS; j++)
++ {
++ if (*(pTX_DMA_STATE_WORD_0(SarBase) + (i*64) + j) != 0)
++ {
++ return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_TX_STATE_RAM_NOT_CLEARED);
++ }
++ }*/
++
++ /* GSG +030523 Malloc space for the Rx fraglist */
++ HalDev->fraglist = HalDev->OsFunc->Malloc(HalDev->MaxFrags * sizeof(FRAGLIST));
++
++ /* For any channels that have been pre-initialized, set them up now */
++ for (i=0; i<NUM_AAL5_CHAN; i++)
++ {
++ if ((HalDev->ChIsSetup[i][0]==TRUE) && (HalDev->ChIsOpen[i][0]==FALSE))
++ {
++ CHANNEL_INFO HalChn;
++ HalChn.Channel = i;
++ Ret = ChannelConfigApply(HalDev, &HalChn);
++ if (Ret) return (Ret);
++ }
++ }
++
++ /* OAM code would be a candidate to go into ConfigApply */
++
++ /* Configure OAM Timer State Block */
++ OamRateConfig(HalDev); /* +GSG 030416 */
++
++ /* Setup OAM Configuration Block */
++ for (i=0; i<8; i++) /* ~GSG 030603 4->8 */
++ {
++ if (i < 4)
++ *(pOAM_CONFIG_BLOCK_WORD_0(SarBase) + i) = HalDev->DeviceCPID[i];
++ else
++ *(pOAM_CONFIG_BLOCK_WORD_0(SarBase) + i) = HalDev->LBSourceLLID[i-4];
++ }
++
++ /* Setup OAM Padding Block */
++ for (i=0; i<12; i++)
++ {
++ *(pOAM_PADDING_BLOCK_WORD_0(SarBase) + i) = ((i==11)?0x6a6a0000:0x6a6a6a6a);
++ }
++
++ /* Enable Tx CPPI DMA */
++ TX_CPPI_CTL_REG(HalDev->dev_base) = 1;
++
++ /* Enable Rx CPPI DMA */
++ RX_CPPI_CTL_REG(HalDev->dev_base) = 1;
++
++ /* +GSG 030306 */
++ /* Fix for PITS 103 */
++ /* Enable Host Interrupt for GPR 2 (OAM LB result register) */
++ SAR_HOST_INT_EN_SET_REG(HalDev->dev_base) |= 0x04000000;
++
++ /* +GSG 030304 to fix PITS 99 (if block is new)*/
++ if (HalDev->StrictPriority == 1)
++ {
++#ifdef __CPHAL_DEBUG
++ if (DBG(1))
++ {
++ dbgPrintf("[aal5->os]IsrRegister(OsDev:%08x, halIsr:%08x, Interrupt:%d)\n",
++ (bit32u)HalDev->OsDev, (bit32u)DeviceIntAlt, HalDev->interrupt);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* "register" the interrupt handler */
++ HalDev->OsFunc->IsrRegister(HalDev->OsDev, DeviceIntAlt, HalDev->interrupt);
++ }
++ else /* +GSG 030306 */
++ { /* +GSG 030306 */
++#ifdef __CPHAL_DEBUG
++ if (DBG(1))
++ {
++ dbgPrintf("[aal5->os]IsrRegister(OsDev:%08x, halIsr:%08x, Interrupt:%d)\n",
++ (bit32u)HalDev->OsDev, (bit32u)DeviceInt, HalDev->interrupt);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* "register" the interrupt handler */
++ HalDev->OsFunc->IsrRegister(HalDev->OsDev, DeviceInt, HalDev->interrupt);
++ } /* +GSG 030306 */
++
++ return(EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * Called to retrigger the interrupt mechanism after packets have been
++ * processed. Call this function when the HalISR function indicates that
++ * there is no more work to do. Proper use of this function will guarantee
++ * that interrupts are never missed.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ */
++static int halPacketProcessEnd(HAL_DEVICE *HalDev)
++ {
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]halPacketProcessEnd(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ SAR_EOI(HalDev->dev_base) = 0;
++ return (EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function probes for the instance of the CPHAL module. It will call
++ * the OS function @c DeviceFindInfo() to get the information required.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_DEVICE_NOT_FOUND "EC_VAL_DEVICE_NOT_FOUND"<BR>
++ */
++static int halProbe(HAL_DEVICE *HalDev)
++ {
++ int Ret;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]halProbe(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Verify hardware state is "enConnected */
++ if (HalDev->State != enConnected)
++ return (EC_AAL5|EC_FUNC_PROBE|EC_VAL_INVALID_STATE);
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(1))
++ {
++ dbgPrintf("[aal5->os]DeviceFindInfo(Inst:%d, DeviceName:%s, DeviceInfo:%08x)\n",
++ HalDev->Inst, "aal5", (bit32u)&HalDev->DeviceInfo);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Attempt to find the device information */
++ Ret = HalDev->OsFunc->DeviceFindInfo(HalDev->Inst, "aal5", &HalDev->DeviceInfo);
++ if (Ret)
++ return(EC_AAL5|EC_FUNC_PROBE|EC_VAL_DEVICE_NOT_FOUND);
++
++ /* Call Probe for supporting CPSAR layer */
++ Ret = HalDev->SarFunc->Probe(HalDev->SarDev);
++ if (Ret)
++ return(Ret);
++
++ /* Set device state to DevFound */
++ HalDev->State = enDevFound;
++
++ return(EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function shuts down the CPHAL module completely. The caller must call
++ * Close() to put the device in reset prior shutting down. This call will free
++ * the HalDev and the HAL function pointer structure, effectively ending
++ * communications between the driver and the CPHAL. Further use of the module
++ * must be initiated by a call to xxxInitModule(), which starts the entire process
++ * over again.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * Any error code from halClose().<BR>
++ */
++static int halShutdown(HAL_DEVICE *HalDev)
++ {
++ int Ch, Queue; /*GSG+030514*/
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]halShutdown(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Verify proper device state */
++ if (HalDev->State == enOpened)
++ halClose(HalDev, 3); /*GSG+030429*/
++
++ /* Buffer/descriptor resources may still need to be freed if a Close
++ Mode 1 was performed prior to Shutdown - clean up here */ /*GSG+030514*/
++ for (Ch=0; Ch<NUM_AAL5_CHAN; Ch++)
++ {
++ if (HalDev->RcbStart[Ch] != 0)
++ FreeRx(HalDev,Ch);
++
++ for(Queue=0; Queue<MAX_QUEUE; Queue++)
++ {
++ if (HalDev->TcbStart[Ch][Queue] != 0)
++ FreeTx(HalDev,Ch,Queue);
++ }
++ }
++
++ /* shutdown the CPSAR layer */
++ HalDev->SarFunc->Shutdown(HalDev->SarDev);
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(6))
++ {
++ dbgPrintf(" [aal5 halShutdown()]Free AAL5 function pointers\n");
++ osfuncSioFlush();
++ }
++ if (DBG(1)||DBG(3))
++ {
++ dbgPrintf("[aal5->os]Free(MemPtr:%08x)\n", (bit32u)HalDev->HalFuncPtr);
++ osfuncSioFlush();
++ }
++#endif
++ /* free the HalFunc */
++ HalDev->OsFunc->Free(HalDev->HalFuncPtr);
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(6))
++ {
++ dbgPrintf(" [aal5 halShutdown]Free HalDev\n");
++ osfuncSioFlush();
++ }
++ if (DBG(1)||DBG(3))
++ {
++ dbgPrintf("[aal5->os]Free(MemPtr:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++ /* free the HAL device */
++ HalDev->OsFunc->FreeDev(HalDev);
++
++ return(EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * Used to perform regular checks on the device. This function should be
++ * called at a regular interval specified by the @c Tick parameter.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return EC_NO_ERRORS (ok).<BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ */
++static int halTick(HAL_DEVICE *HalDev)
++ {
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[aal5]halTick(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ if (HalDev->State != enOpened)
++ return(EC_AAL5|EC_FUNC_TICK|EC_VAL_INVALID_STATE);
++
++ return(EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ *
++ * This function will:
++ * -# allocate a HalDev that will be used by the OS for future communications with the device
++ * -# save OsDev for use when calling OS functions
++ * -# allocate and populate HalFunc with the addresses of CPHAL functions.
++ * -# check OsFuncSize to see if it meets the minimum requirement.
++ * -# return the size of the HAL_FUNCTIONS structure through the HalFuncSize pointer. The OS
++ * should check this value to ensure that the HAL meets its minimum requirement.
++ *
++ * Version checking between the OS and the CPHAL is done using the OsFuncSize and
++ * HalFuncSize. Future versions of the CPHAL may add new functions to either
++ * HAL_FUNCTIONS or OS_FUNCTIONS, but will never remove functionality. This enables
++ * both the HAL and OS to check the size of the function structure to ensure that
++ * the current OS and CPHAL are compatible.
++ *
++ * Note: This is the only function exported by a CPHAL module.
++ *
++ * Please refer to the section "@ref hal_init" for example code.
++ *
++ * @param HalDev Pointer to pointer to CPHAL module information. This will
++ * be used by the OS when communicating to this module via
++ * CPHAL. Allocated during the call.
++ * @param OsDev Pointer to OS device information. This will be saved by
++ * the CPHAL and returned to the OS when required.
++ * @param HalFunc Pointer to pointer to structure containing function pointers for all CPHAL
++ * interfaces. Allocated during the call.
++ * @param OsFunc Pointer to structure containing function pointers for all OS
++ * provided interfaces. Must be allocated by OS prior to call.
++ * @param OsFuncSize Size of OS_FUNCTIONS structure.
++ * @param HalFuncSize Pointer to the size of the HAL_FUNCTIONS structure.
++ * @param Inst The instance number of the module to initialize. (start at
++ * 0).
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_OS_VERSION_NOT_SUPPORTED "EC_VAL_OS_VERSION_NOT_SUPPORTED"<BR>
++ * @ref EC_VAL_MALLOC_DEV_FAILED "EC_VAL_MALLOC_DEV_FAILED"<BR>
++ * @ref EC_VAL_MALLOC_FAILED "EC_VAL_MALLOC_FAILED"<BR>
++ */
++int xxxInitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ HAL_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++
++int cpaal5InitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ HAL_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst)
++ {
++ int rc, SarFuncSize;
++ HAL_DEVICE *HalPtr;
++ HAL_FUNCTIONS *HalFuncPtr;
++
++ /* NEW CODE */
++ if (OsFuncSize < sizeof(OS_FUNCTIONS))
++ return (EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_OS_VERSION_NOT_SUPPORTED);
++
++ HalPtr = (HAL_DEVICE *) OsFunc->MallocDev(sizeof(HAL_DEVICE));
++ if (!HalPtr)
++ return (EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_DEV_FAILED);
++
++ HalFuncPtr = (HAL_FUNCTIONS *) OsFunc->Malloc(sizeof(HAL_FUNCTIONS));
++ if (!HalFuncPtr)
++ return (EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_FAILED);
++
++ /* Initialize the size of hal functions */
++ *HalFuncSize = sizeof (HAL_FUNCTIONS);
++
++ /* clear the device structure */
++ OsFunc->Memset(HalPtr, 0, sizeof(HAL_DEVICE));
++
++ /* clear the function pointers */
++ OsFunc->Memset(HalFuncPtr, 0, sizeof(HAL_FUNCTIONS));
++
++ /* initialize the HAL_DEVICE structure */
++ HalPtr->OsDev = OsDev;
++ /*HalPtr->OsOpen = OsDev;*/
++ HalPtr->Inst = Inst;
++ HalPtr->OsFunc = OsFunc;
++
++ /* Supply pointers for the CPHAL API functions */
++ HalFuncPtr->RxReturn = halRxReturn;
++ HalFuncPtr->Init = halInit;
++ HalFuncPtr->Close = halClose;
++ HalFuncPtr->Send = halSend;
++ HalFuncPtr->ChannelSetup = halChannelSetup;
++ HalFuncPtr->ChannelTeardown = halChannelTeardown;
++ HalFuncPtr->Open = halOpen;
++ HalFuncPtr->Kick = halKick;
++ HalFuncPtr->RegAccess = halRegAccess;
++ HalFuncPtr->Probe = halProbe;
++ HalFuncPtr->Control = halControl;
++ HalFuncPtr->Tick = halTick;
++ HalFuncPtr->Shutdown = halShutdown;
++ HalFuncPtr->OamFuncConfig = halOamFuncConfig; /* +GSG 030306 */
++ HalFuncPtr->OamLoopbackConfig = halOamLoopbackConfig; /* ~GSG 030416 */
++
++ /* Temporary */
++ /*HalFuncPtr->StatsGetOld = StatsGet;*/
++ HalFuncPtr->PacketProcessEnd = halPacketProcessEnd;
++
++ /* Now, AAL5 must connect to the CPSAR layer */
++
++ /* Attach to SAR HAL Functions */
++ /*
++ cpsarInitModule(NULL, NULL, 0, NULL, &SarFuncSize, Inst);
++
++ if (SarFuncSize!=sizeof(CPSAR_FUNCTIONS))
++ return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_CPSAR_VERSION_NOT_SUPPORTED);
++
++ HalPtr->SarFunc = (CPSAR_FUNCTIONS *) OsFunc->Malloc(SarFuncSize);
++ */
++
++ rc = cpsarInitModule(&HalPtr->SarDev, OsDev, &HalPtr->SarFunc, OsFunc, sizeof(OS_FUNCTIONS), &SarFuncSize, Inst);
++
++ /* pass back the error value from the CPSAR layer if necessary */
++ if (rc)
++ return(rc);
++
++ /*
++ if (!HalPtr->SarDev)
++ return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_NULL_CPSAR_DEV);
++ */
++
++ /* Initialize the hardware state */
++ HalPtr->State = enConnected;
++
++ /* keep a reference to HalFuncPtr so I can free it later */
++ HalPtr->HalFuncPtr = HalFuncPtr;
++
++ /* pass the HalPtr back to the caller */
++ *HalDev = HalPtr;
++ *HalFunc = HalFuncPtr;
++
++ return(EC_NO_ERRORS);
++ }
+diff -urN linux.old/drivers/atm/sangam_atm/aal5sar.h linux.dev/drivers/atm/sangam_atm/aal5sar.h
+--- linux.old/drivers/atm/sangam_atm/aal5sar.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/aal5sar.h 2005-08-23 04:46:50.080846280 +0200
+@@ -0,0 +1,198 @@
++/**@file************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE: aal5sar.h
++ *
++ * DESCRIPTION:
++ * This file contains data structure definitions for the AAL5 HAL SAR.
++ *
++ * HISTORY:
++ * 28Feb02 Greg 1.00 Original Version created.
++ * 06Mar02 Greg 1.01 Documented structures.
++ * 18Jul02 Greg 1.02 Major reorganization
++ *
++ *****************************************************************************/
++#ifndef _INC_AAL5SAR
++#define _INC_AAL5SAR
++
++/** \namespace AAL5_Version
++This documents version 01.06.06 of the AAL5 CPHAL.
++*/
++const char *pszVersion_CPAAL5="CPAAL5 01.06.06 "__DATE__" "__TIME__;
++
++#include "cpsar_cpaal5.h"
++
++#define NUM_AAL5_CHAN 16
++#define MAX_AAL5_CHAN 15
++#define MAX_QUEUE 2
++#define MAX_DIRECTION 2
++
++#define PKT_TYPE_AAL5 0 /* +GSG 030508 */
++#define PKT_TYPE_NULL 1 /* +GSG 030508 */
++#define PKT_TYPE_OAM 2 /* +GSG 030508 */
++#define PKT_TYPE_TRANS 3 /* +GSG 030508 */
++#define ATM_HEADER_SIZE 4 /* +GSG 030508 */
++
++/*
++ * HAL Default Parameter Values
++ */
++#define CFG_TX_NUM_BUFS {256,256,256,256,256,256,256,256, 256,256,256,256,256,256,256,256}
++#define CFG_RX_NUM_BUFS {256,256,256,256,256,256,256,256, 256,256,256,256,256,256,256,256}
++#define CFG_RX_BUF_SIZE {1518,1518,1518,1518,1518,1518,1518,1518, 1518,1518,1518,1518,1518,1518,1518,1518}
++#define CFG_RX_BUF_OFFSET {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_TX_NUM_QUEUES {1,1,1,1,1,1,1,1, 1,1,1,1,1,1,1,1}
++#define CFG_CPCS_UU {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_DA_MASK {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_PRIORITY {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_PKT_TYPE {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_VCI {100,101,102,103,104,105,106,107, 108,109,110,111,112,113,114,115}
++#define CFG_VPI {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_CELL_RATE {0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4, 0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4}
++#define CFG_QOS_TYPE {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_MBS {8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8}
++#define CFG_PCR {1,1,1,1,1,1,1,1, 1,1,1,1,1,1,1,1}
++#define CFG_GFC {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_CLP {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_PTI {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
++#define CFG_RX_MAX_SERVICE {170,170,170,170,170,170,170,170, 170,170,170,170,170,170,170,170}
++#define CFG_TX_MAX_SERVICE {170,170,170,170,170,170,170,170, 170,170,170,170,170,170,170,170}
++
++static int cfg_tx_num_bufs[NUM_AAL5_CHAN] = CFG_TX_NUM_BUFS;
++static int cfg_rx_num_bufs[NUM_AAL5_CHAN] = CFG_RX_NUM_BUFS;
++static int cfg_rx_buf_size[NUM_AAL5_CHAN] = CFG_RX_BUF_SIZE;
++static int cfg_rx_buf_offset[NUM_AAL5_CHAN] = CFG_RX_BUF_OFFSET;
++static int cfg_tx_num_queues[NUM_AAL5_CHAN] = CFG_TX_NUM_QUEUES;
++static bit32u cfg_cpcs_uu[NUM_AAL5_CHAN] = CFG_CPCS_UU;
++static int cfg_da_mask[NUM_AAL5_CHAN] = CFG_DA_MASK;
++static int cfg_priority[NUM_AAL5_CHAN] = CFG_PRIORITY;
++static int cfg_pkt_type[NUM_AAL5_CHAN] = CFG_PKT_TYPE;
++static int cfg_vci[NUM_AAL5_CHAN] = CFG_VCI;
++static int cfg_vpi[NUM_AAL5_CHAN] = CFG_VPI;
++static bit32u cfg_cell_rate[NUM_AAL5_CHAN] = CFG_CELL_RATE;
++static int cfg_qos_type[NUM_AAL5_CHAN] = CFG_QOS_TYPE;
++static int cfg_mbs[NUM_AAL5_CHAN] = CFG_MBS;
++static int cfg_pcr[NUM_AAL5_CHAN] = CFG_PCR;
++static int cfg_gfc[NUM_AAL5_CHAN] = CFG_GFC;
++static int cfg_clp[NUM_AAL5_CHAN] = CFG_CLP;
++static int cfg_pti[NUM_AAL5_CHAN] = CFG_PTI;
++static int cfg_rx_max_service[NUM_AAL5_CHAN]= CFG_RX_MAX_SERVICE;
++static int cfg_tx_max_service[NUM_AAL5_CHAN]= CFG_TX_MAX_SERVICE;
++static char *channel_names[] = CHANNEL_NAMES;
++
++/*
++ * The HAL_FUNCTIONS struct defines the function pointers for all HAL functions
++ * accessible to upper layer software. It is populated by calling
++ * halInitModules().
++ *
++ * Note that this list is still under definition.
++ */
++
++/*
++ * This is the data structure for a transmit buffer descriptor. The first
++ * four 32-bit words of the BD represent the CPPI 3.0 defined buffer descriptor
++ * words. The other words are SAR/HAL implementation specific.
++ */
++typedef struct
++ {
++ bit32 HNext; /**< Hardware's pointer to next buffer descriptor */
++ bit32 BufPtr; /**< Pointer to the data buffer */
++ bit32 Off_BLen; /**< Contains buffer offset and buffer length */
++ bit32 mode; /**< SOP, EOP, Ownership, EOQ, Teardown Complete bits */
++ bit32 AtmHeader; /**< Atm Header to be used for each fragment */
++ bit32 Word5; /**< General control information for the packet */
++ bit32 Res6;
++ bit32 Res7;
++ void *Next;
++ void *OsInfo;
++#ifdef __CPHAL_DEBUG
++ bit32 DbgSop;
++ bit32 DbgData;
++ bit32 DbgFraglist;
++#endif
++ void *Eop;
++ }HAL_TCB;
++
++/*
++ * This is the data structure for a receive buffer descriptor. The first
++ * six 32-bit words of the BD represent the CPPI 3.0 defined buffer descriptor
++ * words. The other words are HAL implementation specific.
++ */
++typedef volatile struct hal_private
++ {
++ bit32 HNext; /**< Hardware's pointer to next buffer descriptor */
++ bit32 BufPtr; /**< Pointer to the data buffer */
++ bit32 Off_BLen; /**< Contains buffer offset and buffer length */
++ bit32 mode; /**< SOP, EOP, Ownership, EOQ, Teardown, Q Starv, Length */
++ bit32 AtmHeader;
++ bit32 UuCpi;
++ bit32 Res6;
++ bit32 Res7;
++ void *DatPtr;
++ void *Next;
++ void *OsInfo;
++ void *Eop;
++ bit32 FragCount;
++ bit32 Ch;
++ HAL_DEVICE *HalDev;
++ }HAL_RCB;
++
++
++#define MAX_NEEDS 512 /*MJH+030409*/
++/*
++ * This is the data structure for a generic HAL device. It contains all device
++ * specific data for a single instance of that device. This includes Rx/Tx
++ * buffer queues, device base address, reset bit, and other information.
++ */
++typedef struct hal_device
++ {
++ HAL_RCB *RcbPool[NUM_AAL5_CHAN];
++ bit32u rxbufseq;
++ bit32 RxActQueueCount[NUM_AAL5_CHAN];
++ HAL_RCB *RxActQueueHead[NUM_AAL5_CHAN];
++ HAL_RCB *RxActQueueTail[NUM_AAL5_CHAN];
++ bit32 RxActive[NUM_AAL5_CHAN];
++ bit32 dev_base;
++ HAL_TCB *TcbPool[NUM_AAL5_CHAN][MAX_QUEUE];
++ bit32 offset;
++ bit32 TxActQueueCount[NUM_AAL5_CHAN][MAX_QUEUE];
++ HAL_TCB *TxActQueueHead[NUM_AAL5_CHAN][MAX_QUEUE];
++ HAL_TCB *TxActQueueTail[NUM_AAL5_CHAN][MAX_QUEUE];
++ bit32 TxActive[NUM_AAL5_CHAN][MAX_QUEUE];
++ bit32 TxTeardownPending[NUM_AAL5_CHAN];
++ bit32 RxTeardownPending[NUM_AAL5_CHAN];
++ bit32 ChIsOpen[NUM_AAL5_CHAN][MAX_DIRECTION];
++ bit32 ChIsSetup[NUM_AAL5_CHAN][MAX_DIRECTION];
++ bit32 interrupt;
++ bit32 debug;
++ OS_DEVICE *OsDev;
++ OS_FUNCTIONS *OsFunc;
++ CPSAR_FUNCTIONS *SarFunc;
++ CPSAR_DEVICE *SarDev;
++ /*void *OsOpen;*/
++ /*FRAGLIST fraglist[MAX_FRAG];*/
++ FRAGLIST *fraglist;
++ char *TcbStart[NUM_AAL5_CHAN][MAX_QUEUE];
++ char *RcbStart[NUM_AAL5_CHAN];
++ /*bit32 RcbSize[NUM_AAL5_CHAN];*/
++ bit32 InRxInt[NUM_AAL5_CHAN];
++ STAT_INFO Stats;
++ bit32 Inst;
++ bit32u DeviceCPID[4];
++ bit32u LBSourceLLID[4];
++ CHANNEL_INFO ChData[NUM_AAL5_CHAN];
++ DEVICE_STATE State;
++ char *DeviceInfo;
++ HAL_FUNCTIONS *HalFuncPtr;
++ int NextRxCh;
++ int NextTxCh[2];
++ int StrictPriority; /* +GSG 030304 */
++ bit32u NeedsCount; /*MJH+030409*/
++ HAL_RECEIVEINFO *Needs[MAX_NEEDS]; /*MJH+030409*/
++ bit32u SarFrequency; /* +GSG 030416 */
++ int MaxFrags;
++ bit32u TurboDslErrors;
++ bit32u OamLbTimeout;
++ }HALDEVICE;
++
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/cpcommon_cpaal5.c linux.dev/drivers/atm/sangam_atm/cpcommon_cpaal5.c
+--- linux.old/drivers/atm/sangam_atm/cpcommon_cpaal5.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpcommon_cpaal5.c 2005-08-23 04:46:50.081846128 +0200
+@@ -0,0 +1,728 @@
++#ifndef _INC_CPCOMMON_C
++#define _INC_CPCOMMON_C
++
++#ifdef _CPHAL_CPMAC
++#include "cpremap_cpmac.c"
++#endif
++
++#ifdef _CPHAL_AAL5
++#include "cpremap_cpaal5.c"
++#endif
++
++#ifdef _CPHAL_CPSAR
++#include "cpremap_cpsar.c"
++#endif
++
++#ifdef _CPHAL_AAL2
++#include "cpremap_cpaal2.c"
++#endif
++
++/**
++@defgroup Common_Config_Params Common Configuration Parameters
++
++This section documents the configuration parameters that are valid across
++all CPHAL devices.
++@{
++*/
++/** This is the debug level. The field is bit defined, such that the user
++should set to 1 all the bits corresponding to desired debug outputs. The following
++are the meanings for each debug bit:
++- bit0 (LSB): CPHAL Function Trace
++- b1 : OS Function call trace
++- b2 : Critical section entry/exit
++- b3 : Memory allocation/destruction
++- b4 : Detailed information in Rx path
++- b5 : Detailed information in Tx path
++- b6 : Extended error information
++- b7 : General info
++*/
++static const char pszDebug[] = "debug";
++/** CPU Frequency. */
++/*static const char pszCpuFreq[] = "CpuFreq";*/ /*MJH-030403*/
++/** Base address for the module. */
++static const char pszBase[] = "base";
++/** Reset bit for the module. */
++static const char pszResetBit[] = "reset_bit";
++/** Reset base address for the module. */
++static const char pszResetBase[] = "ResetBase";
++/** Interrupt line for the module. */
++static const char pszIntLine[] = "int_line";
++/** VLYNQ offset for the module. Disregard if not using VLYNQ. */
++static const char pszOffset[] = "offset";
++/** The OS may "Get" this parameter, which is a pointer
++ to a character string that indicates the version of CPHAL. */
++static const char pszVer[] = "Version";
++/*@}*/
++
++/**
++@defgroup Common_Control_Params Common Keys for [os]Control()
++
++This section documents the keys used with the OS @c Control() interface that
++are required by CPHAL devices.
++
++@{
++*/
++/** Used to wait for an integer number of clock ticks, given as an integer
++ pointer in the @p Value parameter. No actions are defined. */
++static const char pszSleep[] = "Sleep";
++/** Requests the OS to flush it's IO buffers. No actions are defined. */
++static const char pszSioFlush[] = "SioFlush";
++/*@}*/
++
++static const char pszStateChange[] = "StateChange";
++static const char pszStatus[] = "Status";
++
++static const char pszGET[] = "Get";
++static const char pszSET[] = "Set";
++static const char pszCLEAR[] = "Clear";
++static const char pszNULL[] = "";
++static const char pszLocator[] = "Locator";
++static const char pszOff[] = "Off";
++static const char pszOn[] = "On";
++static const char hcMaxFrags[] = "MaxFrags";
++
++#ifdef _CPHAL_CPMAC
++
++/* New method for string constants */
++const char hcClear[] = "Clear";
++const char hcGet[] = "Get";
++const char hcSet[] = "Set";
++
++const char hcTick[] = "Tick";
++
++static const CONTROL_KEY KeyCommon[] =
++ {
++ {"" , enCommonStart},
++ {pszStatus , enStatus},
++ {pszOff , enOff},
++ {pszOn , enOn},
++ {pszDebug , enDebug},
++ {hcCpuFrequency , enCpuFreq}, /*MJH~030403*/
++ {"" , enCommonEnd}
++ };
++#endif
++
++/**
++@defgroup Common_Statistics Statistics
++
++A broad array of module statistics is available. Statistics values are accessed
++through the @c Control() interface of the CPHAL. There are 5 different levels
++of statistics, each of which correspond to a unique set of data. Furthermore,
++certain statistics data is indexed by using a channel number and Tx queue number.
++The following is a brief description of each statistics level, along with the
++indexes used for the level:
++
++- Level 0: Hardware Statistics (index with channel)
++- Level 1: CPHAL Software Statistics (channel, queue)
++- Level 2: CPHAL Flags (channel, queue)
++- Level 3: CPHAL Channel Configuration (channel)
++- Level 4: CPHAL General Configuration (no index)
++
++The caller requests statistics information by providing a Key string to the
++@c Control() API in the following format: "Stats;[Level #];[Ch #];[Queue #]".
++The only valid Action parameter for statistics usage is "Get".
++
++Code Examples:
++@code
++unsigned int *StatsData;
++
++# Get Level 0 stats for Channel 1
++HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
++
++# Get Level 2 stats for Channel 0, Queue 0
++HalFunc->Control(OsDev->HalDev, "Stats;2;0;0", "Get", &StatsData);
++
++# Get Level 4 stats
++HalFunc->Control(OsDev->HalDev, "Stats;4", "Get", &StatsData);
++@endcode
++
++The information returned in the Value parameter of @c Control() is an
++array of pointers to strings. The pointers are arranged in pairs.
++The first pointer is a pointer to a name string for a particular statistic.
++The next pointer is a pointer to a string containing the representation of
++the integer statistic value corresponding to the first pointer. This is followed
++by another pair of pointers, and so on, until a NULL pointer is encountered. The
++following is example code for processing the statistics data. Note that the OS
++is responsible for freeing the memory passed back through the Value parameter of
++@c Control().
++
++@code
++unsigned int *StatsData;
++
++# Get Level 0 stats for Channel 1
++HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
++
++# output Statistics data
++PrintStats(StatsData);
++
++# the upper layer is responsible for freeing stats info
++free(&StatsPtr);
++
++...
++
++void PrintStats(unsigned int *StatsPtr)
++ {
++ while(*StatsPtr)
++ {
++ printf("%20s:", (char *)*StatsPtr);
++ StatsPtr++;
++ printf("%11s\n", (char *)*StatsPtr);
++ StatsPtr++;
++ }
++ MySioFlush();
++ }
++@endcode
++
++Within each statistics level, there are several statistics defined. The statistics that
++are common to every CPPI module are listed below. In addition, each module may define
++extra statistics in each level, which will be documented within the module-specific
++documentation appendices.
++
++- Level 0 Statistics
++ - All level 0 statistics are module-specific.
++- Level 1 Statistics (CPHAL Software Statistics)
++ - DmaLenErrors: Incremented when the port DMA's more data than expected (per channel). (AAL5 Only)
++ - TxMisQCnt: Incremented when host queues a packet for transmission as the port finishes
++transmitting the previous last packet in the queue (per channel and queue).
++ - RxMisQCnt: Incremented when host queues adds buffers to a queue as the port finished the
++reception of the previous last packet in the queue (per channel).
++ - TxEOQCnt: Number of times the port has reached the end of the transmit queue (per channel and queue).
++ - RxEOQCnt: Number of times the port has reached the end of the receive queue (per channel).
++ - RxPacketsServiced: Number of received packets (per channel).
++ - TxPacketsServiced: Number of transmitted packets (per channel and queue).
++ - RxMaxServiced: Maximum number of packets that the CPHAL receive interrupt has serviced at a time (per channel).
++ - TxMaxServiced: Maximum number of packets that the CPHAL transmit interrupt has serviced at a time (per channel and queue).
++ - RxTotal: Total number of received packets, all channels.
++ - TxTotal: Total number of transmitted packets, all channels and queues.
++- Level 2 Statistics (CPHAL Flags)
++ - RcbPool: Pointer to receive descriptor pool (per channel).
++ - RxActQueueCount: Number of buffers currently available for receive (per channel).
++ - RxActQueueHead: Pointer to first buffer in receive queue (per channel).
++ - RxActQueueTail: Pointer to last buffer in receive queue (per channel).
++ - RxActive: 0 if inactive (no buffers available), or 1 if active (buffers available).
++ - RcbStart: Pointer to block of receive descriptors.
++ - RxTeardownPending: 1 if Rx teardown is pending but incomplete, 0 otherwise.
++ - TcbPool: Pointer to transmit descriptor pool (per channel and queue).
++ - TxActQueueCount: Number of buffers currently queued to be transmitted (per channel and queue).
++ - TxActQueueHead: Pointer to first buffer in transmit queue (per channel and queue).
++ - TxActQueueTail: Pointer to last buffer in transmit queue (per channel and queue).
++ - TxActive: 0 if inactive (no buffers to send), or 1 if active (buffers queued to send).
++ - TcbStart: Pointer to block of transmit descriptors.
++ - TxTeardownPending: 1 if Tx teardown is pending but incomplete, 0 otherwise.
++- Level 3 Statistics (CPHAL Channel Configuration)
++ - RxBufSize: Rx buffer size.
++ - RxBufferOffset: Rx buffer offset.
++ - RxNumBuffers: Number of Rx buffers.
++ - RxServiceMax: Maximum number of receive packets to service at a time.
++ - TxNumBuffers: Number of Tx buffer descriptors.
++ - TxNumQueues: Number of Tx queues to use.
++ - TxServiceMax: Maximum number of transmit packets to service at a time.
++- Level 4 Statistics (CPHAL General Configuration)
++ - Base Address: Base address of the module.
++ - Offset (VLYNQ): VLYNQ relative module offset.
++ - Interrupt Line: Interrupt number.
++ - Debug: Debug flag, 1 to enable debug.
++ - Inst: Instance number.
++*/
++
++/*
++ Data Type 0 = int display
++ Data Type 1 = hex display
++ Data Type 2 = channel structure, int display
++ Data Type 3 = queue index and int display
++ Data Type 4 = queue index and hex display
++*/
++#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC)) /* +GSG 030307 */
++static STATS_TABLE StatsTable0[] =
++ {
++#ifdef _CPHAL_AAL5
++ /* Name , Data Ptr, Data Type */
++ {"Crc Errors", 0, 0},
++ {"Len Errors", 0, 0},
++ {"Abort Errors", 0, 0},
++ {"Starv Errors", 0, 0}
++#endif
++#ifdef _CPHAL_CPMAC
++ {"Rx Good Frames", 0, 0}
++#endif
++ };
++
++static STATS_TABLE StatsTable1[] =
++ {
++ /* Name , Data Ptr, Data Type */
++ {"DmaLenErrors", 0, 0},
++ {"TxMisQCnt", 0, 3},
++ {"RxMisQCnt", 0, 0},
++ {"TxEOQCnt", 0, 3},
++ {"RxEOQCnt", 0, 0},
++ {"RxPacketsServiced", 0, 0},
++ {"TxPacketsServiced", 0, 3},
++ {"RxMaxServiced", 0, 0},
++ {"TxMaxServiced", 0, 3},
++ {"RxTotal", 0, 0},
++ {"TxTotal", 0, 0},
++ };
++
++static STATS_TABLE StatsTable2[] =
++ {
++ /* Name , Data Ptr, Data Type */
++ {"RcbPool", 0, 1},
++ {"RxActQueueCount", 0, 0},
++ {"RxActQueueHead", 0, 1},
++ {"RxActQueueTail", 0, 1},
++ {"RxActive", 0, 0},
++ {"RcbStart", 0, 1},
++ {"RxTeardownPending", 0, 0},
++ {"TcbPool", 0, 4},
++ {"TxActQueueCount", 0, 3},
++ {"TxActQueueHead", 0, 4},
++ {"TxActQueueTail", 0, 4},
++ {"TxActive", 0, 3},
++ {"TcbStart", 0, 4},
++ {"TxTeardownPending", 0, 0}
++ };
++
++static STATS_TABLE StatsTable3[] =
++ {
++ /* Name , Data Ptr, Data Type */
++ {"RxBufSize", 0, 2},
++ {"RxBufferOffset", 0, 2},
++ {"RxNumBuffers", 0, 2},
++ {"RxServiceMax", 0, 2},
++ {"TxNumBuffers", 0, 2},
++ {"TxNumQueues", 0, 2},
++ {"TxServiceMax", 0, 2},
++#ifdef _CPHAL_AAL5
++ {"CpcsUU", 0, 2},
++ {"Gfc", 0, 2},
++ {"Clp", 0, 2},
++ {"Pti", 0, 2},
++ {"DaMask", 0, 2},
++ {"Priority", 0, 2},
++ {"PktType", 0, 2},
++ {"Vci", 0, 2},
++ {"Vpi", 0, 2},
++ {"CellRate", 0, 2},
++ {"QosType", 0, 2},
++ {"Mbs", 0, 2},
++ {"Pcr", 0, 2}
++#endif
++ };
++
++static STATS_TABLE StatsTable4[] =
++ {
++ {"Base Address", 0, 1},
++ {"Offset (VLYNQ)", 0, 0},
++ {"Interrupt Line", 0, 0},
++ {"Debug", 0, 0},
++ {"Instance", 0, 0},
++#ifdef _CPHAL_AAL5
++ {"UniNni", 0, 0}
++#endif
++ };
++
++static STATS_DB StatsDb[] =
++ {
++ {(sizeof(StatsTable0)/sizeof(STATS_TABLE)), StatsTable0},
++ {(sizeof(StatsTable1)/sizeof(STATS_TABLE)), StatsTable1},
++ {(sizeof(StatsTable2)/sizeof(STATS_TABLE)), StatsTable2},
++ {(sizeof(StatsTable3)/sizeof(STATS_TABLE)), StatsTable3},
++ {(sizeof(StatsTable4)/sizeof(STATS_TABLE)), StatsTable4}
++ };
++#endif /* +GSG 030307 */
++
++#ifdef _CPHAL_CPMAC /* +RC 3.02 */
++static void resetWait(HAL_DEVICE *HalDev)
++ { /*+RC3.02*/
++ const int TickReset=64;
++ osfuncSleep((int*)&TickReset);
++ } /*+RC3.02*/
++#endif /* +RC 3.02 */
++
++/* I only define the reset base function for the modules
++ that can perform a reset. The AAL5 and AAL2 modules
++ do not perform a reset, that is done by the shared module
++ CPSAR */
++#if defined(_CPHAL_CPSAR) || defined(_CPHAL_CPMAC) || defined(_CPHAL_VDMAVT)
++/*
++ * Determines the reset register address to be used for a particular device.
++ * It will search the current device entry for Locator information. If the
++ * device is a root device, there will be no Locator information, and the
++ * function will find and return the root reset register. If a Locator value
++ * is found, the function will search each VLYNQ device entry in the system
++ * looking for a matching Locator. Once it finds a VLYNQ device entry with
++ * a matching Locator, it will extract the "ResetBase" parameter from that
++ * VLYNQ device entry (thus every VLYNQ entry must have the ResetBase parameter).
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param ResetBase Pointer to integer address of reset register.
++ *
++ * @return 0 OK, Non-zero not OK
++ */
++static int ResetBaseGet(HAL_DEVICE *HalDev, bit32u *ResetBase)
++ {
++ char *DeviceInfo = HalDev->DeviceInfo;
++ char *MyLocator, *NextLocator;
++ int Inst=1;
++ bit32u error_code;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpcommon]ResetBaseGet(HalDev:%08x, ResetBase:%08x)\n", (bit32u)HalDev, ResetBase);
++ osfuncSioFlush();
++ }
++#endif
++
++ error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &MyLocator);
++ if (error_code)
++ {
++ /* if no Locator value, device is on the root, so get the "reset" device */
++ error_code = HalDev->OsFunc->DeviceFindInfo(0, "reset", &DeviceInfo);
++ if (error_code)
++ {
++ return(EC_VAL_DEVICE_NOT_FOUND);
++ }
++
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "base", ResetBase);
++ if (error_code)
++ {
++ return(EC_VAL_BASE_ADDR_NOT_FOUND);
++ }
++
++ *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
++
++ /* found base address for root device, so we're done */
++ return (EC_NO_ERRORS);
++ }
++ else
++ {
++ /* we have a Locator value, so the device is remote */
++
++ /* Find a vlynq device with a matching locator value */
++ while ((HalDev->OsFunc->DeviceFindInfo(Inst, "vlynq", &DeviceInfo)) == EC_NO_ERRORS)
++ {
++ error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &NextLocator);
++ if (error_code)
++ {
++ /* no Locator value for this VLYNQ, so move on */
++ continue;
++ }
++ if (HalDev->OsFunc->Strcmpi(MyLocator, NextLocator)==0)
++ {
++ /* we have found a VLYNQ with a matching Locator, so extract the ResetBase */
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "ResetBase", ResetBase);
++ if (error_code)
++ {
++ return(EC_VAL_BASE_ADDR_NOT_FOUND);
++ }
++ *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
++
++ /* found base address for root device, so we're done */
++ return (EC_NO_ERRORS);
++ }
++ Inst++;
++ } /* while */
++ } /* else */
++
++ return (EC_NO_ERRORS);
++ }
++#endif
++
++#ifndef _CPHAL_AAL2 /* + RC 3.02 */
++static bit32u ConfigGetCommon(HAL_DEVICE *HalDev)
++ {
++ bit32u ParmValue;
++ bit32 error_code;
++ char *DeviceInfo = HalDev->DeviceInfo;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpcommon]ConfigGetCommon(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszBase, &ParmValue);
++ if (error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_BASE_ADDR_NOT_FOUND);
++ }
++ HalDev->dev_base = ((bit32u)PhysToVirtNoCache(ParmValue));
++
++#ifndef _CPHAL_AAL5
++#ifndef _CPHAL_AAL2
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszResetBit, &ParmValue);
++ if(error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BIT_NOT_FOUND);
++ }
++ HalDev->ResetBit = ParmValue;
++
++ /* Get reset base address */
++ error_code = ResetBaseGet(HalDev, &ParmValue);
++ if (error_code)
++ return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BASE_NOT_FOUND);
++ HalDev->ResetBase = ParmValue;
++#endif
++#endif
++
++#ifndef _CPHAL_CPSAR
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszIntLine,&ParmValue);
++ if (error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_INTERRUPT_NOT_FOUND);
++ }
++ HalDev->interrupt = ParmValue;
++#endif
++
++ /* only look for the offset if there is a Locator field, which indicates that
++ the module is a VLYNQ module */
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszLocator,&ParmValue);
++ if (!error_code)
++ {
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszOffset,&ParmValue);
++ if (error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_OFFSET_NOT_FOUND);
++ }
++ HalDev->offset = ParmValue;
++ }
++ else
++ HalDev->offset = 0;
++
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszDebug, &ParmValue);
++ if (!error_code) HalDev->debug = ParmValue;
++
++ return (EC_NO_ERRORS);
++ }
++#endif /* +RC 3.02 */
++
++#ifdef _CPHAL_CPMAC /* +RC 3.02 */
++static void StatsInit(HAL_DEVICE *HalDev) /* +() RC3.02 */
++ {
++ /* even though these statistics may be for multiple channels and
++ queues, i need only configure the pointer to the beginning
++ of the array, and I can index from there if necessary */
++
++#ifdef _CPHAL_AAL5
++ StatsTable0[0].StatPtr = &HalDev->Stats.CrcErrors[0];
++ StatsTable0[1].StatPtr = &HalDev->Stats.LenErrors[0];
++ StatsTable0[2].StatPtr = &HalDev->Stats.AbortErrors[0];
++ StatsTable0[3].StatPtr = &HalDev->Stats.StarvErrors[0];
++
++ StatsTable1[0].StatPtr = &HalDev->Stats.DmaLenErrors[0];
++ StatsTable1[1].StatPtr = &HalDev->Stats.TxMisQCnt[0][0];
++ StatsTable1[2].StatPtr = &HalDev->Stats.RxMisQCnt[0];
++ StatsTable1[3].StatPtr = &HalDev->Stats.TxEOQCnt[0][0];
++ StatsTable1[4].StatPtr = &HalDev->Stats.RxEOQCnt[0];
++ StatsTable1[5].StatPtr = &HalDev->Stats.RxPacketsServiced[0];
++ StatsTable1[6].StatPtr = &HalDev->Stats.TxPacketsServiced[0][0];
++ StatsTable1[7].StatPtr = &HalDev->Stats.RxMaxServiced;
++ StatsTable1[8].StatPtr = &HalDev->Stats.TxMaxServiced[0][0];
++ StatsTable1[9].StatPtr = &HalDev->Stats.RxTotal;
++ StatsTable1[10].StatPtr = &HalDev->Stats.TxTotal;
++#endif
++
++#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC))
++ StatsTable2[0].StatPtr = (bit32u *)&HalDev->RcbPool[0];
++ StatsTable2[1].StatPtr = &HalDev->RxActQueueCount[0];
++ StatsTable2[2].StatPtr = (bit32u *)&HalDev->RxActQueueHead[0];
++ StatsTable2[3].StatPtr = (bit32u *)&HalDev->RxActQueueTail[0];
++ StatsTable2[4].StatPtr = &HalDev->RxActive[0];
++ StatsTable2[5].StatPtr = (bit32u *)&HalDev->RcbStart[0];
++ StatsTable2[6].StatPtr = &HalDev->RxTeardownPending[0];
++ StatsTable2[7].StatPtr = (bit32u *)&HalDev->TcbPool[0][0];
++ StatsTable2[8].StatPtr = &HalDev->TxActQueueCount[0][0];
++ StatsTable2[9].StatPtr = (bit32u *)&HalDev->TxActQueueHead[0][0];
++ StatsTable2[10].StatPtr = (bit32u *)&HalDev->TxActQueueTail[0][0];
++ StatsTable2[11].StatPtr = &HalDev->TxActive[0][0];
++ StatsTable2[12].StatPtr = (bit32u *)&HalDev->TcbStart[0][0];
++ StatsTable2[13].StatPtr = &HalDev->TxTeardownPending[0];
++
++ StatsTable3[0].StatPtr = &HalDev->ChData[0].RxBufSize;
++ StatsTable3[1].StatPtr = &HalDev->ChData[0].RxBufferOffset;
++ StatsTable3[2].StatPtr = &HalDev->ChData[0].RxNumBuffers;
++ StatsTable3[3].StatPtr = &HalDev->ChData[0].RxServiceMax;
++ StatsTable3[4].StatPtr = &HalDev->ChData[0].TxNumBuffers;
++ StatsTable3[5].StatPtr = &HalDev->ChData[0].TxNumQueues;
++ StatsTable3[6].StatPtr = &HalDev->ChData[0].TxServiceMax;
++#ifdef _CPHAL_AAL5
++ StatsTable3[7].StatPtr = &HalDev->ChData[0].CpcsUU;
++ StatsTable3[8].StatPtr = &HalDev->ChData[0].Gfc;
++ StatsTable3[9].StatPtr = &HalDev->ChData[0].Clp;
++ StatsTable3[10].StatPtr = &HalDev->ChData[0].Pti;
++ StatsTable3[11].StatPtr = &HalDev->ChData[0].DaMask;
++ StatsTable3[12].StatPtr = &HalDev->ChData[0].Priority;
++ StatsTable3[13].StatPtr = &HalDev->ChData[0].PktType;
++ StatsTable3[14].StatPtr = &HalDev->ChData[0].Vci;
++ StatsTable3[15].StatPtr = &HalDev->ChData[0].Vpi;
++ StatsTable3[16].StatPtr = &HalDev->ChData[0].TxVc_CellRate;
++ StatsTable3[17].StatPtr = &HalDev->ChData[0].TxVc_QosType;
++ StatsTable3[18].StatPtr = &HalDev->ChData[0].TxVc_Mbs;
++ StatsTable3[19].StatPtr = &HalDev->ChData[0].TxVc_Pcr;
++#endif
++#endif
++
++ StatsTable4[0].StatPtr = &HalDev->dev_base;
++ StatsTable4[1].StatPtr = &HalDev->offset;
++ StatsTable4[2].StatPtr = &HalDev->interrupt;
++ StatsTable4[3].StatPtr = &HalDev->debug;
++ StatsTable4[4].StatPtr = &HalDev->Inst;
++ }
++#endif /* +RC 3.02 */
++
++#ifndef _CPHAL_CPSAR /* +RC 3.02 */
++#ifndef _CPHAL_AAL2 /* +RC 3.02 */
++/*
++ * Returns statistics information.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return 0
++ */
++static int StatsGet(HAL_DEVICE *HalDev, void **StatPtr, int Index, int Ch, int Queue)
++ {
++ int Size;
++ bit32u *AddrPtr;
++ char *DataPtr;
++ STATS_TABLE *StatsTable;
++ int i, NumberOfStats;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpcommon]StatsGet(HalDev:%08x, StatPtr:%08x)\n",
++ (bit32u)HalDev, (bit32u)StatPtr);
++ osfuncSioFlush();
++ }
++#endif
++
++ StatsTable = StatsDb[Index].StatTable;
++ NumberOfStats = StatsDb[Index].NumberOfStats;
++
++ Size = sizeof(bit32u)*((NumberOfStats*2)+1);
++ Size += (NumberOfStats*11);
++ *StatPtr = (bit32u *)HalDev->OsFunc->Malloc(Size);
++
++ AddrPtr = (bit32u *) *StatPtr;
++ DataPtr = (char *)AddrPtr;
++ DataPtr += sizeof(bit32u)*((NumberOfStats*2)+1);
++
++ for (i=0; i<NumberOfStats; i++)
++ {
++ *AddrPtr++ = (bit32u)StatsTable[i].StatName;
++ *AddrPtr++ = (bit32u)DataPtr;
++ if (&StatsTable[i].StatPtr[Ch] != 0)
++ {
++ switch(StatsTable[i].DataType)
++ {
++ case 0:
++ HalDev->OsFunc->Sprintf(DataPtr, "%d", (bit32u *)StatsTable[i].StatPtr[Ch]);
++ break;
++ case 1:
++ HalDev->OsFunc->Sprintf(DataPtr, "0x%x", (bit32u *)StatsTable[i].StatPtr[Ch]);
++ break;
++ case 2:
++ HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch * (sizeof(CHANNEL_INFO)/4))));
++ break;
++ case 3:
++ HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
++ break;
++ case 4:
++ HalDev->OsFunc->Sprintf(DataPtr, "0x%x", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
++ break;
++ default:
++ /* invalid data type, due to CPHAL programming error */
++ break;
++ }
++ }
++ else
++ {
++ /* invalid statistics pointer, probably was not initialized */
++ }
++ DataPtr += HalDev->OsFunc->Strlen(DataPtr) + 1;
++ }
++
++ *AddrPtr = (bit32u) 0;
++
++ return (EC_NO_ERRORS);
++ }
++#endif /* +RC 3.02 */
++#endif /* +RC 3.02 */
++
++#ifdef _CPHAL_CPMAC
++static void gpioFunctional(int base, int bit)
++ { /*+RC3.02*/
++ bit32u GpioEnr = base + 0xC;
++ /* To make functional, set to zero */
++ *(volatile bit32u *)(GpioEnr) &= ~(1 << bit); /*+RC3.02*/
++ } /*+RC3.02*/
++
++
++/*+RC3.02*/
++/* Common function, Checks to see if GPIO should be in functional mode */
++static void gpioCheck(HAL_DEVICE *HalDev, void *moduleDeviceInfo)
++ { /*+RC3.02*/
++ int rc;
++ void *DeviceInfo;
++ char *pszMuxBits;
++ char pszMuxBit[20];
++ char *pszTmp;
++ char szMuxBit[20];
++ char *ptr;
++ int base;
++ int reset_bit;
++ int bit;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++
++ rc = OsFunc->DeviceFindParmValue(moduleDeviceInfo, "gpio_mux",&pszTmp);
++ if(rc) return;
++ /* gpio entry found, get GPIO register info and make functional */
++
++ /* temp copy until FinParmValue fixed */
++ ptr = &szMuxBit[0];
++ while ((*ptr++ = *pszTmp++));
++
++ pszMuxBits = &szMuxBit[0];
++
++ rc = OsFunc->DeviceFindInfo(0,"gpio",&DeviceInfo);
++ if(rc) return;
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "base",&base);
++ if(rc) return;
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",&reset_bit);
++ if(rc) return;
++
++ /* If GPIO still in reset, then exit */
++ if((VOLATILE32(HalDev->ResetBase) & (1 << reset_bit)) == 0)
++ return;
++ /* format for gpio_mux is gpio_mux = <int>;<int>;<int>...*/
++ while (*pszMuxBits)
++ {
++ pszTmp = &pszMuxBit[0];
++ if(*pszMuxBits == ';') pszMuxBits++;
++ while ((*pszMuxBits != ';') && (*pszMuxBits != '\0'))
++ {
++ osfuncSioFlush();
++ /*If value not a number, skip */
++ if((*pszMuxBits < '0') || (*pszMuxBits > '9'))
++ pszMuxBits++;
++ else
++ *pszTmp++ = *pszMuxBits++;
++ }
++ *pszTmp = '\0';
++ bit = OsFunc->Strtoul(pszMuxBit, &pszTmp, 10);
++ gpioFunctional(base, bit);
++ resetWait(HalDev); /* not sure if this is needed */
++ }
++ } /*+RC3.02*/
++#endif /* CPMAC */
++
++#ifdef _CPHAL_AAL5
++const char hcSarFrequency[] = "SarFreq";
++#endif
++
++#endif /* _INC */
+diff -urN linux.old/drivers/atm/sangam_atm/cpcommon_cpaal5.h linux.dev/drivers/atm/sangam_atm/cpcommon_cpaal5.h
+--- linux.old/drivers/atm/sangam_atm/cpcommon_cpaal5.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpcommon_cpaal5.h 2005-08-23 04:46:50.082845976 +0200
+@@ -0,0 +1,79 @@
++#ifndef _INC_CPCOMMON_H
++#define _INC_CPCOMMON_H
++
++#define VOLATILE32(addr) (*(volatile bit32u *)(addr))
++#ifndef dbgPrintf
++#define dbgPrintf HalDev->OsFunc->Printf
++#endif
++
++#define ChannelUpdate(Field) if(HalChn->Field != 0xFFFFFFFF) HalDev->ChData[Ch].Field = HalChn->Field
++
++#define DBG(level) (HalDev->debug & (1<<(level)))
++/*
++#define DBG0() DBG(0)
++#define DBG1() DBG(1)
++#define DBG2() DBG(2)
++#define DBG3() DBG(3)
++#define DBG4() DBG(4)
++#define DBG5() DBG(5)
++#define DBG6() DBG(6)
++#define DBG7() DBG(7)
++*/
++
++/*
++ * List of defined actions for use with Control().
++ */
++typedef enum
++ {
++ enGET=0, /**< Get the value associated with a key */
++ enSET, /**< Set the value associates with a key */
++ enCLEAR, /**<Clear the value */
++ enNULL /**< No data action, used to initiate a service or send a message */
++ }ACTION;
++
++/*
++ * Enumerated hardware states.
++ */
++typedef enum
++ {
++ enConnected=1, enDevFound, enInitialized, enOpened
++ }DEVICE_STATE;
++
++typedef enum
++ {
++ enCommonStart=0,
++ /* General */
++ enOff, enOn, enDebug,
++ /* Module General */
++ enCpuFreq,
++ enStatus,
++ enCommonEnd
++ }COMMON_KEY;
++
++typedef struct
++ {
++ const char *strKey;
++ int enKey;
++ }CONTROL_KEY;
++
++typedef struct
++ {
++ char *StatName;
++ unsigned int *StatPtr;
++ int DataType; /* 0: int, 1: hex int, 2:channel data */
++ }STATS_TABLE;
++
++typedef struct
++ {
++ int NumberOfStats;
++ STATS_TABLE *StatTable;
++ }STATS_DB;
++
++#define osfuncSioFlush() HalDev->OsFunc->Control(HalDev->OsDev,"SioFlush",pszNULL,0)
++#define osfuncSleep(Ticks) HalDev->OsFunc->Control(HalDev->OsDev,pszSleep,pszNULL,Ticks)
++#define osfuncStateChange() HalDev->OsFunc->Control(HalDev->OsDev,pszStateChange,pszNULL,0)
++
++#define CHANNEL_NAMES {"Ch0","Ch1","Ch2","Ch3","Ch4","Ch5","Ch6","Ch7","Ch8","Ch9","Ch10","Ch11","Ch12","Ch13","Ch14","Ch15"}
++
++#endif
++
+diff -urN linux.old/drivers/atm/sangam_atm/cpcommon_cpsar.c linux.dev/drivers/atm/sangam_atm/cpcommon_cpsar.c
+--- linux.old/drivers/atm/sangam_atm/cpcommon_cpsar.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpcommon_cpsar.c 2005-08-23 04:46:50.082845976 +0200
+@@ -0,0 +1,728 @@
++#ifndef _INC_CPCOMMON_C
++#define _INC_CPCOMMON_C
++
++#ifdef _CPHAL_CPMAC
++#include "cpremap_cpmac.c"
++#endif
++
++#ifdef _CPHAL_AAL5
++#include "cpremap_cpaal5.c"
++#endif
++
++#ifdef _CPHAL_CPSAR
++#include "cpremap_cpsar.c"
++#endif
++
++#ifdef _CPHAL_AAL2
++#include "cpremap_cpaal2.c"
++#endif
++
++/**
++@defgroup Common_Config_Params Common Configuration Parameters
++
++This section documents the configuration parameters that are valid across
++all CPHAL devices.
++@{
++*/
++/** This is the debug level. The field is bit defined, such that the user
++should set to 1 all the bits corresponding to desired debug outputs. The following
++are the meanings for each debug bit:
++- bit0 (LSB): CPHAL Function Trace
++- b1 : OS Function call trace
++- b2 : Critical section entry/exit
++- b3 : Memory allocation/destruction
++- b4 : Detailed information in Rx path
++- b5 : Detailed information in Tx path
++- b6 : Extended error information
++- b7 : General info
++*/
++static const char pszDebug[] = "debug";
++/** CPU Frequency. */
++/*static const char pszCpuFreq[] = "CpuFreq";*/ /*MJH-030403*/
++/** Base address for the module. */
++static const char pszBase[] = "base";
++/** Reset bit for the module. */
++static const char pszResetBit[] = "reset_bit";
++/** Reset base address for the module. */
++static const char pszResetBase[] = "ResetBase";
++/** Interrupt line for the module. */
++static const char pszIntLine[] = "int_line";
++/** VLYNQ offset for the module. Disregard if not using VLYNQ. */
++static const char pszOffset[] = "offset";
++/** The OS may "Get" this parameter, which is a pointer
++ to a character string that indicates the version of CPHAL. */
++static const char pszVer[] = "Version";
++/*@}*/
++
++/**
++@defgroup Common_Control_Params Common Keys for [os]Control()
++
++This section documents the keys used with the OS @c Control() interface that
++are required by CPHAL devices.
++
++@{
++*/
++/** Used to wait for an integer number of clock ticks, given as an integer
++ pointer in the @p Value parameter. No actions are defined. */
++static const char pszSleep[] = "Sleep";
++/** Requests the OS to flush it's IO buffers. No actions are defined. */
++static const char pszSioFlush[] = "SioFlush";
++/*@}*/
++
++static const char pszStateChange[] = "StateChange";
++static const char pszStatus[] = "Status";
++
++static const char pszGET[] = "Get";
++static const char pszSET[] = "Set";
++static const char pszCLEAR[] = "Clear";
++static const char pszNULL[] = "";
++static const char pszLocator[] = "Locator";
++static const char pszOff[] = "Off";
++static const char pszOn[] = "On";
++static const char hcMaxFrags[] = "MaxFrags";
++
++#ifdef _CPHAL_CPMAC
++
++/* New method for string constants */
++const char hcClear[] = "Clear";
++const char hcGet[] = "Get";
++const char hcSet[] = "Set";
++
++const char hcTick[] = "Tick";
++
++static const CONTROL_KEY KeyCommon[] =
++ {
++ {"" , enCommonStart},
++ {pszStatus , enStatus},
++ {pszOff , enOff},
++ {pszOn , enOn},
++ {pszDebug , enDebug},
++ {hcCpuFrequency , enCpuFreq}, /*MJH~030403*/
++ {"" , enCommonEnd}
++ };
++#endif
++
++/**
++@defgroup Common_Statistics Statistics
++
++A broad array of module statistics is available. Statistics values are accessed
++through the @c Control() interface of the CPHAL. There are 5 different levels
++of statistics, each of which correspond to a unique set of data. Furthermore,
++certain statistics data is indexed by using a channel number and Tx queue number.
++The following is a brief description of each statistics level, along with the
++indexes used for the level:
++
++- Level 0: Hardware Statistics (index with channel)
++- Level 1: CPHAL Software Statistics (channel, queue)
++- Level 2: CPHAL Flags (channel, queue)
++- Level 3: CPHAL Channel Configuration (channel)
++- Level 4: CPHAL General Configuration (no index)
++
++The caller requests statistics information by providing a Key string to the
++@c Control() API in the following format: "Stats;[Level #];[Ch #];[Queue #]".
++The only valid Action parameter for statistics usage is "Get".
++
++Code Examples:
++@code
++unsigned int *StatsData;
++
++# Get Level 0 stats for Channel 1
++HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
++
++# Get Level 2 stats for Channel 0, Queue 0
++HalFunc->Control(OsDev->HalDev, "Stats;2;0;0", "Get", &StatsData);
++
++# Get Level 4 stats
++HalFunc->Control(OsDev->HalDev, "Stats;4", "Get", &StatsData);
++@endcode
++
++The information returned in the Value parameter of @c Control() is an
++array of pointers to strings. The pointers are arranged in pairs.
++The first pointer is a pointer to a name string for a particular statistic.
++The next pointer is a pointer to a string containing the representation of
++the integer statistic value corresponding to the first pointer. This is followed
++by another pair of pointers, and so on, until a NULL pointer is encountered. The
++following is example code for processing the statistics data. Note that the OS
++is responsible for freeing the memory passed back through the Value parameter of
++@c Control().
++
++@code
++unsigned int *StatsData;
++
++# Get Level 0 stats for Channel 1
++HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
++
++# output Statistics data
++PrintStats(StatsData);
++
++# the upper layer is responsible for freeing stats info
++free(&StatsPtr);
++
++...
++
++void PrintStats(unsigned int *StatsPtr)
++ {
++ while(*StatsPtr)
++ {
++ printf("%20s:", (char *)*StatsPtr);
++ StatsPtr++;
++ printf("%11s\n", (char *)*StatsPtr);
++ StatsPtr++;
++ }
++ MySioFlush();
++ }
++@endcode
++
++Within each statistics level, there are several statistics defined. The statistics that
++are common to every CPPI module are listed below. In addition, each module may define
++extra statistics in each level, which will be documented within the module-specific
++documentation appendices.
++
++- Level 0 Statistics
++ - All level 0 statistics are module-specific.
++- Level 1 Statistics (CPHAL Software Statistics)
++ - DmaLenErrors: Incremented when the port DMA's more data than expected (per channel). (AAL5 Only)
++ - TxMisQCnt: Incremented when host queues a packet for transmission as the port finishes
++transmitting the previous last packet in the queue (per channel and queue).
++ - RxMisQCnt: Incremented when host queues adds buffers to a queue as the port finished the
++reception of the previous last packet in the queue (per channel).
++ - TxEOQCnt: Number of times the port has reached the end of the transmit queue (per channel and queue).
++ - RxEOQCnt: Number of times the port has reached the end of the receive queue (per channel).
++ - RxPacketsServiced: Number of received packets (per channel).
++ - TxPacketsServiced: Number of transmitted packets (per channel and queue).
++ - RxMaxServiced: Maximum number of packets that the CPHAL receive interrupt has serviced at a time (per channel).
++ - TxMaxServiced: Maximum number of packets that the CPHAL transmit interrupt has serviced at a time (per channel and queue).
++ - RxTotal: Total number of received packets, all channels.
++ - TxTotal: Total number of transmitted packets, all channels and queues.
++- Level 2 Statistics (CPHAL Flags)
++ - RcbPool: Pointer to receive descriptor pool (per channel).
++ - RxActQueueCount: Number of buffers currently available for receive (per channel).
++ - RxActQueueHead: Pointer to first buffer in receive queue (per channel).
++ - RxActQueueTail: Pointer to last buffer in receive queue (per channel).
++ - RxActive: 0 if inactive (no buffers available), or 1 if active (buffers available).
++ - RcbStart: Pointer to block of receive descriptors.
++ - RxTeardownPending: 1 if Rx teardown is pending but incomplete, 0 otherwise.
++ - TcbPool: Pointer to transmit descriptor pool (per channel and queue).
++ - TxActQueueCount: Number of buffers currently queued to be transmitted (per channel and queue).
++ - TxActQueueHead: Pointer to first buffer in transmit queue (per channel and queue).
++ - TxActQueueTail: Pointer to last buffer in transmit queue (per channel and queue).
++ - TxActive: 0 if inactive (no buffers to send), or 1 if active (buffers queued to send).
++ - TcbStart: Pointer to block of transmit descriptors.
++ - TxTeardownPending: 1 if Tx teardown is pending but incomplete, 0 otherwise.
++- Level 3 Statistics (CPHAL Channel Configuration)
++ - RxBufSize: Rx buffer size.
++ - RxBufferOffset: Rx buffer offset.
++ - RxNumBuffers: Number of Rx buffers.
++ - RxServiceMax: Maximum number of receive packets to service at a time.
++ - TxNumBuffers: Number of Tx buffer descriptors.
++ - TxNumQueues: Number of Tx queues to use.
++ - TxServiceMax: Maximum number of transmit packets to service at a time.
++- Level 4 Statistics (CPHAL General Configuration)
++ - Base Address: Base address of the module.
++ - Offset (VLYNQ): VLYNQ relative module offset.
++ - Interrupt Line: Interrupt number.
++ - Debug: Debug flag, 1 to enable debug.
++ - Inst: Instance number.
++*/
++
++/*
++ Data Type 0 = int display
++ Data Type 1 = hex display
++ Data Type 2 = channel structure, int display
++ Data Type 3 = queue index and int display
++ Data Type 4 = queue index and hex display
++*/
++#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC)) /* +GSG 030307 */
++static STATS_TABLE StatsTable0[] =
++ {
++#ifdef _CPHAL_AAL5
++ /* Name , Data Ptr, Data Type */
++ {"Crc Errors", 0, 0},
++ {"Len Errors", 0, 0},
++ {"Abort Errors", 0, 0},
++ {"Starv Errors", 0, 0}
++#endif
++#ifdef _CPHAL_CPMAC
++ {"Rx Good Frames", 0, 0}
++#endif
++ };
++
++static STATS_TABLE StatsTable1[] =
++ {
++ /* Name , Data Ptr, Data Type */
++ {"DmaLenErrors", 0, 0},
++ {"TxMisQCnt", 0, 3},
++ {"RxMisQCnt", 0, 0},
++ {"TxEOQCnt", 0, 3},
++ {"RxEOQCnt", 0, 0},
++ {"RxPacketsServiced", 0, 0},
++ {"TxPacketsServiced", 0, 3},
++ {"RxMaxServiced", 0, 0},
++ {"TxMaxServiced", 0, 3},
++ {"RxTotal", 0, 0},
++ {"TxTotal", 0, 0},
++ };
++
++static STATS_TABLE StatsTable2[] =
++ {
++ /* Name , Data Ptr, Data Type */
++ {"RcbPool", 0, 1},
++ {"RxActQueueCount", 0, 0},
++ {"RxActQueueHead", 0, 1},
++ {"RxActQueueTail", 0, 1},
++ {"RxActive", 0, 0},
++ {"RcbStart", 0, 1},
++ {"RxTeardownPending", 0, 0},
++ {"TcbPool", 0, 4},
++ {"TxActQueueCount", 0, 3},
++ {"TxActQueueHead", 0, 4},
++ {"TxActQueueTail", 0, 4},
++ {"TxActive", 0, 3},
++ {"TcbStart", 0, 4},
++ {"TxTeardownPending", 0, 0}
++ };
++
++static STATS_TABLE StatsTable3[] =
++ {
++ /* Name , Data Ptr, Data Type */
++ {"RxBufSize", 0, 2},
++ {"RxBufferOffset", 0, 2},
++ {"RxNumBuffers", 0, 2},
++ {"RxServiceMax", 0, 2},
++ {"TxNumBuffers", 0, 2},
++ {"TxNumQueues", 0, 2},
++ {"TxServiceMax", 0, 2},
++#ifdef _CPHAL_AAL5
++ {"CpcsUU", 0, 2},
++ {"Gfc", 0, 2},
++ {"Clp", 0, 2},
++ {"Pti", 0, 2},
++ {"DaMask", 0, 2},
++ {"Priority", 0, 2},
++ {"PktType", 0, 2},
++ {"Vci", 0, 2},
++ {"Vpi", 0, 2},
++ {"CellRate", 0, 2},
++ {"QosType", 0, 2},
++ {"Mbs", 0, 2},
++ {"Pcr", 0, 2}
++#endif
++ };
++
++static STATS_TABLE StatsTable4[] =
++ {
++ {"Base Address", 0, 1},
++ {"Offset (VLYNQ)", 0, 0},
++ {"Interrupt Line", 0, 0},
++ {"Debug", 0, 0},
++ {"Instance", 0, 0},
++#ifdef _CPHAL_AAL5
++ {"UniNni", 0, 0}
++#endif
++ };
++
++static STATS_DB StatsDb[] =
++ {
++ {(sizeof(StatsTable0)/sizeof(STATS_TABLE)), StatsTable0},
++ {(sizeof(StatsTable1)/sizeof(STATS_TABLE)), StatsTable1},
++ {(sizeof(StatsTable2)/sizeof(STATS_TABLE)), StatsTable2},
++ {(sizeof(StatsTable3)/sizeof(STATS_TABLE)), StatsTable3},
++ {(sizeof(StatsTable4)/sizeof(STATS_TABLE)), StatsTable4}
++ };
++#endif /* +GSG 030307 */
++
++#ifdef _CPHAL_CPMAC /* +RC 3.02 */
++static void resetWait(HAL_DEVICE *HalDev)
++ { /*+RC3.02*/
++ const int TickReset=64;
++ osfuncSleep((int*)&TickReset);
++ } /*+RC3.02*/
++#endif /* +RC 3.02 */
++
++/* I only define the reset base function for the modules
++ that can perform a reset. The AAL5 and AAL2 modules
++ do not perform a reset, that is done by the shared module
++ CPSAR */
++#if defined(_CPHAL_CPSAR) || defined(_CPHAL_CPMAC) || defined(_CPHAL_VDMAVT)
++/*
++ * Determines the reset register address to be used for a particular device.
++ * It will search the current device entry for Locator information. If the
++ * device is a root device, there will be no Locator information, and the
++ * function will find and return the root reset register. If a Locator value
++ * is found, the function will search each VLYNQ device entry in the system
++ * looking for a matching Locator. Once it finds a VLYNQ device entry with
++ * a matching Locator, it will extract the "ResetBase" parameter from that
++ * VLYNQ device entry (thus every VLYNQ entry must have the ResetBase parameter).
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param ResetBase Pointer to integer address of reset register.
++ *
++ * @return 0 OK, Non-zero not OK
++ */
++static int ResetBaseGet(HAL_DEVICE *HalDev, bit32u *ResetBase)
++ {
++ char *DeviceInfo = HalDev->DeviceInfo;
++ char *MyLocator, *NextLocator;
++ int Inst=1;
++ bit32u error_code;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpcommon]ResetBaseGet(HalDev:%08x, ResetBase:%08x)\n", (bit32u)HalDev, ResetBase);
++ osfuncSioFlush();
++ }
++#endif
++
++ error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &MyLocator);
++ if (error_code)
++ {
++ /* if no Locator value, device is on the root, so get the "reset" device */
++ error_code = HalDev->OsFunc->DeviceFindInfo(0, "reset", &DeviceInfo);
++ if (error_code)
++ {
++ return(EC_VAL_DEVICE_NOT_FOUND);
++ }
++
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "base", ResetBase);
++ if (error_code)
++ {
++ return(EC_VAL_BASE_ADDR_NOT_FOUND);
++ }
++
++ *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
++
++ /* found base address for root device, so we're done */
++ return (EC_NO_ERRORS);
++ }
++ else
++ {
++ /* we have a Locator value, so the device is remote */
++
++ /* Find a vlynq device with a matching locator value */
++ while ((HalDev->OsFunc->DeviceFindInfo(Inst, "vlynq", &DeviceInfo)) == EC_NO_ERRORS)
++ {
++ error_code = HalDev->OsFunc->DeviceFindParmValue(DeviceInfo, "Locator", &NextLocator);
++ if (error_code)
++ {
++ /* no Locator value for this VLYNQ, so move on */
++ continue;
++ }
++ if (HalDev->OsFunc->Strcmpi(MyLocator, NextLocator)==0)
++ {
++ /* we have found a VLYNQ with a matching Locator, so extract the ResetBase */
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, "ResetBase", ResetBase);
++ if (error_code)
++ {
++ return(EC_VAL_BASE_ADDR_NOT_FOUND);
++ }
++ *ResetBase = ((bit32u)PhysToVirtNoCache(*ResetBase));
++
++ /* found base address for root device, so we're done */
++ return (EC_NO_ERRORS);
++ }
++ Inst++;
++ } /* while */
++ } /* else */
++
++ return (EC_NO_ERRORS);
++ }
++#endif
++
++#ifndef _CPHAL_AAL2 /* + RC 3.02 */
++static bit32u ConfigGetCommon(HAL_DEVICE *HalDev)
++ {
++ bit32u ParmValue;
++ bit32 error_code;
++ char *DeviceInfo = HalDev->DeviceInfo;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpcommon]ConfigGetCommon(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszBase, &ParmValue);
++ if (error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_BASE_ADDR_NOT_FOUND);
++ }
++ HalDev->dev_base = ((bit32u)PhysToVirtNoCache(ParmValue));
++
++#ifndef _CPHAL_AAL5
++#ifndef _CPHAL_AAL2
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszResetBit, &ParmValue);
++ if(error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BIT_NOT_FOUND);
++ }
++ HalDev->ResetBit = ParmValue;
++
++ /* Get reset base address */
++ error_code = ResetBaseGet(HalDev, &ParmValue);
++ if (error_code)
++ return(EC_FUNC_HAL_INIT|EC_VAL_RESET_BASE_NOT_FOUND);
++ HalDev->ResetBase = ParmValue;
++#endif
++#endif
++
++#ifndef _CPHAL_CPSAR
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszIntLine,&ParmValue);
++ if (error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_INTERRUPT_NOT_FOUND);
++ }
++ HalDev->interrupt = ParmValue;
++#endif
++
++ /* only look for the offset if there is a Locator field, which indicates that
++ the module is a VLYNQ module */
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszLocator,&ParmValue);
++ if (!error_code)
++ {
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszOffset,&ParmValue);
++ if (error_code)
++ {
++ return(EC_FUNC_HAL_INIT|EC_VAL_OFFSET_NOT_FOUND);
++ }
++ HalDev->offset = ParmValue;
++ }
++ else
++ HalDev->offset = 0;
++
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo, pszDebug, &ParmValue);
++ if (!error_code) HalDev->debug = ParmValue;
++
++ return (EC_NO_ERRORS);
++ }
++#endif /* +RC 3.02 */
++
++#ifdef _CPHAL_CPMAC /* +RC 3.02 */
++static void StatsInit(HAL_DEVICE *HalDev) /* +() RC3.02 */
++ {
++ /* even though these statistics may be for multiple channels and
++ queues, i need only configure the pointer to the beginning
++ of the array, and I can index from there if necessary */
++
++#ifdef _CPHAL_AAL5
++ StatsTable0[0].StatPtr = &HalDev->Stats.CrcErrors[0];
++ StatsTable0[1].StatPtr = &HalDev->Stats.LenErrors[0];
++ StatsTable0[2].StatPtr = &HalDev->Stats.AbortErrors[0];
++ StatsTable0[3].StatPtr = &HalDev->Stats.StarvErrors[0];
++
++ StatsTable1[0].StatPtr = &HalDev->Stats.DmaLenErrors[0];
++ StatsTable1[1].StatPtr = &HalDev->Stats.TxMisQCnt[0][0];
++ StatsTable1[2].StatPtr = &HalDev->Stats.RxMisQCnt[0];
++ StatsTable1[3].StatPtr = &HalDev->Stats.TxEOQCnt[0][0];
++ StatsTable1[4].StatPtr = &HalDev->Stats.RxEOQCnt[0];
++ StatsTable1[5].StatPtr = &HalDev->Stats.RxPacketsServiced[0];
++ StatsTable1[6].StatPtr = &HalDev->Stats.TxPacketsServiced[0][0];
++ StatsTable1[7].StatPtr = &HalDev->Stats.RxMaxServiced;
++ StatsTable1[8].StatPtr = &HalDev->Stats.TxMaxServiced[0][0];
++ StatsTable1[9].StatPtr = &HalDev->Stats.RxTotal;
++ StatsTable1[10].StatPtr = &HalDev->Stats.TxTotal;
++#endif
++
++#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC))
++ StatsTable2[0].StatPtr = (bit32u *)&HalDev->RcbPool[0];
++ StatsTable2[1].StatPtr = &HalDev->RxActQueueCount[0];
++ StatsTable2[2].StatPtr = (bit32u *)&HalDev->RxActQueueHead[0];
++ StatsTable2[3].StatPtr = (bit32u *)&HalDev->RxActQueueTail[0];
++ StatsTable2[4].StatPtr = &HalDev->RxActive[0];
++ StatsTable2[5].StatPtr = (bit32u *)&HalDev->RcbStart[0];
++ StatsTable2[6].StatPtr = &HalDev->RxTeardownPending[0];
++ StatsTable2[7].StatPtr = (bit32u *)&HalDev->TcbPool[0][0];
++ StatsTable2[8].StatPtr = &HalDev->TxActQueueCount[0][0];
++ StatsTable2[9].StatPtr = (bit32u *)&HalDev->TxActQueueHead[0][0];
++ StatsTable2[10].StatPtr = (bit32u *)&HalDev->TxActQueueTail[0][0];
++ StatsTable2[11].StatPtr = &HalDev->TxActive[0][0];
++ StatsTable2[12].StatPtr = (bit32u *)&HalDev->TcbStart[0][0];
++ StatsTable2[13].StatPtr = &HalDev->TxTeardownPending[0];
++
++ StatsTable3[0].StatPtr = &HalDev->ChData[0].RxBufSize;
++ StatsTable3[1].StatPtr = &HalDev->ChData[0].RxBufferOffset;
++ StatsTable3[2].StatPtr = &HalDev->ChData[0].RxNumBuffers;
++ StatsTable3[3].StatPtr = &HalDev->ChData[0].RxServiceMax;
++ StatsTable3[4].StatPtr = &HalDev->ChData[0].TxNumBuffers;
++ StatsTable3[5].StatPtr = &HalDev->ChData[0].TxNumQueues;
++ StatsTable3[6].StatPtr = &HalDev->ChData[0].TxServiceMax;
++#ifdef _CPHAL_AAL5
++ StatsTable3[7].StatPtr = &HalDev->ChData[0].CpcsUU;
++ StatsTable3[8].StatPtr = &HalDev->ChData[0].Gfc;
++ StatsTable3[9].StatPtr = &HalDev->ChData[0].Clp;
++ StatsTable3[10].StatPtr = &HalDev->ChData[0].Pti;
++ StatsTable3[11].StatPtr = &HalDev->ChData[0].DaMask;
++ StatsTable3[12].StatPtr = &HalDev->ChData[0].Priority;
++ StatsTable3[13].StatPtr = &HalDev->ChData[0].PktType;
++ StatsTable3[14].StatPtr = &HalDev->ChData[0].Vci;
++ StatsTable3[15].StatPtr = &HalDev->ChData[0].Vpi;
++ StatsTable3[16].StatPtr = &HalDev->ChData[0].TxVc_CellRate;
++ StatsTable3[17].StatPtr = &HalDev->ChData[0].TxVc_QosType;
++ StatsTable3[18].StatPtr = &HalDev->ChData[0].TxVc_Mbs;
++ StatsTable3[19].StatPtr = &HalDev->ChData[0].TxVc_Pcr;
++#endif
++#endif
++
++ StatsTable4[0].StatPtr = &HalDev->dev_base;
++ StatsTable4[1].StatPtr = &HalDev->offset;
++ StatsTable4[2].StatPtr = &HalDev->interrupt;
++ StatsTable4[3].StatPtr = &HalDev->debug;
++ StatsTable4[4].StatPtr = &HalDev->Inst;
++ }
++#endif /* +RC 3.02 */
++
++#ifndef _CPHAL_CPSAR /* +RC 3.02 */
++#ifndef _CPHAL_AAL2 /* +RC 3.02 */
++/*
++ * Returns statistics information.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return 0
++ */
++static int StatsGet(HAL_DEVICE *HalDev, void **StatPtr, int Index, int Ch, int Queue)
++ {
++ int Size;
++ bit32u *AddrPtr;
++ char *DataPtr;
++ STATS_TABLE *StatsTable;
++ int i, NumberOfStats;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpcommon]StatsGet(HalDev:%08x, StatPtr:%08x)\n",
++ (bit32u)HalDev, (bit32u)StatPtr);
++ osfuncSioFlush();
++ }
++#endif
++
++ StatsTable = StatsDb[Index].StatTable;
++ NumberOfStats = StatsDb[Index].NumberOfStats;
++
++ Size = sizeof(bit32u)*((NumberOfStats*2)+1);
++ Size += (NumberOfStats*11);
++ *StatPtr = (bit32u *)HalDev->OsFunc->Malloc(Size);
++
++ AddrPtr = (bit32u *) *StatPtr;
++ DataPtr = (char *)AddrPtr;
++ DataPtr += sizeof(bit32u)*((NumberOfStats*2)+1);
++
++ for (i=0; i<NumberOfStats; i++)
++ {
++ *AddrPtr++ = (bit32u)StatsTable[i].StatName;
++ *AddrPtr++ = (bit32u)DataPtr;
++ if (&StatsTable[i].StatPtr[Ch] != 0)
++ {
++ switch(StatsTable[i].DataType)
++ {
++ case 0:
++ HalDev->OsFunc->Sprintf(DataPtr, "%d", (bit32u *)StatsTable[i].StatPtr[Ch]);
++ break;
++ case 1:
++ HalDev->OsFunc->Sprintf(DataPtr, "0x%x", (bit32u *)StatsTable[i].StatPtr[Ch]);
++ break;
++ case 2:
++ HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch * (sizeof(CHANNEL_INFO)/4))));
++ break;
++ case 3:
++ HalDev->OsFunc->Sprintf(DataPtr, "%d", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
++ break;
++ case 4:
++ HalDev->OsFunc->Sprintf(DataPtr, "0x%x", *((bit32u *)StatsTable[i].StatPtr + (Ch*MAX_QUEUE)+Queue));
++ break;
++ default:
++ /* invalid data type, due to CPHAL programming error */
++ break;
++ }
++ }
++ else
++ {
++ /* invalid statistics pointer, probably was not initialized */
++ }
++ DataPtr += HalDev->OsFunc->Strlen(DataPtr) + 1;
++ }
++
++ *AddrPtr = (bit32u) 0;
++
++ return (EC_NO_ERRORS);
++ }
++#endif /* +RC 3.02 */
++#endif /* +RC 3.02 */
++
++#ifdef _CPHAL_CPMAC
++static void gpioFunctional(int base, int bit)
++ { /*+RC3.02*/
++ bit32u GpioEnr = base + 0xC;
++ /* To make functional, set to zero */
++ *(volatile bit32u *)(GpioEnr) &= ~(1 << bit); /*+RC3.02*/
++ } /*+RC3.02*/
++
++
++/*+RC3.02*/
++/* Common function, Checks to see if GPIO should be in functional mode */
++static void gpioCheck(HAL_DEVICE *HalDev, void *moduleDeviceInfo)
++ { /*+RC3.02*/
++ int rc;
++ void *DeviceInfo;
++ char *pszMuxBits;
++ char pszMuxBit[20];
++ char *pszTmp;
++ char szMuxBit[20];
++ char *ptr;
++ int base;
++ int reset_bit;
++ int bit;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++
++ rc = OsFunc->DeviceFindParmValue(moduleDeviceInfo, "gpio_mux",&pszTmp);
++ if(rc) return;
++ /* gpio entry found, get GPIO register info and make functional */
++
++ /* temp copy until FinParmValue fixed */
++ ptr = &szMuxBit[0];
++ while ((*ptr++ = *pszTmp++));
++
++ pszMuxBits = &szMuxBit[0];
++
++ rc = OsFunc->DeviceFindInfo(0,"gpio",&DeviceInfo);
++ if(rc) return;
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "base",&base);
++ if(rc) return;
++
++ rc = OsFunc->DeviceFindParmUint(DeviceInfo, "reset_bit",&reset_bit);
++ if(rc) return;
++
++ /* If GPIO still in reset, then exit */
++ if((VOLATILE32(HalDev->ResetBase) & (1 << reset_bit)) == 0)
++ return;
++ /* format for gpio_mux is gpio_mux = <int>;<int>;<int>...*/
++ while (*pszMuxBits)
++ {
++ pszTmp = &pszMuxBit[0];
++ if(*pszMuxBits == ';') pszMuxBits++;
++ while ((*pszMuxBits != ';') && (*pszMuxBits != '\0'))
++ {
++ osfuncSioFlush();
++ /*If value not a number, skip */
++ if((*pszMuxBits < '0') || (*pszMuxBits > '9'))
++ pszMuxBits++;
++ else
++ *pszTmp++ = *pszMuxBits++;
++ }
++ *pszTmp = '\0';
++ bit = OsFunc->Strtoul(pszMuxBit, &pszTmp, 10);
++ gpioFunctional(base, bit);
++ resetWait(HalDev); /* not sure if this is needed */
++ }
++ } /*+RC3.02*/
++#endif /* CPMAC */
++
++#ifdef _CPHAL_AAL5
++const char hcSarFrequency[] = "SarFreq";
++#endif
++
++#endif /* _INC */
+diff -urN linux.old/drivers/atm/sangam_atm/cpcommon_cpsar.h linux.dev/drivers/atm/sangam_atm/cpcommon_cpsar.h
+--- linux.old/drivers/atm/sangam_atm/cpcommon_cpsar.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpcommon_cpsar.h 2005-08-23 04:46:50.083845824 +0200
+@@ -0,0 +1,79 @@
++#ifndef _INC_CPCOMMON_H
++#define _INC_CPCOMMON_H
++
++#define VOLATILE32(addr) (*(volatile bit32u *)(addr))
++#ifndef dbgPrintf
++#define dbgPrintf HalDev->OsFunc->Printf
++#endif
++
++#define ChannelUpdate(Field) if(HalChn->Field != 0xFFFFFFFF) HalDev->ChData[Ch].Field = HalChn->Field
++
++#define DBG(level) (HalDev->debug & (1<<(level)))
++/*
++#define DBG0() DBG(0)
++#define DBG1() DBG(1)
++#define DBG2() DBG(2)
++#define DBG3() DBG(3)
++#define DBG4() DBG(4)
++#define DBG5() DBG(5)
++#define DBG6() DBG(6)
++#define DBG7() DBG(7)
++*/
++
++/*
++ * List of defined actions for use with Control().
++ */
++typedef enum
++ {
++ enGET=0, /**< Get the value associated with a key */
++ enSET, /**< Set the value associates with a key */
++ enCLEAR, /**<Clear the value */
++ enNULL /**< No data action, used to initiate a service or send a message */
++ }ACTION;
++
++/*
++ * Enumerated hardware states.
++ */
++typedef enum
++ {
++ enConnected=1, enDevFound, enInitialized, enOpened
++ }DEVICE_STATE;
++
++typedef enum
++ {
++ enCommonStart=0,
++ /* General */
++ enOff, enOn, enDebug,
++ /* Module General */
++ enCpuFreq,
++ enStatus,
++ enCommonEnd
++ }COMMON_KEY;
++
++typedef struct
++ {
++ const char *strKey;
++ int enKey;
++ }CONTROL_KEY;
++
++typedef struct
++ {
++ char *StatName;
++ unsigned int *StatPtr;
++ int DataType; /* 0: int, 1: hex int, 2:channel data */
++ }STATS_TABLE;
++
++typedef struct
++ {
++ int NumberOfStats;
++ STATS_TABLE *StatTable;
++ }STATS_DB;
++
++#define osfuncSioFlush() HalDev->OsFunc->Control(HalDev->OsDev,"SioFlush",pszNULL,0)
++#define osfuncSleep(Ticks) HalDev->OsFunc->Control(HalDev->OsDev,pszSleep,pszNULL,Ticks)
++#define osfuncStateChange() HalDev->OsFunc->Control(HalDev->OsDev,pszStateChange,pszNULL,0)
++
++#define CHANNEL_NAMES {"Ch0","Ch1","Ch2","Ch3","Ch4","Ch5","Ch6","Ch7","Ch8","Ch9","Ch10","Ch11","Ch12","Ch13","Ch14","Ch15"}
++
++#endif
++
+diff -urN linux.old/drivers/atm/sangam_atm/cppi_cpaal5.c linux.dev/drivers/atm/sangam_atm/cppi_cpaal5.c
+--- linux.old/drivers/atm/sangam_atm/cppi_cpaal5.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cppi_cpaal5.c 2005-08-23 04:46:50.084845672 +0200
+@@ -0,0 +1,1483 @@
++/*************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002,2003 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE: cppi.c
++ *
++ * DESCRIPTION:
++ * This file contains shared code for all CPPI modules.
++ *
++ * HISTORY:
++ * 7Aug02 Greg RC1.00 Original Version created.
++ * 27Sep02 Mick RC1.01 Merged for use by CPMAC/CPSAR
++ * 16Oct02 Mick RC1.02 Performance Tweaks (see cppihist.txt)
++ * 12Nov02 Mick RC1.02 Updated to use cpmac_reg.h
++ * 09Jan03 Mick RC3.01 Removed modification to RxBuffer ptr
++ * 28Mar03 Mick 1.03 RxReturn now returns error if Malloc Fails
++ * 10Apr03 Mick 1.03.02 Added Needs Buffer Support
++ * 11Jun03 Mick 1.06.02 halSend() errors corrected
++ *
++ * @author Greg Guyotte
++ * @version 1.00
++ * @date 7-Aug-2002
++ *****************************************************************************/
++/* each CPPI module must modify this file, the rest of the
++ code in cppi.c should be totally shared *//* Each CPPI module MUST properly define all constants shown below */
++
++/* CPPI registers */
++
++/* the following defines are not CPPI specific, but still used by cppi.c */
++
++static void FreeRx(HAL_DEVICE *HalDev, int Ch)
++ {
++ HAL_RCB *rcb_ptr; /*+GSG 030303*/
++ int rcbSize = (sizeof(HAL_RCB)+0xf)&~0xf; /*+GSG 030303*/
++ int Num = HalDev->ChData[Ch].RxNumBuffers, i; /*+GSG 030303*/
++
++ /* Free Rx data buffers attached to descriptors, if necessary */
++ if (HalDev->RcbStart[Ch] != 0) /*+GSG 030303*/
++ { /*+GSG 030303*/
++ for(i=0;i<Num;i++) /*+GSG 030303*/
++ { /*+GSG 030303*/
++ rcb_ptr = (HAL_RCB *)(HalDev->RcbStart[Ch] + (i*rcbSize)); /*+GSG 030303*/
++
++ /* free the data buffer */
++ if (rcb_ptr->DatPtr != 0)
++ {
++
++ HalDev->OsFunc->FreeRxBuffer((void *)rcb_ptr->OsInfo, (void *)rcb_ptr->DatPtr);
++ rcb_ptr->OsInfo=0; /*MJH+030522*/
++ rcb_ptr->DatPtr=0; /*MJH+030522*/
++ }
++ } /*+GSG 030303*/
++ } /*+GSG 030303*/
++
++ /* free up all desciptors at once */
++ HalDev->OsFunc->FreeDmaXfer(HalDev->RcbStart[Ch]);
++
++ /* mark buffers as freed */
++ HalDev->RcbStart[Ch] = 0;
++ }
++
++static void FreeTx(HAL_DEVICE *HalDev, int Ch, int Queue)
++ {
++
++/*+GSG 030303*/
++
++ /* free all descriptors at once */
++ HalDev->OsFunc->FreeDmaXfer(HalDev->TcbStart[Ch][Queue]);
++
++ HalDev->TcbStart[Ch][Queue] = 0;
++ }
++
++/* return of 0 means that this code executed, -1 means the interrupt was not
++ a teardown interrupt */
++static int RxTeardownInt(HAL_DEVICE *HalDev, int Ch)
++ {
++ bit32u base = HalDev->dev_base;
++
++ int i;
++ volatile bit32u *pTmp;
++
++ /* check to see if the interrupt is a teardown interrupt */
++ if (((*(pRX_CPPI_COMP_PTR( base )+( Ch *64))) & TEARDOWN_VAL) == TEARDOWN_VAL)
++ {
++ /* finish channel teardown */
++
++ /* Free channel resources on a FULL teardown */
++ if (HalDev->RxTeardownPending[Ch] & FULL_TEARDOWN)
++ {
++ FreeRx(HalDev, Ch);
++ }
++
++ /* bug fix - clear Rx channel pointers on teardown */
++ HalDev->RcbPool[Ch] = 0;
++ HalDev->RxActQueueHead[Ch] = 0;
++ HalDev->RxActQueueCount[Ch] = 0;
++ HalDev->RxActive[Ch] = FALSE;
++
++ /* write completion pointer */
++ (*(pRX_CPPI_COMP_PTR( base )+( Ch *64))) = TEARDOWN_VAL;
++
++ /* use direction bit as a teardown pending bit! May be able to
++ use only one teardown pending integer in HalDev */
++
++ HalDev->RxTeardownPending[Ch] &= ~RX_TEARDOWN;
++
++ HalDev->ChIsOpen[Ch][DIRECTION_RX] = 0;
++
++ /* call OS Teardown Complete (if TX is also done) */
++ if ((HalDev->TxTeardownPending[Ch] & TX_TEARDOWN) == 0)
++ {
++ /* mark channel as closed */
++ HalDev->ChIsOpen[Ch][DIRECTION_TX] = 0;
++
++ /* disable channel interrupt */
++ SAR_TX_MASK_CLR(HalDev->dev_base) = (1<<Ch);
++ SAR_TX_MASK_CLR(HalDev->dev_base) = (1<<(Ch+16)); /* +GSG 030307 */
++ SAR_RX_MASK_CLR(HalDev->dev_base) = (1<<Ch);
++
++ /* Clear PDSP Channel State RAM */
++ pTmp = (pPDSP_BLOCK_0(HalDev->dev_base)+(Ch*64));
++ for (i=0; i<NUM_PDSP_AAL5_STATE_WORDS; i++)
++ *pTmp++ = 0;
++
++ if ((HalDev->RxTeardownPending[Ch] & BLOCKING_TEARDOWN) == 0)
++ {
++
++ HalDev->OsFunc->TeardownComplete(HalDev->OsDev, Ch, DIRECTION_TX|DIRECTION_RX);
++ }
++ /* clear all teardown pending information for this channel */
++ HalDev->RxTeardownPending[Ch] = 0;
++ HalDev->TxTeardownPending[Ch] = 0;
++ }
++
++ return (EC_NO_ERRORS);
++ }
++ return (-1);
++ }
++
++/* return of 0 means that this code executed, -1 means the interrupt was not
++ a teardown interrupt */
++static int TxTeardownInt(HAL_DEVICE *HalDev, int Ch, int Queue)
++ {
++ bit32u base = HalDev->dev_base;
++ HAL_TCB *Last, *Curr, *First; /*+GSG 030303*/
++
++ int i;
++ volatile bit32u *pTmp;
++
++ if (((*(pTXH_CPPI_COMP_PTR( base )+( Ch *64)+( Queue ))) & TEARDOWN_VAL) == TEARDOWN_VAL)
++ {
++ /* return outstanding buffers to OS +RC3.02*/
++ Curr = HalDev->TxActQueueHead[Ch][Queue]; /*+GSG 030303*/
++ First = Curr; /*+GSG 030303*/
++ while (Curr) /*+GSG 030303*/
++ { /*+GSG 030303*/
++ /* Pop TCB(s) for packet from the stack */ /*+GSG 030303*/
++ Last = Curr->Eop; /*+GSG 030303*/
++ HalDev->TxActQueueHead[Ch][Queue] = Last->Next; /*+GSG 030303*/
++ /*+GSG 030303*/
++ /* return to OS */ /*+GSG 030303*/
++ HalDev->OsFunc->SendComplete(Curr->OsInfo); /*+GSG 030303*/
++ /*+GSG 030303*/
++ /* Push Tcb(s) back onto the stack */ /*+GSG 030303*/
++ Curr = Last->Next; /*+GSG 030303*/
++ Last->Next = HalDev->TcbPool[Ch][Queue]; /*+GSG 030303*/
++ HalDev->TcbPool[Ch][Queue] = First; /*+GSG 030303*/
++ /*+GSG 030303*/
++ /* set the first(SOP) pointer for the next packet */ /*+GSG 030303*/
++ First = Curr; /*+GSG 030303*/
++ } /*+GSG 030303*/
++
++ /* finish channel teardown */
++
++ /* save the OsInfo to pass to upper layer
++ THIS WAS CRASHING - because it's possible that I get the teardown
++ notification and the TcbHPool is null. In this case, the buffers
++ to free can be found in the TxHActiveQueue. If I need to get OsInfo
++ in the future, I can get it from one of those buffers.
++ OsInfo = HalDev->TcbHPool[Ch]->OsInfo; */
++
++ if (HalDev->TxTeardownPending[Ch] & FULL_TEARDOWN)
++ {
++ FreeTx(HalDev, Ch, Queue);
++ } /* if FULL teardown */
++
++ /* bug fix - clear Tx channel pointers on teardown */
++ HalDev->TcbPool[Ch][Queue] = 0;
++ HalDev->TxActQueueHead[Ch][Queue] = 0;
++ HalDev->TxActQueueCount[Ch][Queue] = 0;
++ HalDev->TxActive[Ch][Queue] = FALSE;
++
++ /* write completion pointer */
++ (*(pTXH_CPPI_COMP_PTR( base )+( Ch *64)+( Queue ))) = TEARDOWN_VAL;
++
++ /* no longer pending teardown */
++ HalDev->TxTeardownPending[Ch] &= ~TX_TEARDOWN;
++
++ HalDev->ChIsOpen[Ch][DIRECTION_TX] = 0;
++
++ /* call OS Teardown Complete (if Rx is also done) */
++ if ((HalDev->RxTeardownPending[Ch] & RX_TEARDOWN) == 0)
++ {
++ /* mark channel as closed */
++ HalDev->ChIsOpen[Ch][DIRECTION_RX] = 0;
++
++ /* disable channel interrupt */
++ SAR_TX_MASK_CLR(HalDev->dev_base) = (1<<Ch);
++ SAR_TX_MASK_CLR(HalDev->dev_base) = (1<<(Ch+16)); /* +GSG 030307 */
++ SAR_RX_MASK_CLR(HalDev->dev_base) = (1<<Ch);
++
++ /* Clear PDSP Channel State RAM */
++ pTmp = (pPDSP_BLOCK_0(HalDev->dev_base)+(Ch*64));
++ for (i=0; i<NUM_PDSP_AAL5_STATE_WORDS; i++)
++ *pTmp++ = 0;
++
++ if ((HalDev->TxTeardownPending[Ch] & BLOCKING_TEARDOWN) == 0)
++ {
++
++ HalDev->OsFunc->TeardownComplete(HalDev->OsDev, Ch, DIRECTION_TX|DIRECTION_RX);
++ }
++
++ /* clear all teardown pending information for this channel */
++ HalDev->RxTeardownPending[Ch] = 0;
++ HalDev->TxTeardownPending[Ch] = 0;
++ }
++
++ return (EC_NO_ERRORS);
++ }
++ return (-1);
++ }
++
++/* +GSG 030421 */
++static void AddToRxQueue(HAL_DEVICE *HalDev, HAL_RCB *FirstRcb, HAL_RCB *LastRcb, int FragCount, int Ch)
++ {
++ HAL_RCB *OldTailRcb;
++
++ if (HalDev->RxActQueueCount[Ch]==0)
++ {
++
++ HalDev->RxActQueueHead[Ch]=FirstRcb;
++ HalDev->RxActQueueTail[Ch]=LastRcb;
++ HalDev->RxActQueueCount[Ch]=FragCount;
++ if ((!HalDev->InRxInt[Ch])&&(!HalDev->RxActive[Ch]))
++ {
++ /* write Rx Queue Head Descriptor Pointer */
++ (*(pRX_DMA_STATE_WORD_1( HalDev->dev_base )+( Ch *64))) = VirtToPhys(FirstRcb) - HalDev->offset;
++ HalDev->RxActive[Ch]=TRUE;
++ }
++ }
++ else
++ {
++
++ OldTailRcb=HalDev->RxActQueueTail[Ch];
++ OldTailRcb->Next=(void *)FirstRcb;
++
++ /* Emerald fix 10/29 (Denis) */
++ *((bit32u *) VirtToVirtNoCache(&OldTailRcb->HNext))=VirtToPhys(FirstRcb) - HalDev->offset;
++
++ HalDev->RxActQueueTail[Ch]=LastRcb;
++ HalDev->RxActQueueCount[Ch]+=FragCount;
++ }
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function is called to indicate to the CPHAL that the upper layer
++ * software has finished processing the receive data (given to it by
++ * osReceive()). The CPHAL will then return the appropriate receive buffers
++ * and buffer descriptors to the available pool.
++ *
++ * @param HalReceiveInfo Start of receive buffer descriptor chain returned to
++ * CPHAL.
++ * @param StripFlag Flag indicating whether the upper layer software has
++ * retained ownership of the receive data buffers.
++ *<BR>
++ * 'FALSE' means that the CPHAL can reuse the receive data buffers.
++ *<BR>
++ * 'TRUE' : indicates the data buffers were retained by the OS
++ *<BR>
++ * NOTE: If StripFlag is TRUE, it is the responsibility of the upper layer software to free the buffers when they are no longer needed.
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_RCB_NEEDS_BUFFER "EC_VAL_RCB_NEEDS_BUFFER"<BR>
++ * @ref EC_VAL_RCB_DROPPED "EC_VAL_RCB_DROPPED"<BR>
++ */
++static int halRxReturn(HAL_RECEIVEINFO *HalReceiveInfo,
++ int StripFlag)
++ {
++ int Ch = HalReceiveInfo->Ch, i;
++ HAL_RCB *LastRcb, *TempRcb;
++ char *pBuf;
++ HAL_RCB *CurrHeadRcb = HalReceiveInfo, *LastGoodRcb=0; /* +GSG 030421 */
++ HAL_DEVICE *HalDev = HalReceiveInfo->HalDev;
++ int RcbSize = HalDev->ChData[Ch].RxBufSize;
++ int FragCount = HalReceiveInfo->FragCount;
++ int rc=0; /*MJH+030417*/
++ int GoodCount=0; /*GSG+030421*/
++
++ if (HalDev->State != enOpened)
++ return(EC_AAL5 |EC_FUNC_RXRETURN|EC_VAL_INVALID_STATE);
++
++ LastRcb=(HAL_RCB *)HalReceiveInfo->Eop;
++ LastRcb->HNext=0;
++ LastRcb->Next=0;
++
++ if (FragCount>1)
++ {
++ LastRcb->Off_BLen=RcbSize;
++ LastRcb->mode=CB_OWNERSHIP_BIT;
++ }
++
++ HalReceiveInfo->Off_BLen=RcbSize;
++ HalReceiveInfo->mode=CB_OWNERSHIP_BIT;
++
++ /* If OS has kept the buffers for this packet, attempt to alloc new buffers */
++ if (StripFlag)
++ {
++ TempRcb = HalReceiveInfo;
++ for (i=0; i<FragCount; i++)
++ {
++ if (TempRcb == 0)
++ {
++ dbgPrintf("Rx Return error while allocating new buffers\n");
++ dbgPrintf("Rcb = %08x, Rcb->Eop = %08x, FragCount = %d:%d\n",
++ (bit32u)HalReceiveInfo, (bit32u)HalReceiveInfo->Eop, FragCount,i);
++ osfuncSioFlush();
++
++ return(EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_CORRUPT_RCB_CHAIN);
++ }
++
++ /* size = ((RcbSize+15) & ~15) + 15;*/ /*-3.01b*/
++ /*size = RcbSize + 15;*/ /* -GSG 030421 */
++ pBuf= (char *) HalDev->OsFunc->MallocRxBuffer(RcbSize,0,
++ 0xF,HalDev->ChData[Ch].OsSetup,
++ (void *)TempRcb,
++ (void *)&TempRcb->OsInfo,
++ (void *) HalDev->OsDev);
++ if (!pBuf)
++ {
++ /* malloc failed, add this RCB to Needs Buffer List */
++ TempRcb->FragCount = 1; /*MJH+030417*/
++ (HAL_RCB *)TempRcb->Eop = TempRcb; /* GSG +030430 */
++
++ if(HalDev->NeedsCount < MAX_NEEDS) /* +MJH 030410 */
++ { /* +MJH 030410 */
++ HalDev->Needs[HalDev->NeedsCount] = (HAL_RECEIVEINFO *) TempRcb; /* +MJH 030410 */
++ HalDev->NeedsCount++; /* +MJH 030410 */
++ rc = (EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_RCB_NEEDS_BUFFER); /* ~MJH 030417 */
++ } /* +MJH 030410 */
++ else /* +MJH 030410 */
++ rc = (EC_CPPI|EC_FUNC_RXRETURN|EC_VAL_RCB_DROPPED); /* ~MJH 030417 */
++
++ /* requeue any previous RCB's that were ready to go before this one */
++ if (GoodCount > 0) /* +GSG 030421 */
++ { /* +GSG 030421 */
++ LastGoodRcb->HNext=0; /* +GSG 030430 */
++ LastGoodRcb->Next=0; /* +GSG 030430 */
++ osfuncDataCacheHitWriteback((void *)LastGoodRcb, 16); /* +GSG 030430 */
++
++ AddToRxQueue(HalDev, CurrHeadRcb, LastGoodRcb, GoodCount, Ch); /* +GSG 030421 */
++ GoodCount = 0; /* +GSG 030421 */
++ } /* +GSG 030421 */
++
++ CurrHeadRcb = TempRcb->Next; /* +GSG 030421 */
++ }
++ else /* +GSG 030421 */
++ { /* +GSG 030421 */
++ /* malloc succeeded, requeue the RCB to the hardware */
++ TempRcb->BufPtr=VirtToPhys(pBuf) - HalDev->offset;
++ TempRcb->DatPtr=pBuf;
++ /* Emerald fix 10/29 */
++ osfuncDataCacheHitWriteback((void *)TempRcb, 16);
++
++ /* i store the last good RCB in case the malloc fails for the
++ next fragment. This ensures that I can go ahead and return
++ a partial chain of RCB's to the hardware */
++ LastGoodRcb = TempRcb; /* +GSG 030421 */
++ GoodCount++; /* +GSG 030421 */
++ } /* +GSG 030421 */
++ TempRcb = TempRcb->Next;
++ } /* end of Frag loop */
++ /* if there any good RCB's to requeue, do so here */
++ if (GoodCount > 0) /* +GSG 030421 */
++ {
++ AddToRxQueue(HalDev, CurrHeadRcb, LastGoodRcb, GoodCount, Ch); /* +GSG 030421 */
++ }
++ return(rc); /* ~GSG 030421 */
++ }
++ else
++ {
++ /* Not Stripping */
++ /* Emerald */
++ /* Write Back SOP and last RCB */
++ osfuncDataCacheHitWriteback((void *)HalReceiveInfo, 16);
++
++ if (FragCount > 1)
++ {
++ osfuncDataCacheHitWriteback((void *)LastRcb, 16);
++ }
++ /* if not stripping buffers, always add to queue */
++ AddToRxQueue(HalDev, HalReceiveInfo, LastRcb, FragCount, Ch); /*MJH~030520*/
++ }
++
++ return(EC_NO_ERRORS);
++ }
++
++/* +MJH 030410
++ Trys to liberate an RCB until liberation fails.
++ Note: If liberation fails then RxReturn will re-add the RCB to the
++ Needs list.
++*/
++static void NeedsCheck(HAL_DEVICE *HalDev)
++{
++ HAL_RECEIVEINFO* HalRcb;
++ int rc;
++ HalDev->OsFunc->CriticalOn();
++ while(HalDev->NeedsCount)
++ {
++ HalDev->NeedsCount--;
++ HalRcb = HalDev->Needs[HalDev->NeedsCount];
++ rc = halRxReturn(HalRcb, 1);
++ /* short circuit if RxReturn starts to fail */
++ if (rc != 0)
++ break;
++ }
++ HalDev->OsFunc->CriticalOff();
++}
++
++/*
++ * This function allocates transmit buffer descriptors (internal CPHAL function).
++ * It creates a high priority transmit queue by default for a single Tx
++ * channel. If QoS is enabled for the given CPHAL device, this function
++ * will also allocate a low priority transmit queue.
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param Ch Channel number.
++ *
++ * @return 0 OK, Non-Zero Not OK
++ */
++static int InitTcb(HAL_DEVICE *HalDev, int Ch)
++ {
++ int i, Num = HalDev->ChData[Ch].TxNumBuffers;
++ HAL_TCB *pTcb=0;
++ char *AllTcb;
++ int tcbSize, Queue;
++ int SizeMalloc;
++
++ tcbSize = (sizeof(HAL_TCB)+0xf)&~0xf;
++ SizeMalloc = (tcbSize*Num)+0xf;
++
++ for (Queue=0; Queue < HalDev->ChData[Ch].TxNumQueues; Queue++)
++ {
++ if (HalDev->TcbStart[Ch][Queue] == 0)
++ {
++
++ /* malloc all TCBs at once */
++ AllTcb = (char *)HalDev->OsFunc->MallocDmaXfer(SizeMalloc,0,0xffffffff);
++ if (!AllTcb)
++ {
++ return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_TCB_MALLOC_FAILED);
++ }
++
++ HalDev->OsFunc->Memset(AllTcb, 0, SizeMalloc);
++
++ /* keep this address for freeing later */
++ HalDev->TcbStart[Ch][Queue] = AllTcb;
++ }
++ else
++ {
++ /* if the memory has already been allocated, simply reuse it! */
++ AllTcb = HalDev->TcbStart[Ch][Queue];
++ }
++
++ /* align to cache line */
++ AllTcb = (char *)(((bit32u)AllTcb + 0xf) &~ 0xf); /*PITS #143 MJH~030522*/
++
++ /* default High priority transmit queue */
++ HalDev->TcbPool[Ch][Queue]=0;
++ for(i=0;i<Num;i++)
++ {
++ /*pTcb=(HAL_TCB *) OsFunc->MallocDmaXfer(sizeof(HAL_TCB),0,0xffffffff); */
++ pTcb= (HAL_TCB *)(AllTcb + (i*tcbSize));
++ pTcb->mode=0;
++ pTcb->BufPtr=0;
++ pTcb->Next=HalDev->TcbPool[Ch][Queue];
++ pTcb->Off_BLen=0;
++ HalDev->TcbPool[Ch][Queue]=pTcb;
++ }
++ /*HalDev->TcbEnd = pTcb;*/
++ }
++
++ return(EC_NO_ERRORS);
++ }
++
++/*
++ * This function allocates receive buffer descriptors (internal CPHAL function).
++ * After allocation, the function 'queues' (gives to the hardware) the newly
++ * created receive buffers to enable packet reception.
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param Ch Channel number.
++ *
++ * @return 0 OK, Non-Zero Not OK
++ */
++static int InitRcb(HAL_DEVICE *HalDev, int Ch)
++ {
++ int i, Num = HalDev->ChData[Ch].RxNumBuffers;
++ int Size = HalDev->ChData[Ch].RxBufSize;
++ HAL_RCB *pRcb;
++ char *pBuf;
++ char *AllRcb;
++ int rcbSize;
++ int DoMalloc = 0;
++ int SizeMalloc;
++ int MallocSize;
++
++ rcbSize = (sizeof(HAL_RCB)+0xf)&~0xf;
++ SizeMalloc = (rcbSize*Num)+0xf;
++
++ if (HalDev->RcbStart[Ch] == 0)
++ {
++ DoMalloc = 1;
++
++ /* malloc all RCBs at once */
++ AllRcb= (char *)HalDev->OsFunc->MallocDmaXfer(SizeMalloc,0,0xffffffff);
++ if (!AllRcb)
++ {
++ return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_RCB_MALLOC_FAILED);
++ }
++
++ HalDev->OsFunc->Memset(AllRcb, 0, SizeMalloc);
++
++ /* keep this address for freeing later */
++ HalDev->RcbStart[Ch] = AllRcb;
++ }
++ else
++ {
++ /* if the memory has already been allocated, simply reuse it! */
++ AllRcb = HalDev->RcbStart[Ch];
++ }
++
++ /* align to cache line */
++ AllRcb = (char *)(((bit32u)AllRcb + 0xf)&~0xf); /*PITS #143 MJH~030522*/
++
++ HalDev->RcbPool[Ch]=0;
++ for(i=0;i<Num;i++)
++ {
++ pRcb = (HAL_RCB *)(AllRcb + (i*rcbSize));
++
++ if (DoMalloc == 1)
++ {
++
++ MallocSize = Size; /*~3.01 */
++ pBuf= (char *) HalDev->OsFunc->MallocRxBuffer(MallocSize,0,0xF,HalDev->ChData[Ch].OsSetup, (void *)pRcb, (void *)&pRcb->OsInfo, (void *) HalDev->OsDev);
++ if(!pBuf)
++ {
++ return(EC_CPPI|EC_FUNC_HAL_INIT|EC_VAL_RX_BUFFER_MALLOC_FAILED);
++ }
++ /* -RC3.01 pBuf = (char *)(((bit32u)pBuf+0xF) & ~0xF); */
++ pRcb->BufPtr=VirtToPhys(pBuf) - HalDev->offset;
++ pRcb->DatPtr=pBuf;
++ /*pRcb->BufSize=Size;*/
++ }
++ pRcb->mode=0;
++ pRcb->Ch=Ch;
++ pRcb->Next=(void *)HalDev->RcbPool[Ch];
++ pRcb->Off_BLen=0;
++ pRcb->HalDev = HalDev;
++ HalDev->RcbPool[Ch]=pRcb;
++ }
++
++ /* Give all of the Rx buffers to hardware */
++
++ while(HalDev->RcbPool[Ch])
++ {
++ pRcb=HalDev->RcbPool[Ch];
++ HalDev->RcbPool[Ch]=pRcb->Next;
++ pRcb->Eop=(void*)pRcb;
++ pRcb->FragCount=1;
++ halRxReturn((HAL_RECEIVEINFO *)pRcb, 0);
++ }
++
++ return(EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function transmits the data in FragList using available transmit
++ * buffer descriptors. More information on the use of the Mode parameter
++ * is available in the module-specific appendices. Note: The OS should
++ * not call Send() for a channel that has been requested to be torndown.
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param FragList Fragment List structure.
++ * @param FragCount Number of fragments in FragList.
++ * @param PacketSize Number of bytes to transmit.
++ * @param OsSendInfo OS Send Information structure. <BR>
++ * @param Mode 32-bit value with the following bit fields: <BR>
++ * 31-16: Mode (used for module specific data). <BR>
++ * 15-08: Queue (transmit queue to send on). <BR>
++ * 07-00: Channel (channel number to send on).
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_NOT_LINKED "EC_VAL_NOT_LINKED"<BR>
++ * @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
++ * @ref EC_VAL_OUT_OF_TCBS "EC_VAL_OUT_OF_TCBS"<BR>
++ * @ref EC_VAL_NO_TCBS "EC_VAL_NO_TCBS"<BR>
++ */
++static int halSend(HAL_DEVICE *HalDev,FRAGLIST *FragList,
++ int FragCount,int PacketSize, OS_SENDINFO *OsSendInfo,
++ bit32u Mode)
++ {
++ HAL_TCB *tcb_ptr, *head;
++ int i;
++ bit32u base = HalDev->dev_base;
++ int rc = EC_NO_ERRORS;
++ int Ch = Mode & 0xFF;
++ int Queue = (Mode>>8)&0xFF;
++
++ int WaitFlag = (Mode>>30)&1; /* This is for AAL5 testing only */ /* ~GSG 030508 */
++ int Offset = (FragList[0].len >> 16);
++ int PktType = (Mode>>16)&3; /* 0=AAL5, 1=Null AAL, 2=OAM, 3=Transparent */ /* +GSG 030508 */
++ int AtmHeaderInData = (Mode>>31)&1; /* +GSG 030508 */
++ int FragIndex = 0;
++
++ if (HalDev->State != enOpened)
++ return(EC_CPPI|EC_FUNC_SEND|EC_VAL_INVALID_STATE);
++
++ if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == 0) /*MJH~030611*/ /*PITS 148*/
++ return(EC_AAL5 |EC_FUNC_SEND|EC_VAL_INVALID_CH); /*+GSG 030303*/
++
++ HalDev->OsFunc->CriticalOn();
++
++ tcb_ptr = head = HalDev->TcbPool[Ch][Queue];
++
++ if (tcb_ptr)
++ {
++
++ /* these two TCB words are only valid on SOP */
++ if (AtmHeaderInData == 1)
++ {
++ tcb_ptr->AtmHeader = 0; /* bug fix for transparent mode PTI problem */
++ /* Expect AtmHeader in the data */
++ tcb_ptr->AtmHeader |= *((bit8u *)FragList[FragIndex].data++) << 24;
++ tcb_ptr->AtmHeader |= *((bit8u *)FragList[FragIndex].data++) << 16;
++ tcb_ptr->AtmHeader |= *((bit8u *)FragList[FragIndex].data++) << 8;
++ tcb_ptr->AtmHeader |= *((bit8u *)FragList[FragIndex].data++);
++
++ /* decrement data buffer length accordingly */
++ FragList[FragIndex].len -= ATM_HEADER_SIZE;
++
++ /* if the first fragment was ATM Header only, go to next fragment for loop */
++ if (FragList[FragIndex].len == 0)
++ FragIndex++;
++
++ /* No CPCS_UU/CPI if not AAL5 */
++ tcb_ptr->Word5 = ((PktType & 0x3)<<16);
++ }
++ else
++ {
++ /* calculate AtmHeader from fields */
++ tcb_ptr->AtmHeader = atmheader(HalDev->ChData[Ch].Gfc, /* ~GSG 030306 */
++ HalDev->ChData[Ch].Vpi, HalDev->ChData[Ch].Vci,
++ HalDev->ChData[Ch].Pti, HalDev->ChData[Ch].Clp);
++
++ tcb_ptr->Word5 = HalDev->ChData[Ch].CpcsUU | ((HalDev->ChData[Ch].PktType &0x3)<<16);
++ }
++
++ for (i=FragIndex; i<FragCount; i++)
++
++ {
++ /* Setup Tx mode and size */
++ tcb_ptr->HNext = VirtToPhys((bit32 *)tcb_ptr->Next) - HalDev->offset;
++ tcb_ptr->Off_BLen = FragList[i].len;
++
++ if (i==0)
++ tcb_ptr->Off_BLen |= (Offset << 16);
++
++ tcb_ptr->mode = 0; /* MUST clear this for each frag !!! */
++ tcb_ptr->BufPtr = VirtToPhys((bit32 *)FragList[i].data) -
++ HalDev->offset;
++
++ /* first fragment */
++ if (i == 0)
++ {
++ tcb_ptr->mode |= CB_SOF_BIT;
++
++ }
++
++ tcb_ptr->mode |= (PacketSize | CB_OWNERSHIP_BIT);
++ tcb_ptr->OsInfo = OsSendInfo;
++
++ if (i == (FragCount - 1))
++ {
++ /* last fragment */
++ tcb_ptr->mode |= CB_EOF_BIT;
++
++ /* since this is the last fragment, set the TcbPool pointer before
++ nulling out the Next pointers */
++
++ HalDev->TcbPool[Ch][Queue] = tcb_ptr->Next;
++
++ tcb_ptr->Next = 0;
++ tcb_ptr->HNext = 0;
++
++ /* In the Tx Interrupt handler, we will need to know which TCB is EOP,
++ so we can save that information in the SOP */
++ head->Eop = tcb_ptr;
++
++ /* Emerald fix 10/29 */
++ osfuncDataCacheHitWriteback((void *)tcb_ptr, 16);
++
++ osfuncDataCacheHitWriteback((void *)((bit32u)tcb_ptr + 16), 16);
++
++ }
++ else
++ {
++ /* Emerald fix 10/29 */
++ osfuncDataCacheHitWriteback((void *)tcb_ptr, 16);
++
++ osfuncDataCacheHitWriteback((void *)((bit32u)tcb_ptr + 16), 16);
++
++ tcb_ptr = tcb_ptr->Next; /* what about the end of TCB list?? */
++
++ if (tcb_ptr == 0)
++ {
++ rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_OUT_OF_TCBS;
++ goto ExitSend;
++ }
++ }
++ } /* for */
++
++ /* put it on the high priority queue */
++ if (HalDev->TxActQueueHead[Ch][Queue] == 0)
++ {
++ HalDev->TxActQueueHead[Ch][Queue]=head;
++ HalDev->TxActQueueTail[Ch][Queue]=tcb_ptr;
++/*+GSG 030303*//*+GSG 030303*/
++ if (!HalDev->TxActive[Ch][Queue])
++ {
++
++ if (!WaitFlag)
++ {
++
++ /* write CPPI TX HDP */
++ (*(pTX_DMA_STATE_WORD_0( base )+( Ch *64)+( Queue ))) = VirtToPhys(head) - HalDev->offset;
++ HalDev->TxActive[Ch][Queue]=TRUE;
++
++ }
++
++ }
++ }
++ else
++ {
++ HalDev->TxActQueueTail[Ch][Queue]->Next=head;
++ /* Emerald fix 10/29 */
++ *((bit32u *) VirtToVirtNoCache(&HalDev->TxActQueueTail[Ch][Queue]->HNext))=VirtToPhys(head) - HalDev->offset;
++ HalDev->TxActQueueTail[Ch][Queue]=tcb_ptr;
++/*+GSG 030303*//*+GSG 030303*/
++ }
++ rc = EC_NO_ERRORS;
++ goto ExitSend;
++ } /* if (tcb_ptr) */
++ else
++ {
++ rc = EC_CPPI|EC_FUNC_SEND|EC_VAL_NO_TCBS;
++ goto ExitSend;
++ }
++ExitSend:
++
++ HalDev->OsFunc->CriticalOff();
++ return(rc);
++ }
++
++/*
++ * This function processes receive interrupts. It traverses the receive
++ * buffer queue, extracting the data and passing it to the upper layer software via
++ * osReceive(). It handles all error conditions and fragments without valid data by
++ * immediately returning the RCB's to the RCB pool.
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param Ch Channel Number.
++ * @param MoreWork Flag that indicates that there is more work to do when set to 1.
++ *
++ * @return 0 if OK, non-zero otherwise.
++ */
++static int RxInt(HAL_DEVICE *HalDev, int Ch, int *MoreWork)
++ {
++ HAL_RCB *CurrentRcb, *LastRcb=0, *SopRcb, *EofRcb, *EopRcb;
++ bit32u RxBufStatus,PacketsServiced, RxPktLen = 0, RxSopStatus,
++ FrmFrags, TotalFrags, CurrDmaLen, DmaLen, FrmLen;
++ int base = HalDev->dev_base, Ret;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++ int RxServiceMax = HalDev->ChData[Ch].RxServiceMax;
++ int FragIndex; /* +GSG 030508 */
++ int EarlyReturn = 0; /* +GSG 030521 */
++
++ bit32u PktType, ExpDmaSize, Cells;
++ int PassHeader=0;
++
++ int mode;
++
++ bit32u SopOffset;
++
++ if(HalDev->NeedsCount) /* +MJH 030410 */
++ NeedsCheck(HalDev); /* +MJH 030410 */
++
++ /* Handle case of teardown interrupt */
++ if (HalDev->RxTeardownPending[Ch] != 0)
++ {
++ Ret = RxTeardownInt(HalDev, Ch);
++ if (Ret == 0)
++ { /*+GSG 030303*/
++ *MoreWork = 0; /* bug fix 1/6 */ /*+GSG 030303*/
++ return (EC_NO_ERRORS);
++ } /*+GSG 030303*/
++ }
++
++ CurrentRcb=HalDev->RxActQueueHead[Ch];
++
++ osfuncDataCacheHitInvalidate((void*)CurrentRcb, 16);
++
++ RxBufStatus=CurrentRcb->mode;
++
++ /* I think I need to do this to ensure that i read UuCpi properly,
++ which is on the second cache line of the Rcb */
++ osfuncDataCacheHitInvalidate((void*)((bit32u)CurrentRcb+16), 16);
++
++ PacketsServiced=0;
++ HalDev->InRxInt[Ch]=TRUE;
++
++ while((CurrentRcb)&&((RxBufStatus&CB_OWNERSHIP_BIT)==0)&&
++ (PacketsServiced<RxServiceMax)) /* ~GSG 030307 */
++ {
++
++ PacketsServiced++; /* ~GSG 030307 */
++ SopRcb=CurrentRcb;
++ RxSopStatus=RxBufStatus;
++
++ RxPktLen = RxSopStatus&CB_SIZE_MASK;
++ /* Not sure what MAC needs to do for next block */
++
++ PktType=((SopRcb->UuCpi & 0x00030000) >> 16); /* GSG ~030508 */
++ /* Calculate the expected DMA length */
++ if (RxPktLen != 0)
++ {
++ Cells=RxPktLen/48;
++ if ((RxPktLen%48) > 40)
++ Cells++;
++ if (PktType == PKT_TYPE_AAL5) /* ~GSG 030508 */
++ Cells++;
++ ExpDmaSize=Cells*48;
++ }
++ else
++ {
++ ExpDmaSize=0;
++ }
++
++ SopOffset=(SopRcb->Off_BLen&CB_OFFSET_MASK)>>16;
++
++ CurrDmaLen=0;
++ FrmFrags=0;
++ TotalFrags=0;
++ FragIndex=0;
++ FrmLen=0;
++ EofRcb=0;
++
++/* +GSG 030508 */
++ if ((PktType == PKT_TYPE_OAM) || (PktType == PKT_TYPE_TRANS)) /* +GSG 030508 */
++ { /* +GSG 030508 */
++ /* first frag is ATM Header */ /* +GSG 030508 */
++ PassHeader = 1; /* +GSG 030508 */
++ HalDev->fraglist[FragIndex].data = (void *)&SopRcb->AtmHeader; /* +GSG 030508 */
++ HalDev->fraglist[FragIndex].len = 4; /* +GSG 030508 */
++ HalDev->fraglist[FragIndex].OsInfo = SopRcb->OsInfo; /* +GSG 030701 */
++ FragIndex++; /* +GSG 030508 */
++ } /* +GSG 030508 */
++/* +GSG 030508 */
++
++ do
++ {
++
++ DmaLen=CurrentRcb->Off_BLen&CB_SIZE_MASK;
++
++ CurrDmaLen+=DmaLen;
++ FrmLen+=DmaLen;
++ TotalFrags++;
++ if (!EofRcb)
++ {
++ HalDev->fraglist[FragIndex].data=((char *)CurrentRcb->DatPtr); /* ~GSG 030508 */
++
++ HalDev->fraglist[FragIndex].data+=((FrmFrags==0)?SopOffset:0); /* ~GSG 030508 */
++
++ HalDev->fraglist[FragIndex].len=DmaLen; /* ~GSG 030508 */
++
++ /* GSG 12/9 */
++ HalDev->fraglist[FragIndex].OsInfo = CurrentRcb->OsInfo; /* ~GSG 030508 */
++
++ /* Upper layer must do the data invalidate */
++
++ FrmFrags++;
++ FragIndex++; /* ~GSG 030508 */
++ if (FrmLen>=RxPktLen)
++ EofRcb=CurrentRcb;
++ }
++ LastRcb=CurrentRcb;
++ CurrentRcb=LastRcb->Next;
++ if (CurrentRcb)
++ {
++ osfuncDataCacheHitInvalidate((void*)CurrentRcb,16);
++ /* RxBufStatus=CurrentRcb->mode; */ /*DRB~030522*/
++ }
++ }while(((LastRcb->mode&CB_EOF_BIT)==0)&&(CurrentRcb));
++
++ /* New location for interrupt acknowledge */
++ /* Write the completion pointer */
++ (*(pRX_CPPI_COMP_PTR( base )+( Ch *64))) = VirtToPhys(LastRcb) - HalDev->offset;
++
++ EopRcb=LastRcb;
++ HalDev->RxActQueueHead[Ch]=CurrentRcb;
++ HalDev->RxActQueueCount[Ch]-=TotalFrags;
++
++ if (LastRcb->mode&CB_EOQ_BIT)
++ {
++ if (CurrentRcb)
++ {
++
++ HalDev->Stats.RxMisQCnt[Ch]++;
++
++ (*(pRX_DMA_STATE_WORD_1( base )+( Ch *64))) = LastRcb->HNext;
++ }
++ else
++ {
++
++ /* Rx EOQ */
++ HalDev->Stats.RxMisQCnt[Ch]++;
++
++ HalDev->RxActive[Ch]=FALSE;
++ }
++ }
++
++ EopRcb->Next=0;
++
++ /* setup SopRcb for the packet */
++ SopRcb->Eop=(void*)EopRcb;
++ SopRcb->FragCount=TotalFrags;
++
++ if ((ExpDmaSize!=CurrDmaLen)||(RxSopStatus&RX_ERROR_MASK))
++ {
++ /* check for Rx errors (only valid on SOP) */
++ if (RxSopStatus & RX_ERROR_MASK)
++ {
++ if (RxSopStatus & CRC_ERROR_MASK)
++ HalDev->Stats.CrcErrors[Ch]++;
++
++ if (RxSopStatus & LENGTH_ERROR_MASK)
++ HalDev->Stats.LenErrors[Ch]++;
++
++ if (RxSopStatus & ABORT_ERROR_MASK)
++ HalDev->Stats.AbortErrors[Ch]++;
++
++ if (RxSopStatus & STARV_ERROR_MASK)
++ HalDev->Stats.StarvErrors[Ch]++;
++ }
++ else
++ {
++ HalDev->Stats.DmaLenErrors[Ch]++; /* different type of length error */
++ }
++
++ EarlyReturn = 1;
++ }
++
++ /* do not pass up the packet if we're out of RCB's (or have an errored packet)*/
++ if ((CurrentRcb == 0) || (EarlyReturn == 1))
++ {
++ halRxReturn((HAL_RECEIVEINFO *)SopRcb,0);
++ }
++ else
++ {
++
++ if (EopRcb!=EofRcb)
++ {
++ HAL_RCB *FirstEmptyRcb;
++
++ FirstEmptyRcb = EofRcb->Next;
++ FirstEmptyRcb->Eop = (void*)EopRcb;
++ FirstEmptyRcb->FragCount = TotalFrags-FrmFrags;
++
++ halRxReturn((HAL_RECEIVEINFO *)FirstEmptyRcb,0);
++ SopRcb->Eop=(void*)EofRcb;
++ SopRcb->FragCount=FrmFrags;
++ EofRcb->Next=0; /* Optional */
++ }
++
++ mode = Ch | (PktType << 16) | (PassHeader << 31); /* ~GSG 030508 */
++
++ OsFunc->Receive(HalDev->OsDev,HalDev->fraglist,FragIndex,RxPktLen, /* ~GSG 030508 */
++ (HAL_RECEIVEINFO *)SopRcb,mode);
++ } /* else */
++
++ if (CurrentRcb) /*MJH+030522*/
++ {
++ RxBufStatus=CurrentRcb->mode;
++ }
++ } /* while */
++
++ if ((CurrentRcb)&&((RxBufStatus&CB_OWNERSHIP_BIT)==0)) /*~GSG 030307*/
++ {
++ *MoreWork = 1;
++ }
++ else
++ {
++ *MoreWork = 0;
++ }
++
++ if (PacketsServiced != 0)
++ {
++ /* REMOVED when removing InRxInt */
++ if ((!HalDev->RxActive[Ch]) && (HalDev->RxActQueueCount[Ch]))
++ {
++ (*(pRX_DMA_STATE_WORD_1( base )+( Ch *64))) = VirtToPhys(HalDev->RxActQueueHead[Ch]);
++ HalDev->RxActive[Ch]=TRUE;
++ }
++ }
++
++ HalDev->InRxInt[Ch]=FALSE;
++
++ /* update stats */
++ HalDev->Stats.RxPacketsServiced[Ch] += PacketsServiced;
++ HalDev->Stats.RxTotal += PacketsServiced;
++ if (HalDev->Stats.RxMaxServiced < PacketsServiced)
++ HalDev->Stats.RxMaxServiced = PacketsServiced;
++
++ return (EC_NO_ERRORS);
++ }
++
++/*
++ * This function processes transmit interrupts. It traverses the
++ * transmit buffer queue, detecting sent data buffers and notifying the upper
++ * layer software via osSendComplete(). (for SAR, i originally had this split
++ * into two functions, one for each queue, but joined them on 8/8/02)
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param Queue Queue number to service (always 0 for MAC, Choose 1 for SAR to service low priority queue)
++ * @param MoreWork Flag that indicates that there is more work to do when set to 1.
++ *
++ * @return 0 if OK, non-zero otherwise.
++ */
++static int TxInt(HAL_DEVICE *HalDev, int Ch, int Queue, int *MoreWork)
++ {
++ HAL_TCB *CurrentTcb,*LastTcbProcessed,*FirstTcbProcessed;
++ int PacketsServiced;
++ bit32u TxFrameStatus;
++ int base = HalDev->dev_base, Ret;
++ int TxServiceMax = HalDev->ChData[Ch].TxServiceMax;
++ OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
++
++ int OtherQueue = Queue^1;
++
++/*+GSG 030303*//*+GSG 030303*/
++
++ /* Handle case of teardown interrupt. This must be checked at
++ the top of the function rather than the bottom, because
++ the normal data processing can wipe out the completion
++ pointer which is used to determine teardown complete. */
++ if (HalDev->TxTeardownPending[Ch] != 0)
++ {
++ Ret = TxTeardownInt(HalDev, Ch, Queue);
++ if (Ret == 0)
++ { /*+GSG 030303*/
++ *MoreWork = 0; /* bug fix 1/6 */ /*+GSG 030303*/
++ return (EC_NO_ERRORS);
++ } /*+GSG 030303*/
++ }
++
++ CurrentTcb = HalDev->TxActQueueHead[Ch][Queue];
++ FirstTcbProcessed=CurrentTcb;
++
++ if (CurrentTcb==0)
++ {
++ /* I saw this error a couple of times when multi-channels were added */
++ dbgPrintf("[cppi TxInt()]TxH int with no TCB in queue!\n");
++ dbgPrintf(" Ch=%d, CurrentTcb = 0x%08x\n", Ch, (bit32u)CurrentTcb);
++ dbgPrintf(" HalDev = 0x%08x\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ return(EC_CPPI|EC_FUNC_TXINT|EC_VAL_NULL_TCB);
++ }
++
++ osfuncDataCacheHitInvalidate((void *)CurrentTcb, 16);
++ TxFrameStatus=CurrentTcb->mode;
++ PacketsServiced=0;
++
++ /* should the ownership bit check be inside of the loop?? could make it a
++ while-do loop and take this check away */
++ if ((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
++ {
++ OsFunc->CriticalOn(); /* +GSG 030307 */
++ do
++ {
++ /* Pop TCB(s) for packet from the stack */
++ LastTcbProcessed=CurrentTcb->Eop;
++
++ /* new location for acknowledge */
++ /* Write the completion pointer */
++ (*(pTXH_CPPI_COMP_PTR( base )+( Ch *64)+( Queue ))) = VirtToPhys(LastTcbProcessed);
++
++ HalDev->TxActQueueHead[Ch][Queue] = LastTcbProcessed->Next;
++
++/*+GSG 030303*//*+GSG 030303*/
++
++ osfuncDataCacheHitInvalidate((void *)LastTcbProcessed, 16);
++
++ if (LastTcbProcessed->mode&CB_EOQ_BIT)
++ {
++ if (LastTcbProcessed->Next)
++ {
++ /* Misqueued packet */
++
++ HalDev->Stats.TxMisQCnt[Ch][Queue]++;
++
++ (*(pTX_DMA_STATE_WORD_0( base )+( Ch *64)+( Queue ))) = LastTcbProcessed->HNext;
++ }
++ else
++ {
++ /* Tx End of Queue */
++
++ HalDev->Stats.TxEOQCnt[Ch][Queue]++;
++
++ HalDev->TxActive[Ch][Queue]=FALSE;
++ }
++ }
++
++ OsFunc->SendComplete(CurrentTcb->OsInfo);
++
++ /* Push Tcb(s) back onto the stack */
++ CurrentTcb = LastTcbProcessed->Next;
++
++ LastTcbProcessed->Next=HalDev->TcbPool[Ch][Queue];
++
++ HalDev->TcbPool[Ch][Queue]=FirstTcbProcessed;
++
++ PacketsServiced++;
++
++ TxFrameStatus=CB_OWNERSHIP_BIT;
++ /* set the first(SOP) pointer for the next packet */
++ FirstTcbProcessed = CurrentTcb;
++ if (CurrentTcb)
++ {
++ osfuncDataCacheHitInvalidate((void *)CurrentTcb, 16);
++ TxFrameStatus=CurrentTcb->mode;
++ }
++
++ }while(((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
++ &&(PacketsServiced<TxServiceMax));
++
++ /* this fixes the SAR TurboDSL hardware bug (multiple queue failure) */
++ if (HalDev->TxActive[Ch][OtherQueue])
++ if (HalDev->TxActQueueHead[Ch][OtherQueue])
++ if ((*(pTX_DMA_STATE_WORD_0( base )+( Ch *64)+( OtherQueue ))) == 0)
++ {
++ osfuncDataCacheHitInvalidate(HalDev->TxActQueueHead[Ch][OtherQueue],16);
++ if ((HalDev->TxActQueueHead[Ch][OtherQueue]->mode) & CB_OWNERSHIP_BIT)
++ {
++ HalDev->TurboDslErrors++;
++ (*(pTX_DMA_STATE_WORD_0( base )+( Ch *64)+( OtherQueue ))) =
++ VirtToPhys(HalDev->TxActQueueHead[Ch][OtherQueue]);
++ }
++ }
++
++ OsFunc->CriticalOff(); /* +GSG 030307 */
++ if (((TxFrameStatus&CB_OWNERSHIP_BIT)==0)
++ &&(PacketsServiced==TxServiceMax))
++ {
++ *MoreWork = 1;
++ }
++ else
++ {
++ *MoreWork = 0;
++ }
++ }
++
++ /* update stats */
++ HalDev->Stats.TxPacketsServiced[Ch][Queue] += PacketsServiced;
++ HalDev->Stats.TxTotal += PacketsServiced;
++ if (HalDev->Stats.TxMaxServiced[Ch][Queue] < PacketsServiced)
++ HalDev->Stats.TxMaxServiced[Ch][Queue] = PacketsServiced;
++
++ return(EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function performs a teardown for the given channel. The value of the
++ * Mode parameter controls the operation of the function, as documented below.
++ *
++ * Note: If bit 3 of Mode is set, this call is blocking, and will not return
++ * until the teardown interrupt has occurred and been processed. While waiting
++ * for a blocking teardown to complete, ChannelTeardown() will signal the OS
++ * (via Control(.."Sleep"..)) to allow the OS to perform other tasks if
++ * necessary. If and only if bit 3 of Mode is clear, the CPHAL will call the
++ * OS TeardownComplete() function to indicate that the teardown has completed.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param Ch Channel number.
++ * @param Mode Bit 0 (LSB): Perform Tx teardown (if set).<BR>
++ * Bit 1: Perform Rx teardown (if set). <BR>
++ * Bit 2: If set, perform full teardown (free buffers/descriptors).
++ * If clear, perform partial teardown (keep buffers). <BR>
++ * Bit 3 (MSB): If set, call is blocking.
++ * If clear, call is non-blocking.
++ *
++ * @return EC_NO_ERRORS (ok). <BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
++ * @ref EC_VAL_TX_TEARDOWN_ALREADY_PEND "EC_VAL_TX_TEARDOWN_ALREADY_PEND"<BR>
++ * @ref EC_VAL_RX_TEARDOWN_ALREADY_PEND "EC_VAL_RX_TEARDOWN_ALREADY_PEND"<BR>
++ * @ref EC_VAL_TX_CH_ALREADY_TORNDOWN "EC_VAL_TX_CH_ALREADY_TORNDOWN"<BR>
++ * @ref EC_VAL_RX_CH_ALREADY_TORNDOWN "EC_VAL_RX_CH_ALREADY_TORNDOWN"<BR>
++ * @ref EC_VAL_TX_TEARDOWN_TIMEOUT "EC_VAL_TX_TEARDOWN_TIMEOUT"<BR>
++ * @ref EC_VAL_RX_TEARDOWN_TIMEOUT "EC_VAL_RX_TEARDOWN_TIMEOUT"<BR>
++ * @ref EC_VAL_LUT_NOT_READY "EC_VAL_LUT_NOT_READY"<BR>
++ */
++static int halChannelTeardown(HAL_DEVICE *HalDev, int Ch, bit32 Mode)
++ {
++ int DoTx, DoRx, Sleep=2048, timeout=0; /*MJH~030306*/
++ bit32u base = HalDev->dev_base;
++
++/* Set the module, used for error returns */
++
++ int Ret;
++
++ /* AAL5 only supports tearing down both sides at once (currently)*/
++ Mode = (Mode | TX_TEARDOWN | RX_TEARDOWN);
++
++ DoTx = (Mode & TX_TEARDOWN);
++ DoRx = (Mode & RX_TEARDOWN);
++
++ if (HalDev->State < enInitialized)
++ return(EC_AAL5 |EC_FUNC_CHTEARDOWN|EC_VAL_INVALID_STATE);
++
++ if ((Ch < 0) || (Ch > MAX_AAL5_CHAN ))
++ {
++ return(EC_AAL5 |EC_FUNC_CHTEARDOWN|EC_VAL_INVALID_CH);
++ }
++
++ /* set teardown pending bits before performing the teardown, because they
++ will be used in the int handler (this is done for AAL5) */
++ if (DoTx)
++ {
++ if (HalDev->TxTeardownPending[Ch] != 0)
++ return(EC_AAL5 |EC_FUNC_CHTEARDOWN|EC_VAL_TX_TEARDOWN_ALREADY_PEND);
++
++ /* If a full teardown, this also means that the user must
++ setup all channels again to use them */
++ if (Mode & FULL_TEARDOWN)
++ HalDev->ChIsSetup[Ch][DIRECTION_TX] = 0;
++
++ if (HalDev->State < enOpened)
++ {
++ /* if the hardware has never been opened, the channel has never actually
++ been setup in the hardware, so I just need to reset the software flag
++ and leave */
++ HalDev->ChIsSetup[Ch][DIRECTION_TX] = 0;
++ return (EC_NO_ERRORS);
++ }
++ else
++ {
++ if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == 0)
++ {
++ return(EC_AAL5 |EC_FUNC_CHTEARDOWN|EC_VAL_TX_CH_ALREADY_TORNDOWN);
++ }
++
++ /* set teardown flag */
++ HalDev->TxTeardownPending[Ch] = Mode;
++ }
++ }
++
++ if (DoRx)
++ {
++ if (HalDev->RxTeardownPending[Ch] != 0)
++ return(EC_AAL5 |EC_FUNC_CHTEARDOWN|EC_VAL_RX_TEARDOWN_ALREADY_PEND);
++
++ if (Mode & FULL_TEARDOWN)
++ HalDev->ChIsSetup[Ch][DIRECTION_RX] = 0;
++
++ if (HalDev->State < enOpened)
++ {
++ HalDev->ChIsSetup[Ch][DIRECTION_RX] = 0;
++ return (EC_NO_ERRORS);
++ }
++ else
++ {
++ if (HalDev->ChIsOpen[Ch][DIRECTION_RX] == 0)
++ return(EC_AAL5 |EC_FUNC_CHTEARDOWN|EC_VAL_RX_CH_ALREADY_TORNDOWN);
++
++ HalDev->RxTeardownPending[Ch] = Mode;
++ }
++ }
++
++ /* Perform Tx Teardown Duties */
++ if ((DoTx) && (HalDev->State == enOpened))
++ {
++ /* Request TX channel teardown */
++ (TX_CPPI_TEARDOWN_REG( base )) = Ch;
++
++ /* wait until teardown has completed */
++ if (Mode & BLOCKING_TEARDOWN)
++ {
++ timeout = 0;
++ while (HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE)
++ {
++ osfuncSleep(&Sleep);
++
++ timeout++;
++ if (timeout > 100000)
++ {
++ return(EC_AAL5 |EC_FUNC_CHTEARDOWN|EC_VAL_TX_TEARDOWN_TIMEOUT);
++ }
++ }
++ }
++ } /* if DoTx */
++
++ /* Perform Rx Teardown Duties */
++ if ((DoRx) && (HalDev->State == enOpened))
++ {
++
++ /* call main teardown routine for Rx */
++ Ret = HalDev->SarFunc->ChannelTeardown(HalDev->SarDev, Ch, Mode);
++ if (Ret) return (Ret);
++
++ if (Mode & BLOCKING_TEARDOWN)
++ {
++ timeout = 0;
++ while (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE)
++ {
++ osfuncSleep(&Sleep);
++
++ timeout++;
++ if (timeout > 100000)
++ {
++ return(EC_AAL5 |EC_FUNC_CHTEARDOWN|EC_VAL_RX_TEARDOWN_TIMEOUT);
++ }
++ }
++ }
++ } /* if DoRx */
++
++ return (EC_NO_ERRORS);
++ }
++
++/**
++ * @ingroup CPHAL_Functions
++ * This function closes the CPHAL module. The module will be reset.
++ * The Mode parameter should be used to determine the actions taken by
++ * Close().
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ * @param Mode Indicates actions to take on close. The following integer
++ * values are valid: <BR>
++ * 1: Does not free buffer resources, init parameters remain
++ * intact. User can then call Open() without calling Init()
++ * to attempt to reset the device and bring it back to the
++ * last known state.<BR>
++ * 2: Frees the buffer resources, but keeps init parameters. This
++ * option is a more aggressive means of attempting a device reset.
++ * 3: Frees the buffer resources, and clears all init parameters. <BR>
++ * At this point, the caller would have to call to completely
++ * reinitialize the device (Init()) before being able to call
++ * Open(). Use this mode if you are shutting down the module
++ * and do not plan to restart.
++ *
++ * @return EC_NO_ERRORS (ok).<BR>
++ * Possible Error Codes:<BR>
++ * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
++ * Any error code from halChannelTeardown().<BR>
++ */
++static int halClose(HAL_DEVICE *HalDev, bit32 Mode)
++ {
++ int Ch, Inst, Ret;
++ OS_DEVICE *TmpOsDev;
++ OS_FUNCTIONS *TmpOsFunc;
++ HAL_FUNCTIONS *TmpHalFunc;
++ char *TmpDeviceInfo;
++
++ CPSAR_FUNCTIONS *TmpSarFunc;
++ CPSAR_DEVICE *TmpSarDev;
++
++ /* Verify proper device state */
++ if (HalDev->State != enOpened)
++ return (EC_AAL5 | EC_FUNC_CLOSE|EC_VAL_INVALID_STATE);
++
++ /* Teardown all open channels */
++ for (Ch = 0; Ch <= MAX_AAL5_CHAN ; Ch++)
++ {
++ if (HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE)
++ {
++ if (Mode == 1)
++ {
++ Ret = halChannelTeardown(HalDev, Ch, TX_TEARDOWN | PARTIAL_TEARDOWN | BLOCKING_TEARDOWN);
++ if (Ret) return (Ret);
++ }
++ else
++ {
++ Ret = halChannelTeardown(HalDev, Ch, TX_TEARDOWN | FULL_TEARDOWN | BLOCKING_TEARDOWN);
++ if (Ret) return (Ret);
++ }
++ }
++
++ if (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE)
++ {
++ if (Mode == 1)
++ {
++ Ret = halChannelTeardown(HalDev, Ch, RX_TEARDOWN | PARTIAL_TEARDOWN | BLOCKING_TEARDOWN);
++ if (Ret) return (Ret);
++ }
++ else
++ {
++ Ret = halChannelTeardown(HalDev, Ch, RX_TEARDOWN | FULL_TEARDOWN | BLOCKING_TEARDOWN);
++ if (Ret) return (Ret);
++ }
++ }
++ }
++
++ /* free fraglist in HalDev */
++ HalDev->OsFunc->Free(HalDev->fraglist);
++ HalDev->fraglist = 0;
++
++ /* unregister the interrupt */
++ HalDev->OsFunc->IsrUnRegister(HalDev->OsDev, HalDev->interrupt);
++
++ /* Disable the Tx CPPI DMA */
++ TX_CPPI_CTL_REG(HalDev->dev_base) = 0;
++
++ /* Disable the Rx CPPI DMA */
++ RX_CPPI_CTL_REG(HalDev->dev_base) = 0;
++
++ /* Close the SAR hardware - puts the device in reset if this module is the
++ "last one out" */
++ HalDev->SarFunc->Close(HalDev->SarDev, Mode);
++
++ /* If mode is 3, than clear the HalDev and set next state to DevFound*/
++ if (Mode == 3)
++ {
++ /* I need to keep the HalDev parameters that were setup in InitModule */
++ TmpOsDev = HalDev->OsDev;
++ TmpOsFunc = HalDev->OsFunc;
++ TmpDeviceInfo = HalDev->DeviceInfo;
++
++ TmpSarFunc = HalDev->SarFunc;
++ TmpSarDev = HalDev->SarDev;
++
++ TmpHalFunc = HalDev->HalFuncPtr;
++ Inst = HalDev->Inst;
++
++ /* Clear HalDev */
++
++ HalDev->OsFunc->Memset(HalDev, 0, sizeof(HAL_DEVICE));
++
++ /* Restore key parameters */
++ HalDev->OsDev = TmpOsDev;
++ HalDev->OsFunc = TmpOsFunc;
++ HalDev->DeviceInfo = TmpDeviceInfo;
++
++ HalDev->SarFunc = TmpSarFunc;
++ HalDev->SarDev = TmpSarDev;
++
++ HalDev->HalFuncPtr = TmpHalFunc;
++ HalDev->Inst = Inst;
++
++ HalDev->State = enDevFound;
++ }
++ else
++ {
++ HalDev->State = enInitialized;
++ }
++
++ return(EC_NO_ERRORS);
++ }
+diff -urN linux.old/drivers/atm/sangam_atm/cpremap_cpaal5.c linux.dev/drivers/atm/sangam_atm/cpremap_cpaal5.c
+--- linux.old/drivers/atm/sangam_atm/cpremap_cpaal5.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpremap_cpaal5.c 2005-08-23 04:46:50.084845672 +0200
+@@ -0,0 +1,27 @@
++#ifndef _INC_CPREMAP_C
++#define _INC_CPREMAP_C
++
++#ifdef __ADAM2
++static inline void osfuncDataCacheHitInvalidate(void *ptr, int Size)
++ {
++ asm(" cache 17, (%0)" : : "r" (ptr));
++ }
++
++static inline void osfuncDataCacheHitWriteback(void *ptr, int Size)
++ {
++ asm(" cache 25, (%0)" : : "r" (ptr));
++ }
++
++#else
++ #define osfuncDataCacheHitInvalidate(MemPtr, Size) HalDev->OsFunc->DataCacheHitInvalidate(MemPtr, Size)
++ #define osfuncDataCacheHitWriteback(MemPtr, Size) HalDev->OsFunc->DataCacheHitWriteback(MemPtr, Size)
++#endif
++
++/*
++#define osfuncDataCacheHitInvalidate(ptr, Size) asm(" cache 17, (%0)" : : "r" (ptr))
++#define osfuncDataCacheHitWriteback(ptr, Size) asm(" cache 25, (%0)" : : "r" (ptr))
++*/
++
++
++
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/cpremap_cpsar.c linux.dev/drivers/atm/sangam_atm/cpremap_cpsar.c
+--- linux.old/drivers/atm/sangam_atm/cpremap_cpsar.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpremap_cpsar.c 2005-08-23 04:46:50.084845672 +0200
+@@ -0,0 +1,27 @@
++#ifndef _INC_CPREMAP_C
++#define _INC_CPREMAP_C
++
++#ifdef __ADAM2
++static inline void osfuncDataCacheHitInvalidate(void *ptr, int Size)
++ {
++ asm(" cache 17, (%0)" : : "r" (ptr));
++ }
++
++static inline void osfuncDataCacheHitWriteback(void *ptr, int Size)
++ {
++ asm(" cache 25, (%0)" : : "r" (ptr));
++ }
++
++#else
++ #define osfuncDataCacheHitInvalidate(MemPtr, Size) HalDev->OsFunc->DataCacheHitInvalidate(MemPtr, Size)
++ #define osfuncDataCacheHitWriteback(MemPtr, Size) HalDev->OsFunc->DataCacheHitWriteback(MemPtr, Size)
++#endif
++
++/*
++#define osfuncDataCacheHitInvalidate(ptr, Size) asm(" cache 17, (%0)" : : "r" (ptr))
++#define osfuncDataCacheHitWriteback(ptr, Size) asm(" cache 25, (%0)" : : "r" (ptr))
++*/
++
++
++
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/cpsar.c linux.dev/drivers/atm/sangam_atm/cpsar.c
+--- linux.old/drivers/atm/sangam_atm/cpsar.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpsar.c 2005-08-23 04:46:50.086845368 +0200
+@@ -0,0 +1,881 @@
++/**
++ * cpsar.c
++ *
++ * TNETDxxxx Software Support\n
++ * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * This file contains the HAL for the CPSAR module. In the software
++ * architecture, the CPSAR module is used exclusively by the AAL5 and AAL2
++ * CPHAL modules. AAL5 and AAL2 may utilize the same CPSAR instance
++ * simulataneously.
++ *
++ * version
++ * 5Sep02 Greg 1.00 Original Version created.
++ */
++
++/* register files */
++#include "cp_sar_reg.h"
++
++#define _CPHAL_CPSAR
++#define _CPHAL
++
++#define WAIT_THRESH 200000
++#define IRAM_SIZE 1536
++#define MAX_INST 2
++
++/* OS Data Structure definition */
++
++typedef void OS_PRIVATE;
++typedef void OS_DEVICE;
++typedef void OS_SENDINFO;
++typedef void OS_RECEIVEINFO;
++typedef void OS_SETUP;
++
++/* CPHAL Data Structure definitions */
++
++typedef struct cpsar_device CPSAR_DEVICE;
++typedef struct cpsar_device HAL_DEVICE;
++typedef void HAL_RECEIVEINFO;
++
++#define MAX_QUEUE 2
++#define MAX_CHAN 19
++
++#include "cpcommon_cpsar.h"
++#include "cpswhal_cpsar.h"
++#include "cpsar.h"
++#include "cpcommon_cpsar.c"
++
++static CPSAR_DEVICE *CpsarDev[MAX_INST]= {0,0};
++
++/*
++ * Returns statistics information.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return 0
++ */
++static int StatsGet3(CPSAR_DEVICE *HalDev)
++ {
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]StatsGet3(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++ /*
++ dbgPrintf("CPSAR General Stats:\n");
++ DispHexStat(HalDev, "Base Address",HalDev->dev_base);
++ DispStat(HalDev, "Offset (VLYNQ)",HalDev->offset);
++ DispStat(HalDev, "Debug Level",HalDev->debug);
++ DispStat(HalDev, "Instance",HalDev->Inst);
++ DispHexStat(HalDev, "Reset Address",HalDev->ResetBase);
++ DispStat(HalDev, "Reset Bit",HalDev->ResetBit);
++ */
++ return (EC_NO_ERRORS);
++ }
++
++/* +GSG 030407 */
++static void SetOamMode(HAL_DEVICE *HalDev)
++ {
++ int Ch;
++ volatile bit32u *pTmp;
++ int OamMode = (1<<8);
++
++ /* any configuration of OamMode affects all VC's, including AAL2 */
++ for (Ch = 0; Ch < MAX_CHAN; Ch++)
++ {
++ if (Ch < 16)
++ pTmp = (pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base) + (Ch*64));
++ else
++ pTmp = (pPDSP_AAL2_RX_STATE_WORD_0(HalDev->dev_base) + ((Ch-16)*64));
++
++ if (HalDev->OamMode == 0)
++ {
++ *pTmp &=~ OamMode;
++ }
++ else
++ {
++ *pTmp |= OamMode;
++ }
++ }
++ }
++
++static int halControl(CPSAR_DEVICE *HalDev, const char *Key, const char *Action, void *Value)
++ {
++ int KeyFound=0, ActionFound=0, rc=EC_NO_ERRORS, Ch; /* +RC3.02*/
++ char *TmpKey = (char *)Key;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]halControl(HalDev:%08x, Key:%s, Action:%s, Value:%08x)\n", (bit32u)HalDev,
++ Key, Action, (bit32u)Value);
++ osfuncSioFlush();
++ }
++#endif
++
++ if (HalDev->OsFunc->Strcmpi(Key, "Debug") == 0)
++ {
++ KeyFound=1; /* +RC3.02*/
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1; /* +RC3.02*/
++ HalDev->debug = *(int *)Value;
++ }
++ }
++
++ /* +GSG 030407 */
++ if (HalDev->OsFunc->Strcmpi(Key, "OamMode") == 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++ HalDev->OamMode = *(int *)Value;
++
++ /* only do this if we're open */
++ if (HalDev->OpenCount > 0)
++ SetOamMode(HalDev);
++ }
++
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ {
++ ActionFound=1;
++ *(int *)Value = HalDev->OamMode;
++ }
++ }
++
++ if (HalDev->OsFunc->Strcmpi(Key, "Stats3") == 0)
++ {
++ if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
++ StatsGet3(HalDev);
++ }
++
++ /* +RC3.02 (if statement) */
++ /* Fixes PITS #98 */
++ if (HalDev->OsFunc->Strstr(Key, "PdspEnable") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++
++ /* Configure PDSP enable bit based on Value*/
++ if (*(int *)Value & 1)
++ {
++ /* enable PDSP */
++ PDSP_CTRL_REG(HalDev->dev_base) |= 0x2;
++ }
++ else
++ {
++ /* disable PDSP */
++ PDSP_CTRL_REG(HalDev->dev_base) &=~ 0x2;
++ }
++ }
++ }
++
++ if (HalDev->OsFunc->Strstr(Key, "FwdUnkVc.") != 0)
++ {
++ KeyFound=1;
++ if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
++ {
++ ActionFound=1;
++
++ /* extract channel number */
++ TmpKey += HalDev->OsFunc->Strlen("FwdUnkVc.");
++ Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
++
++ /* Configure forwarding of unknown VCI/VPI cells */
++ SAR_PDSP_FWD_UNK_VC_REG(HalDev->dev_base) = (((*(int*)Value)<<31) | Ch);
++ }
++ }
++
++ if (KeyFound == 0) /* +RC3.02 */
++ rc = (EC_CPSAR|EC_FUNC_CONTROL|EC_VAL_KEY_NOT_FOUND); /* +RC3.02 */
++
++ if (ActionFound == 0) /* +RC3.02 */
++ rc = (EC_CPSAR|EC_FUNC_CONTROL|EC_VAL_ACTION_NOT_FOUND); /* +RC3.02 */
++
++ return(rc); /* ~RC3.02 */
++ }
++
++/*
++ * This function opens the specified channel.
++ *
++ * @param HalDev CPHAL module instance. (set by cphalInitModule())
++ * @param Ch Channel number.
++ *
++ * @return 0 OK, Non-zero Not OK
++ */
++static int halChannelSetup(CPSAR_DEVICE *HalDev, CHANNEL_INFO *HalCh)
++ {
++ int i;
++ int Ch = HalCh->Channel;
++ int PdspChBlock = Ch;
++ int PdspBlockOffset = 0;
++ volatile bit32u *pTmp;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]halChannelSetup(HalDev:%08x, HalCh:%08x)\n", (bit32u)HalDev,
++ (bit32u)HalCh);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Figure out the correct offset from the start of the PDSP
++ Scratchpad RAM (starting at 0x8050 in the SAR) */
++ if (Ch > 15)
++ {
++ /* this is an AAL2 channel, which are channels 16-18 */
++ PdspChBlock = Ch - 16;
++ /* Get the offset to the AAL2 portion of the block (in words) */
++ PdspBlockOffset = NUM_PDSP_AAL5_STATE_WORDS + (PdspChBlock*64);
++ /* Clear PDSP State RAM */
++ /*pTmp = (pPDSP_BLOCK_0(HalDev->dev_base)+PdspBlockOffset);
++ for (i=0; i<NUM_PDSP_AAL2_STATE_WORDS; i++)
++ *pTmp++ = 0;*/
++ }
++ else
++ {
++ /* Get the offset to the AAL5 portion of the block (in words) */
++ PdspBlockOffset = (PdspChBlock*64);
++ /* Clear PDSP State RAM */
++ /*pTmp = (pPDSP_BLOCK_0(HalDev->dev_base)+PdspBlockOffset);
++ for (i=0; i<NUM_PDSP_AAL5_STATE_WORDS; i++)
++ *pTmp++ = 0;*/
++ }
++
++ /* Configure PDSP State RAM */
++
++ /* Setup TX PDSP State RAM */
++ pTmp = (pPDSP_BLOCK_0(HalDev->dev_base)+PdspBlockOffset);
++ *pTmp++ = HalCh->TxVc_CellRate; /* Set the cell rate in cells/sec */
++ *pTmp++ = HalCh->TxVc_QosType; /* Configure the QoS Type */
++ *pTmp++ = HalCh->TxVc_Mbs; /* Set minimum burst size */
++ *pTmp++ = 0; /* (skip a register) */
++ *pTmp++ = HalCh->TxVc_Pcr; /* set the peak cell rate */
++ *pTmp++ = 0; /* new addition 4.9.02 */
++ *pTmp++ = HalCh->TxVc_AtmHeader; /* give the ATM header */
++ *pTmp++ = (HalCh->TxVc_OamTc << 8)
++ |(HalCh->TxVc_VpOffset); /* Set the OAM TC Path and VP Offset */
++
++ /* Setup RX PDSP State RAM */
++ *pTmp++ = (HalCh->RxVc_OamCh)|
++ (HalDev->OamMode << 8) |
++ (HalCh->RxVc_OamToHost<<9); /* Set OAM Channel, Mode, and ToHost options */
++ *pTmp++ = HalCh->RxVc_AtmHeader; /* ATM hdr put on firmware generated OAM */
++ *pTmp++ = (HalCh->RxVc_VpOffset)| /* Set Rx OAM TC Path and VP Offset */
++ (HalCh->RxVc_OamTc<<8);
++
++ /* Setup TX VP PDSP State RAM */
++ pTmp = (pPDSP_BLOCK_0(HalDev->dev_base)+PdspBlockOffset+16); /*GSG~030703 12->16 */
++ *pTmp++ = HalCh->TxVp_AtmHeader;
++ *pTmp++ = (HalCh->TxVp_OamTc << 8);
++
++ /* Setup RX VP PDSP State RAM */
++ pTmp = (pPDSP_BLOCK_0(HalDev->dev_base)+PdspBlockOffset+20); /*GSG~030703 16->20 */
++ *pTmp++ = HalCh->RxVp_AtmHeader;
++ *pTmp++ = (HalCh->RxVp_OamCh)|
++ (HalCh->RxVp_OamTc<<8)|
++ (HalCh->RxVp_OamToHost<<9); /* Set OAM Channel, Mode, and ToHost options */
++ *pTmp++ = 0;
++ *pTmp++ = HalCh->RxVp_OamVcList;
++
++ /* Configure forwarding of unknown VCI/VPI cells */
++ if (HalCh->PktType == 3)
++ SAR_PDSP_FWD_UNK_VC_REG(HalDev->dev_base) = ((HalCh->FwdUnkVc<<31)|Ch);
++
++ /* Configure Tx Channel Mapping Register (turn channel "ON") */
++ TX_CH_MAPPING_REG(HalDev->dev_base) = 0x80000000 |
++ (HalCh->DaMask << 30)
++ | (HalCh->Priority << 24) | Ch;
++
++ /* Setup Rx Channel in the LUT */
++ i=0;
++ while (!(RX_LUT_CH_SETUP_REQ_REG(HalDev->dev_base) & 0x80000000))
++ {
++ if (i > WAIT_THRESH)
++ {
++ return(EC_CPSAR|EC_FUNC_CHSETUP|EC_VAL_LUT_NOT_READY);
++ }
++ else
++ i++;
++ }
++
++ /* RX LUT is ready */
++ RX_LUT_CH_SETUP_REQ_REG(HalDev->dev_base) = (HalCh->PktType << 24) | Ch;
++ RX_LUT_CH_SETUP_REQ_VC_REG(HalDev->dev_base) = ((HalCh->Vpi << 20) |
++ (HalCh->Vci << 4));
++
++ return (EC_NO_ERRORS);
++ }
++
++static int halChannelTeardown(CPSAR_DEVICE *HalDev, int Ch, bit32 Mode)
++ {
++ int waitcnt = 0;
++ int PdspBlockOffset = 0, i;
++ volatile bit32u *pTmp;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]halChannelTeardown(HalDev:%08x, Ch:%d, Mode:%d\n",
++ (bit32u)HalDev, Ch, Mode);
++ osfuncSioFlush();
++ }
++#endif
++
++ if ((Ch < 0) || (Ch > MAX_CHAN))
++ return(EC_CPSAR|EC_FUNC_CHTEARDOWN|EC_VAL_INVALID_CH);
++
++ /* Request RX channel teardown through LUT */
++ while ((RX_LUT_CH_TEARDOWN_REQ_REG(HalDev->dev_base) & 0x80000000) == 0)
++ {
++ waitcnt++;
++ if (waitcnt == WAIT_THRESH)
++ {
++ return(EC_CPSAR|EC_FUNC_CHTEARDOWN|EC_VAL_LUT_NOT_READY);
++ }
++ }
++
++ RX_LUT_CH_TEARDOWN_REQ_REG(HalDev->dev_base) = (Ch & 0xffff);
++
++ /* for AAL2, clear channel PDSP RAM here. AAL5 does it when the teardown
++ has completed (which is asynchronous)*/
++ if (Ch > 15)
++ {
++ /* Get the offset to the AAL2 portion of the block (in words) */
++ PdspBlockOffset = NUM_PDSP_AAL5_STATE_WORDS + ((Ch-16)*64);
++ /* Clear PDSP State RAM */
++ pTmp = (pPDSP_BLOCK_0(HalDev->dev_base)+PdspBlockOffset);
++ for (i=0; i<NUM_PDSP_AAL2_STATE_WORDS; i++)
++ *pTmp++ = 0;
++ }
++
++ return (EC_NO_ERRORS);
++ }
++
++int InitPdsp(CPSAR_DEVICE *HalDev)
++ {
++ bit32u NumOfEntries,i,IRamAddress,iTmp;
++ int *SarPdspFirmware; /* ~GSG 030403 */
++ int FirmwareSize, rc; /* ~GSG 030403 */
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]InitPdsp(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Get firmware */
++ rc = HalDev->OsFunc->Control(HalDev->OsDev, "Firmware", "Get", &SarPdspFirmware); /* ~GSG 030403 */
++ if (rc) /* +GSG 030403 */
++ return (EC_CPSAR|EC_FUNC_OPEN|EC_VAL_KEY_NOT_FOUND); /* +GSG 030403 */
++
++ /* Get firmware size */
++ rc = HalDev->OsFunc->Control(HalDev->OsDev, "FirmwareSize", "Get", &FirmwareSize); /* ~GSG 030403 */
++ if (rc) /* +GSG 030403 */
++ return (EC_CPSAR|EC_FUNC_OPEN|EC_VAL_KEY_NOT_FOUND); /* +GSG 030403 */
++
++ IRamAddress = (bit32u) pPDSP_CTRL_REG(HalDev->dev_base);
++
++ NumOfEntries = (FirmwareSize)/4; /* ~GSG 030403 */
++ if (NumOfEntries > IRAM_SIZE)
++ {
++ /* Note: On Avalanche, they truncated the PDSP firmware and warned */
++ /* NumOfEntries = IRAM_SIZE; */
++ return(EC_CPSAR|EC_FUNC_INIT|EC_VAL_FIRMWARE_TOO_LARGE);
++ }
++ for(i=8;i<NumOfEntries;i++)
++ (*((bit32 *) (IRamAddress+(i*4))))=SarPdspFirmware[i]; /* ~GSG 030403 */
++
++ /* Check code */
++ for(i=8;i<NumOfEntries;i++)
++ {
++ iTmp=(*((bit32 *) (IRamAddress+(i*4))));
++ if (iTmp != SarPdspFirmware[i]) /* ~GSG 030403 */
++ {
++ return(EC_CPSAR|EC_FUNC_OPEN|EC_VAL_PDSP_LOAD_FAIL);
++ }
++ }
++
++ return(EC_NO_ERRORS);
++ }
++
++/*
++ * This function probes for the instance of the CPHAL module. It will call
++ * the OS function @c DeviceFindInfo() to get the information required.
++ *
++ * @param HalDev CPHAL module instance. (set by xxxInitModule())
++ *
++ * @return 0 OK, Otherwise error.
++ */
++static int halProbe(CPSAR_DEVICE *HalDev)
++ {
++ int Ret;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]halProbe(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(1))
++ {
++ dbgPrintf("[os]DeviceFindInfo(Inst:%d, DeviceName:%s, DeviceInfo:%08x)\n",
++ HalDev->Inst, "sar", (bit32u)&HalDev->DeviceInfo);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Attempt to find the device information */
++ Ret = HalDev->OsFunc->DeviceFindInfo(HalDev->Inst, "sar", &HalDev->DeviceInfo);
++ if (Ret)
++ return(EC_CPSAR|EC_FUNC_PROBE|EC_VAL_DEVICE_NOT_FOUND);
++
++ return(EC_NO_ERRORS);
++ }
++
++#ifdef __CPHAL_DEBUG
++static void dbgConfigDump(HAL_DEVICE *HalDev)
++ {
++ dbgPrintf(" [cpsar Inst %d] Config Dump:\n", HalDev->Inst);
++ dbgPrintf(" Base :%08x, offset :%08d\n",
++ HalDev->dev_base, HalDev->offset);
++ dbgPrintf(" ResetBit:%08d, ResetBase:%08x\n",
++ HalDev->ResetBit, HalDev->ResetBase);
++ dbgPrintf(" UniNni :%08d, debug :%08d\n",
++ HalDev->ResetBit, HalDev->debug);
++ osfuncSioFlush();
++ }
++#endif
++
++/*
++ * Sets up HAL default configuration parameter values.
++ */
++static void ConfigInit(CPSAR_DEVICE *HalDev)
++ {
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]ConfigInit(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++ /* configure some defaults with tnetd7300 values */
++ HalDev->dev_base = 0xa3000000;
++ HalDev->offset = 0;
++ HalDev->UniNni = CFG_UNI_NNI;
++ HalDev->ResetBit = 9;
++ HalDev->debug = 0;
++ HalDev->ResetBase = 0xa8611600;
++ }
++
++/*
++ * Retrieve HAL configuration parameter values.
++ */
++static bit32u ConfigGet(HAL_DEVICE *HalDev)
++ {
++ bit32u ParmValue, error_code;
++ char *DeviceInfo = HalDev->DeviceInfo;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]ConfigGet(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* get the configuration parameters common to all modules */
++ error_code = ConfigGetCommon(HalDev);
++ if (error_code) return (EC_CPSAR|error_code);
++
++ /* get SAR specific configuration parameters */
++ error_code = HalDev->OsFunc->DeviceFindParmUint(DeviceInfo,"UniNni",&ParmValue);
++ if (!error_code) HalDev->UniNni = ParmValue;
++
++ return (EC_NO_ERRORS);
++ }
++
++static int halInit(CPSAR_DEVICE *HalDev)
++ {
++ bit32u Ret;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]halInit(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(7))
++ {
++ dbgPrintf("[cpsar halInit()]InitCount = %d\n", HalDev->InitCount);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Only run the init code for the first calling module per instance */
++ if (HalDev->InitCount > 1)
++ {
++ return (EC_NO_ERRORS);
++ }
++
++ /* Configure HAL defaults */
++ ConfigInit(HalDev);
++
++ /* Retrieve HAL configuration parameters from data store */
++ Ret = ConfigGet(HalDev);
++ if (Ret) return (Ret);
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(9))
++ dbgConfigDump(HalDev);
++#endif
++
++ return(EC_NO_ERRORS);
++ }
++
++static int halOpen(CPSAR_DEVICE *HalDev)
++ {
++ int Ret, Ticks=64;
++ int i; /*+GSG 030407*/
++ volatile int *pTmp; /*+GSG 030407*/
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]halOpen(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(7))
++ {
++ dbgPrintf("[cpsar halOpen()]OpenCount = %d\n", HalDev->OpenCount);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Only run the open code for the first calling module per instance */
++ if (HalDev->OpenCount++ > 0)
++ {
++ return (EC_NO_ERRORS);
++ }
++
++ /* Take SAR out of reset */
++ if (((*(volatile bit32u *)(HalDev->ResetBase)) & (1<<HalDev->ResetBit)) != 0)
++ {
++ /** @todo Should I somehow call AAL5/AAL2 Close() here? All I've done
++ here is copy the Close code from each and paste it here. */
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(7))
++ {
++ dbgPrintf("[cpsar halOpen()]Module was already out of reset.\n");
++ dbgPrintf(" Closing module and resetting.\n");
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Disable the Tx CPPI DMA */
++ TX_CPPI_CTL_REG(HalDev->dev_base) = 0;
++
++ /* Disable the Rx CPPI DMA */
++ RX_CPPI_CTL_REG(HalDev->dev_base) = 0;
++
++ /* Disable the PDSP */
++ PDSP_CTRL_REG(HalDev->dev_base) &=~ 0x00000002;
++
++ /* disable interrupt masks */
++ SAR_TX_MASK_CLR(HalDev->dev_base) = 0xffffffff;
++ SAR_RX_MASK_CLR(HalDev->dev_base) = 0xffffffff;
++
++#ifndef NO_RESET /* GSG+ 030428 */
++ /* clear reset bit */
++ (*(volatile bit32u *)(HalDev->ResetBase)) &=~ (1<<HalDev->ResetBit); /* ~GSG 030307 */
++ HalDev->OsFunc->Control(HalDev->OsDev, "Sleep", "", &Ticks);
++
++ /* set reset bit */
++ (*(volatile bit32u *)(HalDev->ResetBase)) |= (1<<HalDev->ResetBit); /* ~GSG 030307 */
++ HalDev->OsFunc->Control(HalDev->OsDev, "Sleep", "", &Ticks);
++#endif /* GSG+ 030428 */
++ }
++ else
++ {
++ (*(volatile bit32u *)(HalDev->ResetBase)) |= (1<<HalDev->ResetBit); /* ~GSG 030307 */
++ HalDev->OsFunc->Control(HalDev->OsDev, "Sleep", "", &Ticks);
++ }
++
++ /* Configure UNI/NNI */
++ RX_LUT_GLOBAL_CFG_REG(HalDev->dev_base) |= (HalDev->UniNni & 0x1);
++
++ /* Clear entire PDSP state RAM */ /*+GSG 030407*/
++ pTmp = (pTX_DMA_STATE_WORD_0(HalDev->dev_base)); /*+GSG 030407*/
++ for (i=0; i<PDSP_STATE_RAM_SIZE; i++) /*+GSG 030407*/
++ *pTmp++ = 0; /*+GSG 030407*/
++
++ /* Configure Oam Mode */ /*+GSG 030407*/
++ SetOamMode(HalDev); /*+GSG 030407*/
++
++ /* Initialize PDSP */
++ Ret=InitPdsp(HalDev);
++ if(Ret)
++ return(Ret);
++
++ /* Reset and Enable the PDSP */
++ PDSP_CTRL_REG(HalDev->dev_base) = 0x00080003;
++
++ return(EC_NO_ERRORS);
++ }
++
++static int halClose(CPSAR_DEVICE *HalDev, int Mode)
++ {
++ int Ticks = 64;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]halClose(HalDev:%08x, Mode:%d)\n", (bit32u)HalDev, Mode);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* handle the error case if there is nothing open */
++ if (HalDev->OpenCount == 0)
++ {
++ return(EC_CPSAR|EC_FUNC_CLOSE|EC_VAL_MODULE_ALREADY_CLOSED);
++ }
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(7))
++ {
++ dbgPrintf("[cpsar halClose()]OpenCount = %d\n", HalDev->OpenCount);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Only run the close code for the last calling module per instance */
++ if (HalDev->OpenCount-- > 1)
++ {
++ return (EC_NO_ERRORS);
++ }
++
++ /* Disable the PDSP */
++ PDSP_CTRL_REG(HalDev->dev_base) &=~ 0x00000002;
++
++#ifndef NO_RESET /* GSG +030428 */
++ /* put device back into reset */
++ (*(volatile bit32u *)(HalDev->ResetBase)) &=~ (1<<HalDev->ResetBit); /* ~GSG 030307 */
++ HalDev->OsFunc->Control(HalDev->OsDev, "Sleep", "", &Ticks);
++#endif /* GSG +030428 */
++
++ return(EC_NO_ERRORS);
++ }
++
++static int halShutdown(CPSAR_DEVICE *HalDev)
++ {
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]halShutdown(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* handle the error case */
++ if (HalDev->InitCount == 0)
++ {
++ return(EC_CPSAR|EC_FUNC_CLOSE|EC_VAL_MODULE_ALREADY_SHUTDOWN);
++ }
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(7))
++ {
++ dbgPrintf("[cpsar halShutdown()]InitCount = %d\n", HalDev->InitCount);
++ osfuncSioFlush();
++ }
++#endif
++
++ /* Only run the shutdown code for the last calling module per instance */
++ if (HalDev->InitCount-- > 1)
++ {
++ return (EC_NO_ERRORS);
++ }
++
++ /* free the SAR functions */
++#ifdef __CPHAL_DEBUG
++ if (DBG(6))
++ {
++ dbgPrintf(" [cpsar halShutdown()]: Free CPSAR function pointers\n");
++ osfuncSioFlush();
++ }
++ if (DBG(1)||DBG(3))
++ {
++ dbgPrintf("[os]Free(MemPtr:%08x)\n", (bit32u)HalDev->HalFuncPtr);
++ osfuncSioFlush();
++ }
++#endif
++ /* free the HalFunc */
++ HalDev->OsFunc->Free(HalDev->HalFuncPtr);
++
++ /* we have a static global, so I should clear it's value as well */
++ CpsarDev[HalDev->Inst] = 0;
++
++#ifdef __CPHAL_DEBUG
++ if (DBG(6))
++ {
++ dbgPrintf(" [cpsar halShutdown()]Free HalDev\n");
++ osfuncSioFlush();
++ }
++ if (DBG(1)||DBG(3))
++ {
++ dbgPrintf("[os]Free(MemPtr:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++ /* free the CPSAR device */
++ HalDev->OsFunc->Free(HalDev);
++
++ return(EC_NO_ERRORS);
++ }
++
++static int halTick(CPSAR_DEVICE *HalDev)
++ {
++#ifdef __CPHAL_DEBUG
++ if (DBG(0))
++ {
++ dbgPrintf("[cpsar]halTick(HalDev:%08x)\n", (bit32u)HalDev);
++ osfuncSioFlush();
++ }
++#endif
++
++ return(EC_NO_ERRORS);
++ }
++
++/*
++ * The CPSAR version of InitModule() should be passed the OS_FUNCTIONS pointer,
++ * and will return the HalDev pointer.
++ *
++ * @param HalDev Pointer to CPSAR module information. This will
++ * be used by the OS when communicating to this module via
++ * CPSAR.
++ * @param OsDev Pointer to OS device information. This will be saved by
++ * the CPSAR and returned to the OS when required.
++ * @param HalFunc HAL_FUNCTIONS pointer.
++ * @param Size Pointer to the size of the HAL_FUNCTIONS structure. (If
++ * HalFunc is 0, the value will be set by CPSAR, otherwise
++ * ignored)
++ * @param Inst The instance number of the module to initialize. (start at
++ * 0).
++ *
++ * @return 0 OK, Nonzero - error.
++ */
++/*
++int cpsarInitModule(CPSAR_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ CPSAR_FUNCTIONS *HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int *Size,
++ int Inst)
++*/
++int cpsarInitModule(CPSAR_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ CPSAR_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst)
++ {
++ CPSAR_DEVICE *HalPtr;
++ CPSAR_FUNCTIONS *HalFuncPtr;
++
++ /*
++ if ( HalFunc == 0 )
++ {
++ *Size = sizeof(CPSAR_FUNCTIONS);
++ return(EC_NO_ERRORS);
++ }
++ */
++
++ if (CpsarDev[Inst] != 0)
++ {
++ /* this SAR module has been connected to before, so do not
++ allocate another CPSAR_DEVICE */
++ HalPtr = CpsarDev[Inst];
++
++ /* increase count of attached modules */
++ HalPtr->InitCount++;
++ }
++ else
++ {
++ /* allocate the CPSAR_DEVICE structure */
++ HalPtr = (CPSAR_DEVICE *) OsFunc->MallocDev(sizeof(CPSAR_DEVICE));
++ if(!HalPtr)
++ return(EC_CPSAR|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_DEV_FAILED);
++
++ HalFuncPtr = (CPSAR_FUNCTIONS *) OsFunc->Malloc(sizeof(CPSAR_FUNCTIONS));
++ if (!HalFuncPtr)
++ return (EC_CPSAR|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_FAILED);
++
++ /* Initialize the size of hal functions */
++ *HalFuncSize = sizeof (CPSAR_FUNCTIONS);
++
++ /* ensure the device structure is cleared */
++ OsFunc->Memset(HalPtr, 0, sizeof(CPSAR_DEVICE));
++
++ /* clear the function pointers */
++ OsFunc->Memset(HalFuncPtr, 0, sizeof(CPSAR_FUNCTIONS));
++
++ /* Supply pointers for the CPSAR API functions */
++ HalFuncPtr->ChannelSetup = halChannelSetup;
++ HalFuncPtr->ChannelTeardown = halChannelTeardown;
++ HalFuncPtr->Close = halClose;
++ HalFuncPtr->Control = halControl;
++ HalFuncPtr->Init = halInit;
++ HalFuncPtr->Open = halOpen;
++ HalFuncPtr->Probe = halProbe;
++ HalFuncPtr->Shutdown = halShutdown;
++ HalFuncPtr->Tick = halTick;
++
++ /* keep a reference to HalFuncPtr so I can free it later */
++ HalPtr->HalFuncPtr = HalFuncPtr;
++
++ /* store the CPSAR_DEVICE, so the CPSAR module will know whether
++ it is in use for the given instance */
++ CpsarDev[Inst] = HalPtr;
++
++ /* increase count of attached modules */
++ HalPtr->InitCount++;
++ }
++
++ /* @todo Does this need modification to deal with multiple callers/
++ drivers? If different callers will use different OsDev/OsFunc,
++ then the current code will not work.
++ */
++
++ /* initialize the CPSAR_DEVICE structure */
++ HalPtr->OsDev = OsDev;
++ /*HalPtr->OsOpen = OsDev;*/
++ HalPtr->Inst = Inst;
++ HalPtr->OsFunc = OsFunc;
++
++ /* pass the HalPtr back to the caller */
++ *HalDev = HalPtr;
++ *HalFunc = HalPtr->HalFuncPtr;
++
++ return (EC_NO_ERRORS);
++ }
+diff -urN linux.old/drivers/atm/sangam_atm/cpsar_cpaal5.h linux.dev/drivers/atm/sangam_atm/cpsar_cpaal5.h
+--- linux.old/drivers/atm/sangam_atm/cpsar_cpaal5.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpsar_cpaal5.h 2005-08-23 04:46:50.087845216 +0200
+@@ -0,0 +1,103 @@
++/*******************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE: cpsar.h
++ *
++ * DESCRIPTION:
++ * This file contains data structure definitions for the CPSAR HAL.
++ *
++ * HISTORY:
++ * 6Sep02 Greg 1.00 Original Version created.
++ *
++ *****************************************************************************/
++#ifndef _INC_CPSAR
++#define _INC_CPSAR
++
++#define NUM_RX_STATE_WORDS 7
++#define NUM_TX_STATE_WORDS 9
++#define MAX_CHAN 19
++
++
++#ifndef _CPHAL_CPSAR
++typedef void CPSAR_DEVICE;
++#endif
++
++/*
++ * HAL Default Parameter Values
++ */
++#define CFG_UNI_NNI 0
++
++/**
++ * @ingroup shared_data
++ *
++ * List of defined keys for use with Control().
++ */
++typedef enum
++ {
++ /* SAR */
++ enGET_FIRMWARE, /**< Used by the SAR to request a pointer to firmware */
++ enGET_FIRMWARE_SIZE, /**< Used by the SAR to request the size of the firmware */
++ enEND=9999 /* Last entry */
++ }INFO_KEY;
++
++/*
++ * The CPHAL_FUNCTIONS struct defines the CPHAL function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to cphalInitModule().
++ */
++typedef struct
++ {
++ int (*ChannelSetup)(CPSAR_DEVICE *HalDev, CHANNEL_INFO *HalCh);
++ int (*ChannelTeardown)(CPSAR_DEVICE *HalDev, int Ch, int Mode);
++ int (*Close)(CPSAR_DEVICE *HalDev, int Mode);
++ int (*Control)(CPSAR_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
++ int (*Init)(CPSAR_DEVICE *HalDev);
++ int (*ModeChange)(CPSAR_DEVICE *HalDev, char *DeviceParms);
++ int (*Open)(CPSAR_DEVICE *HalDev);
++ int (*Probe)(CPSAR_DEVICE *HalDev);
++ int (*Shutdown)(CPSAR_DEVICE *HalDev);
++ int (*Tick)(CPSAR_DEVICE *HalDev);
++ } CPSAR_FUNCTIONS;
++
++/*
++ * This is the data structure for a generic HAL device. It contains all device
++ * specific data for a single instance of that device. This includes Rx/Tx
++ * buffer queues, device base address, reset bit, and other information.
++ */
++typedef struct cpsar_device
++ {
++ bit32 dev_base;
++ bit32 offset;
++ bit32 TxTeardownPending[MAX_CHAN];
++ bit32 RxTeardownPending[MAX_CHAN];
++ bit32 ChIsOpen[MAX_CHAN];
++ bit32 ResetBit;
++ bit32 debug;
++ OS_DEVICE *OsDev;
++ OS_FUNCTIONS *OsFunc;
++ /*void *OsOpen;*/
++ bit32 UniNni;
++ bit32 Inst;
++ bit32u DeviceCPID[4];
++ bit32u LBSourceLLID[4];
++ bit32u OamRate[11];
++ CHANNEL_INFO ChData[MAX_CHAN];
++ int InitCount;
++ int OpenCount;
++ char *DeviceInfo;
++ bit32u ResetBase;
++ DEVICE_STATE State;
++ CPSAR_FUNCTIONS *HalFuncPtr;
++ int OamMode; /* +GSG 030407 */
++ }CPSARDEVICE;
++
++extern int cpsarInitModule(CPSAR_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ CPSAR_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/cpsar.h linux.dev/drivers/atm/sangam_atm/cpsar.h
+--- linux.old/drivers/atm/sangam_atm/cpsar.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpsar.h 2005-08-23 04:46:50.087845216 +0200
+@@ -0,0 +1,103 @@
++/*******************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE: cpsar.h
++ *
++ * DESCRIPTION:
++ * This file contains data structure definitions for the CPSAR HAL.
++ *
++ * HISTORY:
++ * 6Sep02 Greg 1.00 Original Version created.
++ *
++ *****************************************************************************/
++#ifndef _INC_CPSAR
++#define _INC_CPSAR
++
++#define NUM_RX_STATE_WORDS 7
++#define NUM_TX_STATE_WORDS 9
++#define MAX_CHAN 19
++
++
++#ifndef _CPHAL_CPSAR
++typedef void CPSAR_DEVICE;
++#endif
++
++/*
++ * HAL Default Parameter Values
++ */
++#define CFG_UNI_NNI 0
++
++/**
++ * @ingroup shared_data
++ *
++ * List of defined keys for use with Control().
++ */
++typedef enum
++ {
++ /* SAR */
++ enGET_FIRMWARE, /**< Used by the SAR to request a pointer to firmware */
++ enGET_FIRMWARE_SIZE, /**< Used by the SAR to request the size of the firmware */
++ enEND=9999 /* Last entry */
++ }INFO_KEY;
++
++/*
++ * The CPHAL_FUNCTIONS struct defines the CPHAL function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to cphalInitModule().
++ */
++typedef struct
++ {
++ int (*ChannelSetup)(CPSAR_DEVICE *HalDev, CHANNEL_INFO *HalCh);
++ int (*ChannelTeardown)(CPSAR_DEVICE *HalDev, int Ch, int Mode);
++ int (*Close)(CPSAR_DEVICE *HalDev, int Mode);
++ int (*Control)(CPSAR_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
++ int (*Init)(CPSAR_DEVICE *HalDev);
++ int (*ModeChange)(CPSAR_DEVICE *HalDev, char *DeviceParms);
++ int (*Open)(CPSAR_DEVICE *HalDev);
++ int (*Probe)(CPSAR_DEVICE *HalDev);
++ int (*Shutdown)(CPSAR_DEVICE *HalDev);
++ int (*Tick)(CPSAR_DEVICE *HalDev);
++ } CPSAR_FUNCTIONS;
++
++/*
++ * This is the data structure for a generic HAL device. It contains all device
++ * specific data for a single instance of that device. This includes Rx/Tx
++ * buffer queues, device base address, reset bit, and other information.
++ */
++typedef struct cpsar_device
++ {
++ bit32 dev_base;
++ bit32 offset;
++ bit32 TxTeardownPending[MAX_CHAN];
++ bit32 RxTeardownPending[MAX_CHAN];
++ bit32 ChIsOpen[MAX_CHAN];
++ bit32 ResetBit;
++ bit32 debug;
++ OS_DEVICE *OsDev;
++ OS_FUNCTIONS *OsFunc;
++ /*void *OsOpen;*/
++ bit32 UniNni;
++ bit32 Inst;
++ bit32u DeviceCPID[4];
++ bit32u LBSourceLLID[4];
++ bit32u OamRate[11];
++ CHANNEL_INFO ChData[MAX_CHAN];
++ int InitCount;
++ int OpenCount;
++ char *DeviceInfo;
++ bit32u ResetBase;
++ DEVICE_STATE State;
++ CPSAR_FUNCTIONS *HalFuncPtr;
++ int OamMode; /* +GSG 030407 */
++ }CPSARDEVICE;
++
++extern int cpsarInitModule(CPSAR_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ CPSAR_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/cp_sar_reg.h linux.dev/drivers/atm/sangam_atm/cp_sar_reg.h
+--- linux.old/drivers/atm/sangam_atm/cp_sar_reg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cp_sar_reg.h 2005-08-23 04:46:50.087845216 +0200
+@@ -0,0 +1,217 @@
++/***************************************************************************
++ TNETD73xx Software Support
++ Copyright(c) 2000, Texas Instruments Incorporated. All Rights Reserved.
++
++ FILE: cp_sar_reg.h Register definitions for the SAR module
++
++ DESCRIPTION:
++ This include file contains register definitions for the
++ SAR module.
++
++ HISTORY:
++ 15 Jan 02 G. Guyotte Original version written
++ 03 Oct 02 G. Guyotte C++ style comments removed
++****************************************************************************/
++#ifndef _INC_SAR_REG
++#define _INC_SAR_REG
++
++/* Global Registers */
++#define pSAR_ID_REG(base) ((volatile bit32u *)(base+0x0000))
++#define SAR_ID_REG(base) (*pSAR_ID_REG(base))
++#define pSAR_STATUS_SET_REG(base) ((volatile bit32u *)(base+0x0008))
++#define SAR_STATUS_SET_REG(base) (*pSAR_STATUS_SET_REG(base))
++#define pSAR_STATUS_CLR_REG(base) ((volatile bit32u *)(base+0x000C))
++#define SAR_STATUS_CLR_REG(base) (*pSAR_STATUS_CLR_REG(base))
++#define pSAR_HOST_INT_EN_SET_REG(base) ((volatile bit32u *)(base+0x0010))
++#define SAR_HOST_INT_EN_SET_REG(base) (*pSAR_HOST_INT_EN_SET_REG(base))
++#define pSAR_HOST_INT_EN_CLR_REG(base) ((volatile bit32u *)(base+0x0014))
++#define SAR_HOST_INT_EN_CLR_REG(base) (*pSAR_HOST_INT_EN_CLR_REG(base))
++#define pSAR_PDSP_INT_EN_SET_REG(base) ((volatile bit32u *)(base+0x0018))
++#define SAR_PDSP_INT_EN_SET_REG(base) (*pSAR_PDSP_INT_EN_SET_REG(base))
++#define pSAR_PDSP_INT_EN_CLR_REG(base) ((volatile bit32u *)(base+0x001C))
++#define SAR_PDSP_INT_EN_CLR_REG(base) (*pSAR_PDSP_INT_EN_CLR_REG(base))
++
++/* PDSP OAM General Purpose Registers */
++#define pSAR_PDSP_HOST_OAM_CONFIG_REG(base) ((volatile bit32u *)(base+0x0020))
++#define SAR_PDSP_HOST_OAM_CONFIG_REG(base) (*pSAR_PDSP_HOST_OAM_CONFIG_REG(base))
++#define pSAR_PDSP_OAM_CORR_REG(base) ((volatile bit32u *)(base+0x0024))
++#define SAR_PDSP_OAM_CORR_REG(base) (*pSAR_PDSP_OAM_CORR_REG(base))
++#define pSAR_PDSP_OAM_LB_RESULT_REG(base) ((volatile bit32u *)(base+0x0028))
++#define SAR_PDSP_OAM_LB_RESULT_REG(base) (*pSAR_PDSP_OAM_LB_RESULT_REG(base))
++#define pSAR_PDSP_OAM_F5_LB_COUNT_REG(base) ((volatile bit32u *)(base+0x002c)) /* +GSG 030416 */
++#define SAR_PDSP_OAM_F5_LB_COUNT_REG(base) (*pSAR_PDSP_OAM_F5_LB_COUNT_REG(base)) /* +GSG 030416 */
++#define pSAR_PDSP_OAM_F4_LB_COUNT_REG(base) ((volatile bit32u *)(base+0x0030)) /* +GSG 030416 */
++#define SAR_PDSP_OAM_F4_LB_COUNT_REG(base) (*pSAR_PDSP_OAM_F4_LB_COUNT_REG(base)) /* +GSG 030416 */
++#define pSAR_PDSP_FWD_UNK_VC_REG(base) ((volatile bit32u *)(base+0x0034)) /* +GSG 030701 */
++#define SAR_PDSP_FWD_UNK_VC_REG(base) (*pSAR_PDSP_FWD_UNK_VC_REG(base)) /* +GSG 030701 */
++
++
++/* Rx Lookup Table Registers */
++#define pRX_LUT_GLOBAL_CFG_REG(base) ((volatile bit32u *)(base+0x0080))
++#define RX_LUT_GLOBAL_CFG_REG(base) (*pRX_LUT_GLOBAL_CFG_REG(base))
++#define pRX_LUT_CH_SETUP_REQ_REG(base) ((volatile bit32u *)(base+0x0090))
++#define RX_LUT_CH_SETUP_REQ_REG(base) (*pRX_LUT_CH_SETUP_REQ_REG(base))
++#define pRX_LUT_CH_SETUP_REQ_VC_REG(base) ((volatile bit32u *)(base+0x0094))
++#define RX_LUT_CH_SETUP_REQ_VC_REG(base) (*pRX_LUT_CH_SETUP_REQ_VC_REG(base))
++#define pRX_LUT_CH_TEARDOWN_REQ_REG(base) ((volatile bit32u *)(base+0x009C))
++#define RX_LUT_CH_TEARDOWN_REQ_REG(base) (*pRX_LUT_CH_TEARDOWN_REQ_REG(base))
++
++/* Tx Scheduler Registers */
++#define pTX_CH_MAPPING_REG(base) ((volatile bit32u *)(base+0x0170))
++#define TX_CH_MAPPING_REG(base) (*pTX_CH_MAPPING_REG(base))
++
++/* Tx CPPI DMA Controller Registers */
++#define pTX_CPPI_CTL_REG(base) ((volatile bit32u *)(base+0x0700))
++#define TX_CPPI_CTL_REG(base) (*pTX_CPPI_CTL_REG(base))
++#define pTX_CPPI_TEARDOWN_REG(base) ((volatile bit32u *)(base+0x0704))
++#define TX_CPPI_TEARDOWN_REG(base) (*pTX_CPPI_TEARDOWN_REG(base))
++
++/* EOI Interrupt Additions */
++#define pSAR_EOI(base) ((volatile bit32u *)(base+0x0708))
++#define SAR_EOI(base) (*pSAR_EOI(base))
++#define pSAR_INTR_VECTOR(base) ((volatile bit32u *)(base+0x070c))
++#define SAR_INTR_VECTOR(base) (*pSAR_INTR_VECTOR(base))
++#define pSAR_TX_MASKED_STATUS(base) ((volatile bit32u *)(base+0x0710))
++#define SAR_TX_MASKED_STATUS(base) (*pSAR_TX_MASKED_STATUS(base))
++#define pSAR_TX_RAW_STATUS(base) ((volatile bit32u *)(base+0x0714))
++#define SAR_TX_RAW_STATUS(base) (*pSAR_TX_RAW_STATUS(base))
++#define pSAR_TX_MASK_SET(base) ((volatile bit32u *)(base+0x0718))
++#define SAR_TX_MASK_SET(base) (*pSAR_TX_MASK_SET(base))
++#define pSAR_TX_MASK_CLR(base) ((volatile bit32u *)(base+0x071c))
++#define SAR_TX_MASK_CLR(base) (*pSAR_TX_MASK_CLR(base))
++
++/* Rx CPPI DMA Controller Registers */
++#define pRX_CPPI_CTL_REG(base) ((volatile bit32u *)(base+0x0780))
++#define RX_CPPI_CTL_REG(base) (*pRX_CPPI_CTL_REG(base))
++#define pSAR_RX_MASKED_STATUS(base) ((volatile bit32u *)(base+0x0790))
++#define SAR_RX_MASKED_STATUS(base) (*pSAR_RX_MASKED_STATUS(base))
++#define pSAR_RX_RAW_STATUS(base) ((volatile bit32u *)(base+0x0794))
++#define SAR_RX_RAW_STATUS(base) (*pSAR_RX_RAW_STATUS(base))
++#define pSAR_RX_MASK_SET(base) ((volatile bit32u *)(base+0x0798))
++#define SAR_RX_MASK_SET(base) (*pSAR_RX_MASK_SET(base))
++#define pSAR_RX_MASK_CLR(base) ((volatile bit32u *)(base+0x079c))
++#define SAR_RX_MASK_CLR(base) (*pSAR_RX_MASK_CLR(base))
++
++/* PDSP Control/Status Registers */
++#define pPDSP_CTRL_REG(base) ((volatile bit32u *)(base+0x4000))
++#define PDSP_CTRL_REG(base) (*pPDSP_CTRL_REG(base))
++
++/* PDSP Instruction RAM */
++#define pPDSP_IRAM(base) ((volatile bit32u *)(base+0x4020))
++#define PDSP_IRAM(base) (*pPDSP_IRAM(base))
++
++/*
++ * Channel 0 State/Scratchpad RAM Block
++ *
++ * The following registers (Tx DMA State, Rx DMA State, CPPI Completion PTR,
++ * and PDSP Data) have been given the correct address for channel 0. To
++ * reach the registers for channel X, add (X * 0x100) to the pointer address.
++ *
++ */
++
++#define PDSP_STATE_RAM_SIZE 1024
++
++/* Tx DMA State RAM */
++#define pTX_DMA_STATE_WORD_0(base) ((volatile bit32u *)(base+0x8000))
++#define TX_DMA_STATE_WORD_0(base) (*pTX_DMA_STATE_WORD_0(base))
++#define pTX_DMA_STATE_WORD_1(base) ((volatile bit32u *)(base+0x8004))
++#define TX_DMA_STATE_WORD_1(base) (*pTX_DMA_STATE_WORD_1(base))
++#define pTX_DMA_STATE_WORD_2(base) ((volatile bit32u *)(base+0x8008))
++#define TX_DMA_STATE_WORD_2(base) (*pTX_DMA_STATE_WORD_2(base))
++#define pTX_DMA_STATE_WORD_3(base) ((volatile bit32u *)(base+0x800C))
++#define TX_DMA_STATE_WORD_3(base) (*pTX_DMA_STATE_WORD_3(base))
++#define pTX_DMA_STATE_WORD_4(base) ((volatile bit32u *)(base+0x8010))
++#define TX_DMA_STATE_WORD_4(base) (*pTX_DMA_STATE_WORD_4(base))
++#define pTX_DMA_STATE_WORD_5(base) ((volatile bit32u *)(base+0x8014))
++#define TX_DMA_STATE_WORD_5(base) (*pTX_DMA_STATE_WORD_5(base))
++#define pTX_DMA_STATE_WORD_6(base) ((volatile bit32u *)(base+0x8018))
++#define TX_DMA_STATE_WORD_6(base) (*pTX_DMA_STATE_WORD_6(base))
++#define pTX_DMA_STATE_WORD_7(base) ((volatile bit32u *)(base+0x801C))
++#define TX_DMA_STATE_WORD_7(base) (*pTX_DMA_STATE_WORD_7(base))
++#define pTX_DMA_STATE_WORD_8(base) ((volatile bit32u *)(base+0x8020))
++#define TX_DMA_STATE_WORD_8(base) (*pTX_DMA_STATE_WORD_8(base))
++
++/* Rx DMA State RAM */
++#define pRX_DMA_STATE_WORD_0(base) ((volatile bit32u *)(base+0x8024))
++#define RX_DMA_STATE_WORD_0(base) (*pRX_DMA_STATE_WORD_0(base))
++#define pRX_DMA_STATE_WORD_1(base) ((volatile bit32u *)(base+0x8028))
++#define RX_DMA_STATE_WORD_1(base) (*pRX_DMA_STATE_WORD_1(base))
++#define pRX_DMA_STATE_WORD_2(base) ((volatile bit32u *)(base+0x802C))
++#define RX_DMA_STATE_WORD_2(base) (*pRX_DMA_STATE_WORD_2(base))
++#define pRX_DMA_STATE_WORD_3(base) ((volatile bit32u *)(base+0x8030))
++#define RX_DMA_STATE_WORD_3(base) (*pRX_DMA_STATE_WORD_3(base))
++#define pRX_DMA_STATE_WORD_4(base) ((volatile bit32u *)(base+0x8034))
++#define RX_DMA_STATE_WORD_4(base) (*pRX_DMA_STATE_WORD_4(base))
++#define pRX_DMA_STATE_WORD_5(base) ((volatile bit32u *)(base+0x8038))
++#define RX_DMA_STATE_WORD_5(base) (*pRX_DMA_STATE_WORD_5(base))
++#define pRX_DMA_STATE_WORD_6(base) ((volatile bit32u *)(base+0x803C))
++#define RX_DMA_STATE_WORD_6(base) (*pRX_DMA_STATE_WORD_6(base))
++
++/* Tx CPPI Completion Pointers */
++#define pTXH_CPPI_COMP_PTR(base) ((volatile bit32u *)(base+0x8040))
++#define TXH_CPPI_COMP_PTR(base) (*pTXH_CPPI_COMP_PTR(base))
++#define pTXL_CPPI_COMP_PTR(base) ((volatile bit32u *)(base+0x8044))
++#define TXL_CPPI_COMP_PTR(base) (*pTXL_CPPI_COMP_PTR(base))
++
++/* Rx CPPI Completion Pointer */
++#define pRX_CPPI_COMP_PTR(base) ((volatile bit32u *)(base+0x8048))
++#define RX_CPPI_COMP_PTR(base) (*pRX_CPPI_COMP_PTR(base))
++
++/* Tx PDSP Defines */
++#define NUM_PDSP_AAL5_STATE_WORDS 24
++#define NUM_PDSP_AAL2_STATE_WORDS 20
++
++/* PDSP State RAM Block 0 */
++#define pPDSP_BLOCK_0(base) ((volatile bit32u *)(base+0x8050))
++#define PDSP_BLOCK_0(base) (*pPDSP_BLOCK_0(base))
++
++/* AAL5 Tx PDSP State RAM */
++#define pPDSP_AAL5_TX_STATE_WORD_0(base) ((volatile bit32u *)(base+0x8050))
++#define PDSP_AAL5_TX_STATE_WORD_0(base) (*pPDSP_AAL5_TX_STATE_WORD_0(base))
++
++/* AAL5 Rx PDSP State RAM */
++#define pPDSP_AAL5_RX_STATE_WORD_0(base) ((volatile bit32u *)(base+0x8070))
++#define PDSP_AAL5_RX_STATE_WORD_0(base) (*pPDSP_AAL5_RX_STATE_WORD_0(base))
++
++/* AAL5 Tx VP PDSP State RAM */
++#define pPDSP_AAL5_TX_VP_STATE_WORD_0(base) ((volatile bit32u *)(base+0x8090))
++#define PDSP_AAL5_TX_VP_STATE_WORD_0(base) (*pPDSP_AAL5_TX_VP_STATE_WORD_0(base))
++
++/* AAL5 Rx VP PDSP State RAM */
++#define pPDSP_AAL5_RX_VP_STATE_WORD_0(base) ((volatile bit32u *)(base+0x80A0))
++#define PDSP_AAL5_RX_VP_STATE_WORD_0(base) (*pPDSP_AAL5_RX_VP_STATE_WORD_0(base))
++
++/* AAL2 Tx PDSP State RAM */
++#define pPDSP_AAL2_TX_STATE_WORD_0(base) ((volatile bit32u *)(base+0x80B0))
++#define PDSP_AAL2_TX_STATE_WORD_0(base) (*pPDSP_AAL2_TX_STATE_WORD_0(base))
++
++/* AAL2 Rx PDSP State RAM */
++#define pPDSP_AAL2_RX_STATE_WORD_0(base) ((volatile bit32u *)(base+0x80D0))
++#define PDSP_AAL2_RX_STATE_WORD_0(base) (*pPDSP_AAL2_RX_STATE_WORD_0(base))
++
++/* AAL2 Tx VP PDSP State RAM */
++#define pPDSP_AAL2_TX_VP_STATE_WORD_0(base) ((volatile bit32u *)(base+0x80E0))
++#define PDSP_AAL2_TX_VP_STATE_WORD_0(base) (*pPDSP_AAL2_TX_VP_STATE_WORD_0(base))
++
++/* AAL2 Rx VP PDSP State RAM */
++#define pPDSP_AAL2_RX_VP_STATE_WORD_0(base) ((volatile bit32u *)(base+0x80F0))
++#define PDSP_AAL2_RX_VP_STATE_WORD_0(base) (*pPDSP_AAL2_RX_VP_STATE_WORD_0(base))
++
++/* PDSP OAM Configuration Block */
++#define pOAM_CONFIG_BLOCK_WORD_0(base) ((volatile bit32u *)(base+0x83C0))
++#define OAM_CONFIG_BLOCK_WORD_0(base) (*pOAM_CONFIG_BLOCK_WORD_0(base))
++
++/* PDSP OAM Padding Block */
++#define pOAM_PADDING_BLOCK_WORD_0(base) ((volatile bit32u *)(base+0x84C0))
++#define OAM_PADDING_BLOCK_WORD_0(base) (*pOAM_PADDING_BLOCK_WORD_0(base))
++
++#define NUM_OAM_RATES 11
++
++/* PDSP OAM Timer State RAM */
++#define pOAM_TIMER_STATE_WORD_0(base) ((volatile bit32u *)(base+0x85B0))
++#define OAM_TIMER_STATE_WORD_0(base) (*pOAM_TIMER_STATE_WORD_0(base))
++
++
++/* END OF FILE */
++
++#endif _INC_SAR_REG
+diff -urN linux.old/drivers/atm/sangam_atm/cpswhal_cpaal5.h linux.dev/drivers/atm/sangam_atm/cpswhal_cpaal5.h
+--- linux.old/drivers/atm/sangam_atm/cpswhal_cpaal5.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpswhal_cpaal5.h 2005-08-23 04:46:50.088845064 +0200
+@@ -0,0 +1,629 @@
++/************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE: cphal.h
++ *
++ * DESCRIPTION:
++ * User include file, contains data definitions shared between the CPHAL
++ * and the upper-layer software.
++ *
++ * HISTORY:
++ * Date Modifier Ver Notes
++ * 28Feb02 Greg 1.00 Original
++ * 06Mar02 Greg 1.01 Documentation enhanced
++ * 18Jul02 Greg 1.02 Many updates (OAM additions, general reorg)
++ * 22Nov02 Mick RC2 Additions from Denis' input on Control
++ *
++ * author Greg Guyotte
++ * version 1.02
++ * date 18-Jul-2002
++ *****************************************************************************/
++#ifndef _INC_CPHAL_H
++#define _INC_CPHAL_H
++
++#ifdef _CPHAL_CPMAC
++#include "ec_errors_cpmac.h"
++#endif
++
++#ifdef _CPHAL_AAL5
++#include "ec_errors_cpaal5.h"
++#endif
++
++#ifdef _CPHAL_CPSAR
++#include "ec_errors_cpsar.h"
++#endif
++
++#ifdef _CPHAL_AAL2
++#include "ec_errors_cpaal2.h"
++#endif
++
++#ifndef __ADAM2
++typedef char bit8;
++typedef short bit16;
++typedef int bit32;
++
++typedef unsigned char bit8u;
++typedef unsigned short bit16u;
++typedef unsigned int bit32u;
++
++/*
++typedef char INT8;
++typedef short INT16;
++typedef int INT32;
++typedef unsigned char UINT8;
++typedef unsigned short UINT16;
++typedef unsigned int UINT32;
++*/
++/*typedef unsigned int size_t;*/
++#endif
++
++#ifdef _CPHAL
++
++#ifndef TRUE
++#define TRUE (1==1)
++#endif
++
++#ifndef FALSE
++#define FALSE (1==2)
++#endif
++
++#ifndef NULL
++#define NULL 0
++#endif
++
++#endif
++
++#define VirtToPhys(a) (((int)a)&~0xe0000000)
++#define VirtToVirtNoCache(a) ((void*)((VirtToPhys(a))|0xa0000000))
++#define VirtToVirtCache(a) ((void*)((VirtToPhys(a))|0x80000000))
++#define PhysToVirtNoCache(a) ((void*)(((int)a)|0xa0000000))
++#define PhysToVirtCache(a) ((void*)(((int)a)|0x80000000))
++/*
++#define DataCacheHitInvalidate(a) {__asm__(" cache 17, (%0)" : : "r" (a));}
++#define DataCacheHitWriteback(a) {__asm__(" cache 25, (%0)" : : "r" (a));}
++*/
++
++#define PARTIAL 1 /**< Used in @c Close() and @c ChannelTeardown() */
++#define FULL 2 /**< Used in @c Close() and @c ChannelTeardown() */
++
++/* Channel Teardown Defines */
++#define RX_TEARDOWN 2
++#define TX_TEARDOWN 1
++#define BLOCKING_TEARDOWN 8
++#define FULL_TEARDOWN 4
++#define PARTIAL_TEARDOWN 0
++
++#define MAX_DIR 2
++#define DIRECTION_TX 0
++#define DIRECTION_RX 1
++#define TX_CH 0
++#define RX_CH 1
++#define HAL_ERROR_DEVICE_NOT_FOUND 1
++#define HAL_ERROR_FAILED_MALLOC 2
++#define HAL_ERROR_OSFUNC_SIZE 3
++#define HAL_DEFAULT 0xFFFFFFFF
++#define VALID(val) (val!=HAL_DEFAULT)
++
++/*
++ERROR REPORTING
++
++HAL Module Codes. Each HAL module reporting an error code
++should OR the error code with the respective Module error code
++from the list below.
++*/
++#define EC_AAL5 EC_HAL|EC_DEV_AAL5
++#define EC_AAL2 EC_HAL|EC_DEV_AAL2
++#define EC_CPSAR EC_HAL|EC_DEV_CPSAR
++#define EC_CPMAC EC_HAL|EC_DEV_CPMAC
++#define EC_VDMA EC_HAL|EC_DEV_VDMA
++#define EC_VLYNQ EC_HAL|EC_DEV_VLYNQ
++#define EC_CPPI EC_HAL|EC_DEV_CPPI
++
++/*
++HAL Function Codes. Each HAL module reporting an error code
++should OR the error code with one of the function codes from
++the list below.
++*/
++#define EC_FUNC_HAL_INIT EC_FUNC(1)
++#define EC_FUNC_CHSETUP EC_FUNC(2)
++#define EC_FUNC_CHTEARDOWN EC_FUNC(3)
++#define EC_FUNC_RXRETURN EC_FUNC(4)
++#define EC_FUNC_SEND EC_FUNC(5)
++#define EC_FUNC_RXINT EC_FUNC(6)
++#define EC_FUNC_TXINT EC_FUNC(7)
++#define EC_FUNC_AAL2_VDMA EC_FUNC(8)
++#define EC_FUNC_OPTIONS EC_FUNC(9)
++#define EC_FUNC_PROBE EC_FUNC(10)
++#define EC_FUNC_OPEN EC_FUNC(11)
++#define EC_FUNC_CONTROL EC_FUNC(12)
++#define EC_FUNC_DEVICE_INT EC_FUNC(13)
++#define EC_FUNC_STATUS EC_FUNC(14)
++#define EC_FUNC_TICK EC_FUNC(15)
++#define EC_FUNC_CLOSE EC_FUNC(16)
++#define EC_FUNC_SHUTDOWN EC_FUNC(17)
++#define EC_FUNC_DEVICE_INT_ALT EC_FUNC(18) /* +GSG 030306 */
++
++/*
++HAL Error Codes. The list below defines every type of error
++used in all HAL modules. DO NOT CHANGE THESE VALUES! Add new
++values in integer order to the bottom of the list.
++*/
++#define EC_VAL_PDSP_LOAD_FAIL EC_ERR(0x01)|EC_CRITICAL
++#define EC_VAL_FIRMWARE_TOO_LARGE EC_ERR(0x02)|EC_CRITICAL
++#define EC_VAL_DEVICE_NOT_FOUND EC_ERR(0x03)|EC_CRITICAL
++#define EC_VAL_BASE_ADDR_NOT_FOUND EC_ERR(0x04)|EC_CRITICAL
++#define EC_VAL_RESET_BIT_NOT_FOUND EC_ERR(0x05)|EC_CRITICAL
++#define EC_VAL_CH_INFO_NOT_FOUND EC_ERR(0x06)
++#define EC_VAL_RX_STATE_RAM_NOT_CLEARED EC_ERR(0x07)|EC_CRITICAL
++#define EC_VAL_TX_STATE_RAM_NOT_CLEARED EC_ERR(0x08)|EC_CRITICAL
++#define EC_VAL_MALLOC_DEV_FAILED EC_ERR(0x09)
++#define EC_VAL_OS_VERSION_NOT_SUPPORTED EC_ERR(0x0A)|EC_CRITICAL
++#define EC_VAL_CPSAR_VERSION_NOT_SUPPORTED EC_ERR(0x0B)|EC_CRITICAL
++#define EC_VAL_NULL_CPSAR_DEV EC_ERR(0x0C)|EC_CRITICAL
++
++#define EC_VAL_LUT_NOT_READY EC_ERR(0x0D)
++#define EC_VAL_INVALID_CH EC_ERR(0x0E)
++#define EC_VAL_NULL_CH_STRUCT EC_ERR(0x0F)
++#define EC_VAL_RX_TEARDOWN_ALREADY_PEND EC_ERR(0x10)
++#define EC_VAL_TX_TEARDOWN_ALREADY_PEND EC_ERR(0x11)
++#define EC_VAL_RX_CH_ALREADY_TORNDOWN EC_ERR(0x12)
++#define EC_VAL_TX_CH_ALREADY_TORNDOWN EC_ERR(0x13)
++#define EC_VAL_TX_TEARDOWN_TIMEOUT EC_ERR(0x14)
++#define EC_VAL_RX_TEARDOWN_TIMEOUT EC_ERR(0x15)
++#define EC_VAL_CH_ALREADY_TORNDOWN EC_ERR(0x16)
++#define EC_VAL_VC_SETUP_NOT_READY EC_ERR(0x17)
++#define EC_VAL_VC_TEARDOWN_NOT_READY EC_ERR(0x18)
++#define EC_VAL_INVALID_VC EC_ERR(0x19)
++#define EC_VAL_INVALID_LC EC_ERR(0x20)
++#define EC_VAL_INVALID_VDMA_CH EC_ERR(0x21)
++#define EC_VAL_INVALID_CID EC_ERR(0x22)
++#define EC_VAL_INVALID_UUI EC_ERR(0x23)
++#define EC_VAL_INVALID_UUI_DISCARD EC_ERR(0x24)
++#define EC_VAL_CH_ALREADY_OPEN EC_ERR(0x25)
++
++#define EC_VAL_RCB_MALLOC_FAILED EC_ERR(0x26)
++#define EC_VAL_RX_BUFFER_MALLOC_FAILED EC_ERR(0x27)
++#define EC_VAL_OUT_OF_TCBS EC_ERR(0x28)
++#define EC_VAL_NO_TCBS EC_ERR(0x29)
++#define EC_VAL_NULL_RCB EC_ERR(0x30)|EC_CRITICAL
++#define EC_VAL_SOP_ERROR EC_ERR(0x31)|EC_CRITICAL
++#define EC_VAL_EOP_ERROR EC_ERR(0x32)|EC_CRITICAL
++#define EC_VAL_NULL_TCB EC_ERR(0x33)|EC_CRITICAL
++#define EC_VAL_CORRUPT_RCB_CHAIN EC_ERR(0x34)|EC_CRITICAL
++#define EC_VAL_TCB_MALLOC_FAILED EC_ERR(0x35)
++
++#define EC_VAL_DISABLE_POLLING_FAILED EC_ERR(0x36)
++#define EC_VAL_KEY_NOT_FOUND EC_ERR(0x37)
++#define EC_VAL_MALLOC_FAILED EC_ERR(0x38)
++#define EC_VAL_RESET_BASE_NOT_FOUND EC_ERR(0x39)|EC_CRITICAL
++#define EC_VAL_INVALID_STATE EC_ERR(0x40)
++#define EC_VAL_NO_TXH_WORK_TO_DO EC_ERR(0x41)
++#define EC_VAL_NO_TXL_WORK_TO_DO EC_ERR(0x42)
++#define EC_VAL_NO_RX_WORK_TO_DO EC_ERR(0x43)
++#define EC_VAL_NOT_LINKED EC_ERR(0x44)
++#define EC_VAL_INTERRUPT_NOT_FOUND EC_ERR(0x45)
++#define EC_VAL_OFFSET_NOT_FOUND EC_ERR(0x46)
++#define EC_VAL_MODULE_ALREADY_CLOSED EC_ERR(0x47)
++#define EC_VAL_MODULE_ALREADY_SHUTDOWN EC_ERR(0x48)
++#define EC_VAL_ACTION_NOT_FOUND EC_ERR(0x49)
++#define EC_VAL_RX_CH_ALREADY_SETUP EC_ERR(0x50)
++#define EC_VAL_TX_CH_ALREADY_SETUP EC_ERR(0x51)
++#define EC_VAL_RX_CH_ALREADY_OPEN EC_ERR(0x52)
++#define EC_VAL_TX_CH_ALREADY_OPEN EC_ERR(0x53)
++#define EC_VAL_CH_ALREADY_SETUP EC_ERR(0x54)
++#define EC_VAL_RCB_NEEDS_BUFFER EC_ERR(0x55) /* +GSG 030410 */
++#define EC_VAL_RCB_DROPPED EC_ERR(0x56) /* +GSG 030410 */
++#define EC_VAL_INVALID_VALUE EC_ERR(0x57)
++
++/**
++@defgroup shared_data Shared Data Structures
++
++The data structures documented here are shared by all modules.
++*/
++
++/**
++ * @ingroup shared_data
++ * This is the fragment list structure. Each fragment list entry contains a
++ * length and a data buffer.
++ */
++typedef struct
++ {
++ bit32u len; /**< Length of the fragment in bytes (lower 16 bits are valid). For SOP, upper 16 bits is the buffer offset. */
++ void *data; /**< Pointer to fragment data. */
++ void *OsInfo; /**< Pointer to OS defined data. */
++ }FRAGLIST;
++
++#if defined (_CPHAL_CPMAC)
++#define CB_PASSCRC_BIT (1<<26)
++
++/* CPMAC CPHAL STATUS */
++#define CPMAC_STATUS_LINK (1 << 0)
++#define CPMAC_STATUS_LINK_DUPLEX (1 << 1) /* 0 - HD, 1 - FD */
++#define CPMAC_STATUS_LINK_SPEED (1 << 2) /* 0 - 10, 1 - 100 */
++
++/* ADAPTER CHECK Codes */
++
++#define CPMAC_STATUS_ADAPTER_CHECK (1 << 7)
++#define CPMAC_STATUS_HOST_ERR_DIRECTION (1 << 8)
++#define CPMAC_STATUS_HOST_ERR_CODE (0xF << 9)
++#define CPMAC_STATUS_HOST_ERR_CH (0x7 << 13)
++
++#define _CPMDIO_DISABLE (1 << 0)
++#define _CPMDIO_HD (1 << 1)
++#define _CPMDIO_FD (1 << 2)
++#define _CPMDIO_10 (1 << 3)
++#define _CPMDIO_100 (1 << 4)
++#define _CPMDIO_NEG_OFF (1 << 5)
++#define _CPMDIO_LOOPBK (1 << 16)
++#define _CPMDIO_NOPHY (1 << 20)
++#endif
++
++/**
++ * @ingroup shared_data
++ * Channel specific configuration information. This structure should be
++ * populated by upper-layer software prior to calling @c ChannelSetup(). Any
++ * configuration item that can be changed on a per channel basis should
++ * be represented here. Each module may define this structure with additional
++ * module-specific members.
++ */
++typedef struct
++ {
++ int Channel; /**< Channel number. */
++ int Direction; /**< DIRECTION_RX(1) or DIRECTION_TX(0). */
++ OS_SETUP *OsSetup; /**< OS defined information associated with this channel. */
++
++#if defined(_CPHAL_AAL5) || defined (_CPHAL_CPSAR) || defined (_CPHAL_CPMAC)
++ int RxBufSize; /**< Size (in bytes) for each Rx buffer.*/
++ int RxBufferOffset; /**< Number of bytes to offset rx data from start of buffer (must be less than buffer size). */
++ int RxNumBuffers; /**< The number of Rx buffer descriptors to allocate for Ch. */
++ int RxServiceMax; /**< Maximum number of packets to service at one time. */
++
++ int TxNumBuffers; /**< The number of Tx buffer descriptors to allocate for Ch. */
++ int TxNumQueues; /**< Number of Tx queues for this channel (1-2). Choosing 2 enables a low priority SAR queue. */
++ int TxServiceMax; /**< Maximum number of packets to service at one time. */
++#endif
++
++#if defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
++ int CpcsUU; /**< The 2-byte CPCS UU and CPI information. */
++ int Gfc; /**< Generic Flow Control. */
++ int Clp; /**< Cell Loss Priority. */
++ int Pti; /**< Payload Type Indication. */
++#endif
++
++#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
++ int DaMask; /**< Specifies whether credit issuance is paused when Tx data not available. */
++ int Priority; /**< Priority bin this channel will be scheduled within. */
++ int PktType; /**< 0=AAL5,1=Null AAL,2=OAM,3=Transparent,4=AAL2. */
++ int Vci; /**< Virtual Channel Identifier. */
++ int Vpi; /**< Virtual Path Identifier. */
++ int FwdUnkVc; /**< Enables forwarding of unknown VCI/VPI cells to host. 1=enable, 0=disable. */
++
++ /* Tx VC State */
++ int TxVc_CellRate; /**< Tx rate, set as clock ticks between transmissions (SCR for VBR, CBR for CBR). */
++ int TxVc_QosType; /**< 0=CBR,1=VBR,2=UBR,3=UBRmcr. */
++ int TxVc_Mbs; /**< Min Burst Size in cells.*/
++ int TxVc_Pcr; /**< Peak Cell Rate for VBR in clock ticks between transmissions. */
++
++ bit32 TxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Tx Ch (must be big endian with 0 PTI). */
++ int TxVc_OamTc; /**< TC Path to transmit OAM cells for TX connection (0,1). */
++ int TxVc_VpOffset; /**< Offset to the OAM VP state table. */
++ /* Rx VC State */
++ int RxVc_OamCh; /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
++ int RxVc_OamToHost; /**< 0=do not pass, 1=pass. */
++ bit32 RxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx conn (must be big endian with 0 PTI). */
++ int RxVc_OamTc; /**< TC Path to transmit OAM cells for RX connection (0,1). */
++ int RxVc_VpOffset; /**< Offset to the OAM VP state table. */
++ /* Tx VP State */
++ int TxVp_OamTc; /**< TC Path to transmit OAM cells for TX VP connection (0,1). */
++ bit32 TxVp_AtmHeader; /**< ATM Header placed on firmware gen'd VP OAM cells for this Tx VP conn (must be big endian with 0 VCI). */
++ /* Rx VP State */
++ int RxVp_OamCh; /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
++ int RxVp_OamToHost; /**< 0=do not pass, 1=pass. */
++ bit32 RxVp_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx VP conn (must be big endian with 0 VCI). */
++ int RxVp_OamTc; /**< TC Path to transmit OAM cells for RX VP connection (0,1). */
++ int RxVp_OamVcList; /**< Indicates all VC channels associated with this VP channel (one-hot encoded). */
++#endif
++
++
++#ifdef _CPHAL_VDMAVT
++ bit32u RemFifoAddr; /* Mirror mode only. */
++ bit32u FifoAddr;
++ bit32 PollInt;
++ bit32 FifoSize;
++ int Ready;
++#endif
++
++ }CHANNEL_INFO;
++
++/*
++ * This structure contains each statistic value gathered by the CPHAL.
++ * Applications may access statistics data by using the @c StatsGet() routine.
++ */
++/* STATS */
++#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
++typedef struct
++ {
++ bit32u CrcErrors[16];
++ bit32u LenErrors[16];
++ bit32u DmaLenErrors[16];
++ bit32u AbortErrors[16];
++ bit32u StarvErrors[16];
++ bit32u TxMisQCnt[16][2];
++ bit32u RxMisQCnt[16];
++ bit32u RxEOQCnt[16];
++ bit32u TxEOQCnt[16][2];
++ bit32u RxPacketsServiced[16];
++ bit32u TxPacketsServiced[16][2];
++ bit32u RxMaxServiced;
++ bit32u TxMaxServiced[16][2];
++ bit32u RxTotal;
++ bit32u TxTotal;
++ } STAT_INFO;
++#endif
++
++/*
++ * VDMA Channel specific configuration information
++ */
++#ifdef _CPHAL_AAL2
++typedef struct
++ {
++ int Ch; /**< Channel Number */
++ int RemoteEndian; /**< Endianness of remote VDMA-VT device */
++ int CpsSwap; /**< When 0, octet 0 in CPS pkt located in LS byte of 16-bit word sent to rem VDMA device. When 1, in MS byte. */
++ }VdmaChInfo;
++#endif
++
++#ifndef _CPHAL
++ typedef void HAL_DEVICE;
++ typedef void HAL_PRIVATE;
++ typedef void HAL_RCB;
++ typedef void HAL_RECEIVEINFO;
++#endif
++
++/**
++ * @ingroup shared_data
++ * The HAL_FUNCTIONS struct defines the function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to xxxInitModule().
++ */
++typedef struct
++ {
++ int (*ChannelSetup) (HAL_DEVICE *HalDev, CHANNEL_INFO *Channel, OS_SETUP *OsSetup);
++ int (*ChannelTeardown) (HAL_DEVICE *HalDev, int Channel, int Mode);
++ int (*Close) (HAL_DEVICE *HalDev, int Mode);
++ int (*Control) (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
++ int (*Init) (HAL_DEVICE *HalDev);
++ int (*Open) (HAL_DEVICE *HalDev);
++ int (*PacketProcessEnd) (HAL_DEVICE *HalDev);
++ int (*Probe) (HAL_DEVICE *HalDev);
++ int (*RxReturn) (HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
++ int (*Send) (HAL_DEVICE *HalDev, FRAGLIST *FragList, int FragCount, int PacketSize, OS_SENDINFO *OsSendInfo, bit32u Mode);
++ int (*Shutdown) (HAL_DEVICE *HalDev);
++ int (*Tick) (HAL_DEVICE *HalDev);
++
++#ifdef _CPHAL_AAL5
++ int (*Kick) (HAL_DEVICE *HalDev, int Queue);
++ void (*OamFuncConfig) (HAL_DEVICE *HalDev, unsigned int OamConfig);
++ void (*OamLoopbackConfig) (HAL_DEVICE *HalDev, unsigned int OamConfig, unsigned int *LLID, unsigned int CorrelationTag);
++ volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
++ STAT_INFO* (*StatsGetOld)(HAL_DEVICE *HalDev);
++#endif
++ } HAL_FUNCTIONS;
++
++/**
++ * @ingroup shared_data
++ * The OS_FUNCTIONS struct defines the function pointers for all upper layer
++ * functions accessible to the CPHAL. The upper layer software is responsible
++ * for providing the correct OS-specific implementations for the following
++ * functions. It is populated by calling InitModule() (done by the CPHAL in
++ * xxxInitModule().
++ */
++typedef struct
++ {
++ int (*Control)(OS_DEVICE *OsDev, const char *Key, const char *Action, void *Value);
++ void (*CriticalOn)(void);
++ void (*CriticalOff)(void);
++ void (*DataCacheHitInvalidate)(void *MemPtr, int Size);
++ void (*DataCacheHitWriteback)(void *MemPtr, int Size);
++ int (*DeviceFindInfo)(int Inst, const char *DeviceName, void *DeviceInfo);
++ int (*DeviceFindParmUint)(void *DeviceInfo, const char *Parm, bit32u *Value);
++ int (*DeviceFindParmValue)(void *DeviceInfo, const char *Parm, void *Value);
++ void (*Free)(void *MemPtr);
++ void (*FreeRxBuffer)(OS_RECEIVEINFO *OsReceiveInfo, void *MemPtr);
++ void (*FreeDev)(void *MemPtr);
++ void (*FreeDmaXfer)(void *MemPtr);
++ void (*IsrRegister)(OS_DEVICE *OsDev, int (*halISR)(HAL_DEVICE*, int*), int InterruptBit);
++ void (*IsrUnRegister)(OS_DEVICE *OsDev, int InterruptBit);
++ void* (*Malloc)(bit32u size);
++ void* (*MallocDev)(bit32u Size);
++ void* (*MallocDmaXfer)(bit32u size, void *MemBase, bit32u MemRange);
++ void* (*MallocRxBuffer)(bit32u size, void *MemBase, bit32u MemRange,
++ OS_SETUP *OsSetup, HAL_RECEIVEINFO *HalReceiveInfo,
++ OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev);
++ void* (*Memset)(void *Dest, int C, bit32u N);
++ int (*Printf)(const char *Format, ...);
++ int (*Receive)(OS_DEVICE *OsDev,FRAGLIST *FragList,bit32u FragCount,
++ bit32u PacketSize,HAL_RECEIVEINFO *HalReceiveInfo, bit32u Mode);
++ int (*SendComplete)(OS_SENDINFO *OsSendInfo);
++ int (*Sprintf)(char *S, const char *Format, ...);
++ int (*Strcmpi)(const char *Str1, const char *Str2);
++ unsigned int (*Strlen)(const char *S);
++ char* (*Strstr)(const char *S1, const char *S2);
++ unsigned long (*Strtoul)(const char *Str, char **Endptr, int Base);
++ void (*TeardownComplete)(OS_DEVICE *OsDev, int Ch, int Direction);
++ } OS_FUNCTIONS;
++
++/************** MODULE SPECIFIC STUFF BELOW **************/
++
++#ifdef _CPHAL_CPMAC
++
++/*
++int halCpmacInitModule(HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc, int (*osBridgeInitModule)(OS_FUNCTIONS *), void* (*osMallocDev) (bit32u), int *Size, int inst);
++*/
++
++int halCpmacInitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ HAL_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++#ifdef _CPHAL_AAL5
++/*
++ * @ingroup shared_data
++ * The AAL5_FUNCTIONS struct defines the AAL5 function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to cphalInitModule().
++ */
++/*
++typedef struct
++ {
++ int (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
++ int (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
++ int (*Close)(HAL_DEVICE *HalDev, int Mode);
++ int (*Init)(HAL_DEVICE *HalDev);
++ int (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
++ int (*Open)(HAL_DEVICE *HalDev);
++ int (*InfoGet)(HAL_DEVICE *HalDev, int Key, void *Value);
++ int (*Probe)(HAL_DEVICE *HalDev);
++ int (*RxReturn)(HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
++ int (*Send)(HAL_DEVICE *HalDev,FRAGLIST *FragList,int FragCount,
++ int PacketSize,OS_SENDINFO *OsSendInfo,int Ch, int Queue,
++ bit32u Mode);
++ int (*StatsClear)(HAL_DEVICE *HalDev);
++ STAT_INFO* (*StatsGet)(HAL_DEVICE *HalDev);
++ int (*Status)(HAL_DEVICE *HalDev);
++ void (*Tick)(HAL_DEVICE *HalDev);
++ int (*Kick)(HAL_DEVICE *HalDev, int Queue);
++ volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
++ } AAL5_FUNCTIONS;
++*/
++
++int cpaal5InitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ HAL_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++#ifdef _CPHAL_AAL2
++/**
++ * @ingroup shared_data
++ * The AAL2_FUNCTIONS struct defines the AAL2 function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to cphalInitModule().
++ */
++typedef struct
++ {
++ int (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
++ int (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
++ int (*Close)(HAL_DEVICE *HalDev, int Mode);
++ int (*Init)(HAL_DEVICE *HalDev);
++ int (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
++ int (*Open)(HAL_DEVICE *HalDev);
++ int (*OptionsGet)(HAL_DEVICE *HalDev, char *Key, bit32u *Value);
++ int (*Probe)(HAL_DEVICE *HalDev);
++
++ int (*StatsClear)(HAL_DEVICE *HalDev);
++ STAT_INFO* (*StatsGet)(HAL_DEVICE *HalDev);
++ int (*Status)(HAL_DEVICE *HalDev);
++ void (*Tick)(HAL_DEVICE *HalDev);
++ int (*Aal2UuiMappingSetup)(HAL_DEVICE *HalDev, int VC, int UUI,
++ int VdmaCh, int UUIDiscard);
++ int (*Aal2RxMappingSetup)(HAL_DEVICE *HalDev, int VC, int CID,
++ int LC);
++ int (*Aal2TxMappingSetup)(HAL_DEVICE *HalDev, int VC, int LC, int VdmaCh);
++ int (*Aal2VdmaChSetup)(HAL_DEVICE *HalDev, bit32u RemVdmaVtAddr,
++ VdmaChInfo *VdmaCh);
++ volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
++ int (*Aal2ModeChange)(HAL_DEVICE *HalDev, int Vc, int RxCrossMode,
++ int RxMultiMode, int TxMultiMode, int SchedMode,
++ int TcCh);
++ void (*Aal2VdmaEnable)(HAL_DEVICE *HalDev, int Ch);
++ int (*Aal2VdmaDisable)(HAL_DEVICE *HalDev, int Ch);
++ } AAL2_FUNCTIONS;
++
++int cpaal2InitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ AAL2_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++#ifdef _CPHAL_VDMAVT
++/**
++ * @ingroup shared_data
++ * The VDMA_FUNCTIONS struct defines the HAL function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to InitModule().
++ *
++ * Note that this list is still under definition.
++ */
++typedef struct
++ {
++ bit32 (*Init)( HAL_DEVICE *VdmaVtDev);
++ /* bit32 (*SetupTxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
++ bit32u Addr, bit32u Size, bit32u PollInt);
++ bit32 (*SetupRxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
++ bit32u Addr, bit32u Size, bit32u PollInt); */
++ bit32 (*Tx)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*Rx)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*SetRemoteChannel)(HAL_DEVICE *VdmaVtDev, bit32u RemAddr,
++ bit32u RemDevID);
++ bit32 (*ClearRxInt)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*ClearTxInt)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*Open)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*Close)(HAL_DEVICE *VdmaVtDev);
++ int (*Control) (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
++ int (*ChannelSetup)(HAL_DEVICE *VdmaVtDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
++ int (*ChannelTeardown)(HAL_DEVICE *VdmaVtDev, int Ch, int Mode);
++ int (*Send)(HAL_DEVICE *VdmaVtDev,FRAGLIST *FragList,int FragCount,
++ int PacketSize,OS_SENDINFO *OsSendInfo,bit32u Mode);
++ } VDMA_FUNCTIONS;
++
++int VdmaInitModule(HAL_DEVICE **VdmaVt,
++ OS_DEVICE *OsDev,
++ VDMA_FUNCTIONS **VdmaVtFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++/*
++extern int cphalInitModule(MODULE_TYPE ModuleType, HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc,
++ int (*osInitModule)(OS_FUNCTIONS *), void* (*osMallocDev)(bit32u),
++ int *Size, int Inst);
++*/
++
++
++#ifdef _CPHAL_AAL5
++extern const char hcSarFrequency[];
++#endif
++
++#ifdef _CPHAL_CPMAC
++/* following will be common, once 'utl' added */
++extern const char hcClear[];
++extern const char hcGet[];
++extern const char hcSet[];
++extern const char hcTick[];
++
++extern const char hcCpuFrequency[];
++extern const char hcCpmacFrequency[];
++extern const char hcMdioBusFrequency[];
++extern const char hcMdioClockFrequency[];
++extern const char hcCpmacBase[];
++extern const char hcPhyNum[];
++extern const char hcSize[];
++extern const char hcCpmacSize[];
++extern const char hcPhyAccess[];
++#endif
++
++#endif /* end of _INC_ */
+diff -urN linux.old/drivers/atm/sangam_atm/cpswhal_cpsar.h linux.dev/drivers/atm/sangam_atm/cpswhal_cpsar.h
+--- linux.old/drivers/atm/sangam_atm/cpswhal_cpsar.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/cpswhal_cpsar.h 2005-08-23 04:46:50.089844912 +0200
+@@ -0,0 +1,629 @@
++/************************************************************************
++ * TNETDxxxx Software Support
++ * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
++ *
++ * FILE: cphal.h
++ *
++ * DESCRIPTION:
++ * User include file, contains data definitions shared between the CPHAL
++ * and the upper-layer software.
++ *
++ * HISTORY:
++ * Date Modifier Ver Notes
++ * 28Feb02 Greg 1.00 Original
++ * 06Mar02 Greg 1.01 Documentation enhanced
++ * 18Jul02 Greg 1.02 Many updates (OAM additions, general reorg)
++ * 22Nov02 Mick RC2 Additions from Denis' input on Control
++ *
++ * author Greg Guyotte
++ * version 1.02
++ * date 18-Jul-2002
++ *****************************************************************************/
++#ifndef _INC_CPHAL_H
++#define _INC_CPHAL_H
++
++#ifdef _CPHAL_CPMAC
++#include "ec_errors_cpmac.h"
++#endif
++
++#ifdef _CPHAL_AAL5
++#include "ec_errors_cpaal5.h"
++#endif
++
++#ifdef _CPHAL_CPSAR
++#include "ec_errors_cpsar.h"
++#endif
++
++#ifdef _CPHAL_AAL2
++#include "ec_errors_cpaal2.h"
++#endif
++
++#ifndef __ADAM2
++typedef char bit8;
++typedef short bit16;
++typedef int bit32;
++
++typedef unsigned char bit8u;
++typedef unsigned short bit16u;
++typedef unsigned int bit32u;
++
++/*
++typedef char INT8;
++typedef short INT16;
++typedef int INT32;
++typedef unsigned char UINT8;
++typedef unsigned short UINT16;
++typedef unsigned int UINT32;
++*/
++/*typedef unsigned int size_t;*/
++#endif
++
++#ifdef _CPHAL
++
++#ifndef TRUE
++#define TRUE (1==1)
++#endif
++
++#ifndef FALSE
++#define FALSE (1==2)
++#endif
++
++#ifndef NULL
++#define NULL 0
++#endif
++
++#endif
++
++#define VirtToPhys(a) (((int)a)&~0xe0000000)
++#define VirtToVirtNoCache(a) ((void*)((VirtToPhys(a))|0xa0000000))
++#define VirtToVirtCache(a) ((void*)((VirtToPhys(a))|0x80000000))
++#define PhysToVirtNoCache(a) ((void*)(((int)a)|0xa0000000))
++#define PhysToVirtCache(a) ((void*)(((int)a)|0x80000000))
++/*
++#define DataCacheHitInvalidate(a) {__asm__(" cache 17, (%0)" : : "r" (a));}
++#define DataCacheHitWriteback(a) {__asm__(" cache 25, (%0)" : : "r" (a));}
++*/
++
++#define PARTIAL 1 /**< Used in @c Close() and @c ChannelTeardown() */
++#define FULL 2 /**< Used in @c Close() and @c ChannelTeardown() */
++
++/* Channel Teardown Defines */
++#define RX_TEARDOWN 2
++#define TX_TEARDOWN 1
++#define BLOCKING_TEARDOWN 8
++#define FULL_TEARDOWN 4
++#define PARTIAL_TEARDOWN 0
++
++#define MAX_DIR 2
++#define DIRECTION_TX 0
++#define DIRECTION_RX 1
++#define TX_CH 0
++#define RX_CH 1
++#define HAL_ERROR_DEVICE_NOT_FOUND 1
++#define HAL_ERROR_FAILED_MALLOC 2
++#define HAL_ERROR_OSFUNC_SIZE 3
++#define HAL_DEFAULT 0xFFFFFFFF
++#define VALID(val) (val!=HAL_DEFAULT)
++
++/*
++ERROR REPORTING
++
++HAL Module Codes. Each HAL module reporting an error code
++should OR the error code with the respective Module error code
++from the list below.
++*/
++#define EC_AAL5 EC_HAL|EC_DEV_AAL5
++#define EC_AAL2 EC_HAL|EC_DEV_AAL2
++#define EC_CPSAR EC_HAL|EC_DEV_CPSAR
++#define EC_CPMAC EC_HAL|EC_DEV_CPMAC
++#define EC_VDMA EC_HAL|EC_DEV_VDMA
++#define EC_VLYNQ EC_HAL|EC_DEV_VLYNQ
++#define EC_CPPI EC_HAL|EC_DEV_CPPI
++
++/*
++HAL Function Codes. Each HAL module reporting an error code
++should OR the error code with one of the function codes from
++the list below.
++*/
++#define EC_FUNC_HAL_INIT EC_FUNC(1)
++#define EC_FUNC_CHSETUP EC_FUNC(2)
++#define EC_FUNC_CHTEARDOWN EC_FUNC(3)
++#define EC_FUNC_RXRETURN EC_FUNC(4)
++#define EC_FUNC_SEND EC_FUNC(5)
++#define EC_FUNC_RXINT EC_FUNC(6)
++#define EC_FUNC_TXINT EC_FUNC(7)
++#define EC_FUNC_AAL2_VDMA EC_FUNC(8)
++#define EC_FUNC_OPTIONS EC_FUNC(9)
++#define EC_FUNC_PROBE EC_FUNC(10)
++#define EC_FUNC_OPEN EC_FUNC(11)
++#define EC_FUNC_CONTROL EC_FUNC(12)
++#define EC_FUNC_DEVICE_INT EC_FUNC(13)
++#define EC_FUNC_STATUS EC_FUNC(14)
++#define EC_FUNC_TICK EC_FUNC(15)
++#define EC_FUNC_CLOSE EC_FUNC(16)
++#define EC_FUNC_SHUTDOWN EC_FUNC(17)
++#define EC_FUNC_DEVICE_INT_ALT EC_FUNC(18) /* +GSG 030306 */
++
++/*
++HAL Error Codes. The list below defines every type of error
++used in all HAL modules. DO NOT CHANGE THESE VALUES! Add new
++values in integer order to the bottom of the list.
++*/
++#define EC_VAL_PDSP_LOAD_FAIL EC_ERR(0x01)|EC_CRITICAL
++#define EC_VAL_FIRMWARE_TOO_LARGE EC_ERR(0x02)|EC_CRITICAL
++#define EC_VAL_DEVICE_NOT_FOUND EC_ERR(0x03)|EC_CRITICAL
++#define EC_VAL_BASE_ADDR_NOT_FOUND EC_ERR(0x04)|EC_CRITICAL
++#define EC_VAL_RESET_BIT_NOT_FOUND EC_ERR(0x05)|EC_CRITICAL
++#define EC_VAL_CH_INFO_NOT_FOUND EC_ERR(0x06)
++#define EC_VAL_RX_STATE_RAM_NOT_CLEARED EC_ERR(0x07)|EC_CRITICAL
++#define EC_VAL_TX_STATE_RAM_NOT_CLEARED EC_ERR(0x08)|EC_CRITICAL
++#define EC_VAL_MALLOC_DEV_FAILED EC_ERR(0x09)
++#define EC_VAL_OS_VERSION_NOT_SUPPORTED EC_ERR(0x0A)|EC_CRITICAL
++#define EC_VAL_CPSAR_VERSION_NOT_SUPPORTED EC_ERR(0x0B)|EC_CRITICAL
++#define EC_VAL_NULL_CPSAR_DEV EC_ERR(0x0C)|EC_CRITICAL
++
++#define EC_VAL_LUT_NOT_READY EC_ERR(0x0D)
++#define EC_VAL_INVALID_CH EC_ERR(0x0E)
++#define EC_VAL_NULL_CH_STRUCT EC_ERR(0x0F)
++#define EC_VAL_RX_TEARDOWN_ALREADY_PEND EC_ERR(0x10)
++#define EC_VAL_TX_TEARDOWN_ALREADY_PEND EC_ERR(0x11)
++#define EC_VAL_RX_CH_ALREADY_TORNDOWN EC_ERR(0x12)
++#define EC_VAL_TX_CH_ALREADY_TORNDOWN EC_ERR(0x13)
++#define EC_VAL_TX_TEARDOWN_TIMEOUT EC_ERR(0x14)
++#define EC_VAL_RX_TEARDOWN_TIMEOUT EC_ERR(0x15)
++#define EC_VAL_CH_ALREADY_TORNDOWN EC_ERR(0x16)
++#define EC_VAL_VC_SETUP_NOT_READY EC_ERR(0x17)
++#define EC_VAL_VC_TEARDOWN_NOT_READY EC_ERR(0x18)
++#define EC_VAL_INVALID_VC EC_ERR(0x19)
++#define EC_VAL_INVALID_LC EC_ERR(0x20)
++#define EC_VAL_INVALID_VDMA_CH EC_ERR(0x21)
++#define EC_VAL_INVALID_CID EC_ERR(0x22)
++#define EC_VAL_INVALID_UUI EC_ERR(0x23)
++#define EC_VAL_INVALID_UUI_DISCARD EC_ERR(0x24)
++#define EC_VAL_CH_ALREADY_OPEN EC_ERR(0x25)
++
++#define EC_VAL_RCB_MALLOC_FAILED EC_ERR(0x26)
++#define EC_VAL_RX_BUFFER_MALLOC_FAILED EC_ERR(0x27)
++#define EC_VAL_OUT_OF_TCBS EC_ERR(0x28)
++#define EC_VAL_NO_TCBS EC_ERR(0x29)
++#define EC_VAL_NULL_RCB EC_ERR(0x30)|EC_CRITICAL
++#define EC_VAL_SOP_ERROR EC_ERR(0x31)|EC_CRITICAL
++#define EC_VAL_EOP_ERROR EC_ERR(0x32)|EC_CRITICAL
++#define EC_VAL_NULL_TCB EC_ERR(0x33)|EC_CRITICAL
++#define EC_VAL_CORRUPT_RCB_CHAIN EC_ERR(0x34)|EC_CRITICAL
++#define EC_VAL_TCB_MALLOC_FAILED EC_ERR(0x35)
++
++#define EC_VAL_DISABLE_POLLING_FAILED EC_ERR(0x36)
++#define EC_VAL_KEY_NOT_FOUND EC_ERR(0x37)
++#define EC_VAL_MALLOC_FAILED EC_ERR(0x38)
++#define EC_VAL_RESET_BASE_NOT_FOUND EC_ERR(0x39)|EC_CRITICAL
++#define EC_VAL_INVALID_STATE EC_ERR(0x40)
++#define EC_VAL_NO_TXH_WORK_TO_DO EC_ERR(0x41)
++#define EC_VAL_NO_TXL_WORK_TO_DO EC_ERR(0x42)
++#define EC_VAL_NO_RX_WORK_TO_DO EC_ERR(0x43)
++#define EC_VAL_NOT_LINKED EC_ERR(0x44)
++#define EC_VAL_INTERRUPT_NOT_FOUND EC_ERR(0x45)
++#define EC_VAL_OFFSET_NOT_FOUND EC_ERR(0x46)
++#define EC_VAL_MODULE_ALREADY_CLOSED EC_ERR(0x47)
++#define EC_VAL_MODULE_ALREADY_SHUTDOWN EC_ERR(0x48)
++#define EC_VAL_ACTION_NOT_FOUND EC_ERR(0x49)
++#define EC_VAL_RX_CH_ALREADY_SETUP EC_ERR(0x50)
++#define EC_VAL_TX_CH_ALREADY_SETUP EC_ERR(0x51)
++#define EC_VAL_RX_CH_ALREADY_OPEN EC_ERR(0x52)
++#define EC_VAL_TX_CH_ALREADY_OPEN EC_ERR(0x53)
++#define EC_VAL_CH_ALREADY_SETUP EC_ERR(0x54)
++#define EC_VAL_RCB_NEEDS_BUFFER EC_ERR(0x55) /* +GSG 030410 */
++#define EC_VAL_RCB_DROPPED EC_ERR(0x56) /* +GSG 030410 */
++#define EC_VAL_INVALID_VALUE EC_ERR(0x57)
++
++/**
++@defgroup shared_data Shared Data Structures
++
++The data structures documented here are shared by all modules.
++*/
++
++/**
++ * @ingroup shared_data
++ * This is the fragment list structure. Each fragment list entry contains a
++ * length and a data buffer.
++ */
++typedef struct
++ {
++ bit32u len; /**< Length of the fragment in bytes (lower 16 bits are valid). For SOP, upper 16 bits is the buffer offset. */
++ void *data; /**< Pointer to fragment data. */
++ void *OsInfo; /**< Pointer to OS defined data. */
++ }FRAGLIST;
++
++#if defined (_CPHAL_CPMAC)
++#define CB_PASSCRC_BIT (1<<26)
++
++/* CPMAC CPHAL STATUS */
++#define CPMAC_STATUS_LINK (1 << 0)
++#define CPMAC_STATUS_LINK_DUPLEX (1 << 1) /* 0 - HD, 1 - FD */
++#define CPMAC_STATUS_LINK_SPEED (1 << 2) /* 0 - 10, 1 - 100 */
++
++/* ADAPTER CHECK Codes */
++
++#define CPMAC_STATUS_ADAPTER_CHECK (1 << 7)
++#define CPMAC_STATUS_HOST_ERR_DIRECTION (1 << 8)
++#define CPMAC_STATUS_HOST_ERR_CODE (0xF << 9)
++#define CPMAC_STATUS_HOST_ERR_CH (0x7 << 13)
++
++#define _CPMDIO_DISABLE (1 << 0)
++#define _CPMDIO_HD (1 << 1)
++#define _CPMDIO_FD (1 << 2)
++#define _CPMDIO_10 (1 << 3)
++#define _CPMDIO_100 (1 << 4)
++#define _CPMDIO_NEG_OFF (1 << 5)
++#define _CPMDIO_LOOPBK (1 << 16)
++#define _CPMDIO_NOPHY (1 << 20)
++#endif
++
++/**
++ * @ingroup shared_data
++ * Channel specific configuration information. This structure should be
++ * populated by upper-layer software prior to calling @c ChannelSetup(). Any
++ * configuration item that can be changed on a per channel basis should
++ * be represented here. Each module may define this structure with additional
++ * module-specific members.
++ */
++typedef struct
++ {
++ int Channel; /**< Channel number. */
++ int Direction; /**< DIRECTION_RX(1) or DIRECTION_TX(0). */
++ OS_SETUP *OsSetup; /**< OS defined information associated with this channel. */
++
++#if defined(_CPHAL_AAL5) || defined (_CPHAL_CPSAR) || defined (_CPHAL_CPMAC)
++ int RxBufSize; /**< Size (in bytes) for each Rx buffer.*/
++ int RxBufferOffset; /**< Number of bytes to offset rx data from start of buffer (must be less than buffer size). */
++ int RxNumBuffers; /**< The number of Rx buffer descriptors to allocate for Ch. */
++ int RxServiceMax; /**< Maximum number of packets to service at one time. */
++
++ int TxNumBuffers; /**< The number of Tx buffer descriptors to allocate for Ch. */
++ int TxNumQueues; /**< Number of Tx queues for this channel (1-2). Choosing 2 enables a low priority SAR queue. */
++ int TxServiceMax; /**< Maximum number of packets to service at one time. */
++#endif
++
++#if defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
++ int CpcsUU; /**< The 2-byte CPCS UU and CPI information. */
++ int Gfc; /**< Generic Flow Control. */
++ int Clp; /**< Cell Loss Priority. */
++ int Pti; /**< Payload Type Indication. */
++#endif
++
++#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
++ int DaMask; /**< Specifies whether credit issuance is paused when Tx data not available. */
++ int Priority; /**< Priority bin this channel will be scheduled within. */
++ int PktType; /**< 0=AAL5,1=Null AAL,2=OAM,3=Transparent,4=AAL2. */
++ int Vci; /**< Virtual Channel Identifier. */
++ int Vpi; /**< Virtual Path Identifier. */
++ int FwdUnkVc; /**< Enables forwarding of unknown VCI/VPI cells to host. 1=enable, 0=disable. */
++
++ /* Tx VC State */
++ int TxVc_CellRate; /**< Tx rate, set as clock ticks between transmissions (SCR for VBR, CBR for CBR). */
++ int TxVc_QosType; /**< 0=CBR,1=VBR,2=UBR,3=UBRmcr. */
++ int TxVc_Mbs; /**< Min Burst Size in cells.*/
++ int TxVc_Pcr; /**< Peak Cell Rate for VBR in clock ticks between transmissions. */
++
++ bit32 TxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Tx Ch (must be big endian with 0 PTI). */
++ int TxVc_OamTc; /**< TC Path to transmit OAM cells for TX connection (0,1). */
++ int TxVc_VpOffset; /**< Offset to the OAM VP state table. */
++ /* Rx VC State */
++ int RxVc_OamCh; /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
++ int RxVc_OamToHost; /**< 0=do not pass, 1=pass. */
++ bit32 RxVc_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx conn (must be big endian with 0 PTI). */
++ int RxVc_OamTc; /**< TC Path to transmit OAM cells for RX connection (0,1). */
++ int RxVc_VpOffset; /**< Offset to the OAM VP state table. */
++ /* Tx VP State */
++ int TxVp_OamTc; /**< TC Path to transmit OAM cells for TX VP connection (0,1). */
++ bit32 TxVp_AtmHeader; /**< ATM Header placed on firmware gen'd VP OAM cells for this Tx VP conn (must be big endian with 0 VCI). */
++ /* Rx VP State */
++ int RxVp_OamCh; /**< Ch to terminate rx'd OAM cells to be forwarded to the host. */
++ int RxVp_OamToHost; /**< 0=do not pass, 1=pass. */
++ bit32 RxVp_AtmHeader; /**< ATM Header placed on firmware gen'd OAM cells for this Rx VP conn (must be big endian with 0 VCI). */
++ int RxVp_OamTc; /**< TC Path to transmit OAM cells for RX VP connection (0,1). */
++ int RxVp_OamVcList; /**< Indicates all VC channels associated with this VP channel (one-hot encoded). */
++#endif
++
++
++#ifdef _CPHAL_VDMAVT
++ bit32u RemFifoAddr; /* Mirror mode only. */
++ bit32u FifoAddr;
++ bit32 PollInt;
++ bit32 FifoSize;
++ int Ready;
++#endif
++
++ }CHANNEL_INFO;
++
++/*
++ * This structure contains each statistic value gathered by the CPHAL.
++ * Applications may access statistics data by using the @c StatsGet() routine.
++ */
++/* STATS */
++#if defined(_CPHAL_AAL2) || defined(_CPHAL_AAL5) || defined(_CPHAL_CPSAR)
++typedef struct
++ {
++ bit32u CrcErrors[16];
++ bit32u LenErrors[16];
++ bit32u DmaLenErrors[16];
++ bit32u AbortErrors[16];
++ bit32u StarvErrors[16];
++ bit32u TxMisQCnt[16][2];
++ bit32u RxMisQCnt[16];
++ bit32u RxEOQCnt[16];
++ bit32u TxEOQCnt[16][2];
++ bit32u RxPacketsServiced[16];
++ bit32u TxPacketsServiced[16][2];
++ bit32u RxMaxServiced;
++ bit32u TxMaxServiced[16][2];
++ bit32u RxTotal;
++ bit32u TxTotal;
++ } STAT_INFO;
++#endif
++
++/*
++ * VDMA Channel specific configuration information
++ */
++#ifdef _CPHAL_AAL2
++typedef struct
++ {
++ int Ch; /**< Channel Number */
++ int RemoteEndian; /**< Endianness of remote VDMA-VT device */
++ int CpsSwap; /**< When 0, octet 0 in CPS pkt located in LS byte of 16-bit word sent to rem VDMA device. When 1, in MS byte. */
++ }VdmaChInfo;
++#endif
++
++#ifndef _CPHAL
++ typedef void HAL_DEVICE;
++ typedef void HAL_PRIVATE;
++ typedef void HAL_RCB;
++ typedef void HAL_RECEIVEINFO;
++#endif
++
++/**
++ * @ingroup shared_data
++ * The HAL_FUNCTIONS struct defines the function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to xxxInitModule().
++ */
++typedef struct
++ {
++ int (*ChannelSetup) (HAL_DEVICE *HalDev, CHANNEL_INFO *Channel, OS_SETUP *OsSetup);
++ int (*ChannelTeardown) (HAL_DEVICE *HalDev, int Channel, int Mode);
++ int (*Close) (HAL_DEVICE *HalDev, int Mode);
++ int (*Control) (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
++ int (*Init) (HAL_DEVICE *HalDev);
++ int (*Open) (HAL_DEVICE *HalDev);
++ int (*PacketProcessEnd) (HAL_DEVICE *HalDev);
++ int (*Probe) (HAL_DEVICE *HalDev);
++ int (*RxReturn) (HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
++ int (*Send) (HAL_DEVICE *HalDev, FRAGLIST *FragList, int FragCount, int PacketSize, OS_SENDINFO *OsSendInfo, bit32u Mode);
++ int (*Shutdown) (HAL_DEVICE *HalDev);
++ int (*Tick) (HAL_DEVICE *HalDev);
++
++#ifdef _CPHAL_AAL5
++ int (*Kick) (HAL_DEVICE *HalDev, int Queue);
++ void (*OamFuncConfig) (HAL_DEVICE *HalDev, unsigned int OamConfig);
++ void (*OamLoopbackConfig) (HAL_DEVICE *HalDev, unsigned int OamConfig, unsigned int *LLID, unsigned int CorrelationTag);
++ volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
++ STAT_INFO* (*StatsGetOld)(HAL_DEVICE *HalDev);
++#endif
++ } HAL_FUNCTIONS;
++
++/**
++ * @ingroup shared_data
++ * The OS_FUNCTIONS struct defines the function pointers for all upper layer
++ * functions accessible to the CPHAL. The upper layer software is responsible
++ * for providing the correct OS-specific implementations for the following
++ * functions. It is populated by calling InitModule() (done by the CPHAL in
++ * xxxInitModule().
++ */
++typedef struct
++ {
++ int (*Control)(OS_DEVICE *OsDev, const char *Key, const char *Action, void *Value);
++ void (*CriticalOn)(void);
++ void (*CriticalOff)(void);
++ void (*DataCacheHitInvalidate)(void *MemPtr, int Size);
++ void (*DataCacheHitWriteback)(void *MemPtr, int Size);
++ int (*DeviceFindInfo)(int Inst, const char *DeviceName, void *DeviceInfo);
++ int (*DeviceFindParmUint)(void *DeviceInfo, const char *Parm, bit32u *Value);
++ int (*DeviceFindParmValue)(void *DeviceInfo, const char *Parm, void *Value);
++ void (*Free)(void *MemPtr);
++ void (*FreeRxBuffer)(OS_RECEIVEINFO *OsReceiveInfo, void *MemPtr);
++ void (*FreeDev)(void *MemPtr);
++ void (*FreeDmaXfer)(void *MemPtr);
++ void (*IsrRegister)(OS_DEVICE *OsDev, int (*halISR)(HAL_DEVICE*, int*), int InterruptBit);
++ void (*IsrUnRegister)(OS_DEVICE *OsDev, int InterruptBit);
++ void* (*Malloc)(bit32u size);
++ void* (*MallocDev)(bit32u Size);
++ void* (*MallocDmaXfer)(bit32u size, void *MemBase, bit32u MemRange);
++ void* (*MallocRxBuffer)(bit32u size, void *MemBase, bit32u MemRange,
++ OS_SETUP *OsSetup, HAL_RECEIVEINFO *HalReceiveInfo,
++ OS_RECEIVEINFO **OsReceiveInfo, OS_DEVICE *OsDev);
++ void* (*Memset)(void *Dest, int C, bit32u N);
++ int (*Printf)(const char *Format, ...);
++ int (*Receive)(OS_DEVICE *OsDev,FRAGLIST *FragList,bit32u FragCount,
++ bit32u PacketSize,HAL_RECEIVEINFO *HalReceiveInfo, bit32u Mode);
++ int (*SendComplete)(OS_SENDINFO *OsSendInfo);
++ int (*Sprintf)(char *S, const char *Format, ...);
++ int (*Strcmpi)(const char *Str1, const char *Str2);
++ unsigned int (*Strlen)(const char *S);
++ char* (*Strstr)(const char *S1, const char *S2);
++ unsigned long (*Strtoul)(const char *Str, char **Endptr, int Base);
++ void (*TeardownComplete)(OS_DEVICE *OsDev, int Ch, int Direction);
++ } OS_FUNCTIONS;
++
++/************** MODULE SPECIFIC STUFF BELOW **************/
++
++#ifdef _CPHAL_CPMAC
++
++/*
++int halCpmacInitModule(HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc, int (*osBridgeInitModule)(OS_FUNCTIONS *), void* (*osMallocDev) (bit32u), int *Size, int inst);
++*/
++
++int halCpmacInitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ HAL_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++#ifdef _CPHAL_AAL5
++/*
++ * @ingroup shared_data
++ * The AAL5_FUNCTIONS struct defines the AAL5 function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to cphalInitModule().
++ */
++/*
++typedef struct
++ {
++ int (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
++ int (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
++ int (*Close)(HAL_DEVICE *HalDev, int Mode);
++ int (*Init)(HAL_DEVICE *HalDev);
++ int (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
++ int (*Open)(HAL_DEVICE *HalDev);
++ int (*InfoGet)(HAL_DEVICE *HalDev, int Key, void *Value);
++ int (*Probe)(HAL_DEVICE *HalDev);
++ int (*RxReturn)(HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
++ int (*Send)(HAL_DEVICE *HalDev,FRAGLIST *FragList,int FragCount,
++ int PacketSize,OS_SENDINFO *OsSendInfo,int Ch, int Queue,
++ bit32u Mode);
++ int (*StatsClear)(HAL_DEVICE *HalDev);
++ STAT_INFO* (*StatsGet)(HAL_DEVICE *HalDev);
++ int (*Status)(HAL_DEVICE *HalDev);
++ void (*Tick)(HAL_DEVICE *HalDev);
++ int (*Kick)(HAL_DEVICE *HalDev, int Queue);
++ volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
++ } AAL5_FUNCTIONS;
++*/
++
++int cpaal5InitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ HAL_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++#ifdef _CPHAL_AAL2
++/**
++ * @ingroup shared_data
++ * The AAL2_FUNCTIONS struct defines the AAL2 function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to cphalInitModule().
++ */
++typedef struct
++ {
++ int (*ChannelSetup)(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
++ int (*ChannelTeardown)(HAL_DEVICE *HalDev, int Ch, int Mode);
++ int (*Close)(HAL_DEVICE *HalDev, int Mode);
++ int (*Init)(HAL_DEVICE *HalDev);
++ int (*ModeChange)(HAL_DEVICE *HalDev, char *DeviceParms);
++ int (*Open)(HAL_DEVICE *HalDev);
++ int (*OptionsGet)(HAL_DEVICE *HalDev, char *Key, bit32u *Value);
++ int (*Probe)(HAL_DEVICE *HalDev);
++
++ int (*StatsClear)(HAL_DEVICE *HalDev);
++ STAT_INFO* (*StatsGet)(HAL_DEVICE *HalDev);
++ int (*Status)(HAL_DEVICE *HalDev);
++ void (*Tick)(HAL_DEVICE *HalDev);
++ int (*Aal2UuiMappingSetup)(HAL_DEVICE *HalDev, int VC, int UUI,
++ int VdmaCh, int UUIDiscard);
++ int (*Aal2RxMappingSetup)(HAL_DEVICE *HalDev, int VC, int CID,
++ int LC);
++ int (*Aal2TxMappingSetup)(HAL_DEVICE *HalDev, int VC, int LC, int VdmaCh);
++ int (*Aal2VdmaChSetup)(HAL_DEVICE *HalDev, bit32u RemVdmaVtAddr,
++ VdmaChInfo *VdmaCh);
++ volatile bit32u* (*RegAccess)(HAL_DEVICE *HalDev, bit32u RegOffset);
++ int (*Aal2ModeChange)(HAL_DEVICE *HalDev, int Vc, int RxCrossMode,
++ int RxMultiMode, int TxMultiMode, int SchedMode,
++ int TcCh);
++ void (*Aal2VdmaEnable)(HAL_DEVICE *HalDev, int Ch);
++ int (*Aal2VdmaDisable)(HAL_DEVICE *HalDev, int Ch);
++ } AAL2_FUNCTIONS;
++
++int cpaal2InitModule(HAL_DEVICE **HalDev,
++ OS_DEVICE *OsDev,
++ AAL2_FUNCTIONS **HalFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++#ifdef _CPHAL_VDMAVT
++/**
++ * @ingroup shared_data
++ * The VDMA_FUNCTIONS struct defines the HAL function pointers used by upper layer
++ * software. The upper layer software receives these pointers through the
++ * call to InitModule().
++ *
++ * Note that this list is still under definition.
++ */
++typedef struct
++ {
++ bit32 (*Init)( HAL_DEVICE *VdmaVtDev);
++ /* bit32 (*SetupTxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
++ bit32u Addr, bit32u Size, bit32u PollInt);
++ bit32 (*SetupRxFifo)(HAL_DEVICE *VdmaVtDev, bit32u LclRem,
++ bit32u Addr, bit32u Size, bit32u PollInt); */
++ bit32 (*Tx)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*Rx)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*SetRemoteChannel)(HAL_DEVICE *VdmaVtDev, bit32u RemAddr,
++ bit32u RemDevID);
++ bit32 (*ClearRxInt)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*ClearTxInt)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*Open)(HAL_DEVICE *VdmaVtDev);
++ bit32 (*Close)(HAL_DEVICE *VdmaVtDev);
++ int (*Control) (HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value);
++ int (*ChannelSetup)(HAL_DEVICE *VdmaVtDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup);
++ int (*ChannelTeardown)(HAL_DEVICE *VdmaVtDev, int Ch, int Mode);
++ int (*Send)(HAL_DEVICE *VdmaVtDev,FRAGLIST *FragList,int FragCount,
++ int PacketSize,OS_SENDINFO *OsSendInfo,bit32u Mode);
++ } VDMA_FUNCTIONS;
++
++int VdmaInitModule(HAL_DEVICE **VdmaVt,
++ OS_DEVICE *OsDev,
++ VDMA_FUNCTIONS **VdmaVtFunc,
++ OS_FUNCTIONS *OsFunc,
++ int OsFuncSize,
++ int *HalFuncSize,
++ int Inst);
++#endif
++
++/*
++extern int cphalInitModule(MODULE_TYPE ModuleType, HAL_DEVICE **HalDev, OS_DEVICE *OsDev, HAL_FUNCTIONS *HalFunc,
++ int (*osInitModule)(OS_FUNCTIONS *), void* (*osMallocDev)(bit32u),
++ int *Size, int Inst);
++*/
++
++
++#ifdef _CPHAL_AAL5
++extern const char hcSarFrequency[];
++#endif
++
++#ifdef _CPHAL_CPMAC
++/* following will be common, once 'utl' added */
++extern const char hcClear[];
++extern const char hcGet[];
++extern const char hcSet[];
++extern const char hcTick[];
++
++extern const char hcCpuFrequency[];
++extern const char hcCpmacFrequency[];
++extern const char hcMdioBusFrequency[];
++extern const char hcMdioClockFrequency[];
++extern const char hcCpmacBase[];
++extern const char hcPhyNum[];
++extern const char hcSize[];
++extern const char hcCpmacSize[];
++extern const char hcPhyAccess[];
++#endif
++
++#endif /* end of _INC_ */
+diff -urN linux.old/drivers/atm/sangam_atm/dev_host_interface.h linux.dev/drivers/atm/sangam_atm/dev_host_interface.h
+--- linux.old/drivers/atm/sangam_atm/dev_host_interface.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/dev_host_interface.h 2005-08-23 04:46:50.091844608 +0200
+@@ -0,0 +1,1162 @@
++#ifndef __DEV_HOST_INTERFACE_H__
++#define __DEV_HOST_INTERFACE_H__ 1
++
++/*******************************************************************************
++* FILE PURPOSE: Public header file for the Host-to-DSP interface
++********************************************************************************
++*
++* TEXAS INSTRUMENTS PROPRIETARTY INFORMATION
++*
++* (C) Copyright Texas Instruments Inc. 2002. All rights reserved.
++*
++* Property of Texas Instruments Incorporated
++*
++* Restricted Rights - Use, duplication, or disclosure is subject to
++* restrictions set forth in TI's program license agreement and
++* associated documentation
++*
++*
++* FILE NAME: dev_host_interface.h
++*
++* DESCRIPTION:
++* This header file defines the variables and parameters used between the
++* host processor and the DSP. This file is included in both the DSP
++* software and the host software.
++*
++* RULES FOR MODIFICATION AND USE OF THIS FILE:
++*
++* --The main pointer to the struct of pointers will always be at the same fixed
++* location (0x80000000).
++*
++* --Each pointer element in the struct of pointers (indicated by the main pointer)
++* will always point to a struct only.
++*
++* --Any new structures added to the host interface in subsequent versions must
++* each have a corresponding new pointer element added to the END of the struct
++* of pointers. Other than this, there will never be any moving or rearranging
++* of the pointer elements in the struct of pointers.
++*
++* --Any new elements added to existing structures will be added at the END of the
++* structure. Other than this, there will never be any moving or rearranging
++* of structure elements.
++*
++* --A new structure will never be added as a new element in an old structure.
++* New structures must be added separately with a new entry in the struct of
++* pointers, as noted above.
++*
++* --Also, the sizes of existing arrays within old structures will never be changed.
++*
++* --The modem code in the DSP will never reference the struct of pointers in order
++* to avoid aliasing issues in the DSP code. The modem code will only use the
++* specific structures directly.
++*
++* --The host processor never accesses the DSP side of the ATM-TC hardware directly.
++* The DSP interfaces directly to the ATM-TC hardware and relays information to
++* the host processor through the host interface.
++*
++* --The host processor can track the modem's transition through important states
++* by accessing the Modem State Bit Field in the host interface. Each bit in
++* the bit field represents an important state to track in the modem. As the
++* modem transitions through each important state, the corresponding bit will
++* change from a zero to a one. Each bit in the bit field will only be reset to
++* zero if the modem retrains. If new states need to be tracked and are added
++* in subsequent versions of the host interface, a corresponding bit will be
++* added at the END of the bit field to ensure backwards compatibility. The
++* Modem State Bit Field is reset if the modem retrains or falls out of Showtime.
++*
++* --An interrupt will be sent to the host processor when a change occurs in the
++* Modem State Bit Field. There is an interrupt masking register which can mask
++* specific interrupts corresponding to the bits of the Modem State Bit Field.
++* This allows the host to keep an interrupt from being generated for those
++* states that are masked.
++*
++* HISTORY:
++*
++* 11/20/02 J. Bergsagel Written from the previous host interface file
++* 11/27/02 J. Bergsagel Added comments for mailbox control struct and
++* fixed a couple items for overlay page stuff.
++* Also, added temporary elements for SWTC code.
++* 12/04/02 J. Bergsagel Added extra dummy byte to DEV_HOST_eocVarDef_t
++* for proper word alignment.
++* 12/12/02 J. Bergsagel Changed initial states in the modem state bit field
++* and added more instructions for adding more states.
++* 12/16/02 J. Bergsagel Changed name "hostVersion_p" to "hostIntfcVersion_p".
++* Removed dspAturState from DEV_HOST_modemStateBitField_t.
++* Reorganized several struct elements to clean up the
++* host interface.
++* 12/27/02 Sameer V Added missing channel 0 statistics for TC. Added
++* ocd error information.
++* 12/27/02 Sameer V Added overlayState to OlayDP_Parms to indicate whether
++* overlays are being executed in current state.
++* 01/06/03 J. Bergsagel Added maxAllowedMargin and minRequiredMargin to
++* DEV_HOST_msg_t.
++* Renamed TC chan 1 items to be chan 0 items to start out.
++* 01/17/03 Sameer V Moved delineationState to atmStats structure.
++* 01/21/03 Barnett Implemented Ax7 UNIT-MODULE modular software framework.
++* 01/22/03 J. Bergsagel Added warning comments for certain struct typedefs.
++* 01/23/03 C. Perez-N. Removed old AX5-only diags. command/response entries in the
++* HOST and DSP ennumerations, and added the AX7 new ones
++* Added pointer entries in the DEV_HOST_dspOamSharedInterface_t
++* structure pointing to the analog diags. input/output/options
++* structures.
++* 01/29/03 Sameer V Removed TC_IDLE in enum for delineation state. Hardware
++* only reports TC_HUNT, TC_PRESYNC and TC_SYNC.
++* 03/07/03 Sameer/Jonathan Put SWTC token around structs and elements only used by SWTC
++* 03/12/03 Mannering Add CO profile data structures
++* 03/18/03 J. Bergsagel Removed the obsolete DSP_CHECK_TC response message.
++* 03/24/03 J. Bergsagel Added DEV_HOST_hostInterruptMask_t for masking DSP interrupt sources
++* 03/28/03 C. Perez-N Changed the C-style comments and made them C++ sytle instead.
++* Replaced the occurrences of "SINT32 *" pointer declarations with
++* "PSINT32"
++* 03/28/03 Mannering Update CO profile data structures
++* 04/04/03 S. Yim Add host I/F hooks for switchable hybrid and RJ11
++* inner/outer pair selection
++* 04/11/03 J. Bergsagel Changed modem state bit field struct types to enums instead and used
++* a single integer variable for each "bitfield".
++* Changed bit field for host interrupt masks to an integer value also.
++* 04/14/03 J. Bergsagel Changed name of table pointer "meanSquareTblDstrm_p" to "marginTblDstrm_p".
++* 04/03/03 Umesh Iyer CMsg1 and RMsg1 use the same storage as CMSGPCB and RMSGPCB.
++* The string lengths for these have been adjusted to hold the longest
++* message in each case. The PCB messages from ADSL2 are longer.
++* 04/21/03 Sameeer V Added new host mailbox message for shutting down the DSLSS peripherals.
++* 04/23/03 J. Bergsagel Fixed comments for overlay mailbox messages and for losErrors.
++* 04/28/03 Mannering Added skip phase op flag to CO profile data structure
++* 05/05/03 Mannering Review Comments - Removed "#if CO_PROFILE" from around structure
++* definitions and define the number of profiles (DEV_HOST_LIST_ENTRIES)
++* 05/13/03 J. Bergsagel Added new elements to DEV_HOST_phyPerf_t for host control of hybrid.
++* 05/15/03 J. Bergsagel Added "farEndLosErrors" and "farEndRdiErrors" to DEV_HOST_modemStatsDef_t.
++* 05/16/03 Mannering Updated CO profile structure to support updated bit allocation and
++* interopability.
++* 05/20/03 Sameer V Added DSP message to inicate DYING GASP.
++* 05/22/03 J. Bergsagel Added a new struct typedef "DEV_HOST_hostInterruptSource_t".
++* Added "atucGhsRevisionNum" to "DEV_HOST_dspWrNegoParaDef_t".
++* Moved the following struct typedef's here to the public host interface:
++* DEV_HOST_dspBitSwapDef_t
++* DEV_HOST_atmDsBert_t
++* 05/28/03 A. Redfern Changed pointer type and location for margin reporting.
++* 05/28/03 Mannering Moved CO profile defines to dev_host_interface_pvt.h
++* 05/28/03 J. Bergsagel Moved subStateIndex and STM BERT controls into new struct "DEV_HOST_modemEnvPublic_t"
++* 05/29/03 J. Bergsagel Added elements to "DEV_HOST_modemEnvPublic_t" for host control of DSLSS LED's.
++* 06/10/03 Umesh Iyer Modified trainMode check to be compliant with the new host i/f mods.
++* 06/05/03 J. Bergsagel Added enum that will eventually replace the bitfield: DEV_HOST_diagAnlgOptionsVar_t.
++* Added new element "currentHybridNumUsed" in the DEV_HOST_phyPerf_t typedef
++* Added new host control flags for LPR signal detection on GPIO[0].
++* 06/06/03 A. Redfern Removed fine gain scale from the CO profile and added max downstream power cutback.
++* Changed "test1" in CO profile struct to "phyEcDelayAdjustment".
++* 06/26/03 J. Bergsagel Added genericStructure typedef and two pointer elements of this type in the big table.
++* 07/03/03 Jack Huang Renamed test2 to bSwapThresholdUpdate
++* 07/07/03 Mallesh Changed phySigTxPowerCutback_f flag to a variable phySigTxGainReductionAt0kft which indicates the
++* amount of gain reduction in linear scale.
++* 07/15/03 Sameer V Changed DEV_HOST_diagAnlgOptionsVar_t to be an enum instead of a bit field. Host code
++* does not support setting bit fields.
++* 07/22/03 Jack Huang Added bitswap control flag in host i/f for API calls
++* 08/06/03 Sameer V Added missingToneDs_p to the DEV_HOST_oamWrNegoParaDef_t to enable host to switch off
++* DS tones on specified bins
++* 08/21/03 Jack Huang Added pcbEnabled flag in the DEV_HOST_modemEnvPublic_t structure
++* Added g.hs buffer definitions to DEV_HOST_dspOamSharedInterface_t
++* Added DEV_HOST_consBufDef_t to the DEV_HOST_dspOamSharedInterface_t structure
++* 08/26/03 J. Bergsagel Fixed name of "missingToneDs_p" to be "missingToneDsAddr" instead (since it is
++* not really used as a pointer).
++* 09/11/03 Mallesh Added a flag "usPilotInT1413ModeInMedley" to determine the need to send Upstream Pilot
++* in medley in T1.413 mode.
++* 09/12/03 J. Bergsagel Changed "test3" to "phyBitaFastPathExcessFineGainBump" in CO profile struct.
++* Changed "test4" to "phyBitaSkipGapAdjustment" in CO profile struct.
++* 09/23/03 J. Bergsagel Changed "T1413vendorRevisionNumber" to "vendorRevisionNumber" in DEV_HOST_msg_t.
++* Added ADSL2 and ADSL2 diag. states to the modem state bit field.
++* 10/01/03 J. Bergsagel Changed define of "MULTI_MODE" to be 255 to indicate that all possible bits
++* in the 8-bit bit field are turned on for any current and future training modes.
++* 10/09/03 M. Turkboylari Added DSP_TRAINING_MSGS and adsl2DeltMsgs_p, which is a pointer to a pointer,
++* in order to pass the ADSL2 training and DELT messages to the host side. This is for ACT.
++* 10/20/03 Mallesh Added a GHS state enumerator for cleardown
++* 10/20/03 Xiaohui Li Add definition for READSL2_MODE and READSL2_DELT
++* 11/07/03 J. Bergsagel Removed all code for when SWTC==1, which therefore allows removal of include of
++* "env_def_defines.h". We shouldn't have any compile tokens used in this file.
++* (the SWTC token is always off in any Ax7 code).
++* 11/14/03 J. Bergsagel Also removed READSL2_ENABLE token (no more compile tokens to be used in this .h file).
++* 12/12/03 Sameer/Ram Added DEV_HOST_EOCAOC_INTERRUPT_MASK to enable host to disable response code for AOC/EOC
++* mailbox messages
++* 12/09/03 Jack Huang Changed G.hs txbuf size from 60 to 64 to fit the max segment size
++* 12/15/03 Mallesh Changed vendor ID type defenition from SINT16 to UINT16
++* 12/23/03 Sameer V Added ability to turn off constellation display reporting to host using oamFeature bit field.
++* 12/24/03 Sameer V Changed comment for Constellation Display Current Address to Host Write instead of DSP Write.
++* 12/26/03 Sameer/Ram Added DEV_HOST_GHSMSG_INTERRUPT_MASK to enable host to disable response code for GHS Messages
++* (C) Copyright Texas Instruments Inc. 2002. All rights reserved.
++*******************************************************************************/
++
++#include "dev_host_verdef.h"
++
++// ---------------------------------------------------------------------------------
++// Address of the pointer to the DEV_HOST_dspOamSharedInterface_s struct of pointers
++// This is where it all starts.
++// ---------------------------------------------------------------------------------
++#define DEV_HOST_DSP_OAM_POINTER_LOCATION 0x80000000
++
++// The define "MAX_NUM_UPBINS" is used in "DEV_HOST_diagAnlgInputVar_t" below.
++// This value can never be changed (for host intf. backwards compatibility)
++#define MAX_NUM_UPBINS 64
++
++// -----------------------------------------------
++// Begin common enumerations between DSP and host.
++// -----------------------------------------------
++
++// These Host-to-DSP commands are organized into two groups:
++// immediate state change commands and status affecting commands.
++// Do not add or remove commands except at the bottom since the DSP assumes this sequence.
++
++enum
++{
++ HOST_ACTREQ, // Send R-ACKREQ and monitor for C-ACKx
++ HOST_QUIET, // Sit quietly doing nothing for about 60 seconds, DEFAULT STATE; R_IDLE
++ HOST_XMITBITSWAP, // Perform upstream bitswap - FOR INTERNAL USE ONLY
++ HOST_RCVBITSWAP, // Perform downstream bitswap - FOR INTERNAL USE ONLY
++ HOST_RTDLPKT, // Send a remote download packet - FOR INTERNAL USE ONLY
++ HOST_CHANGELED, // Read the LED settings and change accordingly
++ HOST_IDLE, // Sit quiet
++ HOST_REVERBTEST, // Generate REVERB for manufacturing test
++ HOST_CAGCTEST, // Set coarse receive gain for manufacturing test
++ HOST_DGASP, // send Dying Gasp messages through EOC channel
++ HOST_GHSREQ, // G.hs - FOR INTERNAL USE ONLY
++ HOST_GHSMSG, // G.hs - FOR INTERNAL USE ONLY
++ HOST_GHS_SENDGALF, // G.hs - FOR INTERNAL USE ONLY
++ HOST_GHSEXIT, // G.hs - FOR INTERNAL USE ONLY
++ HOST_GHSMSG1, // G.hs - FOR INTERNAL USE ONLY
++ HOST_HYBRID, // Enable/Disable automatic hybrid switch
++ HOST_RJ11SELECT, // RJ11 inner/outer pair select
++ HOST_DIGITAL_MEM, // Digital Diags: run external memory tests
++ HOST_TXREVERB, // AFE Diags: TX path Reverb
++ HOST_TXMEDLEY, // AFE Diags: TX path Medley
++ HOST_RXNOISEPOWER, // AFE Diags: RX noise power
++ HOST_ECPOWER, // AFE Diags: RX eco power
++ HOST_ALL_ADIAG, // AFE Diags: all major analog diagnostic modes. Host is responsible to initiate each diagnostic sessions
++ HOST_USER_ADIAG, // AFE Diags: Host fills in analog diagnostic input data structure as specified and requests DSP to perform measurements as specified
++ HOST_QUIT_ADIAG, // AFE Diags: Host requests DSP to quit current diagnostic session. This is used for stopping the transmit REVERB/MEDLEY
++ HOST_NO_CMD, // All others - G.hs - FOR INTERNAL USE ONLY
++ HOST_DSLSS_SHUTDOWN, // Host initiated DSLSS shutdown message
++ HOST_SET_GENERIC, // Set generic CO profile
++ HOST_UNDO_GENERIC, // Set profile previous to Generic
++ HOST_GHS_CLEARDOWN // G.hs - FOR INTERNAL USE ONLY to start cleardown
++};
++
++// These DSP-to-Host responses are organized into two groups:
++// responses to commands and requests for OAM services.
++
++enum
++{
++ DSP_IDLE, // R_IDLE state entered
++ DSP_ACTMON, // R_ACTMON state entered
++ DSP_TRAIN, // R_TRAIN state entered
++ DSP_ACTIVE, // R_ACTIVE state entered
++ DSP_XMITBITSWAP, // Upstream bitswap complete - FOR INTERNAL USE ONLY
++ DSP_RCVBITSWAP, // Downstream bitswap complete - FOR INTERNAL USE ONLY
++ DSP_RTDL, // R_RTDL state entered - FOR INTERNAL USE ONLY
++ DSP_RRTDLPKT, // RTDL packet received - FOR INTERNAL USE ONLY
++ DSP_XRTDLPKT, // RTDL packet transmitted - FOR INTERNAL USE ONLY
++ DSP_ERROR, // Command rejected, wrong state for this command
++ DSP_REVERBTEST, // Manufacturing REVERB test mode entered
++ DSP_CAGCTEST, // Manufacturing receive gain test done
++ DSP_OVERLAY_START, // Notify host that page overlay has started - overlay number indicated by "tag"
++ DSP_OVERLAY_END, // Notify host that page overlay has ended - overlay number indicated by "tag"
++ DSP_CRATES1, // CRATES1 message is valid and should be copied to host memory now
++ DSP_SNR, // SNR calculations are ready and should be copied to host memory now
++ DSP_GHSMSG, // G.hs - FOR INTERNAL USE ONLY
++ DSP_RCVBITSWAP_TIMEOUT, // Acknowledge Message was not received within ~500 msec (26 Superframes).
++ DSP_ATM_TC_SYNC, // Indicates true TC sync on both the upstream and downstream. Phy layer ready for data xfer.
++ DSP_ATM_NO_TC_SYNC, // Indicates loss of sync on phy layer on either US or DS.
++ DSP_HYBRID, // DSP completed hybrid switch
++ DSP_RJ11SELECT, // DSP completed RJ11 inner/outer pair select
++ DSP_INVALID_CMD, // Manufacturing (Digital and AFE) diags: CMD received not recognized
++ DSP_TEST_PASSED, // Manufacturing diags: test passed
++ DSP_TEST_FAILED, // Manufacturing diags: test failed
++ DSP_TXREVERB, // Manufacturing AFE diags: Response to HOST_TXREVERB
++ DSP_TXMEDLEY, // Manufacturing AFE diags: Response to HOST_TXMEDLEY
++ DSP_RXNOISEPOWER, // Manufacturing AFE diags: Response to HOST_RXNOISEPOWER
++ DSP_ECPOWER, // Manufacturing AFE diags: Response to HOST_ECPOWER
++ DSP_ALL_ADIAG, // Manufacturing AFE diags: Response to HOST_ALL_ADIAG
++ DSP_USER_ADIAG, // Manufacturing AFE diags: Response to HOST_USER_ADIAG
++ DSP_QUIT_ADIAG, // Manufacturing AFE diags: Response to HOST_QUIT_ADIAG
++ DSP_DGASP, // DSP Message to indicate dying gasp
++ DSP_EOC, // DSP Message to indicate that DSP sent an EOC message to CO
++ DSP_TRAINING_MSGS // DSP Message to indicate that host has to copy the training message specified in the tag field.
++};
++
++// Define different ADSL training modes.
++//Defintions as per new host interface.
++#define NO_MODE 0
++#define GDMT_MODE 2
++#define GLITE_MODE 4
++#define ADSL2_MODE 8
++#define ADSL2_DELT (ADSL2_MODE+1)
++#define ADSL2PLUS_MODE 16
++#define ADSL2PLUS_DELT (ADSL2PLUS_MODE+1)
++#define READSL2_MODE 32
++#define READSL2_DELT (READSL2_MODE+1)
++#define T1413_MODE 128
++#define MULTI_MODE 255 // all possible bits are set in the bit field
++
++// Define the reason for dropping the connection
++
++enum
++{
++ REASON_LOS = 0x01,
++ REASON_DYING_GASP = 0x02,
++ REASON_USCRCERR = 0x04,
++ REASON_MARGIN_DROP = 0x08
++};
++
++
++// ----------------------------------------------------
++// Begin modem state bit field definitions - DSP write.
++// ----------------------------------------------------
++
++// BitField1 for initial states and G.hs states.
++// If more values need to be added, they will be added at the end (up to 32 total entries). However, if this causes
++// the state transitions to tick off out of normal bit order, then the C code will have to be re-written
++// that causes the proper values to be entered into the modem state bit fields.
++typedef enum
++{
++ ZERO_STATE1 = 0,
++ RTEST = 0x1,
++ RIDLE = 0x2,
++ RINIT = 0x4,
++ RRESET = 0x8,
++ GNSFLR = 0x10,
++ GTONE = 0x20,
++ GSILENT = 0x40,
++ GNEGO = 0x80,
++ GFAIL = 0x100,
++ GACKX = 0x200,
++ GQUIET2 = 0x400
++} DEV_HOST_stateBitField1_t; // this enum should only have 32 bit entries in it. Add another enum if you need more.
++
++// BitField2 for T1.413 states and for the rest of the modem states (so far)
++// If more values need to be added, they will be added at the end (up to 32 total entries). However, if this causes
++// the state transitions to tick off out of normal bit order, then the C code will have to be re-written
++// that causes the proper values to be entered into the modem state bit fields.
++typedef enum
++{
++ ZERO_STATE2 = 0,
++ TNSFLR = 0x1,
++ TACTREQ = 0x2,
++ TACTMON = 0x4,
++ TFAIL = 0x8,
++ TACKX = 0x10,
++ TQUIET2 = 0x20,
++ RQUIET2 = 0x40,
++ RREVERB1 = 0x80,
++ RQUIET3 = 0x100,
++ RECT = 0x200,
++ RREVERB2 = 0x400,
++ RSEGUE1 = 0x800,
++ RREVERB3 = 0x1000,
++ RSEGUE2 = 0x2000,
++ RRATES1 = 0x4000,
++ RMSGS1 = 0x8000,
++ RMEDLEY = 0x10000,
++ RREVERB4 = 0x20000,
++ RSEGUE3 = 0x40000,
++ RMSGSRA = 0x80000,
++ RRATESRA = 0x100000,
++ RREVERBRA = 0x200000,
++ RSEGUERA = 0x400000,
++ RMSGS2 = 0x800000,
++ RRATES2 = 0x1000000,
++ RREVERB5 = 0x2000000,
++ RSEGUE4 = 0x4000000,
++ RBNG = 0x8000000,
++ RREVERB6 = 0x10000000,
++ RSHOWTIME = 0x20000000
++} DEV_HOST_stateBitField2_t; // this enum should only have 32 bit entries in it. Add another enum if you need more.
++
++// BitField3 for ADSL2 states
++// If more values need to be added, they will be added at the end (up to 32 total entries). However, if this causes
++// the state transitions to tick off out of normal bit order, then the C code will have to be re-written
++// that causes the proper values to be entered into the modem state bit fields.
++typedef enum
++{
++ ZERO_STATE3 = 0,
++ G2QUIET1 = 0x1,
++ G2COMB1 = 0x2,
++ G2QUIET2 = 0x4,
++ G2COMB2 = 0x8,
++ G2ICOMB1 = 0x10,
++ G2LINEPROBE = 0x20,
++ G2QUIET3 = 0x40,
++ G2COMB3 = 0x80,
++ G2ICOMB2 = 0x100,
++ G2RMSGFMT = 0x200,
++ G2RMSGPCB = 0x400,
++ G2REVERB1 = 0x800,
++ G2QUIET4 = 0x1000,
++ G2REVERB2 = 0x2000,
++ G2QUIET5 = 0x4000,
++ G2REVERB3 = 0x8000,
++ G2ECT = 0x10000,
++ G2REVERB4 = 0x20000,
++ G2SEGUE1 = 0x40000,
++ G2REVERB5 = 0x80000,
++ G2SEGUE2 = 0x100000,
++ G2RMSG1 = 0x200000,
++ G2MEDLEY = 0x400000,
++ G2EXCHANGE = 0x800000,
++ G2RMSG2 = 0x1000000,
++ G2REVERB6 = 0x2000000,
++ G2SEGUE3 = 0x4000000,
++ G2RPARAMS = 0x8000000,
++ G2REVERB7 = 0x10000000,
++ G2SEGUE4 = 0x20000000
++} DEV_HOST_stateBitField3_t; // this enum should only have 32 bit entries in it. Add another enum if you need more.
++
++// BitField4 for ADSL2 diag. states
++// If more values need to be added, they will be added at the end (up to 32 total entries). However, if this causes
++// the state transitions to tick off out of normal bit order, then the C code will have to be re-written
++// that causes the proper values to be entered into the modem state bit fields.
++typedef enum
++{
++ ZERO_STATE4 = 0,
++ GDSEGUE1 = 0x1,
++ GDREVERB5 = 0x2,
++ GDSEGUE2 = 0x4,
++ GDEXCHANGE = 0x8,
++ GDSEGUELD = 0x10,
++ GDRMSGLD = 0x20,
++ GDQUIET1LD = 0x40,
++ GDQUIET2LD = 0x80,
++ GDRACK1 = 0x100,
++ GDRNACK1 = 0x200,
++ GDQUIETLAST = 0x400
++} DEV_HOST_stateBitField4_t; // this enum should only have 32 bit entries in it. Add another enum if you need more.
++
++// This struct collects all of the bitfield types listed above for the modem state bit field(s)
++typedef struct
++{
++ DEV_HOST_stateBitField1_t bitField1; // this is the first modem state bit field (mostly init. and G.hs)
++ DEV_HOST_stateBitField2_t bitField2; // this is the second modem state bit field (T1.413 and G.dmt)
++ DEV_HOST_stateBitField3_t bitField3; // this is the third modem state bit field (ADSL2)
++ DEV_HOST_stateBitField4_t bitField4; // this is the fourth modem state bit field (ADSL2 diag.)
++} DEV_HOST_modemStateBitField_t;
++
++
++// -----------------------------------------------
++// Begin NegoPara message definitions - DSP write.
++// -----------------------------------------------
++
++typedef struct
++{
++ UINT8 trainMode; // Train mode selected. See training modes defined above.
++ UINT8 bDummy1; // dummy byte for explicit 32-bit alignment
++ UINT16 lineLength; // Contains loop length estimate. Accuracy w/i 500 ft. LSbit = 1 for straight loop, = 0 for bridge tap
++ UINT32 atucVendorId; // Pass the vendor id of the CO to the host
++ UINT8 cMsgs1[8]; // CMsgs1 and CMSGPCB
++ UINT16 adsl2DSRate; //
++ UINT8 cRates2; //
++ UINT8 rRates2; //
++ UINT8 rRates1[4][11]; //
++ UINT8 cMsgs2[4]; //
++ UINT8 cRates1[4][30]; //
++ UINT8 rMsgs2[4]; //
++ UINT16 adsl2USRate; //
++ UINT8 atucGhsRevisionNum; // Pass the G.hs Revision number of the CO to the host
++ UINT8 reserved1; //
++ PUINT8 *adsl2DeltMsgs_p; // This pointer to a pointer passes the address of the globalvar.pString, which is also
++ // a pointer list of pointers. It will be used to pass all the new ADSL2 DELT messages to
++ // host side. This is for ACT.
++} DEV_HOST_dspWrNegoParaDef_t;
++
++
++// ----------------------------------------------------
++// Begin OAM NegoPara message definitions - Host write.
++// ----------------------------------------------------
++
++// OAM Feature bit fields.
++//
++// Bit 0 - Enable auto retrain of modem
++// Bit 1 - Detect and report TC sync to host
++// Bit 2-31 - Reserved
++
++#define DEV_HOST_AUTORETRAIN_ON 0x00000001
++#define DEV_HOST_TC_SYNC_DETECT_ON 0x00000002
++
++#define DEV_HOST_AUTORETRAIN_MASK 0x00000001
++#define DEV_HOST_TC_SYNC_DETECT_MASK 0x00000002
++#define DEV_HOST_EOCAOC_INTERRUPT_MASK 0x00000004
++#define DEV_HOST_CONS_DISP_DISABLE_MASK 0x00000008
++#define DEV_HOST_GHSMSG_INTERRUPT_MASK 0x00000010
++
++typedef struct
++{
++ UINT8 stdMode; // Desired train mode. See training modes defined above.
++ UINT8 ghsSequence; // Selected G.hs session as shown in Appendix 1
++ UINT8 usPilotFlag; // Value of 1 indicates transmit an upstream pilot on bin 16
++ UINT8 bDummy1; // dummy byte for 32-bit alignment
++ UINT8 rMsgs1[38]; // RMSG-1(6) and RMSG_PCB (38)
++ UINT8 bDummy2[2]; // dummy bytes for 32-bit alignment
++ UINT32 oamFeature; // 32 bit wide bit field to set OAM-specific features.
++ SINT8 marginThreshold; // Threshold for margin reporting
++ UINT8 hostFixAgc; // flag to force datapump to bypass AGC training and use the following values
++ UINT8 hostFixEqualizer; // forced analog equalizer value used during AGC training when hostfix_agc is on
++ UINT8 hostFixPga1; // forced pga1 value used during AGC training when hostFixAgc is on
++ UINT8 hostFixPga2; // forced pga2 value used during AGC training when hostFixAgc is on
++ UINT8 hostFixPga3; // forced pga3 value used during AGC training when hostFixAgc is on
++ UINT8 marginMonitorShwtme; // margin monitoring flag (during showtime)
++ UINT8 marginMonitorTrning; // margin monitoring flag (during training)
++ UINT8 disableLosAlarm; // flag to disable training based on los
++ UINT8 usCrcRetrain; // flag to disable retrain due to excessive USCRC
++ UINT8 t1413VendorId[2]; // Vendor ID used for T1.413 trainings
++ UINT8 gdmtVendorId[8]; // Vendor ID used for G.dmt trainings (ITU VendorID)
++ UINT8 missingTones[64]; // 64 element array to define missing tones for TX_MEDLEY and TX REVERB tests
++ UINT32 missingToneDsAddr; // Address given to DSP for tones to be switched off in DS direction
++ UINT8 dsToneTurnoff_f; // This flag controls the DS tone turn off logic
++ UINT8 reserved1; // Dummy bytes
++ UINT8 reserved2; // Dummy bytes
++ UINT8 reserved3; // Dummy bytes
++} DEV_HOST_oamWrNegoParaDef_t;
++
++
++// ----------------------------------------
++// Begin Rate-adaptive message definitions.
++// ----------------------------------------
++
++// The four values below can never be changed (for host intf. backwards compatibility)
++#define DEV_HOST_RMSGSRA_LENGTH 10
++#define DEV_HOST_RRATESRA_LENGTH 1
++#define DEV_HOST_CRATESRA_LENGTH 120
++#define DEV_HOST_CMSGSRA_LENGTH 6
++
++typedef struct
++{
++ UINT8 rRatesRaString[DEV_HOST_RRATESRA_LENGTH+3];
++ UINT8 rMsgsRaString[DEV_HOST_RMSGSRA_LENGTH+2];
++ UINT8 cMsgsRaString[DEV_HOST_CMSGSRA_LENGTH+2];
++} DEV_HOST_raMsgsDef_t;
++
++
++// ----------------------------------------------
++// Begin superframe cnts definitions - DSP write.
++// ----------------------------------------------
++
++#define DEV_HOST_FRAMES_PER_SUPER 68
++#define DEV_HOST_SUPERFRAMECNTDSTRM 0
++#define DEV_HOST_SUPERFRAMECNTUSTRM 4
++
++// Although only the least significant 8 bits should be used as an
++// unsigned char for computing the bitswap superframe number, a
++// full 32 bit counter is provided here in order to have an
++// accurate indicator of the length of time that the modem has
++// been connected. This counter will overflow after 2.35 years
++// of connect time.
++
++typedef struct
++{
++ UINT32 wSuperFrameCntDstrm;
++ UINT32 wSuperFrameCntUstrm;
++} DEV_HOST_dspWrSuperFrameCntDef_t;
++
++
++// --------------------------------
++// Begin ATUR/ATUC msg definitions.
++// --------------------------------
++
++// Grouping used by the DSP to simplify parameter passing.
++// All of these are written by the DSP.
++
++typedef struct
++{
++ UINT16 vendorId; // TI's vendor ID = 0x0004; Amati's vendor ID = 0x0006
++ UINT8 versionNum; // T1.413 issue number
++ UINT8 rateAdapt; // 0 = fix rate (Default); 1= adaptive rate
++ UINT8 trellis; // 0 = disable trellis(default); 1 = enable trellis
++ UINT8 echoCancelling; // 0 = disable echo cancelling; 1 = enable echo cancelling(default)
++ UINT8 maxBits; // value range: 0-15; default = 15
++ UINT8 maxPsd; //
++ UINT8 actualPsd; //
++ UINT8 maxIntlvDepth; // 0, 1, 2, or 3 for 64, 128, 256, or 512 max depth
++ UINT8 framingMode; // 0 for asynchronous, 1 for synchronous full overhead
++ // 2 for reduced overhead, 3 for merged reduced overhead DSP write.
++ UINT8 maxFrameMode; // maximum framing mode desired. Nor 0 or 3.
++ SINT16 targetMargin; //
++ SINT16 maxAllowedMargin; //
++ SINT16 minRequiredMargin; //
++ SINT16 maxTotBits; //
++ UINT8 grossGain; //
++ UINT8 ntr; // Enable/disable NTR support
++ SINT16 loopAttn; // Loop Attenuation
++ UINT8 vendorRevisionNumber; // Reported Vendor Revision Number
++ UINT8 reserved1; // for 32-bit alignment
++ UINT8 reserved2; // for 32-bit alignment
++ UINT8 reserved3; // for 32-bit alignment
++} DEV_HOST_msg_t;
++
++
++// --------------------------------------
++// Begin bits and gains table definitions
++// --------------------------------------
++
++typedef struct
++{
++ PUINT8 aturBng_p; // pointer to ATU-R bits and gains table
++ PUINT8 atucBng_p; // pointer to ATU-C bits and gains table
++ PUINT8 bitAllocTblDstrm_p; // pointer to Downstream Bit Allocation table
++ PUINT8 bitAllocTblUstrm_p; // pointer to Upstream Bit Allocation table
++ PSINT8 marginTblDstrm_p; // pointer to Downstream Margin table
++} DEV_HOST_dspWrSharedTables_t;
++
++
++// ----------------------------------------
++// Begin datapump code overlay definitions.
++// ----------------------------------------
++
++#define DEV_HOST_PAGE_NUM 4 // number of overlay pages
++
++// Never access a struct of this typedef directly. Always go through the DEV_HOST_olayDpDef_t struct
++typedef struct
++{
++ UINT32 overlayHostAddr; // source address in host memory
++ UINT32 overlayXferCount; // number of 32bit words to be transfered
++ UINT32 overlayDspAddr; // destination address in DSP's PMEM
++} DEV_HOST_olayDpPageDef_t;
++
++
++typedef struct
++{
++ UINT32 overlayStatus; // Status of current overlay to DSP PMEM
++ UINT32 overlayNumber; // DSP PMEM overlay page number
++ UINT32 overlayState; // Indicates whether current state is an overlay state
++ DEV_HOST_olayDpPageDef_t *olayDpPage_p[DEV_HOST_PAGE_NUM]; // Def's for the Pages
++} DEV_HOST_olayDpDef_t;
++
++
++// -------------------------
++// Begin ATM-TC definitions.
++// -------------------------
++
++// TC cell states.
++typedef enum
++{
++ TC_HUNT,
++ TC_PRESYNC,
++ TC_SYNC
++} DEV_HOST_cellDelinState_t;
++
++
++// --------------------------------------------
++// Begin datapump error/statistics definitions.
++// --------------------------------------------
++
++// Never access a struct of this typedef directly. Always go through the DEV_HOST_modemStatsDef_t struct.
++typedef struct
++{
++ UINT32 crcErrors; // Num of CRC errored ADSL frames
++ UINT32 fecErrors; // Num of FEC errored (corrected) ADSL frames
++ UINT32 ocdErrors; // Out of Cell Delineation
++ UINT32 ncdError; // No Cell Delineation
++ UINT32 lcdErrors; // Loss of Cell Delineation (within the same connection)
++ UINT32 hecErrors; // Num of HEC errored ADSL frames
++} DEV_HOST_errorStats_t;
++
++
++typedef struct
++{
++ DEV_HOST_errorStats_t *usErrorStatsIntlv_p; // us error stats - interleave path
++ DEV_HOST_errorStats_t *dsErrorStatsIntlv_p; // ds error stats - interleave path
++ DEV_HOST_errorStats_t *usErrorStatsFast_p; // us error stats - fast path
++ DEV_HOST_errorStats_t *dsErrorStatsFast_p; // ds error stats - fast path
++ UINT32 losErrors; // Num of ADSL frames where loss-of-signal
++ UINT32 sefErrors; // Num of severly errored ADSL frames - LOS > MAXBADSYNC ADSL frames
++ UINT32 farEndLosErrors; // Number of reported LOS defects by the CO.
++ UINT32 farEndRdiErrors; // Number of reported RDI defects by the CO.
++} DEV_HOST_modemStatsDef_t;
++
++// Never access a struct of this typedef directly. Always go through the DEV_HOST_atmStats_t struct.
++typedef struct
++{
++ UINT32 goodCount; // Upstream Good Cell Count
++ UINT32 idleCount; // Upstream Idle Cell Count
++} DEV_HOST_usAtmStats_t;
++
++// Never access a struct of this typedef directly. Always go through the DEV_HOST_atmStats_t struct.
++typedef struct
++{
++ UINT32 goodCount; // Downstream Good Cell Count
++ UINT32 idleCount; // Downstream Idle Cell Count
++ UINT32 badHecCount; // Downstream Bad Hec Cell Count
++ UINT32 ovflwDropCount; // Downstream Overflow Dropped Cell Count
++ DEV_HOST_cellDelinState_t delineationState; // Indicates current delineation state
++} DEV_HOST_dsAtmStats_t;
++
++
++typedef struct
++{
++ DEV_HOST_usAtmStats_t *us0_p; // US ATM stats for TC channel 0
++ DEV_HOST_dsAtmStats_t *ds0_p; // DS ATM stats for TC channel 0
++ DEV_HOST_usAtmStats_t *us1_p; // US ATM stats for TC channel 1
++ DEV_HOST_dsAtmStats_t *ds1_p; // DS ATM stats for TC channel 1
++} DEV_HOST_atmStats_t;
++
++
++// ----------------------
++// Begin EOC definitions.
++// ----------------------
++
++// The two values below can never change (for backwards compatibility of host intf.)
++#define DEV_HOST_EOCREG4LENGTH 32
++#define DEV_HOST_EOCREG5LENGTH 32
++
++typedef struct
++{
++ UINT8 eocReg4[DEV_HOST_EOCREG4LENGTH]; // Host/Dsp Write, vendor specific EOC Register 4
++ UINT8 eocReg5[DEV_HOST_EOCREG5LENGTH]; // Host/Dsp Write, vendor specific EOC Register 5
++ UINT8 vendorId[8]; // Host write
++ UINT8 revNumber[4]; // Host, ATU-R Revision Number
++ UINT8 serialNumber[32]; // Host write
++ UINT8 eocReg4Length; // Host Write, valid length for EOC register 4
++ UINT8 eocReg5Length; // Host Write, valid length for EOC register 5
++ UINT8 dummy[2]; // dummy bytes for 32-bit alignment
++ UINT32 eocModemStatusReg; // Dsp Write, status bits to host
++ UINT8 lineAtten; // Dsp Write, line attenuation in 0.5 db step
++ SINT8 dsMargin; // DSP Write, measured DS margin
++ UINT8 aturConfig[30]; // Dsp Write, also used by EOC for ATUR Configuration
++} DEV_HOST_eocVarDef_t;
++
++typedef struct
++{
++ UINT16 endEocThresh; // Host Write, end of Clear EOC stream threshold
++ UINT16 dummy; // dummy value to fill gap
++ UINT32 dropEocCount; // Dsp Write, counter of dropped Clear EOC bytes
++ UINT16 eocRxLength; // Host/DSP write, number of valid Rx Clear EOC bytes
++ UINT16 eocTxLength; // Host/DSP write, number of valid Tx Clear EOC bytes
++ UINT8 eocRxBuf[64]; // Dsp Write, Buffer for receiving Rx Clear EOC bytes
++ UINT8 eocTxBuf[64]; // Host Write, Buffer for writing Tx Clear EOC bytes
++} DEV_HOST_clearEocVarDef_t;
++
++
++// -----------------------------------
++// Begin CO profile Definitions.
++// -----------------------------------
++
++/* struct size must be a word size */
++typedef struct
++{
++
++ SINT16 devCodecRxdf4Coeff[12] ; // (BOTH) IIR Coefficients
++ SINT16 devCodecTxdf2aCoeff[64] ; // (BOTH) FIR filter coefficients
++ SINT16 devCodecTxdf2bCoeff[64] ; // (BOTH) FIR filter coefficients
++ SINT16 devCodecTxdf1Coeff[12] ; // (BOTH) IIR filter coefficients
++ UINT16 devCodecTxDf2aDen; // (BOTH) denominator for IIR filter
++ UINT16 devCodecTxDf2bDen; // (BOTH) denominator for IIR filter
++ SINT16 ctrlMsmSpecGain[32]; // (BOTH)
++
++ SINT16 phyBitaRateNegIntNoTrellis ; // (BOTH) value to set
++ SINT16 phyBitaRateNegIntTrellis ; // (BOTH) value to set
++ SINT16 phyBitaRateNegFastNoTrellis ; // (BOTH) value to set
++ SINT16 phyBitaRateNegFastTrellis ; // (BOTH) value to set
++ SINT16 phyBitaRsFlag ; // (BOTH)
++ SINT16 phyBitaFirstSubChannel ; // (BOTH)
++ SINT16 phyBitaMaxFineGainBump; // max fine gain bump
++ SINT16 phyBitaFineGainReduction; // fine gain reduction
++ SINT16 phyBitaMaxDownstreamPowerCutback; // max downstream power cutback
++
++ SINT16 phySigTxGainReductionAt0kft; // upstream power reduction at 0 kft.
++
++ SINT16 phyAgcPgaTarget ; // (BOTH) compare value
++
++ UINT16 imsg413TxRate ; // (BOTH) Tx rate
++ SINT16 imsg413RsBytesAdjust ; // (BOTH) subtract value
++ UINT16 imsg413PstringMask ; // (POTS) Or'ed into pString[RMSGS1_INDEX][1]
++ SINT16 imsg413UsPilot ; // (BOTH)??
++ UINT16 imsg413SkipPhaseOp ; // (POTS)
++
++ UINT16 ctrlMsmSensitivity1 ; // (BOTH) value to set
++ UINT16 ctrlMsmTxPsdShape_f; // (BOTH) upstream spectral shaping flag
++
++ UINT16 ovhdAocUsBswapReq_f ; // (BOTH)value to set
++ UINT16 ovhdAocScanMse_f ; // (BOTH)value to set
++
++ SINT16 phyRevFullFirstBin ; //
++ SINT16 phyRevFullLastBin ; //
++ SINT16 phyRevFirstBin ; //
++ SINT16 phyRevLastBin ; //
++ SINT16 phyMedFirstBin ; //
++ SINT16 phyMedLastBin ; //
++ SINT16 phyMedOptionalLastBin; // Medley last bin - optional
++
++ SINT16 phyEcDelayAdjustment; // Echo delay adjustment
++ SINT16 bSwapThresholdUpdate; // bSwapThresholdUpdate
++ SINT16 phyBitaFastPathExcessFineGainBump; // Used in phy_bita.c
++ SINT16 phyBitaSkipGapAdjustment; // Used in phy_bita.c
++ SINT16 usPilotInT1413ModeInMedley; // To send Upstream Pilot in medley in T1.413 mode.
++
++ UINT32 profileVendorId ; // vendor id
++
++} DEV_HOST_coData_t ;
++
++typedef struct
++{
++ DEV_HOST_coData_t * hostProfileBase_p; // base address of profile list
++} DEV_HOST_profileBase_t ;
++
++
++
++// -----------------------------------
++// Begin DSP/Host Mailbox Definitions.
++// -----------------------------------
++
++// The 3 values below can never be decreased, only increased.
++// If you increase one of the values, you must add more to the
++// initializers in "dev_host_interface.c".
++#define DEV_HOST_HOSTQUEUE_LENGTH 8
++#define DEV_HOST_DSPQUEUE_LENGTH 8
++#define DEV_HOST_TEXTQUEUE_LENGTH 8
++
++// Never access a struct of this typedef directly. Always go through the DEV_HOST_mailboxControl_t struct.
++typedef struct
++{
++ UINT8 cmd;
++ UINT8 tag;
++ UINT8 param1;
++ UINT8 param2;
++} DEV_HOST_dspHostMsg_t;
++
++// Never access a struct of this typedef directly. Always go through the DEV_HOST_mailboxControl_t struct.
++typedef struct
++{
++ UINT32 msgPart1;
++ UINT32 msgPart2;
++} DEV_HOST_textMsg_t;
++
++// The structure below has been ordered so that the Host need only write to
++// even byte locations to update the indices.
++
++// The Buffer pointers in the struct below each point to a different
++// struct array that has an array size of one of the matching Queue Length
++// values defined above (DEV_HOST_HOSTQUEUE_LENGTH, DEV_HOST_DSPQUEUE_LENGTH,
++// and DEV_HOST_TEXTQUEUE_LENGTH).
++
++typedef struct
++{
++ UINT8 hostInInx; // Host write, DSP must never write except for init
++ UINT8 bDummy0[3]; // dummy bytes for explicit 32-bit alignment
++ UINT8 hostOutInx; // DSP write, Host must never write
++ UINT8 bDummy1[3]; // dummy bytes for explicit 32-bit alignment
++ UINT8 dspOutInx; // Host write, DSP must never write except for init
++ UINT8 bDummy2[3]; // dummy bytes for explicit 32-bit alignment
++ UINT8 dspInInx; // DSP write, Host must never write
++ UINT8 bDummy3[3]; // dummy bytes for explicit 32-bit alignment
++ UINT8 textInInx; // DSP write, Host must never write
++ UINT8 bDummy4[3]; // dummy bytes for explicit 32-bit alignment
++ UINT8 textOutInx; // Host write, DSP must never write except for init
++ UINT8 bDummy5[3]; // dummy bytes for explicit 32-bit alignment
++ DEV_HOST_dspHostMsg_t *hostMsgBuf_p; // pointer to Host Mailbox Buffer (Host writes the buffer)
++ DEV_HOST_dspHostMsg_t *dspMsgBuf_p; // pointer to DSP Mailbox Buffer (DSP writes the buffer)
++ DEV_HOST_textMsg_t *textMsgBuf_p; // pointer to Text Mailbox Buffer (DSP writes the buffer)
++} DEV_HOST_mailboxControl_t;
++
++
++//-----------------------------------------
++// Physical layer performance parameter
++//-----------------------------------------
++typedef struct
++{
++ SINT32 hybridCost[5]; // Cost functions for hybrids (0: none, 1-4 hybrid options)
++ SINT32 usAvgGain; // upstream average gain in 20log10 (Q8)
++ SINT32 dsAvgGain; // downstream average gain in 20log10 (Q8)
++ UINT8 disableDspHybridSelect_f; // Allows host to disable the automatic hybrid selection by the DSP
++ UINT8 hostSelectHybridNum; // DSP will use this hybrid number only if DSP Select is disabled (values: 1-4)
++ UINT8 currentHybridNumUsed; // DSP indicates to the host the current hybrid number in use
++ UINT8 reserved1; // reserved for future use
++} DEV_HOST_phyPerf_t;
++
++
++/***********************************************************
++ * The 3 structures below are used only for analog
++ * diagnostic functions originally defined in diag.h
++ * Moved here by Carlos A. Perez under J. Bergsagel request
++ ***********************************************************/
++
++/****************************************************************************/
++/* Options for the Analog Diagnostic user input data structure */
++/* (MUST be word aligned) */
++/****************************************************************************/
++typedef enum
++{
++ ZERO_DIAG_OPT = 0, // dummy value for zero place-holder
++ NOISE_ONLY = 0x1, // diagnostic in noise only mode (on=1, off=0), disregard diagMode 0-4
++ EXTERNAL_CO = 0x2, // operates against external CO (external=1, internal=0)
++ DIAG_AGC = 0x4, // agc selects gains control (agc=1, manual=0)
++ CROSSTALK_TEQ = 0x8, // crosstalk selects teq (crosstalk=1, manual=0)
++ LEAKY_TEQ = 0x10, // use leaky teq (on=1, off=0)
++ AUX_AMPS = 0x20, // auxamps (on=1, off=0)
++ BW_SELECT = 0x40, // change rxhpf/txlpf fc (modify=1, default=0)
++ DIAG_HYB_SELECT = 0x80, // change hybrid (modify=1, default=0)
++ POWER_DOWN_CDC = 0x100, // power down codec (power down=1, no power down=0)
++ ISDN_OP_MODE = 0x200, // operation mode (pots=0, isdn=1)
++ BYPASS_RXAF2 = 0x400, // Bypass except RXAF2 (on=1, off = 0)
++ TX_TEST_CONT = 0x800, // Continuous tx test (on=1, off=0)
++ TX_SCALE_MTT = 0x1000 // Scale tx signal for Mtt test (on=1, off=0)
++} DEV_HOST_diagAnlgOptionsVar_t;
++
++/****************************************************************************/
++/* Analog Diagnostic user input data structure (MUST be word align) */
++/****************************************************************************/
++
++typedef struct
++{
++ DEV_HOST_diagAnlgOptionsVar_t diagOption; // Other diagnostic optional settings
++
++ UINT8 diagMode; // Performance diagnostic mode
++ UINT8 txMode; // transmit mode
++ UINT8 rxMode; // receive mode
++ UINT8 teqSp; // Select teq starting pt
++ UINT8 txDf1; // see dev_codec_filters.c and
++ UINT8 txDf2a; // dev_codec.h for filter coefficients
++ UINT8 txDf2b;
++ UINT8 rxDf4;
++
++ UINT16 codingGain256Log2; // 256*Log2(coding gain)
++ UINT16 noiseMargin256Log2; // 256*Log2(noise margin)
++
++ UINT16 rxPga1; // PGA1
++ UINT16 rxPga2; // PGA2
++ UINT16 rxPga3; // PGA3
++ UINT16 anlgEq; // AEQ settings (dB/MHz)
++
++ SINT8 pilotBin; // Select pilot subchannel
++ SINT8 txSwGain; // manual set for bridge tap loop
++ SINT8 tdw1Len; // TDW1 length - 0,2,4,8,16
++ SINT8 tdw2Len; // TDW2 length - 0,2,4,8,16
++
++ UINT8 teqEcMode; // TEQ/EC mode
++ UINT8 hybrid;
++ UINT8 txAttn; // Codec Tx attenuation
++ UINT8 txGain; // Codec Tx gain (Sangam only)
++
++ SINT16 txPda; //Codec Tx Digital gain/attn
++ UINT8 txTone[MAX_NUM_UPBINS]; // Turning tones on/off
++ // Still govern by lastbin
++ UINT16 rsvd; //for 32 bits alignment
++}DEV_HOST_diagAnlgInputVar_t;
++
++/****************************************************************************/
++/* Analog diagnostic output data structure */
++/****************************************************************************/
++typedef struct
++{
++ PSINT32 rxSnr_p[2]; // Pointer to estimated snr
++ PSINT32 rxSubChannelCapacity_p[2]; // Pointer to estimated subchan capacity
++ PSINT32 rxSignalPower_p[2]; // Pointer to estimated signal power
++ PSINT32 rxNoisePower_p[2]; // Pointer to estimated noise power
++ PSINT32 rxAvg_p; // Pointer to average of rcvd signal
++ SINT32 chanCapacity[2] ; // Channel total capacity
++ SINT32 dataRate[2]; // Modem data rate (SNR)
++ SINT32 avgNoiseFloor; // Average noise floor
++ SINT16 snrGap256Log2; // 256*Log2(snr gap)
++ SINT16 rxPga1; // PGA1
++ SINT16 rxPga2; // PGA2
++ SINT16 rxPga3; // PGA3
++ SINT16 anlgEq; // AEQ settings (dB/MHz)
++ SINT16 rsvd;
++}DEV_HOST_diagAnlgOutputVar_t;
++
++
++// Bit field structure that allows the host to mask off interrupt sources for possible DSP-to-Host interrupts.
++// Each bit represents a possible source of interrupts in the DSP code that might cause a DSP-to-Host
++// interrupt to occur.
++// This mask structure is not intended to show how interrupt sources in the DSP code correspond to the actual
++// DSP-to-Host interrupts. There could be multiple ways to cause an interrupt in the DSP code, but they all
++// eventually tie into one of the three possible DSP-to-Host interrupts.
++// The host should write a "1" to an individual bit when it wants to mask possible interrupts from that source.
++
++// enum that represents individual bits in maskBitField1
++typedef enum
++{
++ ZERO_MASK1 = 0, // dummy value for zero place-holder
++ DSP_MSG_BUF = 0x1, // mask interrupts due to DSP-to-Host message mailbox updates
++ STATE_BIT_FIELD = 0x2, // mask interrupts due to changes in the modem state bit fields
++ DSP_HEARTBEAT = 0x4 // mask interrupts for the DSP hearbeat
++} DEV_HOST_intMask1_t; // this enum should only have 32 values in it (maximum).
++
++// Add more "mask bit fields" at the end of this struct if you need more mask values
++typedef struct
++{
++ DEV_HOST_intMask1_t maskBitField1;
++} DEV_HOST_hostInterruptMask_t; // this struct should only have 32 bits in it.
++
++// Bit field structure that allows the host to determine the source(s) of DSP-to-Host interrupts in case
++// several of the interrupt sources get combined onto a single DSP-to-Host interrupt.
++// DSP will set each bit to a "1"as an interrupt occurs.
++// Host has the reponsibility to clear each bit to a "0" after it has determined the source(s) of interrupts.
++// Each source bit field in this struct will use the same enum typedef that matches the corresponding mask
++// bit field in "DEV_HOST_hostInterruptMask_t"
++typedef struct
++{
++ DEV_HOST_intMask1_t sourceBitField1;
++} DEV_HOST_hostInterruptSource_t;
++
++
++// --------------------------
++// Begin bitswap definitions.
++// --------------------------
++
++// bitSwapSCnt contains the superframe to perform bit swap
++// The entries must be ordered so that the first group only contains bit change commands
++// The other entries may contain power adjustment instructions and must be
++// written with something. NOP (0) is an available instruction.
++typedef struct
++{
++ PUINT8 fineGains_p; // pointer to bng string, needed to check fine gains for powerswap
++ UINT8 bitSwapNewIndices[6]; // Bin before bitSwapBin to process
++ UINT8 bitSwapCmd[6]; // Bitswap command for bitSwapBin
++ UINT8 bitSwapBin[6]; // bin to modify
++ UINT8 bitSwapSCnt; // Superframe count on which to perform bitswap
++ UINT8 bitSwapEnabled; // bitSwapEnabled
++} DEV_HOST_dspBitSwapDef_t;
++
++
++// ---------------------------
++// Begin ATM BERT definitions.
++// ---------------------------
++
++// Structure used for ATM Idle Cells based bit error rate computation.
++typedef struct
++{
++ UINT8 atmBertFlag; // Feature enable/disable flag (Host write)
++ UINT8 dummy1;
++ UINT8 dummy[2]; // Dummy bytes for 32-bit alignment
++ UINT32 bitCountLow; // Low part of 64-bit BERT bit count (DSP write)
++ UINT32 bitCountHigh; // High part of 64-bit BERT bit count (DSP write)
++ UINT32 bitErrorCountLow; // Low part of 64-bit BERT bit count (DSP write)
++ UINT32 bitErrorCountHigh;// High part of 64-bit BERT bit count (DSP write)
++} DEV_HOST_atmDsBert_t;
++
++
++// ------------------------------------
++// Misc. modem environment definitions.
++// ------------------------------------
++
++
++typedef struct
++{
++ SINT16 subStateIndex; // Index that signifies datapump substate. (DSP write)
++ UINT8 externalBert; // Turn on/off external BERT interface. 0 = OFF; 1 = ON. (Host write)
++ UINT8 usBertPattern; // BERT pattern for US TX data. 0 = 2^15-1; 1 = 2^23-1. (Host write)
++ UINT8 overrideDslLinkLed_f; // Overrides DSP operation of the DSL_LINK LED. (Host write)
++ // 0 = DSP is in control; 1 = Host is in control.
++ UINT8 dslLinkLedState_f; // DSL_LINK LED state when override flag has been set. (Host write)
++ // DSL_LINK LED will be updated with this value once per frame.
++ // LED is active-low: 0 = ON, 1 = OFF.
++ UINT8 overrideDslActLed_f; // Overrides DSP operation of the DSL_ACT LED. (Host write)
++ // 0 = DSP is in control; 1 = Host is in control.
++ UINT8 dslActLedState_f; // DSL_ACT LED state when override flag has been set. (Host write)
++ // DSL_ACT LED will be updated with this value once per frame.
++ // LED is active-low: 0 = ON, 1 = OFF.
++ UINT8 dGaspLprIndicator_f; // How LPR signal (GPIO[0]) is to be interpreted. (Host write)
++ // 0 = LPR is active-low; 1 = LPR is active-high.
++ UINT8 overrideDspLprGasp_f; // Overrides DSP detection of LPR signal to send out DGASP. (Host write)
++ // 0 = DSP detects LPR; 1 = Host detects LPR and sends "HOST_DGASP" to DSP.
++ UINT8 pcbEnabled; // DS power cut back
++ UINT8 maxAvgFineGainCtrl_f; // If maxAvgFineGainCtrl_f == 0, then the datapump controls the maximum average fine gain value.
++ // If maxAvgFineGainCtrl_f == 1, then the host controls the maximum average fine gain value.
++ UINT32 reasonForDrop; // This field will tell the host what might be the reason for a dropped connection.
++ SINT16 maxAverageFineGain; // When maxAvgFineGainCtrl_f == 1, the value in maxAverageFineGain is the maximum average fine gain level in 256log2 units.
++ UINT8 reserved1; // These are for 32-bit alignment.
++ UINT8 reserved2; // These are for 32-bit alignment.
++} DEV_HOST_modemEnvPublic_t;
++
++
++// -----------------------------
++// Generic structure definition.
++// -----------------------------
++
++typedef struct
++{
++ PSINT8 parameter1_p;
++ PSINT16 parameter2_p;
++ PSINT32 parameter3_p;
++ PUINT8 parameter4_p;
++ PUINT16 parameter5_p;
++ PUINT32 parameter6_p;
++} DEV_HOST_genericStructure_t;
++
++
++// ------------------------------
++// Begin G.hs buffer definitions.
++// ------------------------------
++
++typedef struct
++{
++ UINT8 txBuf[64]; // G.hs xmt buffer
++} DEV_HOST_ghsDspTxBufDef_t;
++
++
++typedef struct
++{
++ UINT8 rxBuf[80]; // G.hs rcv buffer
++} DEV_HOST_ghsDspRxBufDef_t;
++
++// -----------------------------------------
++// Begin Constellation Display definitions.
++// -----------------------------------------
++
++typedef struct
++{
++ UINT32 consDispStartAddr; // Host write
++ UINT32 consDispCurrentAddr; // Host write
++ UINT32 consDispBufLen; // Constellation Buffer Length
++ UINT32 consDispBin; // Host write, DS band only
++} DEV_HOST_consBufDef_t;
++
++typedef struct
++{
++ PSINT16 buffer1_p; //DSP write
++ PSINT16 buffer2_p; //DSP write
++} DEV_HOST_snrBuffer_t;
++
++// --------------------------------------------------------------------------------------
++// Typedef to be used for the DEV_HOST_dspOamSharedInterface_s struct of pointers
++// (this is used in dev_host_interface.c).
++// NOTE: This struct of pointers is NEVER to be referenced anywhere else in the DSP code.
++// IMPORTANT: Only pointers to other structs go into this struct !!
++// --------------------------------------------------------------------------------------
++typedef struct
++{
++ DEV_HOST_hostIntfcVersionDef_t *hostIntfcVersion_p;
++ DEV_HOST_dspVersionDef_t *datapumpVersion_p;
++ DEV_HOST_modemStateBitField_t *modemStateBitField_p;
++ DEV_HOST_dspWrNegoParaDef_t *dspWriteNegoParams_p;
++ DEV_HOST_oamWrNegoParaDef_t *oamWriteNegoParams_p;
++ DEV_HOST_raMsgsDef_t *raMsgs_p;
++ DEV_HOST_dspWrSuperFrameCntDef_t *dspWriteSuperFrameCnt_p;
++ DEV_HOST_msg_t *atucMsg_p;
++ DEV_HOST_msg_t *aturMsg_p;
++ DEV_HOST_dspWrSharedTables_t *dspWrSharedTables_p;
++ DEV_HOST_olayDpDef_t *olayDpParms_p;
++ DEV_HOST_eocVarDef_t *eocVar_p;
++ DEV_HOST_clearEocVarDef_t *clearEocVar_p;
++ DEV_HOST_modemStatsDef_t *modemStats_p;
++ DEV_HOST_atmStats_t *atmStats_p;
++ DEV_HOST_mailboxControl_t *dspHostMailboxControl_p;
++ DEV_HOST_phyPerf_t *phyPerf_p;
++ DEV_HOST_diagAnlgInputVar_t *analogInputVar_p;
++ DEV_HOST_diagAnlgOutputVar_t *analogOutputVar_p;
++ DEV_HOST_hostInterruptMask_t *hostInterruptMask_p;
++ DEV_HOST_profileBase_t *profileList_p;
++ DEV_HOST_hostInterruptSource_t *hostInterruptSource_p;
++ DEV_HOST_dspBitSwapDef_t *dspBitSwapDstrm_p;
++ DEV_HOST_dspBitSwapDef_t *dspBitSwapUstrm_p;
++ DEV_HOST_atmDsBert_t *atmDsBert_p;
++ DEV_HOST_modemEnvPublic_t *modemEnvPublic_p;
++ DEV_HOST_genericStructure_t *genericStructure1_p;
++ DEV_HOST_genericStructure_t *genericStructure2_p;
++ DEV_HOST_ghsDspTxBufDef_t *ghsDspTxBuf_p;
++ DEV_HOST_ghsDspRxBufDef_t *ghsDspRxBuf_p;
++ DEV_HOST_consBufDef_t *consDispVar_p;
++ DEV_HOST_snrBuffer_t *snrBuffer_p;
++} DEV_HOST_dspOamSharedInterface_t;
++
++
++// ---------------------------------------------------------------------------------
++// Typedef to be used for the pointer to the DEV_HOST_dspOamSharedInterface_s struct
++// of pointers (this is used in dev_host_interface.c).
++// ---------------------------------------------------------------------------------
++typedef DEV_HOST_dspOamSharedInterface_t *DEV_HOST_dspOamSharedInterfacePtr_t;
++
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/dev_host_verdef.h linux.dev/drivers/atm/sangam_atm/dev_host_verdef.h
+--- linux.old/drivers/atm/sangam_atm/dev_host_verdef.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/dev_host_verdef.h 2005-08-23 04:46:50.091844608 +0200
+@@ -0,0 +1,102 @@
++#ifndef __DEV_HOST_VERDEF_H__
++#define __DEV_HOST_VERDEF_H__ 1
++
++//********************************************************************
++//*
++//* DMT-BASE ADSL MODEM PROGRAM
++//* TEXAS INSTRUMENTS PROPRIETARTY INFORMATION
++//* AMATI CONFIDENTIAL PROPRIETARY
++//*
++//* (c) Copyright April 1999, Texas Instruments Incorporated.
++//* All Rights Reserved.
++//*
++//* Property of Texas Instruments Incorporated and Amati Communications Corp.
++//*
++//* Restricted Rights - Use, duplication, or disclosure is subject to
++//* restrictions set forth in TI's and Amati program license agreement and
++//* associated documentation
++//*
++//*********************************************************************
++//*
++//* FILENAME: dev_host_verdef.h
++//*
++//* ABSTRACT: This file defines the version structure
++//*
++//* TARGET: Non specific.
++//*
++//* TOOLSET: Non specific.
++//*
++//* ACTIVATION:
++//*
++//* HISTORY: DATE AUTHOR DESCRIPTION
++//* 04/29/99 FLW Created
++//* 01/17/00 Barnett Mod's in support of merging NIC
++//* hardware rev 6/7 T1.413 codebases.
++//* 01/21/00 Wagner derfmake mods
++//* 05/11/00 Barnett hardware_rev is a 2 char string.
++//* 07/24/00 Barnett Rework as part of host interface redesign.
++//* 11/29/00 Hunt added chipset_id2
++//* 03/30/01 Barnett Prefixed all public elements with DSPDP_.
++//* This insures uniqueness of names that might
++//* match host names by coincidence.
++//* 03/30/01 Barnett Added DSPDP_Host_VersionDef to facilitate
++//* representing a version id for the host i/f
++//* separate from the firmware version id as
++//* a courtesy to the host.
++//* 07/23/01 JEB Changed name from verdef_u.h to dpsys_verdef.h
++//* 04/12/02 Barnett Make timestamp unsigned 32-bit field.
++//* Generalizes for all kinds of hosts.
++//* 11/15/02 JEB Changed name from dpsys_verdef.h to dev_host_verdef.h
++//* Updated structs according to coding guidelines
++//* 12/16/02 JEB Renamed some struct elements for new usage in Ax7
++//* 01/21/03 MCB Implemented Ax7 UNIT-MODULE modular software framework.
++//* 03/19/03 JEB Added back in "bugFix" elements into each struct type.
++//* Rearranged elements.
++//*
++//********************************************************************
++
++#include "env_def_typedefs.h"
++
++#define DSPDP_FLAVOR_NEWCODES 0xFF // Other values are valid old-style flavors
++
++// ------------------------------
++// ------------------------------
++// Begin DSP version definitions.
++// ------------------------------
++// ------------------------------
++
++typedef struct
++{
++ UINT32 timestamp; // Number of seconds since 01/01/1970
++ UINT8 major; // Major "00".00.00.00 revision nomenclature
++ UINT8 minor; // Minor 00."00".00.00 revision nomenclature
++ UINT8 bugFix; // Bug Fix 00.00."00".00 revision nomenclature
++ UINT8 buildNum; // Build Number 00.00.00."00" revision nomenclature
++ UINT8 netService; // Network service identifier
++ UINT8 chipsetGen; // chipset generation
++ UINT8 chipsetId; // chipset identifier
++ UINT8 chipsetId2; // second byte for "RV" chipset et al.
++ UINT8 hardwareRev1; // hardware revision, 1st char
++ UINT8 hardwareRev2; // hardware revision, 2nd char
++ UINT8 featureCode; // feature code
++ UINT8 dummy1; // dummy byte for explicit 32-bit alignment
++} DEV_HOST_dspVersionDef_t;
++
++// -------------------------------
++// -------------------------------
++// Begin host version definitions.
++// -------------------------------
++// -------------------------------
++
++typedef struct
++{
++ UINT8 major; // Major "00".00.00.00 revision nomenclature
++ UINT8 minor; // Minor 00."00".00.00 revision nomenclature
++ UINT8 bugFix; // Bug Fix 00.00."00".00 revision nomenclature
++ UINT8 buildNum; // Build Number 00.00.00."00" revision nomenclature
++ UINT8 netService; // Network service identifier
++ UINT8 dummy[3]; // dummy bytes for explicit 32-bit alignment
++} DEV_HOST_hostIntfcVersionDef_t;
++
++
++#endif // __DEV_HOST_VERDEF_H__
+diff -urN linux.old/drivers/atm/sangam_atm/dsl_hal_api.c linux.dev/drivers/atm/sangam_atm/dsl_hal_api.c
+--- linux.old/drivers/atm/sangam_atm/dsl_hal_api.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/dsl_hal_api.c 2005-08-23 04:46:50.095844000 +0200
+@@ -0,0 +1,3339 @@
++/*******************************************************************************
++* FILE PURPOSE: DSL Driver API functions for Sangam
++*
++********************************************************************************
++* FILE NAME: dsl_hal_basicapi.c
++*
++* DESCRIPTION:
++* Contains basic DSL HAL APIs for Sangam
++*
++*
++* (C) Copyright 2001-02, Texas Instruments, Inc.
++* History
++* Date Version Notes
++* 06Feb03 0.00.00 RamP Original Version Created
++* 10Mar03 0.00.01 RamP Initial Revision for Modular Code Branch
++* 19Mar03 0.00.02 RamP Fixed DSL and DSP Version API Structures
++* 20Mar03 0.00.03 RamP Changed byteswap function names
++* 21Mar03 0.00.03 RamP/ZT Malloc for DSP f/w done in dslStartup
++* 25Mar03 0.00.04 RamP Removed statistics used only by SWTC
++* Created Checkpoint 3
++* 26Mar03 0.00.05 RamP Added Memory allocation for fwimage in
++* dslStartup function.
++* 07Apr03 0.00.06 RamP Implemented new error reporting scheme
++* Changed Commenting to C style only
++* 09Apr03 0.00.07 RamP Reorganized code to delete POST_SILICON
++* 10Apr03 0.00.08 RamP Removed ptidsl from loadFWImage function
++* moved size and fwimage initialization to
++* dslStartup function
++* 14Apr03 0.00.09 RamP Moved modemStateBitField processing to a
++* support function; deleted stateHistory
++* renamed the REG32 macro
++* 15Apr03 0.00.10 RamP Changed firmware allocate to shim_
++* osAllocateVMemory function
++* 15Apr03 0.00.11 RamP Changed host version number to 07.00.00.01
++* 16Apr03 0.00.12 RamP Modified return condition on dslShutdown
++* 16Apr03 0.00.13 RamP Changed host version number to 07.00.00.02
++* 21Apr03 0.01.00 RamP Cleaned up dslShutdown function
++* Added new function calls to allocate
++* (Alpha) /free overlay pages for different OS
++* Fixed typecasting for allocate/free fxns
++* Added Interrupt Acknowledge logic
++* 22Apr03 0.01.01 RamP Moved acknowledgeInterrupt into api
++* Added static global for intr source
++* 24Apr03 0.01.02 RamP Added processing for OVERLAY_END in
++* DSP message handlers, verified crc32
++* recovery for overlays
++* 28Apr03 0.01.03 RamP Removed global variable intrSource
++* Added parameter to handleInterrupt fxn
++* (Alpha Plus) to indicate interrupt source
++* Changed version number to 01.00.01.00
++* Fixed setTrainingMode function problem
++* 07May03 0.01.04 RamP Removed delineation state check in
++* message handling functions, added more
++* safety for setting lConnected in TC_SYNC
++* Changed version number to 01.00.01.01
++* 14May03 0.01.05 RamP Added 3 Switchable Hybrid APIs
++* Added additional statistics us/ds TxPower,
++* us margin,attenuation, us/ds bitallocation
++* moved versioning to dsl_hal_version.h
++* 14May03 0.01.06 RamP Fixed problem with CMsgs2 parsing
++* 20May03 0.01.07 RamP Added Inner/Outer pair API support. Added
++* dying gasp message.
++* 29May03 0.01.08 ZT/RamP Added memory optimizations for overlay pages
++* and coProfiles; added functions to free,
++* reload overlays and profiles
++* 04Jun03 0.01.09 RamP Added tick counters, fail states reporting
++* Made statistics fixes for higher data rates
++* Added Margin per tone to statistics
++* Added configuration checks for trellis/FEC
++* 06Jun03 0.01.10 RamP Added LED, STM Bert, dGasp LPR Config APIs
++* Modified interrupt acknowledge logic
++* Added current hybrid flag as statistic
++* 09Jun03 0.01.11 RamP Added function to send dying Gasp to Modem
++* fixed problem with reading OamNegoPara var
++* (Beta) fixed problem with reading current config
++* Added function to configure ATM Bert
++* fixed memory leak due to coProfiles
++* Added us/ds R/S FEC statistics
++* Added additional config capability for LED
++* fixed problem in free memory for CO profiles
++* 18Jul03 0.01.12 RamP Fixed problem with reading modemEnv structure
++* affects LED, DGaspLpr APIs
++* Sending Dying Gasp from shutdown function
++* 01Aug03 0.01.13 RamP Added preferred training mode to statistics
++* 13Aug03 0.01.14 MCB Set rev id for D3/R1.1 (ADSL2).
++* 21Aug03 0.01.15 RamP Added g.hs and aoc bitswap message gathering
++* Added new references to bits n gains table
++* Decoupled modem idle/retrain from pair select
++* Added line length and gross gain to statistics
++* 29Sep03 0.01.16 RamP Replaced advcfg function calls with support
++* module function switches
++* 01Oct03 0.01.17 RamP Added enum translation to set training mode
++* & to read statistics
++* 08Oct03 0.01.18 RamP Fixed problems with usTxPower statistic in
++* Annex B target, fixed problem with Trellis
++* 12Oct03 0.01.19 RamP Added API calls to gather ADSL2 Messages
++* 29Oct03 0.01.20 RamP Restored TC_SYNC detect logic
++* 30Oct03 0.01.21 RamP Removed Scaling factor for adsl2DSConRate
++* Setting Showtime state upon DSP_ACTIVE
++* 14Nov03 0.01.22 RamP Fixed scaling for usTxPower & dsTxPower
++* 14Nov03 0.01.23 RamP Added logic to gather CRates1/RRates1
++* by parsing DSP_CRATES1
++* 20Nov03 0.01.24 RamP Added generic & interface Read
++* and Write functions to read from
++* DSP - Host Interface
++* 24Nov03 0.01.25 RamP Modified interface Read/Write functions
++* to seperate element offsets from pointers
++* 19Dec03 0.01.26 RamP Modified pointer accessing problems with
++* block read functions
++* 26Dec03 0.01.27 RamP Made ghsIndex a local variable & added
++* check to avoid buffer overflow
++* 30Dec03 0.01.28 RamP Added generic mailbox command function
++*******************************************************************************/
++#include "dsl_hal_register.h"
++#include "dsl_hal_support.h"
++#include "dsl_hal_logtable.h"
++#include "dsl_hal_version.h"
++
++static unsigned int hybrid_selected;
++static unsigned int showtimeFlag = FALSE;
++
++#ifdef PRE_SILICON
++/*********************************************/
++/* Base Addresses */
++/*********************************************/
++#define DEV_MDMA_BASE 0x02000500
++
++/*********************************************/
++/* MC DMA Control Registers in DSL */
++/*********************************************/
++
++#define DEV_MDMA0_SRC_ADDR (DEV_MDMA_BASE + 0x00000000)
++#define DEV_MDMA0_DST_ADDR (DEV_MDMA_BASE + 0x00000004)
++#define DEV_MDMA0_CTL_ADDR (DEV_MDMA_BASE + 0x00000008)
++#define DEV_MDMA1_SRC_ADDR (DEV_MDMA_BASE + 0x00000040)
++#define DEV_MDMA1_DST_ADDR (DEV_MDMA_BASE + 0x00000044)
++#define DEV_MDMA1_CTL_ADDR (DEV_MDMA_BASE + 0x00000048)
++#define DEV_MDMA2_SRC_ADDR (DEV_MDMA_BASE + 0x00000080)
++#define DEV_MDMA2_DST_ADDR (DEV_MDMA_BASE + 0x00000084)
++#define DEV_MDMA2_CTL_ADDR (DEV_MDMA_BASE + 0x00000088)
++#define DEV_MDMA3_SRC_ADDR (DEV_MDMA_BASE + 0x000000C0)
++#define DEV_MDMA3_DST_ADDR (DEV_MDMA_BASE + 0x000000C4)
++#define DEV_MDMA3_CTL_ADDR (DEV_MDMA_BASE + 0x000000C8)
++
++#define DEV_MDMA0_SRC (*((volatile UINT32 *) DEV_MDMA0_SRC_ADDR))
++#define DEV_MDMA0_DST (*((volatile UINT32 *) DEV_MDMA0_DST_ADDR))
++#define DEV_MDMA0_CTL (*((volatile UINT32 *) DEV_MDMA0_CTL_ADDR))
++#define DEV_MDMA1_SRC (*((volatile UINT32 *) DEV_MDMA1_SRC_ADDR))
++#define DEV_MDMA1_DST (*((volatile UINT32 *) DEV_MDMA1_DST_ADDR))
++#define DEV_MDMA1_CTL (*((volatile UINT32 *) DEV_MDMA1_CTL_ADDR))
++#define DEV_MDMA2_SRC (*((volatile UINT32 *) DEV_MDMA2_SRC_ADDR))
++#define DEV_MDMA2_DST (*((volatile UINT32 *) DEV_MDMA2_DST_ADDR))
++#define DEV_MDMA2_CTL (*((volatile UINT32 *) DEV_MDMA2_CTL_ADDR))
++#define DEV_MDMA3_SRC (*((volatile UINT32 *) DEV_MDMA3_SRC_ADDR))
++#define DEV_MDMA3_DST (*((volatile UINT32 *) DEV_MDMA3_DST_ADDR))
++#define DEV_MDMA3_CTL (*((volatile UINT32 *) DEV_MDMA3_CTL_ADDR))
++
++/* MDMA control bits */
++
++#define DEV_MDMA_START 0x80000000
++#define DEV_MDMA_STOP 0x00000000
++#define DEV_MDMA_STATUS 0x40000000
++#define DEV_MDMA_DST_INC 0x00000000
++#define DEV_MDMA_DST_FIX 0x02000000
++#define DEV_MDMA_SRC_INC 0x00000000
++#define DEV_MDMA_SRC_FIX 0x00800000
++#define DEV_MDMA_BURST1 0x00000000
++#define DEV_MDMA_BURST2 0x00100000
++#define DEV_MDMA_BURST4 0x00200000
++
++#define DEV_MDMA_LEN_SHF 2
++#define DEV_MDMA_LEN_MASK 0x0000FFFF
++
++#define DMA0 0
++#define DMA1 1
++#define DMA2 2
++#define DMA3 3
++#endif
++#ifdef DMA
++SINT32 getDmaStatus(UINT32 mask)
++{
++ if(!(IFR & mask))
++ {
++ return DSLHAL_ERROR_NO_ERRORS;
++ }
++ else
++ {
++ ICR = mask ;
++ return 1 ;
++ }
++}
++
++void programMdma(UINT32 dma, UINT32 source, UINT32 destination, UINT32 length, UINT32 wait)
++{
++ volatile UINT32 statusMask ;
++
++ switch(dma)
++ {
++ case DMA0:
++ {
++ DEV_MDMA0_SRC = source ;
++ DEV_MDMA0_DST = destination ;
++ DEV_MDMA0_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
++ DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
++ statusMask = 0x00000010 ;
++ }
++ break ;
++ case DMA1:
++ {
++ DEV_MDMA1_SRC = source ;
++ DEV_MDMA1_DST = destination ;
++ DEV_MDMA1_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
++ DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
++ statusMask = 0x00000020 ;
++ }
++ break ;
++ case DMA2:
++ {
++ DEV_MDMA2_SRC = source ;
++ DEV_MDMA2_DST = destination ;
++ DEV_MDMA2_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
++ DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
++ statusMask = 0x00000040 ;
++ }
++ break ;
++ case DMA3:
++ {
++ DEV_MDMA3_SRC = source ;
++ DEV_MDMA3_DST = destination ;
++ DEV_MDMA3_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
++ DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
++ statusMask = 0x00000080 ;
++ }
++ break ;
++
++ }
++
++ if(wait)
++ {
++ while(!(getDmaStatus(statusMask))) ;
++ }
++
++}
++#endif
++
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_dslStartup
++*
++*******************************************************************************************
++* DESCRIPTION: Entry point to initialize and load ax5 daughter board
++*
++* INPUT: PITIDSLHW_T *ppIHw
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++*
++*****************************************************************************************/
++
++int dslhal_api_dslStartup(PITIDSLHW_T *ppIHw)
++{
++
++ ITIDSLHW_T *ptidsl;
++ int i;
++ int rc;
++ dprintf(4,"dslhal_api_dslStartup() NEW 1\n");
++
++ ptidsl=(ITIDSLHW_T *)shim_osAllocateMemory(sizeof(ITIDSLHW_T));
++ if(ptidsl==NULL)
++ {
++ dprintf(1, "unable to allocate memory for ptidsl\n");
++ return 1;
++ }
++ *ppIHw=ptidsl;
++ shim_osZeroMemory((char *) ptidsl, sizeof(ITIDSLHW_T));
++
++ /* Unreset the ADSL Subsystem */
++ rc=dslhal_support_unresetDslSubsystem();
++ if(rc)
++ {
++ dprintf(1, "unable to reset ADSL Subsystem \n");
++ shim_osFreeMemory((void *) ptidsl, sizeof(ITIDSLHW_T));
++ return DSLHAL_ERROR_UNRESET_ADSLSS;
++ }
++ ptidsl->fwimage = shim_osAllocateVMemory(DSP_FIRMWARE_MALLOC_SIZE);
++ if(!ptidsl->fwimage)
++ {
++ dprintf(1,"Failed to Allocate Memory for DSP firmware binary \n");
++ return DSLHAL_ERROR_FIRMWARE_MALLOC;
++ }
++ /* read firmware file from flash */
++ rc=shim_osLoadFWImage(ptidsl->fwimage);
++ if(rc<0)
++ {
++ dprintf(1, "unable to get fw image\n");
++ shim_osFreeVMemory((void *)ptidsl->fwimage,DSP_FIRMWARE_MALLOC_SIZE);
++ shim_osFreeMemory((void *) ptidsl, sizeof(ITIDSLHW_T));
++ return DSLHAL_ERROR_NO_FIRMWARE_IMAGE;
++ }
++ else
++ {
++ ptidsl->imagesize = rc;
++ }
++ /* Compute the CRC checksum on the image and validate the image */
++
++ /* Validate the image in the RAM */
++
++ /* load fw to DSP */
++
++ if(dslhal_support_hostDspCodeDownload(ptidsl))
++ {
++ dprintf(0,"dsp load error\n");
++ for(i=0; i<NUM_PAGES; i++)
++ {
++ if(ptidsl->olayDpPage[i].PmemStartWtAddr !=NULL)
++ {
++ shim_osFreeDmaMemory((void *) ptidsl->olayDpPage[i].PmemStartWtAddr,
++ ptidsl->olayDpPage[i].OverlayXferCount);
++ }
++ }
++ if(ptidsl->coProfiles.PmemStartWtAddr != NULL)
++ shim_osFreeDmaMemory((void *)ptidsl->coProfiles.PmemStartWtAddr, ptidsl->coProfiles.OverlayXferCount);
++ if(ptidsl->constDisplay.PmemStartWtAddr != NULL)
++ shim_osFreeDmaMemory((void *)ptidsl->constDisplay.PmemStartWtAddr, ptidsl->constDisplay.OverlayXferCount);
++ shim_osFreeVMemory((void *)ptidsl->fwimage,DSP_FIRMWARE_MALLOC_SIZE);
++ shim_osFreeMemory((void *) ptidsl, sizeof(ITIDSLHW_T));
++ return DSLHAL_ERROR_CODE_DOWNLOAD;
++ }
++
++ /* set flag to indicated overlay pages are loaded */
++ ptidsl->bOverlayPageLoaded = 1;
++ /* set auto retrain to 1 to disble the overlay page reload */
++ ptidsl->bAutoRetrain = 1;
++
++ /* unreset Raptor */
++ /* change this to new function */
++ /* This function should basically bring DSP out of reset bit 23 of PRCR */
++ /* Function is ready but bypassed for Pre-Silicon */
++
++ rc=dslhal_support_unresetDsp();
++ if (rc)
++ {
++ dprintf(0,"unable to bring DSP out of Reset\n");
++ for(i=0; i<NUM_PAGES; i++)
++ {
++ if(ptidsl->olayDpPage[i].PmemStartWtAddr !=NULL)
++ {
++ shim_osFreeDmaMemory((void *) ptidsl->olayDpPage[i].PmemStartWtAddr,
++ ptidsl->olayDpPage[i].OverlayXferCount);
++ }
++ }
++ if(ptidsl->coProfiles.PmemStartWtAddr != NULL)
++ shim_osFreeDmaMemory((void *)ptidsl->coProfiles.PmemStartWtAddr, ptidsl->coProfiles.OverlayXferCount);
++ if(ptidsl->constDisplay.PmemStartWtAddr != NULL)
++ shim_osFreeDmaMemory((void *)ptidsl->constDisplay.PmemStartWtAddr, ptidsl->constDisplay.OverlayXferCount);
++ shim_osFreeVMemory((void *)ptidsl->fwimage,DSP_FIRMWARE_MALLOC_SIZE);
++ shim_osFreeMemory((void *) ptidsl, sizeof(ITIDSLHW_T));
++ return DSLHAL_ERROR_UNRESET_DSP;
++ }
++ shim_osFreeVMemory((void *)ptidsl->fwimage,DSP_FIRMWARE_MALLOC_SIZE);
++ dprintf(4,"dslhal_api_dslStartup() done\n");
++
++ /* Add the code to initialize the host interface variables */
++ /* Add code to tickle the host interface */
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_dslShutdown
++ *
++ *******************************************************************************************
++ * DESCRIPTION: routine to shutdown ax5 modem and free the resource
++ *
++ * INPUT: tidsl_t *ptidsl
++ *
++ * RETURN: NULL
++ *
++ *
++ *****************************************************************************************/
++
++int dslhal_api_dslShutdown(tidsl_t *ptidsl)
++{
++ int rc= DSLHAL_ERROR_NO_ERRORS;
++ int i;
++
++ dprintf(5, "dslhal_api_dslShutdown\n");
++ rc = dslhal_support_writeHostMailbox(ptidsl, HOST_DSLSS_SHUTDOWN, 0, 0, 0);
++ if(rc)
++ {
++ dprintf(1, " unable to reset DSP \n");
++ rc = DSLHAL_ERROR_RESET_DSP;
++ }
++ /* DSP need 50 ms to send out the message*/
++
++ shim_osClockWait(60 * 1000);
++
++ rc = dslhal_support_writeHostMailbox(ptidsl, HOST_DGASP, 0, 0, 0);
++
++ /* free memory allocated*/
++
++ for(i=0; i<NUM_PAGES; i++)
++ {
++ if(ptidsl->olayDpPage[i].PmemStartWtAddr !=NULL)
++ {
++ shim_osFreeDmaMemory((void *) ptidsl->olayDpPage[i].PmemStartWtAddr,
++ ptidsl->olayDpPage[i].OverlayXferCount);
++ }
++ }
++ if(ptidsl->coProfiles.PmemStartWtAddr != NULL)
++ shim_osFreeDmaMemory((void *)ptidsl->coProfiles.PmemStartWtAddr, ptidsl->coProfiles.OverlayXferCount);
++ if(ptidsl->constDisplay.PmemStartWtAddr != NULL)
++ shim_osFreeDmaMemory((void *)ptidsl->constDisplay.PmemStartWtAddr, ptidsl->constDisplay.OverlayXferCount);
++ shim_osFreeMemory((void *)ptidsl, sizeof(tidsl_t));
++ rc = dslhal_support_resetDsp();
++ if(rc)
++ {
++ dprintf(1, " unable to reset ADSL subsystem \n");
++ rc = DSLHAL_ERROR_RESET_DSP;
++ }
++ rc = dslhal_support_resetDslSubsystem();
++ if(rc)
++ {
++ dprintf(1, " unable to reset ADSL subsystem \n");
++ rc = DSLHAL_ERROR_RESET_ADSLSS;
++ }
++return rc;
++}
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_getDslHalVersion
++*
++*******************************************************************************************
++* DESCRIPTION: This routine supply DSL Driver version.
++*
++* INPUT: tidsl_t * ptidsl
++* void *pVer, DSP Driver Version Pointer
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++* Note: See verdef_u.h for version structure definition.
++*****************************************************************************************/
++
++void dslhal_api_getDslHalVersion(void *pVer)
++{
++ dslVer *pVersion;
++ pVersion = (dslVer *)pVer;
++ pVersion->major = (unsigned char) DSLHAL_VERSION_MAJOR;
++ pVersion->minor = (unsigned char) DSLHAL_VERSION_MINOR;
++ pVersion->bugfix = (unsigned char) DSLHAL_VERSION_BUGFIX;
++ pVersion->buildNum = (unsigned char) DSLHAL_VERSION_BUILDNUM;
++ pVersion->timeStamp = (unsigned char) DSLHAL_VERSION_TIMESTAMP;
++}
++
++/********************************************************************************************
++ * FUNCTION NAME: dslhal_api_pollTrainingStatus()
++ *
++ *********************************************************************************************
++ * DESCRIPTION: code to decode modem status and to start modem training
++ * Input: tidsl_t *ptidsl
++ *
++ * Return: modem status
++ * -1 failed
++ *
++ ********************************************************************************************/
++
++int dslhal_api_pollTrainingStatus(tidsl_t *ptidsl)
++{
++ int cmd;
++ int tag;
++ int parm1,parm2;
++ int rc;
++ unsigned int failState;
++ static unsigned int pollGhsIndex=0;
++
++ /*char *tmp;*/
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++#if SWTC
++ DEV_HOST_tcHostCommDef_t TCHostCommDef;
++#endif
++
++ dprintf(5,"dslhal_api_pollTrainingStatus\n");
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterface_t *) ptidsl->pmainAddr;
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++#if SWTC
++ dspOamSharedInterface.tcHostComm_p =(DEV_HOST_tcHostCommDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.tcHostComm_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.tcHostComm_p,
++ &TCHostCommDef, sizeof(DEV_HOST_tcHostCommDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++#endif
++
++ rc = dslhal_support_processTrainingState(ptidsl);
++ if(rc)
++ {
++ dprintf(0,"Error Reading Modem Training State \n");
++ return DSLHAL_ERROR_MODEMSTATE;
++ }
++ rc = dslhal_support_processModemStateBitField(ptidsl);
++ if(rc)
++ {
++ dprintf(0,"Error Reading Modem Training State \n");
++ return DSLHAL_ERROR_MODEMSTATE;
++ }
++ /*
++ rc = dslhal_support_readDelineationState(ptidsl);
++ if(rc)
++ {
++ dprintf(0,"Error Reading Delineation State \n");
++ return DSLHAL_ERROR_MODEMSTATE;
++ }
++ */
++ while (dslhal_support_readDspMailbox(ptidsl,&cmd, &tag, &parm1, &parm2) == DSLHAL_ERROR_NO_ERRORS )
++ {
++ dprintf(4,"mailbox message: 0x%x\n", cmd);
++ /*
++ for(rc=0;rc<8;rc++)
++ {
++ dslhal_support_readTextMailbox(ptidsl,&msg1, &msg2);
++ }
++ */
++
++ if (cmd == DSP_IDLE)
++ {
++ dprintf(4,"DSP_IDLE\n");
++ ptidsl->lConnected=0;
++ hybrid_selected=888;
++ /* add code for reload overlay pages */
++ if(ptidsl->bAutoRetrain == 0)
++ {
++ while(ptidsl->bOverlayPageLoaded == 0)
++ {
++ shim_osClockWait(6400);
++ }
++ //dslhal_support_restoreTrainingInfo(ptidsl);
++ //ptidsl->bOverlayPageLoaded = 1;
++ }
++ /* command DSP to ACTREQ */
++ if(showtimeFlag == TRUE)
++ {
++ dslhal_api_resetTrainFailureLog(ptidsl);
++ dslhal_support_advancedIdleProcessing(ptidsl);
++ showtimeFlag = FALSE;
++ }
++ failState = (unsigned int)parm1;
++ if(failState!=0)
++ {
++ ptidsl->AppData.trainFailStates[ptidsl->AppData.trainFails]=failState;
++ ptidsl->AppData.trainFails++;
++ if(ptidsl->AppData.trainFails > 30)
++ ptidsl->AppData.trainFails=0;
++ }
++ for(pollGhsIndex=0;pollGhsIndex<10;pollGhsIndex++)
++ {
++ for(rc=0;rc<62;rc++)
++ ptidsl->AppData.dsl_ghsRxBuf[pollGhsIndex][rc]=0;
++ }
++ pollGhsIndex=0;
++ rc = dslhal_support_writeHostMailbox(ptidsl,HOST_ACTREQ, 0, 0, 0);
++ if (rc)
++ return DSLHAL_ERROR_MAILBOX_WRITE;
++ }
++
++ if(cmd == DSP_ATM_TC_SYNC)
++ {
++ dprintf(4,"\nTC_SYNC\n");
++ showtimeFlag = TRUE;
++ ptidsl->lConnected=1;
++ if(ptidsl->bAutoRetrain == 0 && ptidsl->bOverlayPageLoaded == 1)
++ {
++ dslhal_support_clearTrainingInfo(ptidsl);
++ ptidsl->bOverlayPageLoaded = 0;
++ }
++ }
++ if(cmd == DSP_ACTIVE)
++ {
++ dprintf(4,"DSP_ACTIVE");
++ ptidsl->lConnected=0;
++ ptidsl->AppData.bState = RSTATE_SHOWTIME;
++ dprintf(4,"US Connect Rate: %u \n",ptidsl->AppData.USConRate);
++ dprintf(4,"DS Connect Rate: %u \n",ptidsl->AppData.DSConRate);
++ }
++ if(cmd == DSP_ATM_NO_TC_SYNC)
++ {
++ dprintf(4,"\nTC_NOSYNC\n");
++ ptidsl->lConnected=0;
++ }
++ if(cmd == DSP_DGASP)
++ {
++ dprintf(0,"\n GASP!!! \n");
++ }
++ if(cmd == DSP_OVERLAY_END)
++ {
++ dprintf(4,"Overlay Page Done %d \n",tag);
++ rc = dslhal_support_checkOverlayPage(ptidsl,tag);
++ if(rc == DSLHAL_ERROR_OVERLAY_CORRUPTED)
++ {
++ dprintf(0,"Overlay Page: %d CORRUPTED \n",tag);
++ return (0-DSLHAL_ERROR_OVERLAY_CORRUPTED);
++ }
++ }
++ if(cmd == DSP_HYBRID)
++ {
++ dprintf(2,"Hybrid Metrics Available: %d\n",tag);
++ hybrid_selected = tag;
++ }
++ if(cmd == DSP_DGASP)
++ {
++ dprintf(0,"\n GASP!!! \n");
++ }
++ if(cmd == DSP_XMITBITSWAP)
++ {
++ dslhal_support_aocBitSwapProcessing(ptidsl,0);
++ }
++ if(cmd == DSP_RCVBITSWAP)
++ {
++ dslhal_support_aocBitSwapProcessing(ptidsl,1);
++ }
++ if(cmd == DSP_GHSMSG)
++ {
++ dprintf(3,"Ghs Message Received, bytes: %d \n",tag);
++ dprintf(3,"Addr: 0x%x\n",dspOamSharedInterface.ghsDspRxBuf_p);
++ if(pollGhsIndex > 9)
++ pollGhsIndex=0;
++ rc = dslhal_support_blockRead((void *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.ghsDspRxBuf_p), &ptidsl->AppData.dsl_ghsRxBuf[pollGhsIndex++][0], tag);
++ }
++ if(cmd == DSP_CRATES1)
++ {
++ dprintf(3,"DSP C-Rates1 Data Ready \n");
++ rc = dslhal_support_gatherRateMessages(ptidsl);
++ }
++ if(cmd == DSP_SNR)
++ {
++ dprintf(3,"DSP SNR Data Ready \n");
++ rc = dslhal_support_gatherSnrPerBin(ptidsl,tag);
++ }
++ if(cmd == DSP_EOC)
++ {
++ dprintf(3,"DSP_EOC message \n");
++ rc = dslhal_support_gatherEocMessages(ptidsl,tag,parm1,parm2);
++ }
++
++ if(cmd == DSP_TRAINING_MSGS)
++ {
++ dprintf(3,"DSP_TRAINING_MSGS \n");
++ rc = dslhal_support_gatherAdsl2Messages(ptidsl,tag,parm1,parm2);
++ }
++ }
++ dprintf(6,"dslhal_api_pollTrainingStatus done\n");
++ return(ptidsl->AppData.bState);
++
++} /* end of dslhal_api_pollTrainingStatus() */
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_handleTrainingInterrupt()
++*
++*********************************************************************************************
++* DESCRIPTION: Code to handle ax5 hardware interrupts
++*
++* Input: tidsl_t *ptidsl
++* int *pMsg, pointer to returned hardware messages. Each byte represent a messge
++* int *pTag, pointer to returned hardware message tags. Each byte represent a tag.
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++int dslhal_api_handleTrainingInterrupt(tidsl_t *ptidsl, int intrSource)
++{
++ int cmd;
++ int tag;
++ int parm1,parm2;
++ unsigned int msg1;
++ unsigned int msg2;
++ int rc;
++ unsigned int failState;
++ static unsigned int interruptGhsIndex=0;
++ /*char *tmp;*/
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++#if SWTC
++ DEV_HOST_tcHostCommDef_t TCHostCommDef;
++#endif
++ dprintf(6,"dslhal_api_handleTrainingInterrupt\n");
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterface_t *) ptidsl->pmainAddr;
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++#if SWTC
++ dspOamSharedInterface.tcHostComm_p =(DEV_HOST_tcHostCommDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.tcHostComm_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.tcHostComm_p,
++ &TCHostCommDef, sizeof(DEV_HOST_tcHostCommDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++#endif
++
++ if(intrSource & MASK_BITFIELD_INTERRUPTS)
++ {
++ dspOamSharedInterface.modemStateBitField_p =(DEV_HOST_modemStateBitField_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.modemStateBitField_p);
++ rc = dslhal_support_processTrainingState(ptidsl);
++ if(rc)
++ {
++ dprintf(0,"Error Reading Modem Training State \n");
++ return DSLHAL_ERROR_MODEMSTATE;
++ }
++ rc = dslhal_support_processModemStateBitField(ptidsl);
++ if(rc)
++ {
++ dprintf(0,"Error Reading Modem Training State \n");
++ return DSLHAL_ERROR_MODEMSTATE;
++ }
++ }
++ if(intrSource & MASK_MAILBOX_INTERRUPTS)
++ {
++ /*
++ rc = dslhal_support_readDelineationState(ptidsl);
++ if(rc)
++ {
++ dprintf(0,"Error Reading Delineation State \n");
++ return DSLHAL_ERROR_MODEMSTATE;
++ }
++ */
++ while (dslhal_support_readDspMailbox(ptidsl,&cmd, &tag, &parm1, &parm2) == DSLHAL_ERROR_NO_ERRORS )
++ {
++ dprintf(4,"mailbox message: 0x%x\n", cmd);
++ /*
++ for(rc=0;rc<8;rc++)
++ {
++ dslhal_support_readTextMailbox(ptidsl,&msg1, &msg2);
++ }
++ */
++ if (cmd == DSP_IDLE)
++ {
++ dprintf(4,"DSP_IDLE\n");
++ ptidsl->lConnected=0;
++ hybrid_selected=888;
++ if(showtimeFlag == TRUE)
++ {
++ dslhal_api_resetTrainFailureLog(ptidsl);
++ dslhal_support_advancedIdleProcessing(ptidsl);
++ showtimeFlag = FALSE;
++ }
++ failState = (unsigned int)parm1;
++ if(failState!=0)
++ {
++ ptidsl->AppData.trainFailStates[ptidsl->AppData.trainFails]=failState;
++ ptidsl->AppData.trainFails++;
++ if(ptidsl->AppData.trainFails > 30)
++ ptidsl->AppData.trainFails=0;
++ }
++ for(interruptGhsIndex=0;interruptGhsIndex<10;interruptGhsIndex++)
++ {
++ for(rc=0;rc<62;rc++)
++ ptidsl->AppData.dsl_ghsRxBuf[interruptGhsIndex][rc]=0;
++ }
++ interruptGhsIndex=0;
++
++ /* add code for reload overlay pages */
++ if(ptidsl->bAutoRetrain == 0 && ptidsl->bOverlayPageLoaded == 0)
++ {
++ dslhal_support_restoreTrainingInfo(ptidsl);
++ ptidsl->bOverlayPageLoaded = 1;
++ }
++ /* command DSP to ACTREQ */
++ rc = dslhal_support_writeHostMailbox(ptidsl, HOST_ACTREQ, 0, 0, 0);
++ if (rc)
++ return DSLHAL_ERROR_MAILBOX_WRITE;
++ }
++ if(cmd == DSP_ATM_TC_SYNC)
++ {
++ dprintf(4,"\nTC_SYNC\n");
++ showtimeFlag = TRUE;
++ ptidsl->lConnected=1;
++ if(ptidsl->bAutoRetrain == 0 && ptidsl->bOverlayPageLoaded == 1)
++ {
++ dslhal_support_clearTrainingInfo(ptidsl);
++ ptidsl->bOverlayPageLoaded = 0;
++ }
++ }
++ if(cmd == DSP_ACTIVE)
++ {
++ ptidsl->lConnected=0;
++ ptidsl->AppData.bState = RSTATE_SHOWTIME;
++ dprintf(4,"DSP_ACTIVE");
++ dprintf(4,"US Connect Rate: %u \n",ptidsl->AppData.USConRate);
++ dprintf(4,"DS Connect Rate: %u \n",ptidsl->AppData.DSConRate);
++ }
++ if(cmd == DSP_ATM_NO_TC_SYNC)
++ {
++ dprintf(4,"\nTC_NOSYNC\n");
++ ptidsl->lConnected=0;
++ /* add code for reload overlay pages */
++ }
++ if(cmd == DSP_OVERLAY_END)
++ {
++ dprintf(4,"Overlay Page Done %d \n",tag);
++ rc = dslhal_support_checkOverlayPage(ptidsl,tag);
++ if(rc == DSLHAL_ERROR_OVERLAY_CORRUPTED)
++ {
++ dprintf(4,"Overlay Page: %d CORRUPTED \n",tag);
++ return(0-DSLHAL_ERROR_OVERLAY_CORRUPTED);
++ }
++ }
++ if(cmd == DSP_HYBRID)
++ {
++ dprintf(2,"Hybrid Metrics Available\n");
++ hybrid_selected = tag;
++ }
++ if(cmd == DSP_XMITBITSWAP)
++ {
++ rc = dslhal_support_aocBitSwapProcessing(ptidsl,0);
++ }
++ if(cmd == DSP_RCVBITSWAP)
++ {
++ rc = dslhal_support_aocBitSwapProcessing(ptidsl,1);
++ }
++ if(cmd == DSP_GHSMSG)
++ {
++ dprintf(3,"Ghs Message Received, bytes: %d \n",tag);
++ dprintf(3,"Addr: 0x%x\n",dspOamSharedInterface.ghsDspRxBuf_p);
++ if(interruptGhsIndex > 9)
++ interruptGhsIndex=0;
++ rc = dslhal_support_blockRead((void *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.ghsDspRxBuf_p), &ptidsl->AppData.dsl_ghsRxBuf[interruptGhsIndex++][0], tag);
++ }
++ if(cmd == DSP_CRATES1)
++ {
++ dprintf(3,"DSP C-Rates1 Data Ready \n");
++ rc = dslhal_support_gatherRateMessages(ptidsl);
++ }
++ if(cmd == DSP_SNR)
++ {
++ dprintf(3,"DSP SNR Data Ready \n");
++ rc = dslhal_support_gatherSnrPerBin(ptidsl,tag);
++ }
++ if(cmd == DSP_EOC)
++ {
++ dprintf(3,"DSP_EOC message \n");
++ rc = dslhal_support_gatherEocMessages(ptidsl,tag,parm1,parm2);
++ }
++ if(cmd == DSP_TRAINING_MSGS)
++ {
++ dprintf(3,"DSP_TRAINING_MSGS \n");
++ rc = dslhal_support_gatherAdsl2Messages(ptidsl,tag,parm1,parm2);
++ }
++ }
++
++ dslhal_support_readTextMailbox(ptidsl,&msg1, &msg2);
++ dprintf(5,"Text Message Part1: 0x%x \t Text Message Part2: 0x%x \n",msg1,msg2);
++ }
++ dprintf(6,"dslhal_api_handleTrainingInterrupt done\n");
++ return(ptidsl->AppData.bState);
++} /* end of dslhal_api_handleTrainingInterrupt() */
++
++
++
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_dslRetrain(tidsl_t *ptidsl)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends CMD_ACTREQ to the DSP to issue a retrain
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_dslRetrain(tidsl_t *ptidsl)
++{
++ int rc;
++
++ dprintf(5, "dslhal_cfg_dslRetrain \n");
++ rc = dslhal_support_writeHostMailbox(ptidsl, HOST_QUIET, 0, 0, 0);
++ if(rc)
++ {
++ dprintf(1,"dslhal_cfg_dslRetrain failed\n");
++ return DSLHAL_ERROR_CTRL_API_FAILURE;
++ }
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_sendQuiet(tidsl_t *ptidsl)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the CMD_QUIET message to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_sendQuiet(tidsl_t *ptidsl)
++{
++ int rc;
++
++ dprintf(5, "dslhal_api_sendQuiet\n");
++ rc = dslhal_support_writeHostMailbox(ptidsl, HOST_QUIET, 0, 0, 0);
++ if(rc)
++ {
++ dprintf(1,"dslhal_api_sendQuiet failed\n");
++ return DSLHAL_ERROR_CTRL_API_FAILURE;
++ }
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_sendIdle(tidsl_t *ptidsl)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the CMD_IDLE message to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_sendIdle(tidsl_t *ptidsl)
++{
++ int rc;
++
++ dprintf(5, "dslhal_api_sendIdle\n");
++ rc = dslhal_support_writeHostMailbox(ptidsl, HOST_IDLE, 0, 0, 0);
++ if(rc)
++ {
++ dprintf(1,"dslhal_api_sendIdle failed\n");
++ return DSLHAL_ERROR_CTRL_API_FAILURE;
++ }
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_sendDgasp(tidsl_t *ptidsl)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the HOST_DGASP message to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_sendDgasp(tidsl_t *ptidsl)
++{
++ int rc;
++
++ dprintf(5, "dslhal_api_sendDgasp\n");
++ rc = dslhal_support_writeHostMailbox(ptidsl, HOST_DGASP, 0, 0, 0);
++ if(rc)
++ {
++ dprintf(1,"dslhal_api_sendDgasp failed\n");
++ return DSLHAL_ERROR_CTRL_API_FAILURE;
++ }
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setTrainingMode(tidsl_t *ptidsl,unsigned int trainmode)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the Desired Training Mode {None/Multimode/G.dmt/lite
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int trainmode :Should be between 0 and 4; 0:No Mode 1:Multimode
++* 2: T1.413, 3:G.dmt, 4: G.lite
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++unsigned int dslhal_api_setTrainingMode(tidsl_t *ptidsl,unsigned int trainmode)
++{
++ DEV_HOST_oamWrNegoParaDef_t NegoPara;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++ dprintf(5," dslhal_api_setTrainingMode()\n");
++ if(trainmode>255)
++ {
++ dprintf(3,"Invalid Value for Desired Training Mode (must be <255)\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.oamWriteNegoParams_p = (DEV_HOST_oamWrNegoParaDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.oamWriteNegoParams_p);
++
++ rc = dslhal_support_blockRead((PVOID) dspOamSharedInterface.oamWriteNegoParams_p,&NegoPara, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ /* Enum Translation to maintain backwards compatibility for train modes */
++ if(trainmode == DSLTRAIN_MULTI_MODE)
++ trainmode = MULTI_MODE;
++ if(trainmode == DSLTRAIN_T1413_MODE)
++ trainmode = T1413_MODE;
++ if(trainmode == DSLTRAIN_GDMT_MODE)
++ trainmode = GDMT_MODE;
++
++ NegoPara.stdMode = trainmode;
++ dprintf(5,"Train Mode: 0x%x\n",trainmode);
++ rc = dslhal_support_blockWrite(&NegoPara,(PVOID)dspOamSharedInterface.oamWriteNegoParams_p, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++
++ dprintf(5," dslhal_api_setTrainingMode() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_getDspVersion
++*
++*******************************************************************************************
++* DESCRIPTION: This routine supply AX5 daugther card DSP version.
++*
++* INPUT: tidsl_t * ptidsl
++* void *pVer, DSP version struct is returned starting at this pointer
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++* Note: See verdef_u.h for version structure definition.
++*****************************************************************************************/
++int dslhal_api_getDspVersion(tidsl_t *ptidsl, void *pVer)
++{
++ /* DEV_HOST_dspVersionDef_t dspVersion; */
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++ dprintf(5, "dslhal_api_getDspVersion\n");
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ if(!pVer)
++ return DSLHAL_ERROR_INVALID_PARAM;
++
++ *(unsigned int *) pVer = 0;
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.datapumpVersion_p = (DEV_HOST_dspVersionDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.datapumpVersion_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.datapumpVersion_p,
++ pVer, sizeof(dspVer));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ pVer = (DEV_HOST_dspVersionDef_t *)(dslhal_support_byteSwap32((unsigned int)pVer));
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_gatherStatistics()
++*
++*********************************************************************************************
++* DESCRIPTION: Read statistical infromation from ax5 modem daugter card.
++* Input: tidsl_t *ptidsl
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++void dslhal_api_gatherStatistics(tidsl_t * ptidsl)
++{
++ int rc,optIdxU,optIdxD,i;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ DEV_HOST_dspWrNegoParaDef_t rateparms;
++ DEV_HOST_oamWrNegoParaDef_t configParms;
++ DEV_HOST_modemStatsDef_t StatisticsDef;
++ DEV_HOST_errorStats_t usIntlvError, usFastError, dsIntlvError, dsFastError;
++ DEV_HOST_atmStats_t atmStats;
++ DEV_HOST_usAtmStats_t usAtmStats0, usAtmStats1;
++ DEV_HOST_dsAtmStats_t dsAtmStats0,dsAtmStats1;
++ DEV_HOST_dspWrSuperFrameCntDef_t SuperFrameCnt;
++ DEV_HOST_msg_t atuc_msg, aturMsg;
++ DEV_HOST_eocVarDef_t eocVar;
++ DEV_HOST_dspWrSharedTables_t sharedTables;
++ DEV_HOST_phyPerf_t phyPerf;
++ unsigned char usBits[64],dsBits[256];
++ unsigned char dsPowerCutBack;
++ int usNumLoadedTones=0, dsNumLoadedTones=0;
++
++ dprintf(5, "dslhal_api_gatherStatistics\n");
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ if(!ptidsl->bStatisticsInitialized && ptidsl->lConnected == LINE_CONNECTED)
++ {
++ dslhal_api_initStatistics(ptidsl);
++ ptidsl->bStatisticsInitialized = TRUE;
++ }
++
++ dspOamSharedInterface.dspWriteNegoParams_p = (DEV_HOST_dspWrNegoParaDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.dspWriteNegoParams_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.dspWriteNegoParams_p,
++ &rateparms, sizeof(DEV_HOST_dspWrNegoParaDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ if(!rc)
++ {
++ /* trained mode */
++ ptidsl->AppData.dsl_modulation = (unsigned int)rateparms.trainMode;
++ if(rateparms.trainMode == T1413_MODE)
++ ptidsl->AppData.dsl_modulation = DSLTRAIN_T1413_MODE;
++ if(rateparms.trainMode == GDMT_MODE)
++ ptidsl->AppData.dsl_modulation = DSLTRAIN_GDMT_MODE;
++ /* rate */
++ /* shim_osMoveMemory((void *)ptidsl->AppData.bCRates1, (void *)rateparms.cRates1, 120); */
++ ptidsl->AppData.bCRates2 = rateparms.cRates2;
++ /* shim_osMoveMemory((void *)ptidsl->AppData.bRRates1, (void *)rateparms.rRates1, 44); */
++ ptidsl->AppData.bRRates2 = rateparms.rRates2;
++ shim_osMoveMemory((void *)ptidsl->AppData.bCMsgs1, (void *)rateparms.cMsgs1, 6);
++ shim_osMoveMemory((void *)ptidsl->AppData.bCMsgs2, (void *)rateparms.cMsgs2, 4);
++ shim_osMoveMemory((void *)ptidsl->AppData.bRMsgs2, (void *)rateparms.rMsgs2, 4);
++ ptidsl->AppData.atucVendorId = (unsigned int)rateparms.atucVendorId;
++ ptidsl->AppData.lineLength = (unsigned int)dslhal_support_byteSwap16((unsigned short)rateparms.lineLength);
++ ptidsl->AppData.atucRevisionNum = (unsigned int)rateparms.atucGhsRevisionNum;
++ ptidsl->AppData.usLineAttn = (ptidsl->AppData.bCMsgs2[3] >>2)&0x003f;
++ ptidsl->AppData.usMargin = (ptidsl->AppData.bCMsgs2[2])&0x001f;
++
++ if((rateparms.cRates2 & 0x0f) == 0x01)
++ optIdxU = 0;
++ else if((rateparms.cRates2 & 0x0f) == 0x02)
++ optIdxU = 1;
++ else if((rateparms.cRates2 & 0x0f) == 0x04)
++ optIdxU = 2;
++ else if((rateparms.cRates2 & 0x0f) == 0x08)
++ optIdxU = 3;
++ else
++ optIdxU = -1;
++
++ dprintf(5, "optIdxU=%d\n", optIdxU);
++
++ /* Obtain the US Rates using Opt# and CRates1 Table */
++ /* Rate(US) = [Bf(LS0) + Bi(LS0)]*32 */
++ if(ptidsl->AppData.dsl_modulation <= DSLTRAIN_GLITE_MODE)
++ ptidsl->AppData.USConRate = ((rateparms.cRates1[optIdxU][CRATES1_BF_LS0] + rateparms.cRates1[optIdxU][CRATES1_BI_LS0]) * 32);
++ else
++ ptidsl->AppData.USConRate = 32 * dslhal_support_byteSwap16((unsigned short)rateparms.adsl2USRate);
++
++ ptidsl->AppData.USPeakCellRate = ptidsl->AppData.USConRate;
++
++ if(((rateparms.cRates2 >> 4) & 0x0f) == 0x01)
++ optIdxD = 0;
++ else if(((rateparms.cRates2 >> 4) & 0x0f) == 0x02)
++ optIdxD = 1;
++ else if(((rateparms.cRates2 >> 4) & 0x0f) == 0x04)
++ optIdxD = 2;
++ else if(((rateparms.cRates2 >> 4) & 0x0f) == 0x08)
++ optIdxD = 3;
++ else
++ optIdxD = -1;
++ /* Obtain the DS Rates using Opt# and CRates1 Table */
++ /* Rate(DS) = [Bf(AS0) + Bi(AS0)]*32 */
++ if(ptidsl->AppData.dsl_modulation <= DSLTRAIN_GLITE_MODE)
++ ptidsl->AppData.DSConRate = (((rateparms.cRates1[optIdxD][CRATES1_BF_AS0]|((rateparms.cRates1[optIdxD][CRATES1_BF_DSRS]&0x80)<<1))+ (rateparms.cRates1[optIdxD][CRATES1_BI_AS0]|((rateparms.cRates1[optIdxD][CRATES1_BI_DSRS]&0x80)<<1)))* 32);
++ else
++ ptidsl->AppData.DSConRate = dslhal_support_byteSwap16((unsigned short)rateparms.adsl2DSRate);
++
++ dprintf(5, "ptidsl->AppData.wDSConRate=%d\n", ptidsl->AppData.DSConRate);
++ /* Determine which Path has Modem Trained with */
++ if((rateparms.cRates1[optIdxU][CRATES1_BF_LS0]) && (rateparms.cRates1[optIdxD][CRATES1_BF_AS0]))
++ ptidsl->AppData.TrainedPath = FAST_PATH;
++ else
++ ptidsl->AppData.TrainedPath = INTERLEAVED_PATH;
++
++ /* Set the mode in which the modem is trained */
++ ptidsl->AppData.TrainedMode = (unsigned int)rateparms.trainMode;
++ if(rateparms.trainMode == T1413_MODE)
++ ptidsl->AppData.TrainedMode = DSLTRAIN_T1413_MODE;
++ if(rateparms.trainMode == GDMT_MODE)
++ ptidsl->AppData.TrainedMode = DSLTRAIN_GDMT_MODE;
++
++ if(ptidsl->AppData.TrainedPath == FAST_PATH)
++ ptidsl->AppData.dsFastParityBytesPerSymbol = (rateparms.cRates1[optIdxU][CRATES1_BF_DSRS]&0x1f);
++ else
++ ptidsl->AppData.dsIntlvParityBytesPerSymbol = (rateparms.cRates1[optIdxU][CRATES1_BI_DSRS]&0x1f);
++ ptidsl->AppData.dsSymbolsPerCodeWord = (rateparms.cRates1[optIdxU][CRATES1_BFI_DSS]&0x1f);
++ ptidsl->AppData.dsInterleaverDepth = ((rateparms.cRates1[optIdxU][CRATES1_BFI_DSI])|((rateparms.cRates1[optIdxU][CRATES1_BFI_DSS]&0xc0)<<2));
++
++ if(ptidsl->AppData.TrainedPath == FAST_PATH)
++ ptidsl->AppData.usFastParityBytesPerSymbol = (rateparms.cRates1[optIdxU][CRATES1_BF_USRS]&0x1f);
++ else
++ ptidsl->AppData.usIntlvParityBytesPerSymbol = (rateparms.cRates1[optIdxU][CRATES1_BI_USRS]&0x1f);
++ ptidsl->AppData.usSymbolsPerCodeWord = (rateparms.cRates1[optIdxU][CRATES1_BFI_USS]&0x1f);
++ ptidsl->AppData.usInterleaverDepth = ((rateparms.cRates1[optIdxU][CRATES1_BFI_USI])|((rateparms.cRates1[optIdxU][CRATES1_BFI_USS]&0xc0)<<2));
++ }
++
++ dspOamSharedInterface.modemStats_p = (DEV_HOST_modemStatsDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.modemStats_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.modemStats_p,&StatisticsDef, sizeof(DEV_HOST_modemStatsDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ /* Populate the Error Structure Variables */
++
++ /* US Interleave Path Error Statistics */
++
++ /* Change the endianness of the Pointer */
++ StatisticsDef.usErrorStatsIntlv_p = (DEV_HOST_errorStats_t *) dslhal_support_byteSwap32((unsigned int)StatisticsDef.usErrorStatsIntlv_p);
++
++ rc = dslhal_support_blockRead((PVOID)StatisticsDef.usErrorStatsIntlv_p,&usIntlvError, (sizeof(DEV_HOST_errorStats_t)));
++
++ if (rc)
++ return;
++
++ /* DS Interleave Path Error Statistics */
++
++ /* Change the endianness of the Pointer */
++ StatisticsDef.dsErrorStatsIntlv_p = (DEV_HOST_errorStats_t *) dslhal_support_byteSwap32((unsigned int)StatisticsDef.dsErrorStatsIntlv_p);
++
++ rc = dslhal_support_blockRead((PVOID)StatisticsDef.dsErrorStatsIntlv_p,&dsIntlvError, (sizeof(DEV_HOST_errorStats_t)));
++
++ if (rc)
++ return;
++
++ /* US Fast Path Error Statistics */
++
++ /* Change the endianness of the Pointer */
++ StatisticsDef.usErrorStatsFast_p = (DEV_HOST_errorStats_t *) dslhal_support_byteSwap32((unsigned int)StatisticsDef.usErrorStatsFast_p);
++
++ rc = dslhal_support_blockRead((PVOID)StatisticsDef.usErrorStatsFast_p,&usFastError, (sizeof(DEV_HOST_errorStats_t)));
++
++ if (rc)
++ return;
++
++ /* DS Fast Path Error Statistics */
++
++ /* Change the endianness of the Pointer */
++ StatisticsDef.dsErrorStatsFast_p = (DEV_HOST_errorStats_t *) dslhal_support_byteSwap32((unsigned int)StatisticsDef.dsErrorStatsFast_p);
++
++ rc = dslhal_support_blockRead((PVOID)StatisticsDef.dsErrorStatsFast_p,&dsFastError, (sizeof(DEV_HOST_errorStats_t)));
++
++ if (rc)
++ return;
++ if(!rc)
++ {
++ if(ptidsl->AppData.bState > 2)
++ {
++ /* Get CRC Errors Stats for both US and DS */
++ ptidsl->AppData.dsICRC_errors = dslhal_support_byteSwap32((unsigned int)dsIntlvError.crcErrors);
++ ptidsl->AppData.dsFCRC_errors = dslhal_support_byteSwap32((unsigned int)dsFastError.crcErrors);
++ ptidsl->AppData.usICRC_errors = dslhal_support_byteSwap32((unsigned int)usIntlvError.crcErrors);
++ ptidsl->AppData.usFCRC_errors = dslhal_support_byteSwap32((unsigned int)usFastError.crcErrors);
++ /* Get FEC Errors Stats for both US and DS */
++ ptidsl->AppData.dsIFEC_errors = dslhal_support_byteSwap32((unsigned int)dsIntlvError.fecErrors);
++ ptidsl->AppData.dsFFEC_errors = dslhal_support_byteSwap32((unsigned int)dsFastError.fecErrors);
++ ptidsl->AppData.usIFEC_errors = dslhal_support_byteSwap32((unsigned int)usIntlvError.fecErrors);
++ ptidsl->AppData.usFFEC_errors = dslhal_support_byteSwap32((unsigned int)usFastError.fecErrors);
++ /* Get NCD Errors Stats for both US and DS */
++ ptidsl->AppData.dsINCD_error = dslhal_support_byteSwap32((unsigned int)dsIntlvError.ncdError);
++ ptidsl->AppData.dsFNCD_error = dslhal_support_byteSwap32((unsigned int)dsFastError.ncdError);
++ ptidsl->AppData.usINCD_error = dslhal_support_byteSwap32((unsigned int)usIntlvError.ncdError);
++ ptidsl->AppData.usFNCD_error = dslhal_support_byteSwap32((unsigned int)usFastError.ncdError);
++ /* Get LCD Errors Stats for both US and DS */
++ ptidsl->AppData.dsILCD_errors = dslhal_support_byteSwap32((unsigned int)dsIntlvError.lcdErrors);
++ ptidsl->AppData.dsFLCD_errors = dslhal_support_byteSwap32((unsigned int)dsFastError.lcdErrors);
++ ptidsl->AppData.usILCD_errors = dslhal_support_byteSwap32((unsigned int)usIntlvError.lcdErrors);
++ ptidsl->AppData.usFLCD_errors = dslhal_support_byteSwap32((unsigned int)usFastError.lcdErrors);
++ /*Get HEC Errors Stats for both US and DS */
++ ptidsl->AppData.dsIHEC_errors = dslhal_support_byteSwap32((unsigned int)dsIntlvError.hecErrors);
++ ptidsl->AppData.dsFHEC_errors = dslhal_support_byteSwap32((unsigned int)dsFastError.hecErrors);
++ ptidsl->AppData.usIHEC_errors = dslhal_support_byteSwap32((unsigned int)usIntlvError.hecErrors);
++ ptidsl->AppData.usFHEC_errors = dslhal_support_byteSwap32((unsigned int)usFastError.hecErrors);
++
++ /* Get LOS and SEF error Stats */
++ ptidsl->AppData.LOS_errors = dslhal_support_byteSwap32(StatisticsDef.losErrors);
++ ptidsl->AppData.SEF_errors = dslhal_support_byteSwap32(StatisticsDef.sefErrors);
++ ptidsl->AppData.coLosErrors = dslhal_support_byteSwap32(StatisticsDef.farEndLosErrors);
++ ptidsl->AppData.coRdiErrors = dslhal_support_byteSwap32(StatisticsDef.farEndRdiErrors);
++
++ dspOamSharedInterface.atmStats_p = (DEV_HOST_atmStats_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.atmStats_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.atmStats_p,&atmStats, sizeof(DEV_HOST_atmStats_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++
++ /* Populate the US/DS ATM Stats Variables */
++
++ /* US ATM Statistics */
++
++ /* Change the endianness of the Pointer */
++ atmStats.us0_p = (DEV_HOST_usAtmStats_t *) dslhal_support_byteSwap32((unsigned int)atmStats.us0_p);
++
++ rc = dslhal_support_blockRead((PVOID)atmStats.us0_p,&usAtmStats0, (sizeof(DEV_HOST_usAtmStats_t)));
++
++ if (rc)
++ return;
++
++ atmStats.us1_p = (DEV_HOST_usAtmStats_t *) dslhal_support_byteSwap32((unsigned int)atmStats.us1_p);
++
++ rc = dslhal_support_blockRead((PVOID)atmStats.us1_p,&usAtmStats1, (sizeof(DEV_HOST_usAtmStats_t)));
++
++ if (rc)
++ return;
++
++ /* DS ATM Statistics */
++
++ /* Change the endianness of the Pointer */
++ atmStats.ds0_p = (DEV_HOST_dsAtmStats_t *) dslhal_support_byteSwap32((unsigned int)atmStats.ds0_p);
++
++ rc = dslhal_support_blockRead((PVOID)atmStats.ds0_p,&dsAtmStats0, (sizeof(DEV_HOST_dsAtmStats_t)));
++
++ if (rc)
++ return;
++ atmStats.ds1_p = (DEV_HOST_dsAtmStats_t *) dslhal_support_byteSwap32((unsigned int)atmStats.ds1_p);
++
++ rc = dslhal_support_blockRead((PVOID)atmStats.ds1_p,&dsAtmStats1, (sizeof(DEV_HOST_dsAtmStats_t)));
++
++ if (rc)
++ return;
++
++ /* Get ATM Stats for both US and DS for Channel 0*/
++ ptidsl->AppData.usAtm_count[0] = dslhal_support_byteSwap32(usAtmStats0.goodCount);
++ ptidsl->AppData.usIdle_count[0] = dslhal_support_byteSwap32(usAtmStats0.idleCount);
++#if SWTC
++ ptidsl->AppData.usPdu_count[0] = dslhal_support_byteSwap32(usAtmStats0.pduCount);
++#endif
++ ptidsl->AppData.dsGood_count[0] = dslhal_support_byteSwap32(dsAtmStats0.goodCount);
++ ptidsl->AppData.dsIdle_count[0] = dslhal_support_byteSwap32(dsAtmStats0.idleCount);
++#if SWTC
++ ptidsl->AppData.dsPdu_count[0] = dslhal_support_byteSwap32(dsAtmStats0.pduCount);
++#endif
++ ptidsl->AppData.dsBadHec_count[0] = dslhal_support_byteSwap32((dsAtmStats0.badHecCount));
++ ptidsl->AppData.dsOVFDrop_count[0] = dslhal_support_byteSwap32((dsAtmStats0.ovflwDropCount));
++ /* Get ATM Stats for both US and DS for Channel 1*/
++ ptidsl->AppData.usAtm_count[1] = dslhal_support_byteSwap32(usAtmStats1.goodCount);
++ ptidsl->AppData.usIdle_count[1] = dslhal_support_byteSwap32(usAtmStats1.idleCount);
++#if SWTC
++ ptidsl->AppData.usPdu_count[1] = dslhal_support_byteSwap32(usAtmStats1.pduCount);
++#endif
++ ptidsl->AppData.dsGood_count[1] = dslhal_support_byteSwap32(dsAtmStats1.goodCount);
++ ptidsl->AppData.dsIdle_count[1] = dslhal_support_byteSwap32(dsAtmStats1.idleCount);
++#if SWTC
++ ptidsl->AppData.dsPdu_count[1] = dslhal_support_byteSwap32(dsAtmStats1.pduCount);
++#endif
++ ptidsl->AppData.dsBadHec_count[1] = dslhal_support_byteSwap32((dsAtmStats1.badHecCount));
++ ptidsl->AppData.dsOVFDrop_count[1] = dslhal_support_byteSwap32((dsAtmStats1.ovflwDropCount));
++
++ /* Determine the US and DS Superframe Count */
++
++ dspOamSharedInterface.dspWriteSuperFrameCnt_p = (DEV_HOST_dspWrSuperFrameCntDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.dspWriteSuperFrameCnt_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.dspWriteSuperFrameCnt_p,&SuperFrameCnt, sizeof(DEV_HOST_dspWrSuperFrameCntDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ ptidsl->AppData.usSuperFrmCnt = dslhal_support_byteSwap32(SuperFrameCnt.wSuperFrameCntUstrm);
++ ptidsl->AppData.dsSuperFrmCnt = dslhal_support_byteSwap32(SuperFrameCnt.wSuperFrameCntDstrm);
++
++ /* Determine Frame Mode and Max Frame Mode */
++
++ dspOamSharedInterface.atucMsg_p = (DEV_HOST_msg_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.atucMsg_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.atucMsg_p,&atuc_msg, sizeof(DEV_HOST_msg_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++
++ ptidsl->AppData.FrmMode = (unsigned int)atuc_msg.framingMode;
++ ptidsl->AppData.MaxFrmMode = (unsigned int)atuc_msg.maxFrameMode;
++
++ /* Determine Gross Gain */
++
++ dspOamSharedInterface.aturMsg_p = (DEV_HOST_msg_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.aturMsg_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.aturMsg_p,&aturMsg, sizeof(DEV_HOST_msg_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ ptidsl->AppData.grossGain = (unsigned int)aturMsg.grossGain;
++
++ /* Determine DS Line Attenuation & Margin */
++ dspOamSharedInterface.eocVar_p = (DEV_HOST_eocVarDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.eocVar_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.eocVar_p,&eocVar, sizeof(DEV_HOST_eocVarDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ ptidsl->AppData.dsLineAttn = (unsigned int)eocVar.lineAtten;
++ ptidsl->AppData.dsMargin = (unsigned int)eocVar.dsMargin;
++ }
++ }
++
++ /* Read in the Shared Tables structure */
++ dspOamSharedInterface.dspWrSharedTables_p = (DEV_HOST_dspWrSharedTables_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.dspWrSharedTables_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.dspWrSharedTables_p,&sharedTables, sizeof(DEV_HOST_dspWrSharedTables_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++
++ /* Read the ATU-R Bits and Gains Table */
++ sharedTables.aturBng_p = (unsigned char *)dslhal_support_byteSwap32((unsigned int)sharedTables.aturBng_p);
++ rc = dslhal_support_blockRead((PVOID)sharedTables.aturBng_p,ptidsl->AppData.rBng,255*2*sizeof(unsigned char));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ /* Read the ATU-C Bits and Gains Table */
++ sharedTables.atucBng_p = (unsigned char *)dslhal_support_byteSwap32((unsigned int)sharedTables.atucBng_p);
++ if(ptidsl->netService == 2) /* for Annex_B */
++ {
++ rc = dslhal_support_blockRead((PVOID)sharedTables.atucBng_p,ptidsl->AppData.cBng,126*sizeof(unsigned char));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ for(i=0;i<US_BNG_LENGTH*2;i++)
++ usBits[i]=0;
++ for(i=1;i<US_BNG_LENGTH*2;i++)
++ {
++ usBits[i]=((ptidsl->AppData.cBng[(i-1)*2])&0xf);
++ dprintf(5,"Bit #%d : 0x%x\n",i,usBits[i]);
++ }
++ for(i=1;i<US_BNG_LENGTH*2;i++)
++ {
++ if(usBits[i])
++ usNumLoadedTones++;
++ }
++ }
++ else
++ {
++ rc = dslhal_support_blockRead((PVOID)sharedTables.atucBng_p,ptidsl->AppData.cBng,62*sizeof(unsigned char));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ for(i=0;i<US_BNG_LENGTH;i++)
++ usBits[i]=0;
++ for(i=1;i<US_BNG_LENGTH;i++)
++ {
++ usBits[i]=((ptidsl->AppData.cBng[(i-1)*2])&0xf);
++ dprintf(5,"Bit #%d : 0x%x\n",i,usBits[i]);
++ }
++ for(i=1;i<US_BNG_LENGTH;i++)
++ {
++ if(usBits[i])
++ usNumLoadedTones++;
++ }
++ }
++
++ /* Determine Number U/S of Loaded Tones */
++
++ /* U/S Power Computation */
++ dspOamSharedInterface.phyPerf_p = (DEV_HOST_phyPerf_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.phyPerf_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.phyPerf_p,
++ &phyPerf, sizeof(DEV_HOST_phyPerf_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ ptidsl->AppData.currentHybridNum = phyPerf.currentHybridNumUsed;
++ phyPerf.usAvgGain = dslhal_support_byteSwap32(phyPerf.usAvgGain);
++ ptidsl->AppData.usTxPower = LOG43125 + phyPerf.usAvgGain + (256*US_NOMINAL_POWER)+log10[usNumLoadedTones-1];
++ dprintf(7,"Avg Gain: 0x%x usNumLoadedTones: 0x%x log: 0x%x\n",phyPerf.usAvgGain, usNumLoadedTones, log10[usNumLoadedTones-1]);
++
++ /* Determine Number D/S of Loaded Tones */
++ dsBits[0]=0;
++ for(i=0;i<DS_BNG_LENGTH;i++)
++ {
++ dsBits[i]=0;
++ /* ptidsl->AppData.rBng[i-1]=dslhal_support_byteSwap32((unsigned int)ptidsl->AppData.rBng[i-1]);*/
++ }
++ for(i=1;i<DS_BNG_LENGTH;i++)
++ {
++ dsBits[i]=((ptidsl->AppData.rBng[(i-1)*2])&0xf);
++ dprintf(5,"Bit #%d : 0x%x\n",i,dsBits[i]);
++ }
++ for(i=1;i<DS_BNG_LENGTH;i++)
++ {
++ if(dsBits[i])
++ dsNumLoadedTones++;
++ }
++ /* D/S Power Computation */
++ dspOamSharedInterface.phyPerf_p = (DEV_HOST_phyPerf_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.phyPerf_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.phyPerf_p,
++ &phyPerf, sizeof(DEV_HOST_phyPerf_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ /* D/S Power Cutback */
++ dsPowerCutBack = (unsigned char)((((ptidsl->AppData.bCMsgs1[0]) >>6) &0x3)+(((ptidsl->AppData.bCMsgs1[1]) &0x1) <<2));
++ phyPerf.dsAvgGain = dslhal_support_byteSwap32(phyPerf.dsAvgGain);
++ ptidsl->AppData.dsTxPower = LOG43125 + phyPerf.dsAvgGain + (256*((2*(dsPowerCutBack-1))-52)) + log10[dsNumLoadedTones-1];
++ dprintf(7,"Avg Gain: %d dsNumLoadedTones: %d log: %d pcb: %d \n",phyPerf.dsAvgGain, dsNumLoadedTones, log10[dsNumLoadedTones-1], dsPowerCutBack);
++ /* ds bit allocation */
++ sharedTables.bitAllocTblDstrm_p = (unsigned char *)dslhal_support_byteSwap32((unsigned int)sharedTables.bitAllocTblDstrm_p);
++ rc = dslhal_support_blockRead((PVOID)sharedTables.bitAllocTblDstrm_p,ptidsl->AppData.BitAllocTblDstrm, 256*sizeof(unsigned char));
++ if(rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed \n");
++ return;
++ }
++
++ /* us bit allocation */
++ sharedTables.bitAllocTblUstrm_p = (unsigned char *)dslhal_support_byteSwap32((unsigned int)sharedTables.bitAllocTblUstrm_p);
++ rc = dslhal_support_blockRead((PVOID)sharedTables.bitAllocTblUstrm_p,ptidsl->AppData.BitAllocTblUstrm, 32*sizeof(unsigned char));
++ if(rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed \n");
++ return;
++ }
++ /* margin per tone */
++ sharedTables.marginTblDstrm_p = (signed char *)dslhal_support_byteSwap32((unsigned int)sharedTables.marginTblDstrm_p);
++ rc = dslhal_support_blockRead((PVOID)sharedTables.marginTblDstrm_p,ptidsl->AppData.marginTblDstrm, 256*sizeof(signed char));
++ if(rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed \n");
++ return;
++ }
++ /* Read Configured Options */
++ dspOamSharedInterface.oamWriteNegoParams_p = (DEV_HOST_oamWrNegoParaDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.oamWriteNegoParams_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.oamWriteNegoParams_p,
++ &configParms, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ else
++ {
++ /* r-Msg1 */
++ ptidsl->AppData.StdMode = (unsigned int)configParms.stdMode;
++ if(configParms.stdMode == T1413_MODE)
++ ptidsl->AppData.StdMode = DSLTRAIN_T1413_MODE;
++ if(configParms.stdMode == GDMT_MODE)
++ ptidsl->AppData.StdMode = DSLTRAIN_GDMT_MODE;
++ if(configParms.stdMode == MULTI_MODE)
++ ptidsl->AppData.StdMode = DSLTRAIN_MULTI_MODE;
++
++ shim_osMoveMemory((void *)ptidsl->AppData.bRMsgs1, (void *)configParms.rMsgs1, 6*sizeof(char));
++ if((ptidsl->AppData.bRMsgs1[2] & 0x02) == 0x02)
++ {
++ dprintf(7,"Trellis!\n");
++ ptidsl->configFlag |= CONFIG_FLAG_TRELLIS;
++ }
++ else
++ ptidsl->configFlag &= ~CONFIG_FLAG_TRELLIS;
++ if(ptidsl->AppData.bRMsgs1[2]&0x01)
++ ptidsl->configFlag |= CONFIG_FLAG_EC;
++ else
++ ptidsl->configFlag &= ~CONFIG_FLAG_EC;
++ }
++ return;
++}
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_initStatistics()
++*
++*********************************************************************************************
++* DESCRIPTION: init statistical information of ax5 modem daugter card.
++*
++* Input: tidsl_t *ptidsl
++*
++* Return: NULL
++*
++********************************************************************************************/
++void dslhal_api_initStatistics(tidsl_t * ptidsl)
++{
++ int rc;
++ /*TCHostCommDef TCHostCommParms; */
++ int optIdxU, optIdxD;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ DEV_HOST_dspWrNegoParaDef_t rateparms;
++ DEV_HOST_modemStatsDef_t StatisticsDef;
++ DEV_HOST_errorStats_t usIntlvError, usFastError, dsIntlvError, dsFastError;
++ DEV_HOST_atmStats_t atmStats;
++ DEV_HOST_usAtmStats_t usAtmStats0, usAtmStats1;
++ DEV_HOST_dsAtmStats_t dsAtmStats0,dsAtmStats1;
++ DEV_HOST_dspWrSuperFrameCntDef_t SuperFrameCnt;
++ DEV_HOST_msg_t atuc_msg, aturMsg;
++ DEV_HOST_eocVarDef_t eocVar;
++
++ dprintf(5, "dslhal_api_initStatistics\n");
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterface_t *) ptidsl->pmainAddr;
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ dspOamSharedInterface.dspWriteNegoParams_p = (DEV_HOST_dspWrNegoParaDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.dspWriteNegoParams_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.dspWriteNegoParams_p,&rateparms, sizeof(DEV_HOST_dspWrNegoParaDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ if(!rc)
++ {
++ /* shim_osMoveMemory((void *)ptidsl->AppData.bCRates1, (void *)rateparms.cRates1, SIZE_OF_CRATES1_TABLE); */
++ ptidsl->AppData.bCRates2 = rateparms.cRates2;
++ /* shim_osMoveMemory((void *)ptidsl->AppData.bRRates1, (void *)rateparms.rRates1, 44); */
++ ptidsl->AppData.bRRates2 = rateparms.rRates2;
++ shim_osMoveMemory((void *)ptidsl->AppData.bCMsgs1, (void *)rateparms.cMsgs1, 6);
++ shim_osMoveMemory((void *)ptidsl->AppData.bCMsgs2, (void *)rateparms.cMsgs2, 4);
++ shim_osMoveMemory((void *)ptidsl->AppData.bRMsgs2, (void *)rateparms.rMsgs2, 4);
++
++ ptidsl->AppData.atucVendorId = dslhal_support_byteSwap32((unsigned int)rateparms.atucVendorId);
++ ptidsl->AppData.lineLength = (unsigned int)dslhal_support_byteSwap16((unsigned short)rateparms.lineLength);
++ ptidsl->AppData.atucRevisionNum = rateparms.atucGhsRevisionNum;
++ ptidsl->AppData.usLineAttn = (ptidsl->AppData.bCMsgs2[3] >>2)&0x003f;
++ ptidsl->AppData.usMargin = (ptidsl->AppData.bCMsgs2[2])&0x001f;
++
++ /* Get the UpStream Connection Rate */
++ /* Based on the Bit Pattern Get the Opt# */
++ if((rateparms.cRates2 & 0x0f) == 0x01)
++ optIdxU = 0;
++ else if((rateparms.cRates2 & 0x0f) == 0x02)
++ optIdxU = 1;
++ else if((rateparms.cRates2 & 0x0f) == 0x04)
++ optIdxU = 2;
++ else if((rateparms.cRates2 & 0x0f) == 0x08)
++ optIdxU = 3;
++ else
++ optIdxU = -1;
++ dprintf(5, "optIdxU=%d\n", optIdxU);
++ /* Obtain the US Rates using Opt# and CRates1 Table */
++ /* Rate(US) = [Bf(LS0) + Bi(LS0)]*32 */
++ if(ptidsl->AppData.dsl_modulation <= DSLTRAIN_GLITE_MODE)
++ ptidsl->AppData.USConRate = ((rateparms.cRates1[optIdxU][CRATES1_BF_LS0] + rateparms.cRates1[optIdxU][CRATES1_BI_LS0]) * 32);
++ else
++ ptidsl->AppData.USConRate = dslhal_support_byteSwap16((unsigned short)rateparms.adsl2USRate);
++ ptidsl->AppData.USPeakCellRate = ptidsl->AppData.USConRate;
++
++ /* Get the DownStream Connection Rate */
++ /* Based on the Bit Pattern Get the Opt# */
++ if(((rateparms.cRates2 >> 4) & 0x0f) == 0x01)
++ optIdxD = 0;
++ else if(((rateparms.cRates2 >> 4) & 0x0f) == 0x02)
++ optIdxD = 1;
++ else if(((rateparms.cRates2 >> 4) & 0x0f) == 0x04)
++ optIdxD = 2;
++ else if(((rateparms.cRates2 >> 4) & 0x0f) == 0x08)
++ optIdxD = 3;
++ else
++ optIdxD = -1;
++ /* Obtain the DS Rates using Opt# and CRates1 Table */
++ /* Rate(DS) = [Bf(AS0) + Bi(AS0)]*32 */
++ if(ptidsl->AppData.dsl_modulation <= DSLTRAIN_GLITE_MODE)
++ ptidsl->AppData.DSConRate = (((rateparms.cRates1[optIdxD][CRATES1_BF_AS0]|((rateparms.cRates1[optIdxD][CRATES1_BF_DSRS]&0x80)<<1))+ (rateparms.cRates1[optIdxD][CRATES1_BI_AS0]|((rateparms.cRates1[optIdxD][CRATES1_BI_DSRS]&0x80)<<1)))* 32);
++ else
++ ptidsl->AppData.DSConRate = dslhal_support_byteSwap16((unsigned short)rateparms.adsl2DSRate);
++ dprintf(5, "ptidsl->AppData.wDSConRate=%d\n", ptidsl->AppData.DSConRate);
++ /* Determine which Path has Modem Trained with */
++ if((rateparms.cRates1[optIdxU][CRATES1_BF_LS0]) && (rateparms.cRates1[optIdxD][CRATES1_BF_AS0]))
++ ptidsl->AppData.TrainedPath = FAST_PATH;
++ else
++ ptidsl->AppData.TrainedPath = INTERLEAVED_PATH;
++
++ /* Set the mode in which the modem is trained */
++ ptidsl->AppData.TrainedMode = (unsigned int)rateparms.trainMode;
++ if(rateparms.trainMode == T1413_MODE)
++ ptidsl->AppData.TrainedMode = DSLTRAIN_T1413_MODE;
++ if(rateparms.trainMode == GDMT_MODE)
++ ptidsl->AppData.TrainedMode = DSLTRAIN_GDMT_MODE;
++
++ if(ptidsl->AppData.TrainedPath == FAST_PATH)
++ ptidsl->AppData.dsFastParityBytesPerSymbol = (rateparms.cRates1[optIdxU][CRATES1_BF_DSRS]&0x1f);
++ else
++ ptidsl->AppData.dsIntlvParityBytesPerSymbol = (rateparms.cRates1[optIdxU][CRATES1_BI_DSRS]&0x1f);
++ ptidsl->AppData.dsSymbolsPerCodeWord = (rateparms.cRates1[optIdxU][CRATES1_BFI_DSS]&0x1f);
++ ptidsl->AppData.dsInterleaverDepth = ((rateparms.cRates1[optIdxU][CRATES1_BFI_DSI])|((rateparms.cRates1[optIdxU][CRATES1_BFI_DSS]&0xc0)<<2));
++
++ if(ptidsl->AppData.TrainedPath == FAST_PATH)
++ ptidsl->AppData.usFastParityBytesPerSymbol = (rateparms.cRates1[optIdxU][CRATES1_BF_USRS]&0x1f);
++ else
++ ptidsl->AppData.usIntlvParityBytesPerSymbol = (rateparms.cRates1[optIdxU][CRATES1_BI_USRS]&0x1f);
++ ptidsl->AppData.usSymbolsPerCodeWord = (rateparms.cRates1[optIdxU][CRATES1_BFI_USS]&0x1f);
++ ptidsl->AppData.usInterleaverDepth = ((rateparms.cRates1[optIdxU][CRATES1_BFI_USI])|((rateparms.cRates1[optIdxU][CRATES1_BFI_USS]&0xc0)<<2));
++ }
++
++ /* get the Statistics itself */
++
++ dspOamSharedInterface.modemStats_p = (DEV_HOST_modemStatsDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.modemStats_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.modemStats_p,&StatisticsDef, sizeof(DEV_HOST_modemStatsDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++
++ /* Populate the Error Structure Variables */
++
++ /* US Interleave Path Error Statistics */
++
++ /* Change the endianness of the Pointer */
++ StatisticsDef.usErrorStatsIntlv_p = (DEV_HOST_errorStats_t *) dslhal_support_byteSwap32((unsigned int)StatisticsDef.usErrorStatsIntlv_p);
++
++ rc = dslhal_support_blockRead((PVOID)StatisticsDef.usErrorStatsIntlv_p,&usIntlvError, (sizeof(DEV_HOST_errorStats_t)));
++
++ if (rc)
++ return;
++
++ /* DS Interleave Path Error Statistics */
++
++ /* Change the endianness of the Pointer */
++ StatisticsDef.dsErrorStatsIntlv_p = (DEV_HOST_errorStats_t *) dslhal_support_byteSwap32((unsigned int)StatisticsDef.dsErrorStatsIntlv_p);
++
++ rc = dslhal_support_blockRead((PVOID)StatisticsDef.dsErrorStatsIntlv_p,&dsIntlvError, (sizeof(DEV_HOST_errorStats_t)));
++
++ if (rc)
++ return;
++
++ /* US Fast Path Error Statistics */
++
++ /* Change the endianness of the Pointer */
++ StatisticsDef.usErrorStatsFast_p = (DEV_HOST_errorStats_t *) dslhal_support_byteSwap32((unsigned int)StatisticsDef.usErrorStatsFast_p);
++
++ rc = dslhal_support_blockRead((PVOID)StatisticsDef.usErrorStatsFast_p,&usFastError, (sizeof(DEV_HOST_errorStats_t)));
++
++ if (rc)
++ return;
++
++
++ /* DS Fast Path Error Statistics */
++
++ /* Change the endianness of the Pointer */
++ StatisticsDef.dsErrorStatsFast_p = (DEV_HOST_errorStats_t *) dslhal_support_byteSwap32((unsigned int)StatisticsDef.dsErrorStatsFast_p);
++
++ rc = dslhal_support_blockRead((PVOID)StatisticsDef.dsErrorStatsFast_p,&dsFastError, (sizeof(DEV_HOST_errorStats_t)));
++
++ if (rc)
++ return;
++
++ if(ptidsl->AppData.bState > 2)
++ {
++ /* Get CRC Errors Stats for both US and DS */
++ ptidsl->AppData.dsICRC_errors = dslhal_support_byteSwap32((unsigned int)dsIntlvError.crcErrors);
++ ptidsl->AppData.dsFCRC_errors = dslhal_support_byteSwap32((unsigned int)dsFastError.crcErrors);
++ ptidsl->AppData.usICRC_errors = dslhal_support_byteSwap32((unsigned int)usIntlvError.crcErrors);
++ ptidsl->AppData.usFCRC_errors = dslhal_support_byteSwap32((unsigned int)usFastError.crcErrors);
++ /* Get FEC Errors Stats for both US and DS */
++ ptidsl->AppData.dsIFEC_errors = dslhal_support_byteSwap32((unsigned int)dsIntlvError.fecErrors);
++ ptidsl->AppData.dsFFEC_errors = dslhal_support_byteSwap32((unsigned int)dsFastError.fecErrors);
++ ptidsl->AppData.usIFEC_errors = dslhal_support_byteSwap32((unsigned int)usIntlvError.fecErrors);
++ ptidsl->AppData.usFFEC_errors = dslhal_support_byteSwap32((unsigned int)usFastError.fecErrors);
++ /* Get NCD Errors Stats for both US and DS */
++ ptidsl->AppData.dsINCD_error = dslhal_support_byteSwap32((unsigned int)dsIntlvError.ncdError);
++ ptidsl->AppData.dsFNCD_error = dslhal_support_byteSwap32((unsigned int)dsFastError.ncdError);
++ ptidsl->AppData.usINCD_error = dslhal_support_byteSwap32((unsigned int)usIntlvError.ncdError);
++ ptidsl->AppData.usFNCD_error = dslhal_support_byteSwap32((unsigned int)usFastError.ncdError);
++ /* Get LCD Errors Stats for both US and DS */
++ ptidsl->AppData.dsILCD_errors = dslhal_support_byteSwap32((unsigned int)dsIntlvError.lcdErrors);
++ ptidsl->AppData.dsFLCD_errors = dslhal_support_byteSwap32((unsigned int)dsFastError.lcdErrors);
++ ptidsl->AppData.usILCD_errors = dslhal_support_byteSwap32((unsigned int)usIntlvError.lcdErrors);
++ ptidsl->AppData.usFLCD_errors = dslhal_support_byteSwap32((unsigned int)usFastError.lcdErrors);
++ /*Get HEC Errors Stats for both US and DS */
++ ptidsl->AppData.dsIHEC_errors = dslhal_support_byteSwap32((unsigned int)dsIntlvError.hecErrors);
++ ptidsl->AppData.dsFHEC_errors = dslhal_support_byteSwap32((unsigned int)dsFastError.hecErrors);
++ ptidsl->AppData.usIHEC_errors = dslhal_support_byteSwap32((unsigned int)usIntlvError.hecErrors);
++ ptidsl->AppData.usFHEC_errors = dslhal_support_byteSwap32((unsigned int)usFastError.hecErrors);
++
++ /* Get LOS and SEF error Stats */
++ ptidsl->AppData.LOS_errors = dslhal_support_byteSwap32(StatisticsDef.losErrors);
++ ptidsl->AppData.SEF_errors = dslhal_support_byteSwap32(StatisticsDef.sefErrors);
++ ptidsl->AppData.coLosErrors = dslhal_support_byteSwap32(StatisticsDef.farEndLosErrors);
++ ptidsl->AppData.coRdiErrors = dslhal_support_byteSwap32(StatisticsDef.farEndRdiErrors);
++
++ dspOamSharedInterface.atmStats_p = (DEV_HOST_atmStats_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.atmStats_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.atmStats_p,&atmStats, sizeof(DEV_HOST_atmStats_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++
++ /* Populate the US/DS ATM Stats Variables */
++
++ /* US ATM Statistics */
++
++ /* Change the endianness of the Pointer */
++ atmStats.us0_p = (DEV_HOST_usAtmStats_t *) dslhal_support_byteSwap32((unsigned int)atmStats.us0_p);
++
++ rc = dslhal_support_blockRead((PVOID)atmStats.us0_p,&usAtmStats0, (sizeof(DEV_HOST_usAtmStats_t)));
++
++ if (rc)
++ return;
++
++ /* Change the endianness of the Pointer */
++ atmStats.us1_p = (DEV_HOST_usAtmStats_t *) dslhal_support_byteSwap32((unsigned int)atmStats.us1_p);
++
++ rc = dslhal_support_blockRead((PVOID)atmStats.us1_p,&usAtmStats1, (sizeof(DEV_HOST_usAtmStats_t)));
++
++ if (rc)
++ return;
++
++
++ /* DS ATM Statistics */
++
++ /* Change the endianness of the Pointer */
++ atmStats.ds0_p = (DEV_HOST_dsAtmStats_t *) dslhal_support_byteSwap32((unsigned int)atmStats.ds0_p);
++
++ rc = dslhal_support_blockRead((PVOID)atmStats.ds0_p,&dsAtmStats0, (sizeof(DEV_HOST_dsAtmStats_t)));
++
++ if (rc)
++ return;
++
++ /* Change the endianness of the Pointer */
++ atmStats.ds1_p = (DEV_HOST_dsAtmStats_t *) dslhal_support_byteSwap32((unsigned int)atmStats.ds1_p);
++
++ rc = dslhal_support_blockRead((PVOID)atmStats.ds1_p,&dsAtmStats1, (sizeof(DEV_HOST_dsAtmStats_t)));
++
++ if (rc)
++ return;
++ /* Get ATM Stats for both US and DS Channel 0*/
++ ptidsl->AppData.usAtm_count[0] = dslhal_support_byteSwap32(usAtmStats0.goodCount);
++ ptidsl->AppData.usIdle_count[0] = dslhal_support_byteSwap32(usAtmStats0.idleCount);
++#if SWTC
++ ptidsl->AppData.usPdu_count[0] = dslhal_support_byteSwap32(usAtmStats0.pduCount);
++#endif
++ ptidsl->AppData.dsGood_count[0] = dslhal_support_byteSwap32(dsAtmStats0.goodCount);
++ ptidsl->AppData.dsIdle_count[0] = dslhal_support_byteSwap32(dsAtmStats0.idleCount);
++#if SWTC
++ ptidsl->AppData.dsPdu_count[0] = dslhal_support_byteSwap32(dsAtmStats0.pduCount);
++#endif
++ ptidsl->AppData.dsBadHec_count[0] = dslhal_support_byteSwap32((dsAtmStats0.badHecCount));
++ ptidsl->AppData.dsOVFDrop_count[0] = dslhal_support_byteSwap32((dsAtmStats0.ovflwDropCount));
++
++ /* Get ATM Stats for both US and DS Channel 1*/
++ ptidsl->AppData.usAtm_count[1] = dslhal_support_byteSwap32(usAtmStats1.goodCount);
++ ptidsl->AppData.usIdle_count[1] = dslhal_support_byteSwap32(usAtmStats1.idleCount);
++#if SWTC
++ ptidsl->AppData.usPdu_count[1] = dslhal_support_byteSwap32(usAtmStats1.pduCount);
++#endif
++ ptidsl->AppData.dsGood_count[1] = dslhal_support_byteSwap32(dsAtmStats1.goodCount);
++ ptidsl->AppData.dsIdle_count[1] = dslhal_support_byteSwap32(dsAtmStats1.idleCount);
++#if SWTC
++ ptidsl->AppData.dsPdu_count[1] = dslhal_support_byteSwap32(dsAtmStats1.pduCount);
++#endif
++ ptidsl->AppData.dsBadHec_count[1] = dslhal_support_byteSwap32((dsAtmStats1.badHecCount));
++ ptidsl->AppData.dsOVFDrop_count[1] = dslhal_support_byteSwap32((dsAtmStats1.ovflwDropCount));
++
++
++ /* Determine the US and DS Superframe Count */
++
++ dspOamSharedInterface.dspWriteSuperFrameCnt_p = (DEV_HOST_dspWrSuperFrameCntDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.dspWriteSuperFrameCnt_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.dspWriteSuperFrameCnt_p,&SuperFrameCnt, sizeof(DEV_HOST_dspWrSuperFrameCntDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++
++ ptidsl->AppData.usSuperFrmCnt = dslhal_support_byteSwap32(SuperFrameCnt.wSuperFrameCntUstrm);
++ ptidsl->AppData.dsSuperFrmCnt = dslhal_support_byteSwap32(SuperFrameCnt.wSuperFrameCntDstrm);
++
++ /* Determine Frame Mode and Max Frame Mode */
++
++ dspOamSharedInterface.atucMsg_p = (DEV_HOST_msg_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.atucMsg_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.atucMsg_p,&atuc_msg, sizeof(DEV_HOST_msg_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++
++ ptidsl->AppData.FrmMode = (unsigned int)atuc_msg.framingMode;
++ ptidsl->AppData.MaxFrmMode = (unsigned int)atuc_msg.maxFrameMode;
++
++ /* Determine Gross Gain */
++
++ dspOamSharedInterface.aturMsg_p = (DEV_HOST_msg_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.aturMsg_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.aturMsg_p,&aturMsg, sizeof(DEV_HOST_msg_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++ ptidsl->AppData.grossGain = (unsigned int)aturMsg.grossGain;
++ /* Determine DS Line Attenuation & Margin */
++ dspOamSharedInterface.eocVar_p = (DEV_HOST_eocVarDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.eocVar_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.eocVar_p,&eocVar, sizeof(DEV_HOST_eocVarDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return;
++ }
++
++ ptidsl->AppData.dsLineAttn = (unsigned int)eocVar.lineAtten;
++ ptidsl->AppData.dsMargin = (unsigned int)eocVar.dsMargin;
++ }
++
++#if __HOST_FORINTERNALUSEONLY_R_H__
++ ptidsl->AppData.BER = dslhal_INTERNAL_computeAtmBitErrorRate(ptidsl);
++#endif
++ dprintf(5, "initstatistics done\n");
++ return;
++ }
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_disableLosAlarm(tidsl_t *ptidsl,unsigned int set)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction enables/disables all the LOS alarms
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * unsigned int set; //if set is TRUE: LOS Alarms are disabled else enabled
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ * NOTES: Currently not supported in any version other than MR4 Patch release..
++ *****************************************************************************************/
++unsigned int dslhal_api_disableLosAlarm(tidsl_t *ptidsl,unsigned int set)
++{
++ DEV_HOST_oamWrNegoParaDef_t NegoPara;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++ dprintf(5," dslhal_api_setTrainingMode()\n");
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.oamWriteNegoParams_p = (DEV_HOST_oamWrNegoParaDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.oamWriteNegoParams_p);
++
++ rc = dslhal_support_blockRead((PVOID) dspOamSharedInterface.oamWriteNegoParams_p,&NegoPara, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ if(set)
++ {
++ NegoPara.disableLosAlarm = TRUE;
++ /* NegoPara.marginMonitorTrning = TRUE;
++ NegoPara.marginMonitorShwtme = TRUE;*/
++ }
++ else
++ {
++ NegoPara.disableLosAlarm = FALSE;
++ /* NegoPara.marginMonitorTrning = FALSE;
++ NegoPara.marginMonitorShwtme = FALSE;*/
++ }
++
++ rc = dslhal_support_blockWrite(&NegoPara,(PVOID)dspOamSharedInterface.oamWriteNegoParams_p, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ dprintf(5," dslhal_api_disableLosAlarm() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setMarginThreshold(tidsl_t *ptidsl,int threshold)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction does sets the Margin threshold
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * int threshold
++ *
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setMarginThreshold(tidsl_t *ptidsl, int threshold)
++{
++ DEV_HOST_oamWrNegoParaDef_t NegoPara;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++
++ dprintf(5," dslhal_ctrl_setThreshold()\n");
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.oamWriteNegoParams_p = (DEV_HOST_oamWrNegoParaDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.oamWriteNegoParams_p);
++
++
++ rc = dslhal_support_blockRead((PVOID) dspOamSharedInterface.oamWriteNegoParams_p,&NegoPara, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ NegoPara.marginThreshold = threshold;
++
++ rc = dslhal_support_blockWrite(&NegoPara,dspOamSharedInterface.oamWriteNegoParams_p, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++
++ if(rc)
++ return DSLHAL_ERROR_MARGIN_API_FAILURE;
++
++ dprintf(5," dslhal_api_setThreshold() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setMonitorFlags(tidsl_t *ptidsl, unsigned int trainflag,unsigned int shwtflag)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction does sets the Margin monitoring flag
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * unsigned int trainflag
++ * unsigned int shwtflag
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setMarginMonitorFlags(tidsl_t *ptidsl,unsigned int trainflag,unsigned int shwtflag)
++{
++ DEV_HOST_oamWrNegoParaDef_t NegoPara;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++
++ dprintf(5," dslhal_ctrl_setMonitorFlags()\n");
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.oamWriteNegoParams_p = (DEV_HOST_oamWrNegoParaDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.oamWriteNegoParams_p);
++
++
++ rc = dslhal_support_blockRead((PVOID) dspOamSharedInterface.oamWriteNegoParams_p,&NegoPara, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ if (trainflag)
++ {
++ NegoPara.marginMonitorTrning = TRUE;
++ }
++ else
++ {
++ NegoPara.marginMonitorTrning = FALSE;
++ }
++ if (shwtflag)
++ {
++ NegoPara.marginMonitorShwtme = TRUE;
++ }
++ else
++ {
++ NegoPara.marginMonitorShwtme = FALSE;
++ }
++
++ rc = dslhal_support_blockWrite(&NegoPara,dspOamSharedInterface.oamWriteNegoParams_p, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if(rc)
++ return DSLHAL_ERROR_MARGIN_API_FAILURE;
++ dprintf(5," dslhal_api_setMonitorFlags() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setEocSerialNumber(tidsl_t *ptidsl,char *SerialNum)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction Sets the eoc Serial Number
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * char *SerialNum : Input eoc Serial Number
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setEocSerialNumber(tidsl_t *ptidsl,char *SerialNumber)
++{
++ DEV_HOST_eocVarDef_t eocVar;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++ dprintf(5," dslhal_api_setEocSerialNumber()\n");
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.eocVar_p = (DEV_HOST_eocVarDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.eocVar_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.eocVar_p,
++ &eocVar, sizeof(DEV_HOST_eocVarDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ shim_osMoveMemory(eocVar.serialNumber,SerialNumber,32);
++
++ rc= dslhal_support_blockWrite(&eocVar,dspOamSharedInterface.eocVar_p,sizeof(DEV_HOST_eocVarDef_t));
++ if(rc)
++ return DSLHAL_ERROR_EOCREG_API_FAILURE;
++ dprintf(5," dslhal_api_setEocSerialNumber() Done\n");
++
++ return DSLHAL_ERROR_NO_ERRORS;
++
++}
++
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setEocVendorId(tidsl_t *ptidsl,char *VendorID)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction Sets the eoc Vendor ID
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * char *VendorID : Input eoc Vendor ID
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setEocVendorId(tidsl_t *ptidsl,char *VendorID)
++{
++ DEV_HOST_oamWrNegoParaDef_t NegoPara;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++ dprintf(5," dslhal_api_setEocVendorId()\n");
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.oamWriteNegoParams_p = (DEV_HOST_oamWrNegoParaDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.oamWriteNegoParams_p);
++
++
++ rc = dslhal_support_blockRead((PVOID) dspOamSharedInterface.oamWriteNegoParams_p,&NegoPara, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ shim_osMoveMemory(NegoPara.gdmtVendorId,VendorID,8);
++ rc= dslhal_support_blockWrite(&NegoPara,dspOamSharedInterface.oamWriteNegoParams_p, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if(rc)
++ return DSLHAL_ERROR_EOCREG_API_FAILURE;
++
++ dprintf(5," dslhal_api_setEocVendorId() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setEocRevisionNumber(tidsl_t *ptidsl,char *RevNum)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction Sets the eoc Revision Number
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * char *RevNum : Input eoc Revision Number
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setEocRevisionNumber(tidsl_t *ptidsl,char *RevNumber)
++{
++
++ DEV_HOST_eocVarDef_t eocVar;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++ /*add for UR2 test */
++ UINT8 selfTestResults[2];
++ memset(selfTestResults,0x00,sizeof(selfTestResults));
++ /* add for UR2 test */
++ dprintf(5," dslhal_api_setEocRevisionNumber()\n");
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.eocVar_p = (DEV_HOST_eocVarDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.eocVar_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.eocVar_p,
++ &eocVar, sizeof(DEV_HOST_eocVarDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ shim_osMoveMemory(eocVar.revNumber,RevNumber,4);
++ /* add for UR2 test */
++ shim_osMoveMemory(eocVar.dummy,selfTestResults,2);
++ /* add for UR2 test */
++ rc=dslhal_support_blockWrite(&eocVar,dspOamSharedInterface.eocVar_p,sizeof(DEV_HOST_eocVarDef_t));
++ if(rc)
++ return DSLHAL_ERROR_EOCREG_API_FAILURE;
++ dprintf(5," dslhal_api_setEocRevisionNumber Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setAturConfig(tidsl_t *ptidsl,char *ATURConfig)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction Sets the eoc ATUR Config Register
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * char *ATURConfig : Input eoc ATUR Config Register
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setAturConfig(tidsl_t *ptidsl,char *ATURConfig)
++{
++
++ DEV_HOST_eocVarDef_t eocVar;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++ dprintf(5," dslhal_api_setAturConfig()\n");
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.eocVar_p = (DEV_HOST_eocVarDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.eocVar_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.eocVar_p,
++ &eocVar, sizeof(DEV_HOST_eocVarDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ shim_osMoveMemory(eocVar.aturConfig,ATURConfig,30);
++ rc= dslhal_support_blockWrite(&eocVar,dspOamSharedInterface.eocVar_p,sizeof(DEV_HOST_eocVarDef_t));
++ if(rc)
++ return DSLHAL_ERROR_EOCREG_API_FAILURE;
++ dprintf(5," dslhal_api_setAturConfig() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setRateAdaptFlag(tidsl_t *ptidsl,unsigned int flag)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the Rate Adapt Enable Flag
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int flag; //if flag = TRUE set rateadapt flag else reset it
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++unsigned int dslhal_api_setRateAdaptFlag(tidsl_t *ptidsl,unsigned int flag)
++{
++ DEV_HOST_msg_t aturMsg;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++ dprintf(5," dslhal_api_setRateAdaptFlag()\n");
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.aturMsg_p = (DEV_HOST_msg_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.aturMsg_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.aturMsg_p,
++ &aturMsg, sizeof(DEV_HOST_msg_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ if(flag)
++ aturMsg.rateAdapt = TRUE;
++ else
++ aturMsg.rateAdapt = FALSE;
++
++ rc= dslhal_support_blockWrite(&aturMsg,dspOamSharedInterface.aturMsg_p,sizeof(DEV_HOST_msg_t));
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ dprintf(5," dslhal_api_setRateAdaptFlag() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setTrellisFlag(tidsl_t *ptidsl,unsigned int flag)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the Trellis Coding Enable Flag
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int flag; // if flag = TRUE, set trellis flag else reset
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++unsigned int dslhal_api_setTrellisFlag(tidsl_t *ptidsl,unsigned int flag)
++{
++
++ DEV_HOST_msg_t aturMsg;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ DEV_HOST_oamWrNegoParaDef_t negoPara;
++ int rc;
++ dprintf(5," dslhal_api_setTrellisFlag()\n");
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.aturMsg_p = (DEV_HOST_msg_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.aturMsg_p);
++ rc += dslhal_support_blockRead((PVOID)dspOamSharedInterface.aturMsg_p,&aturMsg, sizeof(DEV_HOST_msg_t));
++ dspOamSharedInterface.oamWriteNegoParams_p = (DEV_HOST_oamWrNegoParaDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.oamWriteNegoParams_p);
++ rc += dslhal_support_blockRead((PVOID) dspOamSharedInterface.oamWriteNegoParams_p,&negoPara, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ if(flag)
++ {
++ aturMsg.trellis = TRUE;
++ negoPara.rMsgs1[2] |= 0x02;
++ }
++ else
++ {
++ aturMsg.trellis = FALSE;
++ negoPara.rMsgs1[2] &= 0xFD;
++ }
++ rc=0;
++ rc+=dslhal_support_blockWrite(&aturMsg,dspOamSharedInterface.aturMsg_p,sizeof(DEV_HOST_msg_t));
++ rc+= dslhal_support_blockWrite(&negoPara,dspOamSharedInterface.oamWriteNegoParams_p, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++
++ dprintf(5," dslhal_api_setTrellisFlag() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setMaxBitsPerCarrier(tidsl_t *ptidsl,unsigned int maxbits)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the Maximum bits per carrier value
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int maxbits : should be a value between 0-15
++*
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++unsigned int dslhal_api_setMaxBitsPerCarrier(tidsl_t *ptidsl,unsigned int maxbits)
++{
++
++ DEV_HOST_msg_t aturMsg;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++
++ dprintf(5," dslhal_api_setMaxBitsPerCarrier()\n");
++ if(maxbits>15)
++ {
++ dprintf(3,"Maximum Number of Bits per carrier cannot exceed 15!\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.aturMsg_p = (DEV_HOST_msg_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.aturMsg_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.aturMsg_p,
++ &aturMsg, sizeof(DEV_HOST_msg_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ aturMsg.maxBits = maxbits;
++
++ rc=dslhal_support_blockWrite(&aturMsg,dspOamSharedInterface.aturMsg_p,sizeof(DEV_HOST_msg_t));
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ dprintf(5," dslhal_api_setMaxBitsPerCarrier() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setMaxInterleaverDepth(tidsl_t *ptidsl,unsigned int maxdepth)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the Maximum Interleave Depth Supported
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int maxdepth : Should be between 0 and 3 depending on intlv buffer
++* size 64-512
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++unsigned int dslhal_api_setMaxInterleaverDepth(tidsl_t *ptidsl,unsigned int maxdepth)
++{
++ DEV_HOST_msg_t aturMsg;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ int rc;
++ dprintf(5," dslhal_api_setMaxInterleaverDepth()\n");
++ if(maxdepth>3)
++ {
++ dprintf(3,"Invalid Value for maximum interleave depth (must be <3)\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.aturMsg_p = (DEV_HOST_msg_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.aturMsg_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.aturMsg_p,
++ &aturMsg, sizeof(DEV_HOST_msg_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ aturMsg.maxIntlvDepth = maxdepth;
++
++ rc=dslhal_support_blockWrite(&aturMsg,dspOamSharedInterface.aturMsg_p,sizeof(DEV_HOST_msg_t));
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ dprintf(5," dslhal_api_setMaxInterleaverDepth() Done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_acknowledgeInterrupt()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_acknowledgeInterrupt(tidsl_t * ptidsl)
++{
++ unsigned int interruptSources=0;
++ /* Clear out the DSLSS Interrupt Registers to acknowledge Interrupt */
++ if(DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_SOURCE_REGISTER))&MASK_MAILBOX_INTERRUPTS)
++ {
++ DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_CLEAR_REGISTER))|=MASK_MAILBOX_INTERRUPTS;
++ dprintf(5,"Mailbox Interrupt \n");
++ }
++ if(DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_SOURCE_REGISTER))&MASK_BITFIELD_INTERRUPTS)
++ {
++ DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_CLEAR_REGISTER))|=MASK_BITFIELD_INTERRUPTS;
++ dprintf(5,"Bitfield Interrupt \n");
++ }
++ if(DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_SOURCE_REGISTER))&MASK_HEARTBEAT_INTERRUPTS)
++ {
++ DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_CLEAR_REGISTER))|=MASK_HEARTBEAT_INTERRUPTS;
++ dprintf(5,"HeartBeat Interrupt \n");
++ }
++ interruptSources = dslhal_support_parseInterruptSource(ptidsl);
++ if(interruptSources < 0)
++ return DSLHAL_ERROR_INTERRUPT_FAILURE;
++ else
++ return interruptSources;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_disableDspHybridSelect()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_disableDspHybridSelect(tidsl_t * ptidsl,unsigned int disable)
++{
++ int rc;
++ DEV_HOST_phyPerf_t phyPerf;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.phyPerf_p = (DEV_HOST_phyPerf_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.phyPerf_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.phyPerf_p,
++ &phyPerf, sizeof(DEV_HOST_phyPerf_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ if(disable==1)
++ {
++ phyPerf.disableDspHybridSelect_f = TRUE;
++ // hybrid_selected = 888;
++ }
++ else
++ {
++ phyPerf.disableDspHybridSelect_f = FALSE;
++ // hybrid_selected = 888;
++ }
++ rc=dslhal_support_blockWrite(&phyPerf,dspOamSharedInterface.phyPerf_p,sizeof(DEV_HOST_phyPerf_t));
++ if(rc)
++ return DSLHAL_ERROR_HYBRID_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_selectHybrid()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_selectHybrid(tidsl_t * ptidsl,unsigned int hybridNum)
++{
++ int rc;
++ DEV_HOST_phyPerf_t phyPerf;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ if(hybridNum<1||hybridNum>4)
++ {
++ dprintf(3,"Invalid Value for Hybrid Number \n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.phyPerf_p = (DEV_HOST_phyPerf_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.phyPerf_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.phyPerf_p,
++ &phyPerf, sizeof(DEV_HOST_phyPerf_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ phyPerf.hostSelectHybridNum = hybridNum;
++ rc=dslhal_support_blockWrite(&phyPerf,dspOamSharedInterface.phyPerf_p,sizeof(DEV_HOST_phyPerf_t));
++ if(rc)
++ return DSLHAL_ERROR_HYBRID_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_reportHybridMetrics()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_reportHybridMetrics(tidsl_t * ptidsl,int *metric)
++{
++ int rc,i;
++ DEV_HOST_phyPerf_t phyPerf;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ if(hybrid_selected>5)
++ {
++ dprintf(4,"Hybrid Metrics Not Yet Available \n");
++ }
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return (0-DSLHAL_ERROR_INVALID_PARAM);
++ }
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return (0-DSLHAL_ERROR_BLOCK_READ);
++ }
++
++ dspOamSharedInterface.phyPerf_p = (DEV_HOST_phyPerf_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.phyPerf_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.phyPerf_p,
++ &phyPerf, sizeof(DEV_HOST_phyPerf_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return (0-DSLHAL_ERROR_BLOCK_READ);
++ }
++ rc = sizeof(phyPerf.hybridCost);
++ for(i=0;i<(rc/4);i++)
++ {
++ metric[i] = dslhal_support_byteSwap32(phyPerf.hybridCost[i]);
++ }
++ return hybrid_selected;
++}
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_selectInnerOuterPair(tidsl_t *ptidsl,unsigned int pairSelect)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction selects inner/outer pair on RJ11.
++ *
++ * INPUT: PITIDSLHW_T *ptidsl , unsigned int pairSelect
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_selectInnerOuterPair(tidsl_t *ptidsl,unsigned int pairSelect)
++{
++ int rc;
++
++ dprintf(5, "dslhal_api_sendQuiet\n");
++ rc = dslhal_support_writeHostMailbox(ptidsl, HOST_RJ11SELECT, (unsigned int)pairSelect, 0, 0);
++ if(rc)
++ {
++ dprintf(1,"dslhal_api_sendQuiet failed\n");
++ return DSLHAL_ERROR_CTRL_API_FAILURE;
++ }
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_resetTrainFailureLog(tidsl_t *ptidsl)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction resets the failed state log stored
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_resetTrainFailureLog(tidsl_t *ptidsl)
++{
++
++ int rc;
++ dprintf(5, "dslhal_api_resetTrainFailureLog \n");
++ for(rc=0;rc<ptidsl->AppData.trainFails;rc++)
++ {
++ ptidsl->AppData.trainFailStates[rc]=0;
++ }
++ ptidsl->AppData.trainFails = 0;
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_configureLed()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_configureLed(tidsl_t * ptidsl,unsigned int idLed, unsigned int onOff)
++{
++ int rc;
++ DEV_HOST_modemEnvPublic_t modemEnv;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ if(idLed>2 || onOff>2)
++ {
++ dprintf(3,"Invalid input parameter \n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.modemEnvPublic_p = (DEV_HOST_modemEnvPublic_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.modemEnvPublic_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.modemEnvPublic_p,
++ &modemEnv, sizeof(DEV_HOST_modemEnvPublic_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ if(idLed==ID_DSL_LINK_LED)
++ {
++ modemEnv.overrideDslLinkLed_f = TRUE;
++ if(onOff!=2)
++ modemEnv.dslLinkLedState_f = onOff;
++ }
++ if(idLed==ID_DSL_ACT_LED)
++ {
++ modemEnv.overrideDslLinkLed_f = TRUE;
++ if(onOff!=2)
++ modemEnv.dslLinkLedState_f = onOff;
++ }
++ if(idLed==ID_RESTORE_DEFAULT_LED)
++ {
++ modemEnv.overrideDslLinkLed_f = FALSE;
++ modemEnv.overrideDslActLed_f = FALSE;
++ }
++ rc=dslhal_support_blockWrite(&modemEnv,dspOamSharedInterface.modemEnvPublic_p,sizeof(DEV_HOST_modemEnvPublic_t));
++ if(rc)
++ return DSLHAL_ERROR_MODEMENV_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_configureExternBert()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_configureExternBert(tidsl_t * ptidsl,unsigned int configParm, unsigned int parmVal)
++{
++ int rc;
++ DEV_HOST_modemEnvPublic_t modemEnv;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ if(configParm>1 || parmVal>1)
++ {
++ dprintf(3,"Invalid input parameter \n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.modemEnvPublic_p = (DEV_HOST_modemEnvPublic_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.modemEnvPublic_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.modemEnvPublic_p,
++ &modemEnv, sizeof(DEV_HOST_modemEnvPublic_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ if(configParm==0)
++ {
++ modemEnv.externalBert = parmVal;
++ }
++ if(configParm==1)
++ {
++ modemEnv.usBertPattern = parmVal;
++ }
++ rc=dslhal_support_blockWrite(&modemEnv,dspOamSharedInterface.modemEnvPublic_p,sizeof(DEV_HOST_modemEnvPublic_t));
++ if(rc)
++ return DSLHAL_ERROR_MODEMENV_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_configureAtmBert()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_configureAtmBert(tidsl_t * ptidsl,unsigned int configParm, unsigned int parmVal)
++{
++ int rc;
++ DEV_HOST_atmDsBert_t atmDsBert;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ if(configParm>1 || parmVal>1)
++ {
++ dprintf(3,"Invalid input parameter \n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.atmDsBert_p = (DEV_HOST_atmDsBert_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.atmDsBert_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.atmDsBert_p,
++ &atmDsBert, sizeof(DEV_HOST_atmDsBert_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ if(configParm==0)
++ {
++ atmDsBert.atmBertFlag = parmVal;
++ rc=dslhal_support_blockWrite(&atmDsBert,dspOamSharedInterface.atmDsBert_p,sizeof(DEV_HOST_atmDsBert_t));
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ }
++ if(configParm==1)
++ {
++ ptidsl->AppData.atmBertBitCountLow = atmDsBert.bitCountLow;
++ ptidsl->AppData.atmBertBitCountHigh = atmDsBert.bitCountHigh;
++ ptidsl->AppData.atmBertBitErrorCountLow = atmDsBert.bitErrorCountLow;
++ ptidsl->AppData.atmBertBitErrorCountHigh = atmDsBert.bitErrorCountHigh;
++ }
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_configureDgaspLpr()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Configures dying gasp LPR signal
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_configureDgaspLpr(tidsl_t * ptidsl,unsigned int configParm, unsigned int parmVal)
++{
++ int rc;
++ DEV_HOST_modemEnvPublic_t modemEnv;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ if(configParm>1 || parmVal>1)
++ {
++ dprintf(3,"Invalid input parameter \n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ if(!ptidsl)
++ {
++ dprintf(3, "Error: PTIDSL pointer invalid\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.modemEnvPublic_p = (DEV_HOST_modemEnvPublic_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.modemEnvPublic_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.modemEnvPublic_p,
++ &modemEnv, sizeof(DEV_HOST_modemEnvPublic_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ if(configParm==0)
++ {
++ modemEnv.dGaspLprIndicator_f = parmVal;
++ }
++ if(configParm==1)
++ {
++ modemEnv.overrideDspLprGasp_f = parmVal;
++ }
++ rc=dslhal_support_blockWrite(&modemEnv,dspOamSharedInterface.modemEnvPublic_p,sizeof(DEV_HOST_modemEnvPublic_t));
++ if(rc)
++ return DSLHAL_ERROR_MODEMENV_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_genericDspRead()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Reads from a Generic Location in the DSP Host Interface
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_genericDspRead(tidsl_t * ptidsl,unsigned int offset1, unsigned int offset2,
++ unsigned int offset3, unsigned char *localBuffer, unsigned int numBytes)
++{
++ int rc=0;
++ unsigned int hostIfLoc,structLoc,elementLoc;
++ hostIfLoc = (unsigned int)ptidsl->pmainAddr;
++ if(numBytes<=0 || !localBuffer || !ptidsl)
++ {
++ dprintf(3,"Invalid input parameter \n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ rc += dslhal_support_blockRead((PVOID)(hostIfLoc+sizeof(int)*offset1), &structLoc,sizeof(int));
++ structLoc = dslhal_support_byteSwap32(structLoc);
++ rc += dslhal_support_blockRead((PVOID)(structLoc+sizeof(int)*offset2), &elementLoc,sizeof(int));
++ elementLoc = dslhal_support_byteSwap32(elementLoc);
++ dprintf(3,"Host IF Location: 0x%x Struct1 Location: 0x%x Element Location: 0x%x \n",hostIfLoc, structLoc, elementLoc);
++ rc += dslhal_support_blockRead((PVOID)(elementLoc+(offset3*4)), localBuffer,numBytes);
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_genericDspWrite()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Writes to a Generic Location in the DSP Host Interface
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_genericDspWrite(tidsl_t * ptidsl,unsigned int offset1, unsigned int offset2,
++ unsigned int offset3, unsigned char *localBuffer, unsigned int numBytes)
++{
++
++ int rc=0;
++ unsigned int hostIfLoc,structLoc,elementLoc;
++ hostIfLoc = (unsigned int)ptidsl->pmainAddr;
++ if(numBytes<=0 || !localBuffer || !ptidsl)
++ {
++ dprintf(3,"Invalid input parameter \n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ rc += dslhal_support_blockRead((PVOID)(hostIfLoc+(offset1*4)), &structLoc,4);
++ structLoc = dslhal_support_byteSwap32(structLoc);
++ rc += dslhal_support_blockRead((PVOID)(structLoc+(offset2*4)), &elementLoc,4);
++ elementLoc = dslhal_support_byteSwap32(elementLoc);
++ dprintf(3,"Host IF Location: 0x%x Struct1 Location: 0x%x Element Location: 0x%x \n",hostIfLoc, structLoc, elementLoc);
++ rc += dslhal_support_blockWrite(localBuffer,(PVOID)(elementLoc+(offset3*4)),numBytes);
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_dspInterfaceRead()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Reads from a Generic Location in the DSP Host Interface
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_dspInterfaceRead(tidsl_t * ptidsl,unsigned int baseAddr, unsigned int numOffsets,
++ unsigned int *offsets, unsigned char *localBuffer, unsigned int numBytes)
++{
++ int rc=0, off=0;
++ unsigned int prevAddr,currAddr;
++ prevAddr = baseAddr;
++ if(numBytes<=0 || !localBuffer || !ptidsl || !offsets)
++ {
++ dprintf(3,"Invalid input parameter \n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ for(off=0;off<numOffsets-1;off++)
++ {
++ rc += dslhal_support_blockRead((PVOID)(prevAddr+(4*offsets[off])), &currAddr,4);
++ currAddr = dslhal_support_byteSwap32(currAddr);
++ prevAddr = currAddr;
++ dprintf(5,"Curr Addr = 0x%x Current Level: %d \n",currAddr,off);
++ }
++ currAddr = currAddr + offsets[numOffsets-1]*4;
++ rc += dslhal_support_blockRead((PVOID)(currAddr),localBuffer,numBytes);
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_dspInterfaceWrite()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Writes to a Generic Location in the DSP Host Interface
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_dspInterfaceWrite(tidsl_t * ptidsl,unsigned int baseAddr, unsigned int numOffsets,
++ unsigned int *offsets,unsigned char *localBuffer, unsigned int numBytes)
++{
++
++ int rc=0, off=0;
++ unsigned int prevAddr,currAddr;
++ prevAddr = baseAddr;
++ if(numBytes<=0 || !localBuffer || !ptidsl || !offsets)
++ {
++ dprintf(3,"Invalid input parameter \n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++ for(off=0;off<numOffsets-1;off++)
++ {
++ rc += dslhal_support_blockRead((PVOID)(prevAddr+(4*offsets[off])), &currAddr,4);
++ currAddr = dslhal_support_byteSwap32(currAddr);
++ prevAddr = currAddr;
++ dprintf(5,"Curr Addr = 0x%x Current Level: %d \n",currAddr,off);
++ }
++ currAddr = currAddr + offsets[numOffsets-1]*4;
++ rc += dslhal_support_blockWrite(localBuffer,(PVOID)(currAddr),numBytes);
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_sendMailboxCommand(tidsl_t *ptidsl, unsigned int cmd)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the passed mailbox command to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * unsigned int cmd
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++/* Function is commented out for now since, its not tested */
++ /*unsigned int dslhal_api_sendMailboxCommand(tidsl_t *ptidsl, unsigned int cmd)
++{
++ int rc;
++
++ dprintf(5, "dslhal_api_sendMailboxCommand\n");
++ rc = dslhal_support_writeHostMailbox(ptidsl, cmd, 0, 0, 0);
++ if(rc)
++ {
++ dprintf(1,"dslhal_api_sendMailboxCommand failed\n");
++ return DSLHAL_ERROR_CTRL_API_FAILURE;
++ }
++ return DSLHAL_ERROR_NO_ERRORS;
++} */
++
++
+diff -urN linux.old/drivers/atm/sangam_atm/dsl_hal_api.h linux.dev/drivers/atm/sangam_atm/dsl_hal_api.h
+--- linux.old/drivers/atm/sangam_atm/dsl_hal_api.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/dsl_hal_api.h 2005-08-23 04:46:50.097843696 +0200
+@@ -0,0 +1,1721 @@
++#ifndef __DSL_HAL_API_H__
++#define __DSL_HAL_API_H__ 1
++/*******************************************************************************
++* FILE PURPOSE: DSL HAL to Application Interface for Sangam
++*
++********************************************************************************
++* FILE NAME: dsl_application_interface.h
++*
++* DESCRIPTION:
++* DSL-Application Interface Structures
++*
++*
++* By: Ramakrishnan Parasuraman
++*
++* (C) Copyright 2003, Texas Instruments, Inc.
++* History
++* Data Version By Notes
++* 06Feb03 0.00 RamP Initial Version Written
++* 07Apr03 0.01 RamP Commented out typedefs
++* 09Apr03 0.02 RamP Added deviceContext and extended
++* dspVer to include bugfixes
++* 14Apr03 0.03 RamP Added stateTransition to structure
++* 16Apr03 0.04 RamP Removed typedefs; changed dspVer
++* 22Apr03 0.05 RamP Moved acknowledgeInterrupt from
++* (alpha) support module into this
++* 24Apr03 0.06 RamP Moved the RSTATE enum from register
++*
++* 28Apr03 0.07 RamP Added additional parameter to the
++* (alpha +) handleInterrupt function for intrSrc
++* 14May03 0.08 RamP Added hybrid switching APIs
++* (alpha ++) Added statistics fields in AppData
++* Added netService identifier
++* 20May03 0.09 RamP Added Inner/Outer pair API support.
++* Added dying gasp message.
++* 29May03 0.10 RamP Added coProfile structure
++* 04Jun03 0.11 RamP Added margin per tone statistics,
++* Added timing counters, added train
++* failure functions,added config flags
++* 06Jun03 0.12 RamP Added LED, STM Bert, dGasp LPR
++* config API functions
++* 09Jun03 0.13 RamP Added ATM Bert function, CO stats
++* Moved stateTransition to ITIDSLHW
++* (Beta) Moved configFlag to ITIDSLHW,
++* Cleaned up fifoInfo structure
++* Added US/DS R/S FEC parameters
++* 21Aug03 0.14 RamP Added g.hs message buffer, us/ds
++* bits n gains table, negoMsgs struct
++* (act) bitswap stucts/indices, trainstate,
++* Added functions for advanced config
++* Added gross gain and line length
++* 29Sep03 0.15 RamP Added tokens for advanced config
++* module api functions
++* 12Oct03 0.16 RamP Added adsl2Msgs structure with worst
++* case size for variable length msgs
++* Added API function prototypes
++* 21Oct03 0.17 RamP Added typedef for current modem
++* user settings
++* 28Oct03 0.18 RamP Added function to config blackout
++* bitmap in the RMSGPCB message
++* 20Nov03 0.19 RamP Added functions for generic and
++* host interface read - write
++* 24Nov03 0.20 RamP Added enum for detailed state track
++* Added element for state bit fields
++* Addded rState for encoded main state
++* Added blackout valid flag
++* 26Dec03 0.21 RamP Added defines for oamFeature masks
++* 30Dec03 0.22 RamP Increased sizes for cMsgPcb,RMsgPcb
++* to incorporate DELT mode messages
++* 30Dec03 0.23 RamP Added generic mailbox command fxn
++*******************************************************************************/
++
++#ifdef INTERNAL_BUILD
++#include <dsl_hal_api_pvt.h>
++#endif
++
++#define NUM_PAGES 4
++#define OAMFEATURE_AUTORETRAIN_MASK 0x00000001
++#define OAMFEATURE_TC_SYNC_DETECT_MASK 0x00000002
++#define OAMFEATURE_EOCAOC_INTERRUPT_MASK 0x00000004
++#define OAMFEATURE_CONS_DISP_DISABLE_MASK 0x00000008
++#define OAMFEATURE_GHSMSG_INTERRUPT_MASK 0x00000010
++
++typedef struct tagTIOIDINFO
++{
++ unsigned int bState; /* addr->bDSPATURState */
++ unsigned int USConRate; /* US Conection Rates */
++ unsigned int DSConRate; /* DS Connection Rates */
++ unsigned int USPayload; /* ennic_tx_pullup*/
++ unsigned int DSPayload; /* ennic_indicate_receive_packet*/
++ unsigned int FrmMode; /* addr->atur_msg.framing_mode*/
++ unsigned int MaxFrmMode;
++ unsigned int TrainedPath; /* Status of the Modem in which trained (Fast or Interleaved Path) */
++ unsigned int TrainedMode; /* Status of the mode in which the modem is trained (G.dmt, T1.413, etc) */
++
++ /* Superframe Count */
++ unsigned int usSuperFrmCnt; /* Num of US Superframes */
++ unsigned int dsSuperFrmCnt; /* Num of DS Superframes */
++
++ /* LOS & SEF Stats */
++ unsigned int LOS_errors; /* Num of ADSL frames where loss-of-sync */
++ unsigned int SEF_errors; /* Num of severly errored ADSL frames - LOS > MAXBADSYNC ADSL frames */
++ unsigned int coLosErrors; /* CO LOS Defects */
++ unsigned int coRdiErrors; /* CO RDI defects */
++ /* CRC Stats */
++ unsigned int usICRC_errors; /* Num of Upstream CRC errored ADSL frames on Interleaved Path */
++ unsigned int usFCRC_errors; /* Num of Upstream CRC errored ADSL frames on Fast Path */
++ unsigned int dsICRC_errors; /* Num of Downstream CRC errored ADSL frames on Interleaved Path */
++ unsigned int dsFCRC_errors; /* Num of Downstream CRC errored ADSL frames on Fast Path */
++
++ /* FEC Stats */
++ unsigned int usIFEC_errors; /* Num of Upstream FEC errored (corrected) ADSL frames on Interleaved Path */
++ unsigned int usFFEC_errors; /* Num of Upstream FEC errored (corrected) ADSL frames on Fast Path */
++ unsigned int dsIFEC_errors; /* Num of Downstream FEC errored (corrected) ADSL frames on Interleaved Path */
++ unsigned int dsFFEC_errors; /* Num of Downstream FEC errored (corrected) ADSL frames on Fast Path */
++
++ /* NCD Stats */
++ unsigned int usINCD_error; /* UpStream No Cell Delineation on Interleaved Path */
++ unsigned int usFNCD_error; /* UpStream No Cell Delineation on Fast Path */
++ unsigned int dsINCD_error; /* Downstream No Cell Delineation on Interleaved Path */
++ unsigned int dsFNCD_error; /* Downstream No Cell Delineation on Fast Path */
++
++ /* LCD Stats */
++ unsigned int usILCD_errors; /* UpStream Loss of Cell Delineation (within the same connection) on Interleaved Path */
++ unsigned int usFLCD_errors; /* UpStream Loss of Cell Delineation (within the same connection) on Fast Path */
++ unsigned int dsILCD_errors; /* Downstream Loss of Cell Delineation (within the same connection) on Interleaved Path */
++ unsigned int dsFLCD_errors; /* Downstream Loss of Cell Delineation (within the same connection) on Fast Path */
++
++ /* HEC Stats */
++ unsigned int usIHEC_errors; /* Num of Upstream HEC errored ADSL frames on Interleaved Path */
++ unsigned int usFHEC_errors; /* Num of Upstream HEC errored ADSL frames on Fast Path */
++ unsigned int dsIHEC_errors; /* Num of Downstream HEC errored ADSL frames on Interleaved Path */
++ unsigned int dsFHEC_errors; /* Num of Downstream HEC errored ADSL frames on Fast Path */
++
++ /* Upstream ATM Stats */
++ unsigned int usAtm_count[2]; /* Upstream Good Cell Count */
++ unsigned int usIdle_count[2]; /* Upstream Idle Cell Count */
++ unsigned int usPdu_count[2]; /* UpStream PDU Count */
++
++ /* Downstream ATM Stats */
++ unsigned int dsGood_count[2]; /* Downstream Good Cell Count */
++ unsigned int dsIdle_count[2]; /* Downstream Idle Cell Count */
++ unsigned int dsBadHec_count[2]; /* Downstream Bad Hec Cell Count */
++ unsigned int dsOVFDrop_count[2]; /* Downstream Overflow Dropped Cell Count */
++ unsigned int dsPdu_count[2]; /* Downstream PDU Count */
++ /* (only looks for end of pdu on good atm cells received, */
++ /* not on Bad_Hec or Overflow cell) */
++
++ unsigned int dsLineAttn; /* DS Line Attenuation */
++ unsigned int dsMargin; /* Measured DS MArgin */
++
++ unsigned int usLineAttn;
++ unsigned int usMargin;
++
++ unsigned char bCMsgs1[6];
++ unsigned char bRMsgs1[6];
++ unsigned char bCRates2;
++ unsigned char bRRates2;
++ unsigned char bRRates1[4][11];
++ unsigned char bCMsgs2[4];
++ unsigned char bCRates1[4][30];
++ unsigned char bRMsgs2[4];
++
++ unsigned int USPeakCellRate;
++
++ unsigned int dsl_status;
++ unsigned int dsl_modulation;
++ unsigned char dsl_ghsRxBuf[10][64];
++ unsigned char dsl_GHS_msg_type[2];
++
++ int TxVCs[12];
++ int RxVCs[12];
++
++ unsigned int vci_vpi_val;
++
++ unsigned char BitAllocTblDstrm[256];
++ unsigned char BitAllocTblUstrm[32];
++ signed char marginTblDstrm[256];
++ unsigned char rBng[512];
++ unsigned char cBng[126];
++ int usTxPower;
++ int dsTxPower;
++ short rxSnrPerBin0[256];
++ short rxSnrPerBin1[256];
++ short rxSnrPerBin2[256];
++
++ unsigned int StdMode;
++ unsigned int atucVendorId;
++ unsigned char currentHybridNum;
++ unsigned char atucRevisionNum;
++ unsigned int trainFails;
++ unsigned int trainFailStates[30];
++ unsigned int idleTick;
++ unsigned int initTick;
++ unsigned int showtimeTick;
++ unsigned char dsFastParityBytesPerSymbol;
++ unsigned char dsIntlvParityBytesPerSymbol;
++ unsigned char dsSymbolsPerCodeWord;
++ unsigned int dsInterleaverDepth;
++ unsigned char usFastParityBytesPerSymbol;
++ unsigned char usIntlvParityBytesPerSymbol;
++ unsigned char usSymbolsPerCodeWord;
++ unsigned int usInterleaverDepth;
++ unsigned int atmBertBitCountLow;
++ unsigned int atmBertBitCountHigh;
++ unsigned int atmBertBitErrorCountLow;
++ unsigned int atmBertBitErrorCountHigh;
++ unsigned int lineLength;
++ unsigned int grossGain;
++ int rxNoisePower0[256];
++ int rxNoisePower1[256];
++}TIOIDINFO,*PTIOIDINFO;
++
++typedef struct{
++ unsigned char bCMsgs1[6];
++ unsigned char bCRates2;
++ unsigned char bRRates2;
++ unsigned char bRRates1[4][11];
++ unsigned char bCMsgs2[4];
++ unsigned char bCRates1[4][30];
++ unsigned char bCRatesRA[4][30];
++ unsigned char bRMsgs2[4];
++ unsigned char bRRatesRA[4];
++ unsigned char bRMsgsRA[12];
++ unsigned char bCMsgsRA[6];
++}negoMsgs;
++
++typedef struct{
++ unsigned char cMsgFmt[2];
++ unsigned char rMsgFmt[2];
++ unsigned char cMsgPcb[12];
++ unsigned char rMsgPcb[70];
++ unsigned char dummy1[2];
++ unsigned char cMsg1[40];
++ unsigned char rMsg1[4];
++ unsigned char cMsg2[8];
++ unsigned char rMsg2[64];
++ unsigned char cParams[264];
++ unsigned char rParams[2088];
++ unsigned short cMsgPcbLen;
++ unsigned short rMsgPcbLen;
++ unsigned short cMsg1Len;
++ unsigned short rMsg1Len;
++ unsigned short cMsg2Len;
++ unsigned short rMsg2Len;
++ unsigned short cParamsLen;
++ unsigned short rParamsLen;
++}adsl2Msgs;
++
++typedef struct{
++ unsigned char rMsg1Ld[16];
++ unsigned char rMsg2Ld[260];
++ unsigned char rMsg3Ld[260];
++ unsigned char rMsg4Ld[260];
++ unsigned char rMsg5Ld[260];
++ unsigned char rMsg6Ld[260];
++ unsigned char rMsg7Ld[260];
++ unsigned char rMsg8Ld[260];
++ unsigned char rMsg9Ld[260];
++ unsigned char cMsg1Ld[16];
++ unsigned char cMsg2Ld[260];
++ unsigned char cMsg3Ld[132];
++ unsigned char cMsg4Ld[68];
++ unsigned char cMsg5Ld[68];
++ unsigned short rMsg1LdLen;
++ unsigned short rMsgxLdLen;
++ unsigned short cMsg1LdLen;
++ unsigned short cMsg2LdLen;
++ unsigned short cMsg3LdLen;
++ unsigned short cMsg4LdLen;
++ unsigned short cMsg5LdLen;
++ unsigned short dummy8;
++}adsl2DeltMsgs;
++
++typedef struct{
++ unsigned char trellisFlag;
++ unsigned char rateAdaptFlag;
++ unsigned char marginMonitorTraining;
++ unsigned char marginMonitorShowtime;
++ signed char marginThreshold;
++ unsigned char disableLosFlag;
++ unsigned char aturConfig[30];
++ unsigned char eocVendorId[8];
++ unsigned char eocSerialNumber[32];
++ unsigned char eocRevisionNumber[4];
++}currentPhySettings;
++
++
++typedef struct
++{
++ unsigned int PmemStartWtAddr; /* source address in host memory */
++ unsigned int OverlayXferCount; /* number of 32bit words to be transfered */
++ unsigned int BinAddr; /* destination address in dsp's pmem */
++ unsigned int overlayHostAddr;
++ unsigned int olayPageCrc32;
++ unsigned int SecOffset;
++} OlayDP_Def;
++
++typedef struct
++{
++ unsigned int timeStamp; /* TimeStp revision */
++ unsigned char major; /* Major revision */
++ unsigned char minor; /* Minor revision */
++ unsigned char bugFix; /* BugFix revision */
++ unsigned char buildNum; /* BuildNum revision */
++ unsigned char reserved; /* for future use */
++}dspVer;
++
++typedef struct{
++ unsigned char major;
++ unsigned char minor;
++ unsigned char bugfix;
++ unsigned char buildNum;
++ unsigned int timeStamp;
++}dslVer;
++
++typedef struct{
++ unsigned char bitSwapCommand[6];
++ unsigned char bitSwapBinNum[6];
++ unsigned char bitSwapSFrmCnt;
++}dslBitSwapDef;
++
++typedef struct{
++ unsigned int aturState;
++ unsigned int subStateIndex;
++ unsigned int timeStamp;
++}trainStateInfo;
++
++typedef struct{
++ unsigned char ctrlBits;
++ unsigned char infoBits;
++}eocMessageDef;
++
++enum
++{
++ RSTATE_TEST,
++ RSTATE_IDLE,
++ RSTATE_INIT,
++ RSTATE_HS,
++ RSTATE_RTDL,
++ RSTATE_SHOWTIME,
++};
++
++typedef enum
++{
++ ATU_RZERO1 = 100,
++ ATU_RTEST = 101,
++ ATU_RIDLE = 102,
++ ATU_RINIT = 103,
++ ATU_RRESET = 104,
++ GDMT_NSFLR = 105,
++ GDMT_TONE = 106,
++ GDMT_SILENT = 107,
++ GDMT_NEGO = 108,
++ GDMT_FAIL = 109,
++ GDMT_ACKX = 110,
++ GDMT_QUIET2 = 111,
++ ATU_RZERO2 = 200,
++ T1413_NSFLR = 201,
++ T1413_ACTREQ = 202,
++ T1413_ACTMON = 203,
++ T1413_FAIL = 204,
++ T1413_ACKX = 205,
++ T1413_QUIET2 = 206,
++ ATU_RQUIET2 = 207,
++ ATU_RREVERB1 = 208,
++ ATU_RQUIET3 = 209,
++ ATU_RECT = 210,
++ ATU_RREVERB2 = 211,
++ ATU_RSEGUE1 = 212,
++ ATU_RREVERB3 = 213,
++ ATU_RSEGUE2 = 214,
++ ATU_RRATES1 = 215,
++ ATU_RMSGS1 = 216,
++ ATU_RMEDLEY = 217,
++ ATU_RREVERB4 = 218,
++ ATU_RSEGUE3 = 219,
++ ATU_RMSGSRA = 220,
++ ATU_RRATESRA = 221,
++ ATU_RREVERBRA = 222,
++ ATU_RSEGUERA = 223,
++ ATU_RMSGS2 = 224,
++ ATU_RRATES2 = 225,
++ ATU_RREVERB5 = 226,
++ ATU_RSEGUE4 = 227,
++ ATU_RBNG = 228,
++ ATU_RREVERB6 = 229,
++ ATU_RSHOWTIME = 230,
++ ATU_RZERO3 = 300,
++ ADSL2_QUIET1 = 301,
++ ADSL2_COMB1 = 302,
++ ADSL2_QUIET2 = 303,
++ ADSL2_COMB2 = 304,
++ ADSL2_ICOMB1 = 305,
++ ADSL2_LINEPROBE = 306,
++ ADSL2_QUIET3 = 307,
++ ADSL2_COMB3 = 308,
++ ADSL2_ICOMB2 = 309,
++ ADSL2_RMSGFMT = 310,
++ ADSL2_RMSGPCB = 311,
++ ADSL2_REVERB1 = 312,
++ ADSL2_QUIET4 = 313,
++ ADSL2_REVERB2 = 314,
++ ADSL2_QUIET5 = 315,
++ ADSL2_REVERB3 = 316,
++ ADSL2_ECT = 317,
++ ADSL2_REVERB4 = 318,
++ ADSL2_SEGUE1 = 319,
++ ADSL2_REVERB5 = 320,
++ ADSL2_SEGUE2 = 321,
++ ADSL2_RMSG1 = 322,
++ ADSL2_MEDLEY = 323,
++ ADSL2_EXCHANGE = 324,
++ ADSL2_RMSG2 = 325,
++ ADSL2_REVERB6 = 326,
++ ADSL2_SEGUE3 = 327,
++ ADSL2_RPARAMS = 328,
++ ADSL2_REVERB7 = 329,
++ ADSL2_SEGUE4 = 330,
++ ATU_RZERO4 = 400,
++ DELT_SEGUE1 = 401,
++ DELT_REVERB5 = 402,
++ DELT_SEGUE2 = 403,
++ DELT_EXCHANGE = 404,
++ DELT_SEGUELD = 405,
++ DELT_RMSGLD = 406,
++ DELT_QUIET1LD = 407,
++ DELT_QUIET2LD = 408,
++ DELT_RACK1 = 409,
++ DELT_RNACK1 = 410,
++ DELT_QUIETLAST = 411
++} modemStates_t;
++
++enum
++{
++ DSLTRAIN_NO_MODE,
++ DSLTRAIN_MULTI_MODE,
++ DSLTRAIN_T1413_MODE,
++ DSLTRAIN_GDMT_MODE,
++ DSLTRAIN_GLITE_MODE
++};
++
++enum
++{
++ ID_RESTORE_DEFAULT_LED,
++ ID_DSL_LINK_LED,
++ ID_DSL_ACT_LED
++};
++
++typedef struct _ITIDSLHW
++{
++ /* struct _TIDSL_IHwVtbl * pVtbl; */
++ unsigned char* fwimage;
++ void* pmainAddr;
++ void* pOsContext;
++ unsigned int ReferenceCount;
++ unsigned int netService;
++
++ int InitFlag;
++
++ int imagesize;
++
++ unsigned int lConnected;
++ unsigned int bStatisticsInitialized;
++ unsigned int rState;
++ unsigned int bShutdown;
++ unsigned int blackOutValid_f;
++ unsigned char blackOutBits[64];
++ unsigned int bAutoRetrain;
++ volatile unsigned int bOverlayPageLoaded;
++ unsigned int stateTransition;
++ unsigned int configFlag;
++ unsigned int dsBitSwapInx;
++ unsigned int usBitSwapInx;
++ unsigned int trainStateInx;
++ unsigned int usEocMsgInx;
++ unsigned int dsEocMsgInx;
++ unsigned int reasonForDrop;
++ TIOIDINFO AppData;
++ dspVer dspVer;
++
++ OlayDP_Def olayDpPage[NUM_PAGES];
++ OlayDP_Def coProfiles;
++ OlayDP_Def constDisplay;
++ dslBitSwapDef dsBitSwap[30];
++ dslBitSwapDef usBitSwap[30];
++ trainStateInfo trainHistory[120];
++ eocMessageDef usEocMsgBuf[30];
++ eocMessageDef dsEocMsgBuf[30];
++ adsl2Msgs adsl2TrainingMessages;
++ adsl2DeltMsgs adsl2DiagnosticMessages;
++ unsigned int modemStateBitField[4];
++#ifdef INTERNAL_BUILD
++ internalParameters internalVars;
++#endif
++} ITIDSLHW_T, *PITIDSLHW_T, tidsl_t;
++
++
++/**********************************************************************************
++* API proto type defines
++**********************************************************************************/
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_dslStartup
++*
++*******************************************************************************************
++* DESCRIPTION: Entry point to initialize and load ax5 daughter board
++*
++* INPUT: PITIDSLHW_T *ppIHw
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++*
++* Notes: external function osAllocateMemory(), osZeroMemory(), osLoadFWImage() are required
++*****************************************************************************************/
++int dslhal_api_dslStartup
++(
++ PITIDSLHW_T *ppIHw
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_gatherStatistics
++*
++*********************************************************************************************
++* DESCRIPTION: Read statistical infromation from ax5 modem daugter card.
++* Input: tidsl_t *ptidsl
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++
++void dslhal_api_gatherStatistics
++(
++ tidsl_t * ptidsl
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_initStatistics
++*
++*********************************************************************************************
++* DESCRIPTION: init statistical infromation of ax5 modem daugter card.
++*
++* Input: tidsl_t *ptidsl
++*
++* Return: NULL
++*
++********************************************************************************************/
++
++void dslhal_api_initStatistics
++(
++ tidsl_t * ptidsl
++);
++
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_getDslDriverVersion
++*
++*******************************************************************************************
++* DESCRIPTION: This routine supply DSL Driver version.
++*
++* INPUT: tidsl_t * ptidsl
++* void *pVer, DSP Driver Version Pointer
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++* Note: See verdef_u.h for version structure definition.
++*****************************************************************************************/
++
++void dslhal_api_getDslHalVersion
++(
++ void *pVer
++);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_dslShutdown
++*
++*******************************************************************************************
++* DESCRIPTION: routine to shutdown ax5 modem and free the resource
++*
++* INPUT: tidsl_t *ptidsl
++*
++* RETURN: NULL
++*
++* Notes: external function osFreeMemory() is required.
++*****************************************************************************************/
++
++int dslhal_api_dslShutdown
++(
++ tidsl_t *ptidsl
++);
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_getDspVersion
++*
++*******************************************************************************************
++* DESCRIPTION: This routine supply AX5 daugther card DSP version.
++*
++* INPUT: tidsl_t * ptidsl
++* void *pVer, DSP version struct is returned starting at this pointer
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++*
++*****************************************************************************************/
++
++int dslhal_api_getDspVersion
++(
++ tidsl_t *ptidsl,
++ void *pVer
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_digi_memTestA()
++*
++*********************************************************************************************
++* DESCRIPTION: This function does the digital tests on the DSP. It does the DSP ID test,
++* memory tests on the external and internal memories of DSP, Codec Interconnect
++* test and Interrupt Test.
++*
++* Input: Test selects the test to be performed based on the elements set of 9 element
++* array passed the the parameter.
++*
++* Return: Status of the Tests Failed
++*
++********************************************************************************************/
++
++unsigned int dslhal_diags_digi_memTestA
++(
++unsigned int* Test
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_digi_memTestB()
++*
++*********************************************************************************************
++* DESCRIPTION: This function does the digital tests on the DSP. It does the DSP ID test,
++* memory tests on the external and internal memories of DSP, Codec Interconnect
++* test and Interrupt Test.
++*
++* Input: Test selects the digital test to be performed.
++*
++* Return: Status of the Tests Failed
++*
++********************************************************************************************/
++
++unsigned int dslhal_diags_digi_memTestB
++(
++unsigned int Test,
++unsigned int *Status
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_anlg_tonesTestA()
++*
++*********************************************************************************************
++* DESCRIPTION: This function instructs the Transciever to transmit the Reverb with missing
++* tones and Medley's with missing tones. These signals are defined in ITU
++* G.992.1 ADSL Standards.
++*
++* Input: Test selects between the Reverb or Medley tests. 0 - Reverb, 1 - Medley
++* Array is a 64 element unsigned integer type array. The element of this array
++* describe which tones are to be generated by selecting the element of
++* the array to be non zero.
++* Return: NULL
++*
++********************************************************************************************/
++
++void dslhal_diags_anlg_tonesTestA
++(
++unsigned int Test,
++unsigned int* Array
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_anlg_tonesTestB()
++*
++*********************************************************************************************
++* DESCRIPTION: This function instructs the Transciever to transmit the Reverb with missing
++* tones and Medley's with missing tones. These signals are defined in ITU
++* G.992.1 ADSL Standards.
++*
++* Input: Test selects between the Reverb or Medley tests. 0 - Reverb, 1 - Medley
++* Array is a 64 element unsigned integer type array. The element of this array
++* describe which tones are to be generated by selecting the element of
++* the array to be non zero.
++* Return: NULL
++*
++********************************************************************************************/
++
++void dslhal_diags_anlg_tonesTestB
++(
++unsigned int Test,
++unsigned int Tones
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_anlg_rxNoiseTest()
++*
++*********************************************************************************************
++* DESCRIPTION: This function instructs the Transciever to transmit the Reverb with missing
++* tones and Medley's with missing tones. These signals are defined in ITU
++* G.992.1 ADSL Standards.
++*
++* Input: Test selects between the Reverb or Medley tests. 0 - Reverb, 1 - Medley
++* Tones selects the .
++* Return: NULL
++*
++********************************************************************************************/
++
++void dslhal_diags_anlg_rxNoiseTest
++(int agcFlag,
++short pga1,
++short pga2,
++short pga3,
++short aeq
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_anlg_ecNoiseTest()
++*
++*********************************************************************************************
++* DESCRIPTION: This function instructs the Transciever to transmit the Reverb with missing
++* tones and Medley's with missing tones. These signals are defined in ITU
++* G.992.1 ADSL Standards.
++*
++* Input: Test selects between the Reverb or Medley tests. 0 - Reverb, 1 - Medley
++* Tones selects the .
++* Return: NULL
++*
++********************************************************************************************/
++
++void dslhal_diags_anlg_ecNoiseTest
++(int agcFlag,
++short pga1,
++short pga2,
++short pga3,
++short aeq
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_pollTrainingStatus()
++*
++*********************************************************************************************
++* DESCRIPTION: code to decode modem status and to start modem training
++*
++* Input: tidsl_t *ptidsl
++*
++* Return: 0-? status mode training
++* -1 failed
++*
++********************************************************************************************/
++int dslhal_api_pollTrainingStatus
++(
++ tidsl_t *ptidsl
++);
++
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_handleTrainingInterrupt()
++*
++*********************************************************************************************
++* DESCRIPTION: Code to handle ax5 hardware interrupts
++*
++* Input: tidsl_t *ptidsl
++* int *pMsg, pointer to returned hardware messages. Each byte represent a messge
++* int *pTag, pointer to returned hardware message tags. Each byte represent a tag.
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++int dslhal_api_handleTrainingInterrupt
++(
++ tidsl_t *ptidsl,
++ int intrSource
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setEocSerialNumber(tidsl_t *ptidsl,char *SerialNumber)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction Sets the EOC Serial Number
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * char *SerialNumber : Input EOC Serial Number
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setEocSerialNumber
++(
++tidsl_t *ptidsl,
++char *SerialNumber
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setEocVendorId(tidsl_t *ptidsl,char *VendorID)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction Sets the EOC Serial Number
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * char *VendorID : EOC Vendor ID
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setEocVendorId
++(
++tidsl_t *ptidsl,
++char *VendorID
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setEocRevisionNumber(tidsl_t *ptidsl,char *RevNum)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction Sets the EOC Revision Number
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * char *RevNum : Input EOC Revision Number
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setEocRevisionNumber
++(
++tidsl_t *ptidsl,
++char *RevNumber
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setAturConfig(tidsl_t *ptidsl,char *ATURConfig)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction Sets the EOC ATUR Config Register
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * char *RevNum : Input EOC ATUR Config Register
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setAturConfig
++(
++tidsl_t *ptidsl,
++char *ATURConfig
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_disableLosAlarm(tidsl_t *ptidsl, unsigned int set)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction disables all the LOS alarms
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * unsigned int set // if set == TRUE : Disable LOS alarms, else enable
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ * NOTES: Currently not supported in any version other than MR4 Patch release..
++ *****************************************************************************************/
++unsigned int dslhal_api_disableLosAlarm
++(
++tidsl_t *ptidsl,
++unsigned int
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_sendIdle(tidsl_t *ptidsl)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the CMD_IDLE message to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_sendIdle
++(
++tidsl_t *ptidsl
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_sendQuiet(tidsl_t *ptidsl)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the CMD_QUIET message to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_sendQuiet
++(
++tidsl_t *ptidsl
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_sendDgasp(tidsl_t *ptidsl)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the HOST_DGASP message to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_sendDgasp
++(
++tidsl_t *ptidsl
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setMarginThreshold(tidsl_t *ptidsl, int threshold)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction does sets the Margin threshold
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * int threshold
++ *
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setMarginThreshold
++(
++tidsl_t *ptidsl,
++int threshold
++);
++
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_setMarginMonitorFlags(tidsl_t *ptidsl, unsigned int trainflag,unsigned int shwtflag)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction does sets the Margin monitoring flag
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * unsigned int trainflag
++ * unsigned int shwtflag
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_setMarginMonitorFlags
++(
++tidsl_t *ptidsl,
++unsigned int trainflag,
++unsigned int shwtflag
++);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setRateAdaptFlag(tidsl_t *ptidsl)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the Rate Adapt Enable Flag
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int flag //if flag = TRUE set flag else reset
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++unsigned int dslhal_api_setRateAdaptFlag
++(
++tidsl_t *ptidsl,
++unsigned int flag
++);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setTrellisFlag(tidsl_t *ptidsl, unsigned int flag)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the Trellis Coding Enable Flag
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int flag //if flag = TRUE set flag else reset
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++unsigned int dslhal_api_setTrellisFlag
++(
++tidsl_t *ptidsl,
++unsigned int flag
++);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setMaxBitsPerCarrier(tidsl_t *ptidsl,unsigned int maxbits)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the Maximum bits per carrier value
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int maxbits : should be a value between 0-15
++*
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++unsigned int dslhal_api_setMaxBitsPerCarrier
++(
++tidsl_t *ptidsl,
++unsigned int maxbits
++);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setMaxInterleaverDepth(tidsl_t *ptidsl,unsigned int maxdepth)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the Maximum Interleave Depth Supported
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int maxdepth : Should be between 0 and 3 depending on intlv buffer
++* size 64-512
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++unsigned int dslhal_api_setMaxInterleaverDepth
++(
++tidsl_t *ptidsl,
++unsigned int maxdepth
++);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_api_setTrainingMode(tidsl_t *ptidsl,unsigned int trainmode)
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction Sets the desired training mode(none/T1.413/G.dmt/G.lite)
++*
++* INPUT: PITIDSLHW_T *ptidsl
++* unsigned int trainmode :Should be between 0 and 4; 0:No Mode 1:Multimode
++* 2: T1.413, 3:G.dmt, 4: G.lite
++* RETURN: 0 SUCCESS
++* 1 FAILED
++*
++*****************************************************************************************/
++
++unsigned int dslhal_api_setTrainingMode
++(
++tidsl_t *ptidsl,
++unsigned int trainmode
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_dslRetrain(tidsl_t *ptidsl)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the CMD_QUIET message to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_dslRetrain
++(
++tidsl_t *ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_acknowledgeInterrupt()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_acknowledgeInterrupt
++(tidsl_t * ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_disableDspHybridSelect()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_disableDspHybridSelect
++(tidsl_t * ptidsl,
++ unsigned int disable
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_disableDspHybridSelect()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_selectHybrid
++(tidsl_t * ptidsl,
++ unsigned int hybridNum
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_reportHybridMetrics()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_reportHybridMetrics
++(tidsl_t * ptidsl,
++ int *metric
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_selectInnerOuterPair(tidsl_t *ptidsl, unsigned int pairSelect)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the CMD_QUIET message to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++
++unsigned int dslhal_api_selectInnerOuterPair
++(tidsl_t *ptidsl,
++unsigned int pairSelect
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_resetTrainFailureLog(tidsl_t *ptidsl, unsigned int pairSelect)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the CMD_QUIET message to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++
++unsigned int dslhal_api_resetTrainFailureLog
++(tidsl_t *ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_controlLed()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_configureLed
++(tidsl_t * ptidsl,
++unsigned int idLed,
++unsigned int onOff
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_configureExternBert()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_configureExternBert
++(tidsl_t * ptidsl,
++unsigned int configParm,
++unsigned int parmVal
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_configureAtmBert()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_configureAtmBert
++(tidsl_t * ptidsl,
++unsigned int configParm,
++unsigned int parmVal
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_configureDgaspLpr()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_configureDgaspLpr
++(tidsl_t * ptidsl,
++unsigned int configParm,
++unsigned int parmVal
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_onOffPcb()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_onOffPcb
++(tidsl_t * ptidsl,
++unsigned int onOff
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_onOffBitSwap()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Turns on / off the power cutback feature;
++* Input
++* usDs; 0 = us and 1 = ds;
++* onOff; 0 = OFF and 1 = ON
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_onOffBitSwap
++(tidsl_t * ptidsl,
++ unsigned int usDs,
++ unsigned int onOff
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_configDsTones()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Turns on / off specific tones in the downstream direction;
++* Input
++* pointer to the array specifying the tones to be turned on/off
++*
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_configDsTones
++(tidsl_t * ptidsl,
++ unsigned int *dsTones
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_getAocBitSwapBuffer()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Fetches the Tx/Rx AOC bitswap Buffer;
++* Input
++* Transmit / Receive buffer to be fetched
++*
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_getAocBitswapBuffer
++(tidsl_t * ptidsl,
++unsigned int usDs
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_readTrainingMessages()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Reads all the training messages on demand;
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++* void *msgStruct : Pointer to Message Structure
++*
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_readTrainingMessages
++(tidsl_t * ptidsl,
++void *msgPtr
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_getTrainingState()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Reads all the training messages on demand;
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++* void *msgStruct : Pointer to training state structure
++*
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_getTrainingState
++(tidsl_t * ptidsl,
++void *statePtr
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_resetBitSwapMessageLog()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Clears the Aoc Bitswap Message Log
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++* unsigned int usDs ; Upstream=0, Downstream=1
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_resetBitSwapMessageLog
++(tidsl_t * ptidsl,
++ unsigned int usDs
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_setConstellationBinNumber()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Specifies the bin number for which constellation data should be fetched
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++* unsigned int binNum : constellation bin number whose data is required
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_setConstellationBinNumber
++(tidsl_t * ptidsl,
++ unsigned int binNum
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_resetTrainStateHistory()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Clears the Training State History Log
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++*
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_resetTrainStateHistory
++(tidsl_t * ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_getSnrPerBin()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Get SNR data per bin
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++*
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_getSnrPerBin
++(tidsl_t * ptidsl,
++ unsigned int snrBufferOpt
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_logEocMessages()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Logs EOC messages sent by the Modem to the CO
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++* unsigned int eocLowerBytes : Lower [1-5] bits of EOC Message
++* unsigned int eocUpperBytes : Upper [6-13] bits of EOC Message
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_logEocMessages
++(tidsl_t * ptidsl,
++ unsigned int usDs,
++ unsigned int eocLowerBytes,
++ unsigned int eocUpperBytes
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_getReasonForDrop()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Reads the reason for dropping DSL connection;
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++
++*
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_getReasonForDrop
++(tidsl_t * ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_ctrlMaxAvgFineGains()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Turns on / off the host control for Max Avg Fine Gains; 0 = OFF and 1 = ON
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_ctrlMaxAvgFineGains
++(tidsl_t * ptidsl,
++unsigned int onOff
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_setMaxAvgFineGain()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Set the Maximum Average Fine Gain Value
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_setMaxAvgFineGain
++(tidsl_t * ptidsl,
++ short fineGain
++);
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_readPhySettings()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Reads the advanced Phy layer settings on demand;
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++* void *cfgStruct : Pointer to Phy Config Structure
++*
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_readPhySettings
++(tidsl_t * ptidsl,
++void *cfgPtr
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_advcfg_setBlackOutBits()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the Blackout Bits in the RMSGPCB message
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_advcfg_setBlackOutBits
++(tidsl_t * ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_genericDspRead()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Reads from a generic location in the host interface
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_genericDspRead
++(tidsl_t * ptidsl,
++ unsigned int offset1,
++ unsigned int offset2,
++ unsigned int offset3,
++ unsigned char* localBuffer,
++ unsigned int numBytes
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_genericDspWrite()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Writes to a generic location in the host interface
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_genericDspWrite
++(tidsl_t * ptidsl,
++ unsigned int offset1,
++ unsigned int offset2,
++ unsigned int offset3,
++ unsigned char* localBuffer,
++ unsigned int numBytes
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_dspInterfaceRead()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Reads from a generic location in the host interface
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_dspInterfaceRead
++(tidsl_t * ptidsl,
++ unsigned int baseAddr,
++ unsigned int numOffsets,
++ unsigned int *offsets,
++ unsigned char* localBuffer,
++ unsigned int numBytes
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_api_dspInterfaceWrite()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Writes to a generic location in the host interface
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_api_dspInterfaceWrite
++(tidsl_t * ptidsl,
++ unsigned int baseAddr,
++ unsigned int numOffsets,
++ unsigned int *offsets,
++ unsigned char* localBuffer,
++ unsigned int numBytes
++);
++
++/******************************************************************************************
++ * FUNCTION NAME: dslhal_api_sendMailboxCommand(tidsl_t *ptidsl, unsigned int cmd)
++ *
++ *******************************************************************************************
++ * DESCRIPTION: This fuction sends the passed mailbox command to the DSP
++ *
++ * INPUT: PITIDSLHW_T *ptidsl
++ * unsigned int cmd
++ *
++ * RETURN: 0 SUCCESS
++ * 1 FAILED
++ *
++ *****************************************************************************************/
++unsigned int dslhal_api_sendMailboxCommand
++(tidsl_t *ptidsl,
++unsigned int cmd
++);
++
++#ifdef INTERNAL_BUILD
++#include <dsl_hal_internal_api.h>
++#endif
++
++
++#endif /* pairs #ifndef __DSL_APPLICATION_INTERFACE_H__ */
+diff -urN linux.old/drivers/atm/sangam_atm/dsl_hal_logtable.h linux.dev/drivers/atm/sangam_atm/dsl_hal_logtable.h
+--- linux.old/drivers/atm/sangam_atm/dsl_hal_logtable.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/dsl_hal_logtable.h 2005-08-23 04:46:50.097843696 +0200
+@@ -0,0 +1,259 @@
++unsigned int log10[]=
++{
++ 0,
++ 771,
++ 1221,
++ 1541,
++ 1789,
++ 1992,
++ 2163,
++ 2312,
++ 2443,
++ 2560,
++ 2666,
++ 2763,
++ 2852,
++ 2934,
++ 3011,
++ 3083,
++ 3150,
++ 3213,
++ 3274,
++ 3331,
++ 3385,
++ 3437,
++ 3486,
++ 3533,
++ 3579,
++ 3622,
++ 3664,
++ 3705,
++ 3744,
++ 3781,
++ 3818,
++ 3853,
++ 3887,
++ 3921,
++ 3953,
++ 3984,
++ 4015,
++ 4044,
++ 4073,
++ 4101,
++ 4129,
++ 4156,
++ 4182,
++ 4207,
++ 4232,
++ 4257,
++ 4281,
++ 4304,
++ 4327,
++ 4349,
++ 4371,
++ 4393,
++ 4414,
++ 4435,
++ 4455,
++ 4475,
++ 4495,
++ 4514,
++ 4533,
++ 4552,
++ 4570,
++ 4589,
++ 4606,
++ 4624,
++ 4641,
++ 4658,
++ 4675,
++ 4691,
++ 4707,
++ 4723,
++ 4739,
++ 4755,
++ 4770,
++ 4785,
++ 4800,
++ 4815,
++ 4829,
++ 4844,
++ 4858,
++ 4872,
++ 4886,
++ 4899,
++ 4913,
++ 4926,
++ 4939,
++ 4952,
++ 4965,
++ 4978,
++ 4990,
++ 5003,
++ 5015,
++ 5027,
++ 5039,
++ 5051,
++ 5063,
++ 5075,
++ 5086,
++ 5098,
++ 5109,
++ 5120,
++ 5131,
++ 5142,
++ 5153,
++ 5164,
++ 5174,
++ 5185,
++ 5195,
++ 5206,
++ 5216,
++ 5226,
++ 5236,
++ 5246,
++ 5256,
++ 5266,
++ 5275,
++ 5285,
++ 5295,
++ 5304,
++ 5313,
++ 5323,
++ 5332,
++ 5341,
++ 5350,
++ 5359,
++ 5368,
++ 5377,
++ 5386,
++ 5394,
++ 5403,
++ 5412,
++ 5420,
++ 5429,
++ 5437,
++ 5445,
++ 5454,
++ 5462,
++ 5470,
++ 5478,
++ 5486,
++ 5494,
++ 5502,
++ 5510,
++ 5518,
++ 5525,
++ 5533,
++ 5541,
++ 5548,
++ 5556,
++ 5563,
++ 5571,
++ 5578,
++ 5586,
++ 5593,
++ 5600,
++ 5607,
++ 5614,
++ 5622,
++ 5629,
++ 5636,
++ 5643,
++ 5649,
++ 5656,
++ 5663,
++ 5670,
++ 5677,
++ 5683,
++ 5690,
++ 5697,
++ 5703,
++ 5710,
++ 5716,
++ 5723,
++ 5729,
++ 5736,
++ 5742,
++ 5749,
++ 5755,
++ 5761,
++ 5767,
++ 5773,
++ 5780,
++ 5786,
++ 5792,
++ 5798,
++ 5804,
++ 5810,
++ 5816,
++ 5822,
++ 5828,
++ 5834,
++ 5839,
++ 5845,
++ 5851,
++ 5857,
++ 5862,
++ 5868,
++ 5874,
++ 5879,
++ 5885,
++ 5891,
++ 5896,
++ 5902,
++ 5907,
++ 5913,
++ 5918,
++ 5924,
++ 5929,
++ 5934,
++ 5940,
++ 5945,
++ 5950,
++ 5955,
++ 5961,
++ 5966,
++ 5971,
++ 5976,
++ 5981,
++ 5986,
++ 5992,
++ 5997,
++ 6002,
++ 6007,
++ 6012,
++ 6017,
++ 6022,
++ 6027,
++ 6031,
++ 6036,
++ 6041,
++ 6046,
++ 6051,
++ 6056,
++ 6060,
++ 6065,
++ 6070,
++ 6075,
++ 6079,
++ 6084,
++ 6089,
++ 6093,
++ 6098,
++ 6103,
++ 6107,
++ 6112,
++ 6116,
++ 6121,
++ 6125,
++ 6130,
++ 6134,
++ 6139,
++ 6143,
++ 6148,
++ 6152,
++ 6156,
++ 6161,
++ 6165
++ };
+diff -urN linux.old/drivers/atm/sangam_atm/dsl_hal_register.h linux.dev/drivers/atm/sangam_atm/dsl_hal_register.h
+--- linux.old/drivers/atm/sangam_atm/dsl_hal_register.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/dsl_hal_register.h 2005-08-23 04:46:50.097843696 +0200
+@@ -0,0 +1,337 @@
++#ifndef ___DSL_REGISTER_DEFINES_H___
++#define ___DSL_REGISTER_DEFINES_H___ 1
++
++/*******************************************************************************
++* FILE PURPOSE: DSL HAL H/W Registers and Constant Declarations for Sangam
++*
++********************************************************************************
++* FILE NAME: dsl_hal_register.h
++*
++* DESCRIPTION:
++* Contains DSL HAL APIs for Adam2 OS functions
++*
++*
++* (C) Copyright 2001-02, Texas Instruments, Inc.
++* History
++* Date Version Notes
++* 06Feb03 0.00.00 RamP Created
++* 21Mar03 0.00.01 RamP Changed header files for Modular
++* build framework
++* 21Mar03 0.00.02 RamP Introduced malloc size for DSP f/w
++* 07Apr03 0.00.03 RamP Implemented new error reporting scheme
++* Changed Commenting to C style only
++* 12Apr03 0.00.04 RamP Added Interrupt Mask defines
++* 14Apr03 0.00.05 RamP Renamed macros for REG8, REG16 & REG32
++* 21Apr03 0.01.00 RamP Added Interrupt source/clear registers
++* Changed enum RSTATE_SHOWTIME to 5
++* 24Apr03 0.01.01 RamP Moved the RSTATE enum to api.h
++* Added olay recovery error condition
++* 14May03 0.01.02 RamP Added defines for power computation
++* Added error condition for hybrids
++* 04Jun03 0.01.03 RamP Added enum for config flags,
++* Cleaned up AR5 register defines
++* Added defines for higher data rate
++* 06Jun03 0.01.04 RamP Added error & interrupt defines
++* 09Jun03 0.01.05 RamP Modified enum for current config
++* Added additional C-Rates defines
++* 18Jul03 0.01.06 RamP Modified internal build flow
++* 21Aug03 0.01.07 RamP Added constellation buffer size
++* 08Oct03 0.01.08 RamP Added us/ds Bits n gains size
++* 12Oct03 0.01.08 RamP Added ADSL2 Message sizes, lengths
++* and offsets for various formats
++* 29Oct03 0.01.09 RamP Added ADSL2 Delt offsets & sizes
++* 24Nov03 0.01.10 RamP Added bit field number, scan vector
++* 26Dec03 0.01.11 RamP Removed the oamFeature masks to api.h
++*******************************************************************************/
++
++#include "env_def_typedefs.h"
++#ifdef INTERNAL_BUILD
++#include "dev_host_internalinterface.h"
++#endif
++#include "dev_host_interface.h"
++#include "dsl_hal_api.h"
++
++#define ADSLSS_BASE 0x01000000
++#define BBIF_BASE 0x02000000
++
++#define ADSLSSADR (BBIF_BASE+0x0000)
++#define ADSLSSADRMASK 0xff000000
++#define WAKEUP_DSP 0x00000001
++
++/* Ax7 Reset Control */
++
++#define RST_CNTRL_BASE 0x8611600
++#define RST_CNTRL_PRCR (RST_CNTRL_BASE + 0x00 )
++
++#define RST_CNTRL_PRCR_GPIO 0x00000040
++#define RST_CNTRL_PRCR_ADSLSS 0x00000080
++#define RST_CNTRL_PRCR_USB 0x00000100
++#define RST_CNTRL_PRCR_SAR 0x00000200
++#define RST_CNTRL_PRCR_DSP 0x00800000
++#define RST_CNTRL_PRCR_EMAC1 0x00200000 /* EMAC1 reset */
++
++#define RST_CNTRL_SWRCR (RST_CNTRL_BASE + 0x04 )
++#define RST_SWRCR_SWR0 0x00000001
++#define RST_SWRCR_SWR1 0x00000002
++
++#define RST_CNTRL_RSR (TNETD53XX_RST_CNTRL_BASE + 0x08 )
++#define RST_RSR_RSCAUSE 0x00000003 /* Software Reset Caused by writing to SWR1 bit */
++
++
++/* ******************************************************
++Interrupt sources on Ax7 interrupt controller.
++The reserved sources are noted.
++********************************************************* */
++
++#define INTR_CNTRL_SRC_SECOND 0
++#define INTR_CNTRL_SRC_EXTERNAL0 1
++#define INTR_CNTRL_SRC_EXTERNAL1 2
++/* reserved sources ... */
++#define INTR_CNTRL_SRC_TIMER0 5
++#define INTR_CNTRL_SRC_TIMER1 6
++#define INTR_CNTRL_SRC_UART0 7
++#define INTR_CNTRL_SRC_UART1 8
++#define INTR_CNTRL_SRC_DMA0 9
++#define INTR_CNTRL_SRC_DMA1 10
++/* reserved sources ... */
++#define INTR_CNTRL_SRC_SAR 15
++/* reserved sources ... */
++#define INTR_CNTRL_SRC_EMAC0 19
++/* reserved sources ... */
++#define INTR_CNTRL_SRC_VLYNQ0 21
++#define INTR_CNTRL_SRC_CODEC_WAKE 22
++/* reserved sources ... */
++#define INTR_CNTRL_SRC_USB 24
++#define INTR_CNTRL_SRC_VLYNQ1 25
++/* reserved sources ... */
++#define INTR_CNTRL_SRC_EMAC1 28
++#define INTR_CNTRL_SRC_I2C 29
++#define INTR_CNTRL_SRC_DMA2 30
++#define INTR_CNTRL_SRC_DMA3 31
++/* reserved sources ... */
++#define INTR_CNTRL_SRC_VDMA_RX 37
++#define INTR_CNTRL_SRC_VDMA_TX 38
++#define INTR_CNTRL_SRC_ADSLSS 39
++
++#ifndef K0BASE
++#define K0BASE 0x80000000
++#endif
++
++#ifndef K1BASE
++#define K1BASE 0xA0000000
++#endif
++
++#ifndef PHYS_ADDR
++#define PHYS_ADDR(X) ((X) & 0X1FFFFFFF)
++#endif
++
++#ifndef PHYS_TO_K0
++#define PHYS_TO_K0(X) (PHYS_ADDR(X)|K0BASE)
++#endif
++
++#ifndef PHYS_TO_K1
++#define PHYS_TO_K1(X) (PHYS_ADDR(X)|K1BASE)
++#endif
++
++#ifndef DSLHAL_REG8
++#define DSLHAL_REG8( addr ) (*(volatile unsigned short *) PHYS_TO_K1(addr))
++#endif
++
++#ifndef DSLHAL_REG16
++#define DSLHAL_REG16( addr ) (*(volatile unsigned short *)PHYS_TO_K1(addr))
++#endif
++
++#ifndef DSLHAL_REG32
++#define DSLHAL_REG32( addr ) (*(volatile unsigned int *)PHYS_TO_K1(addr))
++#endif
++
++#ifndef NULL
++#define NULL 0
++#endif
++
++#ifndef TRUE
++#define TRUE (1==1)
++#endif
++
++#ifndef FALSE
++#define FALSE (1==2)
++#endif
++
++/*******************************************************************************
++* Type Defines for Library
++********************************************************************************/
++typedef unsigned int size_t;
++
++#define TIDSL_HW_CREATED 0x00000001
++#define TIDSL_HW_OPENED 0x00000002
++#define TIDSL_HW_STARTED 0x00000004
++#define TIDSL_OS_INITIALIZED 0x00000008
++
++/* Data Pump CRATES Table Defines */
++#define SIZE_OF_CRATES1_TABLE 120
++#define CRATES1_BF_LS0 7
++#define CRATES1_BI_LS0 17
++#define CRATES1_BF_AS0 0
++#define CRATES1_BI_AS0 10
++#define CRATES1_BF_DSRS 20
++#define CRATES1_BI_DSRS 21
++#define CRATES1_BFI_DSS 22
++#define CRATES1_BFI_DSI 23
++#define CRATES1_BF_USRS 25
++#define CRATES1_BI_USRS 26
++#define CRATES1_BFI_USS 27
++#define CRATES1_BFI_USI 28
++
++#define FAST_PATH 0
++#define INTERLEAVED_PATH 1
++
++#define LINE_NOT_CONNECTED 0
++#define LINE_CONNECTED 1
++#define LINE_DISCONNECTED 2
++#define LINE_NOT_TO_CONNECT 3
++
++#define MAXSECTIONS 125
++
++/*****************************************************************************************
++ * Localstructure declarations
++ *
++ ****************************************************************************************/
++enum
++{
++ DSLHAL_ERROR_NO_ERRORS, /* 00 */
++ DSLHAL_ERROR_UNRESET_ADSLSS, /* 01 */
++ DSLHAL_ERROR_RESET_ADSLSS, /* 02 */
++ DSLHAL_ERROR_UNRESET_DSP, /* 03 */
++ DSLHAL_ERROR_RESET_DSP, /* 04 */
++ DSLHAL_ERROR_NO_FIRMWARE_IMAGE, /* 05 */
++ DSLHAL_ERROR_MALLOC, /* 06 */
++ DSLHAL_ERROR_FIRMWARE_MALLOC, /* 07 */
++ DSLHAL_ERROR_DIAG_MALLOC, /* 08 */
++ DSLHAL_ERROR_OVERLAY_MALLOC, /* 09 */
++ DSLHAL_ERROR_CODE_DOWNLOAD, /* 10 */
++ DSLHAL_ERROR_DIAGCODE_DOWNLOAD, /* 11 */
++ DSLHAL_ERROR_BLOCK_READ, /* 12 */
++ DSLHAL_ERROR_BLOCK_WRITE, /* 13 */
++ DSLHAL_ERROR_MAILBOX_READ, /* 14 */
++ DSLHAL_ERROR_MAILBOX_WRITE, /* 15 */
++ DSLHAL_ERROR_MAILBOX_NOMAIL, /* 16 */
++ DSLHAL_ERROR_MAILBOX_OVERFLOW, /* 17 */
++ DSLHAL_ERROR_INVALID_PARAM, /* 18 */
++ DSLHAL_ERROR_ADDRESS_TRANSLATE, /* 19 */
++ DSLHAL_ERROR_FIRMWARE_CRC, /* 20 */
++ DSLHAL_ERROR_FIRMWARE_OFFSET, /* 21 */
++ DSLHAL_ERROR_CONFIG_API_FAILURE, /* 22 */
++ DSLHAL_ERROR_EOCREG_API_FAILURE, /* 23 */
++ DSLHAL_ERROR_VERSION_API_FAILURE, /* 24 */
++ DSLHAL_ERROR_STATS_API_FAILURE, /* 25 */
++ DSLHAL_ERROR_MARGIN_API_FAILURE, /* 26 */
++ DSLHAL_ERROR_CTRL_API_FAILURE, /* 27 */
++ DSLHAL_ERROR_HYBRID_API_FAILURE, /* 28 */
++ DSLHAL_ERROR_MODEMENV_API_FAILURE, /* 29 */
++ DSLHAL_ERROR_INTERRUPT_FAILURE, /* 30 */
++ DSLHAL_ERROR_INTERNAL_API_FAILURE, /* 31 */
++ DSLHAL_ERROR_DIGIDIAG_FAILURE, /* 32 */
++ DSLHAL_ERROR_TONETEST_FAILURE, /* 33 */
++ DSLHAL_ERROR_NOISETEST_FAILURE, /* 34 */
++ DSLHAL_ERROR_MODEMSTATE, /* 35 */
++ DSLHAL_ERROR_OVERLAY_CORRUPTED /* 36 */
++};
++
++enum
++{
++ CONFIG_FLAG_NOFLAG, /* 00 */
++ CONFIG_FLAG_TRELLIS, /* 01 */
++ CONFIG_FLAG_EC, /* 02 */
++ CONFIG_FLAG_RS /* 03 */
++};
++
++#define USE_EMIF_REV 0
++#define USE_CVR_REV 1
++#define TNETD53XX_MAXLOOP 10000
++#define REVERB 0
++#define MEDLEY 1
++#define NONINTENSE 0
++#define slavespace0 0xa1000000
++
++#define MASK_MAILBOX_INTERRUPTS 0x00000001
++#define MASK_BITFIELD_INTERRUPTS 0x00000002
++#define MASK_HEARTBEAT_INTERRUPTS 0x00000004
++#define DSP_INTERRUPT_SOURCE_REGISTER 0x020007A0
++#define DSP_INTERRUPT_CLEAR_REGISTER 0x020007A4
++
++#define DIGITAL_DIAG_MEMSIZE 1048576
++#define CRC32_QUOTIENT 0x04c11db7
++#define DSP_FIRMWARE_MALLOC_SIZE 0x7ffff
++#define DSP_CONSTELLATION_BUFFER_SIZE 1024*4
++#define LOG43125 9303
++#define US_NOMINAL_POWER (-38)
++#define US_BNG_LENGTH 32
++#define DS_BNG_LENGTH 256
++#define NUMBER_OF_BITFIELDS 4
++#define BITFIELD_SCAN 0x80000000
++
++/* ADSL Message offsets from Host Interface Pointer */
++
++/* ADSL2 Messages Index and Length defines */
++
++#define CMSGFMT_INDEX 0
++#define CMSGPCB_INDEX 1
++#define RMSGFMT_INDEX 2
++#define RMSGPCB_INDEX 3
++#define RMSG1LD_INDEX 13
++#define RMSG2LD_INDEX 14
++#define RMSG3LD_INDEX 15
++#define RMSG4LD_INDEX 16
++#define RMSG5LD_INDEX 17
++#define RMSG6LD_INDEX 18
++#define RMSG7LD_INDEX 19
++#define RMSG8LD_INDEX 20
++#define RMSG9LD_INDEX 21
++#define CMSG1LD_INDEX 22
++#define CMSG2LD_INDEX 23
++#define CMSG3LD_INDEX 24
++#define CMSG4LD_INDEX 25
++#define CMSG5LD_INDEX 26
++#define CMSGPCB2_INDEX 28
++#define CMSGPCB2L_INDEX 29
++#define RMSGFMT2_INDEX 30
++#define RMSGPCB2L_INDEX 31
++#define CMSG1ADSL2_INDEX 32
++#define RMSG1ADSL2_INDEX 33
++#define CMSG2ADSL2_INDEX 34
++#define RMSG2ADSL2_INDEX 35
++#define CPARAMS_INDEX 36
++#define RPARAMS_INDEX 37
++
++/* ADSL2 Message Sizes */
++
++#define CMSGFMT_SIZE 2
++#define RMSGFMT_SIZE 2
++#define CMSGPCB_SIZE 2
++#define CMSGPCB2_SIZE 6 /* Annex A with Blackout */
++#define CMSGPCB2L_SIZE 10 /* Annex B with Blackout */
++#define RMSGPCB_SIZE 36
++#define RMSG1LD_SIZE 16
++#define RMSGxLD_SIZE 258
++#define CMSG1LD_SIZE 16
++#define CMSG2LD_SIZE 130
++#define CMSG3LD_SIZE 66
++#define CMSG4LD_SIZE 34
++#define CMSG5LD_SIZE 34
++#define CMSG1ADSL2_SIZE 24
++#define RMSG1ADSL2_SIZE 4
++#define CMSG2ADSL2_SIZE 4
++#define RMSG2ADSL2_SIZE 32
++#define CPARAMS_SIZE 136
++#define RPARAMS_SIZE 808
++
++/* ADSL2 Plus Message Sizes (if Different from ADSL2) */
++
++#define RMSGPCB_P_SIZE 68
++#define CMSG1ADSL2P_SIZE 40 /* With Blackout */
++#define CPARAMS_PA_SIZE 168
++#define RPARAMS_PA_SIZE 2088
++#define CPARAMS_PB_SIZE 296
++#define RPARAMS_PB_SIZE 2088
++
++#endif /* pairs #ifndef ___DSL_REGISTER_DEFINES_H___ */
+diff -urN linux.old/drivers/atm/sangam_atm/dsl_hal_support.c linux.dev/drivers/atm/sangam_atm/dsl_hal_support.c
+--- linux.old/drivers/atm/sangam_atm/dsl_hal_support.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/dsl_hal_support.c 2005-08-23 04:46:50.100843240 +0200
+@@ -0,0 +1,2788 @@
++/*******************************************************************************
++* FILE PURPOSE: DSL Driver API functions for Sangam
++*********************************************************************************
++* FILE NAME: dsl_hal_support.c
++*
++* DESCRIPTION:
++* Contains DSL HAL APIs for Modem Control
++*
++*
++* (C) Copyright 2001-02, Texas Instruments, Inc.
++* History
++* Date Version Notes
++* 06Feb03 0.00.00 RamP Created
++* 21Mar03 0.00.01 RamP Inserted byteswap functions
++* 07Apr03 0.00.02 RamP Implemented new error reporting scheme
++* Changed Commenting to C style only
++* 12Apr03 0.00.03 RamP Added function to set Interrupt Bit
++* Masks for bitfield & Mailboxes
++* 14Apr03 0.00.04 RamP Added function to process modem state
++* bit fields; renamed REG32 macros
++* Changed interrupt bit field settings
++* 15Apr03 0.00.05 RamP Fixed exit condition on dslShutdown
++* 21Apr03 0.01.00 RamP Fixed dslShutdown function & changed
++* loop counter for overlay byteswaps
++* (Alpha) Added cache writeback for overlays
++* Added function acknowledgeInterrupt
++* 22Apr03 0.01.01 RamP Moved acknowledgeInterrupt into api
++* 24Apr03 0.01.02 RamP Added function to compare crc32 with
++* pre-computed value as a recovery
++* scheme for corrupt overlay pages
++* 28Apr03 0.01.03 RamP Fixed a parameter in crc32 fxn call
++* 05May03 0.01.04 RamP Fixed Message structure access in
++* writeHostMailbox function
++* 14May03 0.01.05 RamP Lookup to netService of dsp version
++* (alpha ++) to determine pots/isdn service
++* 21May03 0.01.06 RamP Added support for CO profiles
++* 29May03 0.01.07 RamP Added critical section tabs for block
++* read/write operations
++* Added functions to reload overlay pages
++* and CO Profiles
++* 04Jun03 0.01.08 RamP Added state transition timing counters
++* 06Jun03 0.01.09 RamP Added Interrupt source parsing function
++* Interrupt masking for heartbeat added
++* 09Jun03 0.01.10 RamP Modified modem state bit field processing
++* for structure changes in ITIDSLHW
++* fixed problem in free memory for CO prof
++* 18Jul03 0.01.11 RamP Optimized free memory for CO profiles &
++* overlay pages in the supporting APIs
++* 28Jul03 0.02.00 RamP Modified the process bitfield functn
++* for LED & Application State report
++* 21Aug03 0.03.00 RamP Added logic to allocate & communicate
++* memory for constellation buffer display
++* 29Sep03 0.03.01 RamP Added API switch calls to advcfg module
++* to abstract them from the API module
++* 12Oct03 0.03.02 RamP Added API to gather ADSL2 Messages
++* 14Oct03 0.03.03 RamP Added function to read CMsgsRA
++* 23Oct03 0.03.04 RamP Changed train history index to circular
++* buffer upon rollover
++* 29Oct03 0.03.05 RamP Added Adsl2 Delt Message Parsing
++* 12Nov03 0.03.06 RamP Fixed endianness issues with
++* Constellation Display
++* 14Nov03 0.03.07 RamP Added function to gather CRates1/RRates1
++* before they get overwritten by CRatesRA
++* 19Nov03 0.03.08 JohnP Revised dslhal_support_aocBitSwapProcessing to
++* prevent duplicate ATU-R bitswaps going to ACT
++* 24Nov03 0.03.09 RamP Implemented detailed State Tracking through
++* Modem State bit fields for ADSL/2
++* 12Dec03 0.03.10 RamP Tokenized advanced configuration code
++* 12Dec03 0.03.11 RamP Added state reset upon IDLE
++* 19Dec03 0.03.12 RamP Added static adsl2 byteswap function for
++* handling pointer to pointer cases
++* Changed adsl2 messages to correct pointer to
++* pointer dereferencing problems in some OS
++* 26Dec03 0.03.13 RamP Setting Current Address for Constellation
++* buffer in addition to start address
++* Added additional check to overlay page malloc
++*******************************************************************************/
++#include "dsl_hal_register.h"
++#include "dsl_hal_support.h"
++
++static unsigned int dslhal_support_adsl2ByteSwap32(unsigned int in32Bits);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_unresetDslSubsystem
++*
++*******************************************************************************************
++* DESCRIPTION: This function unreset Dsl Subsystem
++*
++* INPUT: None
++*
++* RETURN: 0 if Pass; 1 if Fail
++*
++*****************************************************************************************/
++int dslhal_support_unresetDslSubsystem(void)
++{
++ dprintf(4," dslhal_support_unresetDslSubsystem()\n");
++ /* Put ADSLSS in to reset */
++ DSLHAL_REG32(0xa8611a10) = 0x1;
++ shim_osClockWait(64);
++ dprintf(5,"Selected APLL Reg \n");
++
++ DSLHAL_REG32(0xa8610a90) = 0x4;
++ shim_osClockWait(64);
++ dprintf(5,"Enable Analog PLL \n");
++
++ DSLHAL_REG32(0xa8610a90) = 0x77fe;
++ shim_osClockWait(64);
++ dprintf(5,"Set PLL for DSP\n");
++
++ /* DSLHAL_REG32(0xa8611600) = 0x007f1bdf;*/
++ DSLHAL_REG32(0xa8611600) |= RST_CNTRL_PRCR_ADSLSS;
++ shim_osClockWait(64);
++ dprintf(5,"Brought ADSLSS out of Reset \n");
++
++ DSLHAL_REG32(0xa861090c) &= ~((1<<20)|(1<<21)|(1<<22)|(1<<23)|(1<<24)|(1<<25));
++ shim_osClockWait(64);
++ dprintf(5,"Configured GPIO 20-25 for McBSP \n");
++
++ /*DSLHAL_REG32(0xa8611600) |= RST_CNTRL_PRCR_ADSLSS;*/
++
++
++ /* DSLHAL_REG32(0xa8611a04) = 0x00000001;
++ shim_osClockWait(64); */
++
++ dprintf(4," dslhal_support_unresetDslSubsystem done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_resetDslSubsystem
++*
++*******************************************************************************************
++* DESCRIPTION: This function unreset Dsl Subsystem
++*
++* INPUT: None
++*
++* RETURN: 0 if Pass; 1 if Fail
++*
++*****************************************************************************************/
++int dslhal_support_resetDslSubsystem(void)
++{
++ dprintf(4, "dslhal_support_resetDslSubsystem \n");
++ /* Put ADSLSS into reset */
++ DSLHAL_REG32(0xa8611600) &= ~RST_CNTRL_PRCR_ADSLSS;
++ shim_osClockWait(64);
++ /* DSLHAL_REG32(0xa8611a04) = 0x00000000;
++ shim_osClockWait(64); */
++ dprintf(4, "dslhal_support_resetDslSubsystem Done \n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_unresetDsp()
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction takes ax5 daugter board out of reset.
++*
++* INPUT: None
++*
++* RETURN: 0 --successful.
++* 1 --failed
++*
++*****************************************************************************************/
++int dslhal_support_unresetDsp(void)
++{
++#ifdef PRE_SILICON
++ /* unsigned char value; */
++ int rc;
++
++ rc=dslhal_support_hostDspAddressTranslate((unsigned int)DEV_MDMA0_SRC_ADDR);
++ if(rc==DSLHAL_ERROR_ADDRESS_TRANSLATE)
++ {
++ dprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
++ return DSLHAL_ERROR_ADDRESS_TRANSLATE;
++ }
++ dprintf(5,"MDMA SRC: %08x\n", rc);
++ DSLHAL_REG32(rc) = 0x80000001;
++ rc=dslhal_support_hostDspAddressTranslate((unsigned int)DEV_MDMA0_DST_ADDR);
++ if(rc==DSLHAL_ERROR_ADDRESS_TRANSLATE)
++ {
++ dprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
++ return DSLHAL_ERROR_ADDRESS_TRANSLATE;
++ }
++ dprintf(5,"MDMA DST: %08x\n", rc);
++ DSLHAL_REG32(rc) = 0x02090001;
++ rc=dslhal_support_hostDspAddressTranslate((unsigned int)DEV_MDMA0_CTL_ADDR);
++ if(rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
++ {
++ dprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
++ return DSLHAL_ERROR_ADDRESS_TRANSLATE;
++ }
++ dprintf(5,"MDMA CTL: %08x\n", rc);
++ DSLHAL_REG32(rc) = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
++ DEV_MDMA_BURST1 | (1 << DEV_MDMA_LEN_SHF));
++ /* statusMask = 0x00000010;*/
++#else
++ dprintf(4, "dslhal_support_unresetDsp()\n");
++
++ /* Bring the DSP core out of reset */
++ /* DSLHAL_REG32(0xa8611600) = 0x00ff1bdf; */
++ DSLHAL_REG32(0xa8611600) |= RST_CNTRL_PRCR_DSP;
++ shim_osClockWait(64);
++ dprintf(5,"Brought DSP out of Reset \n");
++ dprintf(6,"Current Contents of PRCR: 0x%x\n",(unsigned int)DSLHAL_REG32(0xa8611600));
++ /* DSLHAL_REG32(0xa8611a0c) = 0x00000007;
++ shim_osClockWait(64); */
++#endif
++
++ dprintf(4, "dslhal_support_unresetDsp() done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_resetDsp()
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction takes ax5 daugter board into reset.
++*
++* INPUT: None
++*
++* RETURN: 0 --successful.
++* 1 --failed
++*
++*****************************************************************************************/
++int dslhal_support_resetDsp(void)
++{
++ dprintf(4, "dslhal_support_resetDsp \n");
++ /* Put ADSLSS into reset */
++ DSLHAL_REG32(0xa8611600) &= ~RST_CNTRL_PRCR_DSP;
++ shim_osClockWait(64);
++ dprintf(4, "dslhal_support_resetDsp Done \n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_hostDspAddressTranslate()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Maps ax5 daugter card dsp memory address to avalanche memory space
++*
++* Input: unsigned int addr, dsp memory address.
++*
++* Return: >=0, unsigned int, mapped Avalanche address(VBUS address).
++* -1, mapping failed
++*
++*
++********************************************************************************************/
++/* static unsigned int bbifmap0,bbifmap1; */
++
++unsigned int dslhal_support_hostDspAddressTranslate( unsigned int addr )
++{
++ unsigned int addrMap;
++ /* This function should just be used to move the memory window of the ADSLSS */
++ dprintf(5, "dslhal_support_hostDspAddressTranslate()\n");
++
++ /* select vbus to xbus memory */
++ /* addrMap = addr & 0xff000000; */
++ addrMap = addr & ADSLSSADRMASK;
++
++ DSLHAL_REG32(ADSLSSADR) = addrMap;
++
++ dprintf(6, "dslhal_support_hostDspAddressTranslate() done\n");
++#ifdef PRE_SILICON
++ return ((ADSLSS_BASE | (~ADSLSSADRMASK & addr))+ 0x00000100);
++ /* Added 0x100 for Pre-Silicon VLNQ offset.. to be removed for Silicon */
++#else
++ return ((ADSLSS_BASE | (~ADSLSSADRMASK & addr)));
++ /* Added 0x100 for Pre-Silicon VLNQ offset.. to be removed for Silicon */
++#endif
++
++}
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_blockWrite
++*
++*******************************************************************************************
++* DESCRIPTION: This rouin simulates DSP memory write as done in ax5 pci nic card
++*
++* INPUT: void *buffer, data need to written
++* void *adde, memory address to be written
++* size_t count, number of bytes to be written
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++*
++*****************************************************************************************/
++
++int dslhal_support_blockWrite(void *buffer, void *addr, size_t count)
++{
++ int rc, byteCnt=0;
++ unsigned char* ptr;
++ union
++ {
++ unsigned char *cptr;
++ short *sptr;
++ int *iptr;
++ } src;
++ union
++ {
++ int anint; /* DSP location */
++ unsigned char *cptr; /* to avoid casts */
++ } dst;
++ union
++ {
++ unsigned int anint;
++ unsigned char byte[4];
++ }data,dword,sword;
++
++ /* Enter Critical Section */
++ shim_osCriticalEnter();
++
++ dprintf(6, "dslhal_support_blockWrite\n");
++
++ dprintf(6,"addr=0x%X, length=0x%X, buffer=0x%X\n", (unsigned int) addr, (unsigned int) count, (unsigned int)buffer);
++
++ src.cptr = (unsigned char*) buffer; /* local buffer */
++ dst.cptr = addr; /* DSP memory location */
++
++ /*Maps address first*/
++ rc=dslhal_support_hostDspAddressTranslate((unsigned int)addr);
++ dprintf(5, "NewAddr: %08x\n", rc);
++ if(rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
++ {
++ dprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
++ return DSLHAL_ERROR_ADDRESS_TRANSLATE;
++ }
++
++ dst.cptr=(unsigned char *)rc;
++
++ /* check wether address is at 32bits boundary */
++
++ if ((dst.anint & 0x3) && count)
++ {
++ sword.anint = *(unsigned int*)((unsigned int)src.cptr & 0xfffffffc);
++ dword.anint = DSLHAL_REG32((unsigned int)dst.cptr & 0xfffffffc);
++ sword.anint = (unsigned int) dslhal_support_byteSwap32(sword.anint);
++ dword.anint = (unsigned int) dslhal_support_byteSwap32(dword.anint);
++ ptr = (unsigned char *)((unsigned int)dst.cptr & 0xfffffffc);
++
++ if((dst.anint & 3) ==3) /* last byte of a dword */
++ {
++ dword.byte[3] = sword.byte[3];
++ dst.anint++; /* bump the address by one */
++ byteCnt++;
++ count--;
++ }
++
++ if((dst.anint & 3) ==1) /* second byte */
++ {
++ if(count>3)
++ {
++ dword.byte[3] = sword.byte[3];
++ dst.anint++;
++ count--;
++ byteCnt++;
++ }
++ if(count>2)
++ {
++ dword.byte[2] = sword.byte[2];
++ dst.anint++;
++ count--;
++ byteCnt++;
++ }
++ if(count)
++ {
++ dword.byte[1] = sword.byte[1];
++ dst.anint++;
++ count--;
++ byteCnt++;
++ }
++ }
++
++ if((dst.anint & 3) && (count >1))
++ {
++ dword.byte[2] = sword.byte[2];
++ dword.byte[3] = sword.byte[3];
++ byteCnt+=2;
++ dst.anint += 2; /* bump the address by two */
++ count -= 2; /* decrement the byte count by two */
++ }
++
++ if((dst.anint & 3) && (count==1))
++ {
++ dword.byte[2] = sword.byte[2];
++ dst.anint++;
++ byteCnt++;
++ count--;
++ }
++ src.cptr = (char *)((unsigned int)src.cptr & 0xfffffffc); /* fix 032802 */
++ dword.anint = dslhal_support_byteSwap32(dword.anint);
++ DSLHAL_REG32((unsigned int)ptr) = dword.anint;
++ ptr = src.cptr;
++ for(rc=0;rc<count;rc++)
++ {
++ *ptr = *(ptr+byteCnt);
++ ptr++;
++ }
++ }
++
++ /* the dst pointer should now be on a 32-bit boundary */
++
++ while (count > 3)
++ {
++ DSLHAL_REG32((unsigned int)dst.cptr) = dslhal_support_byteSwap32(*src.iptr);
++ src.iptr++; /* bump the data pointer by four */
++ dst.anint += 4; /* bump the address by four */
++ count -= 4; /* decrement the byte count by four */
++ }
++
++ /* write remaining bytes */
++ if(count)
++ {
++ int i;
++
++ data.anint= DSLHAL_REG32((unsigned int)dst.cptr);
++ data.anint=dslhal_support_byteSwap32(data.anint);
++ for (i=0; i< count; i++)
++ {
++ data.byte[i]=*(src.cptr+i);
++ }
++ data.anint=dslhal_support_byteSwap32(data.anint);
++ DSLHAL_REG32((unsigned int)dst.cptr) = data.anint;
++ src.cptr +=count;
++ dst.anint +=count;
++ count=0;
++ }
++ dprintf(6, "dslhal_support_blockWrite done\n");
++ /* Exit Critical Section */
++ shim_osCriticalExit();
++ return DSLHAL_ERROR_NO_ERRORS;
++} /* end of dslhal_support_blockWrite() */
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_blockRead
++*
++*********************************************************************************************
++* DESCRIPTION: This rouin simulates DSP memory read as done in ax5 pci nic card
++*
++* INPUT: void *addr, memory address to be read
++* void *buffer, dat buffer to be filled with from memmory
++* size_t count, number of bytes to be written
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++*
++*****************************************************************************************/
++
++int dslhal_support_blockRead(void *addr, void *buffer, size_t count)
++{
++ int rc;
++ union
++ {
++ int anint; /* DSP location */
++ char *cptr; /* to avoid casts */
++ } src;
++ union
++ {
++ char byte[4];
++ int anint; /* DSP data */
++ } data;
++ union
++ {
++ char *cptr;
++ int *iptr;
++ } dst;
++
++ /* Enter Critical Section */
++ shim_osCriticalEnter();
++
++ dprintf(6,"dslhal_support_blockRead\n");
++
++
++ src.cptr = addr; /* DSP memory location */
++ dst.cptr = buffer; /* local buffer */
++
++ dprintf(6, "Read addr=0x%X, size=0x%X\n", (unsigned int)addr, count);
++
++
++ /*Maps address first*/
++ rc=dslhal_support_hostDspAddressTranslate((unsigned int)addr);
++ if(rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
++ {
++ dprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
++ return DSLHAL_ERROR_ADDRESS_TRANSLATE;
++ }
++
++ src.cptr=(unsigned char *)rc;
++
++ /**********************************************
++ * if the source is NOT on a 32-bit boundary *
++ * then we read the full word *
++ * and ignore the first part of it *
++ **********************************************/
++
++ if ((src.anint & 3) && count)
++ {
++ unsigned int anword;
++
++ anword = DSLHAL_REG32((unsigned int)src.cptr & 0xfffffffc);
++ data.anint = dslhal_support_byteSwap32(anword);
++
++ /************************************
++ * there is no need for case 0 *
++ * notice that there are no breaks *
++ * each falls through to the next *
++ ************************************/
++
++ switch (src.anint & 3)
++ {
++ case 1:
++ /* use only byte[1-3] */
++ *(dst.cptr++) = data.byte[1];
++ src.anint++;
++ count--;
++ case 2:
++ /* use byte[2-3] */
++ if (count)
++ {
++ *(dst.cptr++) = data.byte[2];
++ src.anint++;
++ count--;
++ }
++ case 3:
++ /* use byte[3] */
++ if (count)
++ {
++ *(dst.cptr++) = data.byte[3];
++ src.anint++;
++ count--;
++ }
++ }
++ }
++
++ /* the src pointer should now be on a 32-bit boundary */
++ while (count > 3)
++ {
++ unsigned int anword;
++
++ anword=DSLHAL_REG32((unsigned int)src.cptr);
++
++ *dst.iptr = dslhal_support_byteSwap32(anword);
++ src.anint += 4; /* bump the address by four */
++ dst.iptr++; /* bump the data pointer by four */
++ count -= 4; /* decrement the byte count by four */
++ }
++
++ /*******************************
++ * if there's any count left *
++ * then we read the next word *
++ * and ignore the end of it *
++ *******************************/
++ if (count)
++ {
++ unsigned int anword;
++
++ anword= DSLHAL_REG32((unsigned int)src.cptr);
++ data.anint = dslhal_support_byteSwap32(anword);
++
++ /************************************
++ * there is no need for case 0 *
++ * notice that there are no breaks *
++ * each falls through to the next *
++ ************************************/
++ switch (count)
++ {
++ case 1:
++ /* use byte[0] */
++ *(dst.cptr++) = data.byte[0];
++ src.anint++;
++ count--;
++ break;
++ case 2:
++ /* use byte[0-1] */
++ *(dst.cptr++) = data.byte[0];
++ *(dst.cptr++) = data.byte[1];
++ src.anint +=2;
++ count -= 2;
++ break;
++ case 3:
++ /* use only byte[0-2] */
++ *(dst.cptr++) = data.byte[0];
++ *(dst.cptr++) = data.byte[1];
++ *(dst.cptr++) = data.byte[2];
++ src.anint +=3;
++ count -= 3;
++ break;
++ }
++ }
++ /* Exit Critical Section */
++ shim_osCriticalExit();
++
++ return DSLHAL_ERROR_NO_ERRORS;
++
++} /* end of dslhal_support_blockRead() */
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_readDspMailbox
++*
++*********************************************************************************************
++* DESCRIPTION: Reads a message from the mailbox
++*
++* ARGUMENTS: int *pcmd Pointer to command read
++*
++* RETURNS: 0 if successful
++* 1 if no mail
++* NZ otherwise
++*
++*****************************************************************************************/
++
++int dslhal_support_readDspMailbox(tidsl_t *ptidsl, int *pcmd, int *ptag, int *pprm1, int *pprm2)
++{
++ int rc;
++ int cmd;
++ int tag;
++ int prm1;
++ int prm2;
++ unsigned char dspOutInx;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ DEV_HOST_mailboxControl_t mailboxControl;
++ DEV_HOST_dspHostMsg_t dspMailboxMsg[DEV_HOST_DSPQUEUE_LENGTH];
++
++ dprintf(6,"dslhal_support_readDspMailbox\n");
++
++ /* get the DSP main pointer */
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ /* Read in the command/response buffer */
++ dspOamSharedInterface.dspHostMailboxControl_p = (DEV_HOST_mailboxControl_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.dspHostMailboxControl_p);
++
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.dspHostMailboxControl_p,
++ &mailboxControl, sizeof(DEV_HOST_mailboxControl_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ /* Change the endianness of the Mailbox Pointer */
++ mailboxControl.dspMsgBuf_p = (DEV_HOST_dspHostMsg_t *) dslhal_support_byteSwap32((unsigned int)mailboxControl.dspMsgBuf_p);
++
++ rc = dslhal_support_blockRead((PVOID)mailboxControl.dspMsgBuf_p,
++ &dspMailboxMsg, (sizeof(DEV_HOST_dspHostMsg_t)*DEV_HOST_DSPQUEUE_LENGTH));
++
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ /* Extract the command/response message index */
++ mailboxControl.hostInInx &= 7;
++ mailboxControl.hostOutInx &= 7;
++ mailboxControl.dspOutInx &= 7;
++ mailboxControl.dspInInx &= 7;
++
++
++ /* check for messages in the mailbox */
++
++ if (mailboxControl.dspOutInx == mailboxControl.dspInInx)
++ {
++ return DSLHAL_ERROR_MAILBOX_NOMAIL;
++ /* no messages to read */
++ }
++
++ /* use bDRESPOutInx as index to DRESPMsgBuf */
++
++ cmd = dspMailboxMsg[mailboxControl.dspOutInx].cmd;
++ tag = dspMailboxMsg[mailboxControl.dspOutInx].tag;
++ prm1= dspMailboxMsg[mailboxControl.dspOutInx].param1;
++ prm2= dspMailboxMsg[mailboxControl.dspOutInx].param2;
++
++ mailboxControl.dspOutInx++; /* increment count */
++ mailboxControl.dspOutInx &= 7; /* only two bits */
++
++ dspOutInx = mailboxControl.dspOutInx;
++
++ /* Read in the command response buffer again to take care of changes */
++ mailboxControl.dspOutInx = dspOutInx;
++ rc = dslhal_support_blockWrite(&mailboxControl.dspOutInx,
++ &dspOamSharedInterface.dspHostMailboxControl_p->dspOutInx, sizeof(BYTE));
++
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++
++ /* Is the input parameter address non-zero*/
++
++ if (pcmd)
++ {
++ *pcmd = cmd;
++ }
++ if (ptag)
++ {
++ *ptag = tag;
++ }
++ if (pprm1)
++ {
++ *pprm1 = prm1;
++ }
++ if (pprm2)
++ {
++ *pprm2 = prm2;
++ }
++
++ dprintf(6,"dslhal_support_readDspMailbox done\n");
++ dprintf(6,"cmd=%d, tag=%d\n", cmd, tag);
++ dprintf(6,"dslhal_support_readDspMailbox:cmd: 0x%x, tag=%d\n", cmd, tag);
++ return DSLHAL_ERROR_NO_ERRORS;
++
++} /* end of dslhal_support_readDspMailbox() */
++
++/*******************************************************************************************
++* FUNCTION NAME: dslhal_support_writeHostMailbox
++*
++********************************************************************************************
++* DESCRIPTION: Send a message to a mailbox
++*
++* ARGUMENTS: int cmd command to write
++* int tag tag (currently unused)
++* int p1 parameter 1 (currently unused)
++* int p2 parameter 2 (currently unused)
++*
++* RETURNS: 0 if successful
++* NZ otherwise
++*
++*******************************************************************************************/
++
++int dslhal_support_writeHostMailbox(tidsl_t *ptidsl, int cmd, int tag, int p1, int p2)
++{
++ int rc;
++ int index;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ DEV_HOST_mailboxControl_t mailboxControl;
++ DEV_HOST_dspHostMsg_t hostMailboxMsg[DEV_HOST_HOSTQUEUE_LENGTH];
++ unsigned char hostInInx;
++
++ dprintf(6,"dslhal_support_writeHostMailbox:cmd: 0x%x, tag=%d\n", cmd, tag);
++
++ dprintf(6,"cmd=%d, tag=%d\n", cmd, tag);
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ /* Read in the command/response buffer */
++ dspOamSharedInterface.dspHostMailboxControl_p = (DEV_HOST_mailboxControl_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.dspHostMailboxControl_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.dspHostMailboxControl_p,
++ &mailboxControl, sizeof(DEV_HOST_mailboxControl_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ /* Change the endianness of the Mailbox Control Pointer */
++ mailboxControl.hostMsgBuf_p = (DEV_HOST_dspHostMsg_t *) dslhal_support_byteSwap32((unsigned int)mailboxControl.hostMsgBuf_p);
++ rc = dslhal_support_blockRead((PVOID)mailboxControl.hostMsgBuf_p,
++ &hostMailboxMsg, (sizeof(DEV_HOST_dspHostMsg_t)*DEV_HOST_HOSTQUEUE_LENGTH));
++
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ /* Extract the command/response message index */
++ mailboxControl.hostInInx &= 7;
++ mailboxControl.hostOutInx &= 7;
++ mailboxControl.dspOutInx &= 7;
++ mailboxControl.dspInInx &= 7;
++
++ /* make sure there's room in the mailbox */
++
++ index = mailboxControl.hostInInx;
++ mailboxControl.hostInInx++;
++ mailboxControl.hostInInx &= 7;
++ hostInInx = mailboxControl.hostInInx;
++ if (mailboxControl.hostInInx == mailboxControl.hostOutInx)
++ {
++ /* mailbox is full */
++ return DSLHAL_ERROR_MAILBOX_OVERFLOW;
++ }
++
++ /* use bOCMDInInx as index to OCMDMsgBuf */
++ hostMailboxMsg[index].cmd = (BYTE) cmd;
++ hostMailboxMsg[index].tag = (BYTE) tag;
++ hostMailboxMsg[index].param1 = (BYTE) p1;
++ hostMailboxMsg[index].param2 = (BYTE) p2;
++ rc = dslhal_support_blockWrite(&hostMailboxMsg,
++ (PVOID)mailboxControl.hostMsgBuf_p,
++ sizeof(DEV_HOST_dspHostMsg_t)*DEV_HOST_HOSTQUEUE_LENGTH);
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockWrite failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ rc = dslhal_support_blockWrite(&mailboxControl,
++ &dspOamSharedInterface.dspHostMailboxControl_p,
++ sizeof(DEV_HOST_mailboxControl_t));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++ /* update the index */
++ mailboxControl.hostInInx = hostInInx;
++ rc = dslhal_support_blockWrite(&mailboxControl.hostInInx,
++ &dspOamSharedInterface.dspHostMailboxControl_p->hostInInx,
++ sizeof(BYTE));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++
++ dprintf(6,"dslhal_support_writeHostMailbox done\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++
++}
++/* end of dslhal_support_writeHostMailbox() */
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_readTextMailbox
++*
++*********************************************************************************************
++* DESCRIPTION: Reads a message from the mailbox
++*
++* ARGUMENTS: int *pcmd Pointer to command read
++*
++* RETURNS: 0 if successful
++* 1 if no mail
++* NZ otherwise
++*
++*****************************************************************************************/
++
++int dslhal_support_readTextMailbox(tidsl_t *ptidsl, int *pmsg1, int *pmsg2)
++{
++ int rc;
++ unsigned int msg1;
++ unsigned int msg2;
++ unsigned char textOutInx;
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ DEV_HOST_mailboxControl_t mailboxControl;
++ DEV_HOST_textMsg_t textMailboxMsg[DEV_HOST_TEXTQUEUE_LENGTH];
++
++ dprintf(6,"dslhal_support_readTextMailbox\n");
++
++ /* get the DSP main pointer */
++
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterfacePtr_t) ptidsl->pmainAddr;
++
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ /* Read in the command/response buffer */
++ dspOamSharedInterface.dspHostMailboxControl_p = (DEV_HOST_mailboxControl_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.dspHostMailboxControl_p);
++
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.dspHostMailboxControl_p,
++ &mailboxControl, sizeof(DEV_HOST_mailboxControl_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ /* Change the endianness of the Mailbox Pointer */
++ mailboxControl.textMsgBuf_p = (DEV_HOST_textMsg_t *) dslhal_support_byteSwap32((unsigned int)mailboxControl.textMsgBuf_p);
++
++ rc = dslhal_support_blockRead((PVOID)mailboxControl.textMsgBuf_p,
++ &textMailboxMsg, (sizeof(DEV_HOST_textMsg_t)*DEV_HOST_DSPQUEUE_LENGTH));
++
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ /* Extract the command/response message index */
++
++ mailboxControl.textInInx &= 7;
++ mailboxControl.textOutInx &= 7;
++
++ /* check for messages in the mailbox */
++
++ if (mailboxControl.textOutInx == mailboxControl.textInInx)
++ {
++ return DSLHAL_ERROR_MAILBOX_NOMAIL;
++ /* no messages to read */
++ }
++
++ /* use bDRESPOutInx as index to DRESPMsgBuf */
++
++ msg1 = textMailboxMsg[mailboxControl.textOutInx].msgPart1;
++ msg2 = textMailboxMsg[mailboxControl.textOutInx].msgPart2;
++ msg1 = (unsigned int) dslhal_support_byteSwap32((unsigned int)msg1);
++ msg2 = (unsigned int) dslhal_support_byteSwap32((unsigned int)msg2);
++
++ mailboxControl.textOutInx++; /* increment count */
++ mailboxControl.textOutInx &= 7; /* only two bits */
++
++ textOutInx = mailboxControl.textOutInx;
++
++ /* Read in the command response buffer again to take care of changes */
++
++ mailboxControl.textOutInx = textOutInx;
++
++ rc = dslhal_support_blockWrite(&mailboxControl.textOutInx,
++ &dspOamSharedInterface.dspHostMailboxControl_p->textOutInx, sizeof(BYTE));
++
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++
++ /* Is the input parameter address non-zero*/
++
++ if (pmsg1)
++ {
++ *pmsg1 = msg1;
++ }
++ if (pmsg2)
++ {
++ *pmsg2 = msg2;
++ }
++
++ dprintf(6,"dslhal_support_readTextMailbox done\n");
++ dprintf(6,"msgPart1=%d, msgPart2=%d\n", msg1, msg2);
++ dprintf(6,"dslhal_support_readTextMailbox:Message Part1: 0x%x, tag=0x%x\n", msg1, msg2);
++ return DSLHAL_ERROR_NO_ERRORS;
++
++} /* end of dslhal_support_readTextMailbox() */
++
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_hostDspCodeDownload()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* download DSP image from host memory to dsp memory
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++int dslhal_support_hostDspCodeDownload(tidsl_t * ptidsl)
++{
++
++ unsigned int index;
++ int rc = 0, i;
++ unsigned char *iptr; /* image pointer */
++ unsigned int numbytes,olayXfer,olayStore;
++ /* unsigned int holdSecPhyAddr=0,holdSecVirtAddr; */
++ unsigned int *olayStart;
++ size_t len; /* size of the file */
++ size_t expoffset; /* expected offset for next section header */
++ unsigned short checksum;
++ unsigned int crc32;
++ unsigned char * image;
++ char *tmp = (char *)DEV_HOST_DSP_OAM_POINTER_LOCATION;
++ DEV_HOST_dspVersionDef_t dspVersion;
++#if SWTC
++ DEV_HOST_tcHostCommDef_t TCHostCommDef;
++#endif
++ DEV_HOST_oamWrNegoParaDef_t OamWrNegoParaDef;
++ DEV_HOST_dspOamSharedInterface_t dspOamSharedInterface, *pdspOamSharedInterface;
++ DEV_HOST_olayDpDef_t olayDpParms;
++ DEV_HOST_profileBase_t profileList;
++#ifndef NO_ACT
++ DEV_HOST_consBufDef_t constDisp;
++#endif
++#if CO_PROFILES
++ DEV_HOST_coData_t coData;
++#endif
++ DEV_HOST_olayDpPageDef_t olayDpPageDef[NUM_PAGES];
++ union
++ {
++ char byte[4];
++ unsigned short hword[2];
++ unsigned int aword;
++ } data;
++
++ struct _header
++ {
++ char signature[6];
++ unsigned short sectcount;
++ unsigned int length;
++ } header;
++
++ struct _section
++ {
++ unsigned int addr;
++ unsigned int length;
++ unsigned int offset;
++ unsigned int page;
++ };/* section[MAXSECTIONS]; */
++
++ struct _section *sptr;
++ unsigned int secAddr, secLength, secOffset, secPage;
++
++
++ dprintf(5,"dslhal_support_hostDspCodeDownload\n");
++ image = ptidsl->fwimage;
++
++ if (!image)
++ {
++ dprintf(1,"no image file\n");
++ return DSLHAL_ERROR_NO_FIRMWARE_IMAGE;
++ }
++
++ iptr=image;
++
++ numbytes = sizeof(header);
++
++ shim_osMoveMemory((char *) &header, (char *)iptr, numbytes);
++ header.length = dslhal_support_byteSwap32(header.length);
++ header.sectcount = dslhal_support_byteSwap16(header.sectcount);
++#if 0
++ crc32 = dslhal_support_computeCrc32((unsigned char*)&crcTest[0],20);
++ dprintf(6,"CRC-32 for the crcTest: 0x%x",crc32);
++ dprintf(4,"header.length=%d, header.sectcount=0x%X\n", header.length, header.sectcount);
++#endif
++ /* point to the checksum */
++ /* compute the checksum on CRC32 here */
++ iptr = image + header.length-4;
++ numbytes = sizeof(data.aword);
++
++ dprintf(5,"tiload: check checksum\n");
++ shim_osMoveMemory((char *)&(data.byte), (char *)iptr, numbytes);
++
++ crc32 = dslhal_support_computeCrc32(image,ptidsl->imagesize);
++ dprintf(5,"CRC-32 for the Binary: 0x%x",crc32);
++ /* CRC currently not added to the DSP binary, so this code is commented out */
++ /*
++ data.aword = dslhal_support_byteSwap32(data.aword);
++ if (data.aword != crc32)
++ {
++ dprintf(1,"Checksum error\n");
++ }
++ */
++ /* Verify signature - Changed from "320C6x" to "TIDSL" for load 80 */
++
++ header.signature[5]='\0';
++ dprintf(5, "signature=%s\n", header.signature);
++
++ if (shim_osStringCmp(header.signature, "TIDSL"))
++ {
++ dprintf(1,"Signature not match\n");
++ return DSLHAL_ERROR_FIRMWARE_OFFSET;
++ }
++
++ dprintf(5,"tiload: check sect count\n");
++ /* check section count */
++
++ if (header.sectcount > MAXSECTIONS)
++ {
++ dprintf(1,"Section # %d exceeds max %d\n", header.sectcount, MAXSECTIONS);
++ return DSLHAL_ERROR_FIRMWARE_OFFSET;
++ }
++ else
++ {
++ dprintf(5,"found %d sections\n", header.sectcount);
++ }
++
++ /* Validation of Section offsets */
++
++ /* point to the first section */
++ len = header.length; /* file size in bytes */
++ expoffset = sizeof(struct _header) + header.sectcount * sizeof(struct _section);
++
++ dprintf(5,"tiload: check offset\n");
++ for (index=0; index<header.sectcount; index++) /* parse the sections one by one */
++ {
++ numbytes = sizeof(struct _header) + index * sizeof(struct _section); /* Compute Section Offset */
++ sptr = (struct _section *)(image + numbytes); /* Section Pointer to beginning of the section */
++
++ secAddr = dslhal_support_byteSwap32(sptr->addr);
++ secOffset = dslhal_support_byteSwap32(sptr->offset);
++ secLength = dslhal_support_byteSwap32(sptr->length);
++ secPage = dslhal_support_byteSwap32(sptr->page);
++
++ /* validate offset */
++ if ( secOffset== 0xffffffff)
++ {
++ /* special case: zero fill */
++ /* offset is valid, don't change expoffset */
++ }
++ else
++ {
++ if (secOffset > len-4)
++ {
++ dprintf(5,"Offset error\n");
++ return DSLHAL_ERROR_FIRMWARE_OFFSET;
++ }
++
++ /* determine expected offset of NEXT section */
++ expoffset = secLength + secOffset;
++
++ /* all addresses must be on word boundaries */
++ if (secAddr & 3)
++ {
++
++ }
++ }
++ }
++
++ /* check final offset - should just be a checksum left */
++/* IMPORTANT 11/24/02 --> Got this error... but bypassed for Pf of Concept*/
++ /*
++ if (expoffset != len-4)
++ {
++ dprintf(5,"Final offset error\n");
++ return DSLHAL_ERROR_FIRMWARE_OFFSET;
++ }
++ */
++
++ /* Actual Code loading to DSP Memory */
++
++ /* Initialize DSP Data Memory before code load*/
++ dprintf(5,"Zero Prefill DSP DMEM\n");
++ DSLHAL_REG32(ADSLSSADR)=0x80000000;
++ shim_osZeroMemory((char *)0xa1000000, 0x10000);
++ /* Load sections from the image */
++ for (index=0; index<header.sectcount; index++) /* Parse each section */
++ {
++ numbytes = sizeof(header) + index * sizeof(struct _section); /* Compute offset to next section */
++ sptr = (struct _section *)(image + numbytes); /* Point to next section */
++
++ secAddr = dslhal_support_byteSwap32(sptr->addr);
++ secOffset = dslhal_support_byteSwap32(sptr->offset);
++ secLength = dslhal_support_byteSwap32(sptr->length);
++ secPage = dslhal_support_byteSwap32(sptr->page);
++
++ data.aword = secAddr;
++ checksum += data.byte[0] + data.byte[1] + data.byte[2] + data.byte[3];
++
++ data.aword = secLength;
++ checksum += data.byte[0] + data.byte[1] + data.byte[2] + data.byte[3];
++
++ data.aword = secOffset;
++ checksum += data.byte[0] + data.byte[1] + data.byte[2] + data.byte[3];
++
++ data.aword = secPage;
++ checksum += data.byte[0] + data.byte[1] + data.byte[2] + data.byte[3];
++
++
++ /* validate offset */
++ if (secOffset == 0xffffffff)
++ {
++ /* special case: zero fill */
++ /* offset is valid, don't change expoffset */
++ }
++ else
++ {
++ /* real offset */
++ if(secOffset > len-4)
++ {
++ dprintf(5,"section[%u] offset too big (%X/%X)\n", index,
++ secOffset, len-4);
++
++ return DSLHAL_ERROR_FIRMWARE_OFFSET;
++ }
++
++ /* determine expected offset of NEXT section */
++ expoffset = secLength + secOffset;
++
++ }
++
++ }
++
++ /* check final offset - should just be a checksum left */
++ /*
++ if(expoffset != len-4)
++ {
++ dprintf(1,"sections don't span full file (%X/%X)\n",expoffset,len-2);
++ return DSLHAL_ERROR_FIRMWARE_OFFSET;
++ }
++ */
++ dprintf(5,"tiload: load binary\n");
++
++ for (index=0; index<header.sectcount; index++)
++ {
++ numbytes = sizeof(header) + index * sizeof(struct _section);
++ sptr = (struct _section *)(image + numbytes);
++
++ secAddr = dslhal_support_byteSwap32(sptr->addr);
++ secOffset = dslhal_support_byteSwap32(sptr->offset);
++ secLength = dslhal_support_byteSwap32(sptr->length);
++ secPage = dslhal_support_byteSwap32(sptr->page);
++ dprintf(5,"loading section %u\n", index);
++ dprintf(5,"section %u: addr: %X\n", index, secAddr);
++ dprintf(5,"section %u: length: %X\n", index, secLength);
++ dprintf(5,"section %u: offset: %X\n", index, secOffset);
++ dprintf(5,"section %u: page: %X\n", index, secPage);
++
++ /* point to the section's data */
++ if(secOffset != 0xffffffff)
++ {
++ /* Load this section of data */
++ iptr = image + secOffset;
++ dprintf(6, "iptr %8x\n", (unsigned int)iptr);
++ }
++
++ if(secPage)
++ {
++ dprintf(6,"OVERLAY PAGE #%d\n",secPage);
++ /* overlay page, don't write to dsp yet, save into host memory*/
++
++ dprintf(6,"Section Length: %d \n",secLength);
++ ptidsl->olayDpPage[secPage].PmemStartWtAddr = (unsigned int) shim_osAllocateDmaMemory(secLength);
++ if(ptidsl->olayDpPage[secPage].PmemStartWtAddr == NULL)
++ {
++ dprintf(1, "overlay page allocate error\n");
++ return DSLHAL_ERROR_OVERLAY_MALLOC;
++ }
++#ifdef PRE_SILICON
++ ptidsl->olayDpPage[secPage].overlayHostAddr = ((((ptidsl->olayDpPage[secPage].PmemStartWtAddr)-0x84000000)-0x10000000)+0x030b0000);
++#else
++ /* ptidsl->olayDpPage[secPage].overlayHostAddr = ((unsigned int)(ptidsl->olayDpPage[secPage].PmemStartWtAddr)&~0xe0000000); */
++ ptidsl->olayDpPage[secPage].overlayHostAddr = virtual2Physical((unsigned int)ptidsl->olayDpPage[secPage].PmemStartWtAddr);
++#endif
++ dprintf(6,"Allocated Addr: 0x%x \t Xlated Addr: 0x%x \n",ptidsl->olayDpPage[secPage].PmemStartWtAddr,ptidsl->olayDpPage[secPage].overlayHostAddr);
++
++ ptidsl->olayDpPage[secPage].overlayHostAddr = (unsigned int)dslhal_support_byteSwap32(ptidsl->olayDpPage[secPage].overlayHostAddr);
++ ptidsl->olayDpPage[secPage].OverlayXferCount = secLength;
++ ptidsl->olayDpPage[secPage].BinAddr = secAddr;
++ ptidsl->olayDpPage[secPage].SecOffset = secOffset;
++ shim_osMoveMemory((char *)ptidsl->olayDpPage[secPage].PmemStartWtAddr, (char *)iptr, secLength);
++ /* RamP Image ByteSwap test */
++ olayStart = (unsigned int *)ptidsl->olayDpPage[secPage].PmemStartWtAddr;
++
++ for(olayXfer=0;olayXfer< secLength/4;olayXfer++)
++ {
++ olayStore = *(unsigned int *)olayStart;
++ olayStore = (unsigned int)dslhal_support_byteSwap32(olayStore);
++ *(unsigned int*)olayStart = olayStore;
++ dprintf(5, "Addr:0x%x \t Content: 0x%x \n",olayStart,olayStore);
++ olayStart++;
++ olayStore=0;
++ }
++ /* RamP Image ByteSwap test */
++ /* compute the CRC of each overlay page and Store the Checksum in a local global variable */
++ /* This Value of CRC is to be compared with the header where all the CRC bytes are lumped together */
++ ptidsl->olayDpPage[secPage].olayPageCrc32 = dslhal_support_computeCrc32((char *)ptidsl->olayDpPage[secPage].PmemStartWtAddr, ptidsl->olayDpPage[secPage].OverlayXferCount);
++
++ shim_osWriteBackCache((void *)ptidsl->olayDpPage[secPage].PmemStartWtAddr, secLength);
++ }
++ else
++ {
++ rc = secAddr&0xff000000;
++ if(rc && rc!=0x80000000)
++ {
++ dprintf(4,"Not DSP PMEM/DMEM\n");
++ /* don't write to dsp, save into host memory*/
++ dprintf(4,"Section Addr: %x Section Length: %d \n",secAddr,secLength);
++ ptidsl->coProfiles.PmemStartWtAddr = (unsigned int) shim_osAllocateDmaMemory(secLength);
++ if(ptidsl->coProfiles.PmemStartWtAddr == NULL)
++ {
++ dprintf(1, "memory allocate error\n");
++ return DSLHAL_ERROR_OVERLAY_MALLOC;
++ }
++ ptidsl->coProfiles.overlayHostAddr = virtual2Physical((unsigned int)ptidsl->coProfiles.PmemStartWtAddr);
++ dprintf(4,"Allocated Addr: 0x%x \t Xlated Addr: 0x%x \n",ptidsl->coProfiles.PmemStartWtAddr, ptidsl->coProfiles.overlayHostAddr);
++ ptidsl->coProfiles.overlayHostAddr = (unsigned int)dslhal_support_byteSwap32(ptidsl->coProfiles.overlayHostAddr);
++ ptidsl->coProfiles.OverlayXferCount = secLength;
++ ptidsl->coProfiles.BinAddr = secAddr;
++ ptidsl->coProfiles.SecOffset = secOffset;
++
++ shim_osMoveMemory((char *)ptidsl->coProfiles.PmemStartWtAddr, (char *)iptr, secLength);
++ /* RamP Image ByteSwap test */
++ olayStart = (unsigned int *)ptidsl->coProfiles.PmemStartWtAddr;
++
++ for(olayXfer=0;olayXfer< secLength/4;olayXfer++)
++ {
++ olayStore = *(unsigned int *)olayStart;
++ olayStore = (unsigned int)dslhal_support_byteSwap32(olayStore);
++ *(unsigned int*)olayStart = olayStore;
++ dprintf(5, "Addr:0x%x \t Content: 0x%x \n",olayStart,olayStore);
++ olayStart++;
++ olayStore=0;
++ }
++ shim_osWriteBackCache((void *)ptidsl->coProfiles.PmemStartWtAddr, secLength);
++ }
++ else
++ {
++ /* IMPORTANT: write image to DSP memory */
++ rc=dslhal_support_blockWrite((void *)iptr, (void *)secAddr, secLength);
++ if(rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ shim_osClockWait(0x50000);
++ /*
++ rc=dslhal_support_blockRead((void*)secAddr, (void*)tmpBuffer, secLength);
++ if(rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ for(i=0;i<secLength;i++)
++ {
++ if(*iptr
++ }*/
++ }
++ }
++ } /* end of write dsp image */
++
++ /***********************************************************************************
++ * Start to fillup various values to our hardware structure for late use
++ ************************************************************************************/
++
++ /* get main pointer for data */
++
++ rc = dslhal_support_blockRead(tmp, &pdspOamSharedInterface, sizeof(unsigned int));
++ dprintf(5, "tmp=0x%X, addr=0x%X\n", (unsigned int)tmp, (unsigned int)pdspOamSharedInterface);
++ pdspOamSharedInterface= (DEV_HOST_dspOamSharedInterface_t *)dslhal_support_byteSwap32((unsigned int)pdspOamSharedInterface);
++ dprintf(5, "tmp=0x%X, addr=0x%X\n", (unsigned int)tmp, (unsigned int)pdspOamSharedInterface);
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ if(!pdspOamSharedInterface)
++ {
++ dprintf(1,"Couldn't read main pointer\n");
++ return DSLHAL_ERROR_INVALID_PARAM;
++ }
++
++ ptidsl->pmainAddr=pdspOamSharedInterface;
++
++ /* read the OamSharedInterfaceStructure */
++
++ dprintf(5,"ptidsl->hostIf.mainAddr=0x%X\n", (unsigned int)ptidsl->pmainAddr);
++
++ /* get the pointer to DSP-OAM Shared Interface */
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ /* Communicate the Allocated Memory Address to DSP to choose CO Profiles */
++
++ /* Change the Endianness of the profileList pointer */
++ dspOamSharedInterface.profileList_p = (DEV_HOST_profileBase_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.profileList_p);
++ /* Access the profileList Structure */
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.profileList_p,&profileList, sizeof(DEV_HOST_profileBase_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ dprintf(2,"Old Addr:%x New: %x \n",profileList.hostProfileBase_p,ptidsl->coProfiles.overlayHostAddr);
++ profileList.hostProfileBase_p = (DEV_HOST_coData_t *)ptidsl->coProfiles.overlayHostAddr;
++ rc = dslhal_support_blockWrite(&profileList,(PVOID)dspOamSharedInterface.profileList_p,sizeof(DEV_HOST_profileBase_t));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++
++ /* Communicate the Allocated Memory Address to DSP to do overlays */
++
++ /* Change the Endianness of the olayDpDef pointer */
++ dspOamSharedInterface.olayDpParms_p = (DEV_HOST_olayDpDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.olayDpParms_p);
++ /* Access the olayDpDef Structure */
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.olayDpParms_p,&olayDpParms, sizeof(DEV_HOST_olayDpDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++
++ for(i=1;i<NUM_PAGES;i++)
++ {
++ /* Change the endianness of the olayDpPageDef Pointer */
++ olayDpParms.olayDpPage_p[i] = (DEV_HOST_olayDpPageDef_t *) dslhal_support_byteSwap32((unsigned int)olayDpParms.olayDpPage_p[i]);
++ /* Access the olayDpPageDef Structure */
++ rc = dslhal_support_blockRead((PVOID)olayDpParms.olayDpPage_p[i],&olayDpPageDef[i],sizeof(DEV_HOST_olayDpPageDef_t));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ olayDpPageDef[i].overlayHostAddr = ptidsl->olayDpPage[i].overlayHostAddr;
++ rc = dslhal_support_blockWrite(&olayDpPageDef[i],(PVOID)olayDpParms.olayDpPage_p[i],sizeof(DEV_HOST_olayDpPageDef_t));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++ }
++
++ /* Change the endianness of the Datapump Version Pointer */
++ dspOamSharedInterface.datapumpVersion_p = (DEV_HOST_dspVersionDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.datapumpVersion_p);
++
++ /* get DSPVersion itself */
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.datapumpVersion_p,&dspVersion, sizeof(DEV_HOST_dspVersionDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ /* table_dsp info */
++#if SWTC
++ dspOamSharedInterface.tcHostComm_p = (DEV_HOST_tcHostCommDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.tcHostComm_p);
++ rc = dslhal_support_blockRead(&pdspOamSharedInterface->tcHostComm_p,
++ &pTCHostCommDef, 4);
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ pTCHostCommDef=(DEV_HOST_tcHostCommDef_t *) dslhal_support_byteSwap32((unsigned int)pTCHostCommDef);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.tcHostComm_p,
++ &TCHostCommDef, sizeof(DEV_HOST_tcHostCommDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++#endif
++ /* Select the Multimode Training */
++ dspOamSharedInterface.oamWriteNegoParams_p = (DEV_HOST_oamWrNegoParaDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.oamWriteNegoParams_p);
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.oamWriteNegoParams_p, &OamWrNegoParaDef, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++switch(dspVersion.netService)
++ {
++ case 1: OamWrNegoParaDef.stdMode = MULTI_MODE;
++ dprintf(5,"POTS Service \n");
++ ptidsl->netService = 1;
++ break;
++ case 2: OamWrNegoParaDef.stdMode = GDMT_MODE;
++ dprintf(5,"ISDN Service \n");
++ ptidsl->netService = 2;
++ break;
++ default: OamWrNegoParaDef.stdMode = T1413_MODE;
++ dprintf(5,"Default Service \n");
++ break;
++ }
++
++ ptidsl->AppData.StdMode = (unsigned int)OamWrNegoParaDef.stdMode;
++
++ OamWrNegoParaDef.oamFeature = dslhal_support_byteSwap32((OAMFEATURE_TC_SYNC_DETECT_MASK));
++ /* Set the flag to start retraining if the margin of the modem drops below
++ default margin during showtime */
++
++ OamWrNegoParaDef.marginMonitorShwtme = FALSE;
++ /* Set the flag to start retraining if the margin of the modem drops below default margin during training */
++
++ OamWrNegoParaDef.marginMonitorTrning = FALSE;
++ OamWrNegoParaDef.dsToneTurnoff_f = 0;
++ dslhal_support_blockWrite(&OamWrNegoParaDef,
++ (PVOID)dspOamSharedInterface.oamWriteNegoParams_p, sizeof(DEV_HOST_oamWrNegoParaDef_t));
++ rc=dslhal_support_setInterruptMask(ptidsl,0);
++ if(rc!=DSLHAL_ERROR_NO_ERRORS)
++ return rc;
++ /* Co Profile Test */
++#if CO_PROFILES
++ dspOamSharedInterface.profileList_p = (DEV_HOST_profileBase_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.profileList_p);
++ /* Access the profileList Structure */
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.profileList_p,&profileList, sizeof(DEV_HOST_profileBase_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ profileList.hostProfileBase_p = (DEV_HOST_coData_t *)dslhal_support_byteSwap32((unsigned int)profileList.hostProfileBase_p);
++ rc = dslhal_support_blockRead((PVOID)profileList.hostProfileBase_p,&coData, sizeof(DEV_HOST_coData_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ dprintf(2,"Current Profile Vendor Id: %x \n",coData.phyAgcPgaTarget);
++ coData.phyAgcPgaTarget = 0xcaba;
++ rc = dslhal_support_blockWrite(&coData,(PVOID)profileList.hostProfileBase_p,sizeof(DEV_HOST_coData_t));
++ if(rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++#endif
++ /* End of CO Profile Test */
++
++#ifndef NO_ACT
++ /* Constellation Display Buffer Allocate */
++ ptidsl->constDisplay.PmemStartWtAddr = (unsigned int) shim_osAllocateDmaMemory(DSP_CONSTELLATION_BUFFER_SIZE);
++ if(ptidsl->constDisplay.PmemStartWtAddr == NULL)
++ {
++ dprintf(1, "memory allocate error\n");
++ return DSLHAL_ERROR_OVERLAY_MALLOC;
++ }
++ shim_osZeroMemory((void*)ptidsl->constDisplay.PmemStartWtAddr,DSP_CONSTELLATION_BUFFER_SIZE);
++ ptidsl->constDisplay.overlayHostAddr = virtual2Physical((unsigned int)ptidsl->constDisplay.PmemStartWtAddr);
++ dprintf(4,"Allocated Addr: 0x%x \t Xlated Addr: 0x%x \n",ptidsl->constDisplay.PmemStartWtAddr, ptidsl->constDisplay.overlayHostAddr);
++ ptidsl->constDisplay.OverlayXferCount = DSP_CONSTELLATION_BUFFER_SIZE;
++
++ /* Communicate the Allocated Buffer for DSP load Constellation Data */
++
++ /* Change the Endianness of the profileList pointer */
++ dspOamSharedInterface.consDispVar_p = (DEV_HOST_consBufDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.consDispVar_p);
++ /* Access the profileList Structure */
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.consDispVar_p,&constDisp, sizeof(DEV_HOST_consBufDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ dprintf(2,"Constellation Old Addr:%x New: %x \n",constDisp.consDispStartAddr,ptidsl->constDisplay.overlayHostAddr);
++ constDisp.consDispStartAddr = (unsigned int)dslhal_support_byteSwap32(ptidsl->constDisplay.overlayHostAddr);
++ constDisp.consDispCurrentAddr = constDisp.consDispStartAddr;
++ constDisp.consDispBufLen = (unsigned int)dslhal_support_byteSwap32(DSP_CONSTELLATION_BUFFER_SIZE);
++ rc = dslhal_support_blockWrite(&constDisp,(PVOID)dspOamSharedInterface.consDispVar_p,sizeof(DEV_HOST_consBufDef_t));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++#endif
++ dprintf(5,"dslhal_support_hostDspCodeDownload() completed.\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++
++} /* end of dslhal_support_hostDspCodeDownload() */
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_readDelineationState()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* download DSP image from host memory to dsp memory
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++unsigned int dslhal_support_readDelineationState(tidsl_t * ptidsl)
++{
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ DEV_HOST_atmStats_t atmStats;
++ DEV_HOST_dsAtmStats_t dsAtmStats0;
++ unsigned int rc=0, delinState=0;
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterface_t *) ptidsl->pmainAddr;
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ dspOamSharedInterface.atmStats_p = (DEV_HOST_atmStats_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.atmStats_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.atmStats_p,&atmStats, sizeof(DEV_HOST_atmStats_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ atmStats.ds0_p = (DEV_HOST_dsAtmStats_t *) dslhal_support_byteSwap32((unsigned int)atmStats.ds0_p);
++
++ rc = dslhal_support_blockRead((PVOID)atmStats.ds0_p,&dsAtmStats0, (sizeof(DEV_HOST_dsAtmStats_t)));
++
++ if (rc)
++ return rc;
++ delinState = dslhal_support_byteSwap32(dsAtmStats0.delineationState);
++ if(delinState == TC_SYNC)
++ ptidsl->lConnected = 1;
++ else
++ ptidsl->lConnected = 0;
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_processModemStateBitField()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* download DSP image from host memory to dsp memory
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++unsigned int dslhal_support_processModemStateBitField(tidsl_t * ptidsl)
++{
++ int rc, offset[2]={2,0};
++ int modemStateBitFields[NUMBER_OF_BITFIELDS],changedField=0;
++ rc = dslhal_api_dspInterfaceRead(ptidsl,(unsigned int)ptidsl->pmainAddr,2,(unsigned int *)&offset,
++ (unsigned char *)&modemStateBitFields,NUMBER_OF_BITFIELDS*sizeof(int));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ for(rc=0;rc<NUMBER_OF_BITFIELDS;rc++)
++ dprintf(4,"Bit Field %d: 0x%x \n",rc+1,dslhal_support_byteSwap32((unsigned int)modemStateBitFields[rc]));
++
++ for(rc=NUMBER_OF_BITFIELDS;rc>0;rc--)
++ {
++ if(ptidsl->modemStateBitField[rc-1]!=modemStateBitFields[rc-1])
++ {
++ changedField = rc;
++ break;
++ }
++ }
++ if(changedField)
++ {
++ for(rc=0;rc<32;rc++)
++ {
++ if(modemStateBitFields[changedField-1] & dslhal_support_byteSwap32((BITFIELD_SCAN >> rc)))
++ break;
++ }
++ dprintf(5,"Changed Field : %d Changed Bit : %d \n",changedField,(31-rc));
++ ptidsl->rState = ((changedField*100) + (31-rc));
++ dprintf(5,"Modem State : %d \n",ptidsl->rState);
++ shim_osMoveMemory((void *)ptidsl->modemStateBitField,(void *)modemStateBitFields, 4*NUMBER_OF_BITFIELDS);
++ }
++
++ switch(changedField)
++ {
++ case 1: if((ptidsl->rState >= ATU_RIDLE) && (ptidsl->AppData.bState < RSTATE_IDLE))
++ ptidsl->AppData.bState = RSTATE_IDLE;
++ if((ptidsl->rState >= GDMT_NSFLR) && (ptidsl->AppData.bState < RSTATE_INIT))
++ ptidsl->AppData.bState = RSTATE_INIT;
++ if((ptidsl->rState >= GDMT_ACKX) && (ptidsl->AppData.bState < RSTATE_HS))
++ ptidsl->AppData.bState = RSTATE_HS;
++ break;
++
++ case 2: if((ptidsl->rState >= T1413_NSFLR) && (ptidsl->AppData.bState < RSTATE_INIT))
++ ptidsl->AppData.bState = RSTATE_INIT;
++ if((ptidsl->rState >= T1413_ACKX) && (ptidsl->AppData.bState < RSTATE_HS))
++ ptidsl->AppData.bState = RSTATE_HS;
++ if((ptidsl->rState == ATU_RSHOWTIME) && (ptidsl->AppData.bState < RSTATE_SHOWTIME))
++ ptidsl->AppData.bState = RSTATE_SHOWTIME;
++ break;
++
++ case 3: if((ptidsl->rState >= ADSL2_COMB3) && (ptidsl->AppData.bState < RSTATE_INIT))
++ ptidsl->AppData.bState = RSTATE_INIT;
++ if((ptidsl->rState >= ADSL2_RPARAMS) && (ptidsl->AppData.bState < RSTATE_HS))
++ ptidsl->AppData.bState = RSTATE_HS;
++ break;
++
++ case 4: break;
++ default: break;
++ }
++
++ ptidsl->stateTransition = modemStateBitFields[1];
++ switch(ptidsl->AppData.bState)
++ {
++ case RSTATE_IDLE: ptidsl->AppData.idleTick=shim_osClockTick();
++ ptidsl->AppData.initTick=0;
++ ptidsl->AppData.showtimeTick=0;
++ break;
++ case RSTATE_HS: if(!ptidsl->AppData.initTick)
++ {
++ ptidsl->AppData.initTick=shim_osClockTick();
++ }
++ ptidsl->AppData.showtimeTick=0;
++ break;
++ case RSTATE_SHOWTIME: if(!ptidsl->AppData.showtimeTick)
++ ptidsl->AppData.showtimeTick=shim_osClockTick();
++ break;
++ default: break;
++ }
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_setInterruptMask()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++unsigned int dslhal_support_setInterruptMask(tidsl_t * ptidsl,unsigned int inputMask)
++{
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ DEV_HOST_hostInterruptMask_t interruptMask;
++ unsigned int rc=0;
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterface_t *) ptidsl->pmainAddr;
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ dspOamSharedInterface.hostInterruptMask_p =(DEV_HOST_hostInterruptMask_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.hostInterruptMask_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.hostInterruptMask_p,
++ &interruptMask, sizeof(DEV_HOST_hostInterruptMask_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ if(inputMask & MASK_MAILBOX_INTERRUPTS)
++ {
++ dprintf(7,"Mailbox Interrupts Masked \n");
++ dprintf(7,"interruptMask.maskBitField1 = %d \n",dslhal_support_byteSwap32(interruptMask.maskBitField1));
++ interruptMask.maskBitField1 |= dslhal_support_byteSwap32(MASK_MAILBOX_INTERRUPTS);
++ dprintf(7,"interruptMask.maskBitField1 = %d \n",dslhal_support_byteSwap32(interruptMask.maskBitField1));
++ }
++ if(inputMask & MASK_BITFIELD_INTERRUPTS)
++ {
++ dprintf(7,"Bit field Interrupts Masked \n");
++ dprintf(7,"interruptMask.maskBitField1 = %d \n",dslhal_support_byteSwap32(interruptMask.maskBitField1));
++ interruptMask.maskBitField1 |= dslhal_support_byteSwap32(MASK_BITFIELD_INTERRUPTS);
++ dprintf(7,"interruptMask.maskBitField1 = %d \n",dslhal_support_byteSwap32(interruptMask.maskBitField1));
++ }
++ if(inputMask & MASK_HEARTBEAT_INTERRUPTS)
++ {
++ dprintf(7,"Bit field Interrupts Masked \n");
++ dprintf(7,"interruptMask.maskBitField1 = %d \n",dslhal_support_byteSwap32(interruptMask.maskBitField1));
++ interruptMask.maskBitField1 |= dslhal_support_byteSwap32(MASK_HEARTBEAT_INTERRUPTS);
++ dprintf(7,"interruptMask.maskBitField1 = %d \n",dslhal_support_byteSwap32(interruptMask.maskBitField1));
++ }
++ dslhal_support_blockWrite(&interruptMask,
++ dspOamSharedInterface.hostInterruptMask_p, sizeof(DEV_HOST_hostInterruptMask_t));
++ dprintf(5,"dslhal_support_setInterruptMask() completed.\n");
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_parseInterruptSource()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Parses the Interrupt Source Bit Field
++*
++* Return: interrupt Code if successful
++* negative error code if failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++unsigned int dslhal_support_parseInterruptSource(tidsl_t * ptidsl)
++{
++ DEV_HOST_dspOamSharedInterface_t *pdspOamSharedInterface, dspOamSharedInterface;
++ DEV_HOST_hostInterruptSource_t interruptSource;
++ unsigned int rc=0,intrCode=0;
++ pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterface_t *) ptidsl->pmainAddr;
++ rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return (0-DSLHAL_ERROR_BLOCK_READ);
++ }
++ dspOamSharedInterface.hostInterruptSource_p =(DEV_HOST_hostInterruptSource_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.hostInterruptSource_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.hostInterruptSource_p,
++ &interruptSource, sizeof(DEV_HOST_hostInterruptSource_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return (0-DSLHAL_ERROR_BLOCK_READ);
++ }
++ if(interruptSource.sourceBitField1 & dslhal_support_byteSwap32(MASK_MAILBOX_INTERRUPTS))
++ {
++ dprintf(7,"Mailbox Interrupts Acknowledge \n");
++ intrCode |= 0x00000011;
++ }
++ if(interruptSource.sourceBitField1 & dslhal_support_byteSwap32(MASK_BITFIELD_INTERRUPTS))
++ {
++ dprintf(7,"Bit field Interrupt Acknowledge \n");
++ intrCode |= 0x00001002;
++ }
++ if(interruptSource.sourceBitField1 & dslhal_support_byteSwap32(MASK_HEARTBEAT_INTERRUPTS))
++ {
++ dprintf(7,"HeartBeat Interrupt Acknowledge \n");
++ intrCode |= 0x00100004;
++ }
++
++ interruptSource.sourceBitField1 &=0x0;
++ rc=dslhal_support_blockWrite(&interruptSource,
++ dspOamSharedInterface.hostInterruptSource_p, sizeof(DEV_HOST_hostInterruptSource_t));
++ if(rc)
++ return (0-DSLHAL_ERROR_BLOCK_WRITE);
++ dprintf(5,"dslhal_support_parseInterruptSource() completed.\n");
++ return intrCode;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_byteSwap16()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* input 16 bit short, byte swap from little endian to big endian or vise versa
++*
++********************************************************************************************/
++
++unsigned short dslhal_support_byteSwap16(unsigned short in16Bits)
++{
++ unsigned short out16Bits;
++
++#ifdef EB
++ unsigned char *pchar;
++ unsigned char tmp;
++#endif
++
++ out16Bits = in16Bits;
++
++#ifdef EB
++ pchar = (unsigned char *)(&out16Bits);
++
++ tmp = *pchar;
++ *pchar = *(pchar + 1);
++ *(pchar + 1) = tmp;
++#endif
++
++ return out16Bits;
++
++} /* end of dslhal_support_byteSwap16() */
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_byteSwap32()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* input 32 bit int, byte swap from little endian to big endian or vise versa
++*
++********************************************************************************************/
++
++unsigned int dslhal_support_byteSwap32(unsigned int in32Bits)
++{
++ int out32Bits;
++
++#ifdef EB
++ unsigned char tmp;
++ unsigned char *pchar;
++#endif
++
++ out32Bits = in32Bits;
++
++#ifdef EB
++ pchar = (unsigned char *)(&out32Bits);
++
++ tmp = *pchar;
++ *pchar = *(pchar + 3);
++ *(pchar + 3) = tmp;
++
++ tmp = *(pchar + 1);
++ *(pchar + 1) = *(pchar + 2);
++ *(pchar + 2) = tmp;
++#endif
++
++ return out32Bits;
++
++} /* end of dslhal_support_byteSwap32() */
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_computeCrc32()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Computes the CRC-32 for the input data
++*
++* Return: 32 bit CRC of the input data
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_computeCrc32(unsigned char *data, int len)
++{
++ unsigned int result;
++ int i,j;
++ unsigned char octet;
++
++ if ((len < 4) || (data==NULL))
++ return(0xdeaddead);
++ result = *data++ << 24;
++ result |= *data++ << 16;
++ result |= *data++ << 8;
++ result |= *data++;
++ result = ~ result;
++
++ len -=4;
++
++ for (i=0; i<len; i++)
++ {
++ octet = *(data++);
++ for (j=0; j<8; j++)
++ {
++ if (result & 0x80000000)
++ {
++ result = (result << 1) ^ CRC32_QUOTIENT ^ (octet >> 7);
++ }
++ else
++ {
++ result = (result << 1) ^ (octet >> 7);
++ }
++ octet <<= 1;
++ }
++ }
++ return ~result; /* The complement of the remainder */
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_checkOverlayPage()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Computes the CRC-32 for the input data and compares it with reference
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_checkOverlayPage(tidsl_t *ptidsl, unsigned int tag)
++{
++ unsigned int computedCrc;
++ if((unsigned char *)ptidsl->olayDpPage[tag].PmemStartWtAddr == NULL)
++ {
++ dprintf(5,"Null Address for Page: %d\n",tag);
++ return DSLHAL_ERROR_OVERLAY_MALLOC;
++ }
++ computedCrc = dslhal_support_computeCrc32((unsigned char *)ptidsl->olayDpPage[tag].PmemStartWtAddr, ptidsl->olayDpPage[tag].OverlayXferCount);
++ dprintf(6,"\n Pre-Computed CRC32 = 0x%x \t Current CRC32 = 0x%x \n",ptidsl->olayDpPage[tag].olayPageCrc32,computedCrc);
++ if(computedCrc != ptidsl->olayDpPage[tag].olayPageCrc32)
++ return DSLHAL_ERROR_OVERLAY_CORRUPTED;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_clearTrainingInfo()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Computes the CRC-32 for the input data and compares it with reference
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++int dslhal_support_clearTrainingInfo(tidsl_t *ptidsl)
++{
++ int i;
++
++ for(i=0; i<NUM_PAGES; i++)
++ {
++ if(ptidsl->olayDpPage[i].PmemStartWtAddr !=NULL)
++ {
++ shim_osFreeDmaMemory((void *) ptidsl->olayDpPage[i].PmemStartWtAddr,
++ ptidsl->olayDpPage[i].OverlayXferCount);
++ ptidsl->olayDpPage[i].PmemStartWtAddr =NULL;
++ }
++ }
++ if(ptidsl->coProfiles.PmemStartWtAddr != NULL)
++ {
++ shim_osFreeDmaMemory((void *)ptidsl->coProfiles.PmemStartWtAddr, ptidsl->coProfiles.OverlayXferCount);
++ ptidsl->coProfiles.PmemStartWtAddr = NULL;
++ }
++ return 0;
++}
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_reloadTrainingInfo()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Reload overlay pages from flash or memory
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++int dslhal_support_reloadTrainingInfo(tidsl_t * ptidsl)
++{
++
++ int rc = 0, i;
++ unsigned int olayXfer,olayStore;
++ unsigned int *olayStart;
++
++ unsigned int crc32;
++ DEV_HOST_dspOamSharedInterface_t dspOamSharedInterface;
++ DEV_HOST_olayDpDef_t olayDpParms;
++ DEV_HOST_olayDpPageDef_t olayDpPageDef[NUM_PAGES];
++ DEV_HOST_profileBase_t profileList;
++
++ unsigned int secLength, secOffset, secPage;
++
++ /* co profile */
++ secLength = ptidsl->coProfiles.OverlayXferCount;
++ secOffset = ptidsl->coProfiles.SecOffset;
++ ptidsl->coProfiles.PmemStartWtAddr = (unsigned int) shim_osAllocateDmaMemory(secLength);
++ if(ptidsl->coProfiles.PmemStartWtAddr == NULL)
++ {
++ dprintf(1, "memory allocate error\n");
++ return DSLHAL_ERROR_OVERLAY_MALLOC;
++ }
++ /* holdSecPhyAddr = virtual2Physical((unsigned int)holdSecVirtAddr); */
++ ptidsl->coProfiles.overlayHostAddr = virtual2Physical((unsigned int)ptidsl->coProfiles.PmemStartWtAddr);
++ dprintf(4,"Allocated Addr: 0x%x \t Xlated Addr: 0x%x \n",ptidsl->coProfiles.PmemStartWtAddr, ptidsl->coProfiles.overlayHostAddr);
++ ptidsl->coProfiles.overlayHostAddr = (unsigned int)dslhal_support_byteSwap32(ptidsl->coProfiles.overlayHostAddr);
++
++ rc = shim_read_overlay_page((void *)ptidsl->coProfiles.PmemStartWtAddr, secOffset, secLength);
++ if(rc != secLength)
++ {
++ dprintf(1, "shim_read_overlay_page failed\n");
++ return DSLHAL_ERROR_OVERLAY_MALLOC;
++ }
++
++ /*shim_osMoveMemory((char *)ptidsl->coProfiles.PmemStartWtAddr, (char *)iptr, secLength);*/
++ /* RamP Image ByteSwap test */
++ olayStart = (unsigned int *)ptidsl->coProfiles.PmemStartWtAddr;
++
++ for(olayXfer=0;olayXfer< secLength/4;olayXfer++)
++ {
++ olayStore = *(unsigned int *)olayStart;
++ olayStore = (unsigned int)dslhal_support_byteSwap32(olayStore);
++ *(unsigned int*)olayStart = olayStore;
++ dprintf(5, "Addr:0x%x \t Content: 0x%x \n",olayStart,olayStore);
++ olayStart++;
++ olayStore=0;
++ }
++ shim_osWriteBackCache((void *)ptidsl->coProfiles.PmemStartWtAddr, secLength);
++
++
++ for (secPage=1;secPage<NUM_PAGES; secPage++)
++ {
++
++ dprintf(6,"OVERLAY PAGE #%d\n",secPage);
++
++ secLength = ptidsl->olayDpPage[secPage].OverlayXferCount;
++
++ dprintf(4,"Section[%d] Length: %d \n",secPage, secLength);
++
++ secOffset = ptidsl->olayDpPage[secPage].SecOffset;
++ ptidsl->olayDpPage[secPage].PmemStartWtAddr = (unsigned int) shim_osAllocateDmaMemory(secLength);
++ if(ptidsl->olayDpPage[secPage].PmemStartWtAddr == NULL)
++ {
++ dprintf(1, "overlay page allocate error\n");
++ return DSLHAL_ERROR_OVERLAY_MALLOC;
++ }
++
++ rc = shim_read_overlay_page((void *)ptidsl->olayDpPage[secPage].PmemStartWtAddr,secOffset, secLength);
++ if(rc != secLength)
++ {
++ dprintf(1, "overlay page read error\n");
++ return DSLHAL_ERROR_OVERLAY_MALLOC;
++ }
++
++ /* ptidsl->olayDpPage[secPage].overlayHostAddr = ((unsigned int)(ptidsl->olayDpPage[secPage].PmemStartWtAddr)&~0xe0000000); */
++ ptidsl->olayDpPage[secPage].overlayHostAddr = virtual2Physical((unsigned int)ptidsl->olayDpPage[secPage].PmemStartWtAddr);
++ dprintf(6,"Allocated Addr: 0x%x \t Xlated Addr: 0x%x \n",ptidsl->olayDpPage[secPage].PmemStartWtAddr,ptidsl->olayDpPage[secPage].overlayHostAddr);
++
++ ptidsl->olayDpPage[secPage].overlayHostAddr = (unsigned int)dslhal_support_byteSwap32(ptidsl->olayDpPage[secPage].overlayHostAddr);
++ /*ptidsl->olayDpPage[secPage].OverlayXferCount = secLength;
++ ptidsl->olayDpPage[secPage].BinAddr = secAddr;
++ shim_osMoveMemory((char *)ptidsl->olayDpPage[secPage].PmemStartWtAddr, (char *)iptr, secLength);
++ */
++ olayStart = (unsigned int *)ptidsl->olayDpPage[secPage].PmemStartWtAddr;
++
++ for(olayXfer=0;olayXfer< secLength/4;olayXfer++)
++ {
++ olayStore = *(unsigned int *)olayStart;
++ olayStore = (unsigned int)dslhal_support_byteSwap32(olayStore);
++ *(unsigned int*)olayStart = olayStore;
++ dprintf(5, "Addr:0x%x \t Content: 0x%x \n",olayStart,olayStore);
++ olayStart++;
++ olayStore=0;
++ }
++ /* RamP Image ByteSwap test */
++ /* compute the CRC of each overlay page and Store the Checksum in a local global variable */
++ /* This Value of CRC is to be compared with the header where all the CRC bytes are lumped together */
++ crc32 = dslhal_support_computeCrc32((char *)ptidsl->olayDpPage[secPage].PmemStartWtAddr, ptidsl->olayDpPage[secPage].OverlayXferCount);
++ if(crc32 != ptidsl->olayDpPage[secPage].olayPageCrc32)
++ return DSLHAL_ERROR_OVERLAY_MALLOC;
++
++ shim_osWriteBackCache((void *)ptidsl->olayDpPage[secPage].PmemStartWtAddr, secLength);
++ }
++
++
++ dprintf(5,"ptidsl->hostIf.mainAddr=0x%X\n", (unsigned int)ptidsl->pmainAddr);
++
++ /* get the pointer to DSP-OAM Shared Interface */
++ rc = dslhal_support_blockRead(ptidsl->pmainAddr, &dspOamSharedInterface,
++ sizeof(DEV_HOST_dspOamSharedInterface_t));
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ /* Communicate the Allocated Memory Address to DSP to choose CO Profiles */
++
++ /* Change the Endianness of the profileList pointer */
++ dspOamSharedInterface.profileList_p = (DEV_HOST_profileBase_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.profileList_p);
++ /* Access the profileList Structure */
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.profileList_p,&profileList, sizeof(DEV_HOST_profileBase_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++ dprintf(2,"Old Addr:%x New: %x \n",profileList.hostProfileBase_p,ptidsl->coProfiles.overlayHostAddr);
++ profileList.hostProfileBase_p = (DEV_HOST_coData_t *)ptidsl->coProfiles.overlayHostAddr;
++ rc = dslhal_support_blockWrite(&profileList,(PVOID)dspOamSharedInterface.profileList_p,sizeof(DEV_HOST_profileBase_t));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++
++ /* Communicate the Allocated Memory Address to DSP to do overlays */
++
++ /* Change the Endianness of the olayDpDef pointer */
++ dspOamSharedInterface.olayDpParms_p = (DEV_HOST_olayDpDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.olayDpParms_p);
++ /* Access the olayDpDef Structure */
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.olayDpParms_p,&olayDpParms, sizeof(DEV_HOST_olayDpDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++
++ for(i=1;i<NUM_PAGES;i++)
++ {
++ /* Change the endianness of the olayDpPageDef Pointer */
++ olayDpParms.olayDpPage_p[i] = (DEV_HOST_olayDpPageDef_t *) dslhal_support_byteSwap32((unsigned int)olayDpParms.olayDpPage_p[i]);
++ /* Access the olayDpPageDef Structure */
++ rc = dslhal_support_blockRead((PVOID)olayDpParms.olayDpPage_p[i],&olayDpPageDef[i],sizeof(DEV_HOST_olayDpPageDef_t));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ olayDpPageDef[i].overlayHostAddr = ptidsl->olayDpPage[i].overlayHostAddr;
++ rc = dslhal_support_blockWrite(&olayDpPageDef[i],(PVOID)olayDpParms.olayDpPage_p[i],sizeof(DEV_HOST_olayDpPageDef_t));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_WRITE;
++ }
++
++ ptidsl->bOverlayPageLoaded = 1;
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++ /* end of dslhal_support_reloadTrainingInfo() */
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_restoreTrainingInfo()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Computes the CRC-32 for the input data and compares it with reference
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++
++int dslhal_support_restoreTrainingInfo(tidsl_t *ptidsl)
++{
++ int rc;
++
++ rc=1;
++ while(rc != 0)
++ {
++ dslhal_support_clearTrainingInfo(ptidsl);
++ //shim_osCriticalEnter();
++ rc = dslhal_support_reloadTrainingInfo(ptidsl);
++ //shim_osCriticalExit();
++ shim_osClockWait(6400);
++ }
++ return 0;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_advancedIdleProcessing()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Idle State Processing Functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_advancedIdleProcessing(tidsl_t *ptidsl)
++{
++ int rc=0;
++ ptidsl->AppData.bState = RSTATE_IDLE;
++#ifndef NO_ACT
++ rc += dslhal_advcfg_resetBitSwapMessageLog(ptidsl,0);
++ rc += dslhal_advcfg_resetBitSwapMessageLog(ptidsl,1);
++ rc += dslhal_advcfg_resetTrainStateHistory(ptidsl);
++ rc += dslhal_advcfg_getReasonForDrop(ptidsl);
++#endif
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_aocBitSwapProcessing()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Idle State Processing Functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_aocBitSwapProcessing(tidsl_t *ptidsl,unsigned int usDs)
++{
++ int rc=0;
++#ifndef NO_ACT
++ int i;
++ int differentCmd_f;
++ unsigned int dsSwapInx;
++
++ static UINT8 lastAturBitSwapCommands[6] = {0, 0, 0, 0, 0, 0};
++ static UINT8 lastAturBitSwapBinNum[6] = {0, 0, 0, 0, 0, 0};
++
++ if (usDs == 0)
++ {
++ dprintf(4," DSP_XMITBITSWAP\n");
++ rc += dslhal_advcfg_getAocBitswapBuffer(ptidsl,0);
++ ptidsl->usBitSwapInx++;
++ if (ptidsl->usBitSwapInx > 29)
++ ptidsl->usBitSwapInx=0;
++ }
++
++ if (usDs == 1)
++ {
++ dprintf(4," DSP_RCVBITSWAP\n");
++ rc += dslhal_advcfg_getAocBitswapBuffer(ptidsl,1);
++ differentCmd_f = FALSE;
++ dsSwapInx = ptidsl->dsBitSwapInx;
++ if (! rc)
++ {
++ for (i = 0; i < 6; i++)
++ {
++ if (lastAturBitSwapCommands[i] != ptidsl->dsBitSwap[dsSwapInx].bitSwapCommand[i])
++ {
++ differentCmd_f = TRUE;
++ break;
++ }
++ }
++ if (! differentCmd_f)
++ {
++ for (i = 0; i < 6; i++)
++ {
++ if (lastAturBitSwapBinNum[i] != ptidsl->dsBitSwap[dsSwapInx].bitSwapBinNum[i])
++ {
++ differentCmd_f = TRUE;
++ break;
++ }
++ }
++ }
++ //CPE data pump seems to occasionally send us the same bit swap twice in a row with different sframe counter.
++ //Since these are never counted twice by the debug output of AC5, we should not count them twice either.
++ //So, we ignore the sframe_counter in determining whether the most recent bitswap is a duplicate.
++ if (differentCmd_f)
++ {
++ shim_osMoveMemory((void *)lastAturBitSwapCommands, (void *)ptidsl->dsBitSwap[dsSwapInx].bitSwapCommand, 6);
++ shim_osMoveMemory((void *)lastAturBitSwapBinNum, (void *)ptidsl->dsBitSwap[dsSwapInx].bitSwapBinNum, 6);
++ ptidsl->dsBitSwapInx++;
++ if (ptidsl->dsBitSwapInx > 29)
++ ptidsl->dsBitSwapInx = 0;
++ }
++ }
++ }
++#endif
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_gatherEocMessages()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced EOC Buffering functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_gatherEocMessages(tidsl_t *ptidsl,int usDs, int msgPart1, int msgPart2)
++{
++ int rc=0;
++#ifndef NO_ACT
++ rc = dslhal_advcfg_logEocMessages(ptidsl,usDs, msgPart1, msgPart2);
++#endif
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_gatherSnrPerBin()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Snr per bin buffering Functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_gatherSnrPerBin(tidsl_t *ptidsl,unsigned int snrParam)
++{
++ int rc=0;
++#ifndef NO_ACT
++ rc = dslhal_advcfg_getSnrPerBin(ptidsl,snrParam);
++#endif
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_processTrainingState()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Training State Processing Functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_processTrainingState(tidsl_t *ptidsl)
++{
++ int rc=0;
++#ifndef NO_ACT
++
++ if(ptidsl->trainStateInx<120)
++ {
++ rc = dslhal_advcfg_getTrainingState(ptidsl,(void *)&ptidsl->trainHistory[ptidsl->trainStateInx++]);
++ if(ptidsl->trainHistory[(ptidsl->trainStateInx-1)].subStateIndex ==
++ ptidsl->trainHistory[(ptidsl->trainStateInx-2)].subStateIndex)
++ ptidsl->trainStateInx--;
++ }
++ else
++ ptidsl->trainStateInx = 0;
++#endif
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_gatherAdsl2Messages()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Gathers ADSL2 Training Messages
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_gatherAdsl2Messages(tidsl_t *ptidsl,int tag, int param1, int param2)
++{
++ int rc=0;
++ unsigned int adsl2MsgLoc;
++ switch(tag)
++ {
++ case CMSGFMT_INDEX:
++ dprintf(5,"C-Msg-FMT rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSGFMT_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.cMsgFmt,CMSGFMT_SIZE);
++ break;
++ case RMSGFMT_INDEX:
++ case RMSGFMT2_INDEX:
++ dprintf(5,"R-Msg-FMT rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSGFMT_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.rMsgFmt,RMSGFMT_SIZE);
++ break;
++ case CMSGPCB_INDEX:
++ dprintf(5,"C-Msg-PCB rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSGPCB_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.cMsgPcb,CMSGPCB_SIZE);
++ ptidsl->adsl2TrainingMessages.cMsgPcbLen = CMSGPCB_SIZE;
++ break;
++ case CMSGPCB2_INDEX:
++ dprintf(5,"C-Msg-PCB2 rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSGPCB2_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.cMsgPcb,CMSGPCB2_SIZE);
++ ptidsl->adsl2TrainingMessages.cMsgPcbLen = CMSGPCB2_SIZE;
++#ifndef NO_ACT
++ rc += dslhal_advcfg_setBlackOutBits(ptidsl);
++#endif
++ break;
++ case CMSGPCB2L_INDEX:
++ dprintf(5,"C-Msg-PCB2L rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSGPCB2L_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.cMsgPcb,CMSGPCB2L_SIZE);
++ ptidsl->adsl2TrainingMessages.cMsgPcbLen = CMSGPCB2L_SIZE;
++ break;
++ case RMSGPCB_INDEX:
++ case RMSGPCB2L_INDEX:
++ dprintf(5,"R-Msg-PCB rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSGPCB_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.rMsgPcb,RMSGPCB_SIZE);
++ ptidsl->adsl2TrainingMessages.rMsgPcbLen = RMSGPCB_SIZE;
++ break;
++
++ case CMSG1ADSL2_INDEX:
++ dprintf(5,"C-Msg1 rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSG1ADSL2_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.cMsg1,CMSG1ADSL2_SIZE);
++ ptidsl->adsl2TrainingMessages.cMsg1Len = CMSG1ADSL2_SIZE;
++ break;
++ case CMSG2ADSL2_INDEX:
++ dprintf(5,"C-Msg2 rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSG2ADSL2_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.cMsg2,CMSG2ADSL2_SIZE);
++ ptidsl->adsl2TrainingMessages.cMsg2Len = CMSG2ADSL2_SIZE;
++ break;
++ case RMSG1ADSL2_INDEX:
++ dprintf(5,"R-Msg1 rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG1ADSL2_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.rMsg1,RMSG1ADSL2_SIZE);
++ ptidsl->adsl2TrainingMessages.rMsg1Len = RMSG1ADSL2_SIZE;
++ break;
++ case RMSG2ADSL2_INDEX:
++ dprintf(5,"R-Msg2 rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG2ADSL2_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.rMsg2,RMSG2ADSL2_SIZE);
++ ptidsl->adsl2TrainingMessages.rMsg2Len = RMSG2ADSL2_SIZE;
++ break;
++ case CPARAMS_INDEX:
++ dprintf(5,"C-Params rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CPARAMS_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.cParams,CPARAMS_SIZE);
++ ptidsl->adsl2TrainingMessages.cParamsLen = CPARAMS_SIZE;
++ break;
++ case RPARAMS_INDEX:
++ dprintf(5,"R-Params rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RPARAMS_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2TrainingMessages.rParams,RPARAMS_SIZE);
++ ptidsl->adsl2TrainingMessages.rParamsLen = RPARAMS_SIZE;
++ break;
++ case RMSG1LD_INDEX:
++ dprintf(5,"R-Msg1 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG1LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.rMsg1Ld,RMSG1LD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.rMsg1LdLen = RMSG1LD_SIZE;
++ break;
++ case RMSG2LD_INDEX:
++ dprintf(5,"R-Msg2 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG2LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.rMsg2Ld,RMSGxLD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.rMsgxLdLen = RMSGxLD_SIZE;
++ break;
++ case RMSG3LD_INDEX:
++ dprintf(5,"R-Msg3 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG3LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.rMsg3Ld,RMSGxLD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.rMsgxLdLen = RMSGxLD_SIZE;
++ break;
++ case RMSG4LD_INDEX:
++ dprintf(5,"R-Msg4 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG4LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.rMsg4Ld,RMSGxLD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.rMsgxLdLen = RMSGxLD_SIZE;
++ break;
++ case RMSG5LD_INDEX:
++ dprintf(5,"R-Msg5 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG5LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.rMsg5Ld,RMSGxLD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.rMsgxLdLen = RMSGxLD_SIZE;
++ break;
++ case RMSG6LD_INDEX:
++ dprintf(5,"R-Msg6 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG6LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.rMsg6Ld,RMSGxLD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.rMsgxLdLen = RMSGxLD_SIZE;
++ break;
++ case RMSG7LD_INDEX:
++ dprintf(5,"R-Msg7 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG7LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.rMsg7Ld,RMSGxLD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.rMsgxLdLen = RMSGxLD_SIZE;
++ break;
++ case RMSG8LD_INDEX:
++ dprintf(5,"R-Msg8 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG8LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.rMsg8Ld,RMSGxLD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.rMsgxLdLen = RMSGxLD_SIZE;
++ break;
++ case RMSG9LD_INDEX:
++ dprintf(5,"R-Msg9 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, RMSG9LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.rMsg9Ld,RMSGxLD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.rMsgxLdLen = RMSGxLD_SIZE;
++ break;
++ case CMSG1LD_INDEX:
++ dprintf(5,"C-Msg1 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSG1LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.cMsg1Ld,CMSG1LD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.cMsg1LdLen = CMSG1LD_SIZE;
++ break;
++ case CMSG2LD_INDEX:
++ dprintf(5,"C-Msg2 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSG2LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.cMsg2Ld,CMSG2LD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.cMsg2LdLen = CMSG2LD_SIZE;
++ break;
++ case CMSG3LD_INDEX:
++ dprintf(5,"C-Msg3 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSG3LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.cMsg3Ld,CMSG3LD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.cMsg3LdLen = CMSG3LD_SIZE;
++ break;
++ case CMSG4LD_INDEX:
++ dprintf(5,"C-Msg4 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSG4LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.cMsg4Ld,CMSG4LD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.cMsg4LdLen = CMSG4LD_SIZE;
++ break;
++ case CMSG5LD_INDEX:
++ dprintf(5,"C-Msg5 LD rec'd\n");
++ adsl2MsgLoc = dslhal_support_getAdsl2MessageLocation
++ (ptidsl, CMSG5LD_INDEX);
++ rc += dslhal_support_blockRead((PVOID)adsl2MsgLoc,
++ ptidsl->adsl2DiagnosticMessages.cMsg5Ld,CMSG5LD_SIZE);
++ ptidsl->adsl2DiagnosticMessages.cMsg5LdLen = CMSG5LD_SIZE;
++ break;
++ default:
++ dprintf(5,"Unknown ADSL2 Message rec'd\n");
++ break;
++ }
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_getAdsl2MessageLocation()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Gets the address to the ADSL2 Message being looked up
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_getAdsl2MessageLocation(tidsl_t *ptidsl,int msgOffset)
++{
++ int rc=0;
++
++ DEV_HOST_dspOamSharedInterface_t *pSharedInterface, sharedInterface;
++ DEV_HOST_dspWrNegoParaDef_t dspNegoPara;
++ int adsl2MsgString, adsl2MsgAddr;
++
++ pSharedInterface = (DEV_HOST_dspOamSharedInterface_t *) ptidsl->pmainAddr;
++ rc += dslhal_support_blockRead(pSharedInterface, &sharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ sharedInterface.dspWriteNegoParams_p = (DEV_HOST_dspWrNegoParaDef_t *) dslhal_support_adsl2ByteSwap32((unsigned int)sharedInterface.dspWriteNegoParams_p);
++ rc += dslhal_support_blockRead((PVOID)sharedInterface.dspWriteNegoParams_p,&dspNegoPara, sizeof(DEV_HOST_dspWrNegoParaDef_t));
++
++ if (rc)
++ {
++ dprintf(1,"dslhal_support_blockRead failed\n");
++ return DSLHAL_ERROR_BLOCK_READ;
++ }
++
++ adsl2MsgString = dslhal_support_adsl2ByteSwap32((unsigned int)dspNegoPara.adsl2DeltMsgs_p);
++ dprintf(5,"ADSL2 Message String Address: 0x%x\n",adsl2MsgString);
++ rc += dslhal_support_blockRead((PVOID)(adsl2MsgString +
++ ((sizeof(unsigned char *)*msgOffset))),
++ &adsl2MsgAddr, sizeof(int));
++ adsl2MsgAddr = dslhal_support_adsl2ByteSwap32((unsigned int)adsl2MsgAddr);
++ dprintf(5," Message Address: 0x%x\n",adsl2MsgAddr);
++
++ if(rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ else
++ return adsl2MsgAddr;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_getCMsgsRa()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Training Message functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_getCMsgsRa(tidsl_t *ptidsl,void *cMsg)
++{
++ int rc=0;
++ DEV_HOST_raMsgsDef_t raMsgParms;
++ DEV_HOST_dspOamSharedInterface_t dspOamSharedInterface;
++ rc += dslhal_support_blockRead(ptidsl->pmainAddr, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++
++ dspOamSharedInterface.raMsgs_p = (DEV_HOST_raMsgsDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.raMsgs_p);
++
++ rc += dslhal_support_blockRead((PVOID)dspOamSharedInterface.raMsgs_p,
++ &raMsgParms, sizeof(DEV_HOST_raMsgsDef_t));
++ shim_osMoveMemory((void *)cMsg,(void *)raMsgParms.cMsgsRaString,6);
++
++ if(rc)
++ return DSLHAL_ERROR_CONFIG_API_FAILURE;
++ else
++ return DSLHAL_ERROR_NO_ERRORS;
++}
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_gatherRateMessages()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Gathers Rate Training Messages
++* Input
++* tidsl_t *ptidsl : Pointer to application structure
++*
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_gatherRateMessages(tidsl_t * ptidsl)
++{
++ int rc;
++ DEV_HOST_dspWrNegoParaDef_t negoParms;
++ DEV_HOST_dspOamSharedInterface_t dspOamSharedInterface;
++
++ dprintf(1, "dslhal_support_gatherRateMessages\n");
++
++ rc += dslhal_support_blockRead(ptidsl->pmainAddr, &dspOamSharedInterface,sizeof(DEV_HOST_dspOamSharedInterface_t));
++ dspOamSharedInterface.dspWriteNegoParams_p = (DEV_HOST_dspWrNegoParaDef_t *) dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.dspWriteNegoParams_p);
++
++ rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.dspWriteNegoParams_p, &negoParms, sizeof(DEV_HOST_dspWrNegoParaDef_t));
++ if (rc)
++ return DSLHAL_ERROR_BLOCK_READ;
++ else
++ {
++ shim_osMoveMemory((void *)ptidsl->AppData.bCRates1, (void *)negoParms.cRates1, 120);
++ shim_osMoveMemory((void *)ptidsl->AppData.bRRates1, (void *)negoParms.rRates1, 44);
++ }
++return DSLHAL_ERROR_NO_ERRORS;
++}
++
++static unsigned int dslhal_support_adsl2ByteSwap32(unsigned int in32Bits)
++{
++ int out32Bits=0;
++
++#ifdef EB
++ out32Bits = (in32Bits << 24);
++ out32Bits |=((in32Bits & 0x0000ff00) << 8);
++ out32Bits |=((in32Bits & 0xff000000) >> 24);
++ out32Bits |=((in32Bits & 0x00ff0000) >> 8);
++#else
++ out32Bits = in32Bits;
++#endif
++
++ return out32Bits;
++
++} /* end of dslhal_support_byteSwap32() */
+diff -urN linux.old/drivers/atm/sangam_atm/dsl_hal_support.h linux.dev/drivers/atm/sangam_atm/dsl_hal_support.h
+--- linux.old/drivers/atm/sangam_atm/dsl_hal_support.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/dsl_hal_support.h 2005-08-23 04:46:50.101843088 +0200
+@@ -0,0 +1,718 @@
++#ifndef DSL_HAL_SUPPORT_H__
++#define DSL_HAL_SUPPORT_H__ 1
++
++/*******************************************************************************
++* FILE PURPOSE: DSL Driver API functions for Sangam
++*
++********************************************************************************
++* FILE NAME: dsl_hal_functiondefines.c
++*
++* DESCRIPTION:
++* Contains basic DSL HAL API declarations for Sangam
++*
++*
++* (C) Copyright 2001-02, Texas Instruments, Inc.
++* History
++* Date Version Notes
++* 06Feb03 0.00.00 RamP Created
++* 21Mar03 0.00.01 RamP Removed byteswap functions
++* 21Mar03 0.00.02 RamP Added extern osFreeVMemory declaration
++* 10Apr03 0.00.03 RamP Changed declaration for loadFWImage &
++* loadDebugFWImage to remove ptidsl param
++* 12Apr03 0.00.04 RamP Added function to set Interrupt Bit
++* Masks for bitfield & Mailboxes
++* 14Apr03 0.00.05 RamP Added modem state bit field processing
++* 15Apr03 0.00.06 RamP Added function osAllocateVMemory
++* 21Apr03 0.01.00 RamP Added function osAllocateDmaMemory
++* Added function osFreeDmaMemory
++* (Alpha) Added macro virtual2Physical,
++* 22Apr03 0.01.01 RamP Moved acknowledgeInterrupt to api.h
++* 24Apr03 0.01.02 RamP Added checkOvelayPage function
++* 29May03 0.01.03 RamP Added critical enter/exit function decl
++* 06Jun03 0.01.04 RamP Added Interrupt source parsing function
++* 06Oct03 0.01.05 RamP Added function abstraction switches
++* 12Oct03 0.01.06 RamP Added ADSL2 Message function prototypes
++* 14Nov03 0.03.07 RamP Added function to gather Rate Messages
++*******************************************************************************/
++
++#include "dsl_hal_api.h"
++
++#define virtual2Physical(a) (((int)a)&~0xe0000000)
++/* External Function Prototype Declarations */
++
++extern unsigned int shim_osGetCpuFrequency(void);
++extern void shim_osClockWait(int val);
++extern unsigned int shim_osClockTick(void);
++
++extern int shim_osStringCmp(const char *s1, const char *s2);
++
++extern void dprintf( int uDbgLevel, char * szFmt, ...);
++
++extern int shim_osLoadFWImage(unsigned char *firmwareImage);
++extern int shim_osLoadDebugFWImage(unsigned char *debugFirmwareImage);
++extern unsigned int shim_read_overlay_page(void *ptr, unsigned int secOffset, unsigned int secLength);
++extern void shim_osMoveMemory(char *dst, char *src, unsigned int numBytes);
++extern void shim_osZeroMemory(char *dst, unsigned int numBytes);
++
++extern void *shim_osAllocateMemory(unsigned int size);
++extern void *shim_osAllocateVMemory(unsigned int size);
++extern void *shim_osAllocateDmaMemory(unsigned int size);
++
++extern void shim_osFreeMemory(void *ptr, unsigned int size);
++extern void shim_osFreeVMemory(void *ptr, unsigned int size);
++extern void shim_osFreeDmaMemory(void *ptr, unsigned int size);
++
++extern void shim_osWriteBackCache(void *pMem, unsigned int size);
++extern void shim_osCriticalEnter(void);
++extern void shim_osCriticalExit(void);
++
++
++/*******************************************************************************************
++* FUNCTION NAME: dslhal_support_writeHostMailbox
++*
++********************************************************************************************
++* DESCRIPTION: Send a message to a mailbox
++*
++* ARGUMENTS: int cmd command to write
++* int tag tag (currently unused)
++* int p1 parameter 1 (currently unused)
++* int p2 parameter 2 (currently unused)
++*
++* RETURNS: 0 if successful
++* NZ otherwise
++*
++*******************************************************************************************/
++
++int dslhal_support_writeHostMailbox
++(tidsl_t *ptidsl,
++ int cmd,
++ int tag,
++ int p1,
++ int p2);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_readDspMailbox
++*
++*********************************************************************************************
++* DESCRIPTION: Reads a message from the mailbox
++*
++* ARGUMENTS: int *pcmd Pointer to command read
++*
++* RETURNS: 0 if successful
++* 1 if no mail
++* NZ otherwise
++*
++*****************************************************************************************/
++
++int dslhal_support_readDspMailbox
++(tidsl_t *ptidsl,
++ int *pcmd,
++ int *ptag,
++ int *pprm1,
++ int *pprm2);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_readTextMailbox
++*
++*********************************************************************************************
++* DESCRIPTION: Reads a message from the mailbox
++*
++* ARGUMENTS: int *pcmd Pointer to command read
++*
++* RETURNS: 0 if successful
++* 1 if no mail
++* NZ otherwise
++*
++*****************************************************************************************/
++
++int dslhal_support_readTextMailbox
++(tidsl_t *ptidsl,
++ int *pmsg1,
++ int *pmsg2);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_blockRead
++*
++*********************************************************************************************
++* DESCRIPTION: This rouin simulates DSP memory read as done in ax5 pci nic card
++*
++* INPUT: void *addr, memory address to be read
++* void *buffer, dat buffer to be filled with from memmory
++* size_t count, number of bytes to be written
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++*
++*****************************************************************************************/
++
++int dslhal_support_blockRead
++(void *addr,
++ void *buffer,
++ size_t count);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_blockWrite
++*
++*******************************************************************************************
++* DESCRIPTION: This rouin simulates DSP memory write as done in ax5 pci nic card
++*
++* INPUT: void *buffer, data need to written
++* void *adde, memory address to be written
++* size_t count, number of bytes to be written
++*
++* RETURN: 0 --succeeded
++* 1 --Failed
++*
++*****************************************************************************************/
++
++int dslhal_support_blockWrite
++(void *buffer,
++ void *addr,
++ size_t count);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_hostDspAddressTranslate
++*
++*******************************************************************************************
++* DESCRIPTION: This function moves the address window to translate physical address
++*
++* INPUT: unsigned int addr : address that requires translation
++*
++* RETURN: Translated address or error condition
++*
++*
++*****************************************************************************************/
++
++unsigned int dslhal_support_hostDspAddressTranslate
++( unsigned int addr
++);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_unresetDslSubsystem
++*
++*******************************************************************************************
++* DESCRIPTION: This function unreset Dsl Subsystem
++*
++* INPUT: None
++*
++* RETURN: 0 if Pass; 1 if Fail
++*
++*****************************************************************************************/
++int dslhal_support_unresetDslSubsystem
++(void
++);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_unresetDsp()
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction takes ax5 daugter board out of reset.
++*
++* INPUT: None
++*
++* RETURN: 0 --successful.
++* 1 --failed
++*
++*****************************************************************************************/
++int dslhal_support_unresetDsp
++(void
++);
++
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_resetDslSubsystem
++*
++*******************************************************************************************
++* DESCRIPTION: This function unreset Dsl Subsystem
++*
++* INPUT: None
++*
++* RETURN: 0 if Pass; 1 if Fail
++*
++*****************************************************************************************/
++int dslhal_support_resetDslSubsystem
++(void
++);
++
++/******************************************************************************************
++* FUNCTION NAME: dslhal_support_resetDsp()
++*
++*******************************************************************************************
++* DESCRIPTION: This fuction takes ax5 daugter board out of reset.
++*
++* INPUT: None
++*
++* RETURN: 0 --successful.
++* 1 --failed
++*
++*****************************************************************************************/
++int dslhal_support_resetDsp
++(void
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_hostDspCodeDownload()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* download DSP image from host memory to dsp memory
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++int dslhal_support_hostDspCodeDownload
++(tidsl_t * ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_digi_assignMemTestSpace()
++*
++*********************************************************************************************
++* DESCRIPTION: Assigns Memory Space in SDRAM for External Memory Test
++* Input: tidsl_t *ptidsl
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++
++unsigned int dslhal_diags_digi_assignMemTestSpace
++(tidsl_t *ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_digi_readMemTestResult()
++*
++*********************************************************************************************
++* DESCRIPTION: Reads Results of External Memory Test
++* Input: tidsl_t *ptidsl
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++
++unsigned int dslhal_diags_digi_readMemTestResult
++(tidsl_t *ptidsl,
++unsigned int testResult
++);
++
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_codeDownload()
++*
++*********************************************************************************************
++* DESCRIPTION: Brings DSLSS out of Reset, Downloads Diag Firmware,
++* brings DSP out of Reset
++* Input: tidsl_t *ptidsl
++*
++* Return: 0 success
++* 1 failed
++*
++********************************************************************************************/
++
++unsigned int dslhal_diags_codeDownload
++(tidsl_t *ptidsl,
++unsigned char* missingTones
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_anlg_setPgaParams()
++*
++*********************************************************************************************
++* DESCRIPTION: This function instructs the Transciever to transmit the Reverb with missing
++* tones and Medley's with missing tones. These signals are defined in ITU
++* G.992.1 ADSL Standards.
++*
++* Input: Test selects between the Reverb or Medley tests. 0 - Reverb, 1 - Medley
++* Tones selects the .
++* Return: NULL
++*
++********************************************************************************************/
++
++unsigned int dslhal_diags_anlg_setPgaParams
++(tidsl_t *ptidsl,
++int agcFlag,
++short pga1,
++short pga2,
++short pga3,
++short aeq
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_anlg_getRxNoisePower()
++*
++*********************************************************************************************
++* DESCRIPTION: This function instructs the Transciever to transmit the Reverb with missing
++* tones and Medley's with missing tones. These signals are defined in ITU
++* G.992.1 ADSL Standards.
++*
++* Input: Test selects between the Reverb or Medley tests. 0 - Reverb, 1 - Medley
++* Tones selects the .
++* Return: NULL
++*
++********************************************************************************************/
++
++unsigned int dslhal_diags_anlg_getRxNoisePower
++(tidsl_t *ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_diags_anlg_setMissingTones()
++*
++*********************************************************************************************
++* DESCRIPTION: This function instructs the Transciever to transmit the Reverb with missing
++* tones and Medley's with missing tones. These signals are defined in ITU
++* G.992.1 ADSL Standards.
++*
++* Input: Test selects between the Reverb or Medley tests. 0 - Reverb, 1 - Medley
++* Tones selects the .
++* Return: NULL
++*
++********************************************************************************************/
++
++unsigned int dslhal_diags_anlg_setMissingTones
++(tidsl_t *ptidsl,
++unsigned char* missingTones
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_readDelineationState()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* download DSP image from host memory to dsp memory
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_readDelineationState
++(tidsl_t *ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_processModemStateBitField()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* download DSP image from host memory to dsp memory
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_processModemStateBitField
++(tidsl_t *ptidsl
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_setInterruptMask()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++unsigned int dslhal_support_setInterruptMask
++(tidsl_t * ptidsl,
++unsigned int inputMask
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_computeCrc32()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Computes the CRC-32 for the input data
++*
++* Return: 32 bit CRC of the input data
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_computeCrc32
++(unsigned char *data,
++int len
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_checkOverlayPage()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Computes the CRC-32 for the input data and compares it with reference
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_checkOverlayPage
++(tidsl_t *ptidsl,
++unsigned int tag
++);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_restoreTrainingInfo()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Computes the CRC-32 for the input data and compares it with reference
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++int dslhal_support_restoreTrainingInfo(tidsl_t * ptidsl);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_reloadTrainingInfo()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Computes the CRC-32 for the input data and compares it with reference
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++int dslhal_support_reloadTrainingInfo(tidsl_t * ptidsl);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_clearTrainingInfo()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Computes the CRC-32 for the input data and compares it with reference
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++int dslhal_support_clearTrainingInfo(tidsl_t * ptidsl);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_parseInterruptSource()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Sets the host interrupt bit masks
++*
++* Return: 0 success
++* 1 failed
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++
++unsigned int dslhal_support_parseInterruptSource(tidsl_t * ptidsl);
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_advancedIdleProcessing()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Idle State Processing Functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_advancedIdleProcessing(tidsl_t *ptidsl);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_aocBitSwapProcessing()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Bitswap buffer Processing Functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_aocBitSwapProcessing(tidsl_t *ptidsl,unsigned int usDs);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_gatherEocMessages()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced EOC Buffering functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_gatherEocMessages(tidsl_t *ptidsl,int usDs, int msgPart1, int msgPart2);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_gatherSnrPerBin()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Snr per bin buffering Functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_gatherSnrPerBin(tidsl_t *ptidsl,unsigned int snrParm);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_processTrainingState()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Training State Processing Functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_processTrainingState(tidsl_t *ptidsl);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_gatherAdsl2Messages()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced EOC Buffering functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_gatherAdsl2Messages(tidsl_t *ptidsl,int msgTag, int param1, int param2);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_getAdsl2MsgLocation()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Gets the address to the ADSL2 Message being looked up
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_getAdsl2MessageLocation(tidsl_t *ptidsl,int msgOffset);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_getCMsgsRa()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Calls Advanced Training Message functions
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_getCMsgsRa(tidsl_t *ptidsl,void *cMsg);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_gatherRateMessages()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* Gathers Advanced Training Messages
++*
++* Return: Error Condition (if any)
++*
++*
++* NOTE:
++* DSP image is based on LITTLE endian
++*
++********************************************************************************************/
++unsigned int dslhal_support_gatherRateMessages(tidsl_t *ptidsl);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_byteSwap16()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* byteswap a short
++*
++* INPUT:
++* Return: NULL
++*
++********************************************************************************************/
++
++unsigned short dslhal_support_byteSwap16(unsigned short in16Bits);
++
++/********************************************************************************************
++* FUNCTION NAME: dslhal_support_byteSwap32()
++*
++*********************************************************************************************
++* DESCRIPTION:
++* byteswap a word
++*
++* INPUT:
++* Return: NULL
++*
++********************************************************************************************/
++
++unsigned int dslhal_support_byteSwap32(unsigned int in32Bits);
++
++#endif /* Pairs #ifndef DSL_HAL_FUNCTIONDEFINES_H__ */
+diff -urN linux.old/drivers/atm/sangam_atm/dsl_hal_version.h linux.dev/drivers/atm/sangam_atm/dsl_hal_version.h
+--- linux.old/drivers/atm/sangam_atm/dsl_hal_version.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/dsl_hal_version.h 2005-08-23 04:46:50.102842936 +0200
+@@ -0,0 +1,94 @@
++#ifndef __SYSSW_VERSION_H__
++#define __SYSSW_VERSION_H__ 1
++
++/*******************************************************************************
++* FILE PURPOSE: DSL Driver API functions for Sangam
++*
++********************************************************************************
++* FILE NAME: dsl_hal_basicapi.c
++*
++* DESCRIPTION:
++* Contains basic DSL HAL APIs for Sangam
++*
++* (C) Copyright 2003-04, Texas Instruments, Inc.
++* History
++* Date Version Notes
++* 14May03 0.00.00 RamP Original Version Created
++* 14May03 0.00.01 RamP Initial Rev numbers inserted
++* 14May03 0.00.02 RamP Bumped version numbers for Dsl Hal
++* & dhalapp for alpha plus
++* 19May03 0.00.03 MCB Bumped dslhal version number
++* because of dependant changes
++* wrt. linux-nsp atm drivers.
++* 22May03 0.00.04 RamP Bumped dslhal & dhalapp buildnum
++* for inner/outer pair & DGASP code
++* 06Jun03 0.00.05 RamP Bumped up buildnum for LED, STM,
++* interrupt processing, statistics
++* and other pre-beta features
++* 09Jun03 0.00.06 JEB Fixed error in DHALAPP bugfix/buildnum
++* 09Jun03 0.00.07 RamP Bumped up buildnum for incremental
++* changes to apis, statistics, memory
++* fixes, parameter configurations
++* 11Jun03 0.00.08 RamP Bumped up buildnum for Co profile
++* free memory fix
++* 12Jun03 0.00.09 JEB Bumped version numbers for AR7 1.00 Beta
++* 02Jul03 0.00.10 ZT Bumped HAL version for overlay page
++* 18Jul03 0.00.11 RamP Bumped HAL version for analog diags
++* 22Jul03 0.00.12 JEB Bumped DHALAPP buildnum for analog diags
++* 31Jul03 0.00.13 RamP Bumped HAL version for engr. drop
++* 04Aug03 0.00.14 JEB Bumped HAL version buildnum for CHECKPOINT65 changes
++* Bumped LINUX version buildnum for CHECKPOINT65 changes
++* 06Aug03 0.00.15 MCB Bumped all version numbers in prep for AR7 1.0 R2 release for POTS.
++* 13Aug03 0.00.16 MCB Set rev id's for D3/R1.1 (ADSL2).
++* 21Aug03 0.00.17 JEB Bumped up build numbers for merge of code additions from D1
++* 26Sep03 0.00.18 JEB Set rev id's for another D3/R1 (ADSL2).
++* 14Oct03 0.00.19 JEB Bumped Linux minor number and reset bugfix number for release.
++* Bumped build numbers on DSLHAL and DHALAPP for this checkpoint.
++* 14Oct03 0.00.20 JEB Bumped build numbers on DSLHAL and DHALAPP for CHECKPOINT15.
++* 21Oct03 0.00.21 JEB Bumped build number on DSLHAL for CHECKPOINT16.
++* 22Oct03 0.00.22 MCB Bumped all version numbers in support of D3R1 release.
++* 27Oct03 0.00.23 JEB Bumped build numbers on DSLHAL and DHALAPP for CHECKPOINT19.
++* Updated version for DSLAGENT to be 02.01.00.01 for ACT 2.1 R0.
++* 30Oct03 0.00.24 JEB Bumped bugfix number on LINUXATM Version for next release.
++* Bumped build numbers on DSLHAL and DHALAPP
++* 31Oct03 0.00.25 MCB Bumped all version numbers in support of D3R2 release.
++* 14Nov03 0.00.26 JEB Bumped build numbers on DSLHAL and DHALAPP
++* Changed version for DSLAGENT to be 02.00.01.01 for an ACT 2.0 R0
++* 20Nov03 0.00.27 JEB Bumped build number on DSLHAL.
++* Changed version for DSLAGENT to be 02.00.02.00 for the next ACT 2.0 R2
++* 21Nov03 0.00.28 MCB Bumped all version numbers in support of D3R2 release.
++* 21Nov03 0.00.29 JEB Bumped build numbers on DSLHAL and DHALAPP for D3-R0 drop on 11/21.
++* 16Dec03 0.00.30 JEB Bumped build numbers on DSLHAL and DHALAPP for CHECKPOINT31.
++* 21Dec03 0.00.31 MCB Bumped all version numbers in support of D3R2 release.
++* 05Jan04 0.00.32 JEB Bumped build numbers on DSLHAL and Linux ATM for CHECKPOINT 34.
++* 15Jan04 0.00.33 JEB Bumped build numbers on DSLHAL and Linux ATM for CHECKPOINT 36.
++* 26Jan04 0.00.34 JEB Changed Linux ATM version number to be 04.02.03.00.
++* 27Jan04 0.00.35 MCB Bumped all version numbers in support of D3R2 release.
++*******************************************************************************/
++
++/* Dsl Hal API Version Numbers */
++#define DSLHAL_VERSION_MAJOR 03
++#define DSLHAL_VERSION_MINOR 00
++#define DSLHAL_VERSION_BUGFIX 06
++#define DSLHAL_VERSION_BUILDNUM 00
++#define DSLHAL_VERSION_TIMESTAMP 00
++
++/* dhalapp Adam2 Application Version Numbers */
++#define DHALAPP_VERSION_MAJOR 03
++#define DHALAPP_VERSION_MINOR 00
++#define DHALAPP_VERSION_BUGFIX 05
++#define DHALAPP_VERSION_BUILDNUM 00
++
++/* Linux ATM Driver Version Numbers */
++#define LINUXATM_VERSION_MAJOR 04
++#define LINUXATM_VERSION_MINOR 02
++#define LINUXATM_VERSION_BUGFIX 04
++#define LINUXATM_VERSION_BUILDNUM 00
++
++/* DSL Agent Version Numbers */
++#define DSLAGENT_VERSION_MAJOR 02
++#define DSLAGENT_VERSION_MINOR 00
++#define DSLAGENT_VERSION_BUGFIX 02
++#define DSLAGENT_VERSION_BUILDNUM 00
++
++#endif /* pairs with #ifndef __SYSSW_VERSION_H__ */
+diff -urN linux.old/drivers/atm/sangam_atm/ec_errors_cpaal5.h linux.dev/drivers/atm/sangam_atm/ec_errors_cpaal5.h
+--- linux.old/drivers/atm/sangam_atm/ec_errors_cpaal5.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/ec_errors_cpaal5.h 2005-08-23 04:46:50.102842936 +0200
+@@ -0,0 +1,118 @@
++/***************************************************************************
++ Copyright(c) 2001, Texas Instruments Incorporated. All Rights Reserved.
++
++ FILE: ec_errors.h
++
++ DESCRIPTION:
++ This file contains definitions and function declarations for
++ error code support.
++
++ HISTORY:
++ 14Dec00 MJH Added masking to EC_CLASS etc macros
++ 17Sep02 GSG Added HAL support (new class&devices)
++ 03Oct02 GSG Removed C++ style comments
++***************************************************************************/
++#ifndef _INC_EC_ERRORS
++#define _INC_EC_ERRORS
++
++/*
++ 31 - CRITICAL
++ 30-28 - CLASS (ie. DIAG, KERNEL, FLASH, etc)
++ 27-24 - INSTANCE (ie. 1, 2, 3, etc )
++ 23-16 - DEVICE (ie. EMAC, IIC, etc)
++ 15-08 - FUNCTION (ie. RX, TX, INIT, etc)
++ 07-00 - ERROR CODE (ie. NO_BASE, FILE_NOT_FOUND, etc )
++*/
++
++/*---------------------------------------------------------------------------
++ Useful defines for accessing fields within error code
++---------------------------------------------------------------------------*/
++#define CRITICAL_SHIFT 31
++#define CLASS_SHIFT 28
++#define INST_SHIFT 24
++#define DEVICE_SHIFT 16
++#define FUNCTION_SHIFT 8
++#define ERROR_CODE_SHIFT 0
++
++#define CRITICAL_MASK 1
++#define CLASS_MASK 0x07
++#define DEVICE_MASK 0xFF
++#define INST_MASK 0x0F
++#define FUNCTION_MASK 0xFF
++#define ERROR_CODE_MASK 0xFF
++
++#define EC_CLASS(val) ((val&CLASS_MASK) << CLASS_SHIFT)
++#define EC_DEVICE(val) ((val&DEVICE_MASK) << DEVICE_SHIFT)
++#define EC_INST(val) ((val&INST_MASK) << INST_SHIFT)
++#define EC_FUNC(val) ((val&FUNCTION_MASK) << FUNCTION_SHIFT)
++#define EC_ERR(val) ((val&ERROR_CODE_MASK) << ERROR_CODE_SHIFT)
++
++/*---------------------------------------------------------------------------
++ Operation classes
++---------------------------------------------------------------------------*/
++#define EC_HAL EC_CLASS(0)
++#define EC_DIAG EC_CLASS(8)
++
++/*---------------------------------------------------------------------------
++ Device types
++---------------------------------------------------------------------------*/
++#define EC_DEV_EMAC EC_DEVICE(1)
++#define EC_DEV_IIC EC_DEVICE(2)
++#define EC_DEV_RESET EC_DEVICE(3)
++#define EC_DEV_ATMSAR EC_DEVICE(4)
++#define EC_DEV_MEM EC_DEVICE(5)
++#define EC_DEV_DES EC_DEVICE(6)
++#define EC_DEV_DMA EC_DEVICE(7)
++#define EC_DEV_DSP EC_DEVICE(8)
++#define EC_DEV_TMR EC_DEVICE(9)
++#define EC_DEV_WDT EC_DEVICE(10)
++#define EC_DEV_DCL EC_DEVICE(11)
++#define EC_DEV_BBIF EC_DEVICE(12)
++#define EC_DEV_PCI EC_DEVICE(13)
++#define EC_DEV_XBUS EC_DEVICE(14)
++#define EC_DEV_DSLIF EC_DEVICE(15)
++#define EC_DEV_USB EC_DEVICE(16)
++#define EC_DEV_CLKC EC_DEVICE(17)
++#define EC_DEV_RAPTOR EC_DEVICE(18)
++#define EC_DEV_DSPC EC_DEVICE(19)
++#define EC_DEV_INTC EC_DEVICE(20)
++#define EC_DEV_GPIO EC_DEVICE(21)
++#define EC_DEV_BIST EC_DEVICE(22)
++#define EC_DEV_HDLC EC_DEVICE(23)
++#define EC_DEV_UART EC_DEVICE(24)
++#define EC_DEV_VOIC EC_DEVICE(25)
++/* 9.17.02 (new HAL modules) */
++#define EC_DEV_CPSAR EC_DEVICE(0x1A)
++#define EC_DEV_AAL5 EC_DEVICE(0x1B)
++#define EC_DEV_AAL2 EC_DEVICE(0x1C)
++#define EC_DEV_CPMAC EC_DEVICE(0x1D)
++#define EC_DEV_VDMA EC_DEVICE(0x1E)
++#define EC_DEV_VLYNQ EC_DEVICE(0x1F)
++#define EC_DEV_CPPI EC_DEVICE(0x20)
++#define EC_DEV_CPMDIO EC_DEVICE(0x21)
++
++/*---------------------------------------------------------------------------
++ Function types
++---------------------------------------------------------------------------*/
++#define EC_FUNC_READ_CONF EC_FUNC(1)
++#define EC_FUNC_INIT EC_FUNC(2)
++
++/*---------------------------------------------------------------------------
++ Error codes
++---------------------------------------------------------------------------*/
++#define EC_CRITICAL (1<<CRITICAL_SHIFT)
++#define EC_NO_ERRORS 0
++#define EC_VAL_NO_BASE EC_ERR(1)
++#define EC_VAL_NO_RESET_BIT EC_ERR(2)
++#define EC_VAL_NO_RESET EC_ERR(3)
++#define EC_VAL_BAD_BASE EC_ERR(4)
++#define EC_VAL_MALLOCFAILED EC_ERR(5)
++#define EC_VAL_NO_RESETBASE EC_ERR(6)
++#define EC_DEVICE_NOT_FOUND EC_ERR(7)
++
++/*---------------------------------------------------------------------------
++ Function declarations
++---------------------------------------------------------------------------*/
++extern void ec_log_error( unsigned int );
++
++#endif /* _INC_EC_ERRORS */
+diff -urN linux.old/drivers/atm/sangam_atm/ec_errors_cpsar.h linux.dev/drivers/atm/sangam_atm/ec_errors_cpsar.h
+--- linux.old/drivers/atm/sangam_atm/ec_errors_cpsar.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/ec_errors_cpsar.h 2005-08-23 04:46:50.102842936 +0200
+@@ -0,0 +1,118 @@
++/***************************************************************************
++ Copyright(c) 2001, Texas Instruments Incorporated. All Rights Reserved.
++
++ FILE: ec_errors.h
++
++ DESCRIPTION:
++ This file contains definitions and function declarations for
++ error code support.
++
++ HISTORY:
++ 14Dec00 MJH Added masking to EC_CLASS etc macros
++ 17Sep02 GSG Added HAL support (new class&devices)
++ 03Oct02 GSG Removed C++ style comments
++***************************************************************************/
++#ifndef _INC_EC_ERRORS
++#define _INC_EC_ERRORS
++
++/*
++ 31 - CRITICAL
++ 30-28 - CLASS (ie. DIAG, KERNEL, FLASH, etc)
++ 27-24 - INSTANCE (ie. 1, 2, 3, etc )
++ 23-16 - DEVICE (ie. EMAC, IIC, etc)
++ 15-08 - FUNCTION (ie. RX, TX, INIT, etc)
++ 07-00 - ERROR CODE (ie. NO_BASE, FILE_NOT_FOUND, etc )
++*/
++
++/*---------------------------------------------------------------------------
++ Useful defines for accessing fields within error code
++---------------------------------------------------------------------------*/
++#define CRITICAL_SHIFT 31
++#define CLASS_SHIFT 28
++#define INST_SHIFT 24
++#define DEVICE_SHIFT 16
++#define FUNCTION_SHIFT 8
++#define ERROR_CODE_SHIFT 0
++
++#define CRITICAL_MASK 1
++#define CLASS_MASK 0x07
++#define DEVICE_MASK 0xFF
++#define INST_MASK 0x0F
++#define FUNCTION_MASK 0xFF
++#define ERROR_CODE_MASK 0xFF
++
++#define EC_CLASS(val) ((val&CLASS_MASK) << CLASS_SHIFT)
++#define EC_DEVICE(val) ((val&DEVICE_MASK) << DEVICE_SHIFT)
++#define EC_INST(val) ((val&INST_MASK) << INST_SHIFT)
++#define EC_FUNC(val) ((val&FUNCTION_MASK) << FUNCTION_SHIFT)
++#define EC_ERR(val) ((val&ERROR_CODE_MASK) << ERROR_CODE_SHIFT)
++
++/*---------------------------------------------------------------------------
++ Operation classes
++---------------------------------------------------------------------------*/
++#define EC_HAL EC_CLASS(0)
++#define EC_DIAG EC_CLASS(8)
++
++/*---------------------------------------------------------------------------
++ Device types
++---------------------------------------------------------------------------*/
++#define EC_DEV_EMAC EC_DEVICE(1)
++#define EC_DEV_IIC EC_DEVICE(2)
++#define EC_DEV_RESET EC_DEVICE(3)
++#define EC_DEV_ATMSAR EC_DEVICE(4)
++#define EC_DEV_MEM EC_DEVICE(5)
++#define EC_DEV_DES EC_DEVICE(6)
++#define EC_DEV_DMA EC_DEVICE(7)
++#define EC_DEV_DSP EC_DEVICE(8)
++#define EC_DEV_TMR EC_DEVICE(9)
++#define EC_DEV_WDT EC_DEVICE(10)
++#define EC_DEV_DCL EC_DEVICE(11)
++#define EC_DEV_BBIF EC_DEVICE(12)
++#define EC_DEV_PCI EC_DEVICE(13)
++#define EC_DEV_XBUS EC_DEVICE(14)
++#define EC_DEV_DSLIF EC_DEVICE(15)
++#define EC_DEV_USB EC_DEVICE(16)
++#define EC_DEV_CLKC EC_DEVICE(17)
++#define EC_DEV_RAPTOR EC_DEVICE(18)
++#define EC_DEV_DSPC EC_DEVICE(19)
++#define EC_DEV_INTC EC_DEVICE(20)
++#define EC_DEV_GPIO EC_DEVICE(21)
++#define EC_DEV_BIST EC_DEVICE(22)
++#define EC_DEV_HDLC EC_DEVICE(23)
++#define EC_DEV_UART EC_DEVICE(24)
++#define EC_DEV_VOIC EC_DEVICE(25)
++/* 9.17.02 (new HAL modules) */
++#define EC_DEV_CPSAR EC_DEVICE(0x1A)
++#define EC_DEV_AAL5 EC_DEVICE(0x1B)
++#define EC_DEV_AAL2 EC_DEVICE(0x1C)
++#define EC_DEV_CPMAC EC_DEVICE(0x1D)
++#define EC_DEV_VDMA EC_DEVICE(0x1E)
++#define EC_DEV_VLYNQ EC_DEVICE(0x1F)
++#define EC_DEV_CPPI EC_DEVICE(0x20)
++#define EC_DEV_CPMDIO EC_DEVICE(0x21)
++
++/*---------------------------------------------------------------------------
++ Function types
++---------------------------------------------------------------------------*/
++#define EC_FUNC_READ_CONF EC_FUNC(1)
++#define EC_FUNC_INIT EC_FUNC(2)
++
++/*---------------------------------------------------------------------------
++ Error codes
++---------------------------------------------------------------------------*/
++#define EC_CRITICAL (1<<CRITICAL_SHIFT)
++#define EC_NO_ERRORS 0
++#define EC_VAL_NO_BASE EC_ERR(1)
++#define EC_VAL_NO_RESET_BIT EC_ERR(2)
++#define EC_VAL_NO_RESET EC_ERR(3)
++#define EC_VAL_BAD_BASE EC_ERR(4)
++#define EC_VAL_MALLOCFAILED EC_ERR(5)
++#define EC_VAL_NO_RESETBASE EC_ERR(6)
++#define EC_DEVICE_NOT_FOUND EC_ERR(7)
++
++/*---------------------------------------------------------------------------
++ Function declarations
++---------------------------------------------------------------------------*/
++extern void ec_log_error( unsigned int );
++
++#endif /* _INC_EC_ERRORS */
+diff -urN linux.old/drivers/atm/sangam_atm/env_def_defines.h linux.dev/drivers/atm/sangam_atm/env_def_defines.h
+--- linux.old/drivers/atm/sangam_atm/env_def_defines.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/env_def_defines.h 2005-08-23 04:46:50.103842784 +0200
+@@ -0,0 +1,926 @@
++#ifndef __ENV_DEF_DEFINES_H__
++#define __ENV_DEF_DEFINES_H__ 1
++
++//********************************************************************
++//* DMT-BASE ADSL MODEM PROGRAM
++//* TEXAS INSTRUMENTS PROPRIETARTY INFORMATION
++//* AMATI CONFIDENTIAL PROPRIETARY
++//*
++//* (c) Copyright May 1999, Texas Instruments Incorporated.
++//* All Rights Reserved.
++//*
++//* Property of Texas Instruments Incorporated and Amati Communications Corp.
++//*
++//* Restricted Rights - Use, duplication, or disclosure is subject to
++//* restrictions set forth in TI's and Amati program license agreement and
++//* associated documentation
++//*
++//*********************************************************************
++//*
++//* FILENAME: dpsys_defines.h
++//*
++//* ABSTRACT: This file provides a mechanism for defining standard
++//* preprocessor flag sets for datapump.
++//*
++//* TARGET: Non specific.
++//*
++//* TOOLSET: Non specific.
++//*
++//* ACTIVATION:
++//*
++//* HISTORY: DATE AUTHOR DESCRIPTION
++//* 05/11/99 FLW Created
++//* 01/21/00 FLW derfmake changes
++//* 02/07/00 FLW/M.Seidl added _debug targets
++//* 02/23/00 FLW/M.Barnett merged in from G.lite branch
++//* 03/03/00 FLW/M.Barnett added TRELLIS token
++//* 05/11/00 Barnett Added ap036btp & ap037btp support.
++//* 02/07/00 M.Seidl added HW_TEQ, HW_DEC and DC_BIAS tokens
++//* 02/28/00 Derf/Seidl Mod's in support of suppressing compiler warnings for empty source files
++//* 02/28/00 M. Seidl added SWTC token
++//* 02/28/00 M. Seidl added ap0501tp and its _debug target
++//* 03/03/00 M. Seidl added MODPILOT token, ap0307tp_debug has SWDI and FDD enabled
++//* 03/08/00 Jack Huang Added HWRSDEC token
++//* 03/29/00 Derf/Seidl Mod's in support Soft-TC and derfmake
++//* 04/10/00 Jack Huang Added PCIMASTER token
++//* 04/11/00 Jack Huang Added STBFIX token
++//* 04/24/00 M. Seidl ap0500tp has OLAYDP turned on, ap0500tp_debug has OLAYDP turned off now
++//* 04/28/00 M.Seidl added KAPIL token for ap0501tp targets
++//* 06/02/00 P.Sexton Added OAM_EOC token
++//* 06/06/00 M. Seidl added au0501tp target
++//* 06/12/00 Michael Seidl activated h/w TEQ for KAPIL targets, disabled STBFIX for all targets
++//* 06/14/00 Derf added ap0308tp, alphabetized token lists
++//* 06/16/00 Jack Huang added au0501tp_debug target
++//* 06/22/00 M. Seidl Enabled code overlays through EMIF from external memory. Now there are 3
++//* different code overlay schemes that are differentiated by the following tokens:
++//* OLAYDP_PCI: uses PCI DMA in PCI Master Mode
++//* OLAYDP_HOST: Host downloads overlay code into DMEM upon request from DSP
++//* OLAYDP_EMIF: Host downloads overlay code into ext. mem at boot-time. DSP uses
++//* DMA channel 0 to load code into on-chip PMEM
++//* OLAYDP: turns overlays generally on or off
++//* 07/15/00 B.Srinivasan Cleaned up default tokens and tokens for au0501tp, au0501tp_debug,
++//* ap0501tp and ap0501tp_debug targets as well
++//* 07/19/00 B.Srinivasan Made changes w.r.t cleaning/fixing Rufus Interrupt related code
++//* (changed token TC_INTRPT_RUFUS to INTRPT_RUFUS
++//* 06/14/00 Derf added au0501cp
++//* 08/12/00 Yinong Ding Added DPLL_MODE token.
++//* 08/16/00 F. Mujica Moved DOUBLE_XMT_RATE, RX_HPF, and LEAKY_LMS tokens here.
++//* 09/05/00 M. Seidl Changed ap0501tp back to do overlay through PCI (OLAY_PCI = 1)
++//* 09/11/00 M. Seidl moved USB and OLAYDP_HOST definitions to be CHIPSET specific, not target specific
++//* 09/21/00 U.Dasgupta/ Added a token for separate transmit and receive buffers.
++//* F.Mujica (SEPARATE_TX_RX_BUFFERS).
++//* 10/02/00 U.Dasgupta/ Added DPLL and SEPARATE_TX_RX_BUFFER tokens for au0502 target.
++//* F.Mujica
++//* 10/02/00 M. Castellano Added new tokens for new Host/EMIF DSP code overlay.
++//* OLAYDP_2STEP: Host downloads overlay code into ext. mem upon DSP request. DSP
++//* DMA channel 0 to load code into on-chip PMEM. It is a somewhat hybrid version
++//* of OLAYDP_HOST and OLAYDP_EMIF. The test target is ap0502tp.
++//* 10/25/00 Balaji Added tokens for arv500tp target
++//* 10/31/00 U. Iyer Added TEQ_AVG token and set it one for Ax5
++//* 11/02/00 Barnett Added OAM_EOC=0 in defaults at bottom of file.
++//* 11/21/00 M. Seidl turned OLAYDP and AOC off for ap0307tp to make binary compatible w. whql'ed driver
++//* 11/28/00 Paul Hunt added FASTRETRAIN token for fast retrain specific code
++//* 11/28/00 Paul Hunt added PILOTDATA token to control channel estimation and transmission
++//* of data on the upstream pilot tone for ITU standard code loads
++//* 12/20/00 Jack Huang added EIGHTBITSRAM toekn for the targets that use 8-bit SRAM for
++//* interleaver/deinterleaver
++//* 01/11/01 U.Dasgupta Added mp targets and cleaned up GHS/PILOTDATA variables
++//* 01/23/01 U.Dasgupta Cleaned up code within GLITE tokens
++//* 01/23/00 Barnett Added in full EOC support for AP3/Ax5. Got rid of UTC. No longer needed.
++//* 02/08/01 Barnett Added DDC token.
++//* 03/09/01 Nirmal Warke Added in TOKEN definition for line diagnostics (LINE_DIAG): IMP DEPENDENCIES -
++//* TEQ_AVG must be off when LINE_DIAG is on (since they share a union buffer at the same time)
++//* 03/13/01 M. Seidl Recovered ap0500tp target. Added GHS token as PMEM saving option
++//* 03/14/01 Barnett Added ap0500mb target support. Look-and-feel is similar to ap0500tp.
++//* Added seperate-but-equal def's wrt. ISDN Annex B, Annex C, and PROP.
++//* 03/14/01 J. Bergsagel Added EXTERNBERT token.
++//* 03/15/01 Barnett/Balaji Merged AR5(H) -> 03.00.00 datapump.
++//* 03/16/01 Nirmal Warke Added in TOKEN definition for crosstalk performance mods (CROSSTALK): IMP DEPENDENCIES -
++//* TEQ_AVG must be off and LEAKY_LMS must be on when CROSSTALK is on
++//* 03/21/01 Barnett Added support for ar0500lp, ar0500mp, ar0500dp, arv500lp, arv500mp, and arv500dp.
++//* 03/26/01 M. Seidl enabled 64pt IFFT for ap0500mb (Raptor+AD11, FDM)
++//* 03/28/01 J. Bergsagel Removed EXTERNBERT token (now use host intf. var. instead)
++//* 04/03/01 J. Bergsagel Removed condition of DSPDP_CHIPSET_GEN==5 for default defines
++//* Removed LEAKY_LMS token (assumed always 1)
++//* Removed OLAYDP_HOST token (assumed always 0)
++//* Removed RX_HPF token (assumed always 1)
++//* Removed TRIBRID token (not used any more)
++//* Removed FDD token (assumed always 1)
++//* Removed HW_DEC token (assumed always 1)
++//* Removed HW_TEQ token (assumed always 1)
++//* Removed HWRSDEC token (assumed always 1)
++//* Removed ILEC_AD11_ALCATEL337 token (assumed always 0)
++//* Removed ILEC_AD11_HDSLNOISEFIX token (assumed always 0)
++//* Removed ILEC_AD11_MODULATEPILOT token (assumed always 0)
++//* Removed ILEC_AD11_NEWINTERPOLATE token (assumed always 0)
++//* Removed ILEC_AD11_USTXHPF token (assumed always 0)
++//* Removed SWDI token (assumed always 1)
++//* Removed TD_AGC token (assumed always 1)
++//* Removed DSPDP_LEGACY_TARGET token (assumed always 0)
++//* Removed AD11_20, AD11_20NL and AD11_20_NEWPREC token (always 1)
++//* Removed AI token (assumed always 1)
++//* Removed ATUC token (assumed always 0)
++//* Removed EU token (assumed always 0)
++//* Removed EVM2 token (assumed always 0)
++//* Removed INTRPT_RUFUS token (assumed always 0)
++//* Removed MODPILOT token (assumed always 0)
++//* Removed SL and SL_EVM tokens (assumed always 0)
++//* Removed STBIFX token (assumed always 0)
++//* Removed STD token (assumed always 1)
++//* Removed SWDI_LOOPBACK token (assumed always 0)
++//* Removed TID token (assumed always 0)
++//* Removed TII token (assumed always 1)
++//* Removed TIPCI token (assumed always 1)
++//* Removed UDI token (assumed always 1)
++//* Removed DC_BIAS token (assumed always 1)
++//* 04/05/01 Barnett Added DSPDP_ prefix to tokens that originate
++//* in the public interface.
++//* 05/07/01 Jack Huang Removed DOUBLE_XMT_RATE token.
++//* 05/16/01 Barnett Added back in EXTERNBERT token in support
++//* of saving PMEM.
++//* 06/05/01 Jack Huang Fixed the rules for ar0500mp_debug target
++//* 04/23/01 M. Halleck Merge Astro Wu's DDC enhancements
++//* 06/05/01 M. Capps Changed DSP_DEBUG to ENHANCED_SERIAL_DEBUG
++//* 07/03/01 M. Capps Replaced ESD token with !DDC, added DEV_DEBUG
++//* 06/26/01 J. Bergsagel Removed all the old ap03... stuff
++//* Removed OLAYDP_HOST token (again)
++//* Removed CROSSTALK token (assumed always 1)
++//* Removed TEQ_AVG token (assumed always 0)
++//* Removed DE token (assumed always 1)
++//* Removed PVAT token and au0501cp target
++//* Removed FASTRETRAIN token (assumed always 0)
++//* 07/05/01 J. Bergsagel Changed PCIMASTER token to TC_ATM_PCIMASTER
++//* 07/20/01 Umesh Iyer Added ATMBERT token. ATMBERT is conditional on SWTC definition. if SWTC is 0
++//* ATMBERT should be 0. Else it can be 0/1. Default 0.
++//* 07/23/01 J. Bergsagel Changed name from defines_u.h to dpsys_defines.h
++//* 07/24/01 Barnett Added support for build of $(TARGET)_diag mfgr'ing targets.
++//* 08/02/01 Michael Seidl renamed KAPIL token to !AD1X
++//* 08/02/01 Michael Seidl renamed GHS token to PMEMSAVE_GHS
++//* 08/03/01 S.Yim Added MFGR_DIAG token for afe diagnostic
++//* Added AFEDEV token for afe device driver
++//* Added DSPBIOSII token for dsp bios
++//* 09/21/01 Sameer Enable EXTERNBERT. Disable ATMBERT.
++//* 10/01/01 U.Dasgupta Turned off SMART_MARGIN for ap0500mb because of FECs/CRCs;
++//* 10/09/01 Barnett Added support for ar0500db.
++//* 10/12/01 Barnett Disable EXTERNBERT.
++//* 10/15/01 Barnett Turn off SMART_MARGIN.
++//* 11/07/01 Barnett Def'ed ISDN_DEBUG for all targets to avoid compiler warnings.
++//* Assumed defaul value is zero.
++//* 11/13/01 Barnett Reworked ar0500db_debug to build JTAG-bootable load.
++//* The equivalent production target should only be flash-bootable.
++//* 01/11/02 Yim Added TOKEN JTAG to build JTAG load ar0500db_diag.
++//* 01/23/02 U Iyer Added DEBUG_LOG token. Default value 0
++//* 01/31/02 Barnett Added support for ar0700mp target.
++//* 02/04/02 S.Yim Added TOKEN JTAG to build JTAG load ar0500mp_diag
++//* 02/11/02 U Iyer Added MARGIN_DELTA_RETRAIN token. Default value 1
++//* 05/15/02 Sameer V Enabled EXTERNBERT token for AR5 and AU5 platforms. EXTERNBERT is
++//* not supported on AR5H.
++//* 02/14/02 Barnett Don't ref the SWTC feature token if mfgr'ing diag target.
++//* 02/19/02 Yim Added support to build au0502db_diag target.
++//* 03/08/02 Nirmal Warke Added feature token HYBRID_SWITCH
++//* 03/15/02 U G Jani Turned ON Bitswap support for AU5I (au0502db) targets.
++//* 04/08/02 U G Jani Enabled NLNOISEADJSNR token for AU5I targets.
++//* 06/24/02 Seungmok Oh Added PERTONE_EQ token support for those targets:
++//* (ar0500mp_debug, au0502mp_debug, ar0500mp, au0502mp)
++//* 06/26/02 Mallesh Added DS_PWR_CUTBACK token. Default value 1.
++//* 06/27/02 Mallesh Changed default value of DS_PWR_CUTBACK token to 0.
++//* 06/29/02 U.Dasgupta Token cleanup: Removed ISDN_DEBUG token
++//* 04/29/02 Mannering Remove EIGHTBITSRAM, Combined DOUBLEBUFFER with
++//* BITSWAP, added FPGA token
++//* 05/03/02 Mannering cleanup token changed by the new routine names
++//* 05/06/02 Mannering Add tokens OUTBAND and INBAND for codec commands
++//* If both OUTBAND and INBAND are 0 codec register are
++//* memory mapped.
++//* 05/29/2002 S.Yim Removed AD1X, AFEDEV
++//* 08/31/2002 Paul Hunt Added PERTONE_EQ and HYBRID_SWITCH for ar0700mp
++//* 09/12/2002 Paul Hunt Added support for ar0700db target.
++//* 08/07/2002 U.Dasgupta Turned off MARGIN_DELTA_RETRAIN feature for ISDN platforms
++//* 11/14/2002 Paul Hunt Merged AX5 MR6 PC modifications into AR7 codebase, specifically
++//* turned off MARGIN_DELTA_RETRAIN feature for ar0700db target
++//* 08/26/2002 N. Warke Added DUAL_TEQ token. Active only for Ax7 target
++//* 09/26/2002 Mannering Add token CODEC_EMU for codec emulator board
++//* 10/15/2002 Iyer/Molla Added DMT_BIS token for DELT support
++//* 10/21/2002 A. Redfern Added PHY_EC_ENABLE and PHY_PATH_ENABLE tokens
++//* 10/23/2002 A. Redfern Removed LINE_DIAG token
++//* 10/28/2002 J. Bergsagel Cleaned up old targets and cleaned up the token list
++//* 10/30/2002 A. Redfern Added PHY_TDW_ENABLE
++//* 11/01/2002 A. Redfern Removed SMART_MARGIN token
++//* 11/01/2002 Mustafa Turned on SPECTRAL_SHAPING features for Lucent AnyMedia O.69 Interop.
++//* 11/15/2002 Yim/Mannering Added CODEC_EMU token for analog emulation board specifics
++//* 11/15/2002 Iyer/Molla Added DEBUG_DELT and MEM_STR token to support DELT debug
++//* 12/27/2002 Sameer V Added ATM_TC_HW token for Sangam.
++//* 01/06/2003 J. Bergsagel Added default values for NLNOISEADJSNR, ARTT and DS_PWR_CUTBACK
++//* 01/07/2003 S.Yim Modified ar0700db_diag target to turn on ISDN token
++//* 01/22/2003 J. Bergsagel Added back in defines for the debug targets.
++//* 01/21/2003 MCB Implemented Ax7 UNIT-MODULE modular software framework.
++//* 01/31/2003 J. Bergsagel Made debug targets to be for the FPGA platform; non-debug for Sangam.
++//* Turned off DUAL_TEQ, PHY_EC_ENABLE and PHY_PATH_ENABLE by default
++//* for the Sangam (non-debug) targets.
++//* Turned off OLAYDP token by default.
++//* Turned off SWTC and turned on ATM_TC_HW by default for Sangam targets.
++//* 01/29/2003 Sameer V Added ATMBERT_HW token for Sangam.
++//* 02/04/2003 D. Mannering Added CO_PROFILE token
++//* 02/19/2003 Sameer V Added back EXTERNBERT token for ar0700mp_dp and ar0700db_dp targets.
++//* Disabled EXTERNBERT for debug target since it is not supported on the
++//* FPGA platform.
++//* 02/21/2003 A. Redfern Turned off OAM_EOC, AOC and BITSWAP (until memory issues are resolved).
++//* Turned on DUAL_TEQ, PHY_PATH_ENABLE and PHY_EC_ENABLE.
++//* 02/21/2003 D. Mannering Added DEBUG_DUMP.
++//* 03/06/2003 J. Bergsagel Cleaned up tokens for each target and switched diag targets
++//* over to the Sangam platform (instead of the FPGA platform).
++//* 03/07/2003 J. Bergsagel Cleaned up TC and BERT tokens
++//* 03/11/2003 J. Bergsagel Turned on AOC and BITSWAP for Sangam POTS and ISDN targets.
++//* 03/20/2003 Mallesh Added SHALF token.
++//* 03/24/2003 F. Mujica Enable hybrid selection
++//* 03/26/2003 A. Redfern Removed PMEMSAVE_GHS (always = 1).
++//* 04/08/2003 F. Mujica Renamed HYBRID_SWITCH token to PHY_HYB_ENABLE
++//* 04/08/2003 J. Bergsagel Turned off PHY_HYB_ENABLE for _debug targets (FPGA board builds)
++//* 04/09/2003 J. Bergsagel Turned on OLAYDP only for ar0700mp and ar0700db.
++//* Turned on AOC, BITSWAP, and OAM_EOC for ar0700mp and ar0700db.
++//* 04/09/2003 J. Bergsagel Corrected name "PHY_HYB_SELECT" to "PHY_HYB_ENABLE"
++//* 04/15/2003 A. Redfern Turned on ECI_PULSECOM_INTEROP because phase optimization was enabled.
++//* 05/05/2003 D. Mannering Review Comments - turn on AOC, EXTERNBERT, SHALF, for ar0700mp; amd
++//* turn on AOC for ar0700db
++//* 05/11/2003 Prashant S Added DMT_BIS token for AR7 Soft DI work
++//* 05/13/2003 J. Bergsagel Turned on IMPROVED_STAT_SUPPORT_06_03_00 by default for necessary statistics
++//* 05/15/2003 J. Bergsagel Turned off CO_PROFILE for diag targets.
++//* 05/27/2003 U.Dasgupta Added NLNOISEADJSNR_EC token for ISDN - to take care of non-linear noise
++//* (from ISDN splitter) compensation.
++//* 06/02/2003 Z. Yang Added PHY_NDIAG_ENABLE token.
++//* 06/02/2003 Z. Yang Added COMB_LINEDIAG_ENABLE token.
++//* 06/05/2003 P. Hunt Turned on ATUC_CLEARDOWN_CHANGE token for all targets.
++//* 06/05/2003 Mallesh Turned on CENTILLIUM_VENDORID_AND_TXRATE_CHNG to enable logging the vendor ID
++//* for centillium and litespan
++//* 06/05/2003 U.Dasgupta Turned on SHALF token for ISDN.
++//* 06/06/2003 U.Dasgupta Turned on G.hs nonstandard field token for ar0700db target.
++//* 06/12/2003 J. Bergsagel Changed *_debug targets to be for JTAG=1 instead of FPGA targets
++//* IMPORTANT: For non-JTAG cases, "JTAG" should be undefined.
++//* Therefore, "JTAG" should not have a default case at the bottom (JTAG 0)
++//* 06/18/2003 A. Redfern Turned on spectral shaping token for all targets.
++//* 06/23/2003 J. Bergsagel Turned off GHS_NON_STD_FIELD token for ar0700db until bugs are fixed.
++//* 06/23/2003 U G Jani Undid the above change since the bug is fixed.
++//* 06/27/2003 Mallesh Removed all the interop tokens which are no longer required.
++//* 08/20/2003 J. Bergsagel Added default value for OVHD_PMDTEST_PARA and put default section
++//* tokens in alphabetical order.
++//* 10/09/2003 Hanyu Liu Defined token ADSL2_1BIT_TONE to support Rx one bit constellation.
++//* 10/12/2003 Hanyu Liu Defined token ADSL2_BSWP for bitswap.
++//* 10/20/2003 Xiaohui Li Added READSL2_ENABLE token.
++//* 12/01/2003 Seungmok Oh Added TXDF2B_PROFILING token, which is active only for POTS target.
++//* 12/09/2003 Jack Huang Turned on GHS_NON_STD_FIELD support for AR7 POTS targets
++//* 12/16/2003 Mustafa T. Added the necessary definitions for diag target.
++//*****************************************************************************************************
++//*
++//* The default flag settings are:
++//*
++//* -dATUC=1 -dSTD=0 -dISDN=0 -dTIPCI=0 -dTID=0 -dTII=0 -dAI=0
++//* -dEVM2=0 -dEU=0 -dSL=0 -dSL_EVM=1 -dGLITE=0
++//*
++//* and are set after all the per-suffix options have had a chance to
++//* set them. Each flag is only set if it has not previously been set, so
++//* per-suffix settings can override defaults, and command-line defines can
++//* override per-suffix settings.
++//*
++//*****************************************************************************
++
++
++//* ===========================================================================
++//* Suffix codes
++//* The command-line can include -dOBJSFX_xxx to get a flag set
++//* instead of explicitly setting each flag on each CC/ASM command-line.
++//* and the object suffix will control the settings of "feature" constants.
++//* ===========================================================================
++//
++//* ===========================================================================
++// Flag settings for new suffixes (in alphabetical order of suffix)
++// Each suffix has to specify only those flags which differ from the
++// default settings.
++//* ===========================================================================
++// NOTE: Try to keep feature flags in alphabetical order to ease maintenance.
++//* ===========================================================================
++//*
++
++#define CHIPSET_ID_UNKN '?'
++#define CHIPSET_ID_AH 'H'
++#define CHIPSET_ID_AP 'P'
++#define CHIPSET_ID_AR 'R'
++#define CHIPSET_ID_ARV 'R'
++#define CHIPSET_ID_AT 'T'
++#define CHIPSET_ID_AU 'U'
++
++#define CHIPSET_ID2_GENERIC '0'
++#define CHIPSET_ID2_ARV 'R'
++
++ #define DSPDP_IMAGE_ID_STANDARD(code) ( \
++ STANDARD_is_MULTIMODE(code) ? "M" : \
++ STANDARD_is_GDMT(code) ? "D" : \
++ STANDARD_is_GLITE(code) ? "L" : \
++ STANDARD_is_T1413(code) ? "T" : "_")
++
++ #define DSPDP_IMAGE_ID_SERVICE(code) ( \
++ SERVICE_is_POTS(code) ? "P" : \
++ SERVICE_is_ISDN_ANNEXB(code) ? "B" : \
++ SERVICE_is_ISDN_ANNEXC(code) ? "C" : \
++ SERVICE_is_ISDN_PROP(code) ? "I" : "")
++
++// Bit-codes for feature byte in new version.
++//
++// 0000 0000
++// |||| ||||
++// |||| |||+ -- POTS
++// |||| ||+---- ISDN_ANNEXB
++// |||| |+----- ISDN_ANNEXC
++// |||| +------ ISDN_PROP
++// |||+--------
++// ||+--------- GHS
++// |+---------- GLITE
++// +----------- T1413
++//
++//
++#define FEATURE_BIT_T1413 0x80
++#define FEATURE_BIT_GLITE 0x40
++#define FEATURE_BIT_GHS 0x20
++#define FEATURE_BIT_ISDN_PROP 0x08
++#define FEATURE_BIT_ISDN_ANNEXC 0x04
++#define FEATURE_BIT_ISDN_ANNEXB 0x02
++#define FEATURE_BIT_POTS 0x01
++
++#define STANDARD_BITS_MASK (FEATURE_BIT_T1413 | FEATURE_BIT_GLITE | FEATURE_BIT_GHS)
++#define STANDARD_BITS_T1413 FEATURE_BIT_T1413
++#define STANDARD_BITS_GHS FEATURE_BIT_GHS
++#define STANDARD_BITS_GLITE (FEATURE_BIT_GLITE | FEATURE_BIT_GHS)
++#define STANDARD_BITS_GDMT (STANDARD_BITS_T1413 | STANDARD_BITS_GHS)
++#define STANDARD_BITS_MULTIMODE (STANDARD_BITS_T1413 | STANDARD_BITS_GLITE | STANDARD_BITS_GDMT)
++
++#define SERVICE_BIT_ISDN_ANNEXB FEATURE_BIT_ISDN_ANNEXB
++#define SERVICE_BIT_ISDN_ANNEXC FEATURE_BIT_ISDN_ANNEXC
++#define SERVICE_BIT_ISDN_PROP FEATURE_BIT_ISDN_PROP
++#define SERVICE_BIT_POTS FEATURE_BIT_POTS
++
++//
++// Debug new-style suffixes
++//
++//
++
++#if defined(OBJSFX_ar0700db_debugobj)
++#ifndef OBJSFX_ar0700dbobj
++#define OBJSFX_ar0700dbobj 1
++#endif
++// Here, in alphabetic order, are the feature tokens that
++// distinguish this suffix from its non-_debug partner:
++// (All other tokens from the non-_debug partner that are non-conflicting will also be picked up)
++
++#ifndef JTAG
++#define JTAG 1
++#endif
++
++#elif defined(OBJSFX_ar0700mp_debugobj)
++#ifndef OBJSFX_ar0700mpobj
++#define OBJSFX_ar0700mpobj 1
++#endif
++// Here, in alphabetic order, are the feature tokens that
++// distinguish this suffix from its non-_debug partner:
++// (All other tokens from the non-_debug partner that are non-conflicting will also be picked up)
++
++#ifndef ADSL2_BSWP
++#define ADSL2_BSWP 1
++#endif
++#ifndef AOC
++#define AOC 1
++#endif
++#ifndef BITSWAP
++#define BITSWAP 1
++#endif
++#ifndef DEBUG_ADSL2
++#define DEBUG_ADSL2 0
++#endif
++#ifndef DEBUG_LOG
++#define DEBUG_LOG 0
++#endif
++#ifndef GHS_NON_STD_FIELD
++#define GHS_NON_STD_FIELD 1
++#endif
++#ifndef JTAG
++#define JTAG 1
++#endif
++#endif // end of the series of "#elif defined" for debug targets
++
++
++//
++// Standard new-style suffixes for operational and mfgr'ing diag.
++//
++
++#if defined(OBJSFX_ar0700dbobj)
++#define CHIPSET_AR07 1
++#define PLATFORM_AR0700 1
++#define DSPDP_CHIPSET_ID CHIPSET_ID_AR
++#define DSPDP_CHIPSET_ID2 CHIPSET_ID2_GENERIC
++#define DSPDP_CHIPSET_GEN 7
++#define DSPDP_HARDWARE_REV1 '0'
++#define DSPDP_HARDWARE_REV2 '0'
++#define DSPDP_FEATURE_CODE (STANDARD_BITS_GDMT|SERVICE_BIT_ISDN_ANNEXB)
++#ifndef AOC
++#define AOC 1
++#endif
++// ATM_TC_HW and SWTC are mutually exclusive
++#ifndef ATM_TC_HW
++#define ATM_TC_HW 1
++#endif
++#ifndef SWTC
++#define SWTC 0
++#endif
++#ifndef BITSWAP
++#define BITSWAP 1
++#endif
++#ifndef EXTERNBERT
++#define EXTERNBERT 0
++#endif
++#ifndef GHS_NON_STD_FIELD
++#define GHS_NON_STD_FIELD 1
++#endif
++#ifndef MARGIN_DELTA_RETRAIN
++#define MARGIN_DELTA_RETRAIN 0
++#endif
++#ifndef NLNOISEADJSNR_EC
++#define NLNOISEADJSNR_EC 1
++#endif
++#ifndef OLAYDP
++#define OLAYDP 1
++#endif
++#ifndef SHALF
++#define SHALF 1
++#endif
++
++
++#elif defined(OBJSFX_ar0700db_diagobj)
++#define CHIPSET_AR07 1
++#define PLATFORM_AR0700 1
++#define DSPDP_CHIPSET_ID CHIPSET_ID_AR
++#define DSPDP_CHIPSET_ID2 CHIPSET_ID2_GENERIC
++#define DSPDP_CHIPSET_GEN 7
++#define DSPDP_HARDWARE_REV1 '0'
++#define DSPDP_HARDWARE_REV2 '0'
++#define DSPDP_FEATURE_CODE (STANDARD_BITS_GDMT|SERVICE_BIT_ISDN_ANNEXB)
++#ifndef AOC
++#define AOC 0
++#endif
++// ATM_TC_HW and SWTC are mutually exclusive (or both must be off)
++#ifndef ATM_TC_HW
++#define ATM_TC_HW 0
++#endif
++#ifndef SWTC
++#define SWTC 0
++#endif
++#ifndef BITSWAP
++#define BITSWAP 0
++#endif
++#ifndef CO_PROFILE
++#define CO_PROFILE 0
++#endif
++#ifndef MARGIN_DELTA_RETRAIN
++#define MARGIN_DELTA_RETRAIN 0
++#endif
++#ifndef MFGR_DIAG
++#define MFGR_DIAG 1
++#endif
++#ifndef OAM_EOC
++#define OAM_EOC 0
++#endif
++#ifndef OLAYDP
++#define OLAYDP 0
++#endif
++#ifndef SNR_UPDATE
++#define SNR_UPDATE 0
++#endif
++
++#elif defined(OBJSFX_ar0700mpobj)
++#define CHIPSET_AR07 1
++#define PLATFORM_AR0700 1
++#define DSPDP_CHIPSET_ID CHIPSET_ID_AR
++#define DSPDP_CHIPSET_ID2 CHIPSET_ID2_GENERIC
++#define DSPDP_CHIPSET_GEN 7
++#define DSPDP_HARDWARE_REV1 '0'
++#define DSPDP_HARDWARE_REV2 '0'
++#define DSPDP_FEATURE_CODE (STANDARD_BITS_MULTIMODE|SERVICE_BIT_POTS)
++#ifndef AOC
++#define AOC 1
++#endif
++// ATM_TC_HW and SWTC are mutually exclusive
++#ifndef ADSL2_1BIT_TONE
++#define ADSL2_1BIT_TONE 0
++#endif
++#ifndef ADSL2_BSWP
++#define ADSL2_BSWP 1
++#endif
++#ifndef ATM_TC_HW
++#define ATM_TC_HW 1
++#endif
++#ifndef SWTC
++#define SWTC 0
++#endif
++#ifndef BITSWAP
++#define BITSWAP 1
++#endif
++#ifndef EXTERNBERT
++#define EXTERNBERT 0
++#endif
++#ifndef OLAYDP
++#define OLAYDP 1
++#endif
++#ifndef DMT_BIS
++#define DMT_BIS 1
++#endif
++#ifndef SHALF
++#define SHALF 1
++#endif
++#ifndef MEM_STR
++#define MEM_STR 0
++#endif
++#ifndef DS_LOOP_BACK
++#define DS_LOOP_BACK 0
++#endif
++#ifndef LOOP_BACK_DEBUG
++#define LOOP_BACK_DEBUG 0
++#endif
++#ifndef US_LOOP_BACK
++#define US_LOOP_BACK 0
++#endif
++#ifndef OVHD_PMDTEST_PARA
++#define OVHD_PMDTEST_PARA 0
++#endif
++#ifndef DS_RX_CODEWORD
++#define DS_RX_CODEWORD 1
++#endif
++#ifndef READSL2_ENABLE
++#define READSL2_ENABLE 1
++#endif
++#ifndef GHS_NON_STD_FIELD
++#define GHS_NON_STD_FIELD 1
++#endif
++
++#elif defined(OBJSFX_ar0700mp_diagobj)
++#define CHIPSET_AR07 1
++#define PLATFORM_AR0700 1
++#define DSPDP_CHIPSET_ID CHIPSET_ID_AR
++#define DSPDP_CHIPSET_ID2 CHIPSET_ID2_GENERIC
++#define DSPDP_CHIPSET_GEN 7
++#define DSPDP_HARDWARE_REV1 '0'
++#define DSPDP_HARDWARE_REV2 '0'
++#define DSPDP_FEATURE_CODE (STANDARD_BITS_MULTIMODE|SERVICE_BIT_POTS)
++#ifndef ADSL2_BSWP
++#define ADSL2_BSWP 0
++#endif
++#ifndef AOC
++#define AOC 0
++#endif
++// ATM_TC_HW and SWTC are mutually exclusive (or both must be off)
++#ifndef ATM_TC_HW
++#define ATM_TC_HW 0
++#endif
++#ifndef SWTC
++#define SWTC 0
++#endif
++#ifndef BITSWAP
++#define BITSWAP 0
++#endif
++#ifndef CO_PROFILE
++#define CO_PROFILE 0
++#endif
++#ifndef DMT_BIS
++#define DMT_BIS 0
++#endif
++#ifndef MARGIN_DELTA_RETRAIN
++#define MARGIN_DELTA_RETRAIN 0
++#endif
++#ifndef MFGR_DIAG
++#define MFGR_DIAG 1
++#endif
++#ifndef OAM_EOC
++#define OAM_EOC 0
++#endif
++#ifndef OLAYDP
++#define OLAYDP 0
++#endif
++#ifndef SNR_UPDATE
++#define SNR_UPDATE 0
++#endif
++#ifndef US_CRC_RETRAIN
++#define US_CRC_RETRAIN 0
++#endif
++#ifndef ADSL2_BSWP
++#define ADSL2_BSWP 0
++#endif
++#ifndef DMT_BIS
++#define DMT_BIS 0
++#endif
++#ifndef DS_RX_CODEWORD
++#define DS_RX_CODEWORD 0
++#endif
++
++#else
++#define DSPDP_CHIPSET_ID CHIPSET_ID_UNKN
++#define DSPDP_CHIPSET_ID2 CHIPSET_ID2_GENERIC
++#define DSPDP_CHIPSET_GEN 0
++#define DSPDP_HARDWARE_REV1 '0'
++#define DSPDP_HARDWARE_REV2 '0'
++#define DSPDP_FEATURE_CODE 0
++#endif
++
++// For use in checking the code in drivers -- indented to avoid .h->.ah
++ #define STANDARD_is_T1413(code) (!(((code) & STANDARD_BITS_MASK) ^ STANDARD_BITS_T1413))
++ #define STANDARD_is_GLITE(code) (!(((code) & STANDARD_BITS_MASK) ^ STANDARD_BITS_GLITE))
++ #define STANDARD_is_GHS(code) (((code) & STANDARD_BITS_MASK) & STANDARD_BITS_GHS)
++ #define STANDARD_is_GDMT(code) (!(((code) & STANDARD_BITS_MASK) ^ (STANDARD_BITS_T1413 | STANDARD_BITS_GHS)))
++ #define STANDARD_is_MULTIMODE(code) (!(((code) & STANDARD_BITS_MASK) ^ (STANDARD_BITS_T1413 | STANDARD_BITS_GLITE | STANDARD_BITS_GDMT)))
++ #define SERVICE_is_POTS(code) ((code) & SERVICE_BIT_POTS)
++ #define SERVICE_is_ISDN_ANNEXB(code) ((code) & SERVICE_BIT_ISDN_ANNEXB)
++ #define SERVICE_is_ISDN_ANNEXC(code) ((code) & SERVICE_BIT_ISDN_ANNEXC)
++ #define SERVICE_is_ISDN_PROP(code) ((code) & SERVICE_BIT_ISDN_PROP)
++
++#define STANDARD_T1413 (!((DSPDP_FEATURE_CODE & STANDARD_BITS_MASK) ^ STANDARD_BITS_T1413))
++#define STANDARD_GLITE (!((DSPDP_FEATURE_CODE & STANDARD_BITS_MASK) ^ STANDARD_BITS_GLITE))
++#define STANDARD_GHS ((DSPDP_FEATURE_CODE & STANDARD_BITS_MASK) & STANDARD_BITS_GHS)
++#define STANDARD_GDMT (!((DSPDP_FEATURE_CODE & STANDARD_BITS_MASK) ^ (STANDARD_BITS_T1413 | STANDARD_BITS_GHS)))
++#define STANDARD_MULTIMODE (!((DSPDP_FEATURE_CODE & STANDARD_BITS_MASK) ^ (STANDARD_BITS_T1413 | STANDARD_BITS_GLITE | STANDARD_BITS_GDMT)))
++
++#define SERVICE_POTS (DSPDP_FEATURE_CODE & SERVICE_BIT_POTS)
++#define SERVICE_ISDN_ANNEXB (DSPDP_FEATURE_CODE & SERVICE_BIT_ISDN_ANNEXB)
++#define SERVICE_ISDN_ANNEXC (DSPDP_FEATURE_CODE & SERVICE_BIT_ISDN_ANNEXC)
++#define SERVICE_ISDN_PROP (DSPDP_FEATURE_CODE & SERVICE_BIT_ISDN_PROP)
++#define SERVICE_ISDN (SERVICE_ISDN_ANNEXB | SERVICE_ISDN_ANNEXC | SERVICE_ISDN_PROP)
++
++
++//
++// Backwards compatibility with old tokens
++//
++
++#if (SERVICE_POTS)
++#ifndef ISDN
++#define ISDN 0
++#endif
++#endif
++
++#if (SERVICE_ISDN_ANNEXB | SERVICE_ISDN_PROP)
++#ifndef ISDN
++#define ISDN 1
++#endif
++#endif
++
++
++//
++//* ===========================================================================
++// More Default settings
++//* ===========================================================================
++//
++
++//
++// BEGIN Could automatically generate showdefs code
++//
++#ifndef AOC
++#define AOC 1
++#endif
++#ifndef ARTT
++#define ARTT 0
++#endif
++#ifndef ATMBERT
++#define ATMBERT 0
++#endif
++// ATM_TC_HW and SWTC are mutually exclusive
++#ifndef ATM_TC_HW
++#define ATM_TC_HW 1
++#endif
++#if ATM_TC_HW
++#ifndef ATMBERT_HW
++#define ATMBERT_HW 1
++#endif
++#ifndef SWTC
++#define SWTC 0
++#endif
++#else // else case for #if ATM_TC_HW
++#ifndef ATMBERT_HW
++#define ATMBERT_HW 0
++#endif
++#ifndef SWTC
++#define SWTC 1
++#endif
++#endif // end of #if ATM_TC_HW
++#ifndef ATM_TC_PATH1_ON
++#define ATM_TC_PATH1_ON 0
++#endif
++#ifndef BITSWAP
++#define BITSWAP 1
++#endif
++#ifndef COMB_LINEDIAG_ENABLE
++#define COMB_LINEDIAG_ENABLE 0
++#endif
++#ifndef CODEC_EMU
++#define CODEC_EMU 0
++#endif
++#ifndef CO_PROFILE
++#define CO_PROFILE 1
++#endif
++#ifndef DDC
++#define DDC 0
++#endif
++#ifndef DEBUG_ADSL2
++#define DEBUG_ADSL2 0
++#endif
++#ifndef DEBUG_DUMP
++#define DEBUG_DUMP 0
++#endif
++#ifndef DEBUG_LOG
++#define DEBUG_LOG 0
++#endif
++#ifndef DEV_DEBUG
++#define DEV_DEBUG 0
++#endif
++#ifndef DS_LOOP_BACK
++#define DS_LOOP_BACK 0
++#endif
++#ifndef DS_RX_CODEWORD
++#define DS_RX_CODEWORD 1
++#endif
++#ifndef LOOP_BACK_DEBUG
++#define LOOP_BACK_DEBUG 0
++#endif
++#ifndef US_LOOP_BACK
++#define US_LOOP_BACK 0
++#endif
++#ifndef DPLL_MODE
++#define DPLL_MODE 0
++#endif
++#ifndef DSPBIOSII
++#define DSPBIOSII 0
++#endif
++#ifndef DMT_BIS
++#define DMT_BIS 1
++#endif
++#ifndef ADSL2_1BIT_TONE
++#define ADSL2_1BIT_TONE 0
++#endif
++#ifndef ADSL2_BSWP
++#define ADSL2_BSWP 1
++#endif
++#ifndef MEM_STR
++#define MEM_STR 0
++#endif
++#ifndef DS_PWR_CUTBACK
++#define DS_PWR_CUTBACK 0
++#endif
++#ifndef DUAL_TEQ
++#define DUAL_TEQ 1
++#endif
++#ifndef EXTERNBERT
++#define EXTERNBERT 0
++#endif
++#ifndef FPGA
++#define FPGA 0
++#endif
++#ifndef INBAND
++#define INBAND 0
++#endif
++#ifndef ISDN
++#define ISDN 0
++#endif
++#ifndef ISDN_DEBUG
++#define ISDN_DEBUG 0
++#endif
++#ifndef LINE_DIAG
++#define LINE_DIAG 1
++#endif
++#ifndef LOOP_BACK_DEBUG
++#define LOOP_BACK_DEBUG 0
++#endif
++#ifndef MANUFACTURING_TESTS
++#define MANUFACTURING_TESTS 0
++#endif
++#ifndef MARGIN_DELTA_RETRAIN
++#define MARGIN_DELTA_RETRAIN 1
++#endif
++#ifndef MEM_STR
++#define MEM_STR 0
++#endif
++#ifndef MFGR_DIAG
++#define MFGR_DIAG 0
++#endif
++#ifndef NLNOISEADJSNR
++#define NLNOISEADJSNR 0
++#endif
++#ifndef NLNOISEADJSNR_EC
++#define NLNOISEADJSNR_EC 0
++#endif
++#ifndef NTR_MODE
++#define NTR_MODE 0
++#endif
++#ifndef OAM_EOC
++#define OAM_EOC 1
++#endif
++#ifndef OLAYDP
++#define OLAYDP 0
++#endif
++#ifndef OLAYDP_EMIF
++#define OLAYDP_EMIF 0
++#endif
++#ifndef OLAYDP_2STEP
++#define OLAYDP_2STEP 0
++#endif
++#ifndef OLAYDP_PCI
++#define OLAYDP_PCI 0
++#endif
++#ifndef OUTBAND
++#define OUTBAND 0
++#endif
++#ifndef OVHD_PMDTEST_PARA
++#define OVHD_PMDTEST_PARA 0
++#endif
++#ifndef PERTONE_EQ
++#define PERTONE_EQ 0
++#endif
++#ifndef PHY_EC_ENABLE
++#define PHY_EC_ENABLE 1
++#endif
++#ifndef PHY_HYB_ENABLE
++#define PHY_HYB_ENABLE 1
++#endif
++#ifndef PHY_NDIAG_ENABLE
++#define PHY_NDIAG_ENABLE 0
++#endif
++#ifndef PHY_PATH_ENABLE
++#define PHY_PATH_ENABLE 1
++#endif
++#ifndef PHY_TDW_ENABLE
++#define PHY_TDW_ENABLE 0
++#endif
++#ifndef TC_ATM_PCIMASTER
++#define TC_ATM_PCIMASTER 0
++#endif
++#ifndef SEPARATE_TX_RX_BUFFERS
++#define SEPARATE_TX_RX_BUFFERS 0
++#endif
++#ifndef SHALF
++#define SHALF 0
++#endif
++#ifndef SPECTRAL_SHAPING
++#define SPECTRAL_SHAPING 1
++#endif
++#ifndef SNR_UPDATE
++#define SNR_UPDATE 1
++#endif
++#ifndef TC_DEBUG
++#define TC_DEBUG 0
++#endif
++#ifndef TC_LOOPBACK
++#define TC_LOOPBACK 0
++#endif
++#ifndef TESTMODE
++#define TESTMODE 0
++#endif
++#ifndef TRELLIS
++#define TRELLIS 1
++#endif
++#ifndef TXDF2B_PROFILING
++#if (SERVICE_POTS & (!MFGR_DIAG) & (CO_PROFILE))
++#define TXDF2B_PROFILING 1
++#else
++#define TXDF2B_PROFILING 0
++#endif
++#endif
++#ifndef US_CRC_RETRAIN
++#define US_CRC_RETRAIN 1
++#endif
++#ifndef US_LOOP_BACK
++#define US_LOOP_BACK 0
++#endif
++#ifndef USB
++#define USB 0
++#endif
++#ifndef READSL2_ENABLE
++#define READSL2_ENABLE 1
++#endif
++
++// Interop tokens
++#ifndef GHS_NON_STD_FIELD
++#define GHS_NON_STD_FIELD 0
++#endif
++#ifndef LUCENT_ANYMEDIA_ENIATT_INTEROP
++#define LUCENT_ANYMEDIA_ENIATT_INTEROP 0
++#endif
++
++
++//
++// END Could automatically generate showdefs code
++//
++#if DSPDP_FEATURE_CODE
++#else
++// Unrecognized_suffix____check_spelling
++#endif
++//
++// LNK_CMD is set when running CPP to generate lnk_cpe.cmd file
++// -- the linker is not happy when it sees C code show up in the
++// result!
++//
++#ifndef LNK_CMD
++extern int compile_happy; // Keep the compiler from complaining about an empty file
++#endif
++
++#endif
++
+diff -urN linux.old/drivers/atm/sangam_atm/env_def_typedefs.h linux.dev/drivers/atm/sangam_atm/env_def_typedefs.h
+--- linux.old/drivers/atm/sangam_atm/env_def_typedefs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/env_def_typedefs.h 2005-08-23 04:46:50.104842632 +0200
+@@ -0,0 +1,228 @@
++#ifndef __ENV_DEF_TYPEDEFS_H__
++#define __ENV_DEF_TYPEDEFS_H__ 1
++
++/*******************************************************************************
++* FILE PURPOSE: Define data types for C and TMS320C6x C compilers
++********************************************************************************
++*
++* FILE NAME: dpsys_typedefs.h
++*
++* DESCRIPTION:
++* This file contains the main typedefs that we need.
++*
++* HISTORY:
++*
++* 03/11/97 Bob Lee Created
++* 03/13/97 Chishtie
++* 03/14/97 Bob Lee Format change to meet "Engineering Model
++* - System Architucture Specification"
++* Rev AP3. Jan. 29, 1997
++* 07/21/00 Barnett Moved many common typedefs from
++* host i/f header file to here.
++* 03/30/01 Barnett Mod's per driver team feedback.
++* Some tokens cannot be def'ed
++* if _WINDEF_ is def'ed.
++* 04/05/01 Barnett Added DSPDP_ prefix to tokens that originate
++* in the public interface.
++* 06/01/01 J. Bergsagel Modified to add standard typedefs
++* 07/25/01 J. Bergsagel Changed name from typedefs.h to dpsys_typedefs.h
++* 07/30/01 J. Bergsagel Moved typedefs that were conflicting with Windows
++* driver software to the "#ifndef _WINDEF_" section.
++* 08/09/01 S. Yim Moved FALSE/TRUE definitions from ctl_interface_u.h
++* (conflict with BIOS/std.h)
++* 09/03/01 S. Yim Do not include typedef char and float if _STD defined
++* (conflict with BIOS/std.h)
++* 01/21/03 MCB Implemented Ax7 UNIT-MODULE modular software framework.
++* 03/20/03 Mallesh Defined size of basic variables
++* 03/27/03 F. Mujica Added SINT40 and UINT40 definitions.
++*
++* (C) Copyright Texas Instruments Inc. 1997-2001. All rights reserved.
++*******************************************************************************/
++
++// Common type definitions
++
++// Basic constants needed everywhere
++#ifndef STD_
++#define FALSE 0
++#define TRUE 1
++#endif
++
++// Read-Write Data Types
++typedef signed char SINT8; // Signed 8-bit integer (7-bit magnitude)
++typedef unsigned char UINT8; // Unsigned 8-bit integer
++typedef signed short SINT16; // Signed 16-bit integer (15-bit magnitude)
++typedef unsigned short UINT16; // Unsigned 16-bit integer
++typedef signed int SINT32; // Signed 32-bit integer (31-bit magnitude)
++typedef unsigned int UINT32; // Unsigned 32-bit integer
++typedef long signed int SINT40; // Long signed 40-bit integer
++typedef long unsigned int UINT40; // Long unsigned 40-bit integer
++
++// All pointers are 32 bits long
++typedef SINT8 *PSINT8; // Pointer to SINT8
++typedef UINT8 *PUINT8; // Pointer to UINT8
++typedef SINT16 *PSINT16; // Pointer to SINT16
++typedef UINT16 *PUINT16; // Pointer to UINT16
++typedef SINT32 *PSINT32; // Pointer to SINT32
++typedef UINT32 *PUINT32; // Pointer to UINT32
++
++#define SIZEOF_SINT8 1
++#define SIZEOF_UINT8 1
++#define SIZEOF_SINT16 2
++#define SIZEOF_UINT16 2
++#define SIZEOF_SINT32 4
++#define SIZEOF_UINT32 4
++#define SIZEOF_SINT40 8
++#define SIZEOF_UINT40 8
++
++// Size of Read-Write Data Types - in bytes
++#define SIZEOF_char 1
++#define SIZEOF_Int8 1
++#define SIZEOF_UChar 1
++#define SIZEOF_UInt8 1
++#define SIZEOF_Float 4
++#define SIZEOF_Double 8
++#define SIZEOF_byte 1
++
++// Read-Only Data Types - should be only used for ROM code
++typedef const char CharRom; // 8 bit signed character
++typedef const signed char Int8Rom; // 8 bit signed integer
++typedef const unsigned char UCharRom; // 8 bit unsigned character
++typedef const unsigned char UInt8Rom; // 8 bit unsigned integer
++typedef const float FloatRom; // IEEE 32-bit
++typedef const double DoubleRom; // IEEE 64-bit
++
++#ifndef _WINDEF_
++
++// Read-Write Data Types
++typedef signed char Int8; // 8 bit signed integer
++typedef unsigned char UChar; // 8 bit unsigned character
++typedef unsigned char UInt8; // 8 bit unsigned integer
++#ifndef STD_
++typedef char Char; // 8 bit signed character
++typedef float Float; // IEEE 32-bit
++#endif
++typedef double Double; // IEEE 64-bit
++typedef signed char byte; // 8 bit signed integer
++
++
++// These typedefs collide with those in Win2k DDK inc\WINDEF.H
++
++// common type definition
++typedef unsigned char BYTE; // 8-bit
++typedef signed short SHORT; // 16-bit signed
++typedef unsigned short WORD; // 16-bit
++typedef unsigned int DWORD; // 32-bit, TI DSP has 40 bit longs
++
++// All pointers are 32 bits long
++typedef BYTE *PBYTE; // pointer to 8 bit data
++typedef unsigned char *PCHAR; // pointer to 8 bit data
++typedef SHORT *PSHORT; // pointer to 16 bit data
++typedef WORD *PWORD; // pointer to 16 bit data
++typedef DWORD *PDWORD; // pointer to 32 bit data
++
++#endif // #ifndef _WINDEF_
++
++
++#define SIZEOF_BYTE 1
++#define SIZEOF_SHORT 2
++#define SIZEOF_WORD 2
++#define SIZEOF_DWORD 4
++#define SIZEOF_PCHAR 4
++#define SIZEOF_PWORD 4
++#define SIZEOF_PDWORD 4
++
++// Size of Read-Only Data Types - in bytes
++#define SIZEOF_CharRom 1
++#define SIZEOF_Int8Rom 1
++#define SIZEOF_UCharRom 1
++#define SIZEOF_UInt8Rom 1
++#define SIZEOF_FloatRom 4
++#define SIZEOF_DoubleRom 8
++
++#define SIZEOF_complex_byte (2*SIZEOF_byte)
++#define SIZEOF_PTR_complex_byte 4
++typedef struct {
++ byte re;
++ byte im;
++} complex_byte, *PTR_complex_byte;
++
++#define SIZEOF_complex_short 4
++#define SIZEOF_PTR_complex_short 4
++typedef struct {
++ short re;
++ short im;
++} complex_short, *PTR_complex_short;
++
++#define SIZEOF_complex_int 8
++#define SIZEOF_PTR_complex_int 4
++typedef struct {
++ int re;
++ int im;
++} complex_int, *PTR_complex_int;
++
++typedef struct {
++ int high;
++ unsigned int low;
++} int64;
++
++typedef struct {
++ int64 real;
++ int64 imag;
++} complex_int64;
++
++#define SIZEOF_PVOID 4
++typedef void *PVOID; // pointer to void
++
++//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
++
++#if defined(_TMS320C6X) // TMS320C6xx type definitions
++
++// Read-Write Data Types
++typedef short Int16; // 16 bit signed integer
++typedef unsigned short UInt16; // 16 bit unsigned integer
++typedef int Int32; // 32 bit signed integer
++typedef unsigned int UInt32; // 32 bit unsigned signed integer
++typedef long Long40; // 40 bit signed integer
++typedef unsigned long ULong40; // 40 bit unsigned signed integer
++
++// Size of Read-Write Data Types - in bytes
++#define SIZEOF_Int16 2
++#define SIZEOF_UInt16 2
++#define SIZEOF_Int32 4
++#define SIZEOF_UInt32 4
++#define SIZEOF_Long40 5
++#define SIZEOF_ULong40 5
++
++// Read-Only Data Types - should be only used for ROM code
++typedef const short Int16Rom; // 16 bit signed integer
++typedef const unsigned short UInt16Rom; // 16 bit unsigned integer
++typedef const int Int32Rom; // 32 bit signed integer
++typedef const unsigned int UInt32Rom; // 32 bit unsigned signed integer
++typedef const long Long40Rom; // 40 bit signed integer
++typedef const unsigned long ULong40Rom; // 40 bit unsigned signed integer
++
++// Size of Read-Only Data Types - in bytes
++#define SIZEOF_Int16Rom 2
++#define SIZEOF_UInt16Rom 2
++#define SIZEOF_Int32Rom 4
++#define SIZEOF_UInt32Rom 4
++#define SIZEOF_Long40Rom 5
++#define SIZEOF_ULong40Rom 5
++
++#else // 32 bits PC Host type definitions
++
++// Read-Write Data Types
++typedef short Int16; // 16 bit signed integer
++typedef unsigned short UInt16; // 16 bit unsigned integer
++typedef int Int32; // 32 bit signed integer
++typedef unsigned int UInt32; // 32 bit unsigned integer
++
++// Read-Only Data Types - should be only used for ROM code
++typedef const short Int16Rom; // 16 bit signed integer
++typedef const unsigned short UInt16Rom; // 16 bit unsigned integer
++typedef const int Int32Rom; // 32 bit signed integer
++typedef const unsigned int UInt32Rom; // 32 bit unsigned integer
++
++#endif
++
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/Makefile linux.dev/drivers/atm/sangam_atm/Makefile
+--- linux.old/drivers/atm/sangam_atm/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/Makefile 2005-08-23 04:46:50.104842632 +0200
+@@ -0,0 +1,35 @@
++# File: drivers/net/avalanche_cpmac/Makefile
++#
++# Makefile for the Linux network (CPMAC) device drivers.
++#
++
++
++O_TARGET := tiatm.o
++obj-$(CONFIG_MIPS_SANGAM_ATM) += tiatm.o
++list-multi := tiatm.o
++
++tiatm-objs := tn7atm.o tn7dsl.o tn7sar.o dsl_hal_api.o dsl_hal_support.o cpsar.o aal5sar.o
++
++EXTRA_CFLAGS += -DEL -I$(TOPDIR)/drivers/atm/sangam_atm -DPOST_SILICON -DCOMMON_NSP -DCONFIG_LED_MODULE -DDEREGISTER_LED -DNO_ACT
++
++ifeq ($(ANNEX),B)
++EXTRA_CFLAGS += -DANNEX_B -DB
++else
++ifeq ($(ANNEX),C)
++EXTRA_CFLAGS += -DANNEX_C -DC
++else
++EXTRA_CFLAGS += -DANNEX_A -DP
++endif
++endif
++
++
++include $(TOPDIR)/Rules.make
++
++tiatm.o: $(tiatm-objs)
++ $(LD) -r -o $@ $(tiatm-objs)
++
++#avalanche_cpmac.o: $(avalanche_cpmac-objs)
++# $(LD) -r -o $@ $(avalanche_cpmac-objs)
++
++clean:
++ rm -f core *.o *.a *.s
+diff -urN linux.old/drivers/atm/sangam_atm/queue.h linux.dev/drivers/atm/sangam_atm/queue.h
+--- linux.old/drivers/atm/sangam_atm/queue.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/queue.h 2005-08-23 04:46:50.104842632 +0200
+@@ -0,0 +1,167 @@
++
++#if !defined( __QUEUE_H__ )
++#define __QUEUE_H__
++
++typedef spinlock_t OS_SPIN_LOCK;
++#define osFreeSpinLock(pLock) while(0)
++void osAcquireSpinLock(OS_SPIN_LOCK *pLock);
++void osReleaseSpinLock(OS_SPIN_LOCK *pLock);
++void osAllocateSpinLock(OS_SPIN_LOCK *pLock);
++
++//#define osAcquireSpinLock(pLock) spin_lock(pLock)
++//#define osReleaseSpinLock(pLock) spin_unlock(pLock)
++//#define osAllocateSpinLock(pLock) spin_lock_init(pLock)
++
++
++typedef struct _TI_LIST_ENTRY {
++ struct _TI_LIST_ENTRY *Flink;
++ struct _TI_LIST_ENTRY *Blink;
++} TI_LIST_ENTRY, *PTI_LIST_ENTRY, TQE, *PTQE;
++
++typedef struct _TIATM_LIST_ENTRY
++{
++ TI_LIST_ENTRY Link;
++} TIATM_LIST_ENTRY, *PTIATM_LIST_ENTRY;
++
++//-------------------------------------------------------------------------
++// QueueInitList -- Macro which will initialize a queue to NULL.
++//-------------------------------------------------------------------------
++#define QueueInitList(_L) (_L)->Link.Flink = (_L)->Link.Blink = (PTI_LIST_ENTRY)0;
++
++//-------------------------------------------------------------------------
++// QueueEmpty -- Macro which checks to see if a queue is empty.
++//-------------------------------------------------------------------------
++#define QueueEmpty(_L) (QueueGetHead((_L)) == (PTIATM_LIST_ENTRY)0)
++
++//-------------------------------------------------------------------------
++// QueueGetHead -- Macro which returns the head of the queue, but does not
++// remove the head from the queue.
++//-------------------------------------------------------------------------
++#define QueueGetHead(_L) ((PTIATM_LIST_ENTRY)((_L)->Link.Flink))
++
++#define QueueGetNext(Elem) ((PTIATM_LIST_ENTRY)((Elem)->Link.Flink))
++
++//-------------------------------------------------------------------------
++// QueuePushHead -- Macro which puts an element at the head of the queue.
++//-------------------------------------------------------------------------
++#define QueuePushHead(_L,_E) \
++ if (!((_E)->Link.Flink = (_L)->Link.Flink)) \
++ { \
++ (_L)->Link.Blink = (PTI_LIST_ENTRY)(_E); \
++ } \
++(_L)->Link.Flink = (PTI_LIST_ENTRY)(_E);
++
++//-------------------------------------------------------------------------
++// QueueRemoveHead -- Macro which removes the head of the head of queue.
++//-------------------------------------------------------------------------
++#define QueueRemoveHead(_L) \
++{ \
++ PTIATM_LIST_ENTRY ListElem; \
++ if (ListElem = (PTIATM_LIST_ENTRY)(_L)->Link.Flink) \
++ { \
++ if(!((_L)->Link.Flink = ListElem->Link.Flink)) \
++ (_L)->Link.Blink = (PTI_LIST_ENTRY) 0; \
++ } \
++}
++
++//-------------------------------------------------------------------------
++// QueuePutTail -- Macro which puts an element at the tail (end) of the queue.
++//-------------------------------------------------------------------------
++#define QueuePutTail(_L,_E) \
++{ \
++ if ((_L)->Link.Blink) \
++ { \
++ ((PTIATM_LIST_ENTRY)(_L)->Link.Blink)->Link.Flink = (PTI_LIST_ENTRY)(_E); \
++ (_L)->Link.Blink = (PTI_LIST_ENTRY)(_E); \
++ } \
++ else \
++ { \
++ (_L)->Link.Flink = \
++ (_L)->Link.Blink = (PTI_LIST_ENTRY)(_E); \
++ } \
++ (_E)->Link.Flink = (PTI_LIST_ENTRY)0; \
++}
++
++//-------------------------------------------------------------------------
++// QueuePutTailWithLock -- Macro which puts an element at the tail (end) of
++// the queue, using spin lock.
++//-------------------------------------------------------------------------
++#define QueuePutTailWithLock(_L,_E, pLock) \
++{ \
++ osAcquireSpinLock(pLock); \
++ if ((_L)->Link.Blink) \
++ { \
++ ((PTIATM_LIST_ENTRY)(_L)->Link.Blink)->Link.Flink = (PTI_LIST_ENTRY)(_E); \
++ (_L)->Link.Blink = (PTI_LIST_ENTRY)(_E); \
++ } \
++ else \
++ { \
++ (_L)->Link.Flink = \
++ (_L)->Link.Blink = (PTI_LIST_ENTRY)(_E); \
++ } \
++ (_E)->Link.Flink = (PTI_LIST_ENTRY)0; \
++ osReleaseSpinLock(pLock); \
++}
++
++//-------------------------------------------------------------------------
++// QueueGetTail -- Macro which returns the tail of the queue, but does not
++// remove the tail from the queue.
++//-------------------------------------------------------------------------
++#define QueueGetTail(_L) ((PTIATM_LIST_ENTRY)((_L)->Link.Blink))
++
++//-------------------------------------------------------------------------
++// QueuePopHead -- Macro which will pop the head off of a queue (list), and
++// return it (this differs only from queueremovehead only in
++// the 1st line)
++//-------------------------------------------------------------------------
++#define QueuePopHead(_L) \
++(PTIATM_LIST_ENTRY) (_L)->Link.Flink; QueueRemoveHead(_L);
++
++#define QueueRemoveTail(_L) \
++{ \
++ PTIATM_LIST_ENTRY ListElem; \
++ ListElem = (PTIATM_LIST_ENTRY)(_L)->Link.Flink; \
++ if(ListElem == (PTIATM_LIST_ENTRY)(_L)->Link.Blink) \
++ { \
++ (_L)->Link.Flink = (_L)->Link.Blink = (PTI_LIST_ENTRY) 0; \
++ } \
++ else \
++ { \
++ while(ListElem->Link.Flink != (PTI_LIST_ENTRY)(_L)->Link.Blink) \
++ { \
++ ListElem = (PTIATM_LIST_ENTRY)ListElem->Link.Flink; \
++ } \
++ (_L)->Link.Blink = (PTI_LIST_ENTRY) ListElem; \
++ ListElem->Link.Flink = (PTI_LIST_ENTRY)0; \
++ } \
++}
++
++#define QueueRemoveItem(_L, Elem) \
++{ \
++ PTIATM_LIST_ENTRY ListElem; \
++ ListElem = (PTIATM_LIST_ENTRY)(_L)->Link.Flink; \
++ if(ListElem == Elem) \
++ { \
++ QueueRemoveHead(_L); \
++ } \
++ else \
++ { \
++ while(ListElem) \
++ { \
++ if(Elem == (PTIATM_LIST_ENTRY)ListElem->Link.Flink) \
++ { \
++ ListElem->Link.Flink = ((PTIATM_LIST_ENTRY)Elem)->Link.Flink; \
++ if(Elem == (PTIATM_LIST_ENTRY)(_L)->Link.Blink) \
++ (_L)->Link.Blink = (PTI_LIST_ENTRY) 0; \
++ break; \
++ } \
++ ListElem = (PTIATM_LIST_ENTRY)ListElem->Link.Flink; \
++ }\
++ } \
++ ((PTIATM_LIST_ENTRY)Elem)->Link.Flink = (PTI_LIST_ENTRY) 0; \
++}
++
++#define QueuePopTail(_L) \
++((PTIATM_LIST_ENTRY)((_L)->Link.Blink)); QueueRemoveTail(_L);
++
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/release.txt linux.dev/drivers/atm/sangam_atm/release.txt
+--- linux.old/drivers/atm/sangam_atm/release.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/release.txt 2005-08-23 04:46:50.104842632 +0200
+@@ -0,0 +1,118 @@
++This is release notes for AR7 Linux ATM driver.
++
++version 04.02.04.00
++-------------------
++
++1. Corrected the conditional logic from logical AND to logical OR in the case
++ of check for DSL line down condition. This is to fix PPPoA crashing
++ problem when DSL line is unplugged.
++
++version 04.02.03.00
++-------------------
++1. Changed overlay page to static allocation.
++2. Added flag to stop TX during channel closing.
++3. Changed DMA memory allocation back to "GFP_ATOMIC" flag.
++
++version 04.02.02.00
++-------------------
++1. Changed DMA memory allocation from "GFP_ATOMIC" to "GFP_KERNEL" flag.
++2. Added "DoMask" setting for VBR channel setup.
++
++version 04.02.01.01
++-------------------
++1. Modified priority check scheme per SPTC request.
++
++Version 04.02.01.00
++-------------------
++1. Add check to skb->priority to place packets to either normal or priority queue.
++2. Add spin lock to increment and decrement of queued buffer number.
++
++Version 04.02.00.00
++-------------------
++Features:
++1. Add MBS and CDVT QoS support for ATM driver.
++2. Add "stop/start queue" for ToS application.
++3. Add Showtime margin retrain based on EOC message.
++4. Add EOC vendor ID customalization logic for Annex B.
++5. Supports D3 datapump.
++
++Version 04.01.00.00
++-------------------
++Re-release of 04.00.07.00 for D1.1 datapump.
++
++Version 04.00.07.00
++-------------------
++Features:
++1. Add marging retrain capability by setting following Adam2 Env.
++ setenv enable_margin_retrain 1
++ setenv margin_threshold xx, xx is in half db, i.e., 10 means 5db.
++
++Bugfixs:
++1. New PDSP firmware that fix the F5 OAM cell loopback probelm in Cisco DSLAM.
++
++Version 04.00.06.00
++-------------------
++1. ATM interrupt pacing is defauted to 2 interrupts/s.
++2. Rx Service MAX changed ftom 16 to 8.
++
++Version 04.00.05.00
++-------------------
++Features:
++1. Add Adam2 env to disable the TurboDSL by entering "setenv TurboDSL 0".
++2. Add ability to set interrupt pacing for ATM driver.
++
++Bugfixs:
++1. Fixed the RFC2684 and CLIP problems for Cisco router.
++2. Fixed LED blinking problem when DSL cable is unplugged.
++3. Fixed problem that "selected mode" is not updated.
++
++Version 04.00.04.00
++-------------------
++Features:
++1. Added feature so OAM F5 ping will not require a corresponding PVC channel to
++ be setup.
++2. Added timeout value for F5 OAM ping. The new command are "exxxpyyycdzzzt" for
++ end-to-end and "sxxxpyyycdzzzt" for segment. "zzz" is timeout value in milli-second.
++3. Added proc entry "avsar_pvc_table" to record received VPIs and VCIs. The format is
++ vpi,vci
++ seperated by new line. To search for PVCs, an application can do the following.
++ i) Send a (or several) F5 OAM cell on a VPI/VPI pairs with command
++ echo exxxpyyycd2t > /proc/sys/dev/dslmod
++ ii) Wait >2ms or poll proc entry /proc/avalanche/avsar_oam_ping until the result
++ indicates a failure. (It will be failed all the time with 2ms timeout.)
++ iii) Repeat above two steps for new VPI/VCI pairs.
++ iv) Check proc entry /proc/avalanche/avsar_pvc_table any time for PVCs that responded.
++
++Version 04.00.03.00
++-------------------
++Bug Fixs:
++1. Fixed bug that caused crash when phone cable is unplugged.
++2. Fixed LED operation for "flexible LEDs".
++
++Features:
++1. Added the proc entry "avsar_oam_ping" to signal oam ping result.
++ 0 - failed; 1 - success; 2 - in progress.
++2. Added oam ping timeout env variable. The timeout can be specified by
++ adding Adam2 env "oam_lb_timeout". The value is in millisecond.
++
++Version 04.00.02.00
++-------------------
++1. The driver uses hardware queue for Turbo DSL.
++2. Added new modem statistics listed below:
++ US and DS TX powers, atuc Vendor ID and revision, training mode selected,
++ Hybrid Selected, and etc.
++
++Version 04.00.01.00
++-------------------
++
++1. This driver release contains all the features that exists in AR5 Linux ATM
++ 3.1 driver.
++
++2. F4 OAM generation is added.
++
++3. Software queuing is used for TURBO DSL.
++
++4. Porting guide "is created. Please look into that document for detailed
++ information.
++
++
+diff -urN linux.old/drivers/atm/sangam_atm/syssw_version.h linux.dev/drivers/atm/sangam_atm/syssw_version.h
+--- linux.old/drivers/atm/sangam_atm/syssw_version.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/syssw_version.h 2005-08-23 04:46:50.105842480 +0200
+@@ -0,0 +1,94 @@
++#ifndef __SYSSW_VERSION_H__
++#define __SYSSW_VERSION_H__ 1
++
++/*******************************************************************************
++* FILE PURPOSE: DSL Driver API functions for Sangam
++*
++********************************************************************************
++* FILE NAME: dsl_hal_basicapi.c
++*
++* DESCRIPTION:
++* Contains basic DSL HAL APIs for Sangam
++*
++* (C) Copyright 2003-04, Texas Instruments, Inc.
++* History
++* Date Version Notes
++* 14May03 0.00.00 RamP Original Version Created
++* 14May03 0.00.01 RamP Initial Rev numbers inserted
++* 14May03 0.00.02 RamP Bumped version numbers for Dsl Hal
++* & dhalapp for alpha plus
++* 19May03 0.00.03 MCB Bumped dslhal version number
++* because of dependant changes
++* wrt. linux-nsp atm drivers.
++* 22May03 0.00.04 RamP Bumped dslhal & dhalapp buildnum
++* for inner/outer pair & DGASP code
++* 06Jun03 0.00.05 RamP Bumped up buildnum for LED, STM,
++* interrupt processing, statistics
++* and other pre-beta features
++* 09Jun03 0.00.06 JEB Fixed error in DHALAPP bugfix/buildnum
++* 09Jun03 0.00.07 RamP Bumped up buildnum for incremental
++* changes to apis, statistics, memory
++* fixes, parameter configurations
++* 11Jun03 0.00.08 RamP Bumped up buildnum for Co profile
++* free memory fix
++* 12Jun03 0.00.09 JEB Bumped version numbers for AR7 1.00 Beta
++* 02Jul03 0.00.10 ZT Bumped HAL version for overlay page
++* 18Jul03 0.00.11 RamP Bumped HAL version for analog diags
++* 22Jul03 0.00.12 JEB Bumped DHALAPP buildnum for analog diags
++* 31Jul03 0.00.13 RamP Bumped HAL version for engr. drop
++* 04Aug03 0.00.14 JEB Bumped HAL version buildnum for CHECKPOINT65 changes
++* Bumped LINUX version buildnum for CHECKPOINT65 changes
++* 06Aug03 0.00.15 MCB Bumped all version numbers in prep for AR7 1.0 R2 release for POTS.
++* 13Aug03 0.00.16 MCB Set rev id's for D3/R1.1 (ADSL2).
++* 21Aug03 0.00.17 JEB Bumped up build numbers for merge of code additions from D1
++* 26Sep03 0.00.18 JEB Set rev id's for another D3/R1 (ADSL2).
++* 14Oct03 0.00.19 JEB Bumped Linux minor number and reset bugfix number for release.
++* Bumped build numbers on DSLHAL and DHALAPP for this checkpoint.
++* 14Oct03 0.00.20 JEB Bumped build numbers on DSLHAL and DHALAPP for CHECKPOINT15.
++* 21Oct03 0.00.21 JEB Bumped build number on DSLHAL for CHECKPOINT16.
++* 22Oct03 0.00.22 MCB Bumped all version numbers in support of D3R1 release.
++* 27Oct03 0.00.23 JEB Bumped build numbers on DSLHAL and DHALAPP for CHECKPOINT19.
++* Updated version for DSLAGENT to be 02.01.00.01 for ACT 2.1 R0.
++* 30Oct03 0.00.24 JEB Bumped bugfix number on LINUXATM Version for next release.
++* Bumped build numbers on DSLHAL and DHALAPP
++* 31Oct03 0.00.25 MCB Bumped all version numbers in support of D3R2 release.
++* 14Nov03 0.00.26 JEB Bumped build numbers on DSLHAL and DHALAPP
++* Changed version for DSLAGENT to be 02.00.01.01 for an ACT 2.0 R0
++* 20Nov03 0.00.27 JEB Bumped build number on DSLHAL.
++* Changed version for DSLAGENT to be 02.00.02.00 for the next ACT 2.0 R2
++* 21Nov03 0.00.28 MCB Bumped all version numbers in support of D3R2 release.
++* 21Nov03 0.00.29 JEB Bumped build numbers on DSLHAL and DHALAPP for D3-R0 drop on 11/21.
++* 16Dec03 0.00.30 JEB Bumped build numbers on DSLHAL and DHALAPP for CHECKPOINT31.
++* 21Dec03 0.00.31 MCB Bumped all version numbers in support of D3R2 release.
++* 05Jan04 0.00.32 JEB Bumped build numbers on DSLHAL and Linux ATM for CHECKPOINT 34.
++* 15Jan04 0.00.33 JEB Bumped build numbers on DSLHAL and Linux ATM for CHECKPOINT 36.
++* 26Jan04 0.00.34 JEB Changed Linux ATM version number to be 04.02.03.00.
++* 27Jan04 0.00.35 MCB Bumped all version numbers in support of D3R2 release.
++*******************************************************************************/
++
++/* Dsl Hal API Version Numbers */
++#define DSLHAL_VERSION_MAJOR 03
++#define DSLHAL_VERSION_MINOR 00
++#define DSLHAL_VERSION_BUGFIX 06
++#define DSLHAL_VERSION_BUILDNUM 00
++#define DSLHAL_VERSION_TIMESTAMP 00
++
++/* dhalapp Adam2 Application Version Numbers */
++#define DHALAPP_VERSION_MAJOR 03
++#define DHALAPP_VERSION_MINOR 00
++#define DHALAPP_VERSION_BUGFIX 05
++#define DHALAPP_VERSION_BUILDNUM 00
++
++/* Linux ATM Driver Version Numbers */
++#define LINUXATM_VERSION_MAJOR 04
++#define LINUXATM_VERSION_MINOR 02
++#define LINUXATM_VERSION_BUGFIX 04
++#define LINUXATM_VERSION_BUILDNUM 00
++
++/* DSL Agent Version Numbers */
++#define DSLAGENT_VERSION_MAJOR 02
++#define DSLAGENT_VERSION_MINOR 00
++#define DSLAGENT_VERSION_BUGFIX 02
++#define DSLAGENT_VERSION_BUILDNUM 00
++
++#endif /* pairs with #ifndef __SYSSW_VERSION_H__ */
+diff -urN linux.old/drivers/atm/sangam_atm/tn7api.h linux.dev/drivers/atm/sangam_atm/tn7api.h
+--- linux.old/drivers/atm/sangam_atm/tn7api.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/tn7api.h 2005-08-23 04:46:50.105842480 +0200
+@@ -0,0 +1,54 @@
++/*
++ * Tnetd73xx ATM driver.
++ * by Zhicheng Tang, ztang@ti.com
++ * 2000 (c) Texas Instruments Inc.
++ *
++ *
++*/
++
++#ifndef __SAPI_H
++#define __SAPI_H
++
++/* tn7atm.c */
++void xdump(unsigned char *buff, int len, int debugLev);
++int tn7atm_receive(void *os_dev, int ch, unsigned int packet_size, void *os_receive_info, void *data);
++void *tn7atm_allocate_rx_skb(void *os_dev, void **os_receive_info, unsigned int size);
++void tn7atm_free_rx_skb(void *skb);
++void tn7atm_sarhal_isr_register(void *os_dev, void *hal_isr, int interrupt_num);
++int tn7atm_send_complete(void *osSendInfo);
++int tn7atm_device_connect_status(void *priv, int state);
++int tn7atm_lut_find(short vpi, int vci);
++
++/* tn7dsl.h */
++void tn7dsl_exit(void);
++int tn7dsl_init(void *priv);
++int tn7dsl_proc_stats(char* buf, char **start, off_t offset, int count,int *eof, void *data);
++int tn7dsl_proc_modem(char* buf, char **start, off_t offset, int count,int *eof, void *data);
++int tn7dsl_handle_interrupt(void);
++void dprintf( int uDbgLevel, char * szFmt, ...);
++void tn7dsl_dslmod_sysctl_register(void);
++void tn7dsl_dslmod_sysctl_unregister(void);
++int tn7dsl_get_dslhal_version(char *pVer);
++int tn7dsl_get_dsp_version(char *pVer);
++
++int os_atoi(const char *pStr);
++int os_atoh(const char *pStr);
++unsigned long os_atoul(const char *pStr);
++
++/* tn7sar.c */
++int tn7sar_activate_vc(Tn7AtmPrivate *priv, short vpi, int vci, int pcr, int scr, int mbs, int cdvt, int chan, int qos);
++int tn7sar_init(struct atm_dev *dev, Tn7AtmPrivate *priv);
++int tn7sar_register_interrupt_handle(void *os_dev, void *hal_isr, int *interrupt_num);
++void tn7sar_exit(struct atm_dev *dev, Tn7AtmPrivate *priv);
++int tn7sar_deactivate_vc(Tn7AtmPrivate *priv, int chan);
++int tn7sar_handle_interrupt(struct atm_dev *dev, Tn7AtmPrivate *priv);
++int tn7sar_send_packet(Tn7AtmPrivate *priv, int chan, void *new_skb, void *data,unsigned int len, int priority);
++void tn7sar_get_sar_version(Tn7AtmPrivate *priv, char **pVer);
++int tn7sar_get_near_end_loopback_count(unsigned int *pF4count, unsigned int *pF5count);
++int tn7sar_oam_generation(void *privContext, int chan, int type, int vpi, int vci, int timeout);
++int tn7sar_get_stats(void *priv1);
++int tn7sar_proc_sar_stat(char* buf, char **start, off_t offset, int count,int *eof, void *data);
++void tn7sar_get_sar_firmware_version(unsigned int *pdsp_version_ms, unsigned int *pdsp_version_ls);
++int tn7sar_proc_oam_ping(char* buf, char **start, off_t offset, int count,int *eof, void *data);
++int tn7sar_proc_pvc_table(char* buf, char **start, off_t offset, int count,int *eof, void *data);
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/tn7atm.c linux.dev/drivers/atm/sangam_atm/tn7atm.c
+--- linux.old/drivers/atm/sangam_atm/tn7atm.c 2005-08-28 01:52:26.000000000 -0600
++++ linux.dev/drivers/atm/sangam_atm/tn7atm.c 2005-08-28 02:08:07.000000000 -0600
+@@ -0,0 +1,1233 @@
++/*
++ * tn7.c
++ * Linux atm module implementation.
++ * Zhicheng Tang 01/08/2003
++ * 2003 (c) Texas Instruments Inc.
++ *
++ *
++*/
++
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/atmdev.h>
++#include <linux/delay.h>
++#include <linux/spinlock.h>
++#include <linux/smp_lock.h>
++#include <asm/io.h>
++#include <asm/mips-boards/prom.h>
++#include <linux/proc_fs.h>
++#include <linux/string.h>
++#include <linux/ctype.h>
++#include "tn7atm.h"
++#include "tn7api.h"
++#include "syssw_version.h"
++
++#ifdef CONFIG_LED_MODULE
++#include <asm/ar7/ledapp.h>
++#endif
++#include <asm/ar7/avalanche_intc.h>
++
++#ifdef MODULE
++MODULE_DESCRIPTION ("Tnetd73xx ATM Device Driver");
++MODULE_AUTHOR ("Zhicheng Tang");
++#endif
++
++/* Version Information */
++//static char atm_version[] ="1.0.0.1";
++
++#define TRUE 1
++#define FALSE 0
++
++#define STOP_EMPTY_BUFF 2
++#define START_EMPTY_BUFF 3
++/* externs */
++
++/*end of externs */
++
++#define tn7atm_kfree_skb(x) dev_kfree_skb(x)
++
++/* prototypes */
++int tn7atm_open (struct atm_vcc *vcc, short vpi, int vci);
++
++void tn7atm_close (struct atm_vcc *vcc);
++
++static int tn7atm_ioctl (struct atm_dev *dev, unsigned int cmd, void *arg);
++
++int tn7atm_send (struct atm_vcc *vcc, struct sk_buff *skb);
++
++static int tn7atm_change_qos (struct atm_vcc *vcc, struct atm_qos *qos,int flags);
++
++static int tn7atm_detect(void);
++static int tn7atm_init(struct atm_dev* dev);
++//static int tn7atm_reset(void);
++static int tn7atm_irq_request(struct atm_dev* dev);
++static int tn7atm_proc_version(char* buf, char **start, off_t offset, int count,int *eof, void *data);
++static void tn7atm_exit(void);
++static int tn7atm_proc_channels(char* buf, char **start, off_t offset, int count,int *eof, void *data);
++static int tn7atm_proc_private(char* buf, char **start, off_t offset, int count,int *eof,void *data);
++//static void tn7atm_free_packet(void *vcc1, void *priv, void *skb1);
++static int tn7atm_queue_packet_to_sar(void *vcc1, void *skb1);
++
++#include "turbodsl.c"
++
++/* ATM device operations */
++
++struct atm_dev *mydev;
++
++static const struct atmdev_ops tn7atm_ops = {
++ open: tn7atm_open,
++ close: tn7atm_close,
++ ioctl: tn7atm_ioctl,
++ getsockopt: NULL,
++ setsockopt: NULL,
++ send: tn7atm_send,
++ sg_send: NULL,
++ phy_put: NULL,
++ phy_get: NULL,
++ change_qos: tn7atm_change_qos,
++};
++
++
++int __guDbgLevel = 1;
++
++
++void xdump(unsigned char *buff, int len, int debugLev)
++{
++#ifdef DEBUG_BUILD
++ int i, j;
++ if( __guDbgLevel < debugLev)
++ return;
++
++ j=0;
++ for(i=0;i<len;i++)
++ {
++ printk("%02x ", buff[i]);
++ j++;
++ if(j==8)
++ {
++ j=0;
++ printk("\n");
++ }
++ }
++ printk("\n");
++#endif
++}
++
++
++#if 0 /* by nbd */
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_walk_vccs(struct atm_dev *dev, short *vcc, int *vci)
++ *
++ * Description: retrieve VPI/VCI for connection
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
++static int
++tn7atm_walk_vccs(struct atm_vcc *vcc, short *vpi, int *vci)
++{
++ struct atm_vcc* walk;
++
++ // printk(tn7 "tn7atm_walk_vccs\n");
++ /* find a free VPI */
++ if (*vpi == ATM_VPI_ANY) {
++
++ for (*vpi = 0, walk = vcc->dev->vccs; walk; walk = walk->next) {
++
++ if ((walk->vci == *vci) && (walk->vpi == *vpi)) {
++ (*vpi)++;
++ walk = vcc->dev->vccs;
++ }
++ }
++ }
++
++ /* find a free VCI */
++ if (*vci == ATM_VCI_ANY) {
++
++ for (*vci = ATM_NOT_RSV_VCI, walk = vcc->dev->vccs; walk; walk = walk->next) {
++
++ if ((walk->vpi = *vpi) && (walk->vci == *vci)) {
++ *vci = walk->vci + 1;
++ walk = vcc->dev->vccs;
++ }
++ }
++ }
++
++ return 0;
++}
++#endif
++
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_sar_irq(void)
++ *
++ * Description: tnetd73xx SAR interrupt.
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
++static void
++tn7atm_sar_irq(int irq , void *voiddev , struct pt_regs *regs)
++{
++ struct atm_dev *atmdev;
++ Tn7AtmPrivate *priv;
++
++ dprintf(6, "tn7atm_sar_irq\n");
++ atmdev = (struct atm_dev *) voiddev;
++ priv = (Tn7AtmPrivate *)atmdev->dev_data;
++
++ tn7sar_handle_interrupt(atmdev, priv);
++
++ dprintf(6, "Leaving tn7atm_sar_irq\n");
++}
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_dsl_irq(void)
++ *
++ * Description: tnetd73xx DSL interrupt.
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
++static void
++tn7atm_dsl_irq(int irq , void *voiddev , struct pt_regs *regs)
++{
++ struct atm_dev *atmdev;
++ Tn7AtmPrivate *priv;
++
++ dprintf(4, "tn7atm_dsl_irq\n");
++ atmdev = (struct atm_dev *) voiddev;
++ priv = (Tn7AtmPrivate *)atmdev->dev_data;
++
++ tn7dsl_handle_interrupt();
++
++ dprintf(4, "Leaving tn7atm_dsl_irq\n");
++}
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_Inittxcomp(struct tn7* tn7)
++ *
++ * Description: Initialize Interrupt handler
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
++static int __init
++tn7atm_irq_request (struct atm_dev *dev)
++{
++ Tn7AtmPrivate *priv;
++ char *ptr;
++ int ipace=2;
++
++ dprintf(4, "tn7atm_irq_request()\n");
++ priv = (Tn7AtmPrivate *) dev->dev_data;
++
++ /* Register SAR interrupt */
++ priv->sar_irq = LNXINTNUM(ATM_SAR_INT); /* Interrupt line # */
++ if (request_irq(priv->sar_irq, tn7atm_sar_irq, SA_INTERRUPT, "SAR ", dev))
++ printk ("Could not register tn7atm_sar_irq\n");
++
++ /* interrupt pacing */
++ ptr= prom_getenv("sar_ipacemax");
++ if(ptr)
++ {
++ ipace=os_atoi(ptr);
++ }
++ avalanche_request_pacing(priv->sar_irq, ATM_SAR_INT_PACING_BLOCK_NUM, ipace);
++
++ /* Reigster Receive interrupt A */
++ priv->dsl_irq = LNXINTNUM(ATM_DSL_INT); /* Interrupt line # */
++ if (request_irq(priv->dsl_irq, tn7atm_dsl_irq, SA_INTERRUPT, "DSL ", dev))
++ printk ("Could not register tn7atm_dsl_irq\n");
++
++ return 0;
++}
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_lut_find(struct atm_vcc *vcc)
++ *
++ * Description: find an TX DMA channel
++ * that matches a vpi/vci pair
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
++int
++tn7atm_lut_find(short vpi, int vci)
++{
++ int i;
++ Tn7AtmPrivate *priv;
++
++ priv = (Tn7AtmPrivate *)mydev->dev_data;
++
++ if(vci==0) // find first vpi channel
++ {
++ for(i=0; i< MAX_DMA_CHAN; i++)
++ {
++ if((priv->lut[i].vpi == vpi))
++ return i;
++ }
++ }
++
++ dprintf(4, "vpi=%d, vci=%d\n", vpi, vci);
++ for(i=0; i< MAX_DMA_CHAN; i++)
++ {
++ if((priv->lut[i].vpi == vpi) && (priv->lut[i].vci == vci))
++ return i;
++ }
++
++
++
++ return ATM_NO_DMA_CHAN;
++}
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_lut_clear(struct atm_vcc *vcc,int chan)
++ *
++ * Description: find an TX DMA channel
++ * that matches a vpi/vci pair
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
++static int
++tn7atm_lut_clear(struct atm_vcc *vcc, int chan)
++{
++ Tn7AtmPrivate *priv;
++
++ priv = (Tn7AtmPrivate *)vcc->dev->dev_data;
++
++ memset(&priv->lut[chan], 0, sizeof(priv->lut[chan]));
++
++ return 0;
++}
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_walk_lut(void)
++ *
++ * Description: find an available TX DMA channel
++ * and initialize LUT
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
++static int
++tn7atm_walk_lut(Tn7AtmPrivate *priv)
++{
++ int i;
++
++ for(i=0; i< MAX_DMA_CHAN; i++){
++ if(!priv->lut[i].inuse)
++ {
++ return i; /* return available dma channel number */
++ }
++ }
++ return ATM_NO_DMA_CHAN; /* no tx dma channels available */
++}
++
++static int
++tn7atm_set_lut(Tn7AtmPrivate *priv, struct atm_vcc *vcc, int chan)
++{
++
++ if(!priv->lut[chan].inuse)
++ {
++ priv->lut[chan].vpi = (int)vcc->vpi;
++ priv->lut[chan].vci = vcc->vci;
++ priv->lut[chan].chanid = chan;
++ priv->lut[chan].inuse = 1; /* claim the channel */
++ priv->lut[chan].vcc = (void *)vcc;
++ priv->lut[chan].bClosing = 0;
++ priv->lut[chan].ready = 0;
++ priv->lut[chan].tx_total_bufs = TX_BUFFER_NUM;
++ priv->lut[chan].tx_used_bufs[0] = 0;
++ priv->lut[chan].tx_used_bufs[1] = 0;
++ return 0;
++ }
++ return -1; /* no tx dma channels available */
++}
++
++#if 0
++static void tn7atm_free_packet(void *pVc, void *pDev, void *pPacket)
++ {
++ Tn7AtmPrivate *priv;
++ struct atm_vcc *vcc;
++ struct sk_buff *skb;
++
++ vcc = (struct atm_vcc *)pVc;
++ priv = (Tn7AtmPrivate *)pDev;
++ skb = (struct sk_buff *) pPacket;
++
++ if(vcc->pop)
++ vcc->pop(vcc, skb);
++ else
++ tn7atm_kfree_skb(skb);
++ }
++#endif
++
++static void str2eaddr(char *pMac, char *pStr)
++{
++ char tmp[3];
++ int i;
++
++ for(i=0;i<6;i++)
++ {
++ tmp[0]=pStr[i*3];
++ tmp[1]=pStr[i*3+1];
++ tmp[2]=0;
++ pMac[i]=os_atoh(tmp);
++ }
++}
++
++static int __init
++tn7atm_get_ESI(struct atm_dev *dev)
++{
++ int i;
++ char esi_addr[ESI_LEN]={0x00,0x00,0x11,0x22,0x33,0x44};
++ char *esiaddr_str = NULL;
++
++ esiaddr_str = prom_getenv("macc");
++
++ if (!esiaddr_str) {
++ //printk("macc address not set in adam2 environment space\n");
++ //printk("Using default macc address = 00:01:02:03:04:05\n");
++ esiaddr_str = "00:00:02:03:04:05";
++ }
++ str2eaddr(esi_addr, esiaddr_str);
++
++ for(i=0; i < ESI_LEN; i++)
++ dev->esi[i] = esi_addr[i];
++
++ return 0;
++}
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_open(struct atm_vcc *vcc, short vpi, int vci)
++ *
++ * Description: Device operation: open
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
++//static int
++int tn7atm_open (struct atm_vcc *vcc, short vpi, int vci)
++{
++ Tn7AtmPrivate *priv;
++ int dmachan;
++ int rc;
++ int traffic_type;
++ int pcr = 0x20000;
++ int scr = 0x20000;
++ int mbs = 0x20000;
++ int cdvt = 10000;
++ int err;
++
++ dprintf(1, "tn7atm_open()\n");
++
++ priv = (Tn7AtmPrivate *)vcc->dev->dev_data;
++ if(priv==NULL)
++ {
++ printk("null priv\n");
++ return -1;
++ }
++
++ MOD_INC_USE_COUNT;
++
++#if 0 /* by nbd */
++ /* find a free VPI/VCI */
++ tn7atm_walk_vccs(vcc, &vpi, &vci);
++#else
++ if ((err = atm_find_ci(vcc, &vpi, &vci))) {
++ printk("atm_find_ci err = %d\n", err);
++ return err;
++ }
++
++#endif
++
++ vcc->vpi = vpi;
++ vcc->vci = vci;
++
++ if (vci == ATM_VCI_UNSPEC || vpi == ATM_VCI_UNSPEC)
++ {
++ MOD_DEC_USE_COUNT;
++ return -EBUSY;
++ }
++
++ /* check to see whether PVC is opened or not */
++ if((dmachan = tn7atm_lut_find(vcc->vpi, vcc->vci)) != ATM_NO_DMA_CHAN)
++ {
++ MOD_DEC_USE_COUNT;
++ printk("PVC already opened. dmachan = %d\n", dmachan);
++ return -EBUSY;
++ }
++ /*check for available channel */
++ if((dmachan = tn7atm_walk_lut(priv)) == ATM_NO_DMA_CHAN)
++ {
++ printk("No TX DMA channels available\n");
++ return -EBUSY;
++ }
++
++ set_bit(ATM_VF_ADDR, &vcc->flags); /* claim address */
++
++ vcc->itf = vcc->dev->number; /* interface number */
++
++ switch(vcc->qos.txtp.traffic_class)
++ {
++ case ATM_CBR: /* Constant Bit Rate */
++ traffic_type = 0;
++ pcr = vcc->qos.txtp.pcr;
++ scr = vcc->qos.txtp.pcr;
++ cdvt = vcc->qos.txtp.max_cdv;
++ printk("cdvt=%d\n", cdvt);
++ break;
++ case ATM_UBR: /* Unspecified Bit Rate */
++ traffic_type = 2;
++ break;
++
++ /* Disable ATM_VBR until pppd ppoatm plugin supports it.
++ * NOTE: Support ATM_VBR requires the addition of a scr
++ * field to the atm_trafprm structure which will cause
++ * a change in the SO_ATMQOS ioctl. Make sure that the
++ * revised header file becomes visible to the pppd
++ * pppoatm plugin source, or the SO_ATMQOS ioctl will fail.
++ */
++#if 0
++ case ATM_VBR: /* Variable Bit Rate */
++ traffic_type = 1;
++ pcr = vcc->qos.txtp.pcr;
++ scr = vcc->qos.txtp.scr;
++ if(vcc->qos.txtp.max_pcr >= 0)
++ mbs = vcc->qos.txtp.max_pcr;
++ cdvt = vcc->qos.txtp.max_cdv;
++ printk("cdvt=%d\n", cdvt);
++ printk("mbs=%d\n", mbs);
++ break;
++#endif
++ default:
++ traffic_type = 2;
++ }
++
++ dprintf(4, "vpi=%d, vci=%d, pcr=%d, dmachan=%d, qos=%d\n", vpi,vci,pcr,dmachan,traffic_type);
++ /* Activate SAR channel */
++ rc = tn7sar_activate_vc(priv, vpi, vci, pcr, scr, mbs, cdvt, dmachan, traffic_type);
++ if(rc < 0)
++ {
++
++ MOD_DEC_USE_COUNT;
++ return -EBUSY;
++ }
++
++ /* insure that the the vcc struct points to the correct entry
++ in the lookup table */
++
++ tn7atm_set_lut(priv,vcc, dmachan);
++ vcc->dev_data = (void *)&priv->lut[dmachan];
++ set_bit(ATM_VF_READY, &vcc->flags);
++
++ mdelay(100);
++ priv->lut[dmachan].ready = 1;
++ dprintf (1, "Leave tn7atm_open\n");
++ return 0;
++}
++
++
++//static void
++void tn7atm_close (struct atm_vcc *vcc)
++{
++ Tn7AtmPrivate *priv;
++ int dmachan;
++
++ priv = (Tn7AtmPrivate *)vcc->dev->dev_data;
++ dprintf(4, "closing %d.%d.%d.%d\n", vcc->itf, vcc->vpi, vcc->vci, vcc->qos.aal);
++
++ clear_bit(ATM_VF_READY, &vcc->flags); /* ATM_VF_READY: channel is ready to transfer data */
++
++ dmachan = tn7atm_lut_find(vcc->vpi, vcc->vci);
++ printk("closing channel: %d\n", dmachan);
++ if(dmachan == ATM_NO_DMA_CHAN)
++ {
++ printk("Closing channel not found.\n");
++ return;
++ }
++ priv->lut[dmachan].bClosing = 1;
++ priv->lut[dmachan].ready = 0;
++ if(tn7sar_deactivate_vc(priv,dmachan)) /* tear down channel */
++ {
++ printk("failed to close channel %d.\n", dmachan);
++ }
++
++ clear_bit(ATM_VF_READY, &vcc->flags); /* ATM_VF_READY: channel is ready to transfer data */
++ tn7atm_lut_clear(vcc, dmachan);
++
++ MOD_DEC_USE_COUNT;
++
++ dprintf (1, "Leave tn7atm_close\n");
++}
++
++#define ATM_TXSTOP 0x800c61f4
++static int
++tn7atm_ioctl (struct atm_dev *dev, unsigned int cmd, void *arg)
++{
++ Tn7AtmPrivate *priv;
++ priv = (Tn7AtmPrivate *) dev->dev_data;
++
++ //printk("tn7atm_ioctl\n");
++ //printk("arg = %x\n", *(int *)arg);
++ //printk("cmd =%x\n", cmd);
++ switch(cmd)
++ {
++
++ case ATM_TXSTOP: /*temp fix for SAR tear down problem */
++// printk("ioctl cmd = 0x%x (%u), arg = 0x%p (%lu)\n", cmd, cmd, arg, (unsigned long)arg);
++// printk("arg = %d\n", *(int*)arg);
++ priv->xmitStop = *(int *)arg;
++ //printk("Executing ATM_SETLOOP for tn7 \n");
++ //printk("Stop variable = :%d: \n",priv->xmitStop);
++ return 0;
++
++ //case SAR_DSL_RESET_SOFTBOOT:
++ // return tn7atm_dsl_clean_reboot();
++ case 0:
++ return 0;
++ }
++
++ return -ENOSYS;
++
++}
++
++static int
++tn7atm_change_qos (struct atm_vcc *vcc, struct atm_qos *qos,int flags)
++{
++ dprintf (1, "Enter tn7atm_change_qos\n");
++ dprintf (1, "Leave tn7atm_change_qos\n");
++ return 0;
++}
++
++
++int tn7atm_send (struct atm_vcc *vcc, struct sk_buff *skb)
++{
++
++ Tn7AtmPrivate *priv;
++ int bret;
++ int chan;
++
++ dprintf(4, "tn7atm_send()\n");
++
++ priv = (Tn7AtmPrivate*)vcc->dev->dev_data;
++
++ //if(skb->len < 64)
++ //xdump((unsigned char *)skb->data, skb->len, 1);
++ //else
++ //xdump((unsigned char *)skb->data, 64, 1);
++ /* check for dsl line connection */
++
++ /* add vcc field in skb for clip inATMARP fix */
++ ATM_SKB(skb)->vcc = vcc;
++ /* Ron change 2.3 -> 2.4 ??*/
++ //if(priv->lConnected != 1 || priv->xmitStop == 1)
++ if(priv->lConnected != 1 && priv->xmitStop == 1)
++ {
++ dprintf(4,"dsl line down\n");
++ if(vcc->pop)
++ vcc->pop(vcc, skb);
++ else
++ tn7atm_kfree_skb(skb);
++ return 1;
++ }
++
++ /* check whether PVC is closing */
++ chan = tn7atm_lut_find(vcc->vpi, vcc->vci);
++ /* set br2684 dev pointer */
++ priv->lut[chan].net_device = skb->dev;
++ if(chan == ATM_NO_DMA_CHAN || priv->lut[chan].bClosing == 1)
++ {
++ dprintf(4, "can find sar channel\n");
++ if(vcc->pop)
++ vcc->pop(vcc, skb);
++ else
++ tn7atm_kfree_skb(skb);
++ return 1;
++ }
++
++ bret=tn7atm_queue_packet_to_sar(vcc, skb);
++
++ return bret;
++}
++
++
++static int tn7atm_queue_packet_to_sar(void *vcc1, void *skb1)
++{
++ struct atm_vcc *vcc;
++ struct sk_buff *skb;
++ int priority = 1;
++ Tn7AtmPrivate *priv;
++ int dmachan;
++
++ vcc = (struct atm_vcc *)vcc1;
++ skb = (struct sk_buff *)skb1;
++
++ priv = (Tn7AtmPrivate*)vcc->dev->dev_data;
++
++ dprintf(4, "vcc->vci=%d\n", vcc->vci);
++ dmachan = tn7atm_lut_find(vcc->vpi, vcc->vci);
++ if(dmachan == ATM_NO_DMA_CHAN)
++ {
++ dprintf(4, "can find sar channel\n");
++ if(vcc->pop)
++ vcc->pop(vcc, skb);
++ else
++ tn7atm_kfree_skb(skb);
++ return 1;
++ }
++
++ // turbo dsl TCP ack check
++ if(priv->bTurboDsl)
++ priority = turbodsl_check_priority_type(skb->data);
++
++ //skb priority check
++ if(priority != 0)
++ {
++ if((skb->cb[47])>>1)
++ priority=1;
++ else
++ priority = 0;
++ }
++
++ /* add queue info here */
++ skb->cb[47] = (char)priority;
++ spin_lock_irqsave(&priv->netifqueueLock, priv->netifqueueLockFlag);
++ priv->lut[dmachan].tx_used_bufs[priority]++;
++ spin_unlock_irqrestore(&priv->netifqueueLock, priv->netifqueueLockFlag);
++
++ if(tn7sar_send_packet(priv,dmachan, skb, skb->data, skb->len, priority) != 0)
++ {
++ dprintf(1, "failed to send packet\n");
++ if(vcc->pop)
++ vcc->pop(vcc, skb);
++ else
++ tn7atm_kfree_skb(skb);
++
++ spin_lock_irqsave(&priv->netifqueueLock, priv->netifqueueLockFlag);
++ priv->lut[dmachan].tx_used_bufs[priority]--;
++ spin_unlock_irqrestore(&priv->netifqueueLock, priv->netifqueueLockFlag);
++ return 1;
++ }
++
++ /* check for whether tx queue is full or not */
++ //printk("bufs used = %d\n", priv->lut[dmachan].tx_used_bufs[1]);
++ spin_lock_irqsave(&priv->netifqueueLock, priv->netifqueueLockFlag);
++ if(priv->lut[dmachan].tx_used_bufs[1] >= (priv->lut[dmachan].tx_total_bufs - STOP_EMPTY_BUFF) ||
++ priv->lut[dmachan].tx_used_bufs[0] >= (priv->lut[dmachan].tx_total_bufs - STOP_EMPTY_BUFF))
++ {
++ //printk("net queue stoped\n");
++ netif_stop_queue(priv->lut[dmachan].net_device);
++ priv->lut[dmachan].netqueue_stop = 1;
++ }
++ spin_unlock_irqrestore(&priv->netifqueueLock, priv->netifqueueLockFlag);
++
++ return 0;
++}
++
++/* functions needed by SAR HAL */
++
++int tn7atm_send_complete(void *osSendInfo)
++{
++ Tn7AtmPrivate *priv;
++ //struct atm_dev *dev;
++ struct sk_buff *skb;
++ struct atm_vcc *vcc;
++ int chan;
++
++ dprintf(4, "tn7atm_send_complete()\n");
++
++
++ skb = (struct sk_buff *)osSendInfo;
++ //dev = (struct atm_dev *) (skb->dev);
++ priv = (Tn7AtmPrivate *)mydev->dev_data;
++ vcc =ATM_SKB(skb)->vcc;
++ if(vcc)
++ {
++ dprintf(4, "vcc->vci=%d\n",vcc->vci );
++ chan = tn7atm_lut_find(vcc->vpi, vcc->vci);
++ if(chan==ATM_NO_DMA_CHAN)
++ return 1;
++
++ /*decreament packet queued number */
++ spin_lock_irqsave(&priv->netifqueueLock, priv->netifqueueLockFlag);
++ priv->lut[chan].tx_used_bufs[(int)skb->cb[47]] --;
++ if(priv->lut[chan].tx_used_bufs[1] < priv->lut[chan].tx_total_bufs - START_EMPTY_BUFF &&
++ priv->lut[chan].tx_used_bufs[0] < priv->lut[chan].tx_total_bufs - START_EMPTY_BUFF)
++ {
++ if(priv->lut[chan].netqueue_stop)
++ {
++ //printk("net queue restarted\n");
++ netif_wake_queue(priv->lut[chan].net_device);
++ priv->lut[chan].netqueue_stop = 0;
++ }
++ }
++ spin_unlock_irqrestore(&priv->netifqueueLock, priv->netifqueueLockFlag);
++
++ if(vcc->pop)
++ {
++ dprintf(5, "free packet\n");
++ vcc->pop(vcc, skb);
++ }
++
++
++ }
++
++
++
++ /* Update Stats: There may be a better place to do this, but this is a start */
++ priv->stats.tx_packets++;
++#ifdef CONFIG_LED_MODULE
++// led_operation(MOD_ADSL, DEF_ADSL_ACTIVITY);
++#endif
++
++ /* track number of buffer used */
++
++ dprintf(4, "tn7atm_send_complete() done\n");
++
++ return 0;
++}
++
++void *tn7atm_allocate_rx_skb(void *os_dev, void **os_receive_info, unsigned int size)
++{
++ struct sk_buff *skb;
++ dprintf(4, "tn7atm_allocate_rx_skb size=%d\n", size);
++ size = ((size+3)&0xfffffffc);
++ skb = dev_alloc_skb(size);
++ if(skb==NULL)
++ {
++ //printk("rx allocate skb failed\n");
++ return NULL;
++ }
++ *os_receive_info = (void *)skb;
++ return (skb->data);
++}
++
++void tn7atm_free_rx_skb(void *skb)
++{
++ dprintf(4, "tn7atm_free_rx_skb\n");
++ tn7atm_kfree_skb((struct sk_buff *)skb);
++}
++
++
++int tn7atm_receive(void *os_dev, int ch, unsigned int packet_size, void *os_receive_info, void *data)
++{
++ Tn7AtmPrivate *priv;
++ struct atm_dev *dev;
++ struct sk_buff *skb;
++ struct atm_vcc *vcc;
++
++
++ dprintf(4, "tn7atm_receive()\n");
++ dev = (struct atm_dev *)os_dev;
++
++ priv = (Tn7AtmPrivate *)dev->dev_data;
++
++ if(priv->lConnected != 1 || priv->lut[ch].ready == 0)
++ {
++ //printk("channel not ready\n");
++ return 1;
++ }
++
++ vcc = (struct atm_vcc *)priv->lut[ch].vcc;
++ if(vcc == NULL)
++ {
++ printk("vcc=Null");
++ return 1;
++ }
++
++
++ /* assume no fragment packet for now */
++ skb = (struct sk_buff *)os_receive_info;
++
++ if(skb==NULL)
++ {
++ dprintf(1, "received empty skb.\n");
++ return 1;
++ }
++ /* see skbuff->cb definition in include/linux/skbuff.h */
++ ATM_SKB(skb)->vcc = vcc;
++
++ skb->len = packet_size;
++ dprintf(3, "skb:[0x%p]:0x%x pdu_len: 0x%04x\n",skb,skb->len,packet_size);
++ dprintf(3, "data location: 0x%x, 0x%x\n", (unsigned int)skb->data, (unsigned int)data);
++
++ /*skb_trim(skb,skb->len); */ /* skb size is incorrect for large packets > 1428 bytes ?? */
++ __skb_trim(skb,skb->len); /* change to correct > 1500 ping when firewall is on */
++
++ dprintf(3, "pushing the skb...\n");
++ skb->stamp = xtime;
++
++ xdump((unsigned char *)skb->data, skb->len, 5);
++
++ if(atm_charge(vcc, skb->truesize) == 0)
++ {
++ dprintf(1,"Receive buffers saturated for %d.%d.%d - PDU dropped\n", vcc->itf, vcc->vci, vcc->vpi);
++ return 1;
++ }
++
++ /*pass it up to kernel networking layer and update stats*/
++ vcc->push(vcc,skb);
++
++ /* Update receive packet stats */
++ priv->stats.rx_packets++;
++ atomic_inc(&vcc->stats->rx);
++
++#ifdef CONFIG_LED_MODULE
++// led_operation(MOD_ADSL, DEF_ADSL_ACTIVITY);
++#endif
++ dprintf(3, "(a) Receiving:vpi/vci[%d/%d] chan_id: %d skb len:0x%x skb truesize:0x%x\n",
++ vcc->vpi,vcc->vci,ch,skb->len, skb->truesize);
++
++ return 0;
++}
++
++static int
++tn7atm_proc_channels(char* buf, char **start, off_t offset, int count,int *eof, void *data)
++{
++ int len = 0;
++ int limit = count - 80;
++ int i;
++
++ struct atm_dev *dev;
++ Tn7AtmPrivate *priv;
++
++ dev = (struct atm_dev *)data;
++ priv = (Tn7AtmPrivate *)dev->dev_data;
++
++ if(len<=limit)
++ len += sprintf(buf+len,"Chan Inuse ChanID VPI VCI \n");
++ if(len<=limit)
++ len += sprintf(buf+len,"------------------------------------------------------------------\n");
++
++ for(i=0; i < MAX_DMA_CHAN; i++)
++ {
++ if(len<=limit)
++ {
++ len += sprintf(buf+len,
++ " %02d %05d %05d %05d %05d \n",
++ i,priv->lut[i].inuse,priv->lut[i].chanid,
++ priv->lut[i].vpi,priv->lut[i].vci);
++ }
++ }
++
++ return len;
++}
++
++static int
++tn7atm_proc_private(char* buf, char **start, off_t offset, int count,int *eof, void *data)
++{
++ int len = 0;
++ int limit = count - 80;
++ struct atm_dev *dev;
++ Tn7AtmPrivate *priv;
++
++ dev = (struct atm_dev *)data;
++ priv = (Tn7AtmPrivate *)dev->dev_data;
++
++ if(len<=limit)
++ len += sprintf(buf+len, "\nPrivate Data Structure(%s):\n",priv->name);
++ if(len<=limit)
++ len += sprintf(buf+len, "----------------------------------------\n");
++ if(len<=limit)
++ len += sprintf(buf+len, "priv: 0x%p\n",priv);
++ if(len<=limit)
++ len += sprintf(buf+len, "next: 0x%p",priv->next);
++ if(len<=limit)
++ len += sprintf(buf+len, "\tdev: 0x%p\n",priv->dev);
++
++ if(len<=limit)
++ len += sprintf(buf+len, "tx_irq: %02d",priv->sar_irq);
++ if(len<=limit)
++ len += sprintf(buf+len, "rx_irq: %02d",priv->dsl_irq);
++
++
++ return len;
++}
++
++void tn7atm_sarhal_isr_register(void *os_dev, void *hal_isr, int interrupt_num)
++{
++ struct atm_dev *dev;
++ Tn7AtmPrivate *priv;
++
++ dprintf(4, "tn7atm_sarhal_isr_register()\n");
++
++ dev = (struct atm_dev *)os_dev;
++ priv = (Tn7AtmPrivate *)dev->dev_data;
++ priv->halIsr = (void *)hal_isr;
++ priv->int_num = interrupt_num;
++}
++
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_exit(void)
++ *
++ * Description: Avalanche SAR exit function
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
++
++static void
++tn7atm_exit (void)
++{
++
++ struct atm_dev *dev;
++
++ Tn7AtmPrivate *priv;
++
++ dprintf(4, "tn7atm_exit()\n");
++
++ dev=mydev;
++ priv = (Tn7AtmPrivate *)dev->dev_data;
++ priv->lConnected = 0;
++ tn7dsl_exit();
++
++ tn7sar_exit(dev, priv);
++
++ /* freeup irq's */
++ free_irq(priv->dsl_irq,priv->dev);
++ free_irq(priv->sar_irq,priv->dev);
++
++ kfree (dev->dev_data);
++
++ // atm_dev_deregister (dev);
++ shutdown_atm_dev(dev);
++
++ /* remove proc entries */
++ remove_proc_entry("tiatm/avsar_ver",NULL);
++ remove_proc_entry("tiatm/avsar_modem_stats",NULL);
++ remove_proc_entry("tiatm/avsar_modem_training",NULL);
++ remove_proc_entry("tiatm/avsar_channels",NULL);
++ remove_proc_entry("tiatm/avsar_private",NULL);
++ remove_proc_entry("tiatm/avsar_sarhal_stats",NULL);
++ remove_proc_entry("tiatm/avsar_oam_ping",NULL);
++ remove_proc_entry("tiatm/avsar_pvc_table",NULL);
++ remove_proc_entry("tiatm",NULL);
++ tn7dsl_dslmod_sysctl_unregister();
++
++ printk ("Module Removed\n");
++
++}
++
++
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_registration(struct tn7* tn7)
++ *
++ * Description: ATM driver registration
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
++
++static int __init
++tn7atm_register (Tn7AtmPrivate * priv)
++{
++ /* allocate memory for the device */
++
++ dprintf(4,"device %s being registered\n", priv->name);
++
++ mydev = atm_dev_register (priv->proc_name, &tn7atm_ops, -1, NULL);
++
++ if (mydev == NULL)
++ {
++ printk ("atm_dev_register returning NULL\n");
++ return ATM_REG_FAILED;
++ }
++
++ printk ("registered device %s\n", priv->name);
++
++ mydev->dev_data = priv; /* setup device data in atm_dev struct */
++ priv->dev = mydev; /* setup atm_device in avalanche sar struct */
++
++ mydev->ci_range.vpi_bits = ATM_CI_MAX; /* atm supports 11 bits */
++ mydev->ci_range.vci_bits = 16; /* atm VCI max = 16 bits */
++
++
++ return ATM_REG_OK;
++}
++
++static int
++tn7atm_proc_version(char* buf, char **start, off_t offset, int count,int *eof, void *data)
++{
++ int len = 0;
++ char dslVer[8];
++ char dspVer[10];
++ char *pSarVer;
++ Tn7AtmPrivate *priv;
++ int i;
++ unsigned int pdspV1, pdspV2;
++
++ priv = mydev->dev_data;
++
++ len += sprintf(buf+len, "ATM Driver version:[%d.%02d.%02d.%02d]\n",LINUXATM_VERSION_MAJOR, LINUXATM_VERSION_MINOR,
++ LINUXATM_VERSION_BUGFIX, LINUXATM_VERSION_BUILDNUM);
++
++ tn7dsl_get_dslhal_version(dslVer);
++
++ len += sprintf(buf+len, "DSL HAL version: [%d.%02d.%02d.%02d]\n", dslVer[0], dslVer[1], dslVer[2],
++ dslVer[3]);
++ tn7dsl_get_dsp_version(dspVer);
++
++ len += sprintf(buf+len, "DSP Datapump version: [%d.%02d.%02d.%02d] ", dspVer[4], dspVer[5], dspVer[6],
++ dspVer[7]);
++ if(dspVer[8]==2) // annex B
++ len += sprintf(buf+len, "Annex B\n");
++ else if(dspVer[8]==3) //annex c
++ len += sprintf(buf+len, "Annex c\n");
++ else
++ len += sprintf(buf+len, "Annex A\n");
++
++ tn7sar_get_sar_version(priv, &pSarVer);
++
++ len += sprintf(buf+len, "SAR HAL version: [");
++ for(i=0;i<8;i++)
++ {
++ len += sprintf(buf+len, "%c", pSarVer[i+7]);
++ }
++ len += sprintf(buf+len, "]\n");
++
++ tn7sar_get_sar_firmware_version(&pdspV1, &pdspV2);
++ len += sprintf(buf+len, "PDSP Firmware version:[%01x.%02x]\n",
++ pdspV1,pdspV2);
++
++ return len;
++}
++
++/*
++static struct net_device_stats
++*tn7atm_get_stats(struct atm_dev *dev)
++{
++ Tn7AtmPrivate *priv;
++ //unsigned long flags;
++
++ //spin_lock_irqsave(&priv->stats_lock,flags);
++ priv= (Tn7AtmPrivate *)dev->dev_data;
++ //spin_unlock_irqrestore(&priv->stats_lock,flags);
++
++ return &priv->stats;
++
++}
++*/
++/* Device detection */
++
++static int __init
++tn7atm_detect (void)
++{
++ Tn7AtmPrivate *priv;
++ //static struct proc_dir_entry *proc_dir;
++
++ dprintf(4, "tn7atm_detect().\n");
++ /* Device allocated as a global static structure at top of code "mydev" */
++
++ /* Alloc priv struct */
++ priv=kmalloc(sizeof(Tn7AtmPrivate),GFP_KERNEL);
++ if(!priv)
++ {
++ printk("unable to kmalloc priv structure. Killing autoprobe.\n");
++ return -ENODEV;
++ }
++ memset(priv, 0, sizeof(Tn7AtmPrivate));
++#ifdef COMMON_NSP
++ priv->name = "TI Avalanche SAR";
++ priv->proc_name = "avsar";
++#else
++ priv->name = "TI tnetd73xx ATM Driver";
++ priv->proc_name = "tn7";
++#endif
++
++ if ((tn7atm_register (priv)) == ATM_REG_FAILED)
++ return -ENODEV;
++
++ tn7atm_init(mydev);
++
++ /* Set up proc entry for atm stats */
++ proc_mkdir("tiatm", NULL);
++ create_proc_read_entry("tiatm/avsar_modem_stats",0,NULL,tn7dsl_proc_stats,NULL);
++ create_proc_read_entry("tiatm/avsar_modem_training",0,NULL,tn7dsl_proc_modem,NULL);
++ create_proc_read_entry("tiatm/avsar_ver",0,NULL,tn7atm_proc_version,NULL);
++ create_proc_read_entry("tiatm/avsar_channels",0,NULL,tn7atm_proc_channels,mydev);
++ create_proc_read_entry("tiatm/avsar_private",0,NULL,tn7atm_proc_private,mydev);
++ create_proc_read_entry("tiatm/avsar_sarhal_stats",0,NULL,tn7sar_proc_sar_stat,mydev);
++ create_proc_read_entry("tiatm/avsar_oam_ping",0,NULL,tn7sar_proc_oam_ping,mydev);
++ create_proc_read_entry("tiatm/avsar_pvc_table",0,NULL,tn7sar_proc_pvc_table,mydev);
++
++ tn7dsl_dslmod_sysctl_register();
++
++ printk("Texas Instruments ATM driver: version:[%d.%02d.%02d.%02d]\n",LINUXATM_VERSION_MAJOR, LINUXATM_VERSION_MINOR,
++ LINUXATM_VERSION_BUGFIX, LINUXATM_VERSION_BUILDNUM);
++ return 0;
++}
++
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_probe(void)
++ *
++ * Description: Avalanche SAR driver probe (see net/atm/pvc.c)
++ * this is utilized when the SAR driver is built
++ * into the kernel and needs to be configured.
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
++int __init tn7atm_probe(void)
++{
++ tn7atm_detect();
++ return -ENODEV;
++}
++
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int tn7atm_init(struct atm_dev *dev)
++ *
++ * Description: Device Initialization
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
++static int __init
++tn7atm_init(struct atm_dev *dev)
++{
++ Tn7AtmPrivate *priv;
++ char *ptr;
++
++ dprintf(4, "tn7atm_init()\n");
++
++ priv = (Tn7AtmPrivate *)dev->dev_data;
++
++ if(tn7sar_init(dev, priv) != 0)
++ {
++ printk("Failed to init SAR.\n");
++ return -ENODEV;
++ }
++
++ if(tn7dsl_init(priv) < 0)
++ {
++ printk("Failed to init DSL.\n");
++ return -ENODEV;
++ }
++
++ if(tn7atm_get_ESI(dev) < 0) /* set ESI */
++ return -ENODEV;
++
++ if(tn7atm_irq_request(dev) < 0)
++ return -EBUSY;
++
++ priv->bTurboDsl = 1;
++ // read config for turbo dsl
++ ptr = prom_getenv("TurboDSL");
++ if(ptr)
++ {
++ priv->bTurboDsl = os_atoi(ptr);
++ }
++
++ return 0;
++}
++
++int tn7atm_device_connect_status(void *priv, int state)
++{
++ Tn7AtmPrivate *priv1;
++
++ dprintf(5, "tn7atm_device_connect_status()\n");
++ priv1 = (Tn7AtmPrivate *)priv;
++
++ priv1->lConnected = state;
++ dprintf(5, "priv1->lConnected=%d\n", priv1->lConnected);
++ return 0;
++}
++
++
++#ifdef MODULE
++module_init (tn7atm_detect);
++module_exit (tn7atm_exit);
++#endif /* MODULE */
+diff -urN linux.old/drivers/atm/sangam_atm/tn7atm.h linux.dev/drivers/atm/sangam_atm/tn7atm.h
+--- linux.old/drivers/atm/sangam_atm/tn7atm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/tn7atm.h 2005-08-23 04:46:50.107842176 +0200
+@@ -0,0 +1,115 @@
++/*
++ * Tnetd73xx ATM driver.
++ * by Zhicheng Tang, ztang@ti.com
++ * 2000 (c) Texas Instruments Inc.
++ *
++ *
++*/
++
++#ifndef __TN7ATM_H
++#define __TN7ATM_H
++
++//#include "mips_support.h"
++#include <linux/list.h>
++
++#define ATM_REG_OK 1
++#define ATM_REG_FAILED 0
++
++#define TX_SERVICE_MAX 32
++#define RX_SERVICE_MAX 20
++#define TX_BUFFER_NUM 64
++#define RX_BUFFER_NUM 28
++#define TX_QUEUE_NUM 2
++#define RX_BUFFER_SIZE 1582
++
++#define TX_DMA_CHAN 16 /* number of tx dma channels available */
++#define MAX_DMA_CHAN 16
++#define ATM_NO_DMA_CHAN MAX_DMA_CHAN + 1 /* no tx dma channels available */
++#define ATM_SAR_INT 15
++#define ATM_SAR_INT_PACING_BLOCK_NUM 2
++#define ATM_DSL_INT 39
++
++#define CONFIG_ATM_TN7ATM_DEBUG 0 /* Debug level (0=no mtn7s 5=verbose) */
++
++#define TN7ATM_DEV(d) ((struct tn7atm*)((d)->dev_data))
++
++
++/* Avalanche SAR state information */
++
++typedef enum tn7atm_state
++{
++ TN7ATM_STATE_REGISTER /* device registered */
++}tn7atm_state;
++
++typedef struct _sar_stat
++{
++ unsigned int txErrors;
++ unsigned int rxErrors;
++ unsigned int rxPktCnt;
++ unsigned int txPktCnt;
++ unsigned int rxBytes;
++ unsigned int txBytes;
++}sar_stat_t;
++
++/* Host based look up table to xref Channel Id's, VPI/VCI, LC, CID, packet type */
++typedef struct _tn7atm_tx_lut
++{
++ int inuse; /* is DMA channel available (1=y) */
++ int chanid; /* DMA channel ID (0-0x1f) This corresponds to the Channel ID
++ that is used in the connection config reg (TN7ATM_CONN_CONFIG) */
++ int vpi; /* Virtual path identifier */
++ int vci; /* Virtual channel identifier */
++ void *vcc;
++ int bClosing;
++ int ready;
++ void *net_device;
++ int tx_total_bufs;
++ int tx_used_bufs[2];
++ int netqueue_stop;
++}tn7atm_lut_t;
++
++/* per device data */
++
++typedef struct _tn7atm_private
++{
++ struct _tn7atm_private *next; /* next device */
++ struct atm_dev *dev; /* ATM device */
++ struct net_device_stats stats; /* Used to report Tx/Rx frames from ifconfig */
++ tn7atm_lut_t lut[MAX_DMA_CHAN]; /* Tx DMA look up table (LUT) */
++ int dsl_irq; /* ATM SAR TransmitA interrupt number */
++ int sar_irq; /* ATM SAR ReceiveA interrupt number */
++ char* name; /* device name */
++ char* proc_name; /* board name under /proc/atm */
++ unsigned int available_cell_rate; /* cell rate */
++ unsigned int connection_cell_rate; /* cell rate */
++ int lConnected;
++
++ /* Tnetd73xx CPHAL */
++ void *pSarHalDev;
++ void *pSarHalFunc;
++ void *pSarOsFunc;
++ void *halIsr;
++ int int_num;
++
++ /* turbo dsl */
++ int bTurboDsl;
++
++ /* spin lock for netifqueue */
++ spinlock_t netifqueueLock;
++ int netifqueueLockFlag;
++ int xmitStop; /* temp fix for SAR problem */
++}tn7atm_private_t, Tn7AtmPrivate;
++
++
++
++/* ATM adaptation layer id */
++typedef enum tn7atm_aal {
++ TN7ATM_AAL0 = 0,
++ TN7ATM_AAL2 = 2,
++ TN7ATM_AAL5 = 5,
++} tn7atm_aal_t;
++
++
++
++
++#endif
+diff -urN linux.old/drivers/atm/sangam_atm/tn7dsl.c linux.dev/drivers/atm/sangam_atm/tn7dsl.c
+--- linux.old/drivers/atm/sangam_atm/tn7dsl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/tn7dsl.c 2005-08-23 04:46:50.109841872 +0200
+@@ -0,0 +1,1780 @@
++/*
++ * $Id$
++ *
++ * Avalanche SAR driver
++ *
++ * Zhicheng Tang, ztang@ti.com
++ * 2000 (c) Texas Instruments Inc.
++ *
++ *
++*/
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/atmdev.h>
++#include <linux/delay.h>
++#include <linux/spinlock.h>
++#include <linux/smp_lock.h>
++#include <asm/io.h>
++#include <asm/mips-boards/prom.h>
++#include <linux/proc_fs.h>
++#include <linux/string.h>
++#include <linux/ctype.h>
++#include <linux/sysctl.h>
++#include <linux/timer.h>
++#include <linux/vmalloc.h>
++#include <linux/file.h>
++#include <asm/uaccess.h>
++
++#include "tn7atm.h"
++#include "tn7api.h"
++#include "dsl_hal_api.h"
++
++#ifdef CONFIG_LED_MODULE
++#include <asm/ar7/ledapp.h>
++#define MOD_ADSL 1
++#define DEF_ADSL_IDLE 1
++#define DEF_ADSL_TRAINING 2
++#define DEF_ADSL_SYNC 3
++#define DEF_ADSL_ACTIVITY 4
++
++#define LED_NUM_1 3
++#define LED_NUM_2 4
++
++led_reg_t ledreg[2];
++
++static int led_on;
++#endif
++
++extern int __guDbgLevel;
++extern sar_stat_t sarStat;
++static int dslInSync = 0;
++static int bMarginThConfig;
++static int bMarginRetrainEnable;
++static char EOCVendorID[8]= {0xb5, 0x00, 0x54, 0x53, 0x54, 0x43, 0x00, 0x00};
++
++#define TC_SYNC 1
++#define SYNC_TIME_DELAY 500000
++
++
++#define DEV_DSLMOD 1
++#define MAX_STR_SIZE 256
++#define DSL_MOD_SIZE 256
++
++#define TRUE 1
++#define FALSE 0
++
++
++enum
++{
++ NO_MODE,
++ MULTI_MODE,
++ T1413_MODE,
++ GDMT_MODE,
++ GLITE_MODE
++};
++
++
++
++/* a structure to store all information we need
++ for our thread */
++typedef struct kthread_struct
++{
++ /* private data */
++
++ /* Linux task structure of thread */
++ struct task_struct *thread;
++ /* Task queue need to launch thread */
++ struct tq_struct tq;
++ /* function to be started as thread */
++ void (*function) (struct kthread_struct *kthread);
++ /* semaphore needed on start and creation of thread. */
++ struct semaphore startstop_sem;
++
++ /* public data */
++
++ /* queue thread is waiting on. Gets initialized by
++ init_kthread, can be used by thread itself.
++ */
++ wait_queue_head_t queue;
++ /* flag to tell thread whether to die or not.
++ When the thread receives a signal, it must check
++ the value of terminate and call exit_kthread and terminate
++ if set.
++ */
++ int terminate;
++ /* additional data to pass to kernel thread */
++ void *arg;
++} kthread_t;
++
++#ifndef ADIAG
++#define DSP_FIRMWARE_PATH "/lib/modules/ar0700xx.bin"
++#else
++#define DSP_FIRMWARE_PATH "/var/tmp/ar0700xx_diag.bin"
++#endif
++
++/* externs */
++extern struct atm_dev *mydev;
++extern unsigned int oamFarLBCount[4];
++extern int dslhal_support_restoreTrainingInfo(PITIDSLHW_T pIhw);
++/* gloabal functions */
++
++/* end of global functions */
++
++/* module wide declars */
++static PITIDSLHW_T pIhw;
++static char mod_req[16]={'\t'};
++static volatile int bshutdown;
++static char info[MAX_STR_SIZE];
++static DECLARE_MUTEX_LOCKED(adsl_sem_overlay); /* Used for DSL Polling enable */
++kthread_t overlay_thread;
++/* end of module wide declars */
++
++/* Internal Functions */
++static void tn7dsl_chng_modulation(void* data);
++static void tn7dsl_set_modulation(void* data);
++static int tn7dsl_reload_overlay(void);
++static int dslmod_sysctl(ctl_table *ctl, int write, struct file * filp, void *buffer, size_t *lenp);
++static void tn7dsl_register_dslss_led(void);
++void tn7dsl_dslmod_sysctl_register(void);
++void tn7dsl_dslmod_sysctl_unregister(void);
++/* end of internal functions */
++
++
++
++
++
++/* prototypes */
++
++/* start new kthread (called by creator) */
++void start_kthread(void (*func)(kthread_t *), kthread_t *kthread);
++
++/* stop a running thread (called by "killer") */
++void stop_kthread(kthread_t *kthread);
++
++/* setup thread environment (called by new thread) */
++void init_kthread(kthread_t *kthread, char *name);
++
++/* cleanup thread environment (called by thread upon receiving termination signal) */
++void exit_kthread(kthread_t *kthread);
++
++
++
++/* private functions */
++static void kthread_launcher(void *data)
++{
++ kthread_t *kthread = data;
++ kernel_thread((int (*)(void *))kthread->function, (void *)kthread, 0);
++
++}
++
++/* public functions */
++
++/* create a new kernel thread. Called by the creator. */
++void start_kthread(void (*func)(kthread_t *), kthread_t *kthread)
++{
++ /* initialize the semaphore:
++ we start with the semaphore locked. The new kernel
++ thread will setup its stuff and unlock it. This
++ control flow (the one that creates the thread) blocks
++ in the down operation below until the thread has reached
++ the up() operation.
++ */
++ //init_MUTEX_LOCKED(&kthread->startstop_sem);
++
++ /* store the function to be executed in the data passed to
++ the launcher */
++ kthread->function=func;
++
++ /* create the new thread my running a task through keventd */
++
++ /* initialize the task queue structure */
++ kthread->tq.sync = 0;
++ INIT_LIST_HEAD(&kthread->tq.list);
++ kthread->tq.routine = kthread_launcher;
++ kthread->tq.data = kthread;
++
++ /* and schedule it for execution */
++ schedule_task(&kthread->tq);
++
++ /* wait till it has reached the setup_thread routine */
++ //down(&kthread->startstop_sem);
++
++}
++
++/* stop a kernel thread. Called by the removing instance */
++void stop_kthread(kthread_t *kthread)
++{
++ if (kthread->thread == NULL)
++ {
++ printk("stop_kthread: killing non existing thread!\n");
++ return;
++ }
++
++ /* this function needs to be protected with the big
++ kernel lock (lock_kernel()). The lock must be
++ grabbed before changing the terminate
++ flag and released after the down() call. */
++ lock_kernel();
++
++ /* initialize the semaphore. We lock it here, the
++ leave_thread call of the thread to be terminated
++ will unlock it. As soon as we see the semaphore
++ unlocked, we know that the thread has exited.
++ */
++ //init_MUTEX_LOCKED(&kthread->startstop_sem);
++
++ /* We need to do a memory barrier here to be sure that
++ the flags are visible on all CPUs.
++ */
++ mb();
++
++ /* set flag to request thread termination */
++ kthread->terminate = 1;
++
++ /* We need to do a memory barrier here to be sure that
++ the flags are visible on all CPUs.
++ */
++ mb();
++ kill_proc(kthread->thread->pid, SIGKILL, 1);
++
++ /* block till thread terminated */
++ //down(&kthread->startstop_sem);
++
++ /* release the big kernel lock */
++ unlock_kernel();
++
++ /* now we are sure the thread is in zombie state. We
++ notify keventd to clean the process up.
++ */
++ kill_proc(2, SIGCHLD, 1);
++
++}
++
++/* initialize new created thread. Called by the new thread. */
++void init_kthread(kthread_t *kthread, char *name)
++{
++ /* lock the kernel. A new kernel thread starts without
++ the big kernel lock, regardless of the lock state
++ of the creator (the lock level is *not* inheritated)
++ */
++ lock_kernel();
++
++ /* fill in thread structure */
++ kthread->thread = current;
++
++ /* set signal mask to what we want to respond */
++ siginitsetinv(&current->blocked, sigmask(SIGKILL)|sigmask(SIGINT)|sigmask(SIGTERM));
++
++ /* initialise wait queue */
++ init_waitqueue_head(&kthread->queue);
++
++ /* initialise termination flag */
++ kthread->terminate = 0;
++
++ /* set name of this process (max 15 chars + 0 !) */
++ sprintf(current->comm, name);
++
++ /* let others run */
++ unlock_kernel();
++
++ /* tell the creator that we are ready and let him continue */
++ //up(&kthread->startstop_sem);
++
++}
++
++/* cleanup of thread. Called by the exiting thread. */
++void exit_kthread(kthread_t *kthread)
++{
++ /* we are terminating */
++
++ /* lock the kernel, the exit will unlock it */
++ lock_kernel();
++ kthread->thread = NULL;
++ mb();
++
++ /* notify the stop_kthread() routine that we are terminating. */
++ //up(&kthread->startstop_sem);
++ /* the kernel_thread that called clone() does a do_exit here. */
++
++ /* there is no race here between execution of the "killer" and real termination
++ of the thread (race window between up and do_exit), since both the
++ thread and the "killer" function are running with the kernel lock held.
++ The kernel lock will be freed after the thread exited, so the code
++ is really not executed anymore as soon as the unload functions gets
++ the kernel lock back.
++ The init process may not have made the cleanup of the process here,
++ but the cleanup can be done safely with the module unloaded.
++ */
++
++}
++
++
++
++int os_atoi(const char *pStr)
++{
++ int retVal = -1;
++
++ if(*pStr=='-')
++ retVal = -simple_strtoul(pStr+1, (char **)NULL, 10);
++ else
++ retVal = simple_strtoul(pStr, (char **)NULL, 10);
++ return retVal ;
++}
++
++
++int os_atoh(const char *pStr)
++{
++ int retVal = -1;
++
++ if(*pStr=='-')
++ retVal = -simple_strtoul(pStr+1, (char **)NULL, 16);
++ else
++ retVal = simple_strtoul(pStr, (char **)NULL, 16);
++ return retVal ;
++}
++
++unsigned long os_atoul(const char *pStr)
++{
++ unsigned long retVal = -1;
++
++ retVal = simple_strtoul(pStr, (char **)NULL, 10);
++ return retVal ;
++}
++
++void dprintf( int uDbgLevel, char * szFmt, ...)
++{
++#ifdef DEBUG_BUILD
++ static char buff[256];
++ va_list ap;
++
++ if( __guDbgLevel < uDbgLevel)
++ return;
++
++ va_start( ap, szFmt);
++ vsprintf((char *)buff, szFmt, ap);
++ va_end(ap);
++ printk("%s", buff);
++#endif
++}
++
++/*int strcmp(const char *s1, const char *s2)
++{
++
++ int i=0;
++
++ while(s1[i] !=0)
++ {
++ if(s2[i]==0)
++ return -1;
++ if(s1[i] != s2[i])
++ return 1;
++ i++;
++ }
++ if(s2[i] != 0)
++ return 1;
++ return 0;
++}
++*/
++
++int shim_osLoadFWImage(unsigned char *ptr)
++{
++ unsigned int bytesRead;
++ mm_segment_t oldfs;
++ static struct file *filp;
++ unsigned int imageLength=0x4ffff;
++
++
++ dprintf(4, "tn7dsl_read_dsp()\n");
++
++ dprintf(4,"open file %s\n", DSP_FIRMWARE_PATH);
++
++ filp=filp_open(DSP_FIRMWARE_PATH
++ ,00,O_RDONLY);
++
++ if(filp ==NULL)
++ {
++ printk("Failed: Could not open DSP binary file\n");
++ return -1;
++ }
++
++ if (filp->f_op->read==NULL)
++ return -1; /* File(system) doesn't allow reads */
++
++ /* Now read bytes from postion "StartPos" */
++ filp->f_pos = 0;
++ oldfs = get_fs();
++ set_fs(KERNEL_DS);
++ bytesRead = filp->f_op->read(filp,ptr,imageLength,&filp->f_pos);
++
++ dprintf(4,"file length = %d\n", bytesRead);
++
++ set_fs(oldfs);
++
++ /* Close the file */
++ fput(filp);
++
++ return bytesRead;
++}
++
++unsigned int shim_read_overlay_page(void *ptr, unsigned int secOffset, unsigned int secLength)
++{
++ unsigned int bytesRead;
++ mm_segment_t oldfs;
++ struct file *filp;
++
++ dprintf(4,"shim_read_overlay_page\n");
++ //dprintf(4,"sec offset=%d, sec length =%d\n", secOffset, secLength);
++
++ filp=filp_open(DSP_FIRMWARE_PATH,00,O_RDONLY);
++ if(filp ==NULL)
++ {
++ printk("Failed: Could not open DSP binary file\n");
++ return -1;
++ }
++
++ if (filp->f_op->read==NULL)
++ return -1; /* File(system) doesn't allow reads */
++
++ /* Now read bytes from postion "StartPos" */
++
++ if(filp->f_op->llseek)
++ filp->f_op->llseek(filp,secOffset, 0);
++ oldfs = get_fs();
++ set_fs(KERNEL_DS);
++ filp->f_pos = secOffset;
++ bytesRead = filp->f_op->read(filp,ptr,secLength,&filp->f_pos);
++
++ set_fs(oldfs);
++ /* Close the file */
++ fput(filp);
++ return bytesRead;
++}
++
++int shim_osLoadDebugFWImage(unsigned char *ptr)
++{
++ return 0;
++}
++int shim_osStringCmp(const char *s1, const char *s2)
++{
++ return strcmp(s1, s2);
++}
++
++void *shim_osAllocateMemory(unsigned int size)
++{
++ return ((void *)kmalloc(size, GFP_KERNEL));
++}
++
++void *shim_osAllocateDmaMemory(unsigned int size)
++{
++ /*
++ int order;
++
++ order=1;
++ size=size/4096;
++ while(size >= 1)
++ {
++ order++;
++ size=size/2;
++ }
++
++ return ( (void *)__get_free_pages(GFP_ATOMIC, order));
++ */
++ //return ((void *)kmalloc(size, GFP_ATOMIC));
++ //return ((void *)kmalloc(size, GFP_KERNEL));
++ void *ptr;
++
++ ptr = kmalloc(size, GFP_ATOMIC);
++ if(ptr==NULL)
++ {
++ printk("failed atomic\n");
++ ptr = kmalloc(size, GFP_KERNEL);
++ if(ptr==NULL)
++ {
++ printk("failed kernel\n");
++ ptr = kmalloc(size, GFP_KERNEL|GFP_DMA);
++ }
++ }
++ printk("size=%d\n", size);
++ return ptr;
++
++}
++
++
++void shim_osFreeMemory(void *ptr, unsigned int size)
++{
++
++ kfree(ptr);
++}
++
++void shim_osFreeDmaMemory(void *ptr, unsigned int size)
++{
++/*
++ int order;
++
++ order=1;
++ size=size/4096;
++ while(size >=1)
++ {
++ order++;
++ size=size/2;
++ }
++ free_pages(ptr, order);
++*/
++ kfree(ptr);
++}
++
++void *shim_osAllocateVMemory(unsigned int size)
++{
++
++ return ((void *)vmalloc(size));
++}
++
++void shim_osFreeVMemory(void *ptr, unsigned int size)
++{
++ vfree(ptr);
++}
++
++void shim_osMoveMemory(char *dst, char *src, unsigned int numBytes)
++{
++ memcpy(dst, src, numBytes);
++}
++
++void shim_osZeroMemory(char *dst, unsigned int numBytes)
++{
++ memset(dst, 0, numBytes);
++}
++
++void shim_osWriteBackCache(void *addr, unsigned int size)
++{
++ unsigned int i,Size=(((unsigned int)addr)&0xf)+size;
++
++ for (i=0;i<Size;i+=16,addr+=16)
++ {
++ __asm__(" .set mips3 ");
++ __asm__(" cache 25, (%0)" : : "r" (addr));
++ __asm__(" .set mips0 ");
++ }
++}
++
++void shim_osInvalidateCache(void *addr, unsigned int size)
++{
++ unsigned int i,Size=(((unsigned int)addr)&0xf)+size;
++
++ for (i=0;i<Size;i+=16,addr+=16)
++ {
++ __asm__(" .set mips3 ");
++ __asm__("cache 17, (%0)" : : "r" (addr));
++ __asm__(" .set mips0 ");
++ }
++}
++
++void shim_osClockWait(int val)
++{
++ unsigned int chkvalue;
++ chkvalue=val/64;
++
++ if(chkvalue > 1000)
++ {
++ mdelay(chkvalue/1000);
++ return;
++ }
++ else
++ udelay(val/64);
++} /* end of cwait() */
++
++unsigned int shim_osClockTick(int val)
++{
++ return jiffies;
++}
++
++int flags;
++spinlock_t shimLock;
++
++void shim_osCriticalEnter(void)
++{
++ spin_lock_irqsave(&shimLock, flags);
++
++}
++
++
++void shim_osCriticalExit(void)
++{
++ spin_unlock_irqrestore(&shimLock, flags);
++}
++
++
++int tn7dsl_proc_stats(char* buf, char **start, off_t offset, int count,
++ int *eof, void *data)
++{
++
++ int len = 0;
++ int limit = count - 80;
++ int F4count, F5count;
++
++
++ /* Read Ax5 Stats */
++ dslhal_api_gatherStatistics(pIhw);
++
++ if(len<=limit)
++ len += sprintf(buf+len, "\nAR7 DSL Modem Statistics:\n");
++ if(len<=limit)
++ len += sprintf(buf+len, "--------------------------------\n");
++ /* us and ds Connection Rates */
++ if(len<=limit)
++ len += sprintf(buf+len, "[DSL Modem Stats]\n");
++
++
++ if(len<=limit)
++ {
++ if(pIhw->lConnected != 1)
++ {
++ pIhw->AppData.USConRate = 0;
++ pIhw->AppData.DSConRate = 0;
++ }
++ len += sprintf(buf+len, "\tUS Connection Rate:\t%u\tDS Connection Rate:\t%u\n",
++ (unsigned int)pIhw->AppData.USConRate,
++ (unsigned int)pIhw->AppData.DSConRate );
++ }
++ if(len<=limit)
++ len += sprintf(buf+len, "\tDS Line Attenuation:\t%u\tDS Margin:\t\t%u\n",
++ (unsigned int)pIhw->AppData.dsLineAttn/2,
++ (unsigned int)pIhw->AppData.dsMargin/2 );
++ if(len<=limit)
++ len += sprintf(buf+len, "\tUS Line Attenuation:\t%u\tUS Margin:\t\t%u\n",
++ (unsigned int)pIhw->AppData.usLineAttn,
++ (unsigned int)pIhw->AppData.usMargin );
++ if(len<=limit)
++ len += sprintf(buf+len, "\tUS Payload :\t\t%u\tDS Payload:\t\t%u\n",
++ ((unsigned int)pIhw->AppData.usAtm_count[0] + (unsigned int)pIhw->AppData.usAtm_count[1])*48,
++ ((unsigned int)pIhw->AppData.dsGood_count[0] + (unsigned int)pIhw->AppData.dsGood_count[1])*48);
++ /* Superframe Count */
++ if(len<=limit)
++ len += sprintf(buf+len, "\tUS Superframe Cnt :\t%u\tDS Superframe Cnt:\t%u\n",
++ (unsigned int)pIhw->AppData.usSuperFrmCnt,
++ (unsigned int)pIhw->AppData.dsSuperFrmCnt );
++
++ /* US and DS power */
++ if(len<=limit)
++ len += sprintf(buf+len, "\tUS Transmit Power :\t%u\tDS Transmit Power:\t%u\n",
++ (unsigned int)pIhw->AppData.usTxPower/256,
++ (unsigned int)pIhw->AppData.dsTxPower/256 );
++ /* DSL Stats Errors*/
++ if(len<=limit)
++ len += sprintf(buf+len, "\tLOS errors:\t\t%u\tSEF errors:\t\t%u\n",
++ (unsigned int)pIhw->AppData.LOS_errors,
++ (unsigned int)pIhw->AppData.SEF_errors );
++ if(len<=limit)
++ len += sprintf(buf+len, "\tFrame mode:\t\t%u\tMax Frame mode:\t\t%u\n",
++ (unsigned int)pIhw->AppData.FrmMode,
++ (unsigned int)pIhw->AppData.MaxFrmMode );
++ if(len<=limit)
++ len += sprintf(buf+len, "\tTrained Path:\t\t%u\tUS Peak Cell Rate:\t%u\n",
++ (unsigned int)pIhw->AppData.TrainedPath,
++ (unsigned int)pIhw->AppData.USConRate*1000/8/53 );
++ if(len<=limit)
++ len += sprintf(buf+len, "\tTrained Mode:\t\t%u\tSelected Mode:\t\t%u\n",
++ (unsigned int)pIhw->AppData.TrainedMode, (unsigned int)pIhw->AppData.StdMode );
++
++ if(len<=limit)
++ len += sprintf(buf+len, "\tATUC Vendor ID:\t%u\tATUC Revision:\t\t%u\n",
++ (unsigned int)pIhw->AppData.atucVendorId, pIhw->AppData.atucRevisionNum);
++ if(len<=limit)
++ len += sprintf(buf+len, "\tHybrid Selected:\t%u\n",
++ (unsigned int)pIhw->AppData.currentHybridNum);
++
++ /* Upstream Interleaved Errors */
++ if(len<=limit)
++ len += sprintf(buf+len, "\n\t[Upstream (TX) Interleave path]\n");
++ if(len<=limit)
++ len += sprintf(buf+len, "\tCRC: \t%u\tFEC: \t%u\tNCD: \t%u\n",
++ (unsigned int)pIhw->AppData.usICRC_errors,
++ (unsigned int)pIhw->AppData.usIFEC_errors,
++ (unsigned int)pIhw->AppData.usINCD_error);
++ if(len<=limit)
++ len += sprintf(buf+len, "\tLCD: \t%u\tHEC: \t%u\n",
++ (unsigned int)pIhw->AppData.usILCD_errors,
++ (unsigned int)pIhw->AppData.usIHEC_errors);
++ /* Downstream Interleaved Errors */
++ if(len<=limit)
++ len += sprintf(buf+len, "\n\t[Downstream (RX) Interleave path]\n");
++ if(len<=limit)
++ len += sprintf(buf+len, "\tCRC: \t%u\tFEC: \t%u\tNCD: \t%u\n",
++ (unsigned int)pIhw->AppData.dsICRC_errors,
++ (unsigned int)pIhw->AppData.dsIFEC_errors,
++ (unsigned int)pIhw->AppData.dsINCD_error);
++ if(len<=limit)
++ len += sprintf(buf+len, "\tLCD: \t%u\tHEC: \t%u\n",
++ (unsigned int)pIhw->AppData.dsILCD_errors,
++ (unsigned int)pIhw->AppData.dsIHEC_errors);
++ /* Upstream Fast Errors */
++ if(len<=limit)
++ len += sprintf(buf+len, "\n\t[Upstream (TX) Fast path]\n");
++ if(len<=limit)
++ len += sprintf(buf+len, "\tCRC: \t%u\tFEC: \t%u\tNCD: \t%u\n",
++ (unsigned int)pIhw->AppData.usFCRC_errors,
++ (unsigned int)pIhw->AppData.usFFEC_errors,
++ (unsigned int)pIhw->AppData.usFNCD_error);
++ if(len<=limit)
++ len += sprintf(buf+len, "\tLCD: \t%u\tHEC: \t%u\n",
++ (unsigned int)pIhw->AppData.usFLCD_errors,
++ (unsigned int)pIhw->AppData.usFHEC_errors);
++ /* Downstream Fast Errors */
++ if(len<=limit)
++ len += sprintf(buf+len, "\n\t[Downstream (RX) Fast path]\n");
++ if(len<=limit)
++ len += sprintf(buf+len, "\tCRC: \t%u\tFEC: \t%u\tNCD: \t%u\n",
++ (unsigned int)pIhw->AppData.dsFCRC_errors,
++ (unsigned int)pIhw->AppData.dsFFEC_errors,
++ (unsigned int)pIhw->AppData.dsFNCD_error);
++ if(len<=limit)
++ len += sprintf(buf+len, "\tLCD: \t%u\tHEC: \t%u\n",
++ (unsigned int)pIhw->AppData.dsFLCD_errors,
++ (unsigned int)pIhw->AppData.dsFHEC_errors);
++ /* ATM stats upstream */
++ if(len<=limit)
++ len += sprintf(buf+len, "\n[ATM Stats]");
++ if(len<=limit)
++ len += sprintf(buf+len, "\n\t[Upstream/TX]\n");
++ if(len<=limit)
++ len += sprintf(buf+len, "\tGood Cell Cnt:\t%u\n\tIdle Cell Cnt:\t%u\n\n",
++ (unsigned int)pIhw->AppData.usAtm_count[0] + (unsigned int)pIhw->AppData.usAtm_count[1],
++ (unsigned int)pIhw->AppData.usIdle_count[0] + (unsigned int)pIhw->AppData.usIdle_count[1]);
++ /* ATM stats downstream */
++ if(len<=limit)
++ len += sprintf(buf+len, "\n\t[Downstream/RX)]\n");
++ if(len<=limit)
++ len += sprintf(buf+len, "\tGood Cell Cnt:\t%u\n\tIdle Cell Cnt:\t%u\n\tBad Hec Cell Cnt:\t%u\n",
++ (unsigned int)pIhw->AppData.dsGood_count[0] + (unsigned int)pIhw->AppData.dsGood_count[1],
++ (unsigned int)pIhw->AppData.dsIdle_count[0] + (unsigned int)pIhw->AppData.dsIdle_count[1],
++ (unsigned int)pIhw->AppData.dsBadHec_count[0] + (unsigned int)pIhw->AppData.dsBadHec_count[1]);
++ if(len<=limit)
++ len += sprintf(buf+len, "\tOverflow Dropped Cell Cnt:\t%u\n",
++ (unsigned int)pIhw->AppData.dsOVFDrop_count[0] + (unsigned int)pIhw->AppData.dsOVFDrop_count[1]);
++ tn7sar_get_stats(pIhw->pOsContext);
++ if(len<=limit)
++ len += sprintf(buf+len, "\n[SAR AAL5 Stats]\n");
++ if(len<=limit)
++ len += sprintf(buf+len, "\tTx PDU's:\t%u\n\tRx PDU's:\t%u\n",
++ sarStat.txPktCnt,
++ sarStat.rxPktCnt);
++ if(len<=limit)
++ len += sprintf(buf+len, "\tTx Total Bytes:\t%u\n\tRx Total Bytes:\t%u\n",
++ sarStat.txBytes,
++ sarStat.rxBytes);
++ if(len<=limit)
++ len += sprintf(buf+len, "\tTx Total Error Counts:\t%u\n\tRx Total Error Counts:\t%u\n\n",
++ sarStat.txErrors,
++ sarStat.rxErrors);
++
++ /* oam loopback info */
++ if(len<=limit)
++ len += sprintf(buf+len, "\n[OAM Stats]\n");
++
++ tn7sar_get_near_end_loopback_count(&F4count, &F5count);
++
++ if(len<=limit)
++ {
++ len += sprintf(buf+len, "\tNear End F5 Loop Back Count:\t%u\n\tNear End F4 Loop Back Count:\t%u\n\tFar End F5 Loop Back Count:\t%u\n\tFar End F4 Loop Back Count:\t%u\n",
++ F5count,
++ F4count,
++ oamFarLBCount[0] + oamFarLBCount[2],
++ oamFarLBCount[1] + oamFarLBCount[3]);
++ }
++ return len;
++}
++
++int
++tn7dsl_proc_modem(char* buf, char **start, off_t offset, int count,
++ int *eof, void *data)
++{
++
++ int len = 0;
++ int limit = count - 80;
++
++ char *state;
++ int tag;
++
++ tag= dslhal_api_pollTrainingStatus(pIhw);
++ tag = pIhw->AppData.bState;
++
++ switch(tag){
++ case 0: state = "ACTREQ"; break;
++ case 1: state = "QUIET1"; break;
++ case 2: state = "IDLE"; break;
++ case 3: state = "INIT"; break;
++ case 4: state = "RTDL"; break;
++ case 5: state = "SHOWTIME"; break;
++ default: state = "unknown"; break;
++ }
++
++ if(pIhw->lConnected == 1)
++ state = "SHOWTIME";
++ if(len<=limit)
++ len += sprintf(buf+len,"%s\n",state);
++
++ return len;
++}
++
++
++
++int tn7dsl_handle_interrupt(void)
++{
++ int intsrc;
++ unsigned char cMsgRa[6];
++ short margin;
++
++ dprintf(4, "tn7dsl_handle_dsl_interrupt()\n");
++ if(pIhw)
++ {
++ intsrc=dslhal_api_acknowledgeInterrupt(pIhw);
++ dslhal_api_handleTrainingInterrupt(pIhw, intsrc);
++
++ if(pIhw->lConnected == TC_SYNC)
++ {
++
++ if(dslInSync == 0)
++ {
++ printk("DSL in Sync\n");
++ tn7atm_device_connect_status(pIhw->pOsContext, 1);
++ dslhal_api_initStatistics(pIhw);
++ dslhal_api_gatherStatistics(pIhw);
++#ifdef CONFIG_LED_MODULE
++// led_operation(MOD_ADSL, DEF_ADSL_SYNC);
++ led_on = DEF_ADSL_SYNC;
++#endif
++ /* add auto margin retrain */
++ if(pIhw->AppData.TrainedMode < 5)
++ {
++ if(bMarginRetrainEnable && bMarginThConfig == 0)
++ {
++ dslhal_support_getCMsgsRa(pIhw, cMsgRa);
++ margin = *(unsigned short *)&cMsgRa[4];
++ margin = (margin >> 6) & 0x3f;
++ if(margin & 0x20) // highest bit is 1
++ {
++ margin = -(margin & 0x1f);
++ }
++
++ //printk("margin = %d, cmsg-ra = %02x %02x %02x %02x %02x %02x\n", margin, cMsgRa[0],cMsgRa[1],cMsgRa[2],cMsgRa[3],cMsgRa[4],cMsgRa[5]);
++ dslhal_api_setMarginThreshold(pIhw, margin*2); /* DSL margin is in 0.5db */
++ }
++ }
++
++ }
++ dslInSync = 1;
++ }
++ else
++ {
++ if(dslInSync == 1)
++ {
++ dslInSync = 0;
++ tn7atm_device_connect_status(pIhw->pOsContext, 0);
++ up(&adsl_sem_overlay);
++ printk("DSL out of syn\n");
++ }
++#ifdef CONFIG_LED_MODULE
++ if(pIhw->AppData.bState < RSTATE_INIT)
++ {
++ if(led_on != DEF_ADSL_IDLE)
++ {
++// led_operation(MOD_ADSL, DEF_ADSL_IDLE);
++ led_on = DEF_ADSL_IDLE;
++ }
++ }
++ else
++ {
++ if(led_on != DEF_ADSL_TRAINING)
++ {
++// led_operation(MOD_ADSL, DEF_ADSL_TRAINING);
++ led_on = DEF_ADSL_TRAINING;
++ }
++
++ }
++
++#endif
++
++ }
++ }
++ return 0;
++}
++
++
++int tn7dsl_get_dslhal_version(char *pVer)
++{
++ dslVer ver;
++
++ dslhal_api_getDslHalVersion(&ver);
++
++ memcpy(pVer,&ver,8);
++ return 0;
++}
++
++int tn7dsl_get_dsp_version(char *pVer)
++{
++ dspVer ver;
++ dslhal_api_getDspVersion(pIhw, &ver);
++ memcpy(pVer, &ver, 9);
++ return 0;
++}
++
++
++static int
++tn7dsl_get_modulation(void)
++{
++ char *ptr = NULL;
++
++ dprintf(4, "tn7dsl_get_modulation\n");
++ //printk("tn7dsl_get_modulation\n");
++ ptr = prom_getenv("modulation");
++
++ if (!ptr) {
++ //printk("modulation is not set in adam2 env\n");
++ //printk("Using multimode\n");
++ return 0;
++ }
++ printk("dsl modulation = %s\n", ptr);
++
++ tn7dsl_set_modulation(ptr);
++
++ return 0;
++}
++
++
++static int tn7dsl_set_dsl(void)
++{
++
++ char *ptr = NULL;
++ int value;
++ int i, offset[2]={4,11},oamFeature=0;
++ char tmp[4];
++ char dspVer[10];
++
++ // OAM Feature Configuration
++ dslhal_api_dspInterfaceRead(pIhw,(unsigned int)pIhw->pmainAddr, 2, (unsigned int *)&offset, (unsigned char *)&oamFeature, 4);
++ oamFeature |= dslhal_support_byteSwap32(0x0000000C);
++ dslhal_api_dspInterfaceWrite(pIhw,(unsigned int)pIhw->pmainAddr, 2, (unsigned int *)&offset, (unsigned char *)&oamFeature, 4);
++
++ // modulation
++ ptr = prom_getenv("modulation");
++ if (ptr)
++ {
++ printk("dsl modulation = %s\n", ptr);
++ tn7dsl_set_modulation(ptr);
++ }
++
++ // margin retrain
++ ptr = NULL;
++ ptr = prom_getenv("enable_margin_retrain");
++ if(ptr)
++ {
++ value = os_atoi(ptr);
++ if(value == 1)
++ {
++ dslhal_api_setMarginMonitorFlags(pIhw, 0, 1);
++ bMarginRetrainEnable = 1;
++ printk("enable showtime margin monitor.\n");
++ ptr = NULL;
++ ptr = prom_getenv("margin_threshold");
++ if(ptr)
++ {
++ value = os_atoi(ptr);
++ printk("Set margin threshold to %d x 0.5 db\n",value);
++ if(value >= 0)
++ {
++ dslhal_api_setMarginThreshold(pIhw, value);
++ bMarginThConfig=1;
++ }
++ }
++ }
++ }
++
++ // rate adapt
++ ptr = NULL;
++ ptr = prom_getenv("enable_rate_adapt");
++ if(ptr)
++ {
++ dslhal_api_setRateAdaptFlag(pIhw, os_atoi(ptr));
++ }
++
++ // trellis
++ ptr = NULL;
++ ptr = prom_getenv("enable_trellis");
++ if(ptr)
++ {
++ dslhal_api_setTrellisFlag(pIhw, os_atoi(ptr));
++ }
++
++ // maximum bits per carrier
++ ptr = NULL;
++ ptr = prom_getenv("maximum_bits_per_carrier");
++ if(ptr)
++ {
++ dslhal_api_setMaxBitsPerCarrier(pIhw, os_atoi(ptr));
++ }
++
++ // maximum interleave depth
++ ptr = NULL;
++ ptr = prom_getenv("maximum_interleave_depth");
++ if(ptr)
++ {
++ dslhal_api_setMaxInterleaverDepth(pIhw, os_atoi(ptr));
++ }
++
++ // inner and outer pairs
++ ptr = NULL;
++ ptr = prom_getenv("pair_selection");
++ if(ptr)
++ {
++ dslhal_api_selectInnerOuterPair(pIhw, os_atoi(ptr));
++ }
++
++ ptr = NULL;
++ ptr = prom_getenv("dgas_polarity");
++ if(ptr)
++ {
++ dslhal_api_configureDgaspLpr(pIhw, 1, 1);
++ dslhal_api_configureDgaspLpr(pIhw, 0, os_atoi(ptr));
++ }
++
++ ptr = NULL;
++ ptr = prom_getenv("los_alarm");
++ if(ptr)
++ {
++ dslhal_api_disableLosAlarm(pIhw, os_atoi(ptr));
++ }
++
++ ptr = NULL;
++ ptr = prom_getenv("eoc_vendor_id");
++ if(ptr)
++ {
++ for(i=0;i<8;i++)
++ {
++ tmp[0]=ptr[i*2];
++ tmp[1]=ptr[i*2+1];
++ tmp[2]=0;
++ EOCVendorID[i] = os_atoh(tmp);
++ //printk("tmp=%s--", tmp);
++ //printk("ID[%d]=0x%02x ", i, (unsigned char)EOCVendorID[i]);
++ }
++ tn7dsl_get_dsp_version(dspVer);
++ //printk("Annex =%d\n", dspVer[8]);
++ if(dspVer[8]==2) // annex b
++ {
++ //printk("EOCVendorID=%02x %02x %02x %02x %02x %02x %02x %02x\n", EOCVendorID[0], EOCVendorID[1], EOCVendorID[2], EOCVendorID[3],
++ // EOCVendorID[4], EOCVendorID[5], EOCVendorID[6], EOCVendorID[7]);
++ dslhal_api_setEocVendorId(pIhw, EOCVendorID);
++ }
++
++ }
++
++ return 0;
++}
++
++
++
++
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: static void tn7dsl_init(void)
++ *
++ * Description: This function initializes
++ * Ar7 DSL interface
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
++
++int tn7dsl_init(void *priv)
++{
++
++ printk("Initializing DSL interface\n");
++
++
++ /* start dsl */
++ if(dslhal_api_dslStartup(&pIhw) !=0 )
++ {
++ printk("DSL start failed.\n");
++ return -1;
++ }
++
++ // set dsl into overlay page reload mode
++ pIhw->bAutoRetrain = 1;
++
++ // set default training properties
++ tn7dsl_set_dsl();
++
++ pIhw->pOsContext = priv;
++
++ //start_kthread(tn7dsl_reload_overlay, &overlay_thread);
++
++ /*register dslss LED with led module */
++#ifdef CONFIG_LED_MODULE
++ tn7dsl_register_dslss_led();
++#endif
++
++
++ return 0; /* What do we return here? */
++}
++
++/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * Function: int avsar_exit(void)
++ *
++ * Description: Avalanche SAR exit function
++ *
++ *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
++
++void tn7dsl_exit (void)
++{
++
++ bshutdown = 1;
++#ifdef CONFIG_LED_MODULE
++#ifdef DEREGISTER_LED
++ //down(&adsl_sem_overlay);
++ deregister_led_drv(LED_NUM_1);
++ deregister_led_drv(LED_NUM_2);
++#else
++// led_operation(MOD_ADSL,DEF_ADSL_IDLE);
++#endif
++#endif
++ stop_kthread(&overlay_thread);
++ dslhal_api_dslShutdown(pIhw);
++
++}
++
++
++static int tn7dsl_process_oam_string(int *type, int *pvpi, int *pvci, int *pdelay)
++{
++ int i=1;
++ int j=0;
++ int vci, vpi;
++ char tmp[16];
++ int chan;
++ int tt;
++
++ while(j<8)
++ {
++ tmp[j] = mod_req[i];
++ //printk("tmp[%d]=%c, %d\n", j, tmp[j], tmp[j]);
++ if(tmp[j] == 0x50 || tmp[j] == 0x70)
++ break;
++ j++;
++ i++;
++ }
++
++ tmp[j] = 0;
++ vpi = os_atoi(tmp);
++
++ i++;
++ j=0;
++ while(j<8)
++ {
++ tmp[j] = mod_req[i];
++ //printk("tmp[%d]=%c, %d\n", j, tmp[j], tmp[j]);
++ if(tmp[j] == 0x43 || tmp[j] == 0x63)
++ break;
++
++ j++;
++ i++;
++ }
++
++ vci = os_atoi(tmp);
++
++ if(vci==0) // f4 oam
++ *type = 1;
++ else
++ *type = 0;
++
++
++ tt=5000;
++ i++;
++ j=0;
++ tmp[j] = mod_req[i];
++ if(tmp[j]==0x44 || tmp[j]==0x64)
++ {
++ i++;
++ while(j<8)
++ {
++ tmp[j] = mod_req[i];
++
++ //printk("tmp[%d]=%c, %d\n", j, tmp[j], tmp[j]);
++ if(tmp[j] == 0x54 || tmp[j] == 0x74)
++ break;
++
++ j++;
++ i++;
++ }
++ tt = os_atoi(tmp);
++ }
++
++ chan = tn7atm_lut_find(vpi, vci);
++
++ *pvci=vci;
++ *pvpi=vpi;
++ *pdelay =tt;
++ dprintf(2, "oam chan=%d, type =%d\n", chan, *type);
++
++ return chan;
++}
++
++static void tn7dsl_dump_memory(void)
++{
++ unsigned int *pUi;
++ int i=1;
++ int j=0;
++ int addr, len;
++ char tmp[16];
++
++
++ while(j<8)
++ {
++ tmp[j] = mod_req[i];
++ j++;
++ i++;
++ }
++
++ tmp[j] = 0;
++
++ addr = os_atoh(tmp);
++
++ printk("start dump address =0x%x\n", addr);
++ pUi = (unsigned int *)addr;
++ i++;
++ j=0;
++ while(j<8)
++ {
++ tmp[j] = mod_req[i];
++ //printk("tmp[%d]=%c, %d\n", j, tmp[j], tmp[j]);
++ if(tmp[j] == 0x43 || tmp[j] == 0x63)
++ break;
++
++ j++;
++ i++;
++ }
++
++ len = os_atoi(tmp);
++ j=0;
++ for(i=0; i<len; i++)
++ {
++ if(j==0)
++ printk("0x%08x: ", (unsigned int)pUi);
++ printk("%08x ", *pUi);
++ pUi++;
++ j++;
++ if(j==4)
++ {
++ printk("\n");
++ j=0;
++ }
++ }
++
++}
++
++
++
++static int dslmod_sysctl(ctl_table *ctl, int write, struct file * filp,
++ void *buffer, size_t *lenp)
++{
++ char *ptr;
++ int ret, len = 0;
++ int chan;
++ int type;
++ int vpi,vci,timeout;
++
++ if (!*lenp || (filp->f_pos && !write)) {
++ *lenp = 0;
++ return 0;
++ }
++ /* DSL MODULATION is changed */
++ if(write)
++ {
++ ret = proc_dostring(ctl, write, filp, buffer, lenp);
++
++ switch (ctl->ctl_name)
++ {
++ case DEV_DSLMOD:
++ ptr = strpbrk(info, " \t");
++ strcpy(mod_req, info);
++
++ /* parse the string to determine the action */
++ if(mod_req[0] == 0x45 || mod_req[0] == 0x65 ) // 'e', or 'E' f5 end to end
++ {
++ chan = tn7dsl_process_oam_string(&type, &vpi, &vci, &timeout);
++ tn7sar_oam_generation(pIhw->pOsContext, chan, type, vpi, vci, timeout);
++ }
++ else if(mod_req[0] == 0x53 || mod_req[0] == 0x73 ) // 's', or 'S' f5 seg to seg
++ {
++ chan=tn7dsl_process_oam_string(&type, &vpi, &vci,&timeout);
++ type = type | (1<<1);
++ tn7sar_oam_generation(pIhw->pOsContext, chan, type, vpi, vci,timeout);
++ }
++ //debug only. Dump memory
++ else if(mod_req[0] == 0x44 || mod_req[0] == 0x64 ) // 'd' or 'D'
++ tn7dsl_dump_memory();
++ else
++ tn7dsl_chng_modulation(info);
++ break;
++ }
++ }
++ else
++ {
++ len += sprintf(info+len, mod_req);
++ ret = proc_dostring(ctl, write, filp, buffer, lenp);
++ }
++ return ret;
++}
++
++
++ctl_table dslmod_table[] = {
++ {DEV_DSLMOD, "dslmod", info, DSL_MOD_SIZE, 0644, NULL, &dslmod_sysctl},
++ {0}
++ };
++
++/* Make sure that /proc/sys/dev is there */
++ctl_table dslmod_root_table[] = {
++#ifdef CONFIG_PROC_FS
++ {CTL_DEV, "dev", NULL, 0, 0555, dslmod_table},
++#endif /* CONFIG_PROC_FS */
++ {0}
++ };
++
++static struct ctl_table_header *dslmod_sysctl_header;
++
++void tn7dsl_dslmod_sysctl_register(void)
++{
++ static int initialized;
++
++ if (initialized == 1)
++ return;
++
++ dslmod_sysctl_header = register_sysctl_table(dslmod_root_table, 1);
++ dslmod_root_table->child->de->owner = THIS_MODULE;
++
++ /* set the defaults */
++ info[0] = 0;
++
++ initialized = 1;
++}
++
++void tn7dsl_dslmod_sysctl_unregister(void)
++{
++ unregister_sysctl_table(dslmod_sysctl_header);
++}
++
++static void
++tn7dsl_set_modulation(void* data)
++{
++ dprintf(4,"tn7dsl_set_modulation\n");
++
++ if(!strcmp(data, "T1413"))
++ {
++ printk("retraining in T1413 mode\n");
++ dslhal_api_setTrainingMode(pIhw, T1413_MODE);
++ return;
++ }
++ if(!strcmp(data, "GDMT"))
++ {
++ dslhal_api_setTrainingMode(pIhw, GDMT_MODE);
++ return;
++ }
++ if(!strcmp(data, "GLITE"))
++ {
++ dslhal_api_setTrainingMode(pIhw, GLITE_MODE);
++ return;
++ }
++ if(!strcmp(data, "MMODE"))
++ {
++ dslhal_api_setTrainingMode(pIhw, MULTI_MODE);
++ return;
++ }
++ if(!strcmp(data, "NMODE"))
++ {
++ dslhal_api_setTrainingMode(pIhw, NO_MODE);
++ return;
++ }
++
++ return;
++}
++
++
++/* Codes added for compiling tiadiag.o for Analog Diagnostic tests */
++#ifdef ADIAG
++
++enum
++{
++ HOST_ACTREQ, // Send R-ACKREQ and monitor for C-ACKx
++ HOST_QUIET, // Sit quietly doing nothing for about 60 seconds, DEFAULT STATE; R_IDLE
++ HOST_XMITBITSWAP, // Perform upstream bitswap - FOR INTERNAL USE ONLY
++ HOST_RCVBITSWAP, // Perform downstream bitswap - FOR INTERNAL USE ONLY
++ HOST_RTDLPKT, // Send a remote download packet - FOR INTERNAL USE ONLY
++ HOST_CHANGELED, // Read the LED settings and change accordingly
++ HOST_IDLE, // Sit quiet
++ HOST_REVERBTEST, // Generate REVERB for manufacturing test
++ HOST_CAGCTEST, // Set coarse receive gain for manufacturing test
++ HOST_DGASP, // send Dying Gasp messages through EOC channel
++ HOST_GHSREQ, // G.hs - FOR INTERNAL USE ONLY
++ HOST_GHSMSG, // G.hs - FOR INTERNAL USE ONLY
++ HOST_GHS_SENDGALF, // G.hs - FOR INTERNAL USE ONLY
++ HOST_GHSEXIT, // G.hs - FOR INTERNAL USE ONLY
++ HOST_GHSMSG1, // G.hs - FOR INTERNAL USE ONLY
++ HOST_HYBRID, // Enable/Disable automatic hybrid switch
++ HOST_RJ11SELECT, // RJ11 inner/outer pair select
++ HOST_DIGITAL_MEM, // Digital Diags: run external memory tests
++ HOST_TXREVERB, // AFE Diags: TX path Reverb
++ HOST_TXMEDLEY, // AFE Diags: TX path Medley
++ HOST_RXNOISEPOWER, // AFE Diags: RX noise power
++ HOST_ECPOWER, // AFE Diags: RX eco power
++ HOST_ALL_ADIAG, // AFE Diags: all major analog diagnostic modes. Host is responsible to initiate each diagnostic sessions
++ HOST_USER_ADIAG, // AFE Diags: Host fills in analog diagnostic input data structure as specified and requests DSP to perform measurements as specified
++ HOST_QUIT_ADIAG, // AFE Diags: Host requests DSP to quit current diagnostic session. This is used for stopping the transmit REVERB/MEDLEY
++ HOST_NO_CMD, // All others - G.hs - FOR INTERNAL USE ONLY
++ HOST_DSLSS_SHUTDOWN, // Host initiated DSLSS shutdown message
++ HOST_SET_GENERIC, // Set generic CO profile
++ HOST_UNDO_GENERIC // Set profile previous to Generic
++};
++
++enum
++{
++ DSP_IDLE, // R_IDLE state entered
++ DSP_ACTMON, // R_ACTMON state entered
++ DSP_TRAIN, // R_TRAIN state entered
++ DSP_ACTIVE, // R_ACTIVE state entered
++ DSP_XMITBITSWAP, // Upstream bitswap complete - FOR INTERNAL USE ONLY
++ DSP_RCVBITSWAP, // Downstream bitswap complete - FOR INTERNAL USE ONLY
++ DSP_RTDL, // R_RTDL state entered - FOR INTERNAL USE ONLY
++ DSP_RRTDLPKT, // RTDL packet received - FOR INTERNAL USE ONLY
++ DSP_XRTDLPKT, // RTDL packet transmitted - FOR INTERNAL USE ONLY
++ DSP_ERROR, // Command rejected, wrong state for this command
++ DSP_REVERBTEST, // Manufacturing REVERB test mode entered
++ DSP_CAGCTEST, // Manufacturing receive gain test done
++ DSP_OVERLAY_START, // Notify host that page overlay has started - overlay number indicated by "tag"
++ DSP_OVERLAY_END, // Notify host that page overlay has ended - overlay number indicated by "tag"
++ DSP_CRATES1, // CRATES1 message is valid and should be copied to host memory now
++ DSP_SNR, // SNR calculations are ready and should be copied to host memory now
++ DSP_GHSMSG, // G.hs - FOR INTERNAL USE ONLY
++ DSP_RCVBITSWAP_TIMEOUT, // Acknowledge Message was not received within ~500 msec (26 Superframes).
++ DSP_ATM_TC_SYNC, // Indicates true TC sync on both the upstream and downstream. Phy layer ready for data xfer.
++ DSP_ATM_NO_TC_SYNC, // Indicates loss of sync on phy layer on either US or DS.
++ DSP_HYBRID, // DSP completed hybrid switch
++ DSP_RJ11SELECT, // DSP completed RJ11 inner/outer pair select
++ DSP_INVALID_CMD, // Manufacturing (Digital and AFE) diags: CMD received not recognized
++ DSP_TEST_PASSED, // Manufacturing diags: test passed
++ DSP_TEST_FAILED, // Manufacturing diags: test failed
++ DSP_TXREVERB, // Manufacturing AFE diags: Response to HOST_TXREVERB
++ DSP_TXMEDLEY, // Manufacturing AFE diags: Response to HOST_TXMEDLEY
++ DSP_RXNOISEPOWER, // Manufacturing AFE diags: Response to HOST_RXNOISEPOWER
++ DSP_ECPOWER, // Manufacturing AFE diags: Response to HOST_ECPOWER
++ DSP_ALL_ADIAG, // Manufacturing AFE diags: Response to HOST_ALL_ADIAG
++ DSP_USER_ADIAG, // Manufacturing AFE diags: Response to HOST_USER_ADIAG
++ DSP_QUIT_ADIAG, // Manufacturing AFE diags: Response to HOST_QUIT_ADIAG
++ DSP_DGASP // DSP Message to indicate dying gasp
++};
++
++static unsigned char analogNoTonesTestArray[64]=
++ {
++ 0,0,0,0,0,0,0,0, // Tones 01-08
++ 0,0,0,0,0,0,0,0, // Tones 09-16
++ 0,0,0,0,0,0,0,0, // Tones 17-24
++ 0,0,0,0,0,0,0,0, // Tones 25-32
++ 0,0,0,0,0,0,0,0, // Tones 33-40
++ 0,0,0,0,0,0,0,0, // Tones 41-48
++ 0,0,0,0,0,0,0,0, // Tones 49-56
++ 0,0,0,0,0,0,0,0 // Tones 57-64
++ };
++
++static unsigned char analogAllTonesTestArray[64]=
++ {
++ 1,1,1,1,1,1,1,1, // Tones 01-08
++ 1,1,1,1,1,1,1,1, // Tones 09-16
++ 1,1,1,1,1,1,1,1, // Tones 17-24
++ 1,1,1,1,1,1,1,1, // Tones 25-32
++ 1,1,1,1,1,1,1,1, // Tones 33-40
++ 1,1,1,1,1,1,1,1, // Tones 41-48
++ 1,1,1,1,1,1,1,1, // Tones 49-56
++ 1,1,1,1,1,1,1,1 // Tones 57-64
++ };
++
++static unsigned char analogEvenTonesTestArray[64]=
++ {
++ 0,1,0,1,0,1,0,1, // Tones 01-08
++ 0,1,0,1,0,1,0,1, // Tones 09-16
++ 0,1,0,1,0,1,0,1, // Tones 17-24
++ 0,1,0,1,0,1,0,1, // Tones 25-32
++ 0,1,0,1,0,1,0,1, // Tones 33-40
++ 0,1,0,1,0,1,0,1, // Tones 41-48
++ 0,1,0,1,0,1,0,1, // Tones 49-56
++ 0,1,0,1,0,1,0,1 // Tones 57-64
++ };
++
++static unsigned char analogOddTonesTestArray[64]=
++ {
++ 1,0,1,0,1,0,1,0, // Tones 01-08
++ 1,0,1,0,1,0,1,0, // Tones 09-16
++ 1,0,1,0,1,0,1,0, // Tones 17-24
++ 1,0,1,0,1,0,1,0, // Tones 25-32
++ 1,0,1,0,1,0,1,0, // Tones 33-40
++ 1,0,1,0,1,0,1,0, // Tones 41-48
++ 1,0,1,0,1,0,1,0, // Tones 49-56
++ 1,0,1,0,1,0,1,0 // Tones 57-64
++ };
++
++unsigned int shim_osGetCpuFrequency(void)
++{
++ return 150;
++}
++
++static void tn7dsl_adiag(int Test, unsigned char *missingTones)
++{
++ int rc,cmd, tag;
++
++ rc = dslhal_diags_anlg_setMissingTones(pIhw,missingTones);
++ if(rc)
++ {
++ printk(" failed to set Missing town\n");
++ return;
++ }
++
++/*********** Start the actual test **********************/
++
++ if(Test==0)
++ {
++ printk("TX REVERB Test\n");
++ rc = dslhal_support_writeHostMailbox(pIhw, HOST_TXREVERB, 0, 0, 0);
++ if (rc)
++ {
++ printk("HOST_TXREVERB failed\n");
++ return;
++ }
++
++ }
++ if(Test==1)
++ {
++ dprintf(0,"TX MEDLEY Test\n");
++ rc = dslhal_support_writeHostMailbox(pIhw, HOST_TXMEDLEY, 0, 0, 0);
++ if (rc)
++ return;
++ }
++ dprintf(4,"dslhal_diags_anlg_testA() done\n");
++ return;
++}
++
++
++static void tn7dsl_diagnostic_test(char *data)
++{
++ if(!strcmp(data, "ADIAGRALL"))
++ {
++ printk("TX Reverb All tone\n");
++ tn7dsl_adiag(0,analogAllTonesTestArray);
++ return;
++ }
++ if(!strcmp(data, "ADIAGRNONE"))
++ {
++ printk("TX Reverb No tone\n");
++ tn7dsl_adiag(0,analogNoTonesTestArray);
++ return;
++ }
++ if(!strcmp(data, "ADIAGREVEN"))
++ {
++ printk("TX Reverb Even tone\n");
++ tn7dsl_adiag(0,analogEvenTonesTestArray);
++ return;
++ }
++ if(!strcmp(data, "ADIAGRODD"))
++ {
++ printk("TX Reverb Odd tone\n");
++ tn7dsl_adiag(0,analogOddTonesTestArray);
++ return;
++ }
++ if(!strcmp(data, "ADIAGMALL"))
++ {
++ printk("TX Mdelay All tone\n");
++ tn7dsl_adiag(1,analogAllTonesTestArray);
++ return;
++ }
++ if(!strcmp(data, "ADIAGMNONE"))
++ {
++ printk("TX Mdelay No tone\n");
++ tn7dsl_adiag(1,analogNoTonesTestArray);
++ return;
++ }
++ if(!strcmp(data, "ADIAGMEVEN"))
++ {
++ printk("TX Mdelay Even tone\n");
++ tn7dsl_adiag(1,analogEvenTonesTestArray);
++ return;
++ }
++ if(!strcmp(data, "ADIAGMODD"))
++ {
++ printk("TX Mdelay Odd tone\n");
++ tn7dsl_adiag(1,analogOddTonesTestArray);
++ return;
++ }
++ if(!strcmp(data, "ADIAGQUIET"))
++ {
++ dslhal_api_sendIdle(pIhw);
++ return;
++ }
++ if(!strncmp(data, "ADIAGRN", 7))
++ {
++ char tones[64], tmp[4];
++ int nth, i;
++
++ tmp[0]=data[7];
++ tmp[1]=data[8];
++ tmp[2]=data[9];
++
++ nth = os_atoi(tmp);
++
++ for(i=0;i<64;i++)
++ {
++ if(((i+1)% nth)==0)
++ {
++ tones[i]=0;
++ }
++ else
++ {
++ tones[i]=1;
++ }
++ }
++ printk("TX Reverb with %dth tones missing.\n", nth);
++ tn7dsl_adiag(0,tones);
++ return;
++ }
++ if(!strncmp(data, "ADIAGMN", 7))
++ {
++ char tones[64], tmp[4];
++ int nth, i;
++
++ tmp[0]=data[7];
++ tmp[1]=data[8];
++ tmp[2]=data[9];
++ nth = os_atoi(tmp);
++
++ for(i=0;i<64;i++)
++ {
++ if(((i+1)% nth)==0)
++ {
++ tones[i]=0;
++ }
++ else
++ {
++ tones[i]=1;
++ }
++ }
++ printk("TX Mdelay with %dth tones missing.\n", nth);
++ tn7dsl_adiag(1,tones);
++ return;
++ }
++
++
++}
++
++#endif
++
++static void
++tn7dsl_chng_modulation(void* data)
++{
++ //printk("DSL Modem Retraining\n");
++
++ if(!strcmp(data, "T1413"))
++ {
++ printk("retraining in T1413 mode\n");
++ dslhal_api_setTrainingMode(pIhw, T1413_MODE);
++ dslhal_api_sendQuiet(pIhw);
++ return;
++ }
++ if(!strcmp(data, "GDMT"))
++ {
++ dslhal_api_setTrainingMode(pIhw, GDMT_MODE);
++ dslhal_api_sendQuiet(pIhw);
++ return;
++ }
++ if(!strcmp(data, "GLITE"))
++ {
++ dslhal_api_setTrainingMode(pIhw, GLITE_MODE);
++ dslhal_api_sendQuiet(pIhw);
++ return;
++ }
++ if(!strcmp(data, "MMODE"))
++ {
++ dslhal_api_setTrainingMode(pIhw, MULTI_MODE);
++ dslhal_api_sendQuiet(pIhw);
++ return;
++ }
++ if(!strcmp(data, "NMODE"))
++ {
++ dslhal_api_setTrainingMode(pIhw, NO_MODE);
++ dslhal_api_sendQuiet(pIhw);
++ return;
++ }
++
++#ifdef ADIAG
++ tn7dsl_diagnostic_test(data);
++#endif
++
++
++ return;
++}
++
++#ifdef CONFIG_LED_MODULE
++static void tn7dsl_led_on(unsigned long parm)
++{
++ dslhal_api_configureLed(pIhw,parm, 0);
++}
++
++
++static void tn7dsl_led_off(unsigned long parm)
++{
++ dslhal_api_configureLed(pIhw,parm, 1);
++}
++
++static void tn7dsl_led_init(unsigned long parm)
++{
++ dslhal_api_configureLed(pIhw,parm, 2);
++}
++#endif
++
++static void tn7dsl_register_dslss_led(void)
++{
++#ifdef CONFIG_LED_MODULE
++
++ // register led0 with led module
++ ledreg[0].param = 0;
++ ledreg[0].init = (void *)tn7dsl_led_init;
++ ledreg[0].onfunc = (void *)tn7dsl_led_on;
++ ledreg[0].offfunc = (void *)tn7dsl_led_off;
++ register_led_drv(LED_NUM_1, &ledreg[0]);
++
++ // register led1 output with led module
++ ledreg[1].param = 1;
++ ledreg[1].init = (void *)tn7dsl_led_init;
++ ledreg[1].onfunc = (void *)tn7dsl_led_on;
++ ledreg[1].offfunc = (void *)tn7dsl_led_off;
++ register_led_drv(LED_NUM_2, &ledreg[1]);
++#endif
++}
++
++static int tn7dsl_reload_overlay(void)
++{
++ int overlayFlag;
++ spinlock_t overlayLock;
++
++ init_kthread(&overlay_thread, "adsl");
++ down(&adsl_sem_overlay);
++ while(1)
++ {
++ mdelay(500);
++ if(pIhw->lConnected == 0)
++ {
++ spin_lock_irqsave(&overlayLock, overlayFlag);
++ dslhal_support_restoreTrainingInfo(pIhw);
++ spin_unlock_irqrestore(&overlayLock, overlayFlag);
++ }
++ down(&adsl_sem_overlay);
++ }
++ return 0;
++}
++
++
++
++
+diff -urN linux.old/drivers/atm/sangam_atm/tn7sar.c linux.dev/drivers/atm/sangam_atm/tn7sar.c
+--- linux.old/drivers/atm/sangam_atm/tn7sar.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/tn7sar.c 2005-08-23 04:46:50.110841720 +0200
+@@ -0,0 +1,1376 @@
++/******************************************************************************
++ * FILE PURPOSE: OS files for CPSAR
++ ******************************************************************************
++ * FILE NAME: tn7sar.c
++ *
++ * DESCRIPTION: This file contains source for required os files for CPSAR
++ *
++ * (C) Copyright 2002, Texas Instruments Inc
++ *
++ *
++ * Revision History:
++ * 0/11/02 Zhicheng Tang, created.
++ *
++ *******************************************************************************/
++
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/atmdev.h>
++#include <linux/delay.h>
++#include <linux/spinlock.h>
++#include <linux/smp_lock.h>
++#include <asm/io.h>
++#include <asm/mips-boards/prom.h>
++#include <linux/proc_fs.h>
++#include <linux/string.h>
++#include <linux/ctype.h>
++
++
++#define _CPHAL_AAL5
++#define _CPHAL_SAR
++#define _CPHAL_HAL
++typedef void OS_PRIVATE;
++typedef void OS_DEVICE;
++typedef void OS_SENDINFO;
++typedef void OS_RECEIVEINFO;
++typedef void OS_SETUP;
++
++#include "cpswhal_cpsar.h"
++#include "tn7atm.h"
++#include "tn7api.h"
++
++
++/* PDSP Firmware files */
++#include "tnetd7300_sar_firm.h"
++
++
++enum
++{
++ PACKET_TYPE_AAL5,
++ PACKET_TYPE_NULL,
++ PACKET_TYPE_OAM,
++ PACKET_TYPE_TRANS,
++ PACKET_TYPE_AAL2
++}PACKET_TYPE;
++
++enum
++{
++ OAM_PING_FAILED,
++ OAM_PING_SUCCESS,
++ OAM_PING_PENDING,
++ OAM_PING_NOT_STARTED
++}OAM_PING;
++
++/* PDSP OAM General Purpose Registers (@todo: These need to be used in the HAL!) */
++
++#define SAR_PDSP_HOST_OAM_CONFIG_REG_ADDR 0xa3000020
++#define SAR_PDSP_OAM_CORR_REG_ADDR 0xa3000024
++#define SAR_PDSP_OAM_LB_RESULT_REG_ADDR 0xa3000028
++#define SAR_PDSP_OAM_F5LB_COUNT_REG_ADDR 0xa300002c
++#define SAR_PDSP_OAM_F4LB_COUNT_REG_ADDR 0xa3000030
++
++#define SAR_FREQUNCY 50000000
++
++#define AAL5_PARM "id=aal5, base = 0x03000000, offset = 0, int_line=15, ch0=[RxBufSize=1522; RxNumBuffers = 32; RxServiceMax = 50; TxServiceMax=50; TxNumBuffers=32; CpcsUU=0x5aa5; TxVc_CellRate=0x3000; TxVc_AtmHeader=0x00000640]"
++#define SAR_PARM "id=sar,base = 0x03000000, reset_bit = 9, offset = 0; UniNni = 0, PdspEnable = 1"
++#define RESET_PARM "id=ResetControl, base=0xA8611600"
++#define CH0_PARM "RxBufSize=1522, RxNumBuffers = 32, RxServiceMax = 50, TxServiceMax=50, TxNumBuffers=32, CpcsUU=0x5aa5, TxVc_CellRate=0x3000, TxVc_AtmHeader=0x00000640"
++
++#define MAX_PVC_TABLE_ENTRY 16
++
++sar_stat_t sarStat;
++
++typedef struct _channel_parm
++{
++ unsigned int RxBufSize;
++ unsigned int RxNumBuffers;
++ unsigned int RxServiceMax;
++ unsigned int TxServiceMax;
++ unsigned int TxNumBuffers;
++ unsigned int CpcsUU;
++ unsigned int TxVc_CellRate;
++ unsigned int TxVc_AtmHeader;
++}channel_parm_t;
++
++typedef struct _aal5_parm
++{
++ unsigned int base;
++ unsigned int offset;
++ unsigned int int_line;
++ channel_parm_t chan[8];
++}aal5_parm_t;
++
++
++typedef struct _sar_parm
++{
++ unsigned int base;
++ unsigned int reset_bit;
++ unsigned int offset;
++ unsigned int UniNni;
++}sar_parm_t;
++
++typedef struct _pvc_table
++{
++ int bInUse;
++ int vpi;
++ int vci;
++}pvc_table;
++
++static aal5_parm_t aal5Parm;
++static sar_parm_t sarParm;
++static char *pAal5, *pSar, *pReset;
++static int oam_type;
++static unsigned int oamPingStatus;
++static int oamAtmHdr;
++static int oamLbTimeout;
++static char parm_data[1024];
++static char aal5Data[1024];
++static char sarData[1024];
++static char resetData[256];
++static pvc_table pvc_result[MAX_PVC_TABLE_ENTRY];
++
++/* external function */
++extern int __guDbgLevel;
++
++/* gloabal function */
++unsigned int oamFarLBCount[4];
++/* end of gloabal function */
++
++/* internal APIs */
++static int tn7sar_atm_header(int vpi, int vci);
++static void tn7sar_record_pvc(int atmheader);
++
++/*end of internal APIs */
++spinlock_t sar_lock;
++
++/* HAL OS support functions */
++
++
++unsigned long tn7sar_strtoul(const char *str, char **endptr, int base)
++{
++ unsigned long ret;
++
++ ret= simple_strtoul(str, endptr, base);
++ return ret;
++}
++
++static void *tn7sar_malloc(unsigned int size)
++{
++ return(kmalloc(size, GFP_KERNEL));
++}
++
++static unsigned long lockflags;
++static void tn7sar_critical_on(void)
++{
++ spin_lock_irqsave(&sar_lock,lockflags);
++}
++
++static void tn7sar_critical_off(void)
++{
++ spin_unlock_irqrestore(&sar_lock,lockflags);
++}
++
++static void tn7sar_data_invalidate(void *pmem, int size)
++{
++ unsigned int i,Size=(((unsigned int)pmem)&0xf)+size;
++
++ for (i=0;i<Size;i+=16,pmem+=16)
++ {
++ __asm__(" .set mips3 ");
++ __asm__("cache 17, (%0)" : : "r" (pmem));
++ __asm__(" .set mips0 ");
++ }
++
++}
++
++static void tn7sar_data_writeback(void *pmem, int size)
++{
++ unsigned int i,Size=(((unsigned int)pmem)&0xf)+size;
++
++ for (i=0;i<Size;i+=16,pmem+=16)
++ {
++ __asm__(" .set mips3 ");
++ __asm__(" cache 25, (%0)" : : "r" (pmem));
++ __asm__(" .set mips0 ");
++ }
++}
++
++
++static int
++tn7sar_find_device(int unit, const char *find_name, void *device_info)
++{
++ int ret_val = 0;
++ char **ptr;
++
++ ptr = (char **)device_info;
++ dprintf(3,"tn7sar_find_device\n");
++ if(strcmp(find_name, "aal5")==0)
++ {
++ //dprintf(4,"pAal5=%s\n", pAal5);
++ *ptr = pAal5;
++ }
++ else if(strcmp(find_name, "sar")==0)
++ {
++ dprintf(3, "pSar=%s\n", pSar);
++ *ptr = pSar;
++ }
++ else if(strcmp(find_name, "reset")==0)
++ {
++ dprintf(3, "pReset=%s\n", pReset);
++ *ptr = pReset;
++ }
++
++ device_info = NULL;
++
++ return(ret_val);
++}
++
++static int
++tn7sar_get_device_parm_uint(void *dev_info, const char *param, unsigned int *value)
++{
++ char *dev_str;
++ char *pMatch;
++ int i=0, j=0;
++ char val_str[64];
++ unsigned int val;
++ int base = 10;
++
++ dprintf(6, "tn7sar_get_device_parm_uint()\n");
++
++ dev_str = (char *)dev_info;
++ dprintf(3, "parm=%s\n", param);
++ pMatch = strstr(dev_str, param);
++ //dprintf(4, "pMatch=%s\n", pMatch);
++ if(pMatch)
++ {
++ //get "=" position
++ while(pMatch[i] != 0x3d)
++ {
++ i++;
++ }
++ i++;
++ // get rid of spaces
++ while(pMatch[i]==0x20)
++ {
++ i++;
++ }
++ //get rid of 0x
++ if(pMatch[i]==0x30)
++ {
++ if(pMatch[i+1] == 0x58 || pMatch[i+1] == 0x78)
++ {
++ i+=2;
++ base = 16;
++ }
++ }
++
++ // get next delineator
++ while(pMatch[i] != 0x2c && pMatch[i] != 0x0)
++ {
++ val_str[j]=pMatch[i];
++ j++;
++ i++;
++ }
++ val_str[j]=0;
++ //dprintf(4, "val_str=\n%s\n", val_str);
++ //xdump(val_str, strlen(val_str) + 1, 4);
++ val = simple_strtoul(val_str, (char **)NULL, base);
++ dprintf(4, "val =%d\n", val);
++ *value = val;
++ return 0;
++ }
++
++
++ dprintf(3, "match not found.\n");
++ if(strcmp(dev_str, "debug")==0)
++ {
++ dprintf(6,"debug..\n");
++ *value = 6;
++ return 0;
++ }
++ return (1);
++}
++
++static int tn7sar_get_device_parm_value(void *dev_info, const char *param, void *value)
++{
++ char *dev_str;
++ char *pMatch;
++ int i=0, j=0;
++ char *pVal;
++
++
++ dprintf(3, "tn7sar_get_device_parm_value().\n");
++
++ pVal = (char *) parm_data;
++ dev_str = (char *)dev_info;
++ dprintf(3, "dev_info: \n%s\n", dev_str);
++ dprintf(3, "param=%s\n", param);
++ if(strcmp(param, "Ch0")==0)
++ {
++ *(char **)value = CH0_PARM;
++ dprintf(3, "value =%s\n", *(char **)value);
++ return 0;
++ }
++
++ pMatch = strstr(dev_str, param);
++ if(pMatch)
++ {
++ //get "=" position
++ while(pMatch[i] != 0x3d)
++ {
++ i++;
++ }
++ i++;
++ // get rid of spaces
++ while(pMatch[i]==0x20)
++ {
++ i++;
++ }
++
++ if(pMatch[i] != 0x5b) //"["
++ {
++ // get next delineator
++ while(pMatch[i] != 0x2c && pMatch[i] != 0x0)
++ {
++ pVal[j] = pMatch[i];
++ j++;
++ i++;
++ }
++ pVal[j]=0;
++
++ *(char **)value = pVal;
++ return 0;
++ }
++ else
++ {
++ i++; //skip "["
++ while(pMatch[i] != 0x5d)
++ {
++ if(pMatch[i] == 0x3b) //";"
++ pVal[j] = 0x2c;
++ else
++ pVal[j] = pMatch[i];
++ j++;
++ i++;
++ }
++ pVal[j] = 0;
++ *(char **)value = pVal;
++ return 0;
++ }
++
++ }
++
++ return (1);
++}
++
++static void tn7sar_free(void *pmem)
++{
++ kfree(pmem);
++}
++
++static void
++tn7sar_free_buffer(OS_RECEIVEINFO *os_receive_info, void *pmem)
++{
++ tn7atm_free_rx_skb(os_receive_info);
++}
++
++static void tn7sar_free_dev(void *pmem)
++{
++ kfree(pmem);
++}
++
++static void tn7sar_free_dma_xfer(void *pmem)
++{
++ kfree(pmem);
++}
++
++
++static int
++tn7sar_control(void *dev_info, const char *key, const char *action, void *value)
++{
++ int ret_val = -1;
++
++ if (strcmp(key, "Firmware") == 0)
++ {
++ if (strcmp(action, "Get") == 0)
++ {
++ *(int **)value = &SarPdspFirmware[0];
++ }
++ ret_val=0;
++ }
++
++ if (strcmp(key, "FirmwareSize") == 0)
++ {
++ if (strcmp(action, "Get") == 0)
++ {
++ *(int *)value = sizeof(SarPdspFirmware);
++ }
++ ret_val=0;
++ }
++
++ if (strcmp(key, "OamLbResult") == 0)
++ {
++ dprintf(2, "get looback source call back\n");
++ if (strcmp(action, "Set") == 0)
++ {
++ dprintf(2, "oam result = %d\n", *(unsigned int *)value);
++ oamFarLBCount[oam_type] = oamFarLBCount[oam_type] + *(unsigned int *)value;
++ if(oamPingStatus == OAM_PING_PENDING)
++ {
++ oamPingStatus = *(unsigned int *)value;
++ if(oamPingStatus == OAM_PING_SUCCESS)
++ {
++ /* record pvc */
++ tn7sar_record_pvc(oamAtmHdr);
++ }
++ }
++
++ }
++ ret_val=0;
++ }
++
++ if (strcmp(key, "SarFreq") == 0)
++ {
++ if (strcmp(action, "Get") == 0)
++ {
++ *(int *)value = SAR_FREQUNCY;
++ }
++ ret_val=0;
++ }
++ return(ret_val);
++}
++
++
++static void
++tn7sar_sarhal_isr_register(OS_DEVICE *os_dev, int(*hal_isr)(HAL_DEVICE *, int *), int interrupt_num)
++{
++ tn7atm_sarhal_isr_register(os_dev, hal_isr, interrupt_num);
++}
++
++static void
++tn7sar_isr_unregister(OS_DEVICE *os_dev, int interrupt_num)
++{
++ /* TODO */
++}
++
++
++static void *
++tn7sar_malloc_rxbuffer(unsigned int size, void *mem_base, unsigned int mem_range, HAL_DEVICE *hal_dev,
++ HAL_RECEIVEINFO *hal_info, OS_RECEIVEINFO **os_receive_info, OS_DEVICE *os_dev)
++{
++ return tn7atm_allocate_rx_skb(os_dev, os_receive_info, size);
++}
++
++static void *
++tn7sar_malloc_dev(unsigned int size)
++{
++ return(kmalloc(size, GFP_KERNEL));
++}
++
++static void *
++tn7sar_malloc_dma_xfer(unsigned int size, void *mem_base, unsigned int mem_range)
++{
++ dprintf(4, "tn7sar_malloc_dma_xfer, size =%d\n", size);
++
++ return (kmalloc(size, GFP_DMA |GFP_KERNEL));
++
++}
++
++static void *
++tn7sar_memset(void *dst, int set_char, size_t count)
++{
++ return (memset(dst, set_char, count));
++}
++
++static int tn7sar_printf(const char *format, ...)
++{
++ /* TODO: add debug levels */
++ static char buff[256];
++ va_list ap;
++
++ va_start( ap, format);
++ vsprintf((char *)buff, format, ap);
++ va_end(ap);
++
++ printk("SAR HAL: %s\n", buff);
++ return(0);
++}
++
++static void tn7sar_record_pvc(int atmheader)
++{
++ int vci,vpi;
++ int i;
++
++ vci = 0xffff & (atmheader >> 4);
++ vpi = 0xff & (atmheader >> 20);
++ for(i=0;i<MAX_PVC_TABLE_ENTRY;i++)
++ {
++ if(pvc_result[i].bInUse)
++ {
++ if(pvc_result[i].vpi == vpi && pvc_result[i].vci == vci)
++ {
++ return;
++ }
++ }
++ }
++ for(i=0;i<MAX_PVC_TABLE_ENTRY;i++)
++ {
++ if(pvc_result[i].bInUse == 0)
++ {
++ pvc_result[i].bInUse = 1;
++ pvc_result[i].vpi = vpi;
++ pvc_result[i].vci = vci;
++ return;
++ }
++ }
++ return;
++}
++
++static void tn7sar_clear_pvc_table(void)
++{
++ int i;
++
++ for(i=0;i<MAX_PVC_TABLE_ENTRY; i++)
++ {
++ pvc_result[i].bInUse = 0;
++ pvc_result[i].vpi = 0;
++ pvc_result[i].vci = 0;
++ }
++}
++
++int tn7sar_process_unmatched_oam(FRAGLIST *frag_list, unsigned int frag_count, unsigned int packet_size, unsigned int mode)
++{
++
++ FRAGLIST *local_list;
++ int i;
++ unsigned int atmHdr;
++
++ local_list = frag_list;
++
++ for(i=0;i<(int)frag_count;i++)
++ {
++ tn7sar_data_invalidate(local_list->data, (int)local_list->len);
++ local_list ++;
++ }
++ local_list = frag_list;
++ if((mode>>31)) /*vci, vpi is attached */
++ {
++ atmHdr = *(unsigned int *)frag_list->data;
++ tn7sar_record_pvc(atmHdr);
++ if(atmHdr & 0x8) //oam cell
++ {
++ atmHdr &= 0xfffffff0;
++ if(atmHdr == oamAtmHdr)
++ {
++ if(oamPingStatus == OAM_PING_PENDING)
++ {
++ oamPingStatus = OAM_PING_SUCCESS;
++ oamFarLBCount[oam_type] = oamFarLBCount[oam_type] + 1;
++ }
++ return 0;
++ }
++ }
++ }
++
++ return 0;
++}
++
++
++static int
++tn7sar_receive(OS_DEVICE *os_dev,FRAGLIST *frag_list, unsigned int frag_count, unsigned int packet_size,
++ HAL_RECEIVEINFO *hal_receive_info, unsigned int mode)
++{
++ int ch;
++ struct atm_dev *dev;
++ Tn7AtmPrivate *priv;
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++ int bRet;
++
++
++ dprintf(4, "tn7sar_receive\n");
++
++ dev = (struct atm_dev *)os_dev;
++ priv= (Tn7AtmPrivate *)dev->dev_data;
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++
++ /* Mode contains channel info */
++ ch = (mode & 0xFF);
++
++ if(ch == 15)
++ {
++ tn7sar_process_unmatched_oam(frag_list, frag_count, packet_size, mode);
++ pHalFunc->RxReturn(hal_receive_info, 0);
++ return 0;
++ }
++
++ if(frag_count > 1 || frag_list->len == 0)
++ {
++ printk("Packet fragment count > 1, not handdle.\n");
++ return 1;
++ }
++
++ tn7sar_data_invalidate(frag_list->data, (int)frag_list->len);
++ bRet=tn7atm_receive(os_dev, ch, packet_size, frag_list->OsInfo, frag_list->data);
++
++ if(bRet==0)
++ {
++ sarStat.rxPktCnt++;
++ sarStat.rxBytes += packet_size;
++ pHalFunc->RxReturn(hal_receive_info, 1);
++ }
++ else
++ {
++ pHalFunc->RxReturn(hal_receive_info, 0);
++ }
++
++ return bRet;
++}
++
++static int
++tn7sar_send_complete(OS_SENDINFO *osSendInfo)
++{
++ return (tn7atm_send_complete(osSendInfo));
++}
++
++void
++tn7sar_teardown_complete(OS_DEVICE *OsDev, int ch, int Dir)
++{
++ return;
++}
++
++
++/*
++unsigned int tn7sar_virt(unsigned int address)
++{
++ return phys_to_virt(address);
++}
++*/
++
++int tn7sar_init_module(OS_FUNCTIONS *os_funcs)
++{
++ dprintf(4, "tn7sar_init_module\n");
++ if( os_funcs == 0 )
++ {
++ return(-1);
++ }
++ os_funcs->Control = tn7sar_control;
++ os_funcs->CriticalOn = tn7sar_critical_on;
++ os_funcs->CriticalOff = tn7sar_critical_off;
++ os_funcs->DataCacheHitInvalidate = tn7sar_data_invalidate;
++ os_funcs->DataCacheHitWriteback = tn7sar_data_writeback;
++ os_funcs->DeviceFindInfo = tn7sar_find_device;
++ os_funcs->DeviceFindParmUint = tn7sar_get_device_parm_uint;
++ os_funcs->DeviceFindParmValue = tn7sar_get_device_parm_value;
++ os_funcs->Free = tn7sar_free;
++ os_funcs->FreeRxBuffer = tn7sar_free_buffer;
++ os_funcs->FreeDev = tn7sar_free_dev;
++ os_funcs->FreeDmaXfer = tn7sar_free_dma_xfer;
++ os_funcs->IsrRegister = tn7sar_sarhal_isr_register;
++ os_funcs->IsrUnRegister = tn7sar_isr_unregister;
++ os_funcs->Malloc = tn7sar_malloc;
++ os_funcs->MallocRxBuffer = tn7sar_malloc_rxbuffer;
++ os_funcs->MallocDev = tn7sar_malloc_dev;
++ os_funcs->MallocDmaXfer = tn7sar_malloc_dma_xfer;
++ os_funcs->Memset = tn7sar_memset;
++ os_funcs->Printf = tn7sar_printf;
++ os_funcs->Receive = tn7sar_receive;
++ os_funcs->SendComplete = tn7sar_send_complete;
++ os_funcs->Strcmpi = strcmp;
++ os_funcs->Sprintf = sprintf;
++ os_funcs->Strlen = strlen;
++ os_funcs->Strstr = strstr;
++ os_funcs->Strtoul = tn7sar_strtoul;
++ os_funcs->TeardownComplete = tn7sar_teardown_complete;
++
++ return(0);
++}
++
++
++static void tn7sar_init_dev_parm(void)
++{
++ int i;
++
++
++ /* aal5 */
++ //strcpy(aal5Parm.id, "aal5");
++ aal5Parm.base = 0x03000000;
++ aal5Parm.offset = 0;
++ aal5Parm.int_line=15;
++ aal5Parm.chan[0].RxBufSize=1600;
++ aal5Parm.chan[0].RxNumBuffers = 32;
++ aal5Parm.chan[0].RxServiceMax = 50;
++ aal5Parm.chan[0].TxServiceMax=50;
++ aal5Parm.chan[0].TxNumBuffers=32;
++ aal5Parm.chan[0].CpcsUU=0x5aa5;
++ aal5Parm.chan[0].TxVc_CellRate=0x3000;
++ aal5Parm.chan[0].TxVc_AtmHeader=0x00000640;
++ for(i=1;i<8;i++)
++ {
++ memcpy(&aal5Parm.chan[i], &aal5Parm.chan[0], sizeof(aal5Parm.chan[0]));
++ }
++
++
++ /* sar */
++ //strcpy(sarParm.id, "sar");
++ sarParm.base = 0x03000000;
++ sarParm.reset_bit = 9;
++ sarParm.offset = 0;
++ sarParm.UniNni = 0;
++
++ pAal5 = aal5Data;
++ pSar = sarData;
++ pReset = resetData;
++ strcpy(pAal5, AAL5_PARM);
++ strcpy(pSar, SAR_PARM);
++ strcpy(pReset, RESET_PARM);
++
++}
++
++
++int tn7sar_get_stats(void *priv1)
++{
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++ Tn7AtmPrivate *priv;
++ int i, j;
++ unsigned int *pSarStat, *pStateBase;
++ char statString[64];
++ int len;
++
++ dprintf(2, "tn7sar_get_stats\n");
++
++ priv = (Tn7AtmPrivate *)priv1;
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++ //memset(&sarStat, 0, sizeof(sarStat));
++ sarStat.txErrors = 0;
++ sarStat.rxErrors = 0;
++ for(i=0;i<MAX_DMA_CHAN;i++)
++ {
++ if(priv->lut[i].inuse)
++ {
++ for(j=0;j<1;j++)
++ {
++ len=sprintf(statString, "Stats;0;%d", priv->lut[i].chanid);
++ statString[len]=0;
++ dprintf(2, "statString=%s\n",statString);
++ pHalFunc->Control(pHalDev, statString, "Get", &pSarStat);
++ pStateBase = pSarStat;
++ while(pSarStat)
++ {
++ if((char *)*pSarStat == NULL)
++ break;
++ dprintf(2, "%s\n", (char *) *pSarStat);
++ pSarStat++;
++ dprintf(2, "%s\n", (char *) *pSarStat);
++ sarStat.rxErrors += os_atoul((char *) *pSarStat);
++ pSarStat++;
++ }
++
++ kfree(pStateBase);
++ }
++ }
++ }
++ return 0;
++}
++
++int tn7sar_setup_oam_channel(Tn7AtmPrivate *priv)
++{
++
++ CHANNEL_INFO chInfo;
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++ int chan=15;
++ dprintf(4, "tn7sar_setup_oam_channel\n");
++
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++ memset(&chInfo, 0xff, sizeof(chInfo));
++
++ /* channel specific */
++ chInfo.Channel = 15; /* hardcoded for last channel */
++ chInfo.Direction = 0;
++ chInfo.Vci = 30; /* just need below 32 */
++ chInfo.Vpi = 0;
++ chInfo.TxVc_QosType = 2;
++
++ /*default */
++ chInfo.PktType = PACKET_TYPE_TRANS;
++ chInfo.TxServiceMax = 2;
++ chInfo.RxServiceMax = 2;
++ chInfo.TxNumQueues = 1;
++ chInfo.TxNumBuffers = 4;
++ chInfo.RxNumBuffers = 4;
++ chInfo.RxBufSize = 256;
++ chInfo.RxVc_OamToHost = 0;
++ chInfo.RxVp_OamToHost = 0;
++ chInfo.FwdUnkVc = 1; //enable forwarding of unknown vc
++ chInfo.TxVc_AtmHeader = tn7sar_atm_header((int)chInfo.Vpi, chInfo.Vci);
++ chInfo.RxVc_AtmHeader = tn7sar_atm_header((int)chInfo.Vpi, chInfo.Vci);
++ chInfo.TxVp_AtmHeader = tn7sar_atm_header((int)chInfo.Vpi, 0);
++ chInfo.RxVp_AtmHeader = tn7sar_atm_header((int)chInfo.Vpi, 0);
++
++ dprintf(4, "TxVc_AtmHeader=0x%x\n", chInfo.TxVc_AtmHeader);
++
++ if(pHalFunc->ChannelSetup(pHalDev, &chInfo, NULL))
++ {
++ printk("failed to setup channel =%d.\n", chan);
++ return -1;
++ }
++
++ // claiming the channel
++ priv->lut[chan].vpi = 0;
++ priv->lut[chan].vci = 30;
++ priv->lut[chan].chanid = chan;
++ priv->lut[chan].inuse = 1;
++ return 0;
++}
++
++int tn7sar_init(struct atm_dev *dev, Tn7AtmPrivate *priv)
++{
++ int retCode;
++ int hal_funcs_size;
++
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++ OS_FUNCTIONS *pOsFunc;
++ int oamMod;
++ char *pLbTimeout;
++ int lbTimeout;
++
++
++ dprintf(4, "tn7sar_init\n");
++
++ pOsFunc = (OS_FUNCTIONS *)kmalloc(sizeof(OS_FUNCTIONS), GFP_KERNEL);
++
++
++ priv->pSarOsFunc = ( void *)pOsFunc;
++
++ /* init boot parms */
++ tn7sar_init_dev_parm();
++
++ /* init sar os call back functions */
++ retCode = tn7sar_init_module(pOsFunc);
++ if (retCode != 0) /* error */
++ {
++ printk("Failed to init SAR OS Functions\n");
++ return (1);
++ }
++
++ /* Init sar hal */
++ retCode = cpaal5InitModule(&pHalDev, (OS_DEVICE*) dev, &pHalFunc,
++ pOsFunc, sizeof(OS_FUNCTIONS), &hal_funcs_size, 0);
++ if (retCode != 0) /* error */
++ {
++ printk("Failed to init SAR HAL\n");
++ return (1);
++ }
++
++ /* sanity check */
++ if (pHalDev == NULL || pHalFunc == NULL || hal_funcs_size != sizeof(HAL_FUNCTIONS) )
++ {
++ printk("Invalid SAR hal and/or functions.\n");
++ return (1);
++ }
++
++ /* remeber HAL pointers */
++ priv->pSarHalDev = (void *)pHalDev;
++ priv->pSarHalFunc = (void *)pHalFunc;
++
++ /* Probe for the Device to get hardware info from driver */
++ retCode = pHalFunc->Probe(pHalDev);
++ if (retCode !=0)
++ {
++ printk("SAR hal probing error.\n");
++ return (1);
++ }
++
++ /* init sar hal */
++ retCode = pHalFunc->Init(pHalDev);
++ if (retCode != 0) /* error */
++ {
++
++ printk("pHalFunc->Init failed. err code =%d\n", retCode);
++ return (1);
++ }
++
++ /* open hal module */
++ retCode = pHalFunc->Open(pHalDev);
++ if (retCode != 0) /* error */
++ {
++ printk("pHalFunc->open failed, err code: %d\n",retCode );
++ return (1);
++ }
++
++ /* init sar for firmware oam */
++ oamMod= 1;
++ pHalFunc->Control(pHalDev,"OamMode", "Set", &oamMod);
++
++ /* read in oam lb timeout value */
++ pLbTimeout = prom_getenv("oam_lb_timeout");
++ if(pLbTimeout)
++ {
++ lbTimeout =tn7sar_strtoul(pLbTimeout, NULL, 10);
++ oamLbTimeout = lbTimeout;
++ pHalFunc->Control(pHalDev,"OamLbTimeout", "Set", &lbTimeout);
++ }
++ else
++ {
++ oamLbTimeout = 5000;
++ }
++
++ oamFarLBCount[0]=0;
++ oamFarLBCount[1]=0;
++ oamFarLBCount[2]=0;
++ oamFarLBCount[3]=0;
++
++ memset(&sarStat, 0 , sizeof(sarStat));
++
++ /* setup channel 15 for oam operation */
++ tn7sar_setup_oam_channel(priv);
++ dprintf(4, "tn7sar_init done");
++ return 0;
++}
++
++static int
++tn7sar_atm_header(int vpi, int vci)
++{
++ union
++ {
++ unsigned char byte[4];
++ unsigned int dword;
++ }atm_h;
++ int itmp = 0;
++
++ //vci
++ itmp = vci &0xf;
++ atm_h.byte[0] = 0;
++ atm_h.byte[0] |= (itmp << 4);
++ atm_h.byte[1] = ((vci & 0xff0) >> 4);
++ atm_h.byte[2] = 0;
++ atm_h.byte[2] |= ((vci & 0xf000) >>12);;
++ atm_h.byte[2] |= ((vpi & 0xf) << 4);
++ atm_h.byte[3] = 0;
++ atm_h.byte[3] = ((vpi & 0xff0) >> 4);
++ return atm_h.dword;
++}
++
++int tn7sar_activate_vc(Tn7AtmPrivate *priv, short vpi, int vci, int pcr, int scr, int mbs, int cdvt, int chan, int qos)
++{
++ CHANNEL_INFO chInfo;
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++
++ dprintf(4, "tn7sar_activate_vc\n");
++
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++ memset(&chInfo, 0xff, sizeof(chInfo));
++
++ /* channel specific */
++ chInfo.Channel = chan;
++ chInfo.Direction = 0;
++ chInfo.Vci = vci;
++ chInfo.Vpi = vpi;
++ chInfo.TxVc_QosType = qos;
++ chInfo.Priority = qos;
++
++ if(chInfo.TxVc_QosType == 1) /* if the connection is VBR than set the DaMask value to tell the schedular to accumalte the credit */
++ {
++ chInfo.DaMask = 1;
++ }
++ chInfo.TxVc_Mbs = mbs; /* use pcr as MBS */
++ pcr = SAR_FREQUNCY/pcr;
++ scr = SAR_FREQUNCY/scr;
++ chInfo.TxVc_CellRate = scr;
++ chInfo.TxVc_Pcr = pcr;
++
++ /*default */
++ chInfo.PktType = PACKET_TYPE_AAL5;
++ chInfo.TxServiceMax = TX_SERVICE_MAX;
++ chInfo.RxServiceMax = RX_SERVICE_MAX;
++ chInfo.TxNumQueues = TX_QUEUE_NUM;
++ chInfo.TxNumBuffers = TX_BUFFER_NUM;
++ chInfo.RxNumBuffers = RX_BUFFER_NUM;
++ chInfo.RxBufSize = RX_BUFFER_SIZE;
++ chInfo.RxVc_OamToHost = 0;
++ chInfo.RxVp_OamToHost = 0;
++ chInfo.TxVc_AtmHeader = tn7sar_atm_header((int)vpi, vci);
++ chInfo.RxVc_AtmHeader = tn7sar_atm_header((int)vpi, vci);
++ chInfo.TxVp_AtmHeader = tn7sar_atm_header((int)vpi, 0);
++ chInfo.RxVp_AtmHeader = tn7sar_atm_header((int)vpi, 0);
++ chInfo.CpcsUU = 0;
++
++ dprintf(4, "TxVc_AtmHeader=0x%x\n", chInfo.TxVc_AtmHeader);
++
++ if(pHalFunc->ChannelSetup(pHalDev, &chInfo, NULL))
++ {
++ printk("failed to setup channel =%d.\n", chan);
++ return -1;
++ }
++
++
++ return 0;
++}
++
++int tn7sar_send_packet(Tn7AtmPrivate *priv, int chan, void *new_skb, void *data,unsigned int len, int priority)
++{
++ FRAGLIST fragList;
++ unsigned int mode;
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++
++ dprintf(4, "tn7sar_send_packet\n");
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++ fragList.len = len;
++ fragList.data = (void *)data;
++
++ xdump((char *)fragList.data , fragList.len, 6);
++
++ /*mode bit
++ 31-19 unused
++ 18 oam cell, 1 = true, 0=false
++ 17-16 oam type, 0=F4 seg, 1=F4 End, 2=F5 seg, 3=F5 end
++ 15-08 transimit queue, current, 0=priority queue, 1=normal queue
++ 07-00 channel number
++ */
++ mode = 0;
++ mode |= (0xff & chan);
++ mode |= ((0xff & priority) << 8);
++
++ dprintf(4, "mode = %d\n", mode);
++
++ tn7sar_data_writeback(fragList.data, len);
++ if(pHalFunc->Send(pHalDev, &fragList, 1, len, new_skb, mode) != 0)
++ {
++ dprintf(1, "SAR hal failed to send packet.\n");
++ return 1;
++ }
++ //tn7sar_get_stats(priv);
++ sarStat.txPktCnt++;
++ sarStat.txBytes +=len;
++ return 0;
++}
++
++
++
++int tn7sar_handle_interrupt(struct atm_dev *dev, Tn7AtmPrivate *priv)
++{
++ int more;
++ int rc;
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++ int (*halIsr)(HAL_DEVICE *halDev, int *work);
++
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++ halIsr = priv->halIsr;
++
++ rc = halIsr(pHalDev, &more);
++
++ pHalFunc->PacketProcessEnd(pHalDev);
++
++ return rc;
++}
++
++
++int tn7sar_deactivate_vc(Tn7AtmPrivate *priv, int chan)
++{
++ unsigned int mode;
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++
++ dprintf(4, "tn7sar_deactivate_vc\n");
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++ mode = 0xf; //tear down everything, wait for return;
++
++ pHalFunc->ChannelTeardown(pHalDev, chan, mode);
++ return 0;
++}
++
++void tn7sar_exit(struct atm_dev *dev, Tn7AtmPrivate *priv)
++{
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++
++ dprintf(4, "tn7sar_exit()\n");
++
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++ tn7sar_deactivate_vc(priv, 15); // de-activate oam channel
++
++ pHalFunc->Close(pHalDev, 2);
++ pHalFunc->Shutdown(pHalDev);
++
++ kfree(priv->pSarOsFunc);
++
++}
++
++void tn7sar_get_sar_version(Tn7AtmPrivate *priv, char **pVer)
++{
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++
++ dprintf(4, "tn7sar_get_sar_version()\n");
++
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++ pHalFunc->Control(pHalDev, "Version", "Get", pVer);
++}
++
++
++int tn7sar_get_near_end_loopback_count(unsigned int *pF4count, unsigned int *pF5count)
++{
++ unsigned int f4c, f5c;
++
++ f4c = *(volatile unsigned int *)SAR_PDSP_OAM_F4LB_COUNT_REG_ADDR;
++ f5c = *(volatile unsigned int *)SAR_PDSP_OAM_F5LB_COUNT_REG_ADDR;
++ *pF4count = f4c;
++ *pF5count = f5c;
++
++ return 0;
++}
++
++
++int tn7sar_unmatched_oam_generation(void *privContext, int vpi, int vci, int type)
++{
++
++ unsigned int regv = 0;
++ int chan=15;
++ static unsigned int tag;
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++ Tn7AtmPrivate *priv;
++ unsigned int llid[4]={0xffffffff,0xffffffff,0xffffffff,0xffffffff};
++
++ dprintf(4, "tn7sar_unknow_oam_generation()\n");
++
++ priv = (Tn7AtmPrivate *)privContext;
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++ if(vci==0)
++ {
++ oamPingStatus = OAM_PING_FAILED;
++ return 0;
++ }
++ /* calculate atm header */
++ oamAtmHdr = tn7sar_atm_header(vpi,vci);
++
++ /* config the atm header */
++ pHalFunc->Control(pHalDev,"TxVc_AtmHeader.15", "Set", &oamAtmHdr);
++
++ /*record oam type */
++ oam_type = type;
++
++ regv = (0xff & chan);
++
++ switch(type)
++ {
++ case 0:
++ regv |= (1<<12); //f5 end
++ dprintf(2, "f5 loop back\n");
++ break;
++ case 1:
++ regv |= (1<<13); // f4 end
++ break;
++ case 2:
++ regv |= (1<<14); //f5 seg
++ break;
++ case 3:
++ regv |= (1<<15); //f4 seg
++ break;
++ default:
++ break;
++ }
++ oamPingStatus = OAM_PING_PENDING;
++ pHalFunc->OamLoopbackConfig(pHalDev, regv, llid, tag);
++ tag++;
++ return 0;
++
++}
++
++int tn7sar_oam_generation(void *privContext, int chan, int type, int vpi, int vci, int timeout)
++{
++ unsigned int regv = 0;
++ static unsigned int tag;
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++ Tn7AtmPrivate *priv;
++ unsigned int llid[4]={0xffffffff,0xffffffff,0xffffffff,0xffffffff};
++
++ dprintf(2, "tn7sar_oam_generation()\n");
++
++ priv = (Tn7AtmPrivate *)privContext;
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++ if(timeout >= 5000)
++ {
++ if(timeout == 6000)
++ {
++ tn7sar_clear_pvc_table();
++ return 0;
++ }
++ timeout = oamLbTimeout;
++ }
++
++
++ pHalFunc->Control(pHalDev,"OamLbTimeout", "Set", &timeout);
++
++ if(chan == ATM_NO_DMA_CHAN)
++ {
++ tn7sar_unmatched_oam_generation(priv, vpi, vci, type);
++ return 0;
++ }
++
++ /* calculate atm header */
++ oamAtmHdr = tn7sar_atm_header(vpi,vci);
++
++ oam_type = type;
++
++ regv = (0xff & chan);
++ switch(type)
++ {
++ case 0:
++ regv |= (1<<12); //f5 end
++ dprintf(2, "f5 loop back\n");
++ break;
++ case 1:
++ regv |= (1<<13); // f4 end
++ break;
++ case 2:
++ regv |= (1<<14); //f5 seg
++ break;
++ case 3:
++ regv |= (1<<15); //f4 seg
++ break;
++ default:
++ break;
++ }
++ oamPingStatus = OAM_PING_PENDING;
++ pHalFunc->OamLoopbackConfig(pHalDev, regv, llid, tag);
++ tag++;
++
++ return 0;
++}
++
++int tn7sar_proc_oam_ping(char* buf, char **start, off_t offset, int count,int *eof, void *data)
++{
++ int len = 0;
++
++ len += sprintf(buf+len, "%d\n", oamPingStatus);
++
++ return len;
++}
++
++int tn7sar_proc_pvc_table(char* buf, char **start, off_t offset, int count,int *eof, void *data)
++{
++ int len = 0;
++ int i;
++
++ for(i=0;i<16;i++)
++ {
++ if(pvc_result[i].bInUse)
++ {
++ len += sprintf(buf+len, "%d,%d\n", pvc_result[i].vpi,pvc_result[i].vci);
++ }
++ else
++ {
++ len += sprintf(buf+len, "0,0\n");
++ }
++ }
++ return len;
++}
++
++
++
++int tn7sar_proc_sar_stat(char* buf, char **start, off_t offset, int count,int *eof, void *data)
++{
++ int len = 0;
++ int limit = count - 80;
++ struct atm_dev *dev;
++ Tn7AtmPrivate *priv;
++ int i, j, k;
++ int stat_len;
++ char statString[32];
++ unsigned int *pStateBase, *pSarStat;
++ HAL_FUNCTIONS *pHalFunc;
++ HAL_DEVICE *pHalDev;
++ int dBytes;
++
++ dev = (struct atm_dev *)data;
++ priv = (Tn7AtmPrivate *)dev->dev_data;
++
++ pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc;
++ pHalDev = (HAL_DEVICE *)priv->pSarHalDev;
++
++ len += sprintf(buf+len, "SAR HAL Statistics\n");
++ for(i=0;i<MAX_DMA_CHAN;i++)
++ {
++ if(priv->lut[i].inuse)
++ {
++ if(len<=limit)
++ len += sprintf(buf+len, "\nChannel %d:\n",priv->lut[i].chanid);
++ k=0;
++ for(j=0;j<4;j++)
++ {
++ stat_len =sprintf(statString, "Stats;%d;%d", j,priv->lut[i].chanid);
++ statString[stat_len]=0;
++ pHalFunc->Control(pHalDev, statString, "Get", &pSarStat);
++ pStateBase = pSarStat;
++ while(pSarStat)
++ {
++ if((char *)*pSarStat == NULL)
++ break;
++ if(len<=limit)
++ {
++ dBytes = sprintf(buf+len, "%s: ",(char *) *pSarStat);
++ len += dBytes;
++ k += dBytes;
++ }
++ pSarStat++;
++ if(len<=limit)
++ {
++ dBytes = sprintf(buf+len, "%s; ",(char *) *pSarStat);
++ len += dBytes;
++ k += dBytes;
++ }
++ pSarStat++;
++
++ if(k > 60)
++ {
++ k=0;
++ if(len<=limit)
++ len += sprintf(buf+len, "\n");
++ }
++ }
++
++ kfree(pStateBase);
++ }
++ }
++ }
++
++ return len;
++}
++
++void tn7sar_get_sar_firmware_version(unsigned int *pdsp_version_ms, unsigned int *pdsp_version_ls)
++{
++
++ *pdsp_version_ms = (SarPdspFirmware[9]>>20) & 0xF;
++ *pdsp_version_ls = (SarPdspFirmware[9]>>12) & 0xFF;
++ return;
++}
+diff -urN linux.old/drivers/atm/sangam_atm/tnetd7300_sar_firm.h linux.dev/drivers/atm/sangam_atm/tnetd7300_sar_firm.h
+--- linux.old/drivers/atm/sangam_atm/tnetd7300_sar_firm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/tnetd7300_sar_firm.h 2005-08-23 04:46:50.111841568 +0200
+@@ -0,0 +1,988 @@
++//SarPdspFirmware Revision: 49
++
++static int SarPdspFirmware[] = {
++ 0xb0a8d1f1,
++ 0x000003d8,
++ 0x00000000,
++ 0x00000004,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x21000900,
++ 0x24049080,
++ 0x24000080,
++ 0x240000c0,
++ 0x10e0e0e1,
++ 0x10e0e0e2,
++ 0x10e0e0e3,
++ 0x10e0e0e4,
++ 0x10e0e0e5,
++ 0x10e0e0e6,
++ 0x10e0e0e7,
++ 0x10e0e0e8,
++ 0x10e0e0e9,
++ 0x10e0e0ea,
++ 0x10e0e0eb,
++ 0x10e0e0ec,
++ 0x10e0e0ed,
++ 0x10e0e0ee,
++ 0x10e0e0ef,
++ 0x10e0e0f0,
++ 0x10e0e0f1,
++ 0x10e0e0f2,
++ 0x10e0e0f3,
++ 0x10e0e0f4,
++ 0x10e0e0f5,
++ 0x10e0e0f6,
++ 0x10e0e0f7,
++ 0x10e0e0f8,
++ 0x10e0e0f9,
++ 0x10e0e0fa,
++ 0x10e0e0fb,
++ 0x10e0e0fc,
++ 0x10e0e0fd,
++ 0x10e0e0fe,
++ 0x10e0e0ff,
++ 0x81042680,
++ 0x810c2680,
++ 0x81042680,
++ 0x2483c080,
++ 0x81180b80,
++ 0x2484c080,
++ 0x811a0b80,
++ 0x2485c080,
++ 0x811c0b80,
++ 0x240100dd,
++ 0xa07d06fd,
++ 0x240400dd,
++ 0xa07d04fd,
++ 0x24c000dd,
++ 0x2400169d,
++ 0xa07d5cfd,
++ 0x511f9d03,
++ 0x01019d9d,
++ 0x7f0000fd,
++ 0xd11eff05,
++ 0x97c06890,
++ 0x1d00e5e5,
++ 0x2301229e,
++ 0x81bc2890,
++ 0x24000000,
++ 0xc917ff02,
++ 0x81000100,
++ 0x01010000,
++ 0xc918ff02,
++ 0x81000100,
++ 0x01010000,
++ 0xc919ff02,
++ 0x81000100,
++ 0xd110e70a,
++ 0xd11cff09,
++ 0x1d00e5e5,
++ 0xd100e704,
++ 0xd114ff06,
++ 0x2301179e,
++ 0x79000004,
++ 0xd70ffffd,
++ 0x91382486,
++ 0x2301059e,
++ 0xc903ff07,
++ 0xa06047e0,
++ 0xb10043e6,
++ 0xc910e602,
++ 0x81000106,
++ 0x24006025,
++ 0x2300d39e,
++ 0xd11dff09,
++ 0x1f00e5e5,
++ 0xc901e705,
++ 0xd111ff06,
++ 0x91382586,
++ 0x2301059e,
++ 0x79000003,
++ 0xd715fffc,
++ 0x2301179e,
++ 0xc910e706,
++ 0x110f2760,
++ 0x240000c6,
++ 0x24000086,
++ 0x13106006,
++ 0x7b00005a,
++ 0x11079f80,
++ 0x51008010,
++ 0xc912ff0f,
++ 0xd100ff04,
++ 0xd101ff05,
++ 0xa06046e0,
++ 0x79000004,
++ 0xa06044e0,
++ 0x79000002,
++ 0xa06045e0,
++ 0xb10043e6,
++ 0x61150602,
++ 0x2101c500,
++ 0xc910e602,
++ 0xa1001006,
++ 0x24000025,
++ 0x2300d39e,
++ 0xd11fff05,
++ 0x97c06a90,
++ 0x1f00e5e5,
++ 0x2301229e,
++ 0x81bc2a90,
++ 0xd11cff09,
++ 0x1d00e5e5,
++ 0xc900e705,
++ 0xd10fff06,
++ 0x91382486,
++ 0x2301059e,
++ 0x79000003,
++ 0xd714fffc,
++ 0x2301179e,
++ 0xc907ff07,
++ 0xa0604be0,
++ 0xb10043e6,
++ 0xc910e602,
++ 0x81000106,
++ 0x24006025,
++ 0x2300d39e,
++ 0xd111e70a,
++ 0xd11dff09,
++ 0x1f00e5e5,
++ 0xd101e704,
++ 0xd115ff06,
++ 0x2301179e,
++ 0x79000004,
++ 0xd711fffd,
++ 0x91382586,
++ 0x2301059e,
++ 0xc911e706,
++ 0x0b042760,
++ 0x240000c6,
++ 0x24000086,
++ 0x13106006,
++ 0x7b000024,
++ 0x11709f80,
++ 0x5100800e,
++ 0xc913ff0d,
++ 0xd104ff04,
++ 0xd105ff05,
++ 0xa0604ae0,
++ 0x79000004,
++ 0xa06048e0,
++ 0x79000002,
++ 0xa06049e0,
++ 0xb10043e6,
++ 0xc910e602,
++ 0xa1001106,
++ 0x24000025,
++ 0x2300d39e,
++ 0xc90bff02,
++ 0x7900000b,
++ 0xc90aff02,
++ 0x79000012,
++ 0xcf08ff89,
++ 0xb10002e0,
++ 0xcf18e087,
++ 0x790000b6,
++ 0x24000080,
++ 0x24fb00c0,
++ 0xa06003e0,
++ 0x7f000082,
++ 0xb10024e6,
++ 0xb10025e0,
++ 0xa06628e6,
++ 0xa06029e0,
++ 0x248000c6,
++ 0xa06624e6,
++ 0x671006f0,
++ 0x81082186,
++ 0x7f0000ee,
++ 0xb10027e6,
++ 0x61100604,
++ 0xa0662be6,
++ 0x810c2186,
++ 0x79000006,
++ 0xd70cffea,
++ 0xa0662be6,
++ 0x1f1be6e6,
++ 0x81382686,
++ 0x813c2680,
++ 0x248000c6,
++ 0xa06627e6,
++ 0x7f0000e3,
++ 0x110f0600,
++ 0x81100b00,
++ 0x01502545,
++ 0x90457888,
++ 0x5103091c,
++ 0x6901092a,
++ 0xc910e603,
++ 0xd108e90d,
++ 0x79000027,
++ 0x01582545,
++ 0x9045788a,
++ 0xd108e904,
++ 0x1f08e9e9,
++ 0x01552545,
++ 0x80451829,
++ 0x50eaeb20,
++ 0x0101ebeb,
++ 0x015c2545,
++ 0x8045388b,
++ 0x7900001c,
++ 0x015c2545,
++ 0x9045788b,
++ 0x6900eb05,
++ 0x1d08e9e9,
++ 0x01552545,
++ 0x80451829,
++ 0x79000004,
++ 0x0501ebeb,
++ 0x015c2545,
++ 0x8045388b,
++ 0x10ecece8,
++ 0x79000010,
++ 0x24000000,
++ 0x5110000e,
++ 0x690f6903,
++ 0x24000069,
++ 0x79000002,
++ 0x01016969,
++ 0x01010000,
++ 0x81100b69,
++ 0x01542545,
++ 0x90451809,
++ 0x6f0209f7,
++ 0xa1001069,
++ 0x81100b06,
++ 0x01572545,
++ 0x80451869,
++ 0xa06841e8,
++ 0xa1414006,
++ 0x209e0000,
++ 0x81100b06,
++ 0xd11fe603,
++ 0x9164388d,
++ 0x8108248d,
++ 0xd100e507,
++ 0x97406490,
++ 0x9108248d,
++ 0x813c2480,
++ 0x2302b4de,
++ 0x1d00e7e7,
++ 0x79000006,
++ 0x97406590,
++ 0x9108258d,
++ 0x813c2580,
++ 0x1d01e7e7,
++ 0x2302b9de,
++ 0x8164388d,
++ 0x209e0000,
++ 0x81040105,
++ 0x91002286,
++ 0x97086290,
++ 0x81042280,
++ 0xd100e504,
++ 0x2302b4de,
++ 0x1f00e7e7,
++ 0x209e0000,
++ 0x2302b9de,
++ 0x1f01e7e7,
++ 0x209e0000,
++ 0xd109ff00,
++ 0xa0702cf0,
++ 0x79000001,
++ 0xd109ff00,
++ 0xb1002de6,
++ 0xd11ee609,
++ 0xb1000de0,
++ 0xc91fe044,
++ 0x24c338c6,
++ 0x10000006,
++ 0x81382686,
++ 0x87406690,
++ 0x813c2680,
++ 0x7900003e,
++ 0x110f0600,
++ 0x81100b00,
++ 0x24000045,
++ 0x24000025,
++ 0x61100603,
++ 0x24006045,
++ 0x24006025,
++ 0x01704545,
++ 0x90451888,
++ 0x0b034600,
++ 0x11070000,
++ 0x69040004,
++ 0xc916ff2c,
++ 0x01019e9e,
++ 0x7900002f,
++ 0xc90cff04,
++ 0x6f0200fd,
++ 0xd308e8a1,
++ 0x7f0000fb,
++ 0x69020008,
++ 0xd308e89e,
++ 0xb1002fe6,
++ 0x91b82880,
++ 0xc91ce002,
++ 0x1f1ce6e6,
++ 0x10080806,
++ 0x79000015,
++ 0xb1002fe6,
++ 0x69030003,
++ 0x13c06666,
++ 0x79000011,
++ 0x91807809,
++ 0xc910ea09,
++ 0x81082689,
++ 0x01018a8a,
++ 0xc91ee60a,
++ 0x1d10eaea,
++ 0x240557c0,
++ 0x60c08a07,
++ 0x1f1de6e6,
++ 0x79000005,
++ 0x2400018a,
++ 0x1f10eaea,
++ 0x1f1fe6e6,
++ 0xd71ee6f8,
++ 0x51000002,
++ 0x11c76666,
++ 0x81382686,
++ 0x87406690,
++ 0x91082689,
++ 0x813c2680,
++ 0xb1002ee6,
++ 0xd103e609,
++ 0x81807809,
++ 0xc908e807,
++ 0x21039400,
++ 0x81002386,
++ 0x87086390,
++ 0x81042380,
++ 0xc908e802,
++ 0x21039400,
++ 0x209e0000,
++ 0xb10008ef,
++ 0x110f0f00,
++ 0x81100b00,
++ 0x24000025,
++ 0x61100f02,
++ 0x24005025,
++ 0x01952545,
++ 0x9045382e,
++ 0xc91def03,
++ 0x24000900,
++ 0x2301c09e,
++ 0xc91cef03,
++ 0x24001900,
++ 0x2301c09e,
++ 0xc91bef03,
++ 0x24000a00,
++ 0x2301c09e,
++ 0xc91aef03,
++ 0x24001a00,
++ 0x2301c09e,
++ 0x8045382e,
++ 0x01a82545,
++ 0x9045388e,
++ 0xc915ef03,
++ 0x24000000,
++ 0x2301c09e,
++ 0xc914ef03,
++ 0x24001000,
++ 0x2301c09e,
++ 0x8045388e,
++ 0x61100f02,
++ 0x24006025,
++ 0x016d2545,
++ 0x9045382e,
++ 0xc919ef03,
++ 0x24000900,
++ 0x2301c09e,
++ 0xc918ef03,
++ 0x24001900,
++ 0x2301c09e,
++ 0xc917ef03,
++ 0x24000a00,
++ 0x2301c09e,
++ 0xc916ef03,
++ 0x24001a00,
++ 0x2301c09e,
++ 0x8045382e,
++ 0x017c2545,
++ 0x9045388e,
++ 0xc913ef03,
++ 0x24000000,
++ 0x2301c09e,
++ 0xc912ef03,
++ 0x24001000,
++ 0x2301c09e,
++ 0x8045388e,
++ 0xd11eef19,
++ 0x11f02f00,
++ 0x51000017,
++ 0x24001520,
++ 0x81140b20,
++ 0x81b01a0f,
++ 0x1f02e7e7,
++ 0x24c000c0,
++ 0x24001580,
++ 0xa0605ce0,
++ 0xc90fef04,
++ 0x1d04e7e7,
++ 0x1d05e7e7,
++ 0x7900000c,
++ 0xc90eef04,
++ 0x1d04e7e7,
++ 0x1f05e7e7,
++ 0x79000008,
++ 0xc90def04,
++ 0x1f04e7e7,
++ 0x1d05e7e7,
++ 0x79000004,
++ 0xc90cef03,
++ 0x1f04e7e7,
++ 0x1f05e7e7,
++ 0x2100b900,
++ 0xd11eef03,
++ 0x1e00eeee,
++ 0x209e0000,
++ 0x1c00eeee,
++ 0x209e0000,
++ 0x110f0606,
++ 0x81140b06,
++ 0x13100606,
++ 0x91b01a83,
++ 0x24000025,
++ 0x61100304,
++ 0x24005025,
++ 0xc905e702,
++ 0x24006025,
++ 0x110f0300,
++ 0x81100b00,
++ 0x81120b00,
++ 0x51150611,
++ 0x61100302,
++ 0x24005025,
++ 0x1d01e5e5,
++ 0x51160639,
++ 0x511a0650,
++ 0x511c0657,
++ 0x5118065e,
++ 0x511e0685,
++ 0x61100302,
++ 0x24006025,
++ 0x1f01e5e5,
++ 0x51170634,
++ 0x511b064b,
++ 0x511d0652,
++ 0x51190658,
++ 0x511f067f,
++ 0xc903e708,
++ 0x1d03e7e7,
++ 0x24000060,
++ 0xa1000a60,
++ 0x244000c0,
++ 0x24001580,
++ 0xa0605ce0,
++ 0x21007d00,
++ 0xcf02e7fc,
++ 0x1d02e7e7,
++ 0x1f03e7e7,
++ 0xc904e703,
++ 0x1f08e3e3,
++ 0x79000002,
++ 0x1d08e3e3,
++ 0xc905e705,
++ 0x01682545,
++ 0x9045588d,
++ 0x2302879e,
++ 0x79000004,
++ 0x01902545,
++ 0x9045588d,
++ 0x2302819e,
++ 0x24001872,
++ 0x24000152,
++ 0xb10009e0,
++ 0x108080d3,
++ 0x10c0c092,
++ 0x2400102c,
++ 0x2302c8de,
++ 0x91021c97,
++ 0x91001cd8,
++ 0x91061c98,
++ 0x91041cd9,
++ 0x910a1c99,
++ 0x91081cda,
++ 0x910e1c9a,
++ 0x910c1cdb,
++ 0x91261d9b,
++ 0x91287d9c,
++ 0x23028dde,
++ 0x1f02e7e7,
++ 0x1d03e7e7,
++ 0x7d000070,
++ 0x01902545,
++ 0x9045798d,
++ 0x79000003,
++ 0x01682545,
++ 0x9045788d,
++ 0x0b09eee0,
++ 0x24001472,
++ 0xd108e303,
++ 0xc900e00b,
++ 0x79000002,
++ 0xc910e009,
++ 0xd101e503,
++ 0x2302819e,
++ 0x79000002,
++ 0x2302879e,
++ 0x91013d12,
++ 0x9504bd93,
++ 0x23028dde,
++ 0x7d00005d,
++ 0xd108ee03,
++ 0x1d10e7e7,
++ 0x7900009a,
++ 0x1d11e7e7,
++ 0x79000098,
++ 0x01902545,
++ 0x9045798d,
++ 0x79000003,
++ 0x01682545,
++ 0x9045788d,
++ 0x0b0aeee0,
++ 0x24001072,
++ 0x7f0000e8,
++ 0x01a02545,
++ 0x9045b98d,
++ 0x79000003,
++ 0x01742545,
++ 0x9045b88d,
++ 0x0b01efe0,
++ 0x24001172,
++ 0x7f0000e0,
++ 0x2302d1de,
++ 0x79000002,
++ 0x2302d6de,
++ 0x000c2545,
++ 0x9045198f,
++ 0xd100ef07,
++ 0x1d02efef,
++ 0xc901ef0c,
++ 0xc905ef0b,
++ 0x1d01efef,
++ 0x1d05efef,
++ 0x79000008,
++ 0xd102ef04,
++ 0x1f02efef,
++ 0x8045198f,
++ 0x79000078,
++ 0xd101ef04,
++ 0x1f01efef,
++ 0x1f05efef,
++ 0x8045198f,
++ 0x69180673,
++ 0x01ac2545,
++ 0x2302dbde,
++ 0xd100ef03,
++ 0x23036c9e,
++ 0x7900006e,
++ 0xc800e40b,
++ 0x110f0020,
++ 0x81100b20,
++ 0x100c0c45,
++ 0x61100002,
++ 0x01604545,
++ 0x9045188f,
++ 0xd101ef04,
++ 0x1f01efef,
++ 0x1f07efef,
++ 0x8045188f,
++ 0x01010000,
++ 0x6f1300f4,
++ 0x79000060,
++ 0x2302d1de,
++ 0x79000002,
++ 0x2302d6de,
++ 0x000c2545,
++ 0x9045198f,
++ 0xc903ef05,
++ 0x1d03efef,
++ 0x1f04efef,
++ 0x8045198f,
++ 0x79000056,
++ 0xc904ef55,
++ 0x1d04efef,
++ 0xc901ef04,
++ 0xc906ef03,
++ 0x1d01efef,
++ 0x1d06efef,
++ 0x8045198f,
++ 0x691e064e,
++ 0x01ac2545,
++ 0x2302dbde,
++ 0xc800e40c,
++ 0x110f0020,
++ 0x81100b20,
++ 0x100c0c45,
++ 0x61100002,
++ 0x01604545,
++ 0x9045188f,
++ 0xc901ef05,
++ 0xc908ef04,
++ 0x1d01efef,
++ 0x1d07efef,
++ 0x8045188f,
++ 0x01010000,
++ 0x6f1300f3,
++ 0x7900003d,
++ 0x10ededf0,
++ 0xc908e303,
++ 0x13401010,
++ 0x209e0000,
++ 0x13301010,
++ 0x209e0000,
++ 0x10ededf0,
++ 0xc908e303,
++ 0x130a1010,
++ 0x209e0000,
++ 0x13081010,
++ 0x209e0000,
++ 0x24000266,
++ 0x2400c800,
++ 0x24000020,
++ 0xd108ee17,
++ 0x01012020,
++ 0xc91cff09,
++ 0x6e0020fe,
++ 0xc910e702,
++ 0x20de0000,
++ 0x1f10e7e7,
++ 0x110f0600,
++ 0x11f02727,
++ 0x12002727,
++ 0x20de0000,
++ 0x1d10e7e7,
++ 0x2302b4de,
++ 0x511d0605,
++ 0x511c0602,
++ 0x7900001e,
++ 0x01a62545,
++ 0x79000002,
++ 0x01722545,
++ 0x90451880,
++ 0x01018080,
++ 0x80451880,
++ 0x79000017,
++ 0x01012020,
++ 0xc91dff09,
++ 0x6e0020fe,
++ 0xc911e702,
++ 0x20de0000,
++ 0x1f11e7e7,
++ 0x09040600,
++ 0x110f2727,
++ 0x12002727,
++ 0x20de0000,
++ 0x1d11e7e7,
++ 0x2302b9de,
++ 0x7f0000ea,
++ 0x81b82786,
++ 0x240000d1,
++ 0x87c06790,
++ 0x81bc2780,
++ 0x20de0000,
++ 0x81b82986,
++ 0x87c06990,
++ 0x81bc2980,
++ 0x20de0000,
++ 0x91b43a88,
++ 0x2301029e,
++ 0x51150608,
++ 0xc908e305,
++ 0x51120303,
++ 0x01010303,
++ 0x79000002,
++ 0x24000003,
++ 0x01012323,
++ 0x81b01a83,
++ 0x21007d00,
++ 0x902cfc88,
++ 0x10c8c893,
++ 0x108888d4,
++ 0x10c9c994,
++ 0x108989d5,
++ 0x10caca95,
++ 0x108a8ad6,
++ 0x10cbcb96,
++ 0x108b8bd7,
++ 0xd108e303,
++ 0x2400a80c,
++ 0x20de0000,
++ 0x2400aa0c,
++ 0x20de0000,
++ 0xd108e303,
++ 0x24007c0c,
++ 0x20de0000,
++ 0x24007e0c,
++ 0x20de0000,
++ 0x24000000,
++ 0x90453904,
++ 0xd108e303,
++ 0x24007c0c,
++ 0x20de0000,
++ 0x24007e0c,
++ 0x20de0000,
++ 0xb1002fe6,
++ 0x91b82880,
++ 0xc91ce002,
++ 0x209e0000,
++ 0xb1002ee6,
++ 0x69187279,
++ 0xd110f230,
++ 0xc903e769,
++ 0xc90be604,
++ 0xc904e767,
++ 0xd105e766,
++ 0x7900000c,
++ 0xc90ae604,
++ 0xd104e763,
++ 0xd105e762,
++ 0x79000008,
++ 0xc907e604,
++ 0xc904e75f,
++ 0xc905e75e,
++ 0x79000004,
++ 0xc906e65c,
++ 0xd104e75b,
++ 0xc905e75a,
++ 0x91003c80,
++ 0x6897c058,
++ 0x68d88057,
++ 0x91043c80,
++ 0x6898c055,
++ 0x68d98054,
++ 0x91083c80,
++ 0x6899c052,
++ 0x68da8051,
++ 0x910c3c80,
++ 0x689ac04f,
++ 0x68db804e,
++ 0xb10009e0,
++ 0x6892c04c,
++ 0x68d3804b,
++ 0x24000160,
++ 0xa1000a60,
++ 0x244000c0,
++ 0x24001580,
++ 0xa0605ce0,
++ 0x1d03e7e7,
++ 0x109393c8,
++ 0x10d4d488,
++ 0x109494c9,
++ 0x10d5d589,
++ 0x109595ca,
++ 0x10d6d68a,
++ 0x109696cb,
++ 0x10d7d78b,
++ 0x8110fc88,
++ 0x209e0000,
++ 0x91003c80,
++ 0x6893c00c,
++ 0x68d4800b,
++ 0x91043c80,
++ 0x6894c009,
++ 0x68d58008,
++ 0x91083c80,
++ 0x6895c006,
++ 0x68d68005,
++ 0x910c3c80,
++ 0x6896c003,
++ 0x68d78002,
++ 0x79000010,
++ 0x24ffff80,
++ 0x24ffffc0,
++ 0x68809306,
++ 0x68e0f405,
++ 0x68e0f504,
++ 0x68e0f603,
++ 0x6880d702,
++ 0x79000008,
++ 0x24000080,
++ 0x240000c0,
++ 0x68809323,
++ 0x68e0f422,
++ 0x68e0f521,
++ 0x68e0f620,
++ 0x6880d71f,
++ 0x1d10f2f2,
++ 0x2400002c,
++ 0x2302c8de,
++ 0x24000f80,
++ 0x240000c0,
++ 0x0101c0c0,
++ 0xd100e504,
++ 0xc91cff06,
++ 0x6e80c0fd,
++ 0x21016d00,
++ 0xc91dff03,
++ 0x6e80c0fa,
++ 0x21016d00,
++ 0xd104e606,
++ 0xc909e608,
++ 0xb1000ce0,
++ 0x0101e0e0,
++ 0xa0600ce0,
++ 0x79000004,
++ 0xb1000be0,
++ 0x0101e0e0,
++ 0xa0600be0,
++ 0xb1002fe6,
++ 0xd100e504,
++ 0x2302b4de,
++ 0x24000022,
++ 0x209e0000,
++ 0x2302b9de,
++ 0x24000042,
++ 0x209e0000,
++ 0xd104e609,
++ 0x01782545,
++ 0x9045180e,
++ 0x110f0e00,
++ 0x81100b00,
++ 0x2400a445,
++ 0x51002502,
++ 0x01504545,
++ 0x90451888,
++ 0xc909e87d,
++ 0xb1002fe6,
++ 0x1f1fe6e6,
++ 0x10080806,
++ 0x21015f00,
++ 0x6914721b,
++ 0x01782545,
++ 0x2303bade,
++ 0x900c188f,
++ 0x1d02efef,
++ 0xc901ef05,
++ 0xc905ef04,
++ 0x1d01efef,
++ 0x1d05efef,
++ 0x800c188f,
++ 0xc909e66e,
++ 0x2303d0de,
++ 0xc800e40c,
++ 0x110f0020,
++ 0x81100b20,
++ 0x100c0c45,
++ 0x61100002,
++ 0x01604545,
++ 0x9045188f,
++ 0xc901ef05,
++ 0xc907ef04,
++ 0x1d01efef,
++ 0x1d07efef,
++ 0x8045188f,
++ 0x01010000,
++ 0x6f1300f3,
++ 0x7900005e,
++ 0x6910725d,
++ 0x01782545,
++ 0x2303bade,
++ 0x900c188f,
++ 0x1f03efef,
++ 0xd101ef03,
++ 0x1f01efef,
++ 0x1f06efef,
++ 0x800c188f,
++ 0xc909e654,
++ 0x2303d0de,
++ 0xc800e40b,
++ 0x110f0020,
++ 0x81100b20,
++ 0x100c0c45,
++ 0x61100002,
++ 0x01604545,
++ 0x9045188f,
++ 0xd101ef04,
++ 0x1f01efef,
++ 0x1f08efef,
++ 0x8045188f,
++ 0x01010000,
++ 0x6f1300f4,
++ 0x79000045,
++ 0x01782545,
++ 0x9045788e,
++ 0x1d02efef,
++ 0x1d12efef,
++ 0xc905ef04,
++ 0x1d05efef,
++ 0x1d01efef,
++ 0x7900000c,
++ 0xc915ef04,
++ 0x1d15efef,
++ 0x1d11efef,
++ 0x79000008,
++ 0xc907ef04,
++ 0x1d07efef,
++ 0x1d01efef,
++ 0x79000004,
++ 0xc917ef03,
++ 0x1d17efef,
++ 0x1d11efef,
++ 0x017c2545,
++ 0x8045388f,
++ 0x110f0e00,
++ 0x81100b00,
++ 0x2400a845,
++ 0x51002502,
++ 0x01504545,
++ 0x9045388f,
++ 0x1d02efef,
++ 0x1d12efef,
++ 0xc905ef04,
++ 0x1d05efef,
++ 0x1d01efef,
++ 0x79000004,
++ 0xc915ef03,
++ 0x1d15efef,
++ 0x1d11efef,
++ 0x8045388f,
++ 0x7900001f,
++ 0xc909e60d,
++ 0x9045180e,
++ 0x110f0e00,
++ 0x81100b00,
++ 0xc90ae603,
++ 0x2400a80c,
++ 0x79000003,
++ 0xc90be617,
++ 0x2400aa0c,
++ 0x51002503,
++ 0x01500c0c,
++ 0x24005025,
++ 0x20de0000,
++ 0xc904e611,
++ 0xc906e603,
++ 0x24007c0c,
++ 0x79000003,
++ 0xc907e60d,
++ 0x24007e0c,
++ 0x51002502,
++ 0x01600c0c,
++ 0x20de0000,
++ 0x01ac2545,
++ 0x24000000,
++ 0x90453804,
++ 0xd10be603,
++ 0x24007c0c,
++ 0x20de0000,
++ 0x24007e0c,
++ 0x20de0000,
++ 0x209e0000};
+diff -urN linux.old/drivers/atm/sangam_atm/turbodsl.c linux.dev/drivers/atm/sangam_atm/turbodsl.c
+--- linux.old/drivers/atm/sangam_atm/turbodsl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/atm/sangam_atm/turbodsl.c 2005-08-23 04:46:50.111841568 +0200
+@@ -0,0 +1,223 @@
++
++
++/*
++ *
++ * Turbo DSL Implementaion
++ *
++ * Zhicheng Tang ztang@ti.com
++ *
++ * 2002 (c) Texas Instruments Inc.
++ *
++*/
++
++/* defines and variables */
++#define RFC2684_BRIDGED_HDR_SIZE 10
++unsigned char LLC_BRIDGED_HEADER_2684[RFC2684_BRIDGED_HDR_SIZE] =
++ {0xAA, 0xAA, 0x03, 0x00, 0x80, 0xC2, 0x00, 0x07, 0x00, 0x00};
++
++#define RFC2684_ROUTED_HDR_SIZE 6
++unsigned char LLC_ROUTED_HEADER_2684[6] ={0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00};
++
++unsigned long PPP_LLC_HEADER = 0xCF03FEFE;
++
++/* struct definition */
++enum
++{
++ AAL5_ENCAP_PPP_LLC,
++ AAL5_ENCAP_PPP_VCMUX,
++ AAL5_ENCAP_RFC2684_LLC_BRIDGED,
++ AAL5_ENCAP_RFC2684_LLC_ROUTED
++};
++
++/* Etherent header */
++typedef struct _turbodsl_ether_header
++{
++ unsigned char dst_mac_addr[6];
++ unsigned char src_mac_addr[6];
++ unsigned short ether_type;
++} turbodsl_ether_header_t;
++
++
++/* Ip header define */
++typedef struct _turbodsl_ip_header
++{
++
++ unsigned short vit;
++ unsigned short total_length;
++ unsigned short ip_id;
++ unsigned char flag; /* bit 0 = 0, bit1 = don't fragment, bit2=more frag */
++ unsigned char fragment_offset; /* offset include remaining 5 bits above, which make it 13 bits */
++ unsigned char time_to_live;
++ unsigned char protocol;
++ unsigned short checksum;
++ unsigned int src_ip;
++ unsigned int dst_ip;
++} turbodsl_ip_header_t;
++
++/* Arp packet define */
++typedef struct _turbodsl_arp_header
++{
++ unsigned short hardware_type;
++ unsigned short protocol_type;
++ unsigned char h_len;
++ unsigned char p_len;
++ unsigned short operation ;
++ unsigned char snd_hw_address[6];
++ unsigned char snd_pt_address[4];
++ unsigned char dst_hw_address[6];
++ unsigned char dst_pt_address[4];
++} turbodsl_arp_header_t;
++
++#define FIN_FLAG 1
++#define SYN_FLAG 1<<1
++#define RST_FLAG 1<<2
++#define PSH_FLAG 1<<3
++#define ACK_FLAG 1<<4
++#define URG_FLAG 1<<5
++
++typedef struct _turbodsl_tcp_header
++{
++ unsigned short src_port;
++ unsigned short dst_port;
++ unsigned int seq_num;
++ unsigned int ack_num;
++ unsigned char offset; /* only bits 4-7 are for offset */
++ unsigned char flags; /* bits: 0-FIN, 1-SYN, 2-RST, 3-PSH, 4-ACK, 5-URG */
++ unsigned short windows;
++ unsigned short checksum;
++ unsigned short urgent_ptr;
++} turbodsl_tcp_header_t;
++
++
++
++/***************************************************************************
++ * Function: turbodsl_memory_compare
++ * Descripation: Memory compare
++ ****************************************************************************/
++int turbodsl_memory_compare(unsigned char *pIn, unsigned char *pOut, unsigned int len)
++ {
++ int i;
++
++ for(i=0;i<(int)len; i++)
++ {
++ if(pIn[i] != pOut[i])
++ return 0;
++ }
++ return 1;
++ }
++
++/***************************************************************************
++ * Function: turbodsl_check_aal5_encap_type
++ * Descripation: Determine AAL5 Encapsulation type
++ * Input:
++ * unsigned char *pData, AAL5 Packet buffer pointer
++ ****************************************************************************/
++int turbodsl_check_aal5_encap_type(unsigned char *pData)
++ {
++
++ if(turbodsl_memory_compare(pData, LLC_BRIDGED_HEADER_2684, 6))
++ return AAL5_ENCAP_RFC2684_LLC_BRIDGED;
++ if(turbodsl_memory_compare(pData, LLC_ROUTED_HEADER_2684, 6))
++ return AAL5_ENCAP_RFC2684_LLC_ROUTED;
++ if(turbodsl_memory_compare(pData, (unsigned char *)&PPP_LLC_HEADER, sizeof(PPP_LLC_HEADER)))
++ return AAL5_ENCAP_PPP_LLC;
++
++ return AAL5_ENCAP_PPP_VCMUX;
++ }
++
++/***************************************************************************
++ * Function: turbodsl_check_priority_type
++ * Descripation: Determine AAL5 Encapsulation type
++ * Input:
++ * unsigned char *pData, AAL5 Packet buffer pointer.
++ * short vpi, VPI.
++ * int vci, VCI
++ ****************************************************************************/
++int turbodsl_check_priority_type(unsigned char *pData)
++ {
++ int encap;
++ unsigned char *pP;
++ unsigned short etherType;
++ turbodsl_ip_header_t *pIp;
++ turbodsl_tcp_header_t *pTcp;
++ unsigned short ip_length;
++
++ dprintf(2, "turbodsl_check_priority_type ==>\n");
++
++ encap = turbodsl_check_aal5_encap_type(pData);
++ pP = pData;
++
++ switch(encap)
++ {
++ case AAL5_ENCAP_RFC2684_LLC_BRIDGED:
++ pP += RFC2684_BRIDGED_HDR_SIZE; //skip off aal5 encap
++ pP += 12; //skip of mac address
++ etherType = *(unsigned short *)pP;
++ if(etherType != 0x6488 && etherType != 0x0008)
++ {
++ //Not an IP packet
++ return 1;
++ }
++
++ pP +=2; //skip ether type
++ if(etherType == 0x6488)
++ {
++ pP += 6;
++ }
++ break;
++ case AAL5_ENCAP_RFC2684_LLC_ROUTED:
++ pP += RFC2684_ROUTED_HDR_SIZE; //skip of encap
++ pP += 2; //skip ether type
++ break;
++ case AAL5_ENCAP_PPP_LLC:
++ pP += sizeof(PPP_LLC_HEADER);
++ if(*pP == 0xff && *(pP+1) == 0x03) //ppp hdlc header
++ pP += 2;
++ break;
++ case AAL5_ENCAP_PPP_VCMUX:
++ if(*pP == 0xff && *(pP+1) == 0x03) //ppp hdlc header
++ pP += 2;
++ break;
++ default:
++ return 1;
++ }
++
++ pIp = (turbodsl_ip_header_t *)pP;
++ if(pIp->vit != 0x0045)
++ {
++ //Not a IP packet
++ return 1;
++ }
++
++ if(pIp->protocol != 0x06)
++ {
++ //not tcp packet
++ return 1;
++ }
++
++ pTcp = (turbodsl_tcp_header_t *)(pP + sizeof(turbodsl_ip_header_t));
++
++ ip_length = (pIp->total_length>>8) + (pIp->total_length<<8);
++
++ if((pTcp->flags & ACK_FLAG) && ip_length <=40)
++ return 0;
++
++ return 1;
++ }
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
++
+diff -urN linux.old/include/linux/atmdev.h linux.dev/include/linux/atmdev.h
+--- linux.old/include/linux/atmdev.h 2005-08-22 23:18:37.812526104 +0200
++++ linux.dev/include/linux/atmdev.h 2005-08-23 06:33:33.425389944 +0200
+@@ -30,6 +30,9 @@
+ #define ATM_DS3_PCR (8000*12)
+ /* DS3: 12 cells in a 125 usec time slot */
+
++#define ATM_PDU_OVHD 0 /* number of bytes to charge against buffer
++ quota per PDU */
++
+ #define ATM_SD(s) ((s)->sk->protinfo.af_atm)
+
+
+@@ -94,7 +97,8 @@
+ /* set backend handler */
+ #define ATM_NEWBACKENDIF _IOW('a',ATMIOC_SPECIAL+3,atm_backend_t)
+ /* use backend to make new if */
+-
++#define ATM_STOPTX _IOW('a',ATMIOC_SPECIAL+4,struct atmif_sioc)
++ /* Stop Tx on Sangam DSL */
+ /*
+ * These are backend handkers that can be set via the ATM_SETBACKEND call
+ * above. In the future we may support dynamic loading of these - for now,
+@@ -199,7 +203,9 @@
+ "SESSION", "HASSAP", "BOUND", "CLOSE"
+
+
+-#ifdef __KERNEL__
++#ifndef __KERNEL__
++#undef __AAL_STAT_ITEMS
++#else
+
+ #include <linux/sched.h> /* wait_queue_head_t */
+ #include <linux/time.h> /* struct timeval */
+@@ -291,6 +297,7 @@
+ int (*send)(struct atm_vcc *vcc,struct sk_buff *skb);
+ void *dev_data; /* per-device data */
+ void *proto_data; /* per-protocol data */
++ struct timeval timestamp; /* AAL timestamps */
+ struct k_atm_aal_stats *stats; /* pointer to AAL stats group */
+ wait_queue_head_t sleep; /* if socket is busy */
+ struct sock *sk; /* socket backpointer */
+@@ -333,13 +340,14 @@
+ struct k_atm_dev_stats stats; /* statistics */
+ char signal; /* signal status (ATM_PHY_SIG_*) */
+ int link_rate; /* link rate (default: OC3) */
+- atomic_t refcnt; /* reference count */
+- spinlock_t lock; /* protect internal members */
++ atomic_t refcnt; /* reference count */
++ spinlock_t lock; /* protect internal members */
+ #ifdef CONFIG_PROC_FS
+ struct proc_dir_entry *proc_entry; /* proc entry */
+ char *proc_name; /* proc entry name */
+ #endif
+- struct list_head dev_list; /* linkage */
++ struct list_head dev_list; /* linkage */
++
+ };
+
+
diff --git a/openwrt/target/linux/ar7-2.4/patches/005-wdt_driver.patch b/openwrt/target/linux/ar7-2.4/patches/005-wdt_driver.patch
new file mode 100644
index 0000000000..9b01a353da
--- /dev/null
+++ b/openwrt/target/linux/ar7-2.4/patches/005-wdt_driver.patch
@@ -0,0 +1,392 @@
+diff -ruN linux-2.4.30-patch006/drivers/char/ar7_wdt.c linux-2.4.30-patch007/drivers/char/ar7_wdt.c
+--- linux-2.4.30-patch006/drivers/char/ar7_wdt.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.30-patch007/drivers/char/ar7_wdt.c 2005-10-27 09:39:40.000000000 +0200
+@@ -0,0 +1,335 @@
++/* linux/drivers/char/ar7_wdt.c
++
++ TI AR7 watch dog timer support
++
++ Copyright (c) 2005 Enrik Berkhan <Enrik.Berkhan@akk.org>
++
++ Som code taken from:
++ National Semiconductor SCx200 Watchdog support
++ Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
++
++ This program is free software; you can redistribute it and/or
++ modify it under the terms of the GNU General Public License as
++ published by the Free Software Foundation; either version 2 of the
++ License, or (at your option) any later version.
++
++ The author(s) of this software shall not be held liable for damages
++ of any nature resulting due to the use of this software. This
++ software is provided AS-IS with no warranties. */
++
++#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/miscdevice.h>
++#include <linux/watchdog.h>
++#include <linux/notifier.h>
++#include <linux/reboot.h>
++#include <linux/ioport.h>
++
++#include <asm/uaccess.h>
++
++#include <asm/ar7/avalanche_misc.h>
++#include <asm/ar7/sangam.h>
++
++#define NAME "ar7_wdt"
++#define LONGNAME "TI AR7 Watchdog Timer"
++
++MODULE_AUTHOR("Enrik Berkhan <Enrik.Berkhan@akk.org>");
++MODULE_DESCRIPTION(LONGNAME);
++MODULE_LICENSE("GPL");
++
++#ifndef CONFIG_WATCHDOG_NOWAYOUT
++#define CONFIG_WATCHDOG_NOWAYOUT 0
++#endif
++
++static int margin = 60;
++MODULE_PARM(margin, "i");
++MODULE_PARM_DESC(margin, "Watchdog margin in seconds (1 - ~68)");
++
++static int nowayout = CONFIG_WATCHDOG_NOWAYOUT;
++MODULE_PARM(nowayout, "i");
++MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
++
++typedef struct {
++ uint32_t kick_lock;
++ uint32_t kick;
++ uint32_t change_lock;
++ uint32_t change ;
++ uint32_t disable_lock;
++ uint32_t disable;
++ uint32_t prescale_lock;
++ uint32_t prescale;
++} ar7_wdt_t;
++
++volatile ar7_wdt_t *ar7_wdt = (ar7_wdt_t *)AVALANCHE_WATCHDOG_TIMER_BASE;
++
++static struct semaphore open_semaphore;
++static unsigned expect_close;
++
++/* XXX correct? assumed to be sysfreq/2. get this dynamically ... */
++#define vbus_freq 62500000
++
++/* XXX currently fixed, allows max margin ~68.72 secs */
++#define prescale_value 0xFFFF
++
++static void ar7_wdt_kick(uint32_t value)
++{
++ ar7_wdt->kick_lock = 0x5555;
++ if ((ar7_wdt->kick_lock & 3) == 1) {
++ ar7_wdt->kick_lock = 0xAAAA;
++ if ((ar7_wdt->kick_lock & 3) == 3) {
++ ar7_wdt->kick = value;
++ return;
++ }
++ }
++ printk(KERN_ERR NAME "failed to unlock WDT kick reg\n");
++}
++
++static void ar7_wdt_prescale(uint32_t value)
++{
++ ar7_wdt->prescale_lock = 0x5A5A;
++ if ((ar7_wdt->prescale_lock & 3) == 1) {
++ ar7_wdt->prescale_lock = 0xA5A5;
++ if ((ar7_wdt->prescale_lock & 3) == 3) {
++ ar7_wdt->prescale = value;
++ return;
++ }
++ }
++ printk(KERN_ERR NAME "failed to unlock WDT prescale reg\n");
++}
++
++static void ar7_wdt_change(uint32_t value)
++{
++ ar7_wdt->change_lock = 0x6666;
++ if ((ar7_wdt->change_lock & 3) == 1) {
++ ar7_wdt->change_lock = 0xBBBB;
++ if ((ar7_wdt->change_lock & 3) == 3) {
++ ar7_wdt->change = value;
++ return;
++ }
++ }
++ printk(KERN_ERR NAME "failed to unlock WDT change reg\n");
++}
++
++static void ar7_wdt_disable(uint32_t value)
++{
++ ar7_wdt->disable_lock = 0x7777;
++ if ((ar7_wdt->disable_lock & 3) == 1) {
++ ar7_wdt->disable_lock = 0xCCCC;
++ if ((ar7_wdt->disable_lock & 3) == 2) {
++ ar7_wdt->disable_lock = 0xDDDD;
++ if ((ar7_wdt->disable_lock & 3) == 3) {
++ ar7_wdt->disable = value;
++ return;
++ }
++ }
++ }
++ printk(KERN_ERR NAME "failed to unlock WDT disable reg\n");
++ return;
++}
++
++static void ar7_wdt_update_margin(int new_margin)
++{
++ uint32_t change;
++
++ change = new_margin * (vbus_freq / prescale_value);
++ if (change < 1) change = 1;
++ if (change > 0xFFFF) change = 0xFFFF;
++ ar7_wdt_change(change);
++ margin = change * prescale_value / vbus_freq;
++ printk(KERN_INFO NAME
++ ": timer margin %d seconds (prescale %d, change %d, freq %d)\n",
++ margin, prescale_value, change, vbus_freq);
++}
++
++static void ar7_wdt_enable_wdt(void)
++{
++ printk(KERN_DEBUG NAME ": enabling watchdog timer\n");
++ ar7_wdt_disable(1);
++ ar7_wdt_kick(1);
++}
++
++static void ar7_wdt_disable_wdt(void)
++{
++ printk(KERN_DEBUG NAME ": disabling watchdog timer\n");
++ ar7_wdt_disable(0);
++}
++
++static int ar7_wdt_open(struct inode *inode, struct file *file)
++{
++ /* only allow one at a time */
++ if (down_trylock(&open_semaphore))
++ return -EBUSY;
++ ar7_wdt_enable_wdt();
++ expect_close = 0;
++
++ return 0;
++}
++
++static int ar7_wdt_release(struct inode *inode, struct file *file)
++{
++ if (!expect_close) {
++ printk(KERN_WARNING NAME ": watchdog device closed unexpectedly, will not disable the watchdog timer\n");
++ } else if (!nowayout) {
++ ar7_wdt_disable_wdt();
++ }
++ up(&open_semaphore);
++
++ return 0;
++}
++
++static int ar7_wdt_notify_sys(struct notifier_block *this,
++ unsigned long code, void *unused)
++{
++ if (code == SYS_HALT || code == SYS_POWER_OFF)
++ if (!nowayout)
++ ar7_wdt_disable_wdt();
++
++ return NOTIFY_DONE;
++}
++
++static struct notifier_block ar7_wdt_notifier =
++{
++ .notifier_call = ar7_wdt_notify_sys
++};
++
++static ssize_t ar7_wdt_write(struct file *file, const char *data,
++ size_t len, loff_t *ppos)
++{
++ if (ppos != &file->f_pos)
++ return -ESPIPE;
++
++ /* check for a magic close character */
++ if (len)
++ {
++ size_t i;
++
++ ar7_wdt_kick(1);
++
++ expect_close = 0;
++ for (i = 0; i < len; ++i) {
++ char c;
++ if (get_user(c, data+i))
++ return -EFAULT;
++ if (c == 'V')
++ expect_close = 1;
++ }
++
++ }
++ return len;
++}
++
++static int ar7_wdt_ioctl(struct inode *inode, struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ static struct watchdog_info ident = {
++ .identity = LONGNAME,
++ .firmware_version = 1,
++ .options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING),
++ };
++ int new_margin;
++
++ switch (cmd) {
++ default:
++ return -ENOTTY;
++ case WDIOC_GETSUPPORT:
++ if(copy_to_user((struct watchdog_info *)arg, &ident,
++ sizeof(ident)))
++ return -EFAULT;
++ return 0;
++ case WDIOC_GETSTATUS:
++ case WDIOC_GETBOOTSTATUS:
++ if (put_user(0, (int *)arg))
++ return -EFAULT;
++ return 0;
++ case WDIOC_KEEPALIVE:
++ ar7_wdt_kick(1);
++ return 0;
++ case WDIOC_SETTIMEOUT:
++ if (get_user(new_margin, (int *)arg))
++ return -EFAULT;
++ if (new_margin < 1)
++ return -EINVAL;
++
++ ar7_wdt_update_margin(new_margin);
++ ar7_wdt_kick(1);
++
++ case WDIOC_GETTIMEOUT:
++ if (put_user(margin, (int *)arg))
++ return -EFAULT;
++ return 0;
++ }
++}
++
++static struct file_operations ar7_wdt_fops = {
++ .owner = THIS_MODULE,
++ .write = ar7_wdt_write,
++ .ioctl = ar7_wdt_ioctl,
++ .open = ar7_wdt_open,
++ .release = ar7_wdt_release,
++};
++
++static struct miscdevice ar7_wdt_miscdev = {
++ .minor = WATCHDOG_MINOR,
++ .name = "watchdog",
++ .fops = &ar7_wdt_fops,
++};
++
++static __initdata char *last_initiator[] = {
++ [HARDWARE_RESET] = "hardware reset",
++ [SOFTWARE_RESET0] = "SW0 software reset",
++ [SOFTWARE_RESET1] = "SW1 software reset",
++ [WATCHDOG_RESET] = "watchdog"
++};
++
++static int __init ar7_wdt_init(void)
++{
++ int r;
++
++ if (!request_mem_region(AVALANCHE_WATCHDOG_TIMER_BASE,
++ sizeof(ar7_wdt_t), LONGNAME)) {
++ printk(KERN_WARNING NAME ": watchdog I/O region busy\n");
++ return -EBUSY;
++ }
++
++ printk(KERN_INFO NAME ": last system reset initiated by %s\n",
++ last_initiator[avalanche_get_sys_last_reset_status()]);
++
++
++ ar7_wdt_disable_wdt();
++ ar7_wdt_prescale(prescale_value);
++ ar7_wdt_update_margin(margin);
++
++ sema_init(&open_semaphore, 1);
++
++ r = misc_register(&ar7_wdt_miscdev);
++ if (r) {
++ printk(KERN_ERR NAME ": unable to register misc device\n");
++ release_mem_region(AVALANCHE_WATCHDOG_TIMER_BASE,
++ sizeof(ar7_wdt_t));
++ return r;
++ }
++
++ r = register_reboot_notifier(&ar7_wdt_notifier);
++ if (r) {
++ printk(KERN_ERR NAME ": unable to register reboot notifier\n");
++ misc_deregister(&ar7_wdt_miscdev);
++ release_mem_region(AVALANCHE_WATCHDOG_TIMER_BASE,
++ sizeof(ar7_wdt_t));
++ return r;
++ }
++
++ return 0;
++}
++
++static void __exit ar7_wdt_cleanup(void)
++{
++ unregister_reboot_notifier(&ar7_wdt_notifier);
++ misc_deregister(&ar7_wdt_miscdev);
++ release_mem_region(AVALANCHE_WATCHDOG_TIMER_BASE, sizeof(ar7_wdt_t));
++}
++
++module_init(ar7_wdt_init);
++module_exit(ar7_wdt_cleanup);
+diff -ruN linux-2.4.30-patch006/drivers/char/Config.in linux-2.4.30-patch007/drivers/char/Config.in
+--- linux-2.4.30-patch006/drivers/char/Config.in 2005-10-27 11:25:29.000000000 +0200
++++ linux-2.4.30-patch007/drivers/char/Config.in 2005-10-27 11:17:32.000000000 +0200
+@@ -251,6 +251,9 @@
+ bool 'Watchdog Timer Support' CONFIG_WATCHDOG
+ if [ "$CONFIG_WATCHDOG" != "n" ]; then
+ bool ' Disable watchdog shutdown on close' CONFIG_WATCHDOG_NOWAYOUT
++ if [ "$CONFIG_AR7" = "y" ] ; then
++ tristate ' TI AR7 Watchdog Timer' CONFIG_AR7_WDT
++ else
+ tristate ' Acquire SBC Watchdog Timer' CONFIG_ACQUIRE_WDT
+ tristate ' Advantech SBC Watchdog Timer' CONFIG_ADVANTECH_WDT
+ tristate ' ALi M7101 PMU on ALi 1535D+ Watchdog Timer' CONFIG_ALIM1535_WDT
+@@ -271,7 +274,6 @@
+ tristate ' SBC-60XX Watchdog Timer' CONFIG_60XX_WDT
+ dep_tristate ' SC1200 Watchdog Timer (EXPERIMENTAL)' CONFIG_SC1200_WDT $CONFIG_EXPERIMENTAL
+ tristate ' NatSemi SCx200 Watchdog' CONFIG_SCx200_WDT
+- tristate ' Software Watchdog' CONFIG_SOFT_WATCHDOG
+ tristate ' W83877F (EMACS) Watchdog Timer' CONFIG_W83877F_WDT
+ tristate ' WDT Watchdog timer' CONFIG_WDT
+ tristate ' WDT PCI Watchdog timer' CONFIG_WDTPCI
+@@ -282,6 +284,8 @@
+ fi
+ fi
+ tristate ' ZF MachZ Watchdog' CONFIG_MACHZ_WDT
++ fi
++ tristate ' Software Watchdog' CONFIG_SOFT_WATCHDOG
+ if [ "$CONFIG_SGI_IP22" = "y" ]; then
+ dep_tristate ' Indy/I2 Hardware Watchdog' CONFIG_INDYDOG $CONFIG_SGI_IP22
+ fi
+diff -ruN linux-2.4.30-patch006/drivers/char/Makefile linux-2.4.30-patch007/drivers/char/Makefile
+--- linux-2.4.30-patch006/drivers/char/Makefile 2005-10-27 11:19:38.000000000 +0200
++++ linux-2.4.30-patch007/drivers/char/Makefile 2005-10-27 09:39:40.000000000 +0200
+@@ -342,6 +342,7 @@
+ obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
+ obj-$(CONFIG_INDYDOG) += indydog.o
+ obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
++obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
+
+ subdir-$(CONFIG_MWAVE) += mwave
+ ifeq ($(CONFIG_MWAVE),y)
+diff -ruN linux-2.4.30-patch006/include/asm-mips/ar7/sangam.h linux-2.4.30-patch007/include/asm-mips/ar7/sangam.h
+--- linux-2.4.30-patch006/include/asm-mips/ar7/sangam.h 2005-10-27 11:25:51.000000000 +0200
++++ linux-2.4.30-patch007/include/asm-mips/ar7/sangam.h 2005-10-27 11:13:37.000000000 +0200
+@@ -152,7 +152,7 @@
+ #define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
+ #define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
+ #define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
+-#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
++#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611608))
+
+ #define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
+ #define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
diff --git a/openwrt/target/linux/ar7-2.4/patches/006-sched_use_tsc.patch b/openwrt/target/linux/ar7-2.4/patches/006-sched_use_tsc.patch
new file mode 100644
index 0000000000..5b64310738
--- /dev/null
+++ b/openwrt/target/linux/ar7-2.4/patches/006-sched_use_tsc.patch
@@ -0,0 +1,84 @@
+diff -urN linux.old/arch/mips/kernel/time.c linux.dev/arch/mips/kernel/time.c
+--- linux.old/arch/mips/kernel/time.c 2005-11-14 11:06:38.661262000 +0100
++++ linux.dev/arch/mips/kernel/time.c 2005-11-15 20:02:50.059676750 +0100
+@@ -151,6 +151,27 @@
+ unsigned int (*mips_hpt_read)(void);
+ void (*mips_hpt_init)(unsigned int);
+
++extern __u32 get_htscl(void)
++{
++ return timerhi;
++}
++
++static __u64 tscll_last = 0;
++
++extern __u64 get_tscll(void)
++{
++ __u64 h = (__u64) timerhi;
++ __u32 c = read_c0_count();
++
++ h <<= 32;
++ h += c;
++
++ while (h < tscll_last)
++ h += (((__u64) 1) << 32);
++
++ tscll_last = h;
++ return h;
++}
+
+ /*
+ * timeofday services, for syscalls.
+@@ -761,3 +782,5 @@
+ EXPORT_SYMBOL(to_tm);
+ EXPORT_SYMBOL(rtc_set_time);
+ EXPORT_SYMBOL(rtc_get_time);
++EXPORT_SYMBOL(get_htscl);
++EXPORT_SYMBOL(get_tscll);
+diff -urN linux.old/include/asm-mips/timex.h linux.dev/include/asm-mips/timex.h
+--- linux.old/include/asm-mips/timex.h 2005-11-14 11:06:38.685263500 +0100
++++ linux.dev/include/asm-mips/timex.h 2005-11-14 11:02:21.069163500 +0100
+@@ -31,6 +31,19 @@
+ return read_c0_count();
+ }
+
++extern __u32 get_htscl(void);
++extern __u64 get_tscll(void);
++
++#define rdtsc(low, high) \
++ high = get_htscl(); \
++ low = read_c0_count();
++
++#define rdtscl(low) \
++ low = read_c0_count();
++
++#define rdtscll(val) \
++ val = get_tscll();
++
+ #define vxtime_lock() do {} while (0)
+ #define vxtime_unlock() do {} while (0)
+
+diff -urN linux.old/include/net/pkt_sched.h linux.dev/include/net/pkt_sched.h
+--- linux.old/include/net/pkt_sched.h 2005-11-14 11:06:38.709265000 +0100
++++ linux.dev/include/net/pkt_sched.h 2005-11-14 11:02:21.069163500 +0100
+@@ -5,7 +5,11 @@
+ #define PSCHED_JIFFIES 2
+ #define PSCHED_CPU 3
+
++#ifdef __mips__
++#define PSCHED_CLOCK_SOURCE PSCHED_CPU
++#else
+ #define PSCHED_CLOCK_SOURCE PSCHED_JIFFIES
++#endif
+
+ #include <linux/config.h>
+ #include <linux/types.h>
+@@ -271,7 +275,7 @@
+ #define PSCHED_US2JIFFIE(delay) (((delay)+psched_clock_per_hz-1)/psched_clock_per_hz)
+ #define PSCHED_JIFFIE2US(delay) ((delay)*psched_clock_per_hz)
+
+-#ifdef CONFIG_X86_TSC
++#if defined(CONFIG_X86_TSC) || defined(__mips__)
+
+ #define PSCHED_GET_TIME(stamp) \
+ ({ u64 __cur; \
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-06 00:21:28 +0000