diff options
| author | luka <luka@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-12-17 02:47:15 +0000 |
|---|---|---|
| committer | luka <luka@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-12-17 02:47:15 +0000 |
| commit | 1325556d31df8022ca3cfc8ad035ad56d978cbd8 (patch) | |
| tree | 869d7f0c10c490fcd3262f3a0712f3108dbafb8f | |
| parent | 2b2956250905a4139c6debeb6fc05bd65e4f2d82 (diff) | |
imx6: drop upstreamed patch
Signed-off-by: Luka Perkov <luka@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39109 3c298f89-4303-0410-b956-a3cf2f4a3e73
| -rw-r--r-- | target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch b/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch deleted file mode 100644 index 8ea02f6dc6..0000000000 --- a/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 9b3d423707c3b1f6633be1be7e959623e10c596b Mon Sep 17 00:00:00 2001 -From: Jiada Wang <jiada_wang@mentor.com> -Date: Wed, 30 Oct 2013 04:25:51 -0700 -Subject: [PATCH] ARM: i.MX6q: fix the wrong parent of can_root clock - -instead of pll3_usb_otg the parent of can_root clock -should be pll3_60m. - -Signed-off-by: Jiada Wang <jiada_wang@mentor.com> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> ---- - arch/arm/mach-imx/clk-imx6q.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/mach-imx/clk-imx6q.c -+++ b/arch/arm/mach-imx/clk-imx6q.c -@@ -442,7 +442,7 @@ int __init mx6q_clocks_init(void) - clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); - clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); - clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); -- clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); -+ clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); - clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); - clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); - clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); |