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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-11-29 20:18:43 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-11-29 20:18:43 +0000
commit2b4757410dabacee09fa17f4a2c5f08428e00be6 (patch)
tree041955805e54370450073d4d851c16d45eedc834
parent365c0a909b2e3316928fa633d1755b0bd2e06dae (diff)
ag71xx: add F1E specific feature bit definitions to AR934X register file
The F1E Phy (AR8035?) requires additional bits to be set in order to provide a fast and reliable connection over gigabit links. When enabled, the link doesn't suffer anymore from a small package loss under load and the performance is improved quite a bit as well. (203 mbit/s vs 112 mbit/s, iperf tcp). Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Patchwork: http://patchwork.openwrt.org/patch/4460/ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38948 3c298f89-4303-0410-b956-a3cf2f4a3e73
-rw-r--r--target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch4
1 files changed, 3 insertions, 1 deletions
diff --git a/target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch
index 014c7696af..4812a624f2 100644
--- a/target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch
@@ -207,7 +207,7 @@
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
-@@ -561,4 +664,144 @@
+@@ -561,4 +664,146 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
@@ -341,6 +341,8 @@
+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
++#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
++#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
+
+/*
+ * QCA955X GMAC Interface