targets += $(dtb-y)
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
-@@ -0,0 +1,20 @@
+@@ -0,0 +1,35 @@
+/*
+ * Broadcom BCM470X / BCM5301X arm platform code.
++ * DTS for Netgear R6250 V1
+ *
+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+#include "bcm4708.dtsi"
+
+/ {
-+ compatible = "netgear,r6250v1", "broadcom,bcm4708";
++ compatible = "netgear,r6250v1", "brcm,bcm4708";
+ model = "Netgear R6250 V1 (BCM4708)";
+
++ chosen {
++ bootargs = "console=ttyS0,115200";
++ };
++
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
++
++ chipcommonA {
++ uart0: serial@0300 {
++ status = "okay";
++ };
++
++ uart1: serial@0400 {
++ status = "okay";
++ };
++ };
+};
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708.dtsi
-@@ -0,0 +1,100 @@
+@@ -0,0 +1,34 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
++ * DTS for BCM4708 SoC.
+ *
-+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
++ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/interrupt-controller/irq.h>
-+
-+#include "skeleton.dtsi"
++#include "bcm5301x.dtsi"
+
+/ {
-+ compatible = "broadcom,bcm4708";
-+ model = "Broadcom BCM4708";
-+ interrupt-parent = <&gic>;
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200 debug earlyprintk";
-+ };
++ compatible = "brcm,bcm4708";
+
+ cpus {
+ #address-cells = <1>;
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
-+ reg = <0>;
++ reg = <0x0>;
+ };
++
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
-+ reg = <1>;
++ reg = <0x1>;
+ };
+ };
+
-+ clocks {
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -0,0 +1,95 @@
++/*
++ * Broadcom BCM470X / BCM5301X ARM platform code.
++ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
++ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
++ *
++ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include "skeleton.dtsi"
++
++/ {
++ interrupt-parent = <&gic>;
++
++ chipcommonA {
++ compatible = "simple-bus";
++ ranges = <0x00000000 0x18000000 0x00001000>;
+ #address-cells = <1>;
-+ #size-cells = <0>;
++ #size-cells = <1>;
++
++ uart0: serial@0300 {
++ compatible = "ns16550";
++ reg = <0x0300 0x100>;
++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++ clock-frequency = <100000000>;
++ status = "disabled";
++ };
+
-+ clk_periph: periph {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
++ uart1: serial@0400 {
++ compatible = "ns16550";
++ reg = <0x0400 0x100>;
++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++ clock-frequency = <100000000>;
++ status = "disabled";
+ };
+ };
+
-+ uart@18000300 {
-+ compatible = "ns16550";
-+ reg = <0x18000300 0x100>;
-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-frequency = <100000000>;
-+ };
++ mpcore {
++ compatible = "simple-bus";
++ ranges = <0x00000000 0x19020000 0x00003000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+
-+ uart@18000400 {
-+ compatible = "ns16550";
-+ reg = <0x18000400 0x100>;
-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-frequency = <100000000>;
-+ };
++ scu@0000 {
++ compatible = "arm,cortex-a9-scu";
++ reg = <0x0000 0x100>;
++ };
+
-+ gic: interrupt-controller@19021000 {
-+ compatible = "arm,cortex-a9-gic";
-+ #interrupt-cells = <3>;
-+ #address-cells = <0>;
-+ interrupt-controller;
-+ reg = <0x19021000 0x1000>,
-+ <0x19020100 0x100>;
-+ };
++ timer@0200 {
++ compatible = "arm,cortex-a9-global-timer";
++ reg = <0x0200 0x100>;
++ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clk_periph>;
++ };
+
-+ timer@19020200 {
-+ compatible = "arm,cortex-a9-global-timer";
-+ reg = <0x19020200 0x100>;
-+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clk_periph>;
-+ };
++ local-timer@0600 {
++ compatible = "arm,cortex-a9-twd-timer";
++ reg = <0x0600 0x100>;
++ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clk_periph>;
++ };
+
-+ local-timer@19020600 {
-+ compatible = "arm,cortex-a9-twd-timer";
-+ reg = <0x19020600 0x100>;
-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clk_periph>;
-+ };
++ gic: interrupt-controller@1000 {
++ compatible = "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0x1000 0x1000>,
++ <0x0100 0x100>;
++ };
+
-+ L2: cache-controller@19022000 {
-+ compatible = "arm,pl310-cache";
-+ reg = <0x19022000 0x1000>;
-+ cache-unified;
-+ cache-level = <2>;
++ L2: cache-controller@2000 {
++ compatible = "arm,pl310-cache";
++ reg = <0x2000 0x1000>;
++ cache-unified;
++ cache-level = <2>;
++ };
+ };
+
-+ scu@19020000 {
-+ compatible = "arm,cortex-a9-scu";
-+ reg = <0x19020000 0x100>;
++ clocks {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /* As long as we do not have a real clock driver us this
++ * fixed clock */
++ clk_periph: periph {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <400000000>;
++ };
+ };
+};
--- /dev/null
+#include <asm/hardware/debug-8250.S>
--- /dev/null
+++ b/arch/arm/mach-bcm53xx/Kconfig
-@@ -0,0 +1,26 @@
+@@ -0,0 +1,25 @@
+config ARCH_BCM_5301X
+ bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+ depends on MMU
+ select HAVE_SMP
+ select COMMON_CLK
+ select GENERIC_CLOCKEVENTS
-+ select GENERIC_TIME
+ select ARM_GLOBAL_TIMER
+ select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+ select MIGHT_HAVE_PCI
+obj-y += bcm53xx.o
--- /dev/null
+++ b/arch/arm/mach-bcm53xx/bcm53xx.c
-@@ -0,0 +1,60 @@
+@@ -0,0 +1,70 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ *
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
-+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <asm/mach/arch.h>
-+#include <asm/mach/map.h>
++#include <asm/siginfo.h>
+#include <asm/signal.h>
+
++
++static bool first_fault = true;
++
+static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
+ struct pt_regs *regs)
+{
-+ /*
-+ * These happen for no good reason, possibly left over from CFE
-+ */
-+ pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
++ if (fsr == 0x1c06 && first_fault) {
++ first_fault = false;
++
++ /*
++ * These faults with code 0x1c06 happens for no good reason,
++ * possibly left over from the CFE boot loader.
++ */
++ pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
+ addr, fsr);
+
-+ /* Returning non-zero causes fault display and panic */
-+ return 0;
++ /* Returning non-zero causes fault display and panic */
++ return 0;
++ }
++
++ /* Others should cause a fault */
++ return 1;
+}
+
+static void __init bcm5301x_init_early(void)
+{
+ /* Install our hook */
-+ hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, 0,
++ hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
+ "imprecise external abort");
+}
+
+}
+
+static const char __initconst *bcm5301x_dt_compat[] = {
-+ "broadcom,bcm4708",
++ "brcm,bcm4708",
+ NULL,
+};
+
projects / openwrt.git / blobdiff