[kernel] refresh patches

[openwrt.git] / target / linux / atheros / patches-2.6.28 / 100-board.patch

diff --git a/target/linux/atheros/patches-2.6.28/100-board.patch b/target/linux/atheros/patches-2.6.28/100-board.patch
index 2f7bb5b196eb3371b8cca304e0d902fd5152dd67..38ac2ad173c70f9aaa16a46f358f69a1ae8ac41c 100644 (file)
--- a/target/linux/atheros/patches-2.6.28/100-board.patch
+++ b/target/linux/atheros/patches-2.6.28/100-board.patch
@@ -1803,7 +1803,6 @@
 +      .name = "leds-gpio",
 +      .id = -1,
 +      .dev.platform_data = (void *) &ar5312_led_data,
-+      .num_resources  = 1,
 +};
 +#endif
 +
@@ -1925,7 +1924,7 @@
 +              if (!ar231x_board.radio)
 +                      return 0;
 +
-+              if (*((u32 *) ar231x_board.radio) & AR531X_RADIO0_MASK)
++              if (*((u32 *) radio) & AR531X_RADIO0_MASK)
 +                      ar231x_add_wmac(0, AR531X_WLAN0,
 +                              AR5312_IRQ_WLAN0_INTRS);
 +
@@ -1949,7 +1948,7 @@
 +              break;
 +      }
 +
-+      if (*((u32 *) ar231x_board.radio) & AR531X_RADIO1_MASK)
++      if (*((u32 *) radio) & AR531X_RADIO1_MASK)
 +              ar231x_add_wmac(1, AR531X_WLAN1,
 +                      AR5312_IRQ_WLAN1_INTRS);
 +
@@ -1993,7 +1992,7 @@
 +      if ((result = ar231x_read_reg(AR5312_SCRATCH)))
 +              return result;
 +
-+      devid = ar231x_board.devid;
++      devid = ar231x_read_reg(AR531X_REV);
 +      devid &= AR531X_REV_MAJ;
 +      devid >>= AR531X_REV_MAJ_S;
 +      if (devid == AR531X_REV_MAJ_AR2313) {
@@ -2064,9 +2063,6 @@
 +      if (!IS_5312())
 +              return;
 +
-+      devid = ar231x_read_reg(AR531X_REV);
-+      devid &= AR531X_REV_MAJ | AR531X_REV_MIN;
-+
 +      /* Detect memory size */
 +      memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
 +      bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
@@ -2075,8 +2071,12 @@
 +              + (bank1AC ? (1 << (bank1AC+1)) : 0);
 +      memsize <<= 20;
 +      add_memory_region(0, memsize, BOOT_MEM_RAM);
-+      ar231x_gpiodev = &ar5312_gpiodev;
++
++      devid = ar231x_read_reg(AR531X_REV);
++      devid >>= AR531X_REV_WMAC_MIN_S;
++      devid &= AR531X_REV_CHIP;
 +      ar231x_board.devid = (u16) devid;
++      ar231x_gpiodev = &ar5312_gpiodev;
 +}
 +
 +void __init
@@ -2096,7 +2096,7 @@
 +
 --- /dev/null
 +++ b/arch/mips/ar231x/ar2315.c
-@@ -0,0 +1,663 @@
+@@ -0,0 +1,679 @@
 +/*
 + * This file is subject to the terms and conditions of the GNU General Public
 + * License.  See the file "COPYING" in the main directory of this archive
@@ -2142,22 +2142,24 @@
 +static inline void ar2315_gpio_irq(void)
 +{
 +      u32 pend;
-+      int bit;
++      int bit = -1;
 +
 +      /* only do one gpio interrupt at a time */
 +      pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
-+      if (!pend)
-+              return;
 +
-+      bit = fls(pend);
-+      pend ^= (1 << bit);
-+      gpiointval ^= (1 << bit);
++      if (pend) {
++              bit = fls(pend) - 1;
++              printk("GPIO IRQ: pend=0x%08x, val=%08x, bit=%d\n", pend, gpiointval, bit);
++              pend &= ~(1 << bit);
++              gpiointval ^= (1 << bit);
++              printk("AFTER IRQ: pend=0x%08x, val=%08x, bit=%d\n", pend, gpiointval, bit);
++      }
 +
-+      /* ACK the interrupt only if we handled all bits */
 +      if (!pend)
-+              ar231x_write_reg(AR2315_ISR, ar231x_read_reg(AR2315_IMR) | ~AR2315_ISR_GPIO);
++              ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
 +
-+      do_IRQ(AR531X_GPIO_IRQ_BASE + fls(pend) - 1);
++      if (bit >= 0)
++              do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
 +}
 +
 +
@@ -2203,7 +2205,6 @@
 +{
 +      u32 reg;
 +
-+
 +      reg = ar231x_read_reg(AR2315_GPIO_INT);
 +      reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
 +      reg |= gpio | AR2315_GPIO_INT_LVL(level);
@@ -2213,17 +2214,12 @@
 +static void ar2315_gpio_intr_enable(unsigned int irq)
 +{
 +      unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
-+      u32 reg;
-+
-+      gpiointmask &= ~(1 << gpio);
 +
 +      /* reconfigure GPIO line as input */
-+      reg = ar231x_read_reg(AR2315_GPIO_CR);
-+      reg &= ~(AR2315_GPIO_CR_M(gpio));
-+      reg |= AR2315_GPIO_CR_I(gpio);
-+      ar231x_write_reg(AR2315_GPIO_CR, reg);
++      ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio));
 +
 +      /* Enable interrupt with edge detection */
++      gpiointmask |= (1 << gpio);
 +      ar2315_set_gpiointmask(gpio, 3);
 +}
 +
@@ -2231,19 +2227,33 @@
 +{
 +      unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
 +
-+      gpiointmask |= (1 << gpio);
-+
 +      /* Disable interrupt */
++      gpiointmask &= ~(1 << gpio);
 +      ar2315_set_gpiointmask(gpio, 0);
 +}
 +
++static unsigned int
++ar2315_gpio_intr_startup(unsigned int irq)
++{
++      ar2315_gpio_intr_enable(irq);
++      return 0;
++}
++
++static void
++ar2315_gpio_intr_end(unsigned int irq)
++{
++      if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
++              ar2315_gpio_intr_enable(irq);
++}
++
 +static struct irq_chip ar2315_gpio_intr_controller = {
 +      .typename       = "AR2315-GPIO",
++      .startup  = ar2315_gpio_intr_startup,
++      .shutdown = ar2315_gpio_intr_disable,
++      .enable   = ar2315_gpio_intr_enable,
 +      .disable  = ar2315_gpio_intr_disable,
 +      .ack      = ar2315_gpio_intr_disable,
-+      .mask_ack = ar2315_gpio_intr_disable,
-+      .unmask   = ar2315_gpio_intr_enable,
-+      .eoi   = ar2315_gpio_intr_enable,
++      .end      = ar2315_gpio_intr_end,
 +};
 +
 +static void
@@ -2361,6 +2371,9 @@
 +{
 +      int i;
 +
++      if (!IS_2315())
++              return;
++
 +      ar231x_irq_dispatch = ar2315_irq_dispatch;
 +      gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
 +      for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
@@ -2709,6 +2722,9 @@
 +void __init
 +ar2315_time_init(void)
 +{
++      if (!IS_2315())
++              return;
++
 +      mips_hpt_frequency = ar2315_cpu_frequency() / 2;
 +}
 +
@@ -2875,13 +2891,13 @@
 +static inline u32
 +ar231x_read_reg(u32 reg)
 +{
-+      return __raw_readl((u32 *) reg);
++      return __raw_readl((u32 *) KSEG1ADDR(reg));
 +}
 +
 +static inline void
 +ar231x_write_reg(u32 reg, u32 val)
 +{
-+      __raw_writel(val, (u32 *)reg);
++      __raw_writel(val, (u32 *) KSEG1ADDR(reg));
 +}
 +
 +static inline u32