ar71xx: fix mac address calculation on the OpenMesh MR600

[openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-rb2011.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c
index ecdd7ea2e89f00a2968ffaf3b8a374b41e6dfe9d..60baae9b79b4f18ff76f60a94408559ab119eab0 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c
@@ -106,7 +106,7 @@ static struct ar8327_pad_cfg rb2011_ar8327_pad0_cfg = {
 
 static struct ar8327_platform_data rb2011_ar8327_data = {
        .pad0_cfg = &rb2011_ar8327_pad0_cfg,
-       .cpuport_cfg = {
+       .port0_cfg = {
                .force_link = 1,
                .speed = AR8327_PORT_SPEED_1000,
                .duplex = 1,
@@ -123,23 +123,6 @@ static struct mdio_board_info rb2011_mdio0_info[] = {
        },
 };
 
-static void __init rb2011_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-               AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
-       t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
-
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init rb2011_wlan_init(void)
 {
        u8 *hard_cfg = (u8 *) KSEG1ADDR(0x1f000000 + RB_HARD_CFG_OFFSET);
@@ -217,6 +200,7 @@ static void __init rb2011_nand_init(void)
        ath79_nfc_set_parts(rb2011_nand_partitions,
                            ARRAY_SIZE(rb2011_nand_partitions));
        ath79_nfc_set_select_chip(rb2011_nand_select_chip);
+       ath79_nfc_set_swap_dma(true);
        ath79_register_nfc();
 }
 
@@ -232,7 +216,8 @@ static void __init rb2011_setup(void)
        ath79_register_m25p80(&rb2011_spi_flash_data);
        rb2011_nand_init();
 
-       rb2011_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
+                                  AR934X_ETH_CFG_SW_ONLY_MODE);
 
        ath79_register_mdio(1, 0x0);
        ath79_register_mdio(0, 0x0);