ar71xx: fix link speed between AR7242 and AR8327 on the RB750GL/RB751G boards

[openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 9cd6e37efce599f0b55933c2e7f34374083683d2..5a0b950c1bf907f837503f8c58df9de5c85a2366 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -19,6 +19,7 @@
 #include <linux/etherdevice.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/clk.h>
 
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
@@ -146,6 +147,31 @@ static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
        iounmap(base);
 }
 
+static unsigned long ar934x_get_mdio_ref_clock(void)
+{
+       void __iomem *base;
+       unsigned long ret;
+       u32 t;
+
+       base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+
+       ret = 0;
+       t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
+       if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
+               ret = 100 * 1000 * 1000;
+       } else {
+               struct clk *clk;
+
+               clk = clk_get(NULL, "ref");
+               if (!IS_ERR(clk))
+                       ret = clk_get_rate(clk);
+       }
+
+       iounmap(base);
+
+       return ret;
+}
+
 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
 {
        struct platform_device *mdio_dev;
@@ -217,6 +243,13 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
+               if (id == 1) {
+                       mdio_data->builtin_switch = 1;
+                       mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
+                       mdio_data->mdio_clock = 6250000;
+               }
+               mdio_data->is_ar934x = 1;
+               break;
        case ATH79_SOC_QCA9558:
                if (id == 1)
                        mdio_data->builtin_switch = 1;
@@ -616,14 +649,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                        break;
 
                case ATH79_SOC_AR7242:
-                       switch (pdata->phy_if_mode) {
-                       case PHY_INTERFACE_MODE_RGMII:
-                               break;
-                       default:
-                               /* Other PHY modes are not tested yet. */
-                               return -EINVAL;
-                       }
-                       break;
+                       /* FIXME */
 
                case ATH79_SOC_AR9341:
                case ATH79_SOC_AR9342:
@@ -665,6 +691,30 @@ void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
        iounmap(base);
 }
 
+void __init ath79_setup_ar934x_eth_cfg(u32 mask)
+{
+       void __iomem *base;
+       u32 t;
+
+       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
+              AR934X_ETH_CFG_MII_GMAC0 |
+              AR934X_ETH_CFG_GMII_GMAC0 |
+              AR934X_ETH_CFG_SW_ONLY_MODE |
+              AR934X_ETH_CFG_SW_PHY_SWAP);
+
+       t |= mask;
+
+       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+       /* flush write */
+       __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+       iounmap(base);
+}
+
 static int ath79_eth_instance __initdata;
 void __init ath79_register_eth(unsigned int id)
 {
@@ -966,7 +1016,10 @@ void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
 {
        int t;
 
-       if (!is_valid_ether_addr(src)) {
+       if (!dst)
+               return;
+
+       if (!src || !is_valid_ether_addr(src)) {
                memset(dst, '\0', ETH_ALEN);
                return;
        }
@@ -986,7 +1039,10 @@ void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
 {
        int i;
 
-       if (!is_valid_ether_addr(src)) {
+       if (!dst)
+               return;
+
+       if (!src || !is_valid_ether_addr(src)) {
                memset(dst, '\0', ETH_ALEN);
                return;
        }