iounmap(base);
}
+static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
+ unsigned int mii_if)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
+
+ t = __raw_readl(base + reg);
+ t &= ~(MII_CTRL_IF_MASK);
+ t |= (mii_if & MII_CTRL_IF_MASK);
+ __raw_writel(t, base + reg);
+
+ iounmap(base);
+}
+
+static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
+{
+ void __iomem *base;
+ unsigned int mii_speed;
+ u32 t;
+
+ switch (speed) {
+ case SPEED_10:
+ mii_speed = MII_CTRL_SPEED_10;
+ break;
+ case SPEED_100:
+ mii_speed = MII_CTRL_SPEED_100;
+ break;
+ case SPEED_1000:
+ mii_speed = MII_CTRL_SPEED_1000;
+ break;
+ default:
+ BUG();
+ }
+
+ base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
+
+ t = __raw_readl(base + reg);
+ t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
+ t |= mii_speed << MII_CTRL_SPEED_SHIFT;
+ __raw_writel(t, base + reg);
+
+ iounmap(base);
+}
+
void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
{
struct platform_device *mdio_dev;
return pll_val;
}
-static void ar71xx_set_pll_ge0(int speed)
+static void ar71xx_set_speed_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
val, AR71XX_ETH0_PLL_SHIFT);
+ ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
}
-static void ar71xx_set_pll_ge1(int speed)
+static void ar71xx_set_speed_ge1(int speed)
{
u32 val = ar71xx_get_eth_pll(1, speed);
ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
val, AR71XX_ETH1_PLL_SHIFT);
+ ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
}
-static void ar724x_set_pll_ge0(int speed)
+static void ar724x_set_speed_ge0(int speed)
{
/* TODO */
}
-static void ar724x_set_pll_ge1(int speed)
+static void ar724x_set_speed_ge1(int speed)
{
/* TODO */
}
-static void ar7242_set_pll_ge0(int speed)
+static void ar7242_set_speed_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
void __iomem *base;
iounmap(base);
}
-static void ar91xx_set_pll_ge0(int speed)
+static void ar91xx_set_speed_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
val, AR91XX_ETH0_PLL_SHIFT);
+ ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
}
-static void ar91xx_set_pll_ge1(int speed)
+static void ar91xx_set_speed_ge1(int speed)
{
u32 val = ar71xx_get_eth_pll(1, speed);
ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
val, AR91XX_ETH1_PLL_SHIFT);
+ ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
}
-static void ar933x_set_pll_ge0(int speed)
+static void ar933x_set_speed_ge0(int speed)
{
/* TODO */
}
-static void ar933x_set_pll_ge1(int speed)
+static void ar933x_set_speed_ge1(int speed)
{
/* TODO */
}
-static void ar934x_set_pll_ge0(int speed)
+static void ar934x_set_speed_ge0(int speed)
{
/* TODO */
}
-static void ar934x_set_pll_ge1(int speed)
+static void ar934x_set_speed_ge1(int speed)
{
/* TODO */
}
.flags = IORESOURCE_MEM,
.start = AR71XX_GE0_BASE,
.end = AR71XX_GE0_BASE + 0x200 - 1,
- }, {
- .name = "mii_ctrl",
- .flags = IORESOURCE_MEM,
- .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
- .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
}, {
.name = "mac_irq",
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_MEM,
.start = AR71XX_GE1_BASE,
.end = AR71XX_GE1_BASE + 0x200 - 1,
- }, {
- .name = "mii_ctrl",
- .flags = IORESOURCE_MEM,
- .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
- .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
}, {
.name = "mac_irq",
.flags = IORESOURCE_IRQ,
pll_data->pll_1000 = pll_1000;
}
-static int ar71xx_eth_instance __initdata;
-void __init ar71xx_add_device_eth(unsigned int id)
+static int __init ar71xx_setup_phy_if_mode(unsigned int id,
+ struct ag71xx_platform_data *pdata)
{
- struct platform_device *pdev;
- struct ag71xx_platform_data *pdata;
-
- ar71xx_init_eth_pll_data(id);
+ unsigned int mii_if;
switch (id) {
case 0:
- switch (ar71xx_eth0_data.phy_if_mode) {
- case PHY_INTERFACE_MODE_MII:
- ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII;
- break;
- case PHY_INTERFACE_MODE_GMII:
- ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII;
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7130:
+ case AR71XX_SOC_AR7141:
+ case AR71XX_SOC_AR7161:
+ case AR71XX_SOC_AR9130:
+ case AR71XX_SOC_AR9132:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ mii_if = MII0_CTRL_IF_MII;
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ mii_if = MII0_CTRL_IF_GMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = MII0_CTRL_IF_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = MII0_CTRL_IF_RMII;
+ break;
+ default:
+ return -EINVAL;
+ }
+ ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL, mii_if);
break;
- case PHY_INTERFACE_MODE_RGMII:
- ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII;
+
+ case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR9330:
+ case AR71XX_SOC_AR9331:
+ pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
break;
- case PHY_INTERFACE_MODE_RMII:
- ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII;
+
+ case AR71XX_SOC_AR7242:
+ /* FIXME */
+
+ case AR71XX_SOC_AR9341:
+ case AR71XX_SOC_AR9342:
+ case AR71XX_SOC_AR9344:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RMII:
+ break;
+ default:
+ return -EINVAL;
+ }
break;
+
default:
- printk(KERN_ERR "ar71xx: invalid PHY interface mode "
- "for eth0\n");
- return;
+ BUG();
}
- pdev = &ar71xx_eth0_device;
break;
case 1:
- switch (ar71xx_eth1_data.phy_if_mode) {
- case PHY_INTERFACE_MODE_RMII:
- ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII;
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7130:
+ case AR71XX_SOC_AR7141:
+ case AR71XX_SOC_AR7161:
+ case AR71XX_SOC_AR9130:
+ case AR71XX_SOC_AR9132:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = MII1_CTRL_IF_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = MII1_CTRL_IF_RGMII;
+ break;
+ default:
+ return -EINVAL;
+ }
+ ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL, mii_if);
break;
- case PHY_INTERFACE_MODE_RGMII:
- ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII;
+
+ case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR9330:
+ case AR71XX_SOC_AR9331:
+ pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
break;
+
+ case AR71XX_SOC_AR7242:
+ /* FIXME */
+
+ case AR71XX_SOC_AR9341:
+ case AR71XX_SOC_AR9342:
+ case AR71XX_SOC_AR9344:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+
default:
- printk(KERN_ERR "ar71xx: invalid PHY interface mode "
- "for eth1\n");
- return;
+ BUG();
}
- pdev = &ar71xx_eth1_device;
break;
- default:
+ }
+
+ return 0;
+}
+
+static int ar71xx_eth_instance __initdata;
+void __init ar71xx_add_device_eth(unsigned int id)
+{
+ struct platform_device *pdev;
+ struct ag71xx_platform_data *pdata;
+ int err;
+
+ if (id > 1) {
printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
return;
}
+ ar71xx_init_eth_pll_data(id);
+
+ if (id == 0)
+ pdev = &ar71xx_eth0_device;
+ else
+ pdev = &ar71xx_eth1_device;
+
pdata = pdev->dev.platform_data;
+ err = ar71xx_setup_phy_if_mode(id, pdata);
+ if (err) {
+ printk(KERN_ERR
+ "ar71xx: invalid PHY interface mode for GE%u\n", id);
+ return;
+ }
+
switch (ar71xx_soc) {
case AR71XX_SOC_AR7130:
- pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
- : ar71xx_ddr_flush_ge0;
- pdata->set_pll = id ? ar71xx_set_pll_ge1
- : ar71xx_set_pll_ge0;
+ if (id == 0) {
+ pdata->ddr_flush = ar71xx_ddr_flush_ge0;
+ pdata->set_speed = ar71xx_set_speed_ge0;
+ } else {
+ pdata->ddr_flush = ar71xx_ddr_flush_ge1;
+ pdata->set_speed = ar71xx_set_speed_ge1;
+ }
break;
case AR71XX_SOC_AR7141:
case AR71XX_SOC_AR7161:
- pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
- : ar71xx_ddr_flush_ge0;
- pdata->set_pll = id ? ar71xx_set_pll_ge1
- : ar71xx_set_pll_ge0;
+ if (id == 0) {
+ pdata->ddr_flush = ar71xx_ddr_flush_ge0;
+ pdata->set_speed = ar71xx_set_speed_ge0;
+ } else {
+ pdata->ddr_flush = ar71xx_ddr_flush_ge1;
+ pdata->set_speed = ar71xx_set_speed_ge1;
+ }
pdata->has_gbit = 1;
break;
case AR71XX_SOC_AR7242:
- ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO |
- RESET_MODULE_GE0_PHY;
- ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO |
- RESET_MODULE_GE1_PHY;
- pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
- : ar724x_ddr_flush_ge0;
- pdata->set_pll = id ? ar724x_set_pll_ge1
- : ar7242_set_pll_ge0;
+ if (id == 0) {
+ pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
+ RESET_MODULE_GE0_PHY;
+ pdata->ddr_flush = ar724x_ddr_flush_ge0;
+ pdata->set_speed = ar7242_set_speed_ge0;
+ } else {
+ pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
+ RESET_MODULE_GE1_PHY;
+ pdata->ddr_flush = ar724x_ddr_flush_ge1;
+ pdata->set_speed = ar724x_set_speed_ge1;
+ }
pdata->has_gbit = 1;
pdata->is_ar724x = 1;
break;
case AR71XX_SOC_AR7241:
- ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
- ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
+ if (id == 0)
+ pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
+ else
+ pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
/* fall through */
case AR71XX_SOC_AR7240:
- ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY;
- ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY;
- pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
- : ar724x_ddr_flush_ge0;
- pdata->set_pll = id ? ar724x_set_pll_ge1
- : ar724x_set_pll_ge0;
+ if (id == 0) {
+ pdata->reset_bit |= RESET_MODULE_GE0_PHY;
+ pdata->ddr_flush = ar724x_ddr_flush_ge0;
+ pdata->set_speed = ar724x_set_speed_ge0;
+
+ pdata->phy_mask = BIT(4);
+ } else {
+ pdata->reset_bit |= RESET_MODULE_GE1_PHY;
+ pdata->ddr_flush = ar724x_ddr_flush_ge1;
+ pdata->set_speed = ar724x_set_speed_ge1;
+
+ pdata->speed = SPEED_1000;
+ pdata->duplex = DUPLEX_FULL;
+ pdata->has_ar7240_switch = 1;
+ }
+ pdata->has_gbit = 1;
pdata->is_ar724x = 1;
if (ar71xx_soc == AR71XX_SOC_AR7240)
pdata->is_ar7240 = 1;
break;
case AR71XX_SOC_AR9130:
- pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
- : ar91xx_ddr_flush_ge0;
- pdata->set_pll = id ? ar91xx_set_pll_ge1
- : ar91xx_set_pll_ge0;
+ if (id == 0) {
+ pdata->ddr_flush = ar91xx_ddr_flush_ge0;
+ pdata->set_speed = ar91xx_set_speed_ge0;
+ } else {
+ pdata->ddr_flush = ar91xx_ddr_flush_ge1;
+ pdata->set_speed = ar91xx_set_speed_ge1;
+ }
pdata->is_ar91xx = 1;
break;
case AR71XX_SOC_AR9132:
- pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
- : ar91xx_ddr_flush_ge0;
- pdata->set_pll = id ? ar91xx_set_pll_ge1
- : ar91xx_set_pll_ge0;
+ if (id == 0) {
+ pdata->ddr_flush = ar91xx_ddr_flush_ge0;
+ pdata->set_speed = ar91xx_set_speed_ge0;
+ } else {
+ pdata->ddr_flush = ar91xx_ddr_flush_ge1;
+ pdata->set_speed = ar91xx_set_speed_ge1;
+ }
pdata->is_ar91xx = 1;
pdata->has_gbit = 1;
break;
case AR71XX_SOC_AR9330:
case AR71XX_SOC_AR9331:
- ar71xx_eth0_data.reset_bit = AR933X_RESET_GE0_MAC |
- AR933X_RESET_GE0_MDIO;
- ar71xx_eth1_data.reset_bit = AR933X_RESET_GE1_MAC |
- AR933X_RESET_GE1_MDIO;
- pdata->ddr_flush = id ? ar933x_ddr_flush_ge1
- : ar933x_ddr_flush_ge0;
- pdata->set_pll = id ? ar933x_set_pll_ge1
- : ar933x_set_pll_ge0;
+ if (id == 0) {
+ pdata->reset_bit = AR933X_RESET_GE0_MAC |
+ AR933X_RESET_GE0_MDIO;
+ pdata->ddr_flush = ar933x_ddr_flush_ge0;
+ pdata->set_speed = ar933x_set_speed_ge0;
+
+ pdata->phy_mask = BIT(4);
+ } else {
+ pdata->reset_bit = AR933X_RESET_GE1_MAC |
+ AR933X_RESET_GE1_MDIO;
+ pdata->ddr_flush = ar933x_ddr_flush_ge1;
+ pdata->set_speed = ar933x_set_speed_ge1;
+
+ pdata->speed = SPEED_1000;
+ pdata->duplex = DUPLEX_FULL;
+ pdata->has_ar7240_switch = 1;
+ }
+
pdata->has_gbit = 1;
pdata->is_ar724x = 1;
case AR71XX_SOC_AR9341:
case AR71XX_SOC_AR9342:
case AR71XX_SOC_AR9344:
- ar71xx_eth0_data.reset_bit = AR934X_RESET_GE0_MAC |
- AR934X_RESET_GE0_MDIO;
- ar71xx_eth1_data.reset_bit = AR934X_RESET_GE1_MAC |
- AR934X_RESET_GE1_MDIO;
- pdata->ddr_flush = id ? ar934x_ddr_flush_ge1
- : ar934x_ddr_flush_ge0;
- pdata->set_pll = id ? ar934x_set_pll_ge1
- : ar934x_set_pll_ge0;
+ if (id == 0) {
+ pdata->reset_bit = AR934X_RESET_GE0_MAC |
+ AR934X_RESET_GE0_MDIO;
+ pdata->ddr_flush =ar934x_ddr_flush_ge0;
+ pdata->set_speed = ar934x_set_speed_ge0;
+ } else {
+ pdata->reset_bit = AR934X_RESET_GE1_MAC |
+ AR934X_RESET_GE1_MDIO;
+ pdata->ddr_flush = ar934x_ddr_flush_ge1;
+ pdata->set_speed = ar934x_set_speed_ge1;
+ }
+
pdata->has_gbit = 1;
pdata->is_ar724x = 1;
projects / openwrt.git / blobdiff